diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centiped.sdc b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centiped.sdc index 69dc312a..e5fef2fd 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centiped.sdc +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centiped.sdc @@ -84,8 +84,8 @@ set_input_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI #************************************************************** set_output_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[4]}] 1.000 [get_ports {AUDIO_L}] -set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[4]}] 1.000 [get_ports {AUDIO_R}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] @@ -94,7 +94,6 @@ set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|cl #************************************************************** set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] -set_clock_groups -asynchronous -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[4]}] #************************************************************** # Set False Path diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Centipede (revision 4).mra b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Centipede (revision 4).mra index 90f3d924..17517122 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Centipede (revision 4).mra +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Centipede (revision 4).mra @@ -9,12 +9,16 @@ Maze / Centipede Maze / Spiders centiped - - - - - - + + + + + + + + + + diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Centipede.mra b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Centipede.mra index 9b7a0dcc..9f8b6bf7 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Centipede.mra +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Centipede.mra @@ -9,12 +9,16 @@ Maze / Centipede Maze / Spiders centiped - + + + + + diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Millipede.mra b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Millipede.mra index 52decf04..20e0a40c 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Millipede.mra +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Millipede.mra @@ -9,11 +9,23 @@ Maze / Centipede Maze / Spiders centiped - - - - - + + + + + + + + + + + + + + + + + 1 diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede_MiST.sv b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede_MiST.sv index e4e2a64f..0b4ce793 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede_MiST.sv +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede_MiST.sv @@ -54,26 +54,24 @@ localparam CONF_STR = { wire rotate = status[2]; wire [1:0] scanlines = status[4:3]; wire blend = status[5]; -wire joyswap = status[6]; wire service = status[7]; wire milliped = core_mod[0]; -wire [15:0] dipsw; +wire [23:0] dipsw; assign dipsw[ 7:0] = status[15:8]; -assign dipsw[15:8] = 8'h01; +assign dipsw[23:8] = status[31:16]; assign LED = ~(ioctl_downl | ioctl_upl); assign AUDIO_R = AUDIO_L; -wire clk_24, clk_12, clk_100mhz; +wire clk_24, clk_12; wire pll_locked; pll pll( .inclk0(CLOCK_27), .areset(0), .c0(clk_24), - .c2(clk_12), - .c4(clk_100mhz) + .c2(clk_12) ); wire [31:0] status; @@ -91,7 +89,7 @@ wire key_strobe; wire [7:0] RGB; wire hs, vs, vb, hb; wire blankn = ~(hb | vb); -wire [3:0] audio; +wire [5:0] audio; wire ioctl_downl; wire ioctl_upl; @@ -120,7 +118,6 @@ reg reset; always @(posedge clk_12) reset <= status[0] | buttons[1] | ioctl_downl; centipede centipede( - .clk_100mhz(clk_100mhz), .clk_12mhz(clk_12), .reset(reset), .milli(milliped), @@ -128,7 +125,7 @@ centipede centipede( .trakball_i(), .joystick_i(~{m_right , m_left, m_down, m_up, m_right , m_left, m_down, m_up}), .sw1_i(dipsw[7:0]), - .sw2_i(dipsw[15:8]), + .sw2_i(dipsw[23:8]), .rgb_o(RGB), .hsync_o(hs), .vsync_o(vs), @@ -194,11 +191,11 @@ user_io( ); dac #( - .C_bits(15)) + .C_bits(12)) dac ( - .clk_i(clk_100mhz), + .clk_i(clk_12), .res_n_i(1), - .dac_i({2{audio,audio}}), + .dac_i({audio,audio}), .dac_o(AUDIO_L) ); @@ -215,7 +212,7 @@ arcade_inputs inputs ( .joystick_1 ( joystick_1 ), .rotate ( rotate ), .orientation ( 2'b01 ), - .joyswap ( joyswap ), + .joyswap ( 1'b0 ), .oneplayer ( 1'b1 ), .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ), .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ), diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/POKEY.sv b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/POKEY.sv deleted file mode 100644 index 6cbbac04..00000000 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/POKEY.sv +++ /dev/null @@ -1,505 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: M-x Butterfly -// Engineer: Peter Pearson -// -// Create Date: 10/29/2015 03:59:30 PM -// Design Name: -// Module Name: POKEY -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - - - -module POKEY - ( - input logic [7:0] Din, - output logic [7:0] Dout, - input logic [3:0] A, - input logic [7:0] P, - input logic phi2, - input logic readHighWriteLow, - input logic cs0Bar, - output logic aud, - output logic [3:0] audio, - //This clk is the 100 MHz clock, and is not a pin on the POKEY DIP - input logic clk - ); - - - logic [7:0] audf1, audf2, audf3, audf4, audc1, audc2, audc3, audc4, audCtl, allPot, skCtl; - logic [7:0] dataIn, dataOut; - logic clr; - logic baseClkWave; - logic wave15k, pulse15k, wave64k, pulse64k, wave179m, pulse179m; - logic rand4, rand5, rand17, reduce9; - logic [7:0] rngRead; - logic phi2Rising; - logic [3:0] bypassMask1, bypassMask2, bypassMask3, bypassMask4; - - //Outputs of the divide-by-N blocks for each channel - logic [3:0] divOut; - - //Base clock fed to each channel - logic [3:0] baseClks; - - //High pass filter clocks fed to each channel - logic [3:0] hpfClks; - - //Output waveform of each channel - logic [3:0] rawWave; - - assign clr = (skCtl[1:0] == 2'b00); - - -// tristateDriver #(8) triDrv(.i(dataOut), .o(D), .en(readHighWriteLow)); - assign dataIn = Din; - assign Dout = dataOut; - - - wave15kGen w15k(.clk(clk), .clr(clr), .wave(wave15k), .pulse(pulse15k)); - wave64kGen w64k(.clk(clk), .clr(clr), .wave(wave64k), .pulse(pulse64k)); - wave179mGen w179m(.clk(clk), .clr(clr), .wave(wave179m), .pulse(pulse179m)); - - polyCounter4 pc4(.clk(clk), .pulse179m(pulse179m), .rand4(rand4), .clr(clr)); - polyCounter5 pc5(.clk(clk), .pulse179m(pulse179m), .rand5(rand5), .clr(clr)); - polyCounter17 pc17(.clk(clk), .pulse179m(pulse179m), .reduce9(reduce9), .rand17(rand17), .rngVal(rngRead), .clr(clr)); - - - risingDetector risingPhi(.clk(clk), .clr(clr), .signalIn(phi2), .risingEdge(phi2Rising)); - - - audioChannelDigital channel1(.clk(clk), .clr(clr), .baseClkWave(baseClks[0]), .audf(audf1), .audc(audc1), .rand4(rand4), .rand5(rand5), .rand17(rand17), .hpfClk(hpfClks[0]), .bypassMask(bypassMask1), .rawWave(rawWave[0]), .divOut(divOut[0])); - audioChannelDigital channel2(.clk(clk), .clr(clr), .baseClkWave(baseClks[1]), .audf(audf2), .audc(audc2), .rand4(rand4), .rand5(rand5), .rand17(rand17), .hpfClk(hpfClks[1]), .bypassMask(bypassMask2), .rawWave(rawWave[1]), .divOut(divOut[1])); - audioChannelDigital channel3(.clk(clk), .clr(clr), .baseClkWave(baseClks[2]), .audf(audf3), .audc(audc3), .rand4(rand4), .rand5(rand5), .rand17(rand17), .hpfClk(hpfClks[2]), .bypassMask(bypassMask3), .rawWave(rawWave[2]), .divOut(divOut[2])); - audioChannelDigital channel4(.clk(clk), .clr(clr), .baseClkWave(baseClks[3]), .audf(audf4), .audc(audc4), .rand4(rand4), .rand5(rand5), .rand17(rand17), .hpfClk(hpfClks[3]), .bypassMask(bypassMask4), .rawWave(rawWave[3]), .divOut(divOut[3])); - - assign audio = {4{aud}}; - volumeMixer finalMix(.clk(clk), .clr(clr), .audc1(audc1), .audc2(audc2), .audc3(audc3), .audc4(audc4), .digitalWave(rawWave), .pwmWave(aud)); - - - assign hpfClks = {{divOut[2]},{divOut[3]},{2'b00}}; - - - //AUDCTL and bypass mask logic - always_comb - begin - reduce9 = audCtl[7]; - - baseClks[0] = (audCtl[6] ? wave179m : baseClkWave); - baseClks[2] = (audCtl[5] ? wave179m : baseClkWave); - baseClks[1] = (audCtl[4] ? divOut[0] : baseClkWave); - baseClks[3] = (audCtl[3] ? divOut[2] : baseClkWave); - - bypassMask1 = {{audCtl[2]},{3'b000}}; - bypassMask2 = {{audCtl[1]},{3'b000}}; - bypassMask3 = 4'h8; - bypassMask4 = 4'h8; - - baseClkWave = (audCtl[0] ? wave15k : wave64k); - end - - - always_ff@(posedge clk) - begin - if(phi2Rising & !cs0Bar) - begin - if(clr) - begin - audf1 <= 8'd0; - audf2 <= 8'd0; - audf3 <= 8'd0; - audf4 <= 8'd0; - audc1 <= 8'd0; - audc2 <= 8'd0; - audc3 <= 8'd0; - audc4 <= 8'd0; - audCtl <= 8'd0; - allPot <= 8'd0; - dataOut <= 8'd0; - if(!readHighWriteLow & (A == 4'hF)) - begin - skCtl <= dataIn; - end - end - else - begin - if(readHighWriteLow) - begin - case(A) - 4'h8: dataOut <= allPot; - 4'hA: dataOut <= rngRead; - endcase - end - else - begin - case(A) - 4'h0: audf1 <= dataIn; - 4'h1: audc1 <= dataIn; - 4'h2: audf2 <= dataIn; - 4'h3: audc2 <= dataIn; - 4'h4: audf3 <= dataIn; - 4'h5: audc3 <= dataIn; - 4'h6: audf4 <= dataIn; - 4'h7: audc4 <= dataIn; - 4'h8: audCtl <= dataIn; - 4'hB: allPot <= P; - 4'hF: skCtl <= dataIn; - endcase // case (A) - end // else: !if(readHighWriteLow) - end - end - end - - -endmodule: POKEY - -module tristateDriver - #(parameter WIDTH = 8) - ( - input logic [WIDTH-1:0] i, - output logic [WIDTH-1:0] o, - input logic en - ); - - assign o = (en) ? i : ({WIDTH{1'bz}}); - -endmodule: tristateDriver - -module volumeMixer - ( - input logic clk, clr, - input logic [7:0] audc1, audc2, audc3, audc4, - input logic [3:0] digitalWave, - output logic pwmWave - ); - - logic [5:0] volume; - logic [5:0] pwmCnt; - - assign volume = - ((digitalWave[3] | audc4[4]) ? audc4[3:0] : 0) + - ((digitalWave[2] | audc3[4]) ? audc3[3:0] : 0) + - ((digitalWave[1] | audc2[4]) ? audc2[3:0] : 0) + - ((digitalWave[0] | audc1[4]) ? audc1[3:0] : 0); - - m_counter #(6) pwmClk(.Q(pwmCnt), .D(6'd0), .clk(clk), .clr(clr), .load(1'b0), .en(1'b1), .up(1'b1)); - - assign pwmWave = (pwmCnt < volume); - -endmodule: volumeMixer - -module audioChannelDigital - ( - input logic clk, clr, - input logic baseClkWave, - input logic [7:0] audf, audc, - input logic rand4, rand5, rand17, - input logic hpfClk, - input logic [3:0] bypassMask, - output logic rawWave, divOut, noiseOut, arbDiv2Out - ); - - - logic noise; - - logic [3:0] sigIn, sigOut; - - divideByN stage1(.signalIn(sigIn[0]), .clk(clk), .clr(clr), .N(audf), .signalOut(sigOut[0])); - noiseGen rng(.rand4(rand4), .rand5(rand5), .rand17(rand17), .noise(noise), .randSel(audc[7:5])); - randomMixer randMix(.clk(clk), .clr(clr), .randomIn(noise), .signalIn(sigIn[1]), .signalOut(sigOut[1])); - arbDivBy2 adb2(.clk(clk), .clr(clr), .signalIn(sigIn[2]), .signalOut(sigOut[2])); - highPassFilter hpf(.hpfClk(hpfClk), .clk(clk), .clr(clr), .inputSignal(sigIn[3]), .outputSignal(sigOut[3])); - - - assign sigIn[0] = baseClkWave; - assign sigIn[1] = bypassMask[0] ? sigIn[0] : sigOut[0]; - assign sigIn[2] = bypassMask[1] ? sigIn[1] : sigOut[1]; - assign sigIn[3] = bypassMask[2] ? sigIn[2] : sigOut[2]; - assign rawWave = bypassMask[3] ? sigIn[3] : sigOut[3]; - assign divOut = sigOut[0]; - assign noiseOut = sigOut[1]; - assign arbDiv2Out = sigOut[2]; - -endmodule: audioChannelDigital - -module highPassFilter - ( - input logic clk, clr, - input logic hpfClk, - input logic inputSignal, - output logic outputSignal - ); - - logic ffOut; - - m_register #(1) filterReg(.Q(ffOut), .D(inputSignal), .clr(clr), .clk(clk), .en(hpfClk)); - assign outputSignal = (inputSignal ^ ffOut); - -endmodule: highPassFilter - - -module noiseGen - ( - input logic rand4, rand5, rand17, - input logic [2:0] randSel, - output logic noise - ); - - always_comb - begin - casex(randSel) - 3'b000: - begin - noise = rand5 & rand17; - end - 3'b0?1: - begin - noise = rand5; - end - 3'b010: - begin - noise = rand4 & rand5; - end - 3'b100: - begin - noise = rand17; - end - 3'b1?1: - begin - noise = 1'b1; - end - 3'b110: - begin - noise = rand4; - end - default: - begin - noise = 1'b1; - end - endcase // casex (randSel) - - end - - -endmodule: noiseGen - -module edgeDetector - ( - input logic clk, clr, - input logic signal, - output logic edgeFound - ); - - logic prevSignal; - - m_register #(1) edgeRegister(.Q(prevSignal), .D(signal), .clk(clk), .clr(clr), .en(1'b1)); - - assign edgeFound = signal ^ prevSignal; - -endmodule: edgeDetector - - -module divideByN - ( - input logic signalIn, clk, clr, - input logic [7:0] N, - output logic signalOut - ); - - logic [7:0] countOut; - logic rollover, edgeFound; - - edgeDetector edgeChecker(.clk(clk), .clr(clr), .signal(signalIn), .edgeFound(edgeFound)); - m_counter #(8) divCounter(.D(8'd0), .Q(countOut), .clk(clk), .en(edgeFound), .up(1'b1), .clr(clr), .load(rollover)); - m_register #(1) waveTracker(.Q(signalOut), .D(!signalOut), .clk(clk), .en(rollover), .clr(clr)); - - assign rollover = (countOut >= N) & edgeFound; - -endmodule: divideByN - - -module wave15kGen - ( - input logic clk, clr, - output logic wave, pulse - ); - - logic [11:0] parallel15k; - - m_counter #(12) counter15k(.D(12'd0), .Q(parallel15k), .clk(clk), .en(1'b1), .up(1'b1), .clr(clr), .load(pulse)); - m_register #(1) waveTracker(.D(!wave), .Q(wave), .clk(clk), .en(pulse), .clr(clr)); - - assign pulse = (parallel15k == 12'd3333); - -endmodule: wave15kGen - -module wave64kGen - ( - input logic clk, clr, - output logic wave, pulse - ); - - logic [9:0] parallel64k; - - m_counter #(10) counter64k(.D(10'd0), .Q(parallel64k), .clk(clk), .en(1'b1), .up(1'b1), .clr(clr), .load(pulse)); - m_register #(1) waveTracker(.D(!wave), .Q(wave), .clk(clk), .en(pulse), .clr(clr)); - - assign pulse = (parallel64k == 10'd781); - -endmodule: wave64kGen - -module wave179mGen - ( - input logic clk, clr, - output logic wave, pulse - ); - - logic [4:0] parallel179m; - - m_counter #(5) counter64k(.D(5'd0), .Q(parallel179m), .clk(clk), .en(1'b1), .up(1'b1), .clr(clr), .load(pulse)); - m_register #(1) waveTracker(.D(!wave), .Q(wave), .clk(clk), .en(pulse), .clr(clr)); - - assign pulse = (parallel179m == 5'd28); - -endmodule: wave179mGen - - -module polyCounter4 - ( - input logic clk, pulse179m, clr, - output logic rand4 - ); - - logic [3:0] regValue; - logic feedbackVal; - - m_shift_register #(4) polyShifter(.Q(regValue), .clk(clk), .en(pulse179m), .left(1'b0), .s_in(feedbackVal), .clr(clr)); - - assign feedbackVal = !(regValue[3] ^ regValue[2]); - assign rand4 = regValue[3]; - -endmodule: polyCounter4 - - -module polyCounter5 - ( - input logic clk, pulse179m, clr, - output logic rand5 - ); - - logic [4:0] regValue; - logic feedbackVal; - - m_shift_register #(5) polyShifter(.Q(regValue), .clk(clk), .en(pulse179m), .left(1'b1), .s_in(feedbackVal), .clr(clr)); - - assign feedbackVal = !(regValue[4] ^ regValue[2]); - assign rand5 = regValue[4]; - -endmodule: polyCounter5 - - -module polyCounter17 - ( - input logic clk, pulse179m, clr, - input logic reduce9, - output logic rand17, - output logic [7:0] rngVal - ); - - logic [16:0] regValue; - logic feedbackVal; - - m_shift_register #(9) polyShifterUpper(.Q(regValue[16:8]), .clk(clk), .en(pulse179m), .left(1'b1), .s_in(reduce9 ? feedbackVal : regValue[7]), .clr(clr)); - m_shift_register #(8) polyShifterLower(.Q(regValue[7:0]), .clk(clk), .en(pulse179m), .left(1'b1), .s_in(feedbackVal), .clr(clr)); - - assign feedbackVal = !(regValue[16] ^ regValue[11]); - assign rand17 = regValue[16]; - assign rngVal = regValue[16:9]; - -endmodule: polyCounter17 - -module volumeControl - ( - input logic clk, clr, - input logic signalIn, - input logic [3:0] volume, - input logic dcVolume, - output logic signalOut - ); - - logic [3:0] pwmCount; - logic pwmOn; - - m_counter #(4) pwmTimer(.Q(pwmCount), .D(4'h0), .clk(clk), .clr(clr), .load(1'b0), .en(1'b1), .up(1'b1)); - - assign pwmOn = (pwmCount <= volume); - - assign signalOut = dcVolume ? pwmOn : (pwmOn & signalIn); - - -endmodule: volumeControl - -module risingDetector - ( - input logic clk, clr, - input logic signalIn, - output logic risingEdge - ); - - logic prevSignal; - - m_register #(1) risingRegister(.Q(prevSignal), .D(signalIn), .en(1'b1), .clk(clk), .clr(clr)); - assign risingEdge = signalIn & ~prevSignal; - -endmodule: risingDetector - -module randomMixer - ( - input logic clk, clr, - input logic signalIn, - input logic randomIn, - output logic signalOut - ); - - logic risingEdge; - - logic waveWideRandom; - - //This instance name made sense at 4AM when I typed it - risingDetector rayfall(.clk(clk), .clr(clr), .signalIn(signalIn), .risingEdge(risingEdge)); - - m_register #(1) randomCapture(.Q(waveWideRandom), .D(randomIn), .en(risingEdge), .clk(clk), .clr(clr)); - - assign signalOut = signalIn & waveWideRandom; - -endmodule: randomMixer - -module arbDivBy2 - ( - input logic clk, clr, - input logic signalIn, - output logic signalOut - ); - - logic risingEdge; - - risingDetector risingCheck(.clk(clk), .clr(clr), .signalIn(signalIn), .risingEdge(risingEdge)); - - m_register #(1) waveTracker(.Q(signalOut), .D(~signalOut), .en(risingEdge), .clk(clk), .clr(clr)); - -endmodule: arbDivBy2 - - - diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/centipede.v b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/centipede.v index 67f79219..90e3cdd8 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/centipede.v +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/centipede.v @@ -21,23 +21,22 @@ // - Added Millipede module centipede( - input clk_100mhz, input clk_12mhz, input reset, input milli, - input [9:0] playerinput_i, - input [7:0] trakball_i, - input [7:0] joystick_i, - input [7:0] sw1_i, - input [7:0] sw2_i, - output [4:1] led_o, - output [8:0] rgb_o, + input [9:0] playerinput_i, + input [7:0] trakball_i, + input [7:0] joystick_i, + input [7:0] sw1_i, + input [15:0] sw2_i, + output [4:1] led_o, + output [8:0] rgb_o, output sync_o, output hsync_o, output vsync_o, output hblank_o, output vblank_o, - output [3:0] audio_o, + output [5:0] audio_o, input [14:0] dl_addr, input [7:0] dl_data, @@ -183,7 +182,7 @@ module centipede( wire coloram_w_n; reg coloren; - wire [3:0] audio; + wire [5:0] audio; // wire mob_n; wire blank_clk; @@ -197,6 +196,7 @@ module centipede( wire flip; wire cntrlsel; + wire tben; wire coin_ctr_r_drive, coin_ctr_c_drive, coin_ctr_l_drive; wire [7:0] playerin_out; @@ -584,10 +584,10 @@ module centipede( hs_ram( .clk_a_i(s_12mhz), .clk_b_i(s_12mhz), - .we_i(hs_ctrl[1] & ~hs_ctrl[2]), + .we_i(hs_ctrl[1]), .addr_a_i(hs_addr), .data_a_o(hs_out), - .data_a_i(hs_data), + .data_a_i(hs_ctrl[2] ? 8'd0 : hs_data), .addr_b_i(hsram_addr), .data_b_o(hsram_dout), .data_b_i(hsram_din), @@ -620,7 +620,7 @@ module centipede( // Option Input Circuitry assign switch_out = ab[0] ? - sw2_i : + sw2_i[7:0] : sw1_i; // Player Input Circuitry @@ -642,11 +642,11 @@ module centipede( wire [7:0] playerin_out1; assign playerin_out1 = milli ? - { dir2, 1'b0, start2, fire2, sw1_i[7:4] } : + { dir2, 1'b0, start2, fire2, tben ? 4'd0 : sw1_i[7:4] } : { coin_r, coin_c, coin_l, slam, fire2, fire1, start2, start1 }; assign playerin_out0 = milli ? - { dir1, vblank, start1, fire1, sw1_i[3:0] } : + { dir1, vblank, start1, fire1, tben ? 4'd0 : sw1_i[3:0] } : { dir1, vblank, self_test, cocktail, tra }; assign playerin_out = ab[0] ? playerin_out1 : playerin_out0; @@ -657,12 +657,13 @@ module centipede( always @(posedge s_12mhz) if (reset) cc_latch <= 0; - else if (s_6mhz_en) + else /*if (s_6mhz_en)*/ if (~out0_n) cc_latch[ ab[2:0] ] <= db_out[7]; assign flip = milli ? cc_latch[6] : cc_latch[7]; - assign cntrlsel = milli ? cc_latch[6] : 1'b0; + assign cntrlsel = milli ? cc_latch[7] : 1'b0; + assign tben = milli ? cc_latch[5] : 1'b0; assign led_o[4] = milli ? 1'b0 : cc_latch[6]; assign led_o[3] = milli ? 1'b0 : cc_latch[5]; assign led_o[2] = cc_latch[4]; @@ -1120,35 +1121,42 @@ module centipede( assign vblank_o = vblankd; // Audio output circuitry - - wire [3:0] pokey_audio; + wire [3:0] pokey_ch0, pokey_ch1, pokey_ch2, pokey_ch3; POKEY POKEY( - .Din(db_out[7:0]), - .Dout(pokey_out), - .A(ab[3:0]), - .P(8'b0), - .phi2(phi2), - .readHighWriteLow(rw_n), - .cs0Bar(pokey_n), - .audio(pokey_audio), - .clk(clk_100mhz) + .RESET_N(~reset), + .CLK(s_12mhz), + .ENABLE_179(phi0_en), + .DATA_IN(db_out[7:0]), + .DATA_OUT(pokey_out), + .ADDR(ab[3:0]), + .WR_EN(~(pokey_n | rw_n)), + .POT_IN(milli ? ~sw2_i[7:0] : 8'd0), + .CHANNEL_0_OUT(pokey_ch0), + .CHANNEL_1_OUT(pokey_ch1), + .CHANNEL_2_OUT(pokey_ch2), + .CHANNEL_3_OUT(pokey_ch3) ); + wire [5:0] pokey_audio = pokey_ch0 + pokey_ch1 + pokey_ch2 + pokey_ch3; + wire [3:0] pokey2_ch0, pokey2_ch1, pokey2_ch2, pokey2_ch3; POKEY POKEY2( - .Din(db_out[7:0]), - .Dout(pokey2_out), - .A(ab[3:0]), - .P(8'b0), - .phi2(phi2), - .readHighWriteLow(rw_n), - .cs0Bar(pokey2_n), - .audio(pokey2_audio), - .clk(clk_100mhz) + .RESET_N(~reset), + .CLK(s_12mhz), + .ENABLE_179(phi0_en), + .DATA_IN(db_out[7:0]), + .DATA_OUT(pokey2_out), + .ADDR(ab[3:0]), + .WR_EN(~(pokey2_n | rw_n)), + .POT_IN(milli ? ~sw2_i[15:8] : 8'd0), + .CHANNEL_0_OUT(pokey2_ch0), + .CHANNEL_1_OUT(pokey2_ch1), + .CHANNEL_2_OUT(pokey2_ch2), + .CHANNEL_3_OUT(pokey2_ch3) ); - wire [3:0] pokey2_audio; - wire [4:0] pokey_mux = pokey_audio + pokey2_audio; + wire [5:0] pokey2_audio = pokey2_ch0 + pokey2_ch1 + pokey2_ch2 + pokey2_ch3; + wire [6:0] pokey_mux = pokey_audio + pokey2_audio; - assign audio = milli ? (pokey_mux[4] ? 4'hf : pokey_mux[3:0]) : pokey_audio; + assign audio = milli ? (pokey_mux[6] ? 6'h3f : pokey_mux[5:0]) : pokey_audio; endmodule diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/matoro.sv b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/matoro.sv deleted file mode 100644 index c647dc1f..00000000 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/matoro.sv +++ /dev/null @@ -1,129 +0,0 @@ -`timescale 1ns / 1ps -module m_range_check - #(parameter WIDTH = 6) - (input logic [WIDTH-1:0] val, low, high, - output logic is_between); - - logic smallEnough, largeEnough; - - m_comparator #(WIDTH) lc(,,largeEnough, low, val); - m_comparator #(WIDTH) hc(,,smallEnough, val, high); - - assign is_between = ~smallEnough & ~largeEnough; - -endmodule: m_range_check - -module m_offset_check - #(parameter WIDTH = 6) - (input logic [WIDTH-1:0] val, low, delta, - output logic is_between); - - logic [WIDTH-1:0] high; - - m_adder #(WIDTH) add(high,, low, delta, 1'b0); - m_range_check #(WIDTH) rc(.*); - -endmodule: m_offset_check - -module m_comparator - #(parameter WIDTH = 6) - (output logic AltB, AeqB, AgtB, - input logic [WIDTH-1:0] A, B); - - assign AltB = (A < B); - assign AeqB = (A == B); - assign AgtB = (A > B); - -endmodule: m_comparator - -module m_adder - #(parameter WIDTH = 6) - (output logic [WIDTH-1:0] Sum, - output logic Cout, - input logic [WIDTH-1:0] A, B, - input logic Cin); - - assign {Cout, Sum} = A + B + Cin; - -endmodule: m_adder - -module m_mux - #(parameter WIDTH = 6) - (output logic Y, - input logic [WIDTH-1:0] I, - input logic [$clog2(WIDTH)-1:0] Sel); - - assign Y = I[Sel]; - -endmodule: m_mux - -module m_mux2to1 - #(parameter WIDTH = 6) - (output logic [WIDTH-1:0] Y, - input logic [WIDTH-1:0] I0, I1, - input logic Sel); - - assign Y = (Sel ? I1 : I0); - -endmodule: m_mux2to1 - -module m_decoder - #(parameter WIDTH = 6) - (output logic [(1 << WIDTH)-1:0] D, - input logic [WIDTH-1:0] I, - input logic en); - - assign D = en << I; - -endmodule: m_decoder - -module m_register - #(parameter WIDTH = 6) - (output logic [WIDTH-1:0] Q, - input logic [WIDTH-1:0] D, - input logic clr, en, clk); - - always_ff @(posedge clk) - if(clr) - Q <= 0; - else if(en) - Q <= D; - -endmodule: m_register - -module m_counter - #(parameter WIDTH = 6) - (output logic [WIDTH-1:0] Q, - input logic [WIDTH-1:0] D, - input logic clk, clr, load, en, up); - - always_ff @(posedge clk) begin - if(clr) - Q <= 0; - else if(load) - Q <= D; - else if(en) - Q <= (up ? Q + 1 : Q - 1); - end -endmodule: m_counter - -module m_shift_register - #(parameter WIDTH = 6) - (output logic [WIDTH-1:0] Q, - input logic clk, en, left, s_in, clr); - - always_ff @(posedge clk) - if (clr) begin - Q <= 'd0; - end - else if(en) begin - if(left) begin - Q <= (Q << 1); - Q[0] <= s_in; - end - else begin - Q <= (Q >> 1); - Q[WIDTH-1] <= s_in; - end - end -endmodule: m_shift_register diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/pll.vhd b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/pll.vhd index 7a70df8d..7c5889ee 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/pll.vhd +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/pll.vhd @@ -14,7 +14,7 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition -- ************************************************************ @@ -45,8 +45,7 @@ ENTITY pll IS areset : IN STD_LOGIC := '0'; inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c4 : OUT STD_LOGIC + c2 : OUT STD_LOGIC ); END pll; @@ -57,10 +56,9 @@ ARCHITECTURE SYN OF pll IS SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); @@ -75,10 +73,6 @@ ARCHITECTURE SYN OF pll IS clk2_duty_cycle : NATURAL; clk2_multiply_by : NATURAL; clk2_phase_shift : STRING; - clk4_divide_by : NATURAL; - clk4_duty_cycle : NATURAL; - clk4_multiply_by : NATURAL; - clk4_phase_shift : STRING; compensate_clock : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; @@ -137,16 +131,14 @@ ARCHITECTURE SYN OF pll IS END COMPONENT; BEGIN - sub_wire6_bv(0 DOWNTO 0) <= "0"; - sub_wire6 <= To_stdlogicvector(sub_wire6_bv); - sub_wire3 <= sub_wire0(4); + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); sub_wire2 <= sub_wire0(2); sub_wire1 <= sub_wire0(0); c0 <= sub_wire1; c2 <= sub_wire2; - c4 <= sub_wire3; - sub_wire4 <= inclk0; - sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; altpll_component : altpll GENERIC MAP ( @@ -159,10 +151,6 @@ BEGIN clk2_duty_cycle => 50, clk2_multiply_by => 4, clk2_phase_shift => "0", - clk4_divide_by => 13, - clk4_duty_cycle => 50, - clk4_multiply_by => 48, - clk4_phase_shift => "0", compensate_clock => "CLK0", inclk0_input_frequency => 37037, intended_device_family => "Cyclone III", @@ -199,7 +187,7 @@ BEGIN port_clk1 => "PORT_UNUSED", port_clk2 => "PORT_USED", port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_USED", + port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", port_clkena1 => "PORT_UNUSED", @@ -215,7 +203,7 @@ BEGIN ) PORT MAP ( areset => areset, - inclk => sub_wire5, + inclk => sub_wire4, clk => sub_wire0 ); @@ -244,13 +232,10 @@ END SYN; -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "13" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "99.692307" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -272,33 +257,25 @@ END SYN; -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" -- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "48" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "99.70000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz" -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -322,16 +299,13 @@ END SYN; -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1" -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_CLK0 STRING "1" -- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK4 STRING "1" -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0" -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -344,10 +318,6 @@ END SYN; -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "13" --- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "48" --- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -383,7 +353,7 @@ END SYN; -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" @@ -401,14 +371,12 @@ END SYN; -- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE