diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/Snapshot/System1_MiST.rbf b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/Snapshot/System1_MiST.rbf
index 98991188..da5addc2 100644
Binary files a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/Snapshot/System1_MiST.rbf and b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/Snapshot/System1_MiST.rbf differ
diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1_MiST.qsf b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1_MiST.qsf
index b61b832f..5cf25f04 100644
--- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1_MiST.qsf
+++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1_MiST.qsf
@@ -18,14 +18,14 @@
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 06:24:46 May 16, 2020
+# Date created = 21:33:05 May 17, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
-# Flicky_MiST_assignment_defaults.qdf
+# System1_MiST_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@@ -43,6 +43,23 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/System1_MiST.sv
+set_global_assignment -name VERILOG_FILE rtl/System1_Top.v
+set_global_assignment -name VERILOG_FILE rtl/System1_Main.v
+set_global_assignment -name VERILOG_FILE rtl/System1_Video.v
+set_global_assignment -name VERILOG_FILE rtl/System1_Sound.v
+set_global_assignment -name VERILOG_FILE rtl/System1_Sprite.v
+set_global_assignment -name VERILOG_FILE rtl/System1_Parts.v
+set_global_assignment -name VERILOG_FILE rtl/System1_hvgen.v
+set_global_assignment -name VERILOG_FILE rtl/SN76496.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name VERILOG_FILE rtl/pll_mist.v
+set_global_assignment -name VERILOG_FILE rtl/z80ip.v
+set_global_assignment -name VERILOG_FILE rtl/DPRAM1024_11B.v
+set_global_assignment -name VHDL_FILE rtl/rom/dec_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/clut.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
# Pin & Location Assignments
# ==========================
@@ -168,77 +185,58 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-# -------------------------
-# start ENTITY(Flicky_MiST)
+# --------------------------
+# start ENTITY(System1_MiST)
# Pin & Location Assignments
# ==========================
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+ set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+ set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
# Fitter Assignments
# ==================
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
+ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
+ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
+ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
+ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
-# end ENTITY(Flicky_MiST)
-# -----------------------
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/System1_MiST.sv
-set_global_assignment -name VERILOG_FILE rtl/System1_Top.v
-set_global_assignment -name VERILOG_FILE rtl/System1_Main.v
-set_global_assignment -name VERILOG_FILE rtl/System1_Video.v
-set_global_assignment -name VERILOG_FILE rtl/System1_Sound.v
-set_global_assignment -name VERILOG_FILE rtl/System1_Sprite.v
-set_global_assignment -name VERILOG_FILE rtl/System1_Parts.v
-set_global_assignment -name VERILOG_FILE rtl/System1_hvgen.v
-set_global_assignment -name VERILOG_FILE rtl/SN76496.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
-set_global_assignment -name VERILOG_FILE rtl/pll_mist.v
-set_global_assignment -name VERILOG_FILE rtl/z80ip.v
-set_global_assignment -name VERILOG_FILE rtl/DPRAM1024_1B.v
-set_global_assignment -name VERILOG_FILE rtl/DPRAM1024_11B.v
-set_global_assignment -name VHDL_FILE rtl/rom/dec_rom.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/clut.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/spr_rom.vhd
-set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+# end ENTITY(System1_MiST)
+# ------------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Flicky.mra b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Flicky.mra
index ec3834d4..c0e311e5 100644
--- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Flicky.mra
+++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Flicky.mra
@@ -11,13 +11,13 @@
0
-
-
+ FF
+ FF
diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/MyHero.mra b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/MyHero.mra
new file mode 100644
index 00000000..55309cb9
--- /dev/null
+++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/MyHero.mra
@@ -0,0 +1,34 @@
+
+ MyHero
+ 0216
+ 202001010000
+ 1985
+ Sega
+´ System1_MiST
+ Action
+ myhero
+
+ 5
+
+
+
+ FF
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ FF
+
+
\ No newline at end of file
diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Pitfall2.mra b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Pitfall2.mra
index 679c7973..f3101ef9 100644
--- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Pitfall2.mra
+++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Pitfall2.mra
@@ -18,6 +18,7 @@
+ FF
diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Regulus.mra b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Regulus.mra
index 40bada9b..b386b60b 100644
--- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Regulus.mra
+++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Regulus.mra
@@ -22,6 +22,7 @@
+ FF
diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/SegaNinja.mra b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/SegaNinja.mra
new file mode 100644
index 00000000..3b9bb3dc
--- /dev/null
+++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/SegaNinja.mra
@@ -0,0 +1,34 @@
+
+ SegaNinja
+ 0216
+ 202001010000
+ 1985
+ Sega
+´ System1_MiST
+ Action
+ seganinja
+
+ 6
+
+
+
+ FF
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ FF
+
+
\ No newline at end of file
diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Starjacker.mra b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Starjacker.mra
index 2b98d1ba..825f118e 100644
--- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Starjacker.mra
+++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Starjacker.mra
@@ -22,6 +22,7 @@
+ FF
diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/UpNDown.mra b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/UpNDown.mra
index 549f33aa..691adeef 100644
--- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/UpNDown.mra
+++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/UpNDown.mra
@@ -22,6 +22,7 @@
+ FF
diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/memorymap.txt b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/memorymap.txt
index 0d719009..62f2ecd8 100644
--- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/memorymap.txt
+++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/memorymap.txt
@@ -1,15 +1,15 @@
#Flicky
prog epr-5978a.116 + epr-5979a.109 + epr-5978a.116 + epr-5979a.109 64k
sound epr-5869.120 8k
- sprite epr-5855.117 + epr-5856.110 32k
+ sprite epr-5855.117 + epr-5856.110 64k
tiles epr-5868.62 + epr-5867.61 + epr-5866.64 + epr-5865.63 + epr-5864.66 + epr-5863.65 48k
color pr-5317.76 256b
- prot dec_flicky.bin 128b needs to be added manually mra tool ignore it- todo
+ prot dec_flicky.bin 128b
-#PITLALL2
+#PITFALL2
prog epr-6623.116 + epr6624a.109 + epr-6625.96 + epr-6625.96 64k
sound epr-6462.120 8k
- sprite epr6454a.117 + epr-6455.05 32k
+ sprite epr6454a.117 + epr-6455.05 64k
tiles epr6474a.62 + epr6473a.61 + epr6472a.64 + epr6471a.63 + epr6470a.66 + epr6469a.65 48k
color pr-5317.76 256b
prot 0x80 x $FF 128b
diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/DPRAM1024_11B.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/DPRAM1024_11B.v
index 37ec49d1..89034869 100644
--- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/DPRAM1024_11B.v
+++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/DPRAM1024_11B.v
@@ -14,23 +14,23 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
-// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
-//Copyright (C) 2017 Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
-//to the terms and conditions of the Intel Program License
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel FPGA IP License Agreement, or other applicable license
-//agreement, including, without limitation, that your use is for
-//the sole purpose of programming logic devices manufactured by
-//Intel and sold by Intel or its authorized distributors. Please
-//refer to the applicable agreement for further details.
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
// synopsys translate_off
@@ -74,14 +74,14 @@ module DPRAM1024_11B (
wire [15:0] q_b = sub_wire1[15:0];
altsyncram altsyncram_component (
- .address_a (address_a),
- .address_b (address_b),
.clock0 (clock_a),
- .clock1 (clock_b),
- .data_a (data_a),
- .data_b (data_b),
.wren_a (wren_a),
+ .address_b (address_b),
+ .clock1 (clock_b),
+ .data_b (data_b),
.wren_b (wren_b),
+ .address_a (address_a),
+ .data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
@@ -126,3 +126,119 @@ module DPRAM1024_11B (
endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "5"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
+// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
+// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
+// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
+// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
+// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
+// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
+// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
+// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
+// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
+// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_11B.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_11B.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_11B.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_11B.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_11B_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_11B_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/DPRAM1024_1B.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/DPRAM1024_1B.v
deleted file mode 100644
index 32434cef..00000000
--- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/DPRAM1024_1B.v
+++ /dev/null
@@ -1,128 +0,0 @@
-// megafunction wizard: %RAM: 2-PORT%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altsyncram
-
-// ============================================================
-// File Name: DPRAM1024_1B.v
-// Megafunction Name(s):
-// altsyncram
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2017 Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Intel Program License
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel FPGA IP License Agreement, or other applicable license
-//agreement, including, without limitation, that your use is for
-//the sole purpose of programming logic devices manufactured by
-//Intel and sold by Intel or its authorized distributors. Please
-//refer to the applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module DPRAM1024_1B (
- address_a,
- address_b,
- clock_a,
- clock_b,
- data_a,
- data_b,
- wren_a,
- wren_b,
- q_a,
- q_b);
-
- input [9:0] address_a;
- input [9:0] address_b;
- input clock_a;
- input clock_b;
- input [0:0] data_a;
- input [0:0] data_b;
- input wren_a;
- input wren_b;
- output [0:0] q_a;
- output [0:0] q_b;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
- tri1 clock_a;
- tri0 wren_a;
- tri0 wren_b;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
- wire [0:0] sub_wire0;
- wire [0:0] sub_wire1;
- wire [0:0] q_a = sub_wire0[0:0];
- wire [0:0] q_b = sub_wire1[0:0];
-
- altsyncram altsyncram_component (
- .address_a (address_a),
- .address_b (address_b),
- .clock0 (clock_a),
- .clock1 (clock_b),
- .data_a (data_a),
- .data_b (data_b),
- .wren_a (wren_a),
- .wren_b (wren_b),
- .q_a (sub_wire0),
- .q_b (sub_wire1),
- .aclr0 (1'b0),
- .aclr1 (1'b0),
- .addressstall_a (1'b0),
- .addressstall_b (1'b0),
- .byteena_a (1'b1),
- .byteena_b (1'b1),
- .clocken0 (1'b1),
- .clocken1 (1'b1),
- .clocken2 (1'b1),
- .clocken3 (1'b1),
- .eccstatus (),
- .rden_a (1'b1),
- .rden_b (1'b1));
- defparam
- altsyncram_component.address_reg_b = "CLOCK1",
- altsyncram_component.clock_enable_input_a = "BYPASS",
- altsyncram_component.clock_enable_input_b = "BYPASS",
- altsyncram_component.clock_enable_output_a = "BYPASS",
- altsyncram_component.clock_enable_output_b = "BYPASS",
- altsyncram_component.indata_reg_b = "CLOCK1",
- altsyncram_component.intended_device_family = "Cyclone III",
- altsyncram_component.lpm_type = "altsyncram",
- altsyncram_component.numwords_a = 1024,
- altsyncram_component.numwords_b = 1024,
- altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
- altsyncram_component.outdata_aclr_a = "NONE",
- altsyncram_component.outdata_aclr_b = "NONE",
- altsyncram_component.outdata_reg_a = "CLOCK0",
- altsyncram_component.outdata_reg_b = "CLOCK1",
- altsyncram_component.power_up_uninitialized = "FALSE",
- altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
- altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
- altsyncram_component.widthad_a = 10,
- altsyncram_component.widthad_b = 10,
- altsyncram_component.width_a = 1,
- altsyncram_component.width_b = 1,
- altsyncram_component.width_byteena_a = 1,
- altsyncram_component.width_byteena_b = 1,
- altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
-
-
-endmodule
diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Main.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Main.v
index 81ef93c6..95e36a79 100644
--- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Main.v
+++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Main.v
@@ -133,7 +133,7 @@ wire [7:0] dectbl;
wire [7:0] mdec = ( mdat & andv ) | ( dectbl ^ xorv );
//DLROM #( 7,8) decrom( clk, decidx, dectbl, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16: 7]==10'b1_1110_0001_0) ); // $1E100-$1E17F
-dec_rom dec_rom(
+dec_rom dec_rom(//only 32k are encrypted todo
.clk(clk),
.addr(decidx),
.data(dectbl)
diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_MiST.sv b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_MiST.sv
index 4995205e..b3b47c2f 100644
--- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_MiST.sv
+++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_MiST.sv
@@ -37,7 +37,7 @@ localparam CONF_STR = {
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blend,Off,On;",
"O6,Service,Off,On;",
- "O7,Crypt,Off,On;",
+ "O7,Crypt,On,OFF;",
"O89,Lives,3,4,5,Infinite;",
"OAB,Extend,30k/80k/160k,30k/100k/200k,40k/120k/240k,40k/140k/280k;",
"OC,Difficulty,Easy,Hard;",
@@ -90,7 +90,7 @@ always @(*) begin
// crypt = 1'b0;
end
- 7'h2: // STARJACKER - PPI no Sound todo
+ 7'h2: // STARJACKER no Sound todo
begin
INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireA,m_fireB,1'b0};
INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2A,m_fire2B,1'b0};
@@ -120,6 +120,27 @@ always @(*) begin
// crypt = 1'b0;
end
+ 7'h5: // My Hero - PIO
+ begin
+ INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireA,2'b0};
+ INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2A,2'b0};
+ INP2 = ~{2'd0,m_two_players, m_one_player,dsService,2'b0, m_coin1};
+ DSW0 = 8'hFF;
+ DSW1 = {dsDifclt,dsExtend,dsLives,2'b00};//Continue, Difficulty
+
+// crypt = 1'b0;
+ end
+ 7'h6: // Sega Ninja - PIO
+ begin
+ INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireA,2'b0};
+ INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2A,2'b0};
+ INP2 = ~{2'd0,m_two_players, m_one_player,dsService,2'b0, m_coin1};
+ DSW0 = 8'hFF;
+ DSW1 = {dsDifclt,dsExtend,dsLives,2'b00};//Continue, Difficulty
+
+// crypt = 1'b0;
+//Check graphic
+ end
default: ;
endcase
end
@@ -180,7 +201,7 @@ wire [2:0] g, r;
wire [1:0] b;
wire [15:0] rom_addr;
wire [15:0] rom_do;
-wire [14:0] spr_rom_addr;
+wire [15:0] spr_rom_addr;
wire [15:0] spr_rom_do;
wire [12:0] snd_rom_addr;
wire [15:0] snd_rom_do;
@@ -206,7 +227,7 @@ data_io data_io(
reg port1_req, port2_req;
-wire [24:0] tl_ioctl_addr = ioctl_addr - 17'h1A000;
+wire [24:0] tl_ioctl_addr = ioctl_addr - 18'h22000;
sdram sdram(
.*,
.init_n ( pll_locked ),
@@ -225,7 +246,7 @@ sdram sdram(
.cpu1_q ( rom_do ),
.cpu2_addr ( ioctl_downl ? 16'hffff : (16'h8000 + snd_rom_addr[12:1]) ),
.cpu2_q ( snd_rom_do ),
- .cpu3_addr ( ioctl_downl ? 16'hffff : (17'h10000 + spr_rom_addr[14:1]) ),
+ .cpu3_addr ( ioctl_downl ? 16'hffff : (17'h10000 + spr_rom_addr[15:1]) ),
.cpu3_q ( spr_rom_do ),
// port2 for sprite graphics
@@ -284,7 +305,7 @@ System1_Top System1_Top(
.cpu_rom_do( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
.snd_rom_addr(snd_rom_addr),
.snd_rom_do(snd_rom_addr[0] ? snd_rom_do[15:8] : snd_rom_do[7:0] ),
- .spr_rom_addr(spr_rom_addr),//Internal for now
+ .spr_rom_addr(spr_rom_addr),
.spr_rom_do(spr_rom_addr[0] ? spr_rom_do[15:8] : spr_rom_do[7:0] ),
.tile_rom_addr(tile_rom_addr),
.tile_rom_do(tile_rom_do),
diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Top.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Top.v
index 98ad123c..9d77cfd3 100644
--- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Top.v
+++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Top.v
@@ -25,7 +25,7 @@ module System1_Top
output [15:0] SOUT, // Sound Out (PCM)
output [15:0] cpu_rom_addr,
input [7:0] cpu_rom_do,
- output [14:0] spr_rom_addr,
+ output [15:0] spr_rom_addr,
input [7:0] spr_rom_do,
output [12:0] snd_rom_addr,
input [7:0] snd_rom_do,
diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Video.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Video.v
index 66d74f49..7452a913 100644
--- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Video.v
+++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Video.v
@@ -21,7 +21,7 @@ module System1_Video
input [7:0] cpu_dw,
output cpu_rd,
output [7:0] cpu_dr,
- output [14:0] spr_rom_addr,
+ output [15:0] spr_rom_addr,
input [7:0] spr_rom_do,
output [13:0] tile_rom_addr,
input [23:0] tile_rom_do
@@ -79,7 +79,7 @@ VIDHVGEN hv(
// Sprite Engine
wire [10:0] SPRPX;
-wire [14:0] sprchad;
+wire [15:0] sprchad;
wire [7:0] sprchdt;
//DLROM #(15,8) sprchr(VCLKx8,sprchad,sprchdt, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2'b0_1)); // $08000-$0FFFF
//spr_rom spr_rom(