From b362c4d3f80d260b11d1d9444a51af2f0b1a6a25 Mon Sep 17 00:00:00 2001 From: Marcel Date: Sun, 9 Jun 2019 21:56:13 +0200 Subject: [PATCH] New Core : Jin --- .../Jin/Jin_MiST.qpf | 31 + .../Jin/Jin_MiST.qsf | 203 + .../Jin/Jin_MiST.sdc | 137 + .../Jin/ReadMe.txt | 8 + .../Jin/Release/JIN.ROM | Bin 0 -> 16384 bytes .../Jin/Release/Jin_MiST.rbf | Bin 0 -> 256409 bytes .../Jin/clean.bat | 15 + .../Jin/rtl/Jin_MiST.sv | 244 + .../Jin/rtl/YM2149.sv | 329 + .../Jin/rtl/build_id.tcl | 35 + .../Jin/rtl/cpu09l_128.vhd | 5906 +++++++++++++++++ .../Jin/rtl/cpu68.vhd | 3963 +++++++++++ .../Jin/rtl/dac.vhd | 48 + .../Jin/rtl/data_io.v | 115 + .../Jin/rtl/defender.vhd | 780 +++ .../Jin/rtl/defender_cmos_ram.vhd | 163 + .../Jin/rtl/defender_decoder_2.vhd | 54 + .../Jin/rtl/defender_decoder_3.vhd | 54 + .../Jin/rtl/defender_prog.vhd | 1686 +++++ .../Jin/rtl/defender_sound.vhd | 150 + .../Jin/rtl/defender_sound_board.vhd | 186 + .../Jin/rtl/gen_ram.vhd | 84 + .../Jin/rtl/pia6821.vhd | 553 ++ .../Jin/rtl/pll_mist.ppf | 14 + .../Jin/rtl/pll_mist.qip | 4 + .../Jin/rtl/pll_mist.vhd | 461 ++ .../Jin/rtl/sdram.sv | 254 + 27 files changed, 15477 insertions(+) create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.qpf create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.qsf create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.sdc create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/ReadMe.txt create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Release/JIN.ROM create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Release/Jin_MiST.rbf create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/clean.bat create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/Jin_MiST.sv create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/YM2149.sv create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/build_id.tcl create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/cpu09l_128.vhd create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/cpu68.vhd create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/dac.vhd create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/data_io.v create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender.vhd create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_cmos_ram.vhd create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_decoder_2.vhd create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_decoder_3.vhd create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_prog.vhd create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_sound.vhd create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_sound_board.vhd create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/gen_ram.vhd create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pia6821.vhd create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.ppf create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.qip create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.vhd create mode 100644 Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/sdram.sv diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.qpf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.qpf new file mode 100644 index 00000000..a47cf603 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Jin_MiST" diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.qsf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.qsf new file mode 100644 index 00000000..47e84678 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.qsf @@ -0,0 +1,203 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 18:04:04 June 09, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Defender_MiST_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:22:13 JUNE 04, 2019" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Jin_MiST.sv +set_global_assignment -name VHDL_FILE rtl/defender.vhd +set_global_assignment -name VHDL_FILE rtl/defender_sound_board.vhd +set_global_assignment -name VHDL_FILE rtl/defender_sound.vhd +set_global_assignment -name VHDL_FILE rtl/defender_decoder_3.vhd +set_global_assignment -name VHDL_FILE rtl/defender_decoder_2.vhd +set_global_assignment -name VHDL_FILE rtl/defender_cmos_ram.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv +set_global_assignment -name VHDL_FILE rtl/pia6821.vhd +set_global_assignment -name VHDL_FILE rtl/cpu68.vhd +set_global_assignment -name VHDL_FILE rtl/cpu09l_128.vhd +set_global_assignment -name QIP_FILE rtl/pll_mist.qip +set_global_assignment -name VERILOG_FILE rtl/data_io.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Jin_MiST +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------------- +# start ENTITY(Defender_MiST) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Defender_MiST) +# ------------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.sdc b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.sdc new file mode 100644 index 00000000..fca44902 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.sdc @@ -0,0 +1,137 @@ +## Generated SDC file "vectrex_MiST.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +## DATE "Sun Jun 24 12:53:00 2018" + +## +## DEVICE "EP3C25E144C8" +## + +# Clock constraints + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +# tsu/th constraints + +# tco constraints + +# tpd constraints + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +#************************************************************** +# Create Generated Clock +#************************************************************** + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] + +set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]] +set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]] + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 1.000 [get_ports {AUDIO_L}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 1.000 [get_ports {AUDIO_R}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] + +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_CLK}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_CLK}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 + +set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 2 +set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/ReadMe.txt b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/ReadMe.txt new file mode 100644 index 00000000..955f72a4 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/ReadMe.txt @@ -0,0 +1,8 @@ +Williams Jin + +Port to MiST + +JIN.ROM is required at the root of the SD-Card. + +I dont know how its should work need feedback. + diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Release/JIN.ROM b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Release/JIN.ROM new file mode 100644 index 0000000000000000000000000000000000000000..632beeff7ddb5a05783a0f084f178849b59bf63a GIT binary patch literal 16384 zcmdUWd3=*qy6}15>}k@I7AO=PlD0HKoVkWof+&jxk&D0w=pfh6VZ7>{>nF-^9mVBB zU}|Pql3S6<3s@84Ks(o~sB={uombL@3`?56c)}pmgny_hNd=cbN?UHsafxNWB^o$E~!-n@38X!k# zty9j>>s#e~>+5nh(e%1$B9u&!o8%VL7?zpXC)d?-${S2Ff!DWgO=8ZMc-FCS`>tJ2 zLY}vE*RJOvH%!Zul#qAs+O>=EeI4?hkO!TvJ@t@32XzLwcGvDb>mf&oNe!PenVU=# z^YWlNk$sTo0sf=y772I(=m7@jmJA8TidN&x4C9QwB}Wpz+X zf*eY6s^ob-&T7C{hKD*+Oqx4$E`xwv$?_q+8NIcvzJ0rkji6MpXE)RTDd4vRa;H;r zIw6k_(j^AoK%g!uqcWY)MAO6&)Pt7smLTM=?YrJBh5Y&_F)^-xTa$8b+OqfH!7ZC$ z9D{445}jk#nCZYkbMt%h_nY7B-!HShj)&+iU$X0#Mtb|!&1MaE11Tup9&ZT7SszU# zB2C_04mzVu;^gk_X_NFcov>!VikUxd_TEhji$> zl}EDuuWKEK8kT9eWw0>B<*(0gPvNg?y$K3r;{L*X{WVhEL=!51%lIHz5Ynv#ZmJJS z5WT4tX4#B23I!~l!PUb`3WWxnH{Svn{hQ=rz#von79!WHL-N4RB+>Yvm;E}HT$18Z z5*)(6rSH#<8p8>a+siaWZzy*L>q#^kk4w^RWrOB;JQ^kSLFW)gGXGoUVOTH%-(hky z)xp{z@kpetZFooCRH^%J&y9rsB0iM~+ywTw;mZX69()S={9X7o()#z|)5zb6KZwpW zfoZz&yNU4aDnqDp{{H}fNcHRd2PH~sF<7~2$=y;J1Yw!nLk1f#e1pZrEhslH=0Tt# zd^AL0xLroCzy11Wl!pP6Y|zaV0K2xW4bX=y_IHFCW;lco6o}lINLUR;E^Ir9T%IQaP`l+0L0Xpxk{zLSc>f=z)t3EwkKL_pA z&>lfZ6RB?xfXz9uYD^{TgmOZo-Eq`R? zBD8YVycMe~^B-BYYS~gW8CjMunfKU&6=>PgC66J?vK1CIWvFc>vcQKXKe8N6f#0fS zkT1F}EYzkA^Kz={QV4<)%U97a=SIaFCG*H#X7Jvi^-1(s!x0^3!~ z^5#8eTWMMJ&<|EVux!Nww0y~ec`FxK9$WUv3d=)FA6oU$yd_CW^OD(ol!{P+gd&n; zl;|nSoua&vCQebwh;zhm0I|ibtmaR3{;TGg1Vg&<#KUdWt5DNCHrRGjcqD zMl=$lQUXg7raYz!7;sos1X?kLm75?`B8VqQLBOZcN)nMMrX0Y+4#0@RNFp3hphHHd z1aSmO7*WD;(18t!1WwRX5)TYySrkSZKSk*&#GOJ3pb1itltjWPApkN;aU-yx9B`G1 zgI0-CAZL0ak(!|O5?3JcsZzW^l2Vx*sGcfPX}q3NP#9R(BZUqn>XD@5P%6jQrvjRU zh>QaQ5Q=n3+LRVB*%gFAQw*SKAVWfOCMXOs@Btj71Rga793$noQK^7ZC*s?Y1PBEj za>78TC!~5A!6|VdJ(hr*R3K3&MRk;KqKO3KgX$6QMv_xTtA}A33u~7RlRTiiyp}2uRcNUaQKgou5K(bN#S@i+sFXydA}TdeX^2WoMglnsbBJgH z(KwL9PAELd8_8{7gXcwZLh<3o#Ali;-8=|d4^EAfen1T!_ zXuksYD@jyI`;@p(MS4}VM@_rcv`a%fHMmntI<%B%G0~BB9c|O$Ha%(8<8h1}N7+~? zNJ4=VN)lJ%xQfKobU;JpkSY9eW{q$QG$B=k6uf)fUk zFp_vGj$;xxkysjzrQ_HL5*tYdM&W@BGBBF-kHP(!xPL5(j>FMAaP)g5I-c~Iai0bE zWs$yYVv{*x#KU64H_kQHVyeSbk7){_211R5rVqJ88jI05jPAhbdl-$! z$c&K%qb!WFG0MSc0!FzQSuwKVo7Cl$gi{etO*jqaw3yRjPLKH%0vB@LNcdF3W6YZ{ zpN9E#tQbKQBZ*=ZQDk7nXsj566`5E$mMF&&&FwlndmK8pCvEFq*db;gjZsPiYU}rsUb=& zR_TaJkJTweZNM5M(WGM78(I_Ar4d~^){h|ikvL@(Ny)&5(ZnzY8#9SY5qjCSFj`=VzziWULsX5Z22KJ*b%^Q_O+nNE#|Z)p4CetgA)1D0I-(-k>nZT+9RVRo#jx}+rjT3DQ>ta+tKvM>&p`RN2i7|>(qZCI8?!%@& zn$}0sdU1NMJW|ZMz=4y%e1h|vY-$_$C z+)8i@HnkA2E%GS_CtLz^al*wgKS20?tcVgtA6E7fWe-+$6IB;h zcM^36))1m;$J#ccZN<74qPvFm%|zdXQ?8PfE7;IT3=J4;3nR)7umnMIf?^mAV6LBV zQOxyWzL)Slgzv_D7glrD& zCtMrmS~1sxxoenjCVUg&uM++W;TtjEfceXq{}wAQ5yeHKs3(d#tf<9`2v*c!Wi?S= zAYfZ=+C^w5p&f*Rv)oQ-8=raH1P0x^SWsCpt)ikVHF4w2^o#j*xX~jJ) zr287~ZYEt#xa%tEyn;I$Nk@Zx8V?eca3VqC2^^1;SRBV-MSlOtnv4IB$u4>eMOIWct zvY0DY6sw9gMQXtw;@;qFd`M9>IWJ!kzH+1}Buts4%-<~hA*Ary-_Y8)$E&7>)Nhyo zNMCjLL-6G*%-h0O$^dd&_{tv|k5+YsW_s;+@gYZFS==?-mshM=CY*9%OPUHS7&NbHl@Ri@W?g=S80c3ZX4waZb+_J{n=TZtev)jei^CEo(kH=^6QLzn) zZ9fy+egle#tsO3t5QJZ@@0^W)KHr#Y?G@X8r4L%KiDabMz6iR?U1Nk?kFX+K{hZjA z>Jjen&Jo-97|+?1zH>50i@w}iEw+E^xxXNM0nk(J+td@o7vc>1;ev3rH`%n>J4I{{ zd;T}H6b`jah88^9l_g}jw2aAjX)8t>N85B*ug|d7Y-)bPHAm1}xwVlC#N4;EY zIul7|uf%$bl5u7Vivy=T-k1H0{fk6N?O)-4)W6)n%Eb$N#O~2z*Z0MaVzCnnJH_T# zeE{TJ;a~21)W1sXJ}7p+DRwBu?pm=gU_3HOA;!M)?s;RbO__hh!f&4|?C}-&KX*+O zzVz-|vSo~wTPA!Vc0Yb2P2V|KjclGaHIMZukloA{XTL*~_IQpf{IHS5KeUT61=PjT zyO{t(@M0L*0ryo>+Nu+5EjcXh)4fJhBes|XJAf0wVK4zx?Gc3 zc84e(6H9knek+#!vqd46{cZ^C{pa&xpZL!)UO{vt(XFTJK@4E~8);TYv2hT%6ci0G%eAPVSrxRinkm>n+ACNVAODkY*bvKsv#g3u&&=3aQn2 z)^=x+(!4Dn3#ZG2RcFpAyuOFlSmQgmxBY_8;5V9W3dZ)-;Zx{d;~ZNZ1AfC|9S!#G z3~Ww5w{pjxOkobp;aOL@#ps>0V=t?6tSU=f(HxJQvlRc?iSo@gfx&ZW+XC%d7QTwROv35AZ`v;E!(~Q9{?dM9A-RY3ICC%$%YoEiVg@!OfjC;&cq0|cL zRcS3Hw$W9la?C`Ve6aWcfKQw2R!yI4X>b(nx21+pA*Uszy>IGCx5Coq@TLhPyy?Qo zqTr7fP2f)umf*9dEBQA>iNyc#XCRos; zU=?OqOyTMcTR2-sxOyX;Pnj9OJg-hxaKvJ=K%68f>IHbOui)!$Sl6)ESu|F#j>@&)hu)R9%tEp-&&RheNVBh z-uDy84kF)k4v~B-l5P(<_O| z_{!B)V;twkgh_nrH;%~NkyVkGA|Ej0tP;saI3LLKKt&{9h@Jn-;on~r6!!V{x0Kj- z6zwn0pE^&!&q{`MSUjx5QYM+jw}NGJeUGwit#1v>oW3Vmw%_+8%YwdVSXS?Q7BbM` z`5_%TgzGwdCF{_!u;by5RUQA-@npxpcC7DsIVobtY!I>|_G^WZ`^EhZzh2gCZAfXS-MI`L1Jn!_=Yx`+ zjzNC^!}y&646&n5?0m`L+YN$S!ku%xd-FFhntIMrbGjx`b0w0&ntecen!~tvQkvNL z4={`j#?$F8atV7`t6uDU5G40`{kvH;UF`fvAPiPm>&g(!U`2Bs98&NumGHLMxnJx` z)xSNd*Wu~>!sO`;g*(6YzP)JjXNSB+=fa(}jCEjr;HALpfvtgG20RDt2iG1fI2b%g ziY$Q_1Fr_00asvWU{~#~+CSEfuUlVtwEph;gBQnN+g`P5bC^dZuwwa*B-Pg~ni6-=+k+l*&e&bU?XQSONj&%~Gg8~hvnoBa9y?SAm?94^kngNyew;Wc54 z@C(5$yd`|;a3SHvCBmyq1m_aLwM5vtMA)@N_`>1a=-=RdRd~_+n(#BUz@O~-0<^4j~!0#Wv_6 zuOr+YW+hmD;iBb5+bCBYgcPwnbkPChm(5{^n|oUrMo{WE{7`(Z2qFP-pr74 za*@fOQFOq{oA;PJJ#WJD{@{QEp&t1EL%nzQJ`U*)go@_9`LQ)^UAaxUZoXB=W-Y|s zAvwl!j-m&kr*GW?=qb0h+qsYe+Kcj_@zT2a(DGK%Q02&@EFLWy=p3+(ZVKBla{*7!SY? z008SszX461ByRF$TsZ*r8z%HHCWIkh1C$|}b%BM96O+SoW{~4aMm)rDN*K=X0sK19 zpFtKM$*dtJ_bd%@7li}L&H=Glzv7TQL`vb_Tq=okl7M(oT) z*{M*|J9hpG<+4Q!MEvhM21TChJ)M_3J1_U&@^Zh(n=nOQ$kz$Y2SN|tMCid`Li2%; znGs@JeU zF&Er~$;p@xGEBx3X2WEot_n5hUYBbdB0SFu{H-8|btG5^wEH6)zQIZ>Hud$wh~!p< zI5*t#De`{xUVd@Di`#cZI0ACjo=^MvSIDNj2rA4NS$EzsW8^fG$rEc_-Ez>r!|$y- zKivdCfpQx*p0TAc5SLRpGH4puhEGa0se)6xtC&6o{hHG_2o++26<>em8%UzZ?;U0N%QJPJK?Yx-_0n%Q(8R*MvMy8brRVWonT5M&kdjM!H09xfhi@!as8krU#?X`12 zYngCX*dx3z>=iy;BHSkwhOexFAQ9Y##P-j{){k5II4;~q~I=*-9W8lWnDM|;DVt6LDxh&w=i}8>s zm5b7UvnY&fiqH?|Y1Cl~5^S;8&n}#9zhrOrUb?bIX@I95b?UTtX4sqUm%Pnao)u%g z;_+2tVu_gWiHSSK_&R)~_B_NjLg>SiD?zq`ti7;yAk4|akMMK>2^3svunauhIF1R& z@d?K3KdXgaTW(!1f z&V94SY8Ix0FF3_};%!H!;P9T@J2O+5=|X$&$rSE!f8UZR%z&=hnZj)7x;Im}7rJI; z3bWkfnEdSK;tj)ivg-@nJmAuCk6Y{Tq_I-+W&*d5+VfNA9V%zu83_MzalWi|V`(^% zS9BE4ll5>K7assK2u8gK@?Q)MNa1h6U51PI;2_jk)k%Cix6>PeE~G$e4k?juE8Kxb z2^mFO!5^!!>XW%mrx?Z7eD+m`omXVsWnsH&C+sn;Z1`%dr;HhsRQ6v!Ww|8V+ZvWK zTUl>u^nMmfgP8*R9ZC~2VSM;1b46ylne&hKGDhI|88hy>a|^QO0*mTwEQ_2e&kGpn zx|-2t95Vgo9m==re2dr?;C)N{zlC9_;1pmm z(<+o4*hqba8axV{qC%mbrffWV8jhIhO7k8IKV6C8W<5N7)A$<(&=9oph7uUQYtwlc z)Zzo)l5@dTc@Q3O3MEy+8z5m{bQnu)N_~l?3EWBWF*$(+UK}po((5Vuu^gdj-va;g z9WH|>V}!pqbgUSn#xZ|4gKu@Gdi}lv@mMyCQ+7Y@kVBBUJnW<|93f6TR_I$C4&3Mc z#=H&gdcLLM!2JqolD4sYjcv&q+e7|QH3eq=%~9FfC0l-#%PqF37jMbT=9ZW_d5%5? z7cI+dGV`Z1vbB$wROfPQEb28SBeJ>2Z-fB%m_rF>^6z<2<*f)E>< z)*K8zO|~BHTzlm^*Cn_gym+YGOv!{N|$UIVapM|^s&&H7G|YH zKIuP)O~B;RF}ak5Wx0pkI+-Ig1HLlWHHCHkAj#M@QtY0QSm9p<&jzbuLLP@HS?hn&{}fEePyEmNpM$B`?e`}AOEFmJ3BD#fsGgwkLB4MT zOm@i&9^qSWA((s{?|sKU2EvZ=l9+CiCCOxLZ+L}pxOMKS$tMSg{2T#GZ|F(Fx5mHP z_k{m(-;@5ezGwVT`JVOv#P_`aIUwOkzEuE9(xNRbTw(h`;iI-Y3)k3k3!kuM6+UVE zUg0yg%))1FqY9t5r4@RudRXk8#=Uo`aA(qsk{>r_=N}RF7_+T2y>|=QF68Sj-sHvSyB~C` z-Ambl;h8)9Mq~06Bj2TPtzp`Fh~i9N4-O5x$U1$O!;$kA2!j^w_cdC&hQS~Jh^-HhIc_w|erymIL7aZupK%Gk@9AM^@&po@|%D<*QagBwe8|bg;0bM++D1^5ZU* zd$xNu#MDh5Lye`jglj;?mHnc+vAD|%$Z0l0s!bf>rz8BB+G4um~1jW zI|_`~G?NR)&SM`MpXp%8U~^cAH*DU<;={tp)$moFU{jp|t_$;7z;$6h3m8P^v^b!Z zIXTeEoE$KnmaAZ38G_buzq~rshWq68ahIp7fwe0<-KG!nJ({(yRAID#ly6i8S}vc0 zzENz~>qlFg9iGe)u76MVhK@6TfC2Ok16*;q{{dpuLC?E0{H4Cq@Vibhxg{+nreAN# zR_7YPh;;c%?W4g$*BgQkcb4UA=1c)tNKpj=bQS_<>Xq49{JX^33X32x%Tfoc=>>04 z*yYj|1Z__XB|v_vE~G0;zEV`sHv0~MZn5haC3R7d3DsX=QOMH6+bcZPde$EcR~Nu( z;I?|4zw|Gzmx@Q-+YoUIE;01`+fjjs4}-xy`A<;+ zEGEm~J9aSnBnU(0z&qi_r!eevz#HK>_Q>l!Z5siB{?S`_@V8xyw^*#a>qih%bNLp- zm^r+zC0o{7+g(|fYjE7-v&pLvJL88%a{H#$ir zN|!Aei^9i_w1mLC$N@;3(wt?{_&?Y8-^Dr3`MuwOy9Emt9Ic}A#nbrku|L9p3K%f& z**zfim;d4}T~%~CZ{Fq}=NK%cFSe?^{dsxddRbLa5c(bAW5ta}&-x#)`qH7%z@O~Q z`R)gQSHk{x7+h@Rzwm)S>e@U<{)->Q&EGT=n1c*o+!%wn6TCDR@j|R6UpP~BS|5XZ zw3D0Y)T*8QopNE~a$e4u0IUwdXihAID755JTlH z3q@$#|A8=A$m;zVU~F;?qkt{uE3H>Crbr(>Si55 z8jv62R`-H%FsR9D9vf69CmU4C*rwUX!)VCLtL@{5b>yz=I1~g^gY211dGc%owDxj zrmPb+l?^qL;smV9tZ!<{KB>vND5o{7y$qrGPrdMOmIWI&Se89+vCOhenE&IaEGwV> z=NDhtFk$7>&p~0r!he14Y0HYcmrZD>JRX@fzb-UyN~nhWqNegpqy&ChsdbxXpu@p3 zU2|ourgCKDe9yAVf=I`4$#_iCACq*)B<(TDa(q^5-Qm&&kxF%QBX_J)*DQ@FogZO2 zlkLOfQ&Q{h=Z??P1JIL^qm?<4lB1P|=8~hcjCF_0adXKlS%x}k^Ra1?<<#^|hmXA? zX-i*;Og}E^gEP?aSAgx;1(BZACn^_3I(p|WdqvWfE{ddDpgPM?*QhD=Mvhm$&l(KP zsoF9~a-fUpW2nnYsr%}b3|jWPNU9OqQ}tzwB6?}UF~w1)N=exn1~(<8ZqfsFOLH33 z=x76|+DI>!NX8Q-wUVAC+R}{LjfYRPM^p?}UstxiR@z)@O}1@P-BtFVwUVmzo?5^? z9{CW6m32fUQ|Y4GhAbnf?tS@US$jkpQ~IOYi?dSdK-;grz8INac_31@v{o8b`hRLG zKaN~1yBLwuON(lcLZ#$l!%<+ky*6j53W#owTr4TuSlhsc@I*%h2zWsXz|YdxO)uSB z3+!@URvv9wCPQwL6dOy$T8V?f|J{Z5$i?-kMo_v^9Vz4LDn~U#`pWDR^|iB4sGDK9 zVAc+wc(Vzn3p!>g5TscO^wZ@v}^6!3N<%+Ebq*mkLNt+`8v;Y&S>@6W5`^=&iB9jACLX#cOL!TcfKc}>bqBb_}Ga4kFT|Wc_4e${Tdt}2MP&fd#7b5auvQo zAbZV@vGhJ2D=iOzDv*}zs^@+|c(RbXKB!Vioe@69WSj{ zAK^*MkN2A5>-CzBleQNfg471n@|CXL+N(T;r8rcsvZdDrU>%@q9#9+6q^m$>OChdl zf2uxhn_jz>Wy>|Lc#@W-81*dp8gM$Ga?uo*E*`7XcxsoHr`K#*dat?^R3;ETqD%Lx z3ld1%=^6o3Kw6hxRW8tTdQIz=wikYZ>^g<)7^34eKyCH|!gC4G0G{T)mU4pc~>Lo|@ zSJ~$PqYQj#&S|^!n(`rAm(>~3mX4|MQb_3%zfxOPJK;SHsO){f4Zyv?Ujr%^Xsr0I z{i(9A0=lXcG%dIa7)c;Yi|$pd>mLCc%L7E4`g|5p`8xpB>G|&x(0vMNnXdl;WS?tG z;ASA^c&rcUy=V}mHl%VrYZ9`#Qvub94n1pZT?M+|nLu0;m!-6*Y6%&&5+Hp{$Jg~Q zfY$&TH(M^61u7S44DneyA`pM{EILwK(Y?yDkn$z1)7(l1nc6PvBpGv`*vi&cL&Pat1_W=CS-?;CFy6fXdZgW#WfG{LuAJ0r5_}Qkm>T zvAghDYJ3aq1psV5~-Rr97Zv$zW%Kr(FehHtFV6}N2@QMV4UpkwP zr>kg9Y1FgU{VYwY({l>)`>9V+nee86 zf4UcFJrX~ChV)+a3({xNA^kVR@gbc}?LpVJ)powq=EuW;bUy{r zlp&+zt>h{Y9cm!jg-2zgPrT2LxRfU8X|_JSPiaVFD)CkND7nYpGyasX(;B!DNaJ{w z$v5u+)+Zo-yb+LHs(cm@ExHP}1G=X4i7v&DDIMak?o)e_nxytCN<^39p)`I@G|&gUH=vMCh$LjF95P1LCOcwE8m}vFMOgyyvRaYmhwh?7i9UR_(L*z zFCh8oS)ek-Kq^nKDw9s=s`6B?L`Mp;0j-z1O7@~Br9)+U7QY0#PeIS4fUctPD4?-a zuQH9P80S@h>J>-*7@#u6Xeljfr*i3BmL}Py#+QtAm0Wd|Of-gcNuc`_^!(NYG^U>A zGgPE_Pkj0h;Maja1ky6mApWRaIwuf4vWMpZ+4xK}iVpcVT~nVS8D;5ExyDcFkiU8x zAfKVKuLF7({3Re7=5%YP`g&{b>v3jpa!y57r9buXG!{=0x;p_CWWCE3DVfb>jqPi;e2 zf$Su{Ykx|YW;SmifNPZeG1@R-j*Hv=+5g?^2EmMvr(A;(XO+dOP{Zg6yg~|oG zS6K=wlUxL%M{`vCoaWiON+yD|?CHQcKwLUBBzay5s7xT4>sdZaakN19F9+hM_%rn- zx=KzOKMNX1W2Su9HKjpU>5m{S(;WT^Fok@G4n2Pf&{d%OBTGO&PxJ{?mB!8~Ez-p- z4f3agv`oB||BOp>Iq^d{WgjXRXk3+LL1ihZJf@)iDVt6Ghpy>(ORw5nksr^NYivQM zGL@&}>b@Vy;#<34mR);Q2B2jt`AQx~N0i+U<)KIcU}wd<+T<37utsOZpW^$9DHmr1jx+)+M@MtA1< zj4WzW2=d&87DdIveBOzL6qMCZok#W;=)Av}FI!gCx60NX*Q&!}K!2$QNjK1_DU5iz zGc%7zKKt~NV_6q#z|GONgC3ZyVH#9J>sbq4u2y|t)uP2@!!NwgrnI8*eUFdHf;F!O z)@b?6T;P7b?B8Ct9Oo+UN2}JEUe0>ob`U#n-Ct>JxXrfqFI4i+%3Hy#@4b&PCJW6E zzZE1SIcwfb*7ZOf#FWu*N;NIea8)(dRK+UQY|^JX&ksf;d23`U537nUpa1fws$U&A zhF(-7h6pWx*+2&(NxUP3NB&}6$BN@A>}cl4gNQz1bH}dZ?AoE*F}T*D^|6bNF-z2; zBOH)qIz#iGuXe65rBXU6+hUkUH9JG|Yqxiol0XR?^Kg$S?n&B zHMsHCr3=bDvr8blxI1lg5QucYCQmjfO* z3(ar*ZT2y}H}O^a(DU_()`C@nF5Y9L%jAzeYV-EJ-5Mk&G@lC=6W>u$5+uzrzZ<&# z%R3oC|5)N4U6`gy<2bBQ0v5Zx2z@4~SyZlv`|e-rik3C$xj?in^xXQ`4TIcy?|tgA zoAgn846gNoC29Ht66b$8VaI2Poyd0Y`?FOItxjIbj?b%h;+g%;I0z@E_M&>;@*^$R z6N8t;?$N<}*=6z4P}csx)KJ>A(n@eKc2-u+wd z3d?1EZun$l@915j_sM6!m4He5w-ZZvSso2DqsUk^O_+cJ8=kDukPIbv=c{^ zVEAE;7PdBER(d42@$oK7443{J?)sy`>B*>WKj3hb$Q#XKXe>v z)N(YY2V-BIQmO3Sc|*=y;p-@s7&-uWy2su`OGm^|UY9nYmztny>(Yw`luqR4StN$8dEmrh+ zv)UY6CFSR<9M*odvPTiNnys=dkL6)nWA=3OMB4K1i6K2STKm;X)Oqz(@ClT~pWrre z$L^2shPM`t$072z)_%2e?N=*%aJ7q?JYhD87R~xZ9@aS4FZb3sw#Kne99ZQ5zS9uL zSN4BAVdgY$?-}}i=g0je6KmDp?$+U2^Ig-&C(};7R#DDD?lt{y({-ZBl&vCRkH@bs zcZ``&u<-E>x#8*w($}&3+B+t<`_EXtz3x>%%Ia!hy;sC9F4#ZwVDDYJw+zfq^_>?! z?k|cT-zNVL<2MO*XLh%mlf${js<4R011IN~$*g_-z#=L2^l&n#Jgc|MxVF*VlQJx7 zw6@WW|6Mf|Tzj>2KTbQ{!L6TMd&OiGzs+Q|{rK@kpNrgN@(_E=PBq6- zc5(!M9SC0|tOHYyS+vHnW3p#?rF-Ofz7TRb9#e8MN4H%_K91s(RmYC&jliz+U(H#% zd(SvIzb>bEbjRIrpzHhCtF{S#Qh#%IR~_iHVr{Rx_xQSF%f~n9Mw%T*J;6fvj^78g+#q_J#F`d;MiK&or=5X>&a@BYhicKB1{{ag@o@x>lj|wgTc-Ld2#SKyX?Jj zb-zV4oyG}YQR!9N@wT2QuXgME^On6Ojm~rkZu@L{rI+ioM;~;6{QA`(vg44=E5CkK z_)Y#4&a+Ez4qwA{<1dyz|J=L6S6ugY^Cxt6UH5kLH+0rNxKn>bXIK4?^=;l<%wN&D z`_XqKe?>>vXP0h_|E$i&M@#1K===~Oi7wWclRwO#)`@2mUHnMni>qg9J%7u$)M+Jn z=*OPEf2B4(*PCBdU$J#BWbsPfd$z8KX@v&uuf1qq`TZ5z_ECMZh5{$!drC1|pD-L- ztzW#f*1qAp4}&yKpD;SsFJrp4hhwXzully|Rb59|B-Y~dwfMZN@^-91qaW80`f)|R z7N6f0{$MhN|JwMR6siw6a+CQhJbm;yM$>Nbd4D9u13dKd)jM?Pyy-em!g?HV^+)o@ z(W`Tp&V+StyJG2Dgt8)wmNZyxj;&g_vlgB&k<^Nht1Qa@g58uAr$_^4xoSFgQvU%S zc04=2wsPFNni*21+fCG3suX)Bgf6z9aZ$~*5u4?B-5 z@~f2Jb{u*6D=hsb3c=C$j;?K>XU+p2=Ky`ti{ zT}CbI80**kVDqjA`kKly8?TPhC*i@3hr0d^i6ECHV`S0O;$WiHZpY$At@7iz`2k4t zIH;n_8e#qNZM8WzV#3*esp!!D3H2+{9p--=MXN2#Roj_b^}lv{@=}(`?2bc%nJ)S} ztgKsWn`Uc&$s?l`z1-pk6!4trCR69FtLECK+1gvDy=bAeXwxk25fqm7To$!2YY`VT zKeuUqwL%MP`PVU2yA0by@zr1N8l^Aq-G0M#d7Vn$^VglrkEgW1T%>sHU9>CTzFc<4 zLzMb-jZ+q9HNBy4e(3p~8?Gv{&O;o#v_JkI8&_AB9lKlSS_oSU(>t@KTj|Lx%ab=4 zK6xoy3)9#B;9fUdKSuc~yMeVZ-Ev1^_aT;#tkf#_m5i78XQsFJdz*DOOd-lv7modD{TL} zs%k}66iyZWLKsy?3L|bIDtd(}o4B?5-*;FI$KLq)g~9>5>~FjG=HTvf)NI%{ zQwK*kopQKQZ#v;6rv{_;m!k)NpzZE-?ztWE9@4N^o>#c}k}dY-yZ@pQeDJ!;ZH;Yz zakJ-+LaVbW@18w%;eK~>c~hbO*)v8z;4}u^&u+0Nz7p+R7|xwhDbL;hZqI%7?&{Tz zdcL%I=fuv^TNWC**DTbXOYUj-KVskT9DC?1(bV9%2PewWOU|V6CA+K5#?Yqx;i-wz zgU?#1+6UjYul(hZ)|I;MMx%7#@{POwZG*wxAHI03@ecda(dvO{!F|gE)xweT z85h`l!+Yx1rRT2qz7h>KKYDRDf%RYBUK;#%XTt22GQM`>_Fa%~KK9)9;|bh(>f3yF zhc8t*-fa4PZ|O`|#lJ?JA@UfARMmXNudUFckLtE= z^wFtHQ)Pmy6<4qQxyCL`K1T5>%W~Bc@lN|~$C$+Vs>iB{`-yXKi%2^klFXx8%MzP@ny!7d$J!ywVsF*uspqfu=+b{t zF-u#g~ZEZXNKlalnUzSynug%=z|3go(ee%QB4hZf@SETK zv>0OBa6-r+kSEZ);*||*rsWyz%+MM(Xxw5h2$?~|+=R~-OOg@HP%-VQY99QW>H|BZ zt$?mMaly7kv+Ym}i^QFzn){gCfUyEQnFp1Iay1g|e7^9{_)NN~I0n(pob@5Fz4&52 zgFMATYiLbbqJjk8Je1xs|5#0sU0TL9E^8H}qfpSolA=|k=Kc+uykRRh3B(L&^)2RH zBTUtzPLd4-LMs}GxOnnBBo#|EmY>IHUh{9a8DU9sAV+AH8*2*Bh)DP{AT3A${>E%& zxRkGk>|&mgg53LGA$$qFkk=-ic}iHB0w^(9K#dYxMJKOoDk}{cSJSQ;JuGAfhmq0} zZYI>33(aAIp%}{a1o#ph_sOGaam(eChP^Rn(`>1f&|ud!WBIZUnT-KMr1|iC!*0u9 z7WQKP59eB9lJ(gjaF;VRMwEOS7Sc7gY^E*InYy?Jiz_~I|D#}!trt37F>?{b`kVAp zKjfCqH(>~spn}$l*kXpU9y>FP5v4p`LM+CX4ihBKfjOJ*VrtCVn9Q^tJF}HH>LKk4 zYFV#7TW!)C!?c;QnXo4%0CX`TLwnP98tlIH1sD5*r$XlH-aOHUf<*01om~u#)03wy zI*t?NJzrWTvnVo}jKZfR$a~!3_QVma#ft|o<|{{k^NV1F&Bg&Skc}ISy;@9CIv1pE zZiNRc@I1p;^Q1vweG#wCJfta1g2@^7OFCZjoSy=7^21oU)=z8R$&E2qdHnW|?4{$6 zX(l=vRIHP{WiOPjd)tRz)bz`Qyxe?5ii&N2=dEeWR zJJ;^m%=rXpyt-dGHE_yDxBj$MgEqv+e=%Zs+B}*|$Z}zRD3i-_X%m0)$k_SxzhukM zo~1Ic#T8Fw{EsVxM6D=je)<1UqgZwM9HAO7dYV4 zM~yM?4wOi3O$%s<>ElYnJU{21ooAY`S@V^?YOe9XjA3+3dZY$wVw6I%2dyRsVpJ5o znuUx(vsAH$(iBxiO)#^i`HLTx6Gm>Jwc@Ewn`e!z$(UJ#+bFJKJgDOt>B1b%#N>%E z2|i=CCQUS)CMD9CK9!HW=uOPX5RE~KiMmf_r>Sbb;%0oIO$_nO%mQQZX%dK1^U%y> zC+34krs{i#UU!NiTG}9qF_4*zMwFP6i(#LUC~Tz|(43fynVPVfJF~zTeu7)AG*5G7 zG_UEOu8?savfWXM-+g|;oIYu^2C7I|$&`;Wx8VMv0+;k~%Ae0ceLJXDJdL*u(u!0l^;DAJ3x; zBYB=`SoE^TV_rgdzCDt!_THT@DKw1FDaqN?32lOd5h6N_k1)Rg5qAW8j4m!M<{_=N zWz-ZSqa(Wqp+DFuX_e%KsPZ+GWo_0(8cfc2uf6rj>p%aZyTY$5Tw}hsarc7x8prYH zJ~;L0_0coj=kmRcZ{E%KHokq|m7}+|-bC}i`fs*Dw-Wvym(gE24$q6|FR{(vaSgw&8IW0Y);c^(B9?T$~HImbfRzK=Ye2OUs zI57L+>rXKrDE0?Jb3OkBX;?4hc*k7wn<|Pvg(d|DGz#oz{=P?`(j3^jqKEB={s&wA4g&IGJAW#`2qxGcoe z4grl9*m=)|P}{bNN(h0JAh=_(fI-3x7)+BvHfFq98M+x99-4tnt!4xA=J;=D2#vrM zITRz?;a|@6U6=%ejk(d8VHnnEpwR=7s=3%wDM?8a;ZEgRDiDv!hTU`kR-VEe1`CxglP~5AyP0gHXzY z{>Niku7BQN=joM97rd-k!i70=-!qB;5*p0v$@CW#@^OO+5_*q-NY zjkJ-&4d4bW_Z|kS|0F9KM%~n_R+bo~jp`~rit(t4frmasSk5RK*61)TJ+~qQNLuKU zSdZo>lqq`+H{zaVQ08L9LH)JYCYxsJ4jY2$GUh0f5|D%qiF!^{g*$^XVY|VsGBd6Q z4PLwcX$z)<3{dL_Ix!v$fElt9rAI%xi~ESw#8*;6%m&wtcudGBOa?$L6>47k5senl z+?U7q!Os=VHyldkiLT_hXF3!U#Kf~VsNx|Y2xgmdGYfTWj{nw3DTn_lIs@3W!$OF6 z9OjCncfGB7B;>kJXM&cDkU8&o;=Or z=Alm(P!JApwM+S86#x!iNdZM%Y}t~fUK>@&7T5Awr#mIRa5YGfu4T5y?* zc;y*2qe6pu3e?Py#s&Ds+WgBtsvTacDo&2x?$$h}SKDG+l_5R1e&CTDv3aJ_JY_%I zEn8ie&aPc&Fv>i+Gp z&$;i{*C|6A%K2N#R%gIGnIXM6QA<<1crcTfCTWpMWMA?=n04moOB)5j8*wP=uq(h(9n=nDnHw&k7SVkU$ znH!ib-1kvH)Mp%wvUEru@Rf_199tQlGEy##B?8POnVA_nuF;fDo+nd~D)RBjUAxSp z6*vPB>WXTg)p3Rij$_8G@bQwys!q-{gwY~xp<{Lk5mEA#h*UF`vo?ky1vl1}d>p#v zR8mHi24e|x_&v#yA5>%pNlIf(V(VJNmpk-~8Bk;LW@|#&(mBRMnt5Y|+Ga2W8KX8V zXOiN4eEHlJ!A_*J)vkv#wo*`hn({k;^Yxzc=EfL9lF<5NFteVgq-MV`3}&9=S}$zS zmL%1rfYdRXdLD@eVO>K~EHPVhUD&ayfC>i>>>d~ zac zG&6QxMIDAJdBbUixN&3-I@(rd2vdo@LfaY8@)txzE-**Wx=MsreZz~&%_G&jd2@RnPC*Ln@37RKX9t%kwG5& z;webmu8~plRC9tTB93D$Vkbp*CV0$~#&b?E&T#<&qsbOou|o|L%R`gUl=PW|Pf!pt zSh1Qf7UF8px_aNK6@`wBNI%6%$lOxu3kgL6Dgp)){5(Il#|P2YfDgl%mU2MDD%hme zDjZMN6=7gt@vmxCTxYgi%unXM+HTG}@_zGcf1(jBtp<#u_D;6X{RPEYVokkkKKa=n=4iIM`esL(2>|=b9CIikuMFxvDjJ%-A z+DaEwVp_r@zORf4*EUk#{D&7xyG$CO6kXdwI{0EZr6cjI3$4{w~+XH6T-o(+d75BFpYE>REClmMvM{kfa%J(iQ7uXMxz#HMHdW~=dhuY zcppxWh@j)D&^#7Nm6 zGWI1mga>o6wH9HC?^EMMsYHFj;5L|{z-s>OM{8x99M`q3H|ralPy7_ah}C2$bix^r z!`$LT!HGDILcyut0`^T`V}vzZUJPhLu^r z8tUI1|7d0&CL>BGzr2tu4s4}0j^DS{yE456QrzKaBAOWR$A=?rP0nm6P7G-uvVtwi z#)B}5qTJTVv8T%rUU8%&#JS*wquv#RwV|!#*dHSH-*CD;&$jRImU5*Yg+tMn(A`vZF1I=5 zHOY9{tJfBo<`!puy6n}w4J6~_SblUMQgU_SXoW1BjKrJ;n`GSgYP)^}Y%~7k`slUQ z!lr`fo!{^{GInV;yWrKT-iD*^`G7U| zOB{*fFo~g(@v<@^erSut=#9xh3y*O*T!M%yMU%5tYqDT@yR_uYZX@_`^4neKwXYw< zvDG$=X~Ugn7%PKs9iY3V5u6D|f+CN!M0;SV z(oS)aC-c#oA5Y9oG&5Z@X5N~t7K&1KEV9bSc^5wg&%xe^WSC5i$WdH#BrhBkYmz(% zK&hxQ7Q}tLa3qprzRc0cG0A9=p5hy%DK1aWmYcVHMEPrgjvB^+!qc$B12EU<4m#n) z!i$Gvks&bWe(A)RSUDfdlAOSx5obCoxXAEeR#uHb>FWVR~4iaPBm zdwajPPFZ?|6du_o(~;DdK;Pp`8U-SgCSRU_=VQjRP?vIUqKN-o^>e=Sa`#pc(U#oQ7Kuo%__a zeEJ8LPxtb5@YpcXfB}@$=u7;hPfD`Tyx}zm>b#ugEez+i3$9=%hfiS<9jI+lutKgy z!i$$9!Qu#zS4Ya@Cd($m)azL$n)UtlL;)DSZ$?lkgNmq%Fo4K0U;!Z{8n5lHm4o~) z`_Rj(di!)gn~2&olohzv7_>owO^i?CEiYmR17ix8*sDh$b%P%nGa-(GKHBSl5`dXl z8ON=R&ZAcq!>Qz(|MCaKN_Irfkj`7#n^zp7;{=Hv{~(%SIRe6|m6Qrp!o1l(npntH zG$=m=O@lbl^C8&GNv8l+6|+$2#MY`d=N<_Zn2h_1@^c~$YjdVG9gZ*YE`)%{#b>`) znG&%r$SbU2O7O_Rbvy=k<*v$cFn00^k|Sn5%UVQuqQH2P*%2la|5Fk@GX1;IPDq9@ z)RS?@U6rNyIytS_GoG+X=E{E^Pb0V^Lie1Z$uPTi=Vya0L;d!VjP+emFDUdrE8wme9LARHKMB* zumym$g$B08?$dYz5NS7vR$vNAKWY)~M0CM3=wJlbnxr5qXg3Lk@H7e7QqjfSANtUf zq^a~_5bhX*%+NuPKoLTe=A!{{5jaW?MG+{*;iEk$6$XJAsFpOCN$4XIO;MpE)1ZjE z^>^L}w^Ov7X6{kK$D50fXvh2*ow=kV33d5)ka_2#Qj8Vl(GY|- zi#A7KX2vp4>RC?sMgmWB7VKia`1k@tNw;|``~6R|Yg>xB%0!rFIzeuHm^s-4j+%bFB9*(BV?ihKvZ4Xq2rzez#KWS^;t(95ZYp>;r zBz`DFAc&yi&O|I4b3XpnFOoAl?lv-OoGTeWa;uTv&%mi_Nc6+GuMc0RyyFa$9@Y5&kEb};MAR;G9HU{6mB=ZBpzs@g;0lPZ(p>0!Q7 zsN^vfd$zXAfBl?YoQ_yZXUcPyU#&!LRM_Q*6_+)Y%+e`@>=DkCYr7}ea7IBYZ@l1X z+4P>F`^fqiZw)N%Yuq&q*poM@KNk}I-JzWLp1fOCv2S1b>rbg2R5pFOec0JLJ*30) z8GCprD$m-y;XN~SenV*pXO8vS2iO$YdJV6EbM`p=dcRtq3AeBFPoLfXPGx6h zvu0(b(|9)2zqZx3wzH8sOWZRwe9GkP*5O>pRBB39%J(R-tAa z(HUX_?Fa05CF)$O?!k)vJLj-!8EaczjO0~*JO z#2BQ)f(0pLp)+%|o80ldtq>CCCTTp0MzbwY+&(5spyKqrQfmz{iHn^ix11!$(;@C8 zR0K{`P--pWX6L+Op?U2vxvV8_jDuT?pEWMu?pJUpB%qK)cQ!WW_7sBcRjam*X2VYk zW|{7em$G%T9cfXuW6rBhZ$Aa@ZO5tAB8yoE3=zz10~gMNZr&~pj4@5lzEXSXY#f-4 z0@7XH4}?T*0TQ593?D3Od@G!X4=&y=aC5b3Cddm2kQwHx?3e^Qh9Gn-Sf8(jME%=I z(K+3&kd6CZu-?JVG5jmN+T5g@_jk#e@{A1jtjDk|YwzE{D~VkT8um+CKh9A$;>STz zLDoN@P+|MfKyBEn&7lWuWK33b#p+NV=DR2XQeZ=;N{$OFUJ0$Wp<2~v_lM=%Fqz?S z?G?lObqE}3K?7T_JKqGgyyL-6P{;y__(4|N;8`dmUJ=$(|a}N z*rW!HFW3&PbI5(;J-hG8R|6yUPjt7%7W#d9Z3b)*$A}3 z5ahJ!!8t$1$uWPsJ(%@ z#TP5dF)ssl+Oklx=H=f)5dP{}HIIa^W_&2B2hw6R&=@0%CosUM+~CQIV@Eh}M)&OD zQ!5;1lS0^X6aZB1sIV zz@1Kt#`K$P`-Y~skOg`TW>FSdnj~a#ERsXNarDXrCI+;1NTvo}#^G|LOuH)NT2r2H z?IJELgP34;@6=C_!5W@WfSV*AtBqP?F+22YiOif|^&)V~+52*Oojf3Gf+Th@6zsX~ zm|huVwek63F}RB96xVa+5hnmNsVc_56Bk!jfQdiSC$S}g7sp=Y(R7YLtn#Hb-hf$mn*C=7CpWsQ0)V`b7W#w}E<)_(ay2GvPw zwORf&(O7V~XD_gvkUnwx><3SVr#45n+IJYQ5oR+{rL@G{Ox4Zb&FWKzUv7?UqOxvs zfdvPKPBWnAg~gc}E~J9Q;e}b|Js0kRpKOIr?j9}X*XO;-0aTkMab5E>zw8e0EC*z2 zHY}SUi;D(^ol?&Bw&siXd*MV*s-g`9f0%u&(5;#?$f`XTdMfnoU12y4d6jCuvduXd z?W$DmZ3H>hYN5J^ecR$p$R<$8fq|j}(P?qA6|4)n?6%H#J#TWNx-IW1#r)&vYrltZ zb}EE(2+PJHyKGihY}AVI+8(btuw&XIHwp%d&O{W2M8V^JI9v#ZPGNh=AD%(lVR1*q zd@dxC_Qz{8yu;yM?x1OY73LCjBS#3S);0#)3gIr&nq5J3k5h6hv*k-k>ikL7U;9gV z_QAj|p&ck3*&eUxaSECft38xo$p)%3WO90}7PpM*pufd}O;#RS!DN9YMHvf$SQI&u zJ2qLZxFNU1{O5Wc)W8uo0P=tHuNV#(5xP`W$|57INDHK(GBkN8W?OVnH8+Q(?E;|> z`-kjsl#4biZq4UxleWbL)1^{Czl-@$$rQ9z)@^`#6z7q@{1<}}JwqNObDC8$0ojsG zQjabwV}W;URfq$8c%Z?-VC{k`q*}bpiApjzMxvAa1hC7unqT}j^SU@1Yz#+(!=>=l zo6WC|F&Era1gl8Vz{AnD!#fSZM2HvC?#OUd-~}0j%%C#HZ+R#l`C(OiM3Z?=1rNLP zxlJ~Q7uAJasW|TX*H%vT7lNtjh1x=JY9knIRKh3YsER{y04-r8=84RplT&7nva4`Z zRtW^=H3N2D5FKs`Pk{5=R^3KsR@9pWNMhb@+8x3vpjneq0T+lq(nW*eAheem@Vj-8MDzt80W_dU5E{cs&S9_Cf$;SO zC%kX-g}HH1OR2#dX`Nts@OhU9wdAEMjf1qpJydAVn^R|_hfEX1r1F|&0zp(|+e3;H znyFNft=TW0&o#gJ>mcN{mjMrzl2RHjYdhG(HyU!m0!|hUwst4k?wkzt`D-6M#Y350G`-sVq2Tg%@rFY<$qq=K9R_!YAL0xuyTc7* z>o<%!8+Pq-E_Hl%NY;PC-83D2>4m5GcB4N0Q>EcE|NO1>yXuWw8}+R`MK)VXmzR;I zkL~iv%N9_!HNTaukJ*irp}YOLtg#{c-fV!EhhYnm3dBsep0=K#j_fyRub}sZv8xA^7Y5i`yS~~1F;fC;mTL<@7uA3_D+yZqK zCoKJBIoMg+nrAi0ZkDvSKQ>ykZ%As3vs+l=l@4%8T5w1o*OJjugi9xo-_zO_ndOPK z(`k6q<@sIVo_uNjthsTHes;Z8;f>|zJkM^t-Koqt!E4Ji&J8oq-|9rWU4Bbm?-*P- zy7jLn2HB1ns{31C#=F|KGoRa<({IXezx*2Bd?3BpK3rHhystLrZMApK4gcg&&ENjI zq1>eoTLQJp1`?~u9nbarmsYofa?kp8*UyY?rgg<}cFyrj3zIYD4Y`ZL_4)0u-N>#B z|cSc71-SiF{nKS87N60 znK0SvBri$Ss-(JA(q#Y3yX^d#UZ`D*-QFEHKLy(mYi{?3!zm}yxorJSFkgZ+1l)6fh~jrKGNUg=4;#CV8=CEb92McGE0m#^IGDSX-@B}Y>v~D z%>ev6ZjrP--YuxCE3!2+Q!SNz@65Ulb@=r{Gpbk%Fkx#r=nYTrw~9M|Z|i_HO#05d zs_bLH72*OMGftIgu)@|%Fta1XyvdSzu);T7&SuUVZ1!z<-ti+|ZF^`TT3$DpGw&K; z%XqdqNO$p{qF^L+ZnK}cK2-O~S*LkTNectNoWb{vY9qyKymMxQXWpeS(jgep>-LV> zJ&@;~-p(%-Y^Ny1i_IXGS`}$r&VTKtXzFYf;BzYl-aw(-HuiV)Mupj?nqf}?$|M|z zt&4@DuH$+0$mY`Zd)!Cv_%%(Q%@%}H9Q3^4Wm^m-wKAiO!OAUT7F%Od6ZvJBgK&H= zR4??N5;E;@Omt~Gj1|(-#)ljt%dgpTf@ow}_U5O{BVWe6EXVh*^7gEMr#~ zp-yA=xNc{)$K5ah2pJ2xva1q=8peio@xB%FIG^8E@b^H5**huJ?wKqUXXl3N_UtS>JhP*<>KoS8w!emkY_X}$9@?;I zROjs~DzOJ7dfP)Ah?fjr<@wePxskhFzq$Lr1sCTV`||b;_LLLt9OWI1+x1KSdQJKh z`z*A&p~YoBhkJi#nZ0c5KosQ1tg{>Joj3yxoPNYs26C*+1dfoBSZsfwTGs8vC{@qA zma&iBA2&bwc~)L0zy1@~&)@BaP~bV?uI86N7U&?;)+S0&kEVzu*ecT7>~dZj-VdghJM|2-f&8v~%(A!SkPvp!70zrVBC#O3^XEs?5nO*!AH%G|qK$IU&EJhNVi47J>mBmD3V`Xhbt$}ta|6>Lej88Nr$kcDb6e*1fSlQ=3bK1 z(P6~a1i>E|Ir}4l4Twiw7t7)(j0xDjHA>v1DR7*lD45uesF>p$qCNHn%rP6@g^a-p zJsg)+J?zvXeoLdUlb{w9#dX3~xa|7V*za(ZvM(6kNcBNXNPmz)2`xCFGaQ@M`Itg+ zw4e83Hxc*+c@~f=@&82LTR+TdHmaDcoC7`UC#|W+Ufuiw7dkxWAI>Ts42$8Zjl&lc zqC!W&f;2Mg9L5XWW_g?7MNq&k3{Eaolv}Y+GB#O{@`%~1I>i!OQBsJ8ABJSEQ=iHm zIJ3cA=IudiUzI5hhJ>3O&pCx1E<~>{jGpg~$=7rI}6T$$Vs=o0}-?ddPO{o68k{dWy~D!HxcOxX-EcwnD*vXSqy7;?GSKiVysF ze%h;U9rVtR>Yh`tTI(;#7k{=z!ot_qziN1tSG z9JnZ7x1yV8*&2(^3Zv(jP~PHm%KpBg!F|)-#pMVWZHMs33$7To++AabODHYBxRJZ6 zd`6x(dp6jcw*@<+4g2%esbF1k?5tvLa^NB_oXY#7qkgH%uat7eU`+*$!sG+q-Pezd zHLQznioz|o*UD2txe%5&&HBN@BmcIOoN*rO8rc$gRqHCdxU&vN`Ra>ca4Lk!R=GCi zTlI#u+4int*BpKW*nH#_%Y)ViUULZ!DwgnhtEkLwd3hvnjTEL>j;^v7*d^CK0ECo+ z@|2q|U-^jk$m^I*7?4qJ!0RX(-iKD{JsxS-t`L{bnq&Ensa5!PIE1*cvXCF4+;We2 zQGPyGn!>6)E0R*6_A?Pz?mcUcM}9H;$N$h8W$=;eU~zEXHC;FPdDiY}Zxr5CY%>?C z&*uwuuyD&7DdS2?<9Mz~R2i3`2|K0vX=k4^n%|JaN|+s_7K-JA4eQ(m|8}Q->wySs z9p&SZ-`nDDV66f?B zIn&r3UDepwi10j7dUZLpaC$NDjeHZ8mLgRTpci4$)ZgGrP(=n_K?jSzY&soKi zm$yd3a>1Q1FKlU8k#%lbm7*KTkAUvCcl+o1h5G#S8&>H2-Kn5v(+JEC{r$+_mMdEm zgFmr9;LX2!b#Wc!Q*|#>%Jdqb*LY;v=Qr+b@Ef=#Cq`Je%fntd7nG~zf-o|VDY`9K z&Y@SFCf87c1@jnM>2Me@<&j3g1OaF~#Z(nW@>a0F;K4B(Ggp_8U?exCVs{W-1<-!X z2GcnZ?KkaM%s{>OvZwFcxt|Tif^%lBIB1{a+(y73?Do&wRGcE z?K5-1ROuS;*7As#^Uv|`iW=h6qYa#~+90Ph(NFty=UD{o{!5}Cor7N0&ljxvr%o*v zMs7vk=^$SL0YblQiUt_}&iz((fAhCrCDp(a9<~vo5v^4{zcG@pTJ;ela=t9Ul#k>B zQfcC$Smfa4+v?yVC?)U7Q|pX6lCw&!_WphxP&mt~m1zW>uvWu3#}%U`|4&jF++^q@+SN|D?2JR?6ZIsF*Mq{%TwSgTkGQpK^Nn zy!AJG{B@V=EBy<1Sn%u*m2aL%JG`Xv z>Yw#5yX3*LU$}68W8xQYxVJGe_?Ei;(Nb8N`m(+7TKm=wC1>nMqvyZgdt`TbMmhRQ z_1^2ZJ#tTDg+V^h_aJwovl~CSyAcm@=!VmRvb(E{53ZKSC6cg?-PMU5%jer=e4f3r zjJ*5^$5t=8gO*bq&0&;7UcPHb-&7Vd9nWthSV!`XkX}`eniuU0cDtLleSY^i$!fT{ z+W71RH(WAU|Lp#|OV@>i&Tri9ow4CMdzW*;=J4#@udK8GXBywLsW9(u)X72b@YrQ- zn)wYW_DYjOmjnfG}n^cz(yv(fO4kbuc;&q6Vd&F)v z|K^+&z2uLaI4cpSVQvekfXy0GyjrZ6twx=0UVeH~%HDvw2NIzXYP&Vl@T7ty^qC>s z^&Ri-cw-?cN3ldyln>zWBHDNq)8RU7kJYdvt|f)d*H)7feeVOD^vQp+MyFj`irHuF zgW%@h|9>s4H$( z_4WU`yg=ofHLtBxmMXAs6k&n=Xz>U2mqY}p z0JIs~l^(~1Dp$0L`_THN#iU2L^G}j(HA8YybO@5pJyW?Nb7?LTk!q5n%>#F`o+Ev|#n&+$`%oUr75iU*j-k zeT$`}l~j(TcWSMNZe{z!0BDUF` zNfnNPIm!c>{I=D>h|9$Ga(Aubm2PglF$n|>7v&lhiZJOmaaudY0{OO#Ls|)Q^Sr-G znn-`qG)QKVAbM!^l$(QCDiq51!{t9nahoJvUILXvX|r@2t}_iK3hmjn2Jd$BV;@M# z#)*q;*kKl^b_bLA69*X~_O5cx^2<`x<-dR#FJvzvLbrpO@KD9()w=K=3oD9 zQf0Ib4007(h1$v>K^VI>T_xoD3QBu)JTHo5T9fQ@)7-u-tx?RUEi)6% zriDa;tg%c$ims@pN4W7-Nkj-I<1H3=!D6CSE&-WI0ORG~+NEi2*XzSCPnSGTQ50(g z@pm?YV1ETIL__#TRaZnyDw-eoiKIlrXDd?%oRPi~CSxV5?OXJHXBx=b+IJVUY)Pa*Zto~MPk5G-3(RY zHwGu6Ngp~RSzdZ%e=aRVbx~gWE{ap2T$ZLdo3)jvwE2qHbH13^v4o?X9^WDr&Y)1L zFZL@w)B>;~&a}aeKa-NJ)gs2Z2s3see-tZmMh8;_U9MO1hJXRspa@9Q#z@)-WY>(S zB?*&mmv_O}F23?*iFsfaX4OYr;F0QOJbbLjnh5~_OhX`T6vw`6{>ODm1Br}&GC+8( zm9^EA6-6|o<9)=)4}C68#hA6Rka&be>WgDjf+wSwmG%nXPZv{JAJMy6f3gTnq5yKn z?Z> zf6cLr5>n_5OW^@zx4lr1H@YEq^%G}2_WeSF7Q##z&L)V7!!z;{i^1Ew2(9K%d^$l3 z&R91rd5Si@WU9i*`{lhWoz*PAJ3%Y&4zhU8nLtGfN3O2@Uc6zi@Z$3pZDu9z2;Y}c zfOrswHIaFyVx>WD`9?wr#KHL7>7g9)hHrLF2N zH!n{A&LZi59CU$4`&Vrlnm`VdWFC@nkI?-3Gn1BPyF&;~IG`<|7K)hfQV_+beQ5LR zwx`HV@&Im@p)7`Y&j`%;I2llD$Q5oL3JXaK_)7$!5Jh2ls~ZNcm0S{*zu==)wbIQk zcPF|h7NfuN!3rlb#NqnTIUKX$Odq(noJ`ACp0UYe;&e0D#Qd|~?-4sz)! zKd~r)#xilGEPX4nAX9(shttzCDVVWjh!yFrMrPMn5xM4*_0_Ewoo^16QzM6;iJ)*6 z7)aYNkRyC*3o>I#osqUnUvxCNNBj!9Oss-MW&|lqG#jAQW{TT5I^H$!OV1^7JE=xX zjBUQ6(E6s!L_SnLfiZxDYjJzGVawFM4l zG_j2!Mi?t+#sjQ`|LPYdsg>D%Fsf@#It_Q*o#C;J5MK0yyONrDKm;p?9g$DANj3=z z#$?oo^4?wQ;a4Q2p&j6bi^>W?l~QaTd4^Rwqi9#84Z2;M`)^B8W5&h~4)BrQH}2 z8Y%W6O6#28&&3F|a$}Xu8XmLJCMr`fo>6`ZruQyPtNE(*byzfn2}>W$lEM^H)C8s) z4~Z}>1;u?hs#pJJf(2G$&;%sOF--=&5>loT$ML)?)4RspIhJf@#_KDqmbuXZN1MiY zUxLM*N>+&8v0wf7e2a^Keys6Wx#q9cprz|np@}*M>WAyiXFoqiEFYzn7p!7`*4?pz zWmsWWwT#^+9lKqchw4cc#3qOC2rg@$j0Y!}j#MV2_}x$@<*)jq_`7L&m{=N0BM3UnGA!Ozm`o+p)b{FzV#Vx%4BVN$DviC%~Gi3Co@#5w)0K% zHR&d-qH|UO*+aZmr5%LUYzK+QVo;Cp;(tju<;7U38LS{o<*to^MZ9%#*DgKwUGqJ! zNg8MkF;N}5W(H_=G_N;Pq^K+t_q6J}+&naq})&YlnkX0&;%v7Yqceyt2 z|Hq_8`T=rsBdo>*3N6x2wxki_h^ils9~f^9EQ+-&odhARa=3y{!mK=$_hX7ff05vb zd66!%i#HWe%}DOs7`j%(9^nOv<3ns|Xl?MM-C-A*xhx8O$rw~x-|c$sf3{vg1~rt+ zE#suxiejnRvYa$ z`B#dW=}Wt%A!fTFEnn$+=(9;2W5RJT7>_NhZmC|pVS_JWot1X?2w&QnzD1_B#l-3H zTP>~rWdp}y2uA<*5H>I(-Fjc z6PswuGb7uyzRR`wliy2fw6++NlO98Ao7b_|lcQx}M?uhNjE4eSl)a|+X5C5Ewpol>VmkEN+OKnE)wX4;;8d}!JUzDJQ+nBpz zC_G7K8B<_Iu!;!#@PL+eWJltn;;j#K11z${dg8#2wh%$#~FpR5VTs>1ZfdhMLmiEsB2qSroPMVopXsNH(1j} zAVablryr{{1MPiYvRo>Fq{O^@&?YxC`D`ZGg~qh_{9jJ)K%@nRm;`HCVjiZ*_>;8T zO4sJ;slCU0%`g$vS}_Q>5V-Q?Y|_Qtg@*?r!-;@>Z5GvX+Y{Cgw}~nQ($V5-oHw?zW86 zHr=l8YbB}J1%fo#7v&pZM8Xh{()UUEPk$#F7M};vtO$$tfQ?|ayVzP6x>32bym`~7 zlOkd<%{p&>XD?%Vir%z)rk$8RslN7xQ)1)_eht}LSTeW`|53j#0+J}F#r6A_8 zpXAy^VL&$xUV09T-+&}-9Fo!*^=geTmdD3}a;nDG z7mwU(+2Q6$m}J>X#V`%X6gyhVB@ZBr;nEi`ZkbMbLEa@*!vjj6(}2~G0w?)%xW$ zO+s9-A=Z@Gho?kn`IWylr?lpw503wP%JDdXj@8-VTg2K}wPCjSt&jL8BlDD+F4yJ- ztzRj`lg6CTkXe7lv=}EsVNzmxcL2=^zOl^!uFiz2ATjS4Fi49g<$L@$eo`rS@Axmf zClRk=Hkgcp!-I_LL;tZ~EEw#HqI*aEp7Rp=bVRQ>T>d)S9jAzMFnji`nXGVg&bw1` zweCXOl3g9W@ke6VhbA7`lzOXJ2hcI5%a&-164qxOt&^^4FJjRQT5USsoaeRoi?yc% zy<%;~bigWCVl+?u?PufbqV>t3_(F&>?-rO>0a~=k8<>Dcd7&(+RkPB~p-a>03x)C2 zS}|MQR46CgDp>iZIrWjWk-VQ6A)k?<$(-t7dD*Bi?b7vn^;i)z;oWNnd=F!!wK6Vx)T82Yh|(Tv*mEUr(Z7?bM*YdUG;k53$yY`i$~*op@4l z*-MlB9F*+zDKs~JAnnJq%5l#2@i(DC zW|Wn1TGo9(n&ekHu0 z-L6-@Ak_dVx&)2R$_!ed*i+PJ+*zxx%gwbfPVy-Zp)^?qQW*xI58?}WakW_qc0rdE zH{bb+Oat^aGfSqda8NFmEMd{>=b1hoZ?F8F#CdC*QEzPN$Yya%dB(*h$9mfP!X$i^ zJuYczw){{r4VBqwoFTx6%qx~x!ePAL%)Qv(^KDkf`n($-KC zw(5PqR{07y&HsH_+QJ}Z`faA$6;NF5bVW7trY z0z!ecav|B$w6^oLdFU%?h1s+;JXuyOEcaU+cD=yJov6w8QWfuPf&7LnH6_cp62MeVG1>L(vr| z>QH^oRC=&swqs&Hl=Y3=OQrf@X!Ch#qRjlnNKx7bm6^a6?aF9YyFsVB=Ih>;7MpHn zlin;iX)#y1HA1NLtf3F=Z}{xU0}F)%QSsULxShaKNnmK+}Hd= z1vQZwOjV7ueYMn0)7rwrY*w=2uC+MSk_V5^qRwHOeev$CK934{V0ks8s_xBDPNVd4 zN{xUl^fAIO;{MuUA=rmnEWQs^&RwUWFnI0u(gNi6y&d&F2F{D2`m7iZF9*>epVWthjVMCt)BU)) zKV!x8Q({LzmxMbT4f7Y>Y%G{U-MY}qE!&BrZblrKCa)B=rcg@Km1T{{*mH$6@>!utM=ww5Yb;f7JAZr^G}IG z_1|~@$y@zRNy?k}#y&R^0rd^k3Y`d>BG_RRP21XGX1KtD0lzjiaTj?R$ps!HqbQZy zhnhaQ;hPak=3#XjMZp`tC2tNlf+d?SCWlayf-u)cHQS-FKi+0MgxoarqYz84eO=~Fr`z(5J(CN9%zJnvE3WAm!l6|o0 z<#3G23H31Rzx%!0GvDwEd<_-OGmmYC)5&)Q=ZA}E+O_ElAISqgN$Kvj7geeA+ni^>5z^e zL4yVJb`(%kQt+F_=OKV@NO_UI=o%dDM~`>>9X|9Qpc<6C1Xc+(GmH+9 zj{r5-G1YVdX$+jlwrFK}3qcuN${0bZICBrvMZYJRA-sNjvLBU0Y?WkZC>%%BfWSl% zGC}nuZyT&T)B~Xo5GuFlABms;W6TXGf1mHd<3cH9sED3h5p=}CAuPb>aGX%L4tfvy zz*G`aHBcWB>WT3uWDP~wP$V%!wGy3k){0?U8(~NF%$35Q4F5j;UKAtd4TN4b-rBC%F+jS73H;^fF2(zo5DmZ5H<5TZtgQF_rXV%DG>$cQ`9r_B#~ zU;VIvZ9%b^FNEg;W{>c9ha&}>?RQAm4_x3waZsC8Xwda{{T}Miahnwjx|%9#L?}Cq3Q8?dON2NT zYVx6=jAj3+7h)mJvW&+Lo(U?s<4W-0g+6QVF^0=Ddw<%>bfn{VbUSRNp!;M%an*Mc z!-sXSSHc`Zww*&^!S6qiLi8SHc&cVQs8du`vtou`AOB|0@549%d-IQBJx6cQEnLB8 znBE3z{=!LS2I>ini%Db*(_Vd0dYtMkrfTaV_wnLqpU{-{4xJ&Vv4^Y&hi( zJwpo^4rqtngswrcU_0a8S}8qq#E^`raxljIZk>nf(|-Z2LN)3V>dxRmjGwM(XrO>0 zP66XdP!1bc^#Uz37)!qt2$b){(uD&Q4>_*u8>zE^&$->M>2u&Z?JUN;OC85Khh+z2 zwm>oIoj5?F-}uUtwt=Z^QjyvYY;eyTfmne$LX-+GbenZSTpn|rhww5=F?lDcF=h*> zR#l+dBg>7PT47H-X(m#9CtJ59st9q@4`Fd#Y6`KBOD&jxahruR>Zz8Y;w(na(5J^$ z&_Vs4}!@)3gb8@ zOQ({~yNz<%Nu2SfaOA@dnVV65W(=x1%9&zmeuBQ+Df5UIN=+x9j3DNlyuy_I)dQlSv8@Es`iBos|MX-?BuQUoYjPK_*u z_TnmLb|x9}+tIvP##2`)o*7>Ghf9kO3Dg%KqThSZHk1ozD1KdrKZ%murCHZYn_n3( z2BS)s79USg+^zI)4;N6Yn?_Aka4ex__()R3p+7xzgw;y-+$ZE@t2G=pZ+m2&-aVY$ z_MW_gGRq$uf7*GallIxldjZD)6;wC zlXi6Et0*tsxSf4#1yFMlc+ufS=owan#S6)xuJR3Ej-Y(BE;g=9T>Hg7En$U1>hZWF zs$|GVri;48#S+@DlJaL)zXk1<-YTBQ$5(0j*ss#cD=Wz(BtP~~ zOIxlU86l0p%&r~-5&i3pGRh}+P~}u^GO`C1#sipZr;J~6zMsrn|J$o5s?Fm|C@YWqpy74dz)8 z9)3^_`}ckvMXoc6wM=TOFm9scwH6&9R!kbagi?m6^&QUlqXIf99lpnB=0)nYim1OX zD(c8j3o_69!p5`AXiY!Mpqj15h9l;!xH4{}>s)^`ey(BVg$8df$_`0G=3tVkMz%u9 zjPNXnHTof}BiA4PRi7QEDH0IH6ji|EOQ@LJybXoH0i$C+3sP#rH^r*NeMn&rsBh^= zUHGWS-9!a-i8;HIp^7#Og||ZIAZ+_E^{s^j<;ovVldqMGGszhdFQNoGYL5GsNb~Jv zt8;favyQR>Sj5-{{H)X)Hg?&^4w{QI_l=d`(eiQ`hVjw zR>!iA=0U6AqUcKLhya060GZG_g!=6Lx+Z!&j*Ba@vvPI2Z_;=!B@Gh=JyBuY6fFZIOdpxXxu(hVG{$H` zt4%nrhg?*WuyKUNbB~}7HwMj_zGqUzjm8=p_Y?D0-d-IyuC``H9Dawh_G=A1g^hkJ zhUrBLZIn2L7RX)YIV=Zg)gNtL6Mj@Nbv;L}mwQy!6aM8)H!VZsy6^{JBjT`58Yu49 zC>t9YIiOI8e)~cKKekuW{>W%8o&%L=YS=0tyN}2(oI+XqcaX-;ZCL|D7TRbktC5S; z0rC-tPGvL0yI4pH3nB?$`1P$>DKIiF96MoY#%nfZCVvm+9W`H=Xv0?sj5VkVh1ZL~ z2{pp0c`on+nx>nXs8VLE!N)@I0@sY!;Blnsu!WkFFC26X3~+|UUe_%SabnI*g*w07 za;D$_2-ZL_?e*_@SUZnGS8+{wEwlT`h!vxX>)ul^#&FuO++rF*Jauwzf{ZPQr7rRN ze21k5%9h^{oWC^T#IWIukRb%;nP&~@JMA(&ZW4Yt!%?^*w{W)5fBm`1|G#Sa|7+E9 zI87-+2%Ttx40{D1P@J+iVX&&g*$or?{NNw0CcMn&l>WOB@US(67xTRrQ#9mX^#Cz3Lv5qN5r4o8pcDd5j`{Qb-~0}_UCAccL3nqI$W z!7;qMyS1K?v9#m_(L`kWZ2_PLE+`_u#BQGCb@;oO_d1HzBhE#LpbwGCgG}}D5tM>= z6x>sq>Jb=5WTE|QCaE73aHP4osIGM4!M?k zEr_5_L|v44#M&-dUn+WVwsB1JrYD+#?1{lr4K(Ua8PS`>K?*~>qU^@f%O66pTmkRLTb2Gc1{2ct* z5Wy&KCsiGLC}&a^|)ofk*~&B z9l3XSg_l0C0w=;tR=F1?wXY?cGKIfB*68ynWjhWt>hY$VdS?>8G~eVBbL+6aW@EF= zJyftCqptFn%j*eBM+auU43>E>cdv~EYFp}!!X^dXR}xZ!Qx$9ARO zWXQIM%=<6@aR(+X<}$FD{3QegmnFvSWS zx(D9#R=ZV3c+aK_ShR_sbk~8(^)09Z`mQ59RiB{UQ~1U`*{X0aqK42y)N3F8bakF+EB2PRBd zO8kL#MCvD1Gs8(m$gjNbSArf=g)fJ&*f^Q395XG`{*_YHq07G7+Bg(hao6LN2Fgl- z2=TxIT#N1+&_RR%18`SN014Eybh>zfYGk>&igpoa%D|P)a~w9p4xiv8hF^su&OpV# z@Kq=x;s_4lV-t1+OR&Z>lphBDP)nS8AvuNfmzqQ9rKm&d(Dx3s+YeF%9c4>9ZWN;9 zG$j6c2Y#25G5j}Zi$qr~&q{UWagb-xuIq3AmR1OK5bGt-9eB`9d>4)=QYY}fHP{Z+ z56Hl#Z$i3M4gd|LmaPJANU{&BB$Evj^1)a^J!KgBO-vknk(x7l0f1w8!yZ=AeUp6g z=lkLyKB)~PbW)?``toph0hI|GB1#hdQHmxB-`LA=20wwi`{y}CWsx}GRcb(A;F{um z)Tt&x?_>Z7rN2E~u}z@AJ#EY|a^!*11jF(L{8yp5_)4XKxs9m6Bx@NV&)PwRcByvc z2a}w(81P4k7{>cQVF>wu;gIaHO>!6EX1qK@0UOG zQ!_Oz?mR=G6eyu?u3IU!3m&=;uc!sd!E#OLl{KtmRmb%J zj3aQvA`D$H{V6!In8O%8$by66F{_Y_u);7UsTaQf5f=**Y!?~|!Q}xg8pAC|((85USQkbs5d>F(Wlo4pz+tQp{ zs_ZxsWmAy_-$%`e>!12J52lPxCgOs5p&Xi}d)-i62%FK8S6D7p+N&4lmadwwyaZ5b znRqHWSaRC@O5>1KY7bqR57@nzJyn`kb}|-nj|LQwO(VgY+;Wq-cvN}3fw0TuUT|Pu zDONuqN^^pijX|0)ta)p5SgO*&#EpY&9sHDgBOzscY9%|F1mSDtpHi8BqIB%I%sG20 zpgbH>fBx^jAB%X5ddhr+HCjmC#O|0x_j!6{s_ zhifSsJE;<^r8zAn;^t1nRhzUlO8Er9rIvk#dlQtG8|1 zqQi+q7VHqp#SSgDe#i>fg#v3_D!j7lAnIkSe(CE z16px750uOG+fcx~?IeEt6No>v^<(PWE6G2jX?#0Hczrv~uA)mjo&4S*l27mQgVF`& z-<)@Zr(v&oJgG*}D7Qw7##D0qyNq~fKqT!)x|qr()4PXO4DWEUn%ut7QS)XNyX=K1 zxzAyFYsg{Yym@*hAF#^p|3f)>dpC`r`_8sBoUa7H%h)TwxkXNYkom`oW%cq}a%5aN zb=O;}UAVIteBxlcG0fY4=B?1vi|fBzEIhuF{4$Y`+}d2sn?Ey{EZ$WHXaSJH+chg{ z7vBFfqRLm2SdOn~Y>ZA_qWHq$($mhc~88UGc(Wy9bSa z5W|4IhcBCbqPid%RPF{DMt5X)PFkt4#K8LXB*rTFS$NcWK z*Ry`&adLATYr7xadk=z8zb9v>-5}q18_69rE&|iL*~CiIldvX(=f`dngjbBYo^(a8 zos>dGl2j0B`ML|eMt%hn(>R#UpFyZ>6@y_j$kabJgig?b&*Ff22-ZgXv_P{w5)k|! zlKYb&UVN-FZ#=;JWJ!-OFvm6EpupK!(0-Q`dHW1WONSZDkF9#fW0kA~4`ZCRYtx5W z-u}F&!81Uz=7n1j0HUo(fB{!)0#ya}0>m0XauJJ-i0c5prY(t6RTRV9tj}+TB89h- zb%2CgKC{vk%XYsM5MJ|?xY6VhYCiD(ZSl<{9XIR&BO`W%q;h+a4ojw4&5Kz&8_hOLe{GFugV*SOFjgcUWhZ;yD4AD6TcE_P4@VP#aM%7GC6%0ms1$0O(NX5Qfr?f|G;Qh%^8ZhPG1xP$<4F zD26hJlqx{A1O}db@wxsr&&b=0;v8%gTI8n;OKk>x3VtJ&P%kO^ZFCnIWQxSvX>;=t z%YF$#;#kSr$S6V11ui<=X!JEV;lJ7d;Xo|{FlG4;)X-g^2;1&GQX}&gusivkNoyzD zn_YxT&G%O}9fHYih)@4QVXZNtqCw<9BkLz98KY;D z2w_8Otme0dNDJ^;OOd@fB^`1FD@N!QQ)3JP#Yr>lkZ{=Y`^i5jka-iCLWmLq16GI7 z4M?9!h8+v+oDA0tPW(<^`K9+ht6uG%a9+CoSvA`|tv)(&%h>HNN8djc+`?~vx&8gq zvmZIZ@H=-u0)* z!P+X$_KAOfb(NK0zT?@e&$zE__P+hM&+`2nXZg_os4Z{yXtzE|aH!Xz+S;2f2@XB; zS>qJwTRH~RP?`y-EW{Y|{cszdmO7~L1b7?t5kLkhBCQOw61;^m&=U#{Tx$esvAa*d zC>NNsQPR0IHe%@bZ9yO+VBtA@(s2;CM$d5@3^17i5{n#5g}|c!>@VSr|MjDa5hV-y z30ehzv-j`|HK@vs$Aa~P7jRvP`{p0LJiLCbKmPQS+eZp3KnGT7sXfYfv{u)y_^tg2 zIXN9~f7nmXQ@D4-v zcjDPlN&ax7&p+(wj_-qE+spjE5U6U#gIjr6RDtSa-fZ1&joc6pBWKli2xoZ=;S+3H z(4SR>vZ{$>GfIZyegCyk0*S~uD#9x~^TG+Z-!kJ$#WGH@RtR_qTaq}S#vJgy zMpEHvv;*N0f)3c2BV(YQC4s==m3qOH=|R)7Wnc(*F)3|FgD|k=Ok@J_8VS>|Bb{!T zkrDN%F>J_eSUth)`_ym}DA9Q1mk+`yk11PCglfXF5uufuk;oBq_f3cstXSvuI=Ntq z5fvF?{5fQ!ovX7H%Vr9QWflRf37k&>A0a9Z2C)(%NRMlXUK#}qAO_BY(G}1G3!nqm zI%{7AfDwY$&?|I^Qek;cq+!g`>wo@}{EDI%Si`u$+0g*LokzUrXi&1~cwoeX{OC1T zC2mq`bFx%EXr*T;tm;>(7*0mB5~5B78)Lw7lfjnPa`5$8nSn=l5?CpZySaJBILARS zUyB2YFm)S(VK8CK+kjF`9g!nT^pu&ES;UTuHOFWB`P@W$EjZyUm%X47{pm;kqaV`J z;b&vVJG@p3_*=YIq)IGoBq_a`G_`7sC4<*o`Y@XoQ^`A$P?a1ya5$(t&THJxl#wGd zlME8?@Q0y9fR8Pp!QKE54$IPjd6EWEb2$tL0!D+%eikz?aA38(R*hjC0qF?OO?KOE zy(==9E%_jGtPwR!#b77(tf{2y%-53c1H0bht3rmrcR)wk_!h7sQi9L1#O#L~)5eiIsJivT=4ZnPIfxiA5uh`nA0o-e4cq(`WAPLAPG)%`~K241$ zX&KaF9PVJ!rnYeoNRGc|c&Q7G0 zmR|is<9} zR*H_}n;m_<1?~3%kHTd!Ys?f;L1$0X5S&s#7dLsxaqo%VB}Qw_4JxW|fxuY_+viC_B(w zP=^fYOJ7lYx;PblXhJ?jfir*D(A`5`s$oDw@R$)W#TahLf%tCS5e%sw6UZ==bJ>5H zh7kdJzK&DUb?XX( zEH#CvX?;I<%qYEx>*P&Uq-rruRe0I4U+%n3;N3tIsaObj4q2B5G`uBv6&nz2K$T2k z`hY5Hk_{lQ1Mt^b66v#o1}L=~a>IAPr9%ue7OD-nHoe}GlN9;`xqDcigY6>*xxSk8 z4)>!1AW8+Xg)kJ5nF;>|-OaLaxtc0b$GZ!L{zO&{l`Q}r(Q?HEhQJlDV6?$eI2rQaJ~l^a$(>bd3w}=+T5_qJ z5#Xy8Kw8MHLEubiZY*?iLE+$XU}7VQEc zGNK3Fca5ykr)g^$vfIAYlSRu72)^tM7QXCQg9g?lJsDG+OiCa7BXnn(?&6hB!-=qd zVI#+)A*zONed(pQjPqhtiKdRG*^(@^GW*yHU!N=&bl%2UH%C;x_-<9)q;rjAFyzzh z;Eyy8wZ=l}+=ZlB<7O50{WzoLqOnvOFj6&a0O16N8u3;%OfNejES$%Kev)?$cniX_ zK5wMJ$|W3|x%)xx9#mm85Jv6p++5i#Kg6GNMi2wM+7Zrgiz#}!yeU8Z3kL(NF2nKu z3w&FteD58bUUNOGdleoiJ`MVG;!*ygM6ex8G@DO4tyb%WXVpi=X?hoBW9%-ZFUudf zb|z`FF-$MG!d`1FJLjxD#x|H^N6P~eY?+T%q&!!a&PF8<*fkIqKt7)jdbCd@a2Jr+ z1+)G^7CqrKuxOPpSJJ28RJeQoj8nBM}c-0 zPhlo#gw1Xveoktx+0jtsZfknjx_a;Qw`)mp(b>r!DLvy{ zn@g^c=Q}`I7q5O`PJ<=~W}TXRxRPA@?JLt4nj;F>&8gP=@}5y%DZWZ2QW z*eJian25p4^po|gA8?0P=z(xyjb_66U)cCHy7)RTd+fY(cPCjzgbwg(gEh+CMD3d0 zODoN}Iq~?)i70xOP1n3YzJAuppUbWf4CECTl$(q^zhd0>`nQh6AqQ<|vZUIzd1@>* z0;6;j4x#Y0xdwLcnJ(ZPS8_>0PRD=EC>6Z&@SU5EVZ`ru$@pI>leR)r2}f@g$dx_ zkBRuK1TuM$nlW(6t$>jqzz*HYjrbmzi-PG8}uA#!G@I0eVs@ z;k#qAPh< z4a*>ch>KK8fqA`$!oA1~l7WbYrO-y`1Vz;FBg{C)lS!CvZO#2cHR-}^U!>uj_xb~e zVeg}cA;(Lmk|KT*@Efwm+h#-w*s2rLYVxz_RA)R{Y_w)~Q8Is?L6d$1qjv!S7Z{S> zG0c#8T&F_WGY()eANqSnnV9A3BEV$}FV+O0Wn6J5Blrsv1<+=aN{Y9zb1&MiiF%9K zLb9ma*AB1$y`6Aiq5_0E54xy-(##K<*Z|=-9Zc}|oc2mR5wJ92@Jb(q z1YpVXUkrf11!T?R5XkkpF9OITYo&76;35mX3$A~(>=*VP08rw;IMFV%GWN=y;D;=G zz`}kPxE^^Q$7Ibk7Pyfq($Fh3LOrNZCP71M1g3u_KzA?WL+zCGpcU1F=D?$a%d|IB z2swObXE#;-A6&Ff;S3sCE0cJ%hV{TDIL4=jV9g-=efayp7)Bnd=Z2v8mhL!Yh z1A9Ff?C(V6{-?3DTjYPKRS}n|R1YpZOYE@3Kh`?bh_;Y}$_itpd{f0NoIr{(R1PFA zkRT7^Q9Ek8?4Y>jinQ*W1#afcO+K;7nS-bDqxJGsojdG|S`@|$pwn0f1r4t-rojwn z&{#OZOrM{3;u^FM8-M*LczOGRAyfP1YnbIf{LmqdR)8OVPrugQ+z%db>J|`e^^U|R z_+7=%0u;AuJb3hNcOh3sqoaqWTD9am>SZV7?TpSl(6X#$hrh*qbq$;M#zG_8eO2gpY5nJH?7KMG?_p2eOvrA7b;5mJ{DlSu7j zToG-CC8fe!W^j&Ph4(D?!MZ2}z_N>teODrcw?ar@T1||;dEgTH;_+<=ow2uYPUfw0 zuFg-*rHw-qg#htUe}i3|tA~FeO)^oq)k#VwAc`CgnK-Ay zC6(=KBb+{Tf+24k(CCoK7HAjbJ>VtioKy&oO&2E(2kA#tihPWl*4fT3up4v2*p;3& zs_H-e(_iy3FkJ*qTQ|M!GKI76CH!@;Au`HGK!1jhQFe`3z|(KaB}8SH!-km&Zy-{j z0kKlF#O9pR6Y$6Yw7*5hkr&J&vZ5pd5U z`O=b>5i7MPh7l@cgC}6NS5m|`G`vZIy=boag)?ya&!qI5ySW2yh`rlT6v!m2!9FYO z)bYZ}Ml|Z!;bp)+(MMGHYru=4>g=E%kKg zA8N!^l|jU$9@6=SN0YrJUgWJ*X1~r$EoX^)R>R=V&FOg5w;o&(Ua;L`bnzwE0I2JQ zFRt}@?{>Uxc~Ip0-;I4|QJ$_S$0~E z4JzOeR6Pg1x-|=)gnNQ*Uwh#ATOY=pz}%t2l^HTHvgK?NnStPKEMSmAC|X`pSWRsQ zAqfG(p{4?Z=n%ViBO3uNOECcfoYZU!`{})Hg9=}jqytUv_e|l8b>r?0`z1oGig2*r zxObJn*C9%h9BRZ6Z(?B#sfQ#)DGG}Q0FuA}`3g*#I(BM-`Ax|o}m^DL405YUQnCvri8TY%*Z4dQ8fX8AOJWL0-PS9g;a(c z63XI$>jIXm3M>Js#NDhMwk0_SpEM1La656=cR{Q*ar1y3zXnVLn^`b71jLIO!mng; zC8K#?Ze|(m-#1f4e8EBBd!|2e3q)-jWA@felok!Zi^xuffu`QUX~k4tzy?I^caRKh zRgr$!z&w;!w8hQnHXkW<3;7H{-5LzreBZzCL)%}&1OZTqt$-H1Y-0|C9llh9yk(k^ z6&OKw&>*+~WPmJTA?qzPPZ{J~&rGB}H|H$mu~sg?cg-|hk)DI+oYvygA~gH{bYvT;WwzBTn!xE0978sVv}S_ldNLV7r{%@!4y zh|3NpzSbaY($$IFZ2;aR{z{1-S-{^b2w)ayl+i%nl_JhEiA@Br-~Fq|dfHgjH0Eow ziiyl41_#KNSAu<#K*0)JBY7N>4V=)ef$fKJu$^`Ul2h*saqarwFM~%-kjjAVRCefC4YLE-hbkbz`(X-U=YhaVh48O1 z24oJG&-9f9U=XnDwgYb~pt%C?l60Ym9$||o#(V%KS^9Db=hxrC%`dDq(75!d`!BEG zrRSrsLQO!#Xkj6ShWer5n;RgENtk#{kxb87KQ#t4(uU!HLurCQ3uFjW5**bOyV}8V zAgl@pRI?(P{RH0tRt+KnuwbB|7EUgH|MyIsM-n7~eO{r5f~`mboYZ(R8b&EJ0w0#5 zZGbSh`H+yth|LVAacV%B04HjI8ENDc^DhIStMMqiW(cRcS+v>xI52=L4h(HtVyllE30y|5is;PJ4u3w144bZnc7M|{0a z7R@6LR7oR)Xrj(RL!&~I0e!3DL}EsJdQesJ&iDLC=$E#le@Y$f4>yrZ4L1pL8CZNm zT-V;_0nudDg3|Os@?i^f?5EUBWQa ztPGu6=Ki)u1V;*M?ULWReW|nTB~iBCa`S2SinvM>2U|hGrGqlh4bWp)1H#Uuuvz08B4!HPP`n9AMchdu+e24Q}*P^;J(or80v@o2~sVQrIKTo~wAH^bjWF((t z?T7CE=35lPa(i;3>5XxCT=DSO(mXhJ&h$S?8+UH;rrmUXx%lN~D(a2mkFQ*44$L2Y zCPg~|`sK|u5035kcN}$Sx|ilBZb6#DGe2*5%^K`19KGWy%d(Wgd1%*w5N`7q>yFp1 zojsv54OO}gc6`m=#`adqW6swT_q1|8)KM8?=~3X{O66nNt)cS%T`O{P{+au>G+G$8 z`7*X=ff;wdM&iJAJ9h6h589uYwi?Io2p{D4z88nw3=+gVaJa|=c6am!eJ%rmFKFLE zodfB5F;zg)5U2V3o%td4a+J8k0Qp=eL;KfKdlrsFrL(e*?T9!|gCJ+?&b-?@q_<79 zgAIG&#(@^c){lkp+4VzK{(&JoYJJvkKR0ha&#_bQUYh33$seWZT?3`V#dP`;GEAFK zJ_0h)zgwQp!{+agZ#jMG%fH;cKCtuZ2Z||paSu7|OOO00%O0!nIt1@*0qV(^s$sZ6{ls zw@zQmpXfTzr?`T1SD8GXVl(G`gRk$|;d8E{b_k#@Dp3HQUTEYyK)|`Tv?cz^^p+eU z`rTuk~JOeZW{L;XZgI`iqt}Rk7)8y+RP!NTUsYW$f4AElCj*i_Y{_FVm zP+^e@OEmgG5qbrPI3FFWdKd46rEzrjOV&@F7iYj2N)wv$ZT&Rx)jZ-jRHm&w&*w*X{om4rG} zH1i-Srg?=0(Lu(d1pa=``ttTk&(PKuE>Ip|z#hle zu?@sPX^(M+Ln_H@5c<Bk1x zcIH`#f7(3s+dD#k8)-y9a6PU?0{PWFSo;geM8WSNa;y%Q2`dXBd4yY#AjyFLq+(QG z5uk8G%p;*Oc=u#+MfcFnr|cP*s45-JT(E_ zD0IsTdbVMpA;gSmU>LtH(zQ;7wzI0yu%KQc8U{2FfZts_{I;Ia0l)j3mTpH>C_xb; zylAr;z6w+;H~ikgkzPC;oc~w{X|eT7L5Cm zc3kMBDd5_Lq(;i^nzt@+94t%KP~T2B(FX7}JDZrMur3e&(bh)0ZAXV%^h~nm(PH!g zQ0Jl@$>~O*$7jmflAGwQcIFX72?9=A z1$RKP&H{vZE)z2lApZH5_O!vY0~9RD=H39~l8MyGuDxcUy_@0;mMH6kAHgmh^jEL< zI1e|l>$E3|T(hw7Q7SccZcJ}uC3THc#`{UO_cYuwo$OELhLc;pJ+85<>2VoxUYISw z9dgQWV+$J&LiMzfnm8!DD}YCV`*Xo(xq?ul5xo8__f5R7(xc7Ep^x`ibRQf2-8boT zzx#L4=YBwZd*=^0Yj|;k`u5Jh#i08E4-ZVbzs;cgVb`qf@K};StpVwHsZ=q-QfqKu2_Yu7U7Y0JWsYRwgWz0`f%gN{(~Xap zj)_v3WcCE|^nvQor{kJ*<}wY+BVKQu2Sf%}J5HT_tYl^@slZg|kdaOb>$HP8qh%10 zWVj}kS2#)KHEgIHSX^?xgtVCxT;`2CTWe1C{OntCgP_ny{FexcjJY3lGS~rq+qBrx z8*5=DH;N!kS;)Q@JbouFtL-!%g%JVL=qdmV?cF}m^oJ2Ef$5}hn=;kcu?sf~ggdi{ zFc~(om~*~Gau7mTh|o7B=Y9p@q{=X7-#!f<4FW43GlUZ1RfEcgI*eUd$>}=iV$FkK z(bW#nQokP@2ia;cH^T|sbVB+DK|T#^b@ejthJ$>o1rE+WM`Ka&;myn+R$CDke?-6( zR~+-}M!J$g5vrYN4o&zB<(Rx7E3l^$m|GB9rWvoPk3Vt~0!)_jB@nRsu7E7(ln}_< zCUCbB+mZuA2@c^lQ@-KpjypxOszeh!JujtyNJrfiDn@3&1~#S4O;*KTGf7tL0O-e% zjw)-&tAmCNbeYV_2Zx@ho#PTa6Q5%kP~wlulL|KE?ccI|Wn@~Z_!Zy60%ohPQ3uia ze!va|p7E1S$KPK|?LrHoTX_do2h5W!ph0JFCLNsUilhePNyvmkJ9JEJNcKYaB%4K| z+I-3g7tDsKkHC#mMAZ=0AnF&AxV9W+Paz&eDE+<> zW`ez@%O0Ib($wFql|Jrbfmy2M#***6SPPQwr!W&!L`8y693JGg({5ZFs)2WqBK{*H z8$1uNeRq{&&!@wlsf@bbOD@QxciYiu_N$H1($9~#>4US~236=KG{E*S~V zI~(#Y2Zr~3XAUSs`YJhDM=Tcyik>yRslsD4ZrjcMdC~<&4%l3n{_mVOv*cYb3bQWL za*!JC5}hz_Gxt^oicd4w+{MI#nicjac1VqMjV~~FFGI)}I+ttZVdLb98UP|8<=M@e zSYU?=DRCzl8+DPgBrd|@QTDHxa%;oXyuXvqxqD?kB#Qj|2Yw$*M+P7X%1(*~)(Zr< z=)JV95fk_9f=dKW7EZQcl6}HoGzQIcFg`-=(*&?#0e!R)rWb`#b#YS%B8Gw>>rqh- zf`bb7lD;``eB5!W7-nb2Rq2;pWqt48954VO;J#M~{zpd5SA6zANytF<&tv6z~V zdGIJ^l($X0D{STGKmE3MEgHNf$H1UT(T5N;txXc|)-Hre_&(QH(2Ah2kPJFxjJviu zwNxXc+Roy?e%OT_1||uUm_wLFy_rI)=0SKL1ZZd|hPo6;fU4oc-%q!9mw|z7O$Av4 ze~G$AmI-t)Td`r?DCDW{*~YUJr(N&3zR8D8!gd(w^=C{1Q4{hG&G(9*Wmlj%o_P`+=xwmL=7Q;_a3!>= zHwr3+wUPvT0&2sld5}F(8}8m#ad!)I@R@(Ty_|N^9b%KlstT{!AdN+X9aLd$X&|#z z!%(ht51I!9$D%_I$%2dd2}@Sn5Zo1Gt~)#{YPV+{cSdM3780VhSXRxd;p`Hux&-hC zYFk@i`)g>CTdTPU0afK;Y8wxKE<>uh191gD3+>tka^$(D<)9?!+ z1JuF}AY_bj+Xa1}EC;ue#Mof-LqmgvnzPpvZ7QG;CWI`JaKMBj0Lxby23=~6!{pfO zkQdw=<7MN>s<>R+Up0~GQjrqm;kOJLq%g+&^0qXwM>; zkt%hCFfi5i;))3%23gnC0Cj{wL^I2P?1SelPb*D>4>KykBol1R`SuCR0d}YHei!?M zOlMPJZrJ_4iM#Mx%C@S^@(mo|67FhrKL5?~!WzuxlPPL*Gi* z&aq9FyuyKI1&(&bl>5hF_HKZ!ouef?+Ox_zmXn-x%H4U%6a+ z%pJi^sL#23YeTbLx8{AKw#q&!9(03QcPJPenRl9NUz_cQyMo5?Kn=CBsbpv<_^#Ut zCT3rGJXmsnQXEus!NKJC^^gC1K5$Lc>A$8(cW;$T`N_@7f%NQ&@)G}}BpqBTm6vZV zw@)Wa4VKi@)x$ikA7Eml>24NZ>^9jSy?F9Pc3GTuvC*k69@94~zAR*I#x2c`GX8?w z5sxueeGyYfR%hMaOQU;Wxkpmt^kBLR7=3!$-B$@340Cm=qJ{Q1}nrRt*he-sjlhQu!74z~J5P5jRr z%~HOjlP)O$dG}7k240vh;pOj48;!P8vKsde>=>vC-(rKdyZegsk~TahlHjs`&Kpz3pz* zUP2^(V&DVr%~Wqmt=|ex+JV_JkiGHgU!$j2ZeE_g5R{vM+DS-9Ngnp*WBHcO?P+|J8Nlo_aBJl(cx$Ir|Os7-Itj+3g)Eu z%qTYPJmkK?Xl3F>_nA>_+RbWrfUS4leK2dfd)Iac&Cl&|Q@=7=dptGnSanCJ+ii-U znDx-AKOR|iWpH0-9Qz73FTSgUJGOnL8U&wnvo+k+FOQnHjjy;DBGzp>Zy$Ze z4b0uoK*n!p7!fif)>qx#gKE^>4T#VcXe&Bfl%AUgZ@BKBQ6QbWpBeqPNd4|{eccZX zpYDvARgB#@O*LrVcdm97y&!i7fEvGJ0cCW+N4l-tI)2gJ$<^*v*IsphatzczBQIc& zV_bY6_?(jf1WRD{C5zK-evyv1?(y4?dWQP5-*mh11pRgq7>|^mA%*b2KPYya7hT;t zf!nT$-K&E;*}CHb0^H;7Hl?UZIe1b9K;qml+F zeJg$xXBwyG6^{<$hCycoY{XxbUV@FPFv(8~NCVv_xEBg77!}S*18Wgb13%g(Kz(`;JSBq5# zP}U_OvfN3E5UQE*J=9KGa4yFs(pN^!co(~;^8f# z6t{8DOJ8I~ZS(f@oV@R)gq*aArq#LV2ee}2Eu@B91RyL9o#Z#7V0%6lgg zj$M~x)r#(fQc0Z=esb4!pn!*C9F1UW=yp^QY4kd*_>ht!v&BO{O2m(b9budZeXKkx zreKusiO@_-%!>ioyXXi9V;qGb18rtJxc0XXc|fB8@k$7Y4hAJ)DE^HS$3gyRc$e#O z@7)Y~R-}_sn;`Te~w;n z>(9ubMbhg}XY(%I%H}=7)<5NjctcX~vE=&4oVk8Tam0T-&$r#=i2vk+Zb8kFAEyQ1 zgqojtJ-PU2<@2t82=4ZJIH`ZFQAvaL=E>mVIOh}D4{hLX$i6926p9EOyDp>uggLff zjFz#;Wwe#y$${UF&wbnB+d{lonXUgU7*y}U13f~SuK<BkQw8R6lnqkiGFk*YOe z29IuzA>+^6&=5rV`+)n^w3P$bdRKqqt~B$$CRCkyJg+=xEQa}L{>+<=#msb0yWb^)O&M8 zq_M@I=3rH1l$0fctYiQD7Q;oIDx&pb38ke(dg<%zO8#T6;*n9nd-MNBk8olLlL&^x%jY2Pe`=Yno zM$V;lB|SOX?OjcK+J=gNJEF)WSk;I!&BLxmp)-vB68O zc#3Wnj3Dr2l_5urU`#su)B>xJ>#-GI6}fWSm30=bV^Y36jS`Hi^v&J zEp@{ABF0K4)}+_J@!f{8rewF*)5^It7!EWhIiObmp_x7w?9X=5te?92s%d4NBFn$xEl)0{2{NYmiiCDi_} z|8N-Y9NCdNH6z}2;JEv-leT3``&Z?ibN)esl5o*Luj#*&lA@TP)OGK0Pf%mmf1`8T z5Ayi|+Hyk^lAch`)1=iUd^>w4b%bv0&$!9vT*1y%q@Od5B%mN&q_e3V#I<+Wh3#3AT&A=?*cyKL z6K~Om?$$h{qeI)@g$J&=3gy8tfn6}`I`c)(u6&$hA{0!w`NKShB`|4Zzr{q=H65nU z7#AgG7n?kwgIl6Inmi(nIkrWYv&1F%#2khcN18^RV(H{U1ABnpnCr7P%Px}zO7F3* zfBc3AjeSS}Yv+g~ApzbZCWr%o?L*0Fdx5KKcjtL+IAWL+xrVB+T6V-uYd zirk_tzW)-+``SafqNB@T+IzEo5mIJMwW@+g4ezauTQ!cATfsP~uV9S_e8x4AH1-*w zX_NSdpQ&sj0U(t|#1x&iXH#0DX#`l(fmGGRjj4Z#Oo@gOxQ;X^#k}#uNAGY#G`^Of zfHsDCH8B-Na)`4)OT0_&QZD_(-h``A{I4`%0VLn<(XnEIPpL3#T+Qp#^Z*q#`jjt z&1Ere_pO?m-D|oMswf9HO}f&HeB(HbBgC8$CdPZ!%#7VytOYV)whf4(2YlZ}#Wh`U z>kP8O=jN59@|WoCIs=0}@nOi&*q9L5jZN7z0MySP|EJRFZ%w%^N42=MjuGtUHq0 zNY$S$Zny6ouVdWnb|4*->+VcQIQ2iGON})tW|1MRGQ1E8@V+6g$svLmzVf-_*ipfD zY686qkjh6?Cu=keXNj@_11vP`b#}P!F5g z9h~Y47*Y7R6Y0dEnH`UQkj$6c`6n!|=dj3_adB8zbw9206+h2zGGm-i!f5Df6kt%q(F@_0X%y=zN(o;3k&ja{6G>e_ z`mw>a1(YBsQNrUcT*nkGFA>N0E1=FR=#xm^HDneJla!Lcevy{P>a0nO%n=?QfoFD# z1yX8G9t&>QRe8iVra(IzN)z!qb_w&SY9j=8)apqfwU09lN$>FDrUb2v1q`gq%xD0U zGjS)GqoS+_vl-?fN+@uam^@uAu@}e33?*;{>eCz_L>t*g2HJeoc*aF9(}p$AU1bQS zt-9C^i-4^Xnj-Kbn2EM)7!ZG}$w2cL++Q2`#gAZ5vco1jYx+C+9c;AshMgI^IzGXV z4}T#2(tG*D{XfiYeuu33|_=!|7_}z+53G$Cpm9S~GFTkB<7;z2DwZqe=gC zif7}t-5FQLS@QI7C!FI`^SLYJHP-8Xd39THtH^vX$LQs7bxWpbZ56Gry891^d(HQp zwdUQC?~Gs0%5%H;7yLOg#YX9>)i{veVQo!kH*BK=Y)J*<25M=0FoZ(#3}G2RzAU8s zbd~e;DjzW1UvYPg{OF;LeRWnC^yz+*U85uQ{2q3Zk%?i_SJ?4&vc1}R*U8l5M|P|h zPkwX$5f_FNog@9cQ)L}Gmm9qr>c^RjU6g3&aE>wY8*-2en^EA~IxUF8LgG}i~s1>b|#N-av{I9G(<>>)k{gXpD{1nbphfW zq~`xpmA`C@Q$G(@RSw7eBQ? zz9!vKyZ~x?mP6aN

AD{3G)S$Cejc4m8KI_>+%*bZf3gCq@9?9(^y(<*g?#oA^F+ zla1!U-!KplhUuP6NU;#+sM*Fzz$fx2pK?G(QN&((Qy=i(>i+4EylQj7Jm3F=Jl(-x z=s)hC{9mU>$sy!X9kW%;*mUt*smnU62+KGN4ukad*#PwaC0GH@RL z3}plfnfxmyVeA&2CD!`j=zD_H#2KZtJ24~9vZr>YOjO^yLd^o?l8ff$b)xh~g&!2{ zo5b^k-2b6ADm~Y-ry_?uUq6`fgp?di@30LIpUoRZ`Pk-;BGWk?Wn9wlKIGz3A~0oGI>w# z`rq8{kzN4O@&w(+jW z>zun3V2S}lB8YYVJpo8)28T$AdA57W)KXo7C0MawXbJtZ1=I<|X+YZdH@`%1y_cwojj8bWahcajZ^ zw-XFRKfqj$G-)?&XgETZfv2G^q`6tdL921WJ`m z&{y@U0b?w{-+AhsL8}WuU(748BJ_I=GemcyIfhm!Kgr(u0ya0HspdGn>k44z?`%cU zPq(&WZ{C;Q-@gBMseW`3g&1)LX4TwXqfaK)joijs7gP%~5YS0CaaH2uTX85U7a<2$ zn0tZk#>ac~<^Vxu!Qq_qr(C|oR?ziv1-&74xk%heZa9XaC)(3&CQxJt-5jsnC z5y2k|w(Z>A0krZGLP#d(*uTF1!|2tldAw&3j(I&%pneogi^O%`1 zn&VsY13D0OmF1@>eH#g{U_6X0sS?FH>X?52wlG-0ei|Nwa9$iaX<`BYTqxtp5s_n`B?Zi?VdxI>P?gCkP42`Hk^WLb3V`f8L zf8-s78GMs5!h|h@_io}4g>NX9H-MT*<6*}1Ss%?x?TZ!QO)z6o!LZe9d#}r?SLsq{ zRta`etBjN8_~0;?o8LzV;Ghq>zWsJYEdDThFZE&oVcbSC{>*qZ%gD5nTBL{_#h}P5 z%F!aq3Rzfpp7fzYa93=t&#(B;q9)sXnrKkU-tXHh|3QUsBPa9?UWEBQMh4bT+$C|A zlXKw$j2OFPek5#;*Y{p$U!H11%^8L|6lP_JADA(F4-DjYg#y}E(slfbk+myWzhJYY zDSi7ia|8-Ng13&s4$~q)YPFRhQVV)KD{BOxuy9Y>2I%biju!YGYGWxv3$Ool9sNs- zJ`XWsPJOgivA+MQJ@paAVebt8*@}qk(DKYr7a_c!yTwo;seEHe#HCv$5r3L}9!n-w z{&h}$RS5N%LZ~;?R|R8l2)@ogOP{z^ig4d2+^mAJUwUq2oeQ6NZe+c*;+Z#;R?PkE z0*%+%k4r2595B3oHg72N_;ZRPUO&9k4V3hN@j`&Em_wffUcdvLXH5ABnhNy;l*7S- z=n6#*XLK6Ps1i(`{Tg~s^f5m^TZ|xbjI`XdW}WaHtbVWSLR+i;SMpHxG58==8EM@? z(yWIj|5fAG%j$JJ{wayY>8uMS;4`Q zBW!Fyh)oaV-NFe*bxw+ESX!T=E~^FMMXWFl9UdxmXcs2mVC?&w zkvNW$?-01Tt7gZKBWV|08JmE@Z)%x@E|Q^PJAuMzn;<8uv`xDv8LGVpprHaO@{uB? zP7h6Nn9Zj_zY?c;3kq_V2c(NbNwB6;w>UD-%HceSROzZeJnWsa8xl%CDwjea2ZRye zAu?`i*KYh*1PXx@>vRR%O33aUrn72rsH0qEI^RgBcc94?9%{R}` zG=Rc*=gE(G(S3Tf7X13i7(nlcEcBZeUF^kPqlOtYv+hy z>3NHfv}rF5o98&UZT_-L!@PTMfuzFNjz7V=7C~SJfFdrS>o7$H=CsG5UoMbY8u+$}`mM;Fc^tkT zKq!M~3X>Wr7y~R$qFyS*VY(v?Z9AJqDjg|_)2=o{urm>gLLv(=2to2Sp?L}{1w89V zb>E?quq$CrV&ddth=K1u^u%p$5V=qtV7k>H+H6x}N~~d1R1Msw&!EVW)oB2kc1$AU zwjabr8zc=FSBOoXVJNo zqaTGIfs}C#unWmpI3k*~(SzW!W_!;rZN#xW&{Q1p<~6HRKpWw>Du{A(oD`e*E3yf5 z2lZok4fL4=1lv{tdSW_g;5wm3Mt`>h+|KEDpTs!d(Z}|wiyTn6%9kj^CN*veUd=Iq9xN&02Vjv|d^5TCx>P`|P;&Ijmre zrZ45hw>YcI&Luu)eFp69iLQN&evKU?#|ty#xgnmh{};(YS!tcNO5faZAe=D|g}`nj z=U|aDEfJY9j`RWy83%V2YrFUC;9C${ibwb#?SKL6U9clKIB`77WLq+0h)2i{>A-~I zQ>&wXycN8iH;-^NJ7vGbU$gj3&uC9_x_i!Vi(zYpAGeav<0hf7Z<`#FnL{-B!4$sv z94$Ee2ak~}+wH~A=2J7~pV;ETy!!N3K9Y>X!^O#V28)G+pOv&Bxva@2L;U+~r!apPM3X~=z*TJ~!IaPeb1?*pD>$9DGH4z_Vv zNdK~pQ(DY-ceqed(%80fpoV>0UiP2bspZbvdem4lo!9P8FCdu>z7RC+kdh&R6F;fa zd<|RxPF)c&jUfS9{Zr@N0uO)`G9;517FcS$vH%3Lz`P)in+9TO%Z0S&Kr!b+MUJ%k z3!}iP@q;cPkw*IaTd`wlRB=Pl5A6$VG^1%}Y^JN{{2y9~d6CjB#8intN?wr$hr;@iDX$dBJKJIlxq1I^DtBf!{N$;qr3#=J=OW_vG1DJI-18{FsdJBU9 z*JgIqg(1c$B2CM!@{T}wRO?jR<)~`|f)@&Qu*cuc%h1-z}-={5R`tY z9*N7vuX{aEN&KFt>H_}9N)W|@} zUojDds4A89ktuGpN5X0ap0O35sR@_a9m9X|vjdygh0w!{dy2r^;{|@LpD=&pT zE_sqIQdCr`Nl2EmC=Nq221OkmqtT=C-Byb5Rxpqm;X?(xh}0G+gb_y|uRV0P76nj9 zVW>gui6iRxl$g3KFAlR4b7KI<3WIJ27-4i7XMi0bkoZ*LiAtXi`i4RQjDoZ^UEN!v z{W;r4d_Up#5P14xt$Xj+$A5E0ar!YM@>7WT-3 z(f=_+Xqp3M0elAJ0%MYjK~A8)1omj&9wq~I7DaHtu}g-8Q^QuU(7@+nC=F~ldSTr+ z@-``NncMss$cdaDcqdQ}=s(JC#BLBRFm%JS`6|F1bd0dQ6C!9=BLewbmco=~iA@2Y zwEue1H7-{4V{~9{cnU<5Sa#-7Y_tJ&BOC)5QouK% z86ty8c6t_26_g@u!D)y)5hWs0v0SMGVCacZU$7jbkxtvl6U=P5GcX`Rg56qwhQp45 zfl4q=B%M_{@I>svf;}a(5PEh>42f})3uwA#48(y=$V4+Q@vX+i$VdWX*mkl_BC}Qt zI$gp>j?Yk$&7-Ugkr^y29L4PsDeFRL zgv%KSva&I4$U;rAO^rFbVLS=OqOR3I{&Ors3gC` zBJzx(g0@GlkWmA&J4^_zX*nt&{(sb*hk4Sd*S$7wbkj)dF1(j8&ovP_u-CB0IPme{ zaPlEgV~pc#2S;ZaZLn#{8h&Noj-sRupY!EV>L&EfhiHLD354M?@!Co*Xolo;AtH&; z81u&}4I|hxM-~9zxe1(A^1)i1uoQPS-s}67O?0H>0zsD|L6){)P;(u}0u2yw#5lL_GGuUOU6 z_4_}eh1vKFh3~wTEn`0sLp~r4kSu|?<2K5L?bUHZb;4(fL@BuiI*a%+#NY(-1W?GC z8r6tBqC<0r2!P#~a~CmZVv4=>KS#*V=wkZPkZ_%FMGSWjiBc3@qtCeW8*jp_<{3QN zVcR32X~AUSD_DBctUK5;2B}U;haul8y;vnF$OuCd&`#oKZ3a$U;ySTwcU;jx0GX;ztwpH987KsT zTU^1p0lfx*seY_vQ1nnl&g9G-pHa7aN<=H@%HWyNST>sF3l#IyEIRXPrqO;Jp-4F7 zcCtqUT_Y0dsE(e~7iiWEk(u6*_y}}N=fY}mf!Gi0*C5tGEJVSVm}rL>I6IKwtl&B-N6d2v z<2k^x{46NySjBVw$dD`<3lMztVgrWlz=?p_f~EgyC=?N!Mzji)uA$GUqvBePK#e-^ zMD??M?bm-vTR~4lo45g|%OFP@ev)2%ME4Agjmt2tDci%Gsi(dpTS!bE*dz1BA($Dp=rMV;UjN)jA1u0s19AcmSkoe{ST2X z9MwpRb#jQ?K3M@I4a%o2Z`cx}rezH?5(TYcR|vssdzdKAyWb(xejo=RGU9&DK;exJ zAW6X?+yF2k4F)5A)uXw zLlIU?b_}1SqY)l{KK|+O>XM$mO8r0K)ZQ9?e%DbEEJmZNeS@pR{q6}-4+jsd24F@0b1aN=jY#^{gC@X zX1Pc3{G6*FxV(D#u_bb@fXLU>>Sxl;0@zxCvjX3Rb*RqR7Z`m4f#x~x)FtGCh_JA$ z-Fg$J4CADzk$nJV2p;JR6^-wVep-=N7;yGpMSH~E}Zt(-r?vvqNwERbzMT<39qN`CJ7?K;Dx`~;UIerb0vf+?r<;(zxjI$ z@|MPMo@G(*D?HGI#t;$M^QTy@ws;<7FR38kVavYY;yDIE!XB~A+1F~BupX9^;Uh() zVJjx_{0FjdciufJ@I3h&_o{c>f8yq9-SZ0cO}u~LYIwMBA`1%Dns|S4mnz+uoIC`r zVQo>Wj4>p|LWh{cla7Osh@XJ;u>nDwDDH|ksIIh&>oD*qzcMx#yw&}c5E-pXtM;8m z^K7AtBxOk4T9bd3MP~F&^?P(Tgh5|hoAt+@Ur3*r8E@x4f+SHbg(oETUhnHiBJ~me ztw2}r`{;*MJ~h;Z-^+ZO9k=%c3y+|39rS8DAFGDBr{K4@DM|(&?1#qd;B$;!o*sWc zvS%qank}l@d`JNY<@pEb`XDC4p2$z#=|2U%(E`*}>_ig>SV-ezLDHJN^s2d-4*(0V z(0qVY=g*jprJd`%5X!S>icgqPE?hDf%I~z{6@Zu0ByM9$Xi0Nd<@lM*S%N<}|4E4LTG*Rr_x>}PFEUm=vk3ebwIFXh zSYX%sQU}@o_UQOD7{!MeVdKwdNS%VAp2O8ZvA4KQ;Ux|Xx4?e6h~pTtyo@X90e=$! zb~{t!fdW0bB_#GLu836@Q_0>N$pap;laGOA4Y5x341L(fPAS{W=J+AHtpKJN1AA?4 zT2G$N89;OJpe!e>zM46U@fs}j%4L;!TY04(UT%xn?sMd?z6?sL6n=$cW<+0xh;aR; zJcsUb9)heBp|2_=f(ehh+ptwKnqNIZ4%qrnjHw?r)hcaZn@NseGK<098~tHBZdg=r604B->maJweWIU;ZAhwnFWnT{cce8=RcHAAH<3N0+ z3NcdVZg`6eDybWVM>I5d&cIUw=PH&NBREZlqcXL!v6rpo;NM-+Ko3(_7S;Wi=phXE z8f^`H{Y>GH?C~}PPalEYP@)hn@`njBfe{|XwmN{hyHQ@#NR2Na{50rMY&YH=4B%E` zE#Cip%f?PF(-h6L%)ALVwb+YkUQs%DpGw*K4EhJ$S~T8S8?6DqdG{g|s@SEZybLYx zveLai<1VFfAv+Muc`?AzW&axv2cICdaIDSvS5@#3_Wny@Qp-K}1c15gf5wfQ=bYIGx@f@h_ zLIEw-k6?qg-g85vjNq?8hb}+o;*`*&xgHFme#{OvA&~d8_r}+@qWO=?r%kNTif2** zV;45~?h>--ufd^2bpjtD++>C!-x^EiZhe_L<54*b(N$pshG_HLNoy7)T);y`S5HJ& znuh8#0IHZ8KmZlwh9!dAtm5I3vsi$D(3}XM0>u0Pt?YgN&4Haqg#eZV(YY9)SN?tQ zS1(J*O|_T99_S^!Mfki~NP4%`cXx@T-k&^{W`fMKsYMWs21JE^9DK8}R6rtgkH*L- zN5jW*k60B0y6qC1x5}qkv0RDj&2Az@FD{~J8-hxQpliHPC(8&V zlkc@d1NMz%h}surfaQG5N*N+xL=41;v(&p1HJae}k>=3Y|GjUj4N+xt9Ar#p5Y~q? z-!RCmKLroojzDvnk|;KqL6P^+pgkE`ijSZ?<~^{K81|(0Y;aryN!p$9iU1CV1sy5& z=_+~&^od}YmV-nFBv{91&$_lY@M%SSM%#wgz%R9zt?TA!n^FN)SjlaJIIG+Gf3gmZX z-|fPE6VskS;n$T7Zw*jW1W4Uw0N?6WZT%URJIJCYVa4H}^PC_HL{=E~^u6_3fw>|clwrIl2f-jq1frUc{8SR;%JQ^ug{6o#f zWlpyj26Z-rooz^^Qn3p>F~MFzY#j{pUXnb64S~CMDU_6*i!7Q8%GSgk!QGTvA@jqK=$dAI8ChD*NAXT6cmk(h?z?gf((;l3Pw57 z&tut|2+N2-4(j50eMT4mt!IHCGTz%oWZ$8ftU!M7`e#vmBu>f(!~m<{V2(5v2!ZXJ z12u#y#(@jZJQv&2yHZ#c7cPZXEW)BPiUmc|;JknCkw(`wn{%eTblieF2TJ7h8i}d} zjgQGuL!MdK-AD{bW7jHZj(1Qsn?Q~a!D=m9{FXY4fk)H{a~c+1zxqdjn{^B0f-HyrJ)k&z!VHAt%@)?gc(u z+>+LQT$V*PE(tJKh@$Q?)=1lB|x&fa0c+bh6u<*X!o zhx?%7MEzmTvu{V$eb{{+@jQ1>#`4tg5O)rQqH|-Q*{-!MA!+XNTDAOKa_U`wO(GyjjZEcp3 z3eu^Eoo6|%e+L8Ri7W8zGx1-6py83iE21twBgk6m+~%e}!sd|QCO?PXMj-XwMz}qS zf~{Y|E(|Wn3$AHOikV+>M=w>r8C_kiDLu-RI7W6rd36|59a|w*B&4dR0DY;@!0_fdO#n0L{rDORLm*My^&Z1+n&2wtX{#}x!&I1! zjN_lvdYg?WUA^Eb=TXC;1TY{TW^a_;1TI@!aX~Fc^-kC$k(8T~ zLsp|_Wf=80NbF@9vL3Jitj++(3qBkQsyRIx5`#7GP&jL8i9^`;7K#~_`U+03*@a@l z7$lMY;zNdGm|kEANB1sRGpHYnMHwbouV|x6CP2{$FjC|h0+3A#Gvn4nA^@aeyV^Vp zs{(~BG#`x#(V~^NF)`U|8BD=Wje?Sl%5{FmM^D*guh9T$)(|R1up`bL!gcok4Vw*E z7*s#y=?|m8hVf*~)9F;mJe@iIAzvG-OT@R3{SI&iIUweEiB$6{zzH^)r;!o6}j}Rm5qUJBx3n<~AB=xRfy$w6^MNq=TWZMZ&cmDbRMG)xjmxBGes* zPbQJ;8L)^QD!?uq=j;ctNa+|>T9Gss30My@uO((IEg6fRu|qmZtn5oDwrWV9mN^%Ze*DkUwLSId&xj;n0 zEFl8~#u%p5lCdW7BPeRapX8Oy^%o(!?JoDbvx-yi zvN5&;KaM5N1IfrzJ z02T+1j`&|g$70u!^$;hqkDx3j_8DsQXccztFW&B9ziWaS4T;T}b`LfKzenxz)?)=) z!k4;-LbNq}3M%!*5y3YEokeZ})T}U%8lj=F&Xo{6Q!+8t#C11~5rgb<87oCb165B9 ztXnx9VLiXpgBx5CoGl3qXaEx})N4z!!rZ&T^$8De}*n+toE2kESb;I9x83=VD>FQX} zktTuABmQ}>)l=vyk>b(WINuDz6Ft=BNkj;=i!KHZR`N(wy%_EXgxPK$Rh2=(poWA2 zXt&Y%rzE-tXfx!IXbT&Y0xnu(USzOfJyw7NU;@ItjSJ8RZhZSg!(sBP*dewrpKs;) z?O{K=!``vE*?W)m7yZ@#+n4%jx3^C6_kSyOoebWMGL?B&+s=2LD%1wxgoMyK7Mk-e z-|n*FuG6UiQK8gX+dpDe&RXoMJj>^@+ezngcp2K|nYtv~3E4_hm&3CvLYcJ>`6E4F zuZiZR)%mw?celGGx`fp=b=F;^1IU<|@}avRyMlTtGhG@z>538jhK$N|lgj)sOFm7? zuZA_5tA#Vfg)lP>LpQ*j($DwM!NY^A5B&KfF2w(4ao6W)x{w>#`LF*q`Hu%uN9>^3 z-^-4;`CZ!xc`NOGg#AtUT9Utw<;@)?wL9}x<}@i@X?E@6x%uoq0#3Qt)k|ifIB>E! zFqg#Yo&8dZe9(Fo@rGtEud%0D_yld%>zxA3n?v1ewtIZI1L0-!!0HPH_CSb8DH$Ff zt=C7-K@+^gx^EG4nyBUIxnWo(BP`5YBc&jQ>^4~W>^|ui2anMtF0L5?*`BjX=d7>$ zH@LNf?0Sj){r@-#Cfj=jNVQr(kN!*~al_~b;S z-mG%Pzw({f;P^k>^&00$Tzx-1&X1?=`X-V|`Jes!>?>;Xnvec|=C+5+$W?t38{+Q% z!Q-}hM+=~+bp`~Bjx&0qskT0;w(qrW0?a@AJ@(sVG2eQyuIS$3O0XuN$BaT*WFYMgC|Ai?({P-8HL=f3hT@{X*& zr*_x=-U!Gwy)6xG-#dRh-(NiczI#^q`S+UI{U$P7Kl*0qP{p_j(u8ZXk#tN?$QpG- zg~ZT|eyrGfpKpVN2Futd$gkN?n*et|z$QC!hMABbm7>62uoeo(3g;2xmuBB`o+u4v zQ+Im6`%teFOwHV9id=Zs(#ZNJlVzljLtj~#(Kpkc1%~zhM01sB$9egk zff8_@5%{#HYf$`Q8yD=V^H-^5U|kgJ+hmZ%a#TWnjDp$*2mzv)0y)Eh11fwF8|2_t@2;MCGM=hY zZTD+dAA)j0ad$O>>auJv119p_uqM(vY9q#+E)h9)5-U7n;v&GU!&r^L){ooIxC}Q8 zqR|)d;(Y=La&+9kwv->6c2V3lFmoubi|UN~zc;O&pZqOtGn#$utvQC=XW(ZDB7+QY zajQQTfv7wvv{rv8;zI55l)2|t6ZNMS7qE}O%h=U9HpI`zp5gl|5VV@#tB0_iU>}7# z2QSyAGf~(ZQ>IH9g%GiXwk9k4SPsQMmsP0?EqA1^FQz$=Iq#u@J@jARg29V2v+sNV zUC?q*AN&Ibq)Erl{7#j66MNMb%0# z?O$T!54gR&2!j=Zc@8N$9Exv|9k9pk(#O_;U$;zc88@xOP*hTy>LN7w1K;Cv%VcoFq1W!!+q+{M- zV6C<&LDU&>kQmOEXQ36|Pz)SBC`-s5yq8#HIE-DYBcn{c2bk6g^?-Q+evLnYY!#zz z)jl4<@P%4+rLW6o#s`DkjX!>Is%7MmVc?>8HS;Y7b-tVn1 znXn4lzA=MWZvID+@COd7FdgjF2Brgn4ZA%fjWTQ=Y*$#X;~*I7n?&I1TB33q)=V^m zB0N|DNH$0ws>%CW*ZOyao z$Tyt~Au*jXu7H;|sC>jSrU4HJjO-eld4k$VPb7|5;)Vgb?u+XaDQr`B;tij}6rAv*wwa7DyeNKt@?*-qZ>?yzXdD5VehNLDP^BX#&l zDDTCN(EpsyUIb_V&qsNdKyG8==SVY)ag!BI%5M?9Qt z_i*e-O^D1|ex*n{)JMTwH_cF!aF~?a2hMf!s73F9fkaUOAOmt+X4;Qpi|Sn|kQ1JB z(>f&MhEtQ#s5$RirL=+ah^0^jF-L|pgoF!#Z-I6oo(Lcf;Uk7$c|tsAmyJBUSub89 z*gheK7032A$S1%M7U)dq7qJvIjI z?DHsZgAFG5QPa!`9bqH$qw}WYpDyMk6_K8-Y-EwPVvSX%gy+_LZ`w?5um@^P!_D3f z_q<`Y!VnkFB-NYJJTiP0NAH9Z)hEMCjG{%6qi3WH2h(y8B&NUmkHHFu$3MlI63Hus-pd7oN0yWY)7>RY z;bj{kXLz$vQHsN+LC~FD{vh@!cX}(BQ4dyzA@9->w>hCiOUrWxUm$HrnUaeT%Q43g zjVnT7rbv!gI=F29;@`am4oe|*(iE@y^fF%7mN`xN?~=JZ`jnj=AK20}GS4A7mBQVL zUO`zlE&%0&q_wHkb1&mb_mbbc5BbxE7pBP(!bQH9?1wNIS5sgkg@Q}m!hMUY#YWwy zxSYYz`~zmchuCMZ;jB)wMLy*Zxv)-ysGrW9bD_6sh6P*9oPz@7YDl|-qj`7afEXo_ zaV>LUXgIjS&Q%Y5t2bwrz@`%|j+LAx3>>%hgbJ?E|_wxI}X%EmbOS zPV3Lo!7iD&j~Yz@PZI8^F`}n0^8+eF98wkg17r{Duy6W1-GQ*+@_Tt{r<C!?apP?m659!JX^;0&?&;m5Dj*%VQ4^eh|4=lX6^gr5_ZR6P(Aj{LU{vY zaD}~_UBBo5z-;4s?-`iokP|^PXR4}hh&wn;ib`yY3?a?ZfbZiJokDY<@LofNAY~v8 z^ak>@_yB6sIkk{^F)s!iMQeaaVf9x*MiVuxQIivYhTE()>Jm|v^{nDq7ewmCzm7kE zAPng<&EG~D$2YG9n>jkIi2|UT+jTj#1^v9^$2^-F(hKz@#vsjZ(2y`Wlxr|yR@!rK zr#xxcs3Q>s44=7T<#f_F4n1Z?5VS1_w4tb@>9d+Jlr zBl^$4^6~S!ZmV)9z5() zOwS2lN8rckWBSL8#|3;fDF6&n+0WX*JRM?V)FrFDi<-Qvy}ZbJV9^+wrzSz_gb-k= zt^$}Pb8>ZffqJ(Ea-ws@##9(!Hq=>5X9=ZJy)CJ_ltEh4epY`+WNZ$q0}Z;tj3Zi#Dq>*>*a(G_Kcx58Ix!s2i8}?<4pHr z*n0J*s| zc9$9AXbM2J5eg3s+3D%J?;+%cEN(YH=vvwM6m#a$9U|!Y;NJXamPY~zidn$0h77V& ziRRpn*Z>%eQRU20h@ACa!@Gc@6Brx`sz;hBH^+KG1V=Ha>B)`Gjq{(t9BiJ(&PV~m znAj$AD#V})4bz$(Y#@R~HXA5!6a?82(`N!oXX3nsfY%QT{F**Ve7v)ClIzUfm~6;+U#Wn zt7lX7^eIMA=XMg^fHs&}skrEty`Ztg;@Ej<9|7g_Zo{ajpr@W8aY7AaMk>JB!O7Sh z5kiUkj=r!0N3}y@j_(>kg>V4enKky6%A2sR+6a-1WTv&|kS<@+OK_%s& ztq*NRwF@ldkmP9;Taa~|dP#S^4Gn7GqPG~@Q4Aqe5HO1c{wF7A0mHQFH9_XiUTa&N$A6Pp;SsK;`$n=a}7&?p#aH%Mnav}ho4V8MgPLB(1D zT`oed4ZUFqfsVF5v`reOJt20WBd)!VDJFlKKmf zmT5YPv5SQS%5+3fR6;wxn51P#$t7n=j#IbStFhq10xc>cDJhYY^ej?xqom2jlHHus zewRp=dGF(1b1|hjuWr*O?>kF578X#1>w9l)k=)tY-^~2xH^2GK zcYZs+bDL+_5!RN~el$04jCH^RcelPev&3x#hGY{cB)j{KRly%pX&Lf+?--drqg68 zRk!t*$^HVq@YwE@he|Vw{fj!DZ&&k!38qVZtJ*>aT zM@M00|HQ;WZVyHuZ+kv`_ybR#!Y=A)__VqgTid(3SenG=I>V{1FPf&|;6r|%z1Msm zd!**s=Z~^Gy3El7$)0eTUc`pHlReM^5b1Whhi%gLS{u(@ye>Mh0X9cUQ=5fTYZQlV zI=K>X+Q}r4SM|=5oE5qN(MAWgWdaj+XE?pRxqKQS(R&N~@ZQrZzHve@9(7w%)^f-21-L+N z_dD5llF0=v_M*GVT2;W=g7*ME{8EA7Tma#n8onLhT9YlqWG3;&sPxd!67Uu6uaIUm z`}-}CG9obHJN5kt`VI%?A5_eXIs#ah{|T*qP<(X_EcHgM@3RX=*B&QwG=V5CC&SZe zoPsDkrUxJ-+aA*02eteF&WwzNr-^%CU_p(#INlK8u-(pa`l;RhQ=Fy=hgmo>hG|)I z=VJmALI4#*xbz;{2d6AG*E`+uvQsGFb8R~|oe+RExah3tSAZ)Wg!3iIz0HyU$|Jy* zVgUuzK!gp9V9eiAk zjTT-~1=9WrwD~+%f_W>QXy3Yc#AMDD=R&I6uG>eGAFwVjPUioXb%p`>}~=oZixdm(GLRWO^g+O*v{t!Sbj-s!N>D?eL5Th#GOYc9U(xd z^l4(=(=R-S321;vGYR402;Xcfy==X|?;}g`xirCLW_)3mG+mEZDGYso}&p&f;mJi2$zQ0FmE4WPj<2HAM_R;lQx;f-P*(I0Ni8Y zih19+Im{YHGbee1=rh8&@v2@rd#dpJ?IjY3Os8IU;CiYBJjYw?cC1Bf;Vz0}6wwFm z35+EIgKyZ(x%`4@9_1@ue!qUx#RSeu)kGBVk1xS^ClPX3N&O+^bd@aM7B4caC z(U&g~8Y42?OA86+==!Y$h})#*-k}%4VvY>}NjMq<^_8Xc788z@Gh`Uf!h;*TkK%j? zxZDEg2iHTvggCBL#0SSdKuUNoKdlzF!9RD(&ZZ-umlfDxFq8UN}OWKFE9Yed$5&-eV6{@fY*c>VBl0%1Ck7j zx&WM7$qfK@)&>UpD(K~c4d3E>0J78ajYd>^H6kRW8BV}h90f8vSn?#lbn{IaN~Rzb zB-7syV;Dv@4%q;I$JFjA?GQdFehCLTF~`L}U58huz)N%6a@2WY&^~j#a2#AM*e~43 zw+zdO4z*>tprg;=H{Q{AJc-Q#^HOW;s#Kqi&`YXtm^NW*=8o|RNOLM} zTFcG=OgHIXa%u_1K2Kq?-4h}lTp1WGoL+Bj`r2%Z4tLsO;nVk-G5||8e!-D%!QMF< zxUVdQR+mN`?AT<$GS!^Mo!$bV+SxZA#=*P)b_hPRK?eN;v=_B> zxQX34xqR4aN2Is-ZtXPeC1{JaEOWO_jA#HkVb^3FSk`c$UNr*UUOtTTpS6ACK-ts6 z=*6Jip|>5|0PkOXU^c70VCjelHOXP2OKU7CG|im9)dD>Q0g@jp&ck5?JLAeq5<}>i zF3sLPp{bwA#$jf;Yxc#7{T28|hs@Ke$;ZMtM#6P+W#v?FNiMVnLIIowg73SV6&$mW zrUWHYZVwnztCQB8HWzkQtTZS5btUXZ#vOTK)pMD_bhCn(lzl3~Y)UHOu6m2ElpST( z#ae(2Icl8dM`x%#0a8% z)@dBO5Dmg(F$mktXvfgwGJ-{gbl_!ek1|tDDnOeRvuNHZ*=wwg7e8@pbczY>UhA|zhQPdQS{$C0 z9TJ~r5d-j*mb@1r^gPZG7}?iJ)$m+bYgY@L$JeY1UpA#?$!@?;VV*iG#q5*06Zt+jL^`o}!&i_!=<%aR2eFbPw|9;^9P3=KpV(!N5J9rObRveGcXF_{+l^%OMB@a%fX>_I643z zcJnlazX?7Y1$rnx@C1;d6lLz<+e4$z5#0?;#6H}K0o+u~zVlyx0u(3IrE@ILG&}UF zCdacCW?CBR#9fRz9bc!%xYK&;-#Dyabs+(fPr(v5aO58wZT$fpfS`%f zQrrw?lsT><2F{QZlHE8rPxH-6X2c9tMoOXMv}ME^g%@tfU`!rz;Gl-J_w~Ak%>nH( zIsL7huN%M#EbxJb&Wi)>QdTjbN6dEM?c;{Nfv__0zjG|NFTaE%I#rg^QCXdUm$B}I zuzZ`0#q0ofJ9ZTGS%Yra{8>1K-q?EzA+7@m7!nZYEf7pWseA-GY&d|pf}e5XP9=)h z zVxWj+tWpf9#ef!3l{k9Knb6ziQ&{FRDWgc-0>p5{;hXb;VsI#5RBS;9<6_~f%O+GT z;FZxyeYGpEXWY%q;}o+r*fM~5e>U%gKJB!^4LQHv$vf*?!uYF% z)yJpJ;$&+6EDncL z8o@W|uA!Sa&{f-L$Qe7BaY#2X3uzYXR(Kx9CjpUE=GCIi>`e?Y6cWy`h4ZFQBphpo zC9MFHcvKIxF?!H;_i(#6g>F5r-p*_r!1L$ztenP~j|M&*hihXVFBA#TFiGm-;5~$oA=FU79plWA zD~yGcH1KjHGmyOG8{>oRFvYIoO*K3W{ce zT}76r0Cg!m`Xo4h!PDH#jf`*>Jq?#l^L_dCd1=3t>k-O>J0DFb(L!vuB%a0gm5u4GU@t3Z%$|EeON%?pnqpZiN=SrqT5n0+2 zjBuoUD6c9RB_kIDCI+P;4WiJgT&M}V8+cVPQ$i$DU}Y#ZE*BjnaNU&b?G{`>1JY2* zwUEugdC7nz*&~;3#77?hl;G(r0HjGhAD4#+{t7plQs&dZ0?;Zmsn|s&PEaU-X9TLT zsBPXb%LWmVx(L2u8zlssM=B~TqZDlvNnt_tz_HZGBMNs#4_eq?2m0*h@9B`6s7lAkIX)oTW(noI95fXb~=OG%G=8yL@sgV7k}0H37+^b^NNJ^ z?t3>2|NbZVm?)S2nDHJ@FRN->Q)f zX5di%-UA$o!T~*VDT`e&yQBsyAh&-5EIpKmPjeEWD@D1T9%+@OZ18&(i7^KcZ3<{M z#KcqG(i4F=PrFaK@Wu?HLQvHxjBxaWrH@E_y}RH(nwKoRh&k4K7-87oY_)kn;@RMf zJ0Qkzz?JAdr{7lu)+fYHuxY}At%}fiPLNru7kDC^M#!@jHvhTPqTtz$zCf3=q2zN_o(%4tMWPt`J(oXk+7nmMr*M$OJ zAzrv%Xr2rDGgct3JmtPAGGIwr2^ND-Y`ziPEDE1!1N}6?&^_4CLCurFvXTghURR;e zB!lTz9Evd;gyH}jgbETpi!Vs<2F@-)dMKEeGB}jOBUM!NjR7g26mMknqFZ(@>p|p1 zapGP^9*y+ z0mm;fvcMozrVZ7~=nz|P_PHW89dyU|I|5idTp(PT&PsnSN3`CM8 z2oj1~Z{Y@GQR>u(?r2v|sDxtJ^fSmytK{#KeD6>Q$<0x2=Ag3x;sX~9FcceDK znDuT2oCv-BSNWan(uj#Q<%qp~<8J#EuG_oae3$!TrMJt)cAA4v(H(U;GnSBU%r#H* zgV`l~UGyO1`iI?5@6fmOzWT3vC9tXDW*;8M(mwcIhdhgq3i9U(Vqs1vG)h)kw|w?; zwf-;r^rIUuopRS$*3S3p)#9s{yvl0Z&R10s3qG1fh(zIaY~?fbTD?T@S=Ej8^T;~ zoE)*&Y|I|CLa$i%Y4`clZs_#5hMf#IKG)m=cw8fhAZ9Kbx!2(d+bg{FQHviOsjQjLe#Ls=!1WNL zMlQEHlke7hxbVy6)tRn(=c$k@o(c_6Lvdkm>WVDC=1=d)yDOi&pofp0uS~+7sf}`6Hz^X5umqnT~)5D-nfpRf1<&NWnWziDE{s9 zS0z&Q0PlKA^u0vXxVFX8bLy`SPJAzGoxjk!8Xh|65?>*B^OtY@W}WwIlTevz0l`ui zHLR`Ux^Fes%jgt;7r3HVYP$LLTm5XUt(`~_m8q^G6uw|Y&FjzI`tICSpVGUjqMvW*dBNSHnw5+P}OpK?m3Tf+>ly=qm*Ec=_)d(m{)z zThr%4!PiuC|Jm#O4Xk(Xkp$bSpSj)us7`|(y36(_)xG!R#n(tr4f%_~3ha%#6#R)E zMZdBHYKdW5+uu9C*O;(-B3LuZ>#DYeyBjmlJOQlHm!j=8>ICdG8Zy$*72aa?3Z96T zi~szpXTf^=idLhqHYnX{1M?p0-rEj(TMjaY8NkXJ+=J7>s;ulM4{|>q4{W=MP zBq&rp!IUPdS*MR~`)WfvQxL^}RYc*9Tu+Lmg&)0Hov;4g9yMZV_&Ubwdz!F1cGjLhlq}^+x$lkG}`mRAn>tN^qe4DT^8!|@_~kC zOVNIhLRAwkb3l|=m5!T7?r!oY)w>s5^~D?rzA~ z^!nY$&P>p&c1@!{yrEtj{b{J5*B#Y;0enm>FZ`L;tn;VTyB8!eI;-Cn6L1YLFtP1u zXm!6x(l4C|@8j9U)g^)Gflt({mp{!TTBATk)9dv49S`|muXn#lvPQH$>%-S=c>VRS zHe`2s7L89Xy-pX}%3q7u{=Pv`U+nkl*CFhp1=We*=Py_Klj_~$RWVEW(1%6K%crXG z`oi0r>Jjm$EfTHasOWm{k-zWHJlD{Q=(1Y#DJHbPmZQ?bo}c(@RqtL@M@YU;t$FsB z9}PhBe>zu>h(B$SXpNAH=6e>3FaN@CjrdaP-d?6!!&S(BJzG(_=jr#?rBj{gDGVP+ zQA?q%{kmub$Sg;(5we$8ky%7iDEQWamMR;5UtbouYIOL0TnE$B8slB({^d0C;bVo+WXDvl>O8mTVP8%BPHAj_7Q8nJ8_X`)(HMA7e}qIJ6c=ZUI}SGhs!g@F55>a`x?;J@~_ zH!^{GHT7h%`hC&sekx>P7eaX`Wfu zSl@d_l5Zq=ZLg6slyG0eZ5PvWRh2HczV4WRtr5Jz8%#AzY&5@4WMm4zwR|(5UuH`d-B-dzUFnAs-LSu>4~yxs4l$t z!E4e)2GMw^qw01ow%4HRcpD)USS7h}AQ2vYWRMV(`=ZTR|ZtLZI zy`>>D1$|OupVlKM-Sf4EOjAJ*jjv0hD)E)cer1-c{q5D#Tg>}vIaq-|j;|bu=JQ{?8l@}KFH^-K zdRL};yP@K{;;Ka4y!_{l!0rNv5weL$OjQJ~hHibnF~n?s61?_{Pui+3!DxtpFBQ1yM;kX^ zMQwcpOSIp^6sro8q}x932|(>QuFmHzrG#u%vvrXJeU<9W`1r;Wl?AGBjUHPhi+cHL zdzDSCr!I+QOU;n;m%eDfJ3h{OW1xnu(!!Tc;Qeb`mR?mch-X9!Z~=da_@WQ+n+#v2{?(W`EAb=~F1c>gI@pP;mKsNm?dg zQ#7DDx1XwzV~9SeRYwRQEFP)&95TZdXHc==vJH8Lx9QUtqwRgl)* zFYv({e*3d667{ilvHkw6(!y8%JJPVp(m-E%;Bs}P(0&+$wYuPew?zAE*I&N!y*bUV zTrmbb6;V^8ou|D;W_1mG6h*0`m;JJe=GPUfh0#A26l(RZkFH15$5PRFG`~iFyyl9= zBMy>}hVK?-3OTK@0z99oI#$4k-xO3E(65VQ-6wj`0Cl8aTKD+kWKdh4ueKh_UL&c3 z1(;xcd8LI8@fiT5su33W*I1(eJu}8fb;0g)L|C zdQAg-Bn8_A`>J^=KJP-52!Gy%&fAeBJSqK8s_#9THCBLVJf2i%l@^{mDrnZ37%B>y}aJM*Gs!^&nvg}#Kb>^vi9&2#qdn3}{`o;SD z8L)7aiK<>}l!Bu8znbRaSDdxdy>5lKV7-<&fu5L*s%hdokh&98L@d_bT70a!Jwjys z@(H9$kgU##yL+qoqra7 zAmDvp-s&29cb*QdqejvAdc)E`lOly8ZQRD|BZ#U zKM_gS)XSprqDOq~!SE71@l$aX$?uwpA}87 zt`pi_cd~C2@^meV-gx)gSxppW)SH&?+30PiUyG`zFlq)J#IsJ z3DB&j=j$!@ztz~u4jxIre4=f2dT3#8T}_SZB#4HKf7Oi<u(^+ZJlQJ?BMidC+ty8qQPlY-i{HHgQvYPrB{dzl@6qWgc}8|~HE z{h2(oVo@(uSM_Q>qFa7X==uh#y0{GUl`d301gwU4FLSZLz2@aj6}95Is8wq_|G6(V zPSr1=fO6|D8J@bOk=-6|T!Vs7O1$QS+coXKId{#rBZHXIYE-D_A1%-mUs(X8j=$L` zRS17=_t#RCq!kAn@ey29YqfnZB(9wlrEkXPo^`ze$yZ+bruWQ6T5ET^z z)mPK2x`_Vqt^Q)_-9!HhwO-B8tGkGv5O~QoFOR5yQo6c>=;r@=O^V0>qP2?js{Wxb zFKw{z!BrneJ!OCaRnz(V8#GA-I9e^>i(QY-s~z_*ztWh}M-Tbxc~!U2GaqimIm@#h z#89lR>Sf>9dISHtwf`G*eO!H)1N983<&A%dUn8pZBEmE*nmMcD_sG%HQAm^G19S776@JJ&Lp_gYg-)Qj{D(+wY zU}N$p=Enxa?}FW^^$AS7KhrkRl&kDe^c{ry#!%A`d8m|@-3XdSSPhM$+JfqsNMGt)xKLNMaW(Q z)c*6I*Lk;2QoY4?oooyLvaC*Oog|@_8>rs#hRz)j>(qt>uhd_sDs_@z0X0y$zy9qy zuhvPbwFv8E!q(9b>m}Ewp=TSY+;=b4zF9Y=A;!J&g}U$7No=5M-~O{Y@6{v;i4*_V zv2kni{{Q6H`4o;P4bgrJ;bgy{_An)6rnE7f(cG7q<@uaxJG-rOs*WT16*i4Ls$z5+ z8CkVho=K~lGJ((twL>?A()Kta(WwD5YdO>mYDr~{9aj;zHFHoe+Ce=-19({tlz34Y zGW$4=C2tQ%B_2P8qi9`e`*VL2AU2{K$8{!4rrIJWl!<12bK24+o!gQ+F%njlX{O`M zS)4n&9>)~R;|i17oP)L+l9^#;EG1u7b-YaOWE98V@*!I)@>0N-@;sAQ^iZ!Z$K^^d zqc`GoVVnnz5Hoo@@Fpg&;yarM)K9+8>EnHdjgxR?d#EI>@;td#@Xc_scS9dncY$S+{0h~rprs&9x|j$#lTi<^fC*dajqh_K?wY$eY3 zM!TgvPW#1$B{9TM14Sb7oGg7(oSQ8!N5HMZ1(@@UuG(Od6h|aS=nr>`jw#&}UR_dk zFSjV9Q^Q@H|x_@}}c6)f`b}Na<5g}EzK}tg; z>$t-lM@Gwyo|7BQRiN;>@TKH)7L{F}G zqvUl&28?^}0yp2guJqI{Ed z$GOrg8xtgC@F>+3x=NMSYHWOttyb*&6-|%it$wD*&0Trfm~FMo-KQ6)Y~#D~SgI49BJopYI}mD}veVpj?V|DMyk?G1x|-Rms-14xRsM2U+?;H8 zDHVGm%}NG`p$9U-F}u{{mX#1{#F*S-?lOCP3-H8W=c>cR`FHvxEG>(AR6n@GsT6ojuMvlI!D-{eQvKgoOPwH7M zurS??k*j79fi&^DqtN8$c}nx&F~ztkx1MtlBp|LHM10yJVr4jEbce%c5xE8YDdWI) z^L~2R(#L|jR5Z=zz!><_XJ`(BLgb64ZQE*~)s=Cca=Vhwy7StE){|Ck6JayQh^`Yv z4u}V7=0qL=G&i#fvB9y5@|j3cex0Ay=4hth=mWjDd6>eZZGuSA(j=9_=Qx-DP{ioL z?qNxB5cNyqRMVo&H1RwxCs=}3h7oxevSAp#^U$frFe26vZa^zZXQ(#}xy$hw(LOZQ zE+S6xY^(^CCQk1zGQ~c0qZI1FA^nIO(}n;G!KB$mh5c4hGCL3j)eSeTp5uIo8XMtmdY#gxXL{rE8E2Q4koQsDh}!22rL7;Kb5hQ<@N-LqmATQa zlx3b}tR%wav`iU#mQNwh%~8am7(pZsO=AAhzWEiI<29~dc(o+}Mo?w(;a`q^-PiuBy;nET1d=Y1JlqHCBpv`4|o;n4L_1PZVrcIfz$0)@1L9)XHl@jYco zcQ6eq8iKWoO}j9HYHMi-q7-sWg}N>aA*gX&agqlii*jfL3Wn*S6S|B+s<=s2PHJ6z zh=ojLg7t;THlvBh7d@aq*DeaU~o(joN}+an2V)$=hB)lV@6va z%M2g{FM3B|RB{k{cMhSlgVHg{976<@As$!a@&su$l|D_%FcGd7jhtsgCTT6nj2q@y zs&&rHY&Tt(x){-}h=;`=4Kz1xbmy3qC&w}RFqI)xw1@{Z9yU<59h^FuOK%oX8{Nsl zRAG_Qq@ExeaS@~2bf%Y4jlgP%lW|$khy(s-)hHY0Aq0~eA7OnsslN!tq_@Z_SJz?= zcO;CJ(1Yr%ZB-yaD;=F>4YKuGW?rI zAnp!$M6?^HrDPy(ViJ{goZPQ<^&mdF!rK(gku8euO*E}cF_QTU6o<|yP7o!AIVLns zqoWED&y9FtkhaV)o6c(SImY6$2pEna8B%yufi(c3h&u#9axiHa8lOevoJXGf4UMQO zbOVc23b7*DK@hx1?TbZaH8V+7HA%vU8DcS)Oft-jB5Xk}&1!^6I;d?ZO(RAKLLyVm zK?GhV7nLZcY%#ZYk*=cSaJdcD(c_RW=)no-Xc-1q2yt#^HJD)tfmM>zlHnR5>(Wbq zkso=R{NQTWbsuBaywkgq!78x8;Gte~L3WiGO zN|%1|JqQgVj%%e3mQ&)xj?~8-m>}-gsC=IjmQ%DDtx<~#MQn6wXbKU3TnINzC^c$u z5JM0i>-uBd)g0!wfiT8m0b!%#C`k>Q@_I7Ma`FITiO~>aWVnQ2KS4y2R+ln92K67a z{(wm@@4Z3eUy+BLA8|KyLtn{NqZM!h(OaVyWJwB}noN>SUik1L1|>C+R{&AaE5? zC{%+Os(pvij5|>_)JXvGF)}i&(@0R*pdA0U+RHi8xWr_C?69uD{ znC}qrIz+m_?;`XYDnr}OedGNhIigi$MDl8L>F}O!jx7Xm|HW(#tQWNVRtm8wV5qlbhf4QVEH075SmNN9%{QK{GY;|sarZ& z`j&Kuju7v!BzLuSrrM~YK7NiJxP=?xG+Q~h+1M|kRw6Sl=-ScTXvfaG43US zjgs?D$uSw3L`N5$g7cM>R=&xAytb!0vx-K?OZU#$&z~E)u4PhJon}@rf4KRg$~*5M z(P$^#M`%kyZz+_@7Y%jIQe#bOAC3Mt-4%Yc>5lFfVOF*c6OG=?x29R{?4C(7uJqBh zTB5^9hVOL3C)s3TNvU~?L{05NX&9m0XJ~m6LH-cn-1ssp@9IKOX+s;G)XMixh3D8A zb+j~}JY$vKAR`IB#G0jHne?VeOVfbSs?VvtSzAX_*d$ruOr@d-q2@S~G@R~=&*?OC zoc5lxQk=c@?{0_|vtqaa0jG+j+q~X)qJ9 zJ);Bn8!I+6^-Zp2dmIsDHgQn|ZqEHIoxPZX z4k?h>iG$=Ko9_OproB*^Ng=9lDn|Yw@x-TtePk)((4NppV6E|eb=#92dmJZskdF6% z1vKajg&d+Wmz$?iDYHO$tT6Tz8oNlJMdaK^DB9YTJW1tp&w+G#5Y%FCIP$H$`+#;6 zMTGIYj9aF(zEo;|>B4j&yei>nH=W=|JIaF_SCKxOtx9Oyex~c)ys&W<*J6dojP3_j zbsN#LCYkQYih#xacJ6J_w$nLxnq(X%q8y7}j5sG$IpQF|b@|5jgj@t8kMSqU*Z1YP zGcG@6^#ACgCp*Rv$(igWxxtjyx92wDI zH%n_1s}g;Wx3UWm26QzdPIue{!+x;+W*VELo$KhOE@NE234y&gEBiEEr&@V4e_o4# z&m%0?%FiB`+h;oNPz&)%m8giCEU#sKHd#TOt#(eICVdFdTo{8WkbMYy9CPHzbYh=Y z4kFAJ?2Z}!#JAqR({(w?EA9&)`K=G7XihDicg%rpG1<-?Ll2c_csJUOZa|NGtvF4{ zZ6Fpykl)-#61S4>tRi(Lr_<6hW(c8cp5ez1?V#C3Gk(`g$$PE2GW?R=VG z35lrIqv$P!a*my~N$aI2-;p9t2_c^|{o&>W32LE%RJ^bZQPV3&D2-&NDJ}P)+7Qpw za>@`D+5Raf-Tf6ER{qI!Q~5Z5UC4jC(#bT$ItOdyb_-#t*Ba%)jumvb5zGbpUSgra zZ7@SOB1*l2D9AK7z;BYx&~!R0w?pF9=4p;lVlYRi_H#q1B%p zB<)sS#sj@=UevLzzf#^j$@`A4q)hsZo$24$rs%!Tt^`LvvVrxTdWw~{+DEvCNZ_zU zIP4o0G3#XMZdg>AAkQdmmrDOP>~u0p@-~8`cSh&5Q%UD}?Vy^F&!hw2C}kqLp^jn&gJAwkeTOY6aWgr*|R_^sD`c z8AW$SgGLwnw5jNrz0RmybmTR|=w3QD=K{7c5ja{iW>_yd$hVviKB~c}Y!W70XWT-( z_(=;DlqgEe9l&gs$2=)_HkZr+mC%fnkO^R_VN7*|S+C{~Gwx#2iRGUk32tmTF zJPa)n>^dZa3a1Eqs{+p=j*KYSHkyPr!=x22VA)X?QQlymG4+8jT_1hrL(iBOO1rdI zHi(GMd(6*dmv(M=HUG||)(U%9=c|M7>>2qF>LzDj`5xoK#$o51FMez_rr2+0Kel== zT|WL+*E8k}UG9qC7fKg3_W}HIIWY8>7wK%i92ojjd!td1E4Pc^zw@UrV0wPF`x*SI zN9EaPdKRhN?x*sp;mdW|r3xw+ti{S)HBR;0roO4P-+brM>r_23l=qtmHQ9YqjqacV;iK-QB!IO9;Hq z$NM=TcdWvsjFP*Z(T3$BmWluyY!&|n5Di)Ue(ygK2vUUG1Nh@)N0crJv|2JlPP-OUP4wYvs9Xmg<@2lp&hI#bi;b)@^PSmtCivbnqJc!-_6-> zY97Uk1R*n(R=s~-?>V0uDe3X&^=K-st|4yQ3=K_^9#fr6t9wkXmpWJ-WC1ZmWw)Kp zuvUofsMCa~&7*w2b5>6q#y55A#1`J9X)Y}*<|ktndF-sKl$FR0NlS5ya$=Go{vR+n z9b9#b^jrz35M}XsGM>_14Iw3CBV5;)vbc4gO_4a4C8Ir1rCndaX^app%;Eni~MDNtqimSbSoc8ZS+C>6BBVLt6w1f)>U}b8wdM7N(@*O`#xA)O1J= zE5s-(aR31>R+gs5fu+#4-G(#ImI6ez0vg>A;C+?^AY;hU(6Vs_5iZBDG=xaYJak(B z;MXDF?ZY!zGaAUFY6tshaS|mvW6Y6{usCt%h~s=ikz92>b;eA)y#2A z&7*8>TyYBMV>?z#$kJ1W%y$EN?XoWn^I_*Je2TDg)0)nk`km;P)ag?znW}|lH_RrT zryY{&*w4|C&T<}~?@D9m4q$|qV7ut%R5}S`Xl&RiGI}yrV*RBhES6^Nli_wY)e&as zwv{w=&KXYZqdf)2J0rk9qdWSehZ+08=tzRJoA#XEKF#9&h?d=>6iXPwN0@YkrN+*lBT=CAnGz5-XtfL`7Hray^)Lfg%j=POmK&IGi|hoTE?IMc z4If{rF70O%A2?jiaoL}h~${KEc73qa=R zlx7m>bn0xUtCeP1$D}-~w`%_B@k_0LI*ak`P*;tU z5vRDDmd+ZEoMA{}8Iy#uO)M4pRF~vngOF|r0zKpNOd6GWm(+e9BCqM1N_DMS-p3G` zo9D3in4N0|(}4j2xHL9}4XFosmQjQh73B8zgvyNp4vQ$~^So+(? zPDpV}8O6kwaxjC0g3~VGi}i`nWBo>G2M}0DfFnsmV5tMNi-hDM3NUpiLA-lI9itV+ zXi>lf2`H+ZEh&(PxNOYoMa9kp49I~tOTi!LPFFW3J}|+tXC@o?0i*1Rk-!j(J96lH zLXYVhsEjp*pl&NNV69>TgVNxL1nU^UG6kB)NutEbMS~I|g4qM11s!jtE3~Li)0B4(8rc>*c*GKbo=gAK@N&F0#hf3%% z%sp6QX%p#;JQ=5kSxC>4A-0cb>j}1>D8!D01V(Cvf`}9C#Hox1$QS}di@5S8(z+R9 zP*O6TYFsX2iOXhnGbRviqc{oyFMMlF-ep3`w>$LGhc*;t+KRBbLy#2=M`~hw z`e0xCsHsRW^OH)e;y8S$R8$~2B2q4gEQL`j?8tdykVwAAgmFqNO`NJ@*cme*G@b@c z3$Y7bCx!SVH6_i(t66}pYM=~eV0JvHKk@K&s0&@+j)iomfjvOX-9XldCh^xqGnj=f z#kiv4yRsc6sn{geHjYM%bG*5!nHMSNB&lnQCG~;G~n(mN^ zaf#|iF)QmSjqcRmmtXhECO}p?_D2+!Jj~Hklp}^THiccDO0h{)ya;~D2KF{h?Bs;8 zPLal@8Dz>15m(V2C@3|~X`m&gjzO7&C7EH2>0ZkfqHb#tF$kHBne}!C;Fr!C+l^V{ zsjwA*iM~CbU-;k`*R!r!GG@tfTEWg?oCL8s6lF~?9EKc;=s+}q&I00;FdNdPG?Rar z0<; z)V}TDx_{o(1ntYq_6`f(mXRYtOe$*8Jgv=YV{@7V6Tc@fk1CKQ*OBfvLxJYQjv z!|4r5d>7LyY2zsNl%}*LjzgAdPm&+T`i*_;@wC`3IjLQssnk%Zb&`ag6fp8ZbHhLC zq-!NLU@WzS^J5*vZIKJwhMzKEL`zC7_d4TgcFHhl_N-fQqvy(K5~tZ=E4{%De?jd% zZ%xCxx;w36U%qEvjm@h@G*G1fO}*FbWuqyz=Y-mCeRp2%u?}`Z5qwe^+pV56t&Jbh zlb!l#hq0#h`AZvl&)d)a(~x=J%uM?(ZJ^a?9n9ZXdSg^sX|%C|v4*z~Pdn`=VR<}B z(X_$t=9#qjlhWiATdR$l&PXXUnMylF0KA8i0C7Fsc2N8j5NrFene%>jHUn?g@OSH= zodae&*lU6ZgUuyY80bM>yU?Ce1rWPS9ncN&(>Cz(5ypE916^qw7M=Y`0qf>PZpZr} zVB5JlV=s-`k9mvH)@RIDkJzo@ZI<8Ld!Z-9H_V-Sm&l1(uM!lwf;V%skG^?`T?t?J_C_vV^1$8S`YHK~~cX zY*$ZE0H}q^tvq(}U}5i?GT_=mitp{%G<;0pre`aKZQYj)V|C%TZYKLjw|?ytz+Zvi z{+WQD=n{2{buzt)(&^NHrjeti*!f}kDeZ&`)HxM16`mUiuj*(I?`nOU0<^W0-=^n| z@9Mn~Sa0F$_Z=g*H$V9|ks{P_+nR=llwMJX@`E8ngW1H zwpcUiO#hPh8FJHE0MKIAO5Xu%y}cxW-gf0ab%xmYO;O;L59=Io7`mtA3IK{+R6G3x0Do}b!P`}y-Dt?koGL?54(E-MZ0~Z8~xK)d7XpN z*a@M1l{P*@*v&LFu#t5a?4*U_x0O+=fo(^^x&Dpuf^kbp-nPwdw`e~wvi{UErmdE- zrE15|ZZB}yqB8){w(DAEzyjOLTA=Ui!|n2uU5OZ){}|Kkq*8uZd&kZu-oEgNq_5(y zPn#DxE9Y;BUNpLnR8|q~m^z`A-=qpKy;~`voQ&F)Kh4(X?{i>jJ~q-`-}2GCbuWp8<; zDI+RLPVjS;ej`HrD;O7yG-Ff*Uw6p$02XikAnP72JYJlmNo$&qiQy1AOJJ6k2j6_8 zUx}Fo(rw-KWzs#&4#_*!{%uD%+&l$_i?*TOk?F7_fsKzdAo##Z8=8&^9B&rbcmmze)5mfr3ZLQk=*4@FrFfn3<@XfTGw;l{n zYN)Y;O0dkGaM0E}?A{d^cB>V9ljnM7l#b;gT7RD$zk(%6)`mE29stAARYzCR>u)0y;Be z=D88AEb<>A%VSUm%jpC9F@4>Irg4)v%sflxyPVGOoTjUo zj>=^Oy78(2>1{u6zVmr&^CF6k`z>$WF#}%Zuqb35#Hg9?m$ zL8a<)uppD)O)38Bxmc+E+Ut>r-d`d6*jUdba5RTZkA(-Vqr0f?nA6N@cAC24@N`p* z^g+fMRS>+SwI@Pv^ z5+>Q@Q{?w)D_lER@36%Trme!dCvk!ovRO=(bQ1e4?ZcK`=v8`8s3j&RPXS|8X9X0X z9aUhntQS5=tF6*!+1tx*pCDK}!o8EwFF~Z&#I$3;CuRwaGAzwxxEQ_e&>($EqlQx| zaUf5<@)!*QR>OEmoM#+fdl~o(9?-MaW`k3D8a|hF)KXQs$iwi;GjzjfnM3UW8rjq72H=sX_9JH?=nZ>U7BX-ak?k9 zC%ak>qi$I9tt19(FHoDEp^U)G#8w@}gx4#ih*Pyk$-n^!IL;7@gAq#4r9WvO;3QJJ`}nx^DKd6|MHL;qO_VG+{blgfF|b00t6FA9BA%E} zIZK>kc(*}P(1p4YiS4ie%sEBVN$GYAl)1*>=rqq`rSL)F*#+maxDrzHoiV3f)>q3> zo-)`T7K4}cFce&jx-s=fzw?^{ADhrJf1x(R74SyFigI+YEi(wXNe#r|KNXzpgG;mZ z7*PQHy3u)Kdq!)g74yb8IZlP+l;jfEnI$fCYlbP(QZURMDu`E=w9SE_VJyy3Q90KP z8FKL~Q;HlK*e!A;|JLs}ZRpRB@1p;K*lXb499%iKV#ZP0=3AKKYD^nH>&QHEIyOe{ z&W;Yl#f{Vcl0h)fvX#tzN*i%pCpyB-jP{td!x=4DygjA0YSYYUn{QJ`i7_(IJEN)9 z#tU3ljrg#&p%W<29kdUQPFATzIw`lgDHSJ~6i?Bl_DYGq3FPyuFxXg13r}eY%nCfZ zokw>#iR^K+_wDcf&shMiEevHlZBS(4)V2mZT!5cu(cG`>YUKm zMzEwBPBia^TO?mC_ZiObtE2O3mljXR(XTU2O47j1*;UL=PO}(w&biLK{uCCQFx>UH zc}mqJvsH!F*?gYPu~vt;{i<0U4&TAE@)-*>f9yC;itE`@sdSVj0cWRMOT&qtdA`Tm zOMBtc)Rm6kYx76G{~J171abUp$;rsjVP>C7>B>@3Sv^g4v9DoDR9_2+aVScrWpoEy z5Fv~$K(tyEK#^KhdKFVRLxuvHWDgN3-oyd@OmJy6^xTB5OHz8J#o$;vLA#8Ml6lsU zf!V|5am!bGX+S_*3d&{04)q(OvJ+>_p$ZLAjFrS_$*cf)rQ#goxi08y8Uny&S<22t zCm-tPG?Q*Iq%PY9)}_F=jGF2-RgtvXH;M>lqwSyE(B1%=T#3S&q7_crn^<%^lbmR92&k5GEHlrs3uT%sO|y8;MSmBGk{RUCBNeU~ z@zRXgg*uN>4zv0o9CizuE5)(zB`{Fhs+uYx4v|Sl{(sneANaVf>&_PdN6y$)k^u-Z z5KYU2OOOVsKNd%l!zgJy7-FK4O-CG>N@!Q9MOkj_Zu%@aahv{I4~7_fXwkJO%UP$* z+mN)}D&4fU6t_)Zwi{8V5@oB@lK;HANw>Bfr%iYJ>XDkX*>2nH_hLwj`cG2y=cQXi z;tU43xPQ()_ug}U_nd=vz;m#H(A(qO7I;kQcu1wgVJE%UhR))~yK1PuSrDr428noU z9-s{#Y#-3IO z3|DW{M~!D3^=5+|1Cc~3^ERk$-nPf|n+?B9YxCB)y6v=pTS{k>*Zi@}oBOpU?YiPM z<_g!s&Ru{iw(20qNOs9Xj0#88Z)HQ+X&bjhDb|#^!smp&-GlTM*m|6eI$PT!lzJ&u zuvd~;1RG(0;VM{u#*|GMX4bXql2w4Ov88A{X=7SxgYtP3v_EAmSDjz@8k>nNS~@n) z#GQ^Mi!}v>6yl)Eo0LDQqPjG`=M7%OuyTuV!OYEpIF z#Hih**#cVF2LH5OfY~kDL46hYcFQ6?DcDs7R&Qs=r66Lt>qoD0lvP$}H$R-w*VzET zy03RZ3%EmF~9%8Q;wI!(Z|uc4;iC& z^HqVp-O|!=<|E%?RcQe)XS!)&Lq1Vfw;Ng{R?*K&3(bZf5-J-u^04qekTXFm2Jo)O z9)UFDR+gmnuoP;FymGJu1R1KOf4K7+s9F%2l~9W4U+QzP2h zAT^dkjnXb#P3zJ_T2f_^_uM=?D!L*~?4d>s_Df_m1vELp9idT=1&$FwNM`nzzIA2s zX8XF)ZyKfhtnrqItQ9NuFAOhVArki)-@3bh_;=*g@qY!S)z)7%8OBn#`NOXW^}2y2 zFNoc1!kg{Re5Psl^6N6!zuxW+?H56NL*myP5HJuv?3x=~mLl<*(T@T(#-_@XcE;Jw z=9;LB1zWqI&O^-DUVQ>1J`;^FM>NC3?`>*d4ofD$- z*1d;&`b79m(PDnhY`HraJY#pp0$h(W001tl#gWJ9q zz}wvY5)AJ05Ip*R$+gx8PaTqg?00ud)c3BUL}Yu7wynjI`QUd3j9jrl2ySF`FbW3* zBI}sZsk-Q&^iI9cF9S);Lvxa_aPAgNck_Pr6Dzx2wgiMDv)#NG+4db1M&!`Sl)z~F| zVg1(Y_5IeZU&K7L^h-HwuUEQ#JzBl{)Yw?Z;h+B7_Zm9^`~K1nu=K56HzpowxNC1a z*zO<(y^pw+rlw{3qoej-(eV4=8e`(oLH&nf@46kX}j z)(B|=T(|aF<3)GJEt|b%pR|7P&rSBa{d@9PuLv8CcjbN2Fl>%s0$RR)+g|(H_gz6Y zU((lMXxntPU2QRTo88+QDF1G(Cd>JMFhHW8v*A{ZJ#&4%W*BBeHUs{w zSE$)d{<`nj>d5M)hSN5dBH6M_S)dqiEOB?_hf_i-MekCxbgYL>%BTJ_&dC7z^QkN((S4DV|j8rro#^f*}jiU z3&Eo!P4v^xFB8V{yl5-#X#DBFywT9IAK7LPc(>QK0RZj;N(YiJC)My;L+dV!hR(jR zWuonn(F`FP^1pGTQ3RlEzS9`OQd!?A!cFFhq5-Zul>fqw8LdGdcWAn@?m6QbF}B*f ze}__DE4eydzayMe-cdFaSGn8_gmfnZBuF7c>I^`r)mM7Yv?3ZtkYv{W3{E9 z^;=Ip{WIxQ(FAK>(~OOI)EpZ1Gjw3-BiUsjdWRP`oV2X_p9SnK#qHEL8^2qxuJ`Uj zyzDXBKuizco@oFM4PRZ*6N4#&E~l6R`nL!?bmuzwYlkIzr^_b@_4<8{7aJkRa)4STGA~yBHP9dl-O$S?KX2 z%kB4Hhgmpdz6rp0T~TM#Mw+~vO+2c%8yh|SQ+9yuaM0s7b1A>}H*Jh4)(z-e4Y~!> z-7h9J%-!|v7$*GS!EV2<=Ga8O$$gZSO*PVEy0TW4P`=;LA29S9P!hCe%y!fGxteUr zx19oBgVez_O;Myw*{0_BYj*x&c*$X+!r)>I-y^$cLTSjmKj#>UZJD;M?CHr5%)Ynj z0P)T-U9wo+qBd>QZwUokfko2z(paOf3%nj3f_+A8H)A8Z(_c9?l+5dO$ID}SZ(U&Y z_SSoSBXbym_>JdA^AOq20flX=$xK z)|CCo>gGUef1lS!^R!%x`eYD?YvUZc=?1OULRNSJgw|Jur`O_nNJ^z=+ynr`9Bl-jthu zNfa~IOU8p4>*qzFtr)V~us#w!69KyEUFNAj|IIDmC}ciOTmwu2Szyg{Uv8~dA8*}j z)aPo_ujJyG-3H06s4EEzk9jL>(sMN}7I3ySRYnL7@iyf?;%WgX9s?t@qdSLH+txPK zXX)*Vvl4T;-ZBB1B*v_Eo33HvYB&r)+{?b~W-IWlP{8<_anOGMJzKp0uk&h5U?Zzw zr{&X;k?^dIXn8ckRHG~+3*4)nmI&Q_*85kO$+qOTHS&@zd zsG-P(H)ZZNKmJ`#qDLk_5aus*IG}cuX_M-C67gu|&z2R+-x=K6w4ujZAqvHwz+GS5 z;x+0-mF*v|KjI7qHEdpV8#v(BuP6>+e2I5jr}41fhXvM?ww*bGrDXbes$a(-qOC_X z_5%TTTw^vKu-oe&F&g{F^ybIx>t47;INO%n`F`tK`*klxfD8w%39JZCeXYN^+cCO? z7ki||y=ONAN~^!Z5%(Nu3c&9Or@;VfPi@#Lgq<8U08p-RKl&GmiH^Z50ZCi5J!yx@ zR>6oy_v6YCM(`~t_URM537Hb!(iQ?n1=}$^3zM>6ys~|t7&pu<#+s~mx6wbeTMr!* z+qp1}WtojWlZh#{y4Dt`yXsoCf>y{}1@W3xy448K2+``HtMZJar!qq?Y`a2nJM3qr zgnz@0l&gl31kg;ei?65cNd0^dLu}y8T<&~@=LpVME$1>Bj3E_gpE1KR^voLQ&Oy}?rYu{Dg0yJ>tY-V)@$3+TYFk} zqy{w?B8>@qRZ6s=&KU--W`wvI5E#S2{;egBx(8%#Wj<|mn1i+onuBqojC7(fe>oeBH9}ep zxuVI|nY_4&D&49kgVp#Os#c17KYDos5R$ZLUuE@MoyWv7F-w9myd^;4PSPL z>ns2+yG9xGir%(j+pvWVtQb1M#zPnm2Huem1VK=b1!kAjpW}78SL*LWwYP&Ohs{Af zvz5{OT1K^!=%Xu4_Zes0S>FW4hnOO?Ri;P_@Hs)e09mgC)^5jY7_*Z>Q+OzINARvs zjM=vsiN2fMy1ttp5|~+*dcCI3Ll%A|yR5qZY8_)|q{FZt5`n)w$S<#d!d%{;S>^8C z;O(KH*dC= z+8c&-eU}Z0CLpMcF(bxB%O0_%)9@G!WA!1X;{X{VGD)^cN>U=~A#IV`!-(90H9L zVEPHH^fws6R^yCpn`}LYJmDZx)tmUdtGdWfg148;f8qg?k-OlvE`~*)z+q_ zg&q?F!7vubi7OK}@I`C8-mGQg>jOpr#_ag|cY8^VpgKfmh%aexC)$MDUF;ap3J3Je zr-7E08yJ~p5;oQ?=^G)0xJ4v;GPdYc*-~}=L15u@47Rp4I+yzv{?3mcjcq7;T6Ycy zj=;j9T-6Vwn3`n(b?db`s#*Z|!oHfEfcydJ2Hss#;9% zG)1=oU=%~ba0QK3qTq$VN_#O&y~<%O_tK81Rho`6GLqN@D%W{Ry2JJm6gS|e@IF;M zXT%fjrjl0EIaS^w!h)H!RXu1N*H>D4aih@K1zd$yU3ue_#dUMegv4`n^U%?{6|dl8f36 z?6vt4k)ums1+~EJ9ZfCD7QOP^dkbn9!mzLd;!F%LdbSSSa8IZVW&ncO4XnJT6 zz{D53On-2g3WjdFz13&S!u0gSu$lDYNqo-YMz4|&(OQ!1n8BAyoqTIr=%;g6C1M3# zkHIs<+_LIpep4otB`S6j?#CB^V$$>i)BU}7yqjcgYCts@;${e{iixPJbZNWRcp%}4 zj#i-9u*JH|s|VlDl_8?p!kBC6kUZpJk&Qhw%Qs;`Wc7tllMAx6L~J?R;ejks7DzFa z0TbMP_tPt`cvxd=N!EpZYB-FYXXPL(;Va8)ZV`gjPk+Km_;JxI(lLc;6t)OQ3}m-> zU?h)+9y3B(OUDixA?&c*u4OkP_@sV_T@BbU%!oS$BV4q^Qp|I*bLmw9TNJgVF0gu! znH$HiET~kgB_MK#?;BQ_tjTv18z#iAKb_lP3p;p>C_|RuTE{`BkSQZ;q&=pn1chqKTx|zkpR_(@mS6DnSBiIzy|{lluEEC87@j)y|IIsYZuM?yy(7r9 zn=K#n)*HjM1FskN%SE9-s6VN@pQ~+eEa{(ZyoR04z{q`89~|#kS$DPFve#Z;yr!e& z|FOjG=9WFJE3N-zcM@^QtUW1MtMsMzwVCm?>uXszZu=6RFmg-o4bO-X;itum!4&#l z%%2K&JNu#%I2CGIBUlsrFIsY-Xy0YL`HPE$J238IXKdVUh>kY4GoR}px1Kv?y0xF| zSktlLOG{oCqqb;ydHHU4;IZZJVc%it^4n;Tv0-)d)kdj5v!o}y29sV4d2RKx{YGPI z$>&zvw;sBQ2(!RH|f3&~A@|x;XXOybjf|i_AAK#ft{TmKL;1iQ5{{hv`C9!k9$3F$J0-TCk4?6G|y*qCX*Yuv`LZwP7qrn}Bp5{wLs# z?H0zmV1C7-cc6WAHGau|3C_^-PY?8r>5tkwx;~a|?Jci;rIP>+gZYPB_qBuW{8zCP zO!4Jwjn@ah6Xdg3i_$Ac)oU@bd)dtZWIg`Z##sBKqy6DW3A0e@`|PHt+P_{d{m>q5 zGy0AIM&U%BwSeU$9&7@u`gx<7B5zs0)!f;>W~Bi4*pbZ+XBzVDn}QRBg;=?_;X5|2 z&pX>2@?%Y7*g-o3yUpzHr$*cLmQ&dJ)-)Y3zGK_Y0j#;2Me)8c^Ll0<#-z?O0284^ zCDnC*f8YNY(UoImRpNf#y7VZ|K5LA-FMkjJZEExQ<}BXyJGuUMjo2PEoEXplM^~)( zDz?4Tc*yJhpdDKIMiw;8d}UMy9x3IsfNn&xXv+`LKBui`VjLI$PQ6!0-Z$>ky}oU0 z8hgswo3NX;WXnc%!Yp9nSNEjeZ7dUt(@NcR&Fc1*F7Nlj$s8MlV+R>k9Z6At_AC`5 z;Ed=a1anYtI`Efq8PWg@s9SFy6&?-H`vx~|J%Cy7H%+5-`!0$_?ocTd;hBLovL^L5zUpBT-H z)d$?3ZFQ94++`lH^1assOEu&-nXlRU3-v_;Zh(BQHnDA`VPNnCpit6#F=phHFb-T) zBz|oxHgiNXtBQ;fkZb$ulhxS9-07MoYvfNIlZv zxZM-qU0m&gwjGWB8wT=B;|?pH4KcAT%Xkl^K5Ju-MjIN7G@(yV=VA>w>mRfpve(vT z`uz5G?-%Pufv?XivbekKX;3>j(XhIOU#PCUIKzNgvu>TAO8Z@wqCvt%XUnq zH?6dXGMkB)&~Am<7y(28Mq!`r&EX5>{AW!WMWnP(V3tb@8eaE2bB7$1X|L~Sdjk;V zMAqDGJ-$x>6mBvbY6zmrY5}T$0_#J}d6g_ASCgZ90#jZrWN>l&CC5wTHiHi)_rquv%ZTwHRd8Fv!L* zK$f*73`l+7;D`~HayF42`t*)YwJuQYI=km@4z_oHA{(pEfjAr4$EA7FlX_ym5Sr5p z*%ZXvY$$nKaYpbCZ0om?F%$>E7p&K~X|MCgPZns$v9h*mbzA4{Khrd-KmP622T}}_ z+w^YtshdXuB)59U{w7~;EB5$x{YJN+{ef+}-J3wwcu$Ur`8eH3cLW=IWPFiw8+x5t z`h-ydCBEOb*)O@Zw)=0^4%ZH1dTR$Se?YWqdL4MHWLq%#CgJt8ECV#wY)Mkd3lg7A z8wU(qEwHu0P6u|oDuuFl8|=+&{M#$)Q4(G&);L$E))~3Sgi*J{IUuyhU+%mj{JmOj z==fIaitOek$sUBkY)o%cA!i!%(X#$p;2lS=$upNfQC6~MOk_9fb)yC$GOW@^Qgyc1 zlj`W+M(l@HM;1NSZmf8S*ys(wnW61Z40zF?H zfA^5Ot3$yMySLvId)G9GeCrx(FmJstJY+muTg<#doUubjfNUbgFD3BJ1`R=KSH`mZ zmOvehqcx0)P+wBa^fc8LYrvD*wB`ZBI*yv4-)n@$e3KBz?v&f*%_yQa+2}q%O!EMQ zQg&rrV7TSS2{qVnC)m17Vmv6WHLrRw?n>zpg;LtuhPxbL?D`oi^j)#5j8jUO#VK4a zkXE0G>QwTF?HjC|8sY`eZT;dEA@Fhik#LEIk*-R00|-)zS@l*fsDTlvz0sQoV8$?p ztDBudzlZotpo%7hQ0^jcb;XqeA=gHX!W-tP@&9>Vu=SH`qEHN1o9ib-7E~iKOj_i= zo|zf^0GAm@+OUGRZY-WWBNW3_=!5Tj<_%FuhchjE&&-F22}DyMqys0_@CW4h{||6` zF6R2eU&V_^rYOWQgjQ)JnM8i|k{Tv!z)x)fKnsH$?+&DS96m!W5o#c-T$56+?Ey)4@U{l`AEa4Gmaz$odwEH-em-wKCWvV!H;*R z(bDE!1ru1MqNioCg4aUBYxQCqc4O{cPFZ!Bt9SroO352yi@}Pw#8SkO6(yNe$A75HwI*In9zi1&49__SllEu!%FGb z|4y9vu&xNO@=?={npnebK+MNseV5D2z;)L<76Pd#i5(_!3h|mvVu(~$-C!`Y&j3&u zcY}tEtj7`4GtjOYGL8)S+Kx#V)-=>b4Fw)-z^4XC9g2lO&MRt7MVns^YR-sV`OLQp z>Xu-y;Q-#a-c==nXS_BFF$~*Zh9AW zb;cP=BmaCjXZqh3U&$yLFDE~vvt&%q6fj9sw)n5!R%0H$Pj?V{hn@F5yWHLuE;XGs zzd9%?hVAR+@MsFqURlgv+%sHBy|=&7bVGGave1=E&+@;v<=p4`L~`BG=hxxr2W0 zGrI%h`h0lAN!&edr8?q1!J*%}@+&E;)t!(Y=kWMUt3`>fyjnR{aX6NBmszbkGG zHQBFc;*}?FRVM1q{+m|hl&dYV{O+*pN^`l0ZM4QQ_gfR1gS#_I*JrJY;dNa_Scwyv zSBkM+x^O;J-r$dmj5i};kJ4quuh%C41>D-x36F#pIW9U+!o8T2>MKKvUSd<-uCg~S zdMY8i4ZAX(xnZ|8c5u(2zTcR5N(t-Lm0@e_N3(m=%^BT!p&x|2mdn0Kvj|~|SJHj! z2|Xd_Z+%=wg&g2!l5rL?(3BWycVWdQ)v=s307|e` zq>GZjB(J4Fl`Iq?U~=$r;2V7IPmMiKxXQG(!IEZTKtq;_{bH~;Obkj;1~eMxX91yd z#5D*8sGh))AS6UU2P(f3+?6ZqM+jw45j+qSSzNG~D+GbcgeHfAEC{b`mD}7glw++P zd0Beg1lS07S$oDYr7U?HI?O$T?UXYB5|j|On#QJB?mY!k&15F^l4>|m3|Ln8HfZUN z#-!TWUo^slvwL)>;f&ukvJeLcC^Wa3MNOHULU<-F;MQ1-iLjx z*XU^_UsLM6CoJZcoazjD!XCB;?S71h%3xDDzg#mkZgqK!JMRp5J|NI)h^=tTV$To_ zuLs&QZu@dObcMAXga6icHk2@@4}_j6+ICHgusvozL=(WRplJ8o9n6hP5^|z~NJ8yU zb{cNw?r)GH3vF*seMW_SrafR>Xv{hn8sV|(`7V~=zy3^f#eT$out|%=QDV?&~J+Z(3c~pStDuF z;DY_6QMqHAtPXpLavfyBlG|B$BLS~T&Q^j{AsClSX9ToM$90L~UCSyeWZA&$%Jm<+3REp#7dN*ApsfCGGe|d@aXS%fgchruL_HD@ zyGevq-VzwqwX~%y*_D=%5hDruZVd#BheZGDS=L!pWWPn^OmYoQhL=a6i|nq-uic{* zBPyq3+tM+h*+G>S>RtNXK|1vOz7Rep^lMqA?M4@PFAIl{2`5lWMj^BbzF=&<1**cS zAn6&|ndqHg`n2(wHP|Pp!o(LaG)6-P6poXv`E?fdu>c33b8 zq#P%(Z9`FL#4{&^Jd2tp*Ux79k9=*}o0LOG;*-h5qymK-@E|?WRFedo5(V=Si=~gsDw6)qDClT%hmuU zZlgniblDlBnbNTe;&RA#QlkQ21zTPDk9-g=#0->R3xD`KFg?YUJ#=UY5j@s=Cd`5k z;)_WS8(Rg~h@6sewB!xRvhrMEi%VWL5cebgL7kRFbqT$k60lw6-h1Fj5)PTh)hD$L9!cso=9QB?+M3{0+5P3n=5M3Vr_4GfwoS!@x|QOMDc++j0o zDu7*d!H6Akm6Eho<#&6N<%oeFvP~v^U1_%TBdk0@BXZrU>AQK!zK{!-jQRpyeiC_~*p^tF`N%;@=0&SZ={m(EV@o_8$ z+9OD2#t^JyDZTtq4jORemLfD##1K&%ptN8f3nEOKDHZ~1EjMKjF*zE7WpJ2FP_@7u z&zQlps6dxQWKU>}&1fLkP$RMND>V-Xb}()wtgAcpfgSaM{t0_SJ5j1uH2w!K%jEx) zjlqBL0uxi0ZGrdijE??QM(5T{mmvplXbs`|VYtt^_0L*GVwDUO4&5-Bu4Ms^#O?H9>0xtAz#NGl8k zq;4BE+JYzTj+T>kO$BxP5<(m#u3X(t^eJ!jsQyd(9!>`O^Fuq#+%M_9Ib%>iVr|gZ zG!Tw=O=?@`AyZ6rX1?rtYY3zg5Z}z*-PlE7t(4U&NzCzY12RzfUypw|WlWZxR+E*XOr>%If=?^7X-|zLkkP*{gPn_5Im*b%)u#n1lpAFsCYz~m>zA$$rT-UjIqV0eSZ1-A#d2?zAsBPWr#al;PUdJ}K z_S0gl-N_L5;tku=+?$s)9}3$#iC}cX_I_Ket3eEq?&kLE`e=LlfN{dM_lnjKGuNA~ zgW_v7T41QdeHpuZL%XzCJ=_>_;Vxq3++Hr6H0w)O zxJ&Du5pmdbUdK?N?K=at#AL9tUli$_J0^w*6T!z3N30J*=A#dG>`h=vla00HBtF{_ zG(&3THQO5#_;RxY3GmwX9r+W0PcC|dE>P1cI9S7YwWctZYEY#Q55R2OslWZXLLMh# z{3rk;&Fi4H_aVT}Y-bIDX#4!`a`RHHL_CGVoByPBti8L1T6V=seM6o!hy)ZY^>vMi z!FBx5M#WbT*I+W4$mKc#adSiq0ZZMh zr!%AaP`;eC^ZP=xq1}2arylMr+ZcLk-(&{>OXMLxLgD*-j1C>)#gXLq2{ih6L#Gu- zl6pPx4C9a+z|kvl9tP!ZJ75eD5H?V43Gz0L)pAvUly!7~N~uN`AXdH%d3%TFds}Q$J-W&Gq6|-^TFKPilv) z7y(OQ5`+B!iTcM~f-Z1&w8Wa*T@Dk{D0=g@rsHMCHShY_w^A&_S5<9v4Ht*w0#o7FGXs)skHmbG{5YmH3bl3xr# z6Bkf&QcJsDY zs?|JjYk9BSjsVsJ1|6{hK+BlaY6lx^pm5g1B={mS&91G`oOwmEAFvbUm$YwgiE#W6&Hovet&>hn9q4eY+V3>0F1! zBG{2QlIlh*(sS5w3H1xZmNB4PWj$8!dakz^(JcsvQXdd*!3%e|DeSifaf+4-qCMUa z6q{q|Eo_eOOt9Tn3L1B7= z0%Ik281LN;nQ}fDYAN^;^IOJDO)$BV^2Tp#>2_+4FPN4=6yFh7D{jrR+Dv-gG1G}+~Kmc}aIfG-q`Rdk1#3xJZ8&orVFb8uat^{|+ z(nTsKJ|ka-e+y+E;X#7T0SwFkPhcc>P%>1Q1Z9!{z(Et~Ul|HCB?+R!9a`w{lDa{ zNPVJukiL4bjHTlO^XP&q{Z(22)fVl>6l(GOQRWNiC&kE zkztUq%JPM1?tltA=HjJ2_)RCr=_GJIw-|tf(ZF47b1InaO4VP&Xh}Zof|isbgmTQa zRlpa5*t_-vO;XhJFWwUF<=D6*0risi^tHRTbkn z_zy{3#~2?#nU=<&^g4Jbp;H;N3SlSs1F-3^`Q9$#O)6Kg`%Zd{=!}*|Z7WE3aZ075 zc@j01aH+g(EC4BSe(HB%-KqCK`_v1|2w2rigtlx^C^@-PRS2CEq|u7Ut-$wLi0q)i zqK+c1frUtM$Vx*>1Jt&Of>3Q?TAPFjxROw~hl7gPr*8S2lJ?@*80uTRpc@2a1F4tD z7x}Dm=;Rm`kSs4=BE|g;ffsC`sgJ`AenZ(vW&wF+|&T_kYuKX zqA(`NbNd?V=d!za$H8M}yw#Iu}nP}mBN?~A8uEMMuwf51MVx&&1X|>+BVgxbp67gMi zW?s=TLNsIDq2$&W7l%})9}rm+a583uE)?)AFCD{{JCuIgRWEWBlm69j2 zCuG^~s+8@#`SGhTWv6G%#9~i!1z}tf*HpzLku1`~l(s$=FsUDGq`$aIAd1iyJ-KAc z@sn`4Yy;9bLz0$AjEuI)CP76R51{}A5fz)(o_<5VX*BKT;_UoM{_B)J_|%(ebz%#W zWPNOxMSz`Q%==|cT!?2Kgp=xz$N)09Xk^$)45@9kHP{>$STKbodc#ksOyP#jG5`aXi~;@RNjzl5hQf|pnih6w6mC^K+h-`4$E!9 z4vHYSq{m%{rqNT7QF1CATZOy}D$|Mtv(l%&+h-PaeUGBE9-EJV&OP314*N&-<2ij% zeLjcJf_2-l*_B$}6?nbjxZkBOW{n&l@T^=ew#qu{;qgse^8qn#)<0pj99h#jYIhP3 z?C9|@Z#FCj2~{XJeOmh{XC zvr{FM??G#*-842Z1%{y)7=!)Z;10{Yd;Adx!-ZFJ!&c|8v(m&6agWp4-q>k;ZuujQ z9}J>>3syyUgazSRxtGuCKiMR={Pi<5u4S}_}QY#!Gkz~(_H zCZOLqf5UZ8>0w=NFQ$Ir6(J|kr=d%sGqgMI=2cU0k>YK3!!fSHdM>!tR zyN7UJJxqAX!|+v^jzGaEzH=o=c*eKM`>^9wzAtaq1L0BJvTnW7g6iiDViGLn+0 z*a&M83sM^ddurWpFoRinVo|ZGr~5YPBl>YuLZ{fNJ+9Mbiwk)_8w+kR zJ&Nv=9LU2ZNubhVf_DN>gplJ1lJiJAJtzjK4tA>WnhvT4cog+n64OBm$q5NNWry zNha>M6%n=~@I>OX#(kf-LP_*tYFf%6Rz@i1rp3=#`A0A~EcHF^%O=uYykLq~k|X<& zA{)b$6^qKvelmX)x*gt(_fM!~{pDl2r!-*h=o1xTf^`T=O2~=QCDVW#K`Sw!vO@$H zNviOhg+5Rt6dv|J0s3UW`6I$E0aKZE;Gi;eXqXL*zE>jCzn9*Jd+}|uLPxoi%Yqr9 zCb6%iWS_FTyKpD(YL!Gg=Etp#9uY&m&At+NBPlP>MgS02{o;bo zB7jt$8?{4L=O;3_=(DOE1*8nzhC_`WTk}rQTbydsb3u_c4EPAOr>4t=Ijqo;%O(T@ zvO(!smQj*IjE9(a7D&r3fNq@n=vQcMVCs0;BayhFuPeRxgv|Sk@Gr()Cx%Xz?m%7u zINE}>ACd=N&N0BEu!}ig5fjYVJ~4?BTr)eug5bRpjzFLr4+~7)BAlGj*=9>i$-!3f zk!FY;L{V1AK(QdZN>Gs1NlZlC*6kTTQR$7}g3&%PA>PN;D2 zd5%d<;H*2*-ZIyY4gN%#IWPbU@Df&|8G>Yn#(1zn4TiKtU#=y_yTpRvIU|=_40gcV zz0klBI6SlL@dAv&VWP!IJ2hjKlSBp)DdPTt7@?Z55(Hqwl82FM5ut^`8YYor>WRb> zfD1`yG+TI0`pMtF4~a6t&`q0c^Ls{U`5;)zU{OsRbwF!y<^{P8s!9WfJ&Ko9L#|lv z&|_{0LhBXAU3Z|UDnsnJBX7c)Xqr-e01ZW3AuK{tL+C}bL?n?qiy|DW@-O$uq+v2n zfr&ap3Amvfq+6(CLAzX|QLUVK6`jv7Vev|X6tpB>Er2f1j(UU|22xs=ed4DP zwfWT;qqzaz>i%M`R}Wc$)TE~lXbQFfjfqBk@6Yo?W)U6JXV_zels0*T%lsl;^>Z?D z^~-Ulf1<3BZMvu%Km7VAI#qWd_iJPxyj{9mR#g(pllj6PTt?KbR=YbVuf`I&n8(Rf zEvD*?m2kBTE;t7vlB*mOYV$un_$NFhai9mm7^DVb=q04l#NnABPeY7pJ8ez?(BT7ymK8Q?2B9l~v= z9(@#|)RRF{;ux@+r%IA@q+?1NEOU}Ha!m(=END{G3?)g=I;6%vsfZeOTEkP)P_BLd zqNp2{pqeM3Fnp%UykJp;2`UPqK;_~xTiFd_OSPk%INt_= zs2%{VGS&lCPk<3XTH2DxO-K`%{!YogbHG9*pH?i0v@oY|2O+0?%}C zz;$GAR6g}^0(_hxgi`QP;CoBboHj^GNTMXY5186 zK5$ASgfjjv|?Q zIqL4EO$Jmq@802kerXJPAQE#9w3z^vB;!e53CMvzZz`wiw+5G0Zqk{6SEAPxNFQDvMo=2?_-f!0V*LO5H2hbrIs(=CLZ z_w<~X)8lo%zqn+2i|TSZ@5IY*FqvfQI?SNUTSJt^*hG4B&Sw$wS$$c00_Gq(Cnl)| z2HML!%lufaM)b+65HlIA`a(ooc5}1V)NWj7ufpH4UU;J2s3&%n;oO)}b<;F;s=*t} zc^O`}=^xGmZ+mN{JKb8*~CO2i4IAoRy4(jTyJa0?k=KJ#BEu~4TtnZ*;tR1$gm zaMIKQ=62{Y#Yu~Pn{q+!mt$#aNIS#kQy=@oNvNXR)MZqbx5QgFV;O zEh^o2%c53H3hNdN9;#F7Jd7+%gai5i@!q;bA6Ba`=j#&Im8&eEg9%(#*v;t!K&5f0 zQ@M}j)4AL9bl>B>>ApaJZCp+6HxbFA8ldSB3a^|Er9POa;8J|L3ZUfd^TcE}GdaVd z4y*yTEvpp~LVD*3ULhgNcarkt)E{;zMJj;rG*5?M0(-KH!aY=ig^0R!hrZ&YxgV8- zowh>@Sv(2p7wRCVGg*8e;)q?OnUHO`qKT<$TmRu1lVMmqVkA;M^-9UHdoKmS`-B=U$kY>XjPB>M8a+d*2!U3pHAA2caqoK|9#BYQj{ zi&cOl@FJtNhiM-$_xV27D+Z-?Pe{Wh9sm$hN-()Zw0I!;iiE@Irl&Iu$B5hH z8H*Y}oCJch{qbK(=R6q3JXY4_n~1wiqN(L%o)%6ReM^+mD>+LoHG*R-R^W5GhzMGA z>*1F^#C@NX48Fq_6TIa2N36q80*5egDjdS7fUK9C7kNJ*br_HmM=O1F@Ii=ySq1`H z<+oo%;UIbl2B_9%bYsNrdt%)=GkVsVfbl?9Fhl8+1zX|xJ+UFZD;7Kw%8?my^`K|b zAKa#5QSN+8-a~4(m2^OpsSCl`q;J}CPs0GzD5}cFUwG$(5k?C(j2zA5CAy*a7h|F6 zrC;eoac_)m3A_UE?U3pvRbD(nT&kIkDzGX|Wk20i`63EO=?3^>5|p($wpG%Aw!&f` z{`%Wmdewoi?Zmiz_r%#R9Y#w}Lav25D%bp{xnv|Yo$675WjH3qit06`vf>X5QjiH) zXkuQ#RX& zbinx^|EgR!0-4lDbW#axLPj~cl1z9APbHI^a(a`cAR|uAa}#p14GR2{NNd|x<+rY@rjQ07bc56qxB#gq+lGf8X8bgt zKQ19saQhq)Rc^;mO4Wc6frQNK+RK&cGd$@o;S zNy86Me#lO{RCZBeG{2hdWZNYX(wg~db_OBmti0~l!8`>m{9+A#uPQHINx(9n1 zDj{hZX0jB|%oCZ!Bn~bLDUurK2gfYNAg!pXpJW`Z6jeiqP5+1_kx%erOyc3$8kVY0<}(DW2tAcUsbtd1$G!h<2}B$JxN3=(z*S@LYPa+Pt=us=mn?7(Sm(C}J#;6}BZS0Tb6c|F~W9#h9&*d|ncd5xXv=|4zt$wO*Oa$cjy zXlT?_smxWr@T&@M$KxU;NhKk>s5`%DQFonun}RHZW)ceH(yUGOrCP{1j0$q(5R?T_ z-nGr|*e;zI6qFW~-8^rTn&|CS{JKRn!8`6=l*ngk)F#<5i8CPm(1J@cIQbb;!_gdB>9kZjzX$%7s>%aO`EMDYJgqs<#YrU$S#0ZciehKC|4O7%-GMukBYy-Q{W>sEl&x_!lDD<;4@Vr zDa)Rts<0N*4AMGPy=H}cJcMMGd+(F$et}+KR~37$4{<}Pa@`1mvFhbn7I0QwY?*KO zXSS53#x>mtpJD$#i98)FMG%z452fBU%XUbWOHKik(NAd3vFOz#=v>{xe0u+n>5Kp7 z{K`J;@FRVR@9I1I=JN`|^S$?P-#d$R=YkyRlYjp2W}T5YGbMa??(wU?VwSl&xs1Y! zlZOn3a@GO!O6I!I5iQaQ1@ReI=5$*5;+r$lpBB1iT%7%BW#0?4PkgDAGiY|Hq?f!;%#KT@ znRSAiFVO(uMsV)LWe1w@atB!jB#a(*f0yh*RUfBt@3XE)^E_Q=YeO^!2uPoYlJ z7qKdm=au7AYg{mWYu+c74_`a)XU}<%fjTJ(R2T5G5+tYBUWtL8ahxxG^7yiMD`kJq z64K1&Pv$#Wr9k<-CH)Da8pPr zy(17Is(D7|(Z^&Vr!UOntn!I(Po+8^ZKv+d?z{4zR(TS$tT_b!ph;yL4Tu63%We{u1gXS53y zG$)p^2NV9@BPV(nJH0yc2Z%DfQoFy=JNhXC%4Ek7=y%behW0g2;E(Zm4`{ zbCh#%I{$f{Nh=nN0$#5w67$O9tcQNA74!uYq_%%)#@6v!6qxJJA8U%uwJ{e=zmW1Z z6iZIde-|uo);H#8dv@`BY2||PnDXj=!qqO&0m%vrMzUj1t1J~4+-bjv+~gQ2EXe&b%qMlZr%qi;Al`Q-;XSQ9$B~y55Fp>8vG$SE~kd_d7@9L zPyfqhG&9QN^oK+S7C^(O5>I(%VKIxeOGDopdHC9=V?~-3{ zP1V^icw3Y|9ijUCHmp+|ei`c&F2PYQ8{NfI_8L>U&j0%>s|#}Q&StT?)XIp3>B&8x zyX>`Kx-FHfUyaVAd20IVc~362QeY9fYM7v+bE%wvR!NM`sY55^>$f8rH>Bin-hC>w zG_cQ=Q8|sL8>+5%v(D{okbe3>GQ69`W8;kgwiMwJLK@B~RF#>jHbmcPt_M>$&L*O) z9S5G6M8&~DP%Cue2>s}PMChHt3I(!=qUXr3*&S0Am9@I|yEu78o_UwGhD7zFT1I8! zAEHWl(QK!<=cy5-;q7gcH)ga%UYVu=j)Jm60;S=hA=%zZYD_*h=dUW6$nAgh(iKr# z&nkKjSw@-3cur8S(wAAkYUvyQ=$%ne1ep4A@{@6!$v)CZQh) z8$$Guvm$kzrrE{MXlNLW=!Bd%f@g>YPkdW_m45w=i?Y2Fgoj;h5EC{}_>9Nh3~xg( zpY2LFCvBh_)aCRe-TNL2cV&o$F`{?&mAm%IP?Yk;;zZ{lAWNluxAeT~KB{yRF$1w& z2F;kyL9`blT_DjD+EWJ6LC6{j*t7V=O2_%(Kk*gEaPvYQF z&FHeGk!m-+`R&OnUDh-b%_54jz3#1*)#b>S?~#!~NvQtJm?ZO65R8K%bTwq_?|6yY zN3W1TkKw|ZF-g?R)NWqg`R=z>jZ3N;epbf3k%MJ^BSp@X3KKBh7cJuN`{gQ|FT|(Z zjbtrj3JT{f5%8XnIH3*s7s`+xiIacuBdR8&nFLXska^aVyn-lppQ3#A-^Zjo>E%d$ zQU;K5CK+seK5+O7A^}WQY+n5`IZv^)nxXRfK8Xkhg}JV@XX^~r8XY_G4p}?0lWm@h zG&J3$Y0;Vb5j6WRo-KH>=rsn3kncj35h29%G4njSSZyDl68Cbd=|aBb^@xtIUN>)_ zn#t^{nMR+FuK9@>zvgi|qYr~h=U0=mxo8UshwtP$%_S`0*=0Z|4hHEAqC^*@P6!LO zEa>J!QbJb?a+sBUGs3=HZk7vdoiIuH%dHj9FSL!!0#vD*#iZ?2c|kHR=6Ji0(ly?39q@Rp)f^(aoAob!D;%{jLwD?^GmAB+S>be9DN(F$JEKp#pcJiW>dAD_xEgibGDh!B-w1AxnR1tD|SKBT;Rr!H^mAw2kHe{ zFq_Md7E!~K3zXT9^vm2gn^9xQ{b2#)#0!M4K5am=5JvkaZ~WklvM=-W$D4C5vvE_8 z|2WT1Z>gwT&72pi1R$IXYr%4T+q^fAlKF`&! zU(YScxyh;4RwId>C+X?x6;GeaA~TZ)c=BrH)Xk@F&izc*WLj2Nlv^65`42DYjY^cm z_maoOfPCZn7i(y2wUDZL^`-JV)3By0{uZYC%6R@{O=P`Gj#C=T)b~X*K27XuvZ>y^ z{w7UcIB#|`&2-7t$EH80S#|nKbW-ViQ?}AO^Xfc*g_W;w;?bymlZ~9J_MCF8J`^ag z)xUdI9XhMbzk2eW#fV3uk6Ar(;Y8-KzSty>TsYAz@9<_SalXy@cqvHcg$tMtz-bJpk9y)R!WIW0Mx5r5HKBennY?`8K3w+iW5F*W)x z`qX)E$`_Q$0Z5i_u3VTXQ@F?!)a_rFgFZZ1mcwD*{ZWuFfCe(6hSsZ(y}O*`jj@yO zf}0$z=WW!*FXCG;^?#LqWBrvlmtrAadZnyJ2KDlli)X!>W&vdThW&d~X-ls@V~y%z zWKVzRJ$STYdp`A7^>Mv;-7jz#3wmYd-;Lk9QYla6E58>iZ&mq)_pwgDC0U!5uReW& z_RaY+-URDg=ls+K9*8o#{82lVJ2nk+P{>htuJH;B$z=)h)2225>M}Psu6XC$_VSms zmyhh-!^pd2zUxR*IxJQHE9O7^zq6AWr?~fG-x>S(vFY+epffg+zWT>= z=8X%|VM=|!V1hZ^FpnYgEYz`(6;m#^FK0ID?TXE$#-+~Fa(Lgn}dCBFVXe z|63i%{;e~KH{Tr8-WJ?1CAeQmyqoi2eoNjFGUr;H{Xiu7=r?}p$8QCRYWB>}&Udam z4;*~Qht9A&Pfm%(lh!zAljh>TE9<{^@dOvVE9a53j>=sV5tuC(&3PZw`Bv`RIPXl( zdGLa=-5jVkP3g+3?~PE!Gvw`aik$6*e|~JXDKDMwg3Y}2qi3f`t3Nk<_OARQc4!QoW&OL|Z5jVR&%#=#I1h$9?<41t@z1o`IPX)ZFD7HB&pG?4&lJuS zf1{OZo99RigS=-vBun;WP@4cBMGr8>D;;!Iu zmz{m@&6_uG-n>kbw=YMpRv|l!CasXgcH2&F#nTrpd!sy4??^3yt??+U-kpDb-#m}V zWRK0g?-FjYIeWMv_V^G=kDY1QRnq0|Eq+W6j{WRnW_kY2w6~2-nO~cNUyh{w98*}= zxco*b29c?#cseD>aiHL_6DvdclmOH)ElETIdQuc!R#iXw)uoo;Pfv0NvI+9Ap^b$< z+74X6woyogevIT7Ze2wYAPK2MK?}u`5!&DDk#b@hC31P?6a<+;UX~`W^qY}zq2$I# z$r8%aRH5gxsy{#PqXKg)?n z`~T)=5X*a%m~%Z)@!){ft}~)Wt}QSp9%^Qxk=DA>aq5X*`ti41HJE3kU{*3KvpM6J zhKQ*%q_8rT&CGI1cCuI9pm2RfcCNxBQ%KEXzTZ77Jg6zPCTUxB@nd6&^G{!)sSeqG z+d3zhHZYT9!C5^`*x!D`ZcWY)RvT`>OEzwTnTwATL3uh;967~)-33`ujwy^H38{mat&n{ZES%s~3kIau%5yLmA2tziOPY*~O(Up&&#$A#3? z*|D?W%_T(jq~dzFRKTtcS2~}iA_}&w=`5OsM?vSx?S3-Ag+*tW%=bThBU;S!c#VJ{ zl7#ZJ(*NF}R81&IEk2>>(LHAu<8_DuOXp0$9K@8%wi97#VEL*du#UZ%4PfS^UYF^M z8?Q_B`k(*v)yDdxQyf|^gV;##Sb{>hjT2YdEhZztyi`SZmg3si%`T{_7rg>MP@95| qI8}$NrH}G{4h{@_Mm~W2Kc8&~1ruu)49@E+FBdn^?;b8TSN;He4&7n^ literal 0 HcmV?d00001 diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/clean.bat b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/clean.bat new file mode 100644 index 00000000..c9a2cb06 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/Jin_MiST.sv b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/Jin_MiST.sv new file mode 100644 index 00000000..8d07b864 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/Jin_MiST.sv @@ -0,0 +1,244 @@ +//============================================================================ +// Arcade: Jin +// + +module Jin_MiST( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27, + + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE +); + +`include "rtl/build_id.v" + +localparam CONF_STR = { + "JIN;;", + "O2,Rotate Controls,Off,On;", + "O34,Scanlines,Off,25%,50%,75%;", + "T6,Reset;", + "V,v1.0.0",`BUILD_DATE +}; + +assign LED = 1; + +wire clk_sys, clock_6, clock_1p79, clock_0p89; +wire pll_locked; +pll_mist pll( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys),//36 + .c1(clock_6),//6 + .c2(clock_1p79),//1.79 + .c3(clock_0p89),//0.89 + .locked(pll_locked) + ); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire [10:0] ps2_key; +wire [7:0] audio; +wire hs, vs; +wire blankn; +wire [2:0] g,b; +wire [1:0] r; + +wire [14:0] cart_addr; +wire [15:0] sdram_do; +wire cart_rd; +wire ioctl_downl; +wire [7:0] ioctl_index; +wire ioctl_wr; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; + +data_io data_io ( + .clk_sys ( clk_sys ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS2 ( SPI_SS2 ), + .SPI_DI ( SPI_DI ), + .ioctl_download( ioctl_downl ), + .ioctl_index ( ioctl_index ), + .ioctl_wr ( ioctl_wr ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ) +); + +assign SDRAM_CLK = clk_sys; + +sdram cart +( + .*, + .init ( ~pll_locked ), + .clk ( clk_sys ), + .wtbt ( 2'b00 ), + .dout ( sdram_do ), + .din ( {ioctl_dout, ioctl_dout} ), + .addr ( ioctl_downl ? ioctl_addr : cart_addr ), + .we ( ioctl_downl & ioctl_wr ), + .rd ( !ioctl_downl), + .ready() +); + +reg reset = 1; +reg rom_loaded = 0; +always @(posedge clk_sys) begin + reg ioctl_downlD; + ioctl_downlD <= ioctl_downl; + + if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1; + reset <= status[0] | buttons[1] | status[6] | ~rom_loaded; +end + +defender defender ( + .clock_6 (clock_6), + .clk_1p79 (clock_1p79), + .clk_0p89 (clock_0p89), + .reset ( reset ), + + .video_r ( r ), + .video_g ( g ), + .video_b ( b ), + .video_hs ( hs ), + .video_vs ( vs ), + .video_blankn ( blankn ), + + .audio_out ( audio ), + + .roms_addr ( cart_addr ), + .roms_do ( sdram_do[7:0] ), + + .btn_two_players ( btn_two_players ), + .btn_one_player ( btn_one_player ), + .btn_left_coin ( btn_coin ), + + .btn_fire(m_fire), + .btn_fire2(m_bomb), + + .btn_left(m_left), + .btn_right(m_right), + .btn_down(m_down), + .btn_up(m_up) +); + +mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( + .clk_sys ( clk_sys ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R ( blankn ? {r, r[1] } : 0 ), + .G ( blankn ? g : 0 ), + .B ( blankn ? b : 0 ), + .HSync ( hs ), + .VSync ( vs ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ), + .rotate ( {1'b1,status[2]} ), + .scandoubler_disable( scandoublerD ), + .scanlines ( status[4:3] ), + .ypbpr ( ypbpr ) + ); + +user_io #( + .STRLEN(($size(CONF_STR)>>3))) +user_io( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +wire dac_o; +assign AUDIO_L = dac_o; +assign AUDIO_R = dac_o; + +dac #( + .C_bits(15)) +dac( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i({audio,audio}), + .dac_o(dac_o) + ); + +// Rotated Normal +wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; +wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; +wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; +wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; +wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; +wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; + +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +reg btn_fire2 = 0; +reg btn_fire3 = 0; +reg btn_coin = 0; +wire key_pressed; +wire [7:0] key_code; +wire key_strobe; + +always @(posedge clk_sys) begin + if(key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 + 'h14: btn_fire3 <= key_pressed; // ctrl + 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/YM2149.sv b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/YM2149.sv new file mode 100644 index 00000000..eae73bb3 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/YM2149.sv @@ -0,0 +1,329 @@ +// +// Copyright (c) MikeJ - Jan 2005 +// Copyright (c) 2016-2018 Sorgelig +// +// All rights reserved +// +// Redistribution and use in source and synthezised forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// Redistributions in synthesized form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// Neither the name of the author nor the names of other contributors may +// be used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// + + +// BDIR BC MODE +// 0 0 inactive +// 0 1 read value +// 1 0 write value +// 1 1 set address +// + +module YM2149 +( + input CLK, // Global clock + input CE, // PSG Clock enable + input RESET, // Chip RESET (set all Registers to '0', active hi) + input BDIR, // Bus Direction (0 - read , 1 - write) + input BC, // Bus control + input A8, + input A9_L, + input [7:0] DI, // Data In + output [7:0] DO, // Data Out + output [7:0] CHANNEL_A, // PSG Output channel A + output [7:0] CHANNEL_B, // PSG Output channel B + output [7:0] CHANNEL_C, // PSG Output channel C + + input SEL, + input MODE, + + output [5:0] ACTIVE, + + input [7:0] IOA_in, + output [7:0] IOA_out, + + input [7:0] IOB_in, + output [7:0] IOB_out +); + +assign ACTIVE = ~ymreg[7][5:0]; +assign IOA_out = ymreg[7][6] ? ymreg[14] : 8'hff; +assign IOB_out = ymreg[7][7] ? ymreg[15] : 8'hff; + +reg [7:0] addr; +reg [7:0] ymreg[16]; +wire cs = !A9_L & A8; + +// Write to PSG +reg env_reset; +always @(posedge CLK) begin + if(RESET) begin + ymreg <= '{default:0}; + ymreg[7] <= '1; + addr <= '0; + env_reset <= 0; + end else begin + env_reset <= 0; + if(cs & BDIR) begin + if(BC) addr <= DI; + else if(!addr[7:4]) begin + ymreg[addr[3:0]] <= DI; + env_reset <= (addr == 13); + end + end + end +end + +// Read from PSG +assign DO = dout; +reg [7:0] dout; +always_comb begin + dout = 8'hFF; + if(cs & ~BDIR & BC & !addr[7:4]) begin + case(addr[3:0]) + 0: dout = ymreg[0]; + 1: dout = ymreg[1][3:0]; + 2: dout = ymreg[2]; + 3: dout = ymreg[3][3:0]; + 4: dout = ymreg[4]; + 5: dout = ymreg[5][3:0]; + 6: dout = ymreg[6][4:0]; + 7: dout = ymreg[7]; + 8: dout = ymreg[8][4:0]; + 9: dout = ymreg[9][4:0]; + 10: dout = ymreg[10][4:0]; + 11: dout = ymreg[11]; + 12: dout = ymreg[12]; + 13: dout = ymreg[13][3:0]; + 14: dout = ymreg[7][6] ? ymreg[14] : IOA_in; + 15: dout = ymreg[7][7] ? ymreg[15] : IOB_in; + endcase + end +end + +reg ena_div; +reg ena_div_noise; + +// p_divider +always @(posedge CLK) begin + reg [3:0] cnt_div; + reg noise_div; + + if(CE) begin + ena_div <= 0; + ena_div_noise <= 0; + if(!cnt_div) begin + cnt_div <= {SEL, 3'b111}; + ena_div <= 1; + + noise_div <= (~noise_div); + if (noise_div) ena_div_noise <= 1; + end else begin + cnt_div <= cnt_div - 1'b1; + end + end +end + + +reg [2:0] noise_gen_op; + +// p_noise_gen +always @(posedge CLK) begin + reg [16:0] poly17; + reg [4:0] noise_gen_cnt; + + if(CE) begin + if (ena_div_noise) begin + if (!ymreg[6][4:0] || noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin + noise_gen_cnt <= 0; + poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]}; + end else begin + noise_gen_cnt <= noise_gen_cnt + 1'd1; + end + noise_gen_op <= {3{poly17[0]}}; + end + end +end + +wire [11:0] tone_gen_freq[1:3]; +assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]}; +assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]}; +assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]}; + +reg [3:1] tone_gen_op; + +//p_tone_gens +always @(posedge CLK) begin + integer i; + reg [11:0] tone_gen_cnt[1:3]; + + if(CE) begin + // looks like real chips count up - we need to get the Exact behaviour .. + + for (i = 1; i <= 3; i = i + 1) begin + if(ena_div) begin + if (tone_gen_freq[i]) begin + if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin + tone_gen_cnt[i] <= 0; + tone_gen_op[i] <= ~tone_gen_op[i]; + end else begin + tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1; + end + end else begin + tone_gen_op[i] <= ymreg[7][i]; + tone_gen_cnt[i] <= 0; + end + end + end + end +end + +reg env_ena; +wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0; + +//p_envelope_freq +always @(posedge CLK) begin + reg [15:0] env_gen_cnt; + + if(CE) begin + env_ena <= 0; + if(ena_div) begin + if (env_gen_cnt >= env_gen_comp) begin + env_gen_cnt <= 0; + env_ena <= 1; + end else begin + env_gen_cnt <= (env_gen_cnt + 1'd1); + end + end + end +end + +reg [4:0] env_vol; + +wire is_bot = (env_vol == 5'b00000); +wire is_bot_p1 = (env_vol == 5'b00001); +wire is_top_m1 = (env_vol == 5'b11110); +wire is_top = (env_vol == 5'b11111); + +always @(posedge CLK) begin + reg env_hold; + reg env_inc; + + // envelope shapes + // C AtAlH + // 0 0 x x \___ + // + // 0 1 x x /___ + // + // 1 0 0 0 \\\\ + // + // 1 0 0 1 \___ + // + // 1 0 1 0 \/\/ + // ___ + // 1 0 1 1 \ + // + // 1 1 0 0 //// + // ___ + // 1 1 0 1 / + // + // 1 1 1 0 /\/\ + // + // 1 1 1 1 /___ + + if(env_reset | RESET) begin + // load initial state + if(!ymreg[13][2]) begin // attack + env_vol <= 5'b11111; + env_inc <= 0; // -1 + end else begin + env_vol <= 5'b00000; + env_inc <= 1; // +1 + end + env_hold <= 0; + end + else if(CE) begin + if (env_ena) begin + if (!env_hold) begin + if (env_inc) env_vol <= (env_vol + 5'b00001); + else env_vol <= (env_vol + 5'b11111); + end + + // envelope shape control. + if(!ymreg[13][3]) begin + if(!env_inc) begin // down + if(is_bot_p1) env_hold <= 1; + end else if (is_top) env_hold <= 1; + end else if(ymreg[13][0]) begin // hold = 1 + if(!env_inc) begin // down + if(ymreg[13][1]) begin // alt + if(is_bot) env_hold <= 1; + end else if(is_bot_p1) env_hold <= 1; + end else if(ymreg[13][1]) begin // alt + if(is_top) env_hold <= 1; + end else if(is_top_m1) env_hold <= 1; + end else if(ymreg[13][1]) begin // alternate + if(env_inc == 1'b0) begin // down + if(is_bot_p1) env_hold <= 1; + if(is_bot) begin + env_hold <= 0; + env_inc <= 1; + end + end else begin + if(is_top_m1) env_hold <= 1; + if(is_top) begin + env_hold <= 0; + env_inc <= 0; + end + end + end + end + end +end + +reg [5:0] A,B,C; +always @(posedge CLK) begin + A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4] ? env_vol[4:0] : { ymreg[8][3:0], ymreg[8][3]}}; + B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4] ? env_vol[4:0] : { ymreg[9][3:0], ymreg[9][3]}}; + C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}}; +end + +wire [7:0] volTable[64] = '{ + //YM2149 + 8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04, + 8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13, + 8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47, + 8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff, + + //AY8910 + 8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06, + 8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22, + 8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72, + 8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff +}; + +assign CHANNEL_A = volTable[A]; +assign CHANNEL_B = volTable[B]; +assign CHANNEL_C = volTable[C]; + +endmodule diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/build_id.tcl b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/cpu09l_128.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/cpu09l_128.vhd new file mode 100644 index 00000000..12039bde --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/cpu09l_128.vhd @@ -0,0 +1,5906 @@ +--===========================================================================-- +-- -- +-- Synthesizable 6809 instruction compatible VHDL CPU core -- +-- -- +--===========================================================================-- +-- +-- File name : cpu09l.vhd +-- +-- Entity name : cpu09 +-- +-- Purpose : 6809 instruction compatible CPU core written in VHDL +-- with Last Instruction Cycle, bus available, bus status, +-- and instruction fetch signals. +-- Not cycle compatible with the original 6809 CPU +-- +-- Dependencies : ieee.std_logic_1164 +-- ieee.std_logic_unsigned +-- +-- Author : John E. Kent +-- +-- Email : dilbert57@opencores.org +-- +-- Web : http://opencores.org/project,system09 +-- +-- Description : VMA (valid memory address) is hight whenever a valid memory +-- access is made by an instruction fetch, interrupt vector fetch +-- or a data read or write otherwise it is low indicating an idle +-- bus cycle. +-- IFETCH (instruction fetch output) is high whenever an +-- instruction byte is read i.e. the program counter is applied +-- to the address bus. +-- LIC (last instruction cycle output) is normally low +-- but goes high on the last cycle of an instruction. +-- BA (bus available output) is normally low but goes high while +-- waiting in a Sync instruction state or the CPU is halted +-- i.e. a DMA grant. +-- BS (bus status output) is normally low but goes high during an +-- interrupt or reset vector fetch or the processor is halted +-- i.e. a DMA grant. +-- +-- Copyright (C) 2003 - 2010 John Kent +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +--===========================================================================-- +-- -- +-- Revision History -- +-- -- +--===========================================================================-- +-- +-- Version 0.1 - 26 June 2003 - John Kent +-- Added extra level in state stack +-- fixed some calls to the extended addressing state +-- +-- Version 0.2 - 5 Sept 2003 - John Kent +-- Fixed 16 bit indexed offset (was doing read rather than fetch) +-- Added/Fixed STY and STS instructions. +-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed +-- CMPX Loaded ACCA and ACCB - Now fixed +-- +-- Version 1.0 - 6 Sep 2003 - John Kent +-- Initial release to Open Cores +-- reversed clock edge +-- +-- Version 1.1 - 29 November 2003 John kent +-- ACCA and ACCB indexed offsets are 2's complement. +-- ALU Right Mux now sign extends ACCA & ACCB offsets +-- Absolute Indirect addressing performed a read on the +-- second byte of the address rather than a fetch +-- so it formed an incorrect address. Now fixed. +-- +-- Version 1.2 - 29 November 2003 John Kent +-- LEAX and LEAY affect the Z bit only +-- LEAS and LEAU do not affect any condition codes +-- added an extra ALU control for LEA. +-- +-- Version 1.3 - 12 December 2003 John Kent +-- CWAI did not work, was missed a PUSH_ST on calling +-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for +-- finding this fault. +-- +-- Version 1.4 - 12 December 2003 John Kent +-- Missing cc_ctrl assignment in otherwise case of +-- lea_state resulted in cc_ctrl being latched in +-- that state. +-- The otherwise statement should never be reached, +-- and has been fixed simply to resolve synthesis warnings. +-- +-- Version 1.5 - 17 january 2004 John kent +-- The clear instruction used "alu_ld8" to control the ALU +-- rather than "alu_clr". This mean the Carry was not being +-- cleared correctly. +-- +-- Version 1.6 - 24 January 2004 John Kent +-- Fixed problems in PSHU instruction +-- +-- Version 1.7 - 25 January 2004 John Kent +-- removed redundant "alu_inx" and "alu_dex' +-- Removed "test_alu" and "test_cc" +-- STD instruction did not set condition codes +-- JMP direct was not decoded properly +-- CLR direct performed an unwanted read cycle +-- Bogus "latch_md" in Page2 indexed addressing +-- +-- Version 1.8 - 27 January 2004 John Kent +-- CWAI in decode1_state should increment the PC. +-- ABX is supposed to be an unsigned addition. +-- Added extra ALU function +-- ASR8 slightly changed in the ALU. +-- +-- Version 1.9 - 20 August 2005 +-- LSR8 is now handled in ASR8 and ROR8 case in the ALU, +-- rather than LSR16. There was a problem with single +-- operand instructions using the MD register which is +-- sign extended on the first 8 bit fetch. +-- +-- Version 1.10 - 13 September 2005 +-- TFR & EXG instructions did not work for the Condition Code Register +-- An extra case has been added to the ALU for the alu_tfr control +-- to assign the left ALU input (alu_left) to the condition code +-- outputs (cc_out). +-- +-- Version 1.11 - 16 September 2005 +-- JSR ,X should not predecrement S before calculating the jump address. +-- The reason is that JSR [0,S] needs S to point to the top of the stack +-- to fetch a valid vector address. The solution is to have the addressing +-- mode microcode called before decrementing S and then decrementing S in +-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than +-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are +-- pushed on the stack. This adds one extra bus cycle, but resolves the +-- addressing conflict. I've also removed the pre-decement S in +-- JSR EXTENDED as it also calls JSR_STATE. +-- +-- Version 1.12 - 6th June 2006 +-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR +-- This is different to the 6800. CLR should reset the V bit. +-- +-- Version 1.13 - 7th July 2006 +-- Disable NMI on reset until S Stack pointer has been loaded. +-- Added nmi_enable signal in sp_reg process and nmi_handler process. +-- +-- Version 1.14 - 11th July 2006 +-- 1. Added new state to RTI called rti_entire_state. +-- This state tests the CC register after it has been loaded +-- from the stack. Previously the current CC was tested which +-- was incorrect. The Entire Flag should be set before the +-- interrupt stacks the CC. +-- 2. On bogus Interrupts, int_cc_state went to rti_state, +-- which was an enumerated state, but not defined anywhere. +-- rti_state has been changed to rti_cc_state so that bogus interrupt +-- will perform an RTI after entering that state. +-- 3. Sync should generate an interrupt if the interrupt masks +-- are cleared. If the interrupt masks are set, then an interrupt +-- will cause the the PC to advance to the next instruction. +-- Note that I don't wait for an interrupt to be asserted for +-- three clock cycles. +-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in +-- the Multiply instruction replacing "alu_add16". This is similar +-- to "alu_add16" except it sets the Carry bit to B7 of the result +-- in ACCB, sets the Zero bit if the 16 bit result is zero, but +-- does not affect The Half carry (H), Negative (N) or Overflow (V) +-- flags. The logic was re-arranged so that it adds md or zero so +-- that the Carry condition code is set on zero multiplicands. +-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N) +-- and Zero Flags. It will also affect the Overflow (V) flag although +-- the operation is undefined. It's anyones guess what DAA does to V. +-- +-- Version 1.15 - 25th Feb 2007 - John Kent +-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then" +-- Changed sensitivity lists. +-- +-- Version 1.16 - 5th February 2008 - John Kent +-- FIRQ interrupts should take priority over IRQ Interrupts. +-- This presumably means they should be tested for before IRQ +-- when they happen concurrently. +-- +-- Version 1.17 - 18th February 2008 - John Kent +-- NMI in CWAI should mask IRQ and FIRQ interrupts +-- +-- Version 1.18 - 21st February 2008 - John Kent +-- Removed default register settings in each case statement +-- and placed them at the beginning of the state sequencer. +-- Modified the SYNC instruction so that the interrupt vector(iv) +-- is not set unless an unmasked FIRQ or IRQ is received. +-- +-- Version 1.19 - 25th February 2008 - John Kent +-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE +-- Enumerated separate states for MASKI and MASKIF states +-- Removed code on BSR/JSR in fetch cycle +-- +-- Version 1.20 - 8th October 2011 - John Kent +-- added fetch output which should go high during the fetch cycle +-- +-- Version 1.21 - 8th October 2011 - John Kent +-- added Last Instruction Cycle signal +-- replaced fetch with ifetch (instruction fetch) signal +-- added ba & bs (bus available & bus status) signals +-- +-- Version 1.22 - 2011-10-29 John Kent +-- The halt state isn't correct. +-- The halt state is entered into from the fetch_state +-- It returned to the fetch state which may re-run an execute cycle +-- on the accumulator and it won't necessarily be the last instruction cycle +-- I've changed the halt state to return to the decode1_state +-- +-- Version 1.23 - 2011-10-30 John Kent +-- sample halt in the change_state process if lic is high (last instruction cycle) +-- +-- Version 1.24 - 2011-11-01 John Kent +-- Handle interrupts in change_state process +-- Sample interrupt inputs on last instruction cycle +-- Remove iv_ctrl and implement iv (interrupt vector) in change_state process. +-- Generate fic (first instruction cycle) from lic (last instruction cycle) +-- and use it to complete the dual operand execute cycle before servicing +-- halt or interrupts requests. +-- rename lic to lic_out on the entity declaration so that lic can be tested internally. +-- add int_firq1_state and int_nmirq1_state to allow for the dual operand execute cycle +-- integrated nmi_ctrl into change_state process +-- Reduces the microcode state stack to one entry (saved_state) +-- imm16_state jumps directly to the fetch_state +-- pull_return_lo states jumps directly to the fetch_state +-- duplicate andcc_state as cwai_state +-- rename exg1_state as exg2 state and duplicate tfr_state as exg1_state +-- +-- Version 1.25 - 2011-11-27 John Kent +-- Changed the microcode for saving registers on an interrupt into a microcode subroutine. +-- Removed SWI servicing from the change state process and made SWI, SWI2 & SWI3 +-- call the interrupt microcode subroutine. +-- Added additional states for nmi, and irq for interrupt servicing. +-- Added additional states for nmi/irq, firq, and swi interrupts to mask I & F flags. +-- +-- Version 1.26 - 2013-03-18 John Kent +-- pre-initialized cond_true variable to true in state sequencer +-- re-arranged change_state process slightly +-- +-- Version 1.27 - 2015-05-30 John Kent +-- Added test in state machine for masked IRQ and FIRQ in Sync_state. +-- +-- Version 1.28 - 2015-05-30 John Kent. +-- Moved IRQ and FIRQ test from state machine to the state sequencer Sync_state. +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity cpu09 is + port ( + clk : in std_logic; -- E clock input (falling edge) + rst : in std_logic; -- reset input (active high) + vma : out std_logic; -- valid memory address (active high) + lic_out : out std_logic; -- last instruction cycle (active high) + ifetch : out std_logic; -- instruction fetch cycle (active high) + opfetch : out std_logic; -- opcode fetch (active high) + ba : out std_logic; -- bus available (high on sync wait or DMA grant) + bs : out std_logic; -- bus status (high on interrupt or reset vector fetch or DMA grant) + addr : out std_logic_vector(15 downto 0); -- address bus output + rw : out std_logic; -- read not write output + data_out : out std_logic_vector(7 downto 0); -- data bus output + data_in : in std_logic_vector(7 downto 0); -- data bus input + irq : in std_logic; -- interrupt request input (active high) + firq : in std_logic; -- fast interrupt request input (active high) + nmi : in std_logic; -- non maskable interrupt request input (active high) + halt : in std_logic; -- halt input (active high) grants DMA + hold : in std_logic -- hold input (active high) extend bus cycle + ); +end cpu09; + +architecture rtl of cpu09 is + + constant EBIT : integer := 7; + constant FBIT : integer := 6; + constant HBIT : integer := 5; + constant IBIT : integer := 4; + constant NBIT : integer := 3; + constant ZBIT : integer := 2; + constant VBIT : integer := 1; + constant CBIT : integer := 0; + + -- + -- Interrupt vector modifiers + -- + constant RST_VEC : std_logic_vector(2 downto 0) := "111"; + constant NMI_VEC : std_logic_vector(2 downto 0) := "110"; + constant SWI_VEC : std_logic_vector(2 downto 0) := "101"; + constant IRQ_VEC : std_logic_vector(2 downto 0) := "100"; + constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011"; + constant SWI2_VEC : std_logic_vector(2 downto 0) := "010"; + constant SWI3_VEC : std_logic_vector(2 downto 0) := "001"; + constant RESV_VEC : std_logic_vector(2 downto 0) := "000"; + + type state_type is (-- Start off in Reset + reset_state, + -- Fetch Interrupt Vectors (including reset) + vect_lo_state, vect_hi_state, vect_idle_state, + -- Fetch Instruction Cycle + fetch_state, + -- Decode Instruction Cycles + decode1_state, decode2_state, decode3_state, + -- Calculate Effective Address + imm16_state, + indexed_state, index8_state, index16_state, index16_2_state, + pcrel8_state, pcrel16_state, pcrel16_2_state, + indexaddr_state, indexaddr2_state, + postincr1_state, postincr2_state, + indirect_state, indirect2_state, indirect3_state, + extended_state, + -- single ops + single_op_read_state, + single_op_exec_state, + single_op_write_state, + -- Dual op states + dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state, + dual_op_write8_state, dual_op_write16_state, + -- + sync_state, halt_state, cwai_state, + -- + andcc_state, orcc_state, + tfr_state, + exg_state, exg1_state, exg2_state, + lea_state, + -- Multiplication + mul_state, mulea_state, muld_state, + mul0_state, mul1_state, mul2_state, mul3_state, + mul4_state, mul5_state, mul6_state, mul7_state, + -- Branches + lbranch_state, sbranch_state, + -- Jumps, Subroutine Calls and Returns + jsr_state, jmp_state, + push_return_hi_state, push_return_lo_state, + pull_return_hi_state, pull_return_lo_state, + -- Interrupt cycles + int_nmi_state, int_nmi1_state, + int_irq_state, int_irq1_state, + int_firq_state, int_firq1_state, + int_entire_state, int_fast_state, + int_pcl_state, int_pch_state, + int_upl_state, int_uph_state, + int_iyl_state, int_iyh_state, + int_ixl_state, int_ixh_state, + int_dp_state, + int_accb_state, int_acca_state, + int_cc_state, + int_cwai_state, + int_nmimask_state, int_firqmask_state, int_swimask_state, int_irqmask_state, + -- Return From Interrupt + rti_cc_state, rti_entire_state, + rti_acca_state, rti_accb_state, + rti_dp_state, + rti_ixl_state, rti_ixh_state, + rti_iyl_state, rti_iyh_state, + rti_upl_state, rti_uph_state, + rti_pcl_state, rti_pch_state, + -- Push Registers using SP + pshs_state, + pshs_pcl_state, pshs_pch_state, + pshs_upl_state, pshs_uph_state, + pshs_iyl_state, pshs_iyh_state, + pshs_ixl_state, pshs_ixh_state, + pshs_dp_state, + pshs_acca_state, pshs_accb_state, + pshs_cc_state, + -- Pull Registers using SP + puls_state, + puls_cc_state, + puls_acca_state, puls_accb_state, + puls_dp_state, + puls_ixl_state, puls_ixh_state, + puls_iyl_state, puls_iyh_state, + puls_upl_state, puls_uph_state, + puls_pcl_state, puls_pch_state, + -- Push Registers using UP + pshu_state, + pshu_pcl_state, pshu_pch_state, + pshu_spl_state, pshu_sph_state, + pshu_iyl_state, pshu_iyh_state, + pshu_ixl_state, pshu_ixh_state, + pshu_dp_state, + pshu_acca_state, pshu_accb_state, + pshu_cc_state, + -- Pull Registers using UP + pulu_state, + pulu_cc_state, + pulu_acca_state, pulu_accb_state, + pulu_dp_state, + pulu_ixl_state, pulu_ixh_state, + pulu_iyl_state, pulu_iyh_state, + pulu_spl_state, pulu_sph_state, + pulu_pcl_state, pulu_pch_state ); + + type st_type is (reset_st, push_st, idle_st ); + type iv_type is (latch_iv, swi3_iv, swi2_iv, firq_iv, irq_iv, swi_iv, nmi_iv, reset_iv); + type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad ); + type dout_type is (cc_dout, acca_dout, accb_dout, dp_dout, + ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout, + up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout, + pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout ); + type op_type is (reset_op, fetch_op, latch_op ); + type pre_type is (reset_pre, fetch_pre, latch_pre ); + type cc_type is (reset_cc, load_cc, pull_cc, latch_cc ); + type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca ); + type accb_type is (reset_accb, load_accb, pull_accb, latch_accb ); + type dp_type is (reset_dp, load_dp, pull_dp, latch_dp ); + type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix ); + type iy_type is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy ); + type sp_type is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp ); + type up_type is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up ); + type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc ); + type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md ); + type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea ); + type left_type is (cc_left, acca_left, accb_left, dp_left, + ix_left, iy_left, up_left, sp_left, + accd_left, md_left, pc_left, ea_left ); + type right_type is (ea_right, zero_right, one_right, two_right, + acca_right, accb_right, accd_right, + md_right, md_sign5_right, md_sign8_right ); + type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc, + alu_and, alu_ora, alu_eor, + alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com, + alu_lsr16, alu_lsl16, + alu_ror8, alu_rol8, alu_mul, + alu_asr8, alu_asl8, alu_lsr8, + alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx, + alu_seif, alu_sei, alu_see, alu_cle, + alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa ); + + signal op_code: std_logic_vector(7 downto 0); + signal pre_code: std_logic_vector(7 downto 0); + signal acca: std_logic_vector(7 downto 0); + signal accb: std_logic_vector(7 downto 0); + signal cc: std_logic_vector(7 downto 0); + signal cc_out: std_logic_vector(7 downto 0); + signal dp: std_logic_vector(7 downto 0); + signal xreg: std_logic_vector(15 downto 0); + signal yreg: std_logic_vector(15 downto 0); + signal sp: std_logic_vector(15 downto 0); + signal up: std_logic_vector(15 downto 0); + signal ea: std_logic_vector(15 downto 0); + signal pc: std_logic_vector(15 downto 0); + signal md: std_logic_vector(15 downto 0); + signal left: std_logic_vector(15 downto 0); + signal right: std_logic_vector(15 downto 0); + signal out_alu: std_logic_vector(15 downto 0); + signal iv: std_logic_vector(2 downto 0); + signal nmi_req: std_logic; + signal nmi_ack: std_logic; + signal nmi_enable: std_logic; + signal fic: std_logic; -- first instruction cycle + signal lic: std_logic; -- last instruction cycle + + signal state: state_type; + signal next_state: state_type; + signal return_state: state_type; + signal saved_state: state_type; + signal st_ctrl: st_type; + signal iv_ctrl: iv_type; + signal pc_ctrl: pc_type; + signal ea_ctrl: ea_type; + signal op_ctrl: op_type; + signal pre_ctrl: pre_type; + signal md_ctrl: md_type; + signal acca_ctrl: acca_type; + signal accb_ctrl: accb_type; + signal ix_ctrl: ix_type; + signal iy_ctrl: iy_type; + signal cc_ctrl: cc_type; + signal dp_ctrl: dp_type; + signal sp_ctrl: sp_type; + signal up_ctrl: up_type; + signal left_ctrl: left_type; + signal right_ctrl: right_type; + signal alu_ctrl: alu_type; + signal addr_ctrl: addr_type; + signal dout_ctrl: dout_type; + + +begin + +---------------------------------- +-- +-- State machine stack +-- +---------------------------------- +--state_stack_proc: process( clk, hold, state_stack, st_ctrl, +-- return_state, fetch_state ) +state_stack_proc: process( clk, st_ctrl, return_state ) +begin + if clk'event and clk = '0' then + if hold = '0' then + case st_ctrl is + when reset_st => + saved_state <= fetch_state; + when push_st => + saved_state <= return_state; + when others => + null; + end case; + end if; + end if; +end process; + +---------------------------------- +-- +-- Interrupt Vector control +-- +---------------------------------- +-- +int_vec_proc: process( clk, iv_ctrl ) +begin + if clk'event and clk = '0' then + if hold = '0' then + case iv_ctrl is + when reset_iv => + iv <= RST_VEC; + when nmi_iv => + iv <= NMI_VEC; + when swi_iv => + iv <= SWI_VEC; + when irq_iv => + iv <= IRQ_VEC; + when firq_iv => + iv <= FIRQ_VEC; + when swi2_iv => + iv <= SWI2_VEC; + when swi3_iv => + iv <= SWI3_VEC; + when others => + null; + end case; + end if; -- hold + end if; -- clk +end process; + +---------------------------------- +-- +-- Program Counter Control +-- +---------------------------------- + +--pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in ) +pc_reg: process( clk ) +begin + if clk'event and clk = '0' then + if hold = '0' then + case pc_ctrl is + when reset_pc => + pc <= (others=>'0'); + when load_pc => + pc <= out_alu(15 downto 0); + when pull_lo_pc => + pc(7 downto 0) <= data_in; + when pull_hi_pc => + pc(15 downto 8) <= data_in; + when incr_pc => + pc <= pc + 1; + when others => + null; + end case; + end if; + end if; +end process; + +---------------------------------- +-- +-- Effective Address Control +-- +---------------------------------- + +--ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp ) +ea_reg: process( clk ) +begin + + if clk'event and clk = '0' then + if hold= '0' then + case ea_ctrl is + when reset_ea => + ea <= (others=>'0'); + when fetch_first_ea => + ea(7 downto 0) <= data_in; + ea(15 downto 8) <= dp; + when fetch_next_ea => + ea(15 downto 8) <= ea(7 downto 0); + ea(7 downto 0) <= data_in; + when load_ea => + ea <= out_alu(15 downto 0); + when others => + null; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- Accumulator A +-- +-------------------------------- +--acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in ) +acca_reg : process( clk ) +begin + if clk'event and clk = '0' then + if hold = '0' then + case acca_ctrl is + when reset_acca => + acca <= (others=>'0'); + when load_acca => + acca <= out_alu(7 downto 0); + when load_hi_acca => + acca <= out_alu(15 downto 8); + when pull_acca => + acca <= data_in; + when others => + null; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- Accumulator B +-- +-------------------------------- +--accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in ) +accb_reg : process( clk ) +begin + if clk'event and clk = '0' then + if hold = '0' then + case accb_ctrl is + when reset_accb => + accb <= (others=>'0'); + when load_accb => + accb <= out_alu(7 downto 0); + when pull_accb => + accb <= data_in; + when others => + null; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- X Index register +-- +-------------------------------- +--ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in ) +ix_reg : process( clk ) +begin + if clk'event and clk = '0' then + if hold = '0' then + case ix_ctrl is + when reset_ix => + xreg <= (others=>'0'); + when load_ix => + xreg <= out_alu(15 downto 0); + when pull_hi_ix => + xreg(15 downto 8) <= data_in; + when pull_lo_ix => + xreg(7 downto 0) <= data_in; + when others => + null; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- Y Index register +-- +-------------------------------- +--iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in ) +iy_reg : process( clk ) +begin + if clk'event and clk = '0' then + if hold = '0' then + case iy_ctrl is + when reset_iy => + yreg <= (others=>'0'); + when load_iy => + yreg <= out_alu(15 downto 0); + when pull_hi_iy => + yreg(15 downto 8) <= data_in; + when pull_lo_iy => + yreg(7 downto 0) <= data_in; + when others => + null; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- S stack pointer +-- +-------------------------------- +--sp_reg : process( clk, sp_ctrl, hold, sp, out_alu, data_in, nmi_enable ) +sp_reg : process( clk ) +begin + if clk'event and clk = '0' then + if hold = '0' then + case sp_ctrl is + when reset_sp => + sp <= (others=>'0'); + nmi_enable <= '0'; + when load_sp => + sp <= out_alu(15 downto 0); + nmi_enable <= '1'; + when pull_hi_sp => + sp(15 downto 8) <= data_in; + when pull_lo_sp => + sp(7 downto 0) <= data_in; + nmi_enable <= '1'; + when others => + null; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- U stack pointer +-- +-------------------------------- +--up_reg : process( clk, up_ctrl, hold, up, out_alu, data_in ) +up_reg : process( clk ) +begin + if clk'event and clk = '0' then + if hold = '0' then + case up_ctrl is + when reset_up => + up <= (others=>'0'); + when load_up => + up <= out_alu(15 downto 0); + when pull_hi_up => + up(15 downto 8) <= data_in; + when pull_lo_up => + up(7 downto 0) <= data_in; + when others => + null; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- Memory Data +-- +-------------------------------- +--md_reg : process( clk, md_ctrl, hold, out_alu, data_in, md ) +md_reg : process( clk ) +begin + if clk'event and clk = '0' then + if hold = '0' then + case md_ctrl is + when reset_md => + md <= (others=>'0'); + when load_md => + md <= out_alu(15 downto 0); + when fetch_first_md => -- sign extend md for branches + md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) & + data_in(7) & data_in(7) & data_in(7) & data_in(7) ; + md(7 downto 0) <= data_in; + when fetch_next_md => + md(15 downto 8) <= md(7 downto 0); + md(7 downto 0) <= data_in; + when shiftl_md => + md(15 downto 1) <= md(14 downto 0); + md(0) <= '0'; + when others => + null; + end case; + end if; + end if; +end process; + + +---------------------------------- +-- +-- Condition Codes +-- +---------------------------------- + +--cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in ) +cc_reg: process( clk ) +begin + if clk'event and clk = '0' then + if hold = '0' then + case cc_ctrl is + when reset_cc => + cc <= "11010000"; -- set EBIT, FBIT & IBIT + when load_cc => + cc <= cc_out; + when pull_cc => + cc <= data_in; + when others => + null; + end case; + end if; + end if; +end process; + +---------------------------------- +-- +-- Direct Page register +-- +---------------------------------- + +--dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in ) +dp_reg: process( clk ) +begin + if clk'event and clk = '0' then + if hold = '0' then + case dp_ctrl is + when reset_dp => + dp <= (others=>'0'); + when load_dp => + dp <= out_alu(7 downto 0); + when pull_dp => + dp <= data_in; + when others => + null; + end case; + end if; + end if; +end process; + + +---------------------------------- +-- +-- op code register +-- +---------------------------------- + +--op_reg: process( clk, op_ctrl, hold, op_code, data_in ) +op_reg: process( clk ) +begin + if clk'event and clk = '0' then + if hold = '0' then + case op_ctrl is + when reset_op => + op_code <= "00010010"; + when fetch_op => + op_code <= data_in; + when others => + null; + end case; + end if; + end if; +end process; + + +---------------------------------- +-- +-- pre byte op code register +-- +---------------------------------- + +--pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in ) +pre_reg: process( clk ) +begin + if clk'event and clk = '0' then + if hold = '0' then + case pre_ctrl is + when reset_pre => + pre_code <= (others=>'0'); + when fetch_pre => + pre_code <= data_in; + when others => + null; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- state machine +-- +-------------------------------- + +--change_state: process( clk, rst, state, hold, next_state ) +change_state: process( clk ) +begin + if clk'event and clk = '0' then + if rst = '1' then + fic <= '0'; + nmi_ack <= '0'; + state <= reset_state; + elsif hold = '0' then + fic <= lic; + -- + -- nmi request is not cleared until nmi input goes low + -- + if (nmi_req = '0') and (nmi_ack='1') then + nmi_ack <= '0'; + end if; + + if (nmi_req = '1') and (nmi_ack = '0') and (state = int_nmimask_state) then + nmi_ack <= '1'; + end if; + + if lic = '1' then + if halt = '1' then + state <= halt_state; + + -- service non maskable interrupts + elsif (nmi_req = '1') and (nmi_ack = '0') then + state <= int_nmi_state; + -- + -- FIRQ & IRQ are level sensitive + -- + elsif (firq = '1') and (cc(FBIT) = '0') then + state <= int_firq_state; + + elsif (irq = '1') and (cc(IBIT) = '0') then + state <= int_irq_state; + -- + -- Version 1.27 2015-05-30 + -- Exit sync_state on masked interrupt. + -- + -- Version 1.28 2015-05-30 + -- Move this code to the state sequencer + -- near line 5566. + -- + -- elsif (state = sync_state) and ((firq = '1') or (irq = '1'))then + -- state <= fetch_state; + -- + else + state <= next_state; + end if; -- halt, nmi, firq, irq + else + state <= next_state; + end if; -- lic + end if; -- reset/hold + end if; -- clk +end process; + +------------------------------------ +-- +-- Detect Edge of NMI interrupt +-- +------------------------------------ + +--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable ) +nmi_handler : process( rst, clk ) +begin + if rst='1' then + nmi_req <= '0'; + elsif clk'event and clk='0' then + if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then + nmi_req <= '1'; + else + if (nmi='0') and (nmi_ack='1') then + nmi_req <= '0'; + end if; + end if; + end if; +end process; + + +---------------------------------- +-- +-- Address output multiplexer +-- +---------------------------------- + +addr_mux: process( addr_ctrl, pc, ea, up, sp, iv ) +begin + ifetch <= '0'; + vma <= '1'; + case addr_ctrl is + when fetch_ad => + addr <= pc; + rw <= '1'; + ifetch <= '1'; + when read_ad => + addr <= ea; + rw <= '1'; + when write_ad => + addr <= ea; + rw <= '0'; + when pushs_ad => + addr <= sp; + rw <= '0'; + when pulls_ad => + addr <= sp; + rw <= '1'; + when pushu_ad => + addr <= up; + rw <= '0'; + when pullu_ad => + addr <= up; + rw <= '1'; + when int_hi_ad => + addr <= "111111111111" & iv & "0"; + rw <= '1'; + when int_lo_ad => + addr <= "111111111111" & iv & "1"; + rw <= '1'; + when others => + addr <= "1111111111111111"; + rw <= '1'; + vma <= '0'; + end case; +end process; + +-------------------------------- +-- +-- Data Bus output +-- +-------------------------------- +dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc ) +begin + case dout_ctrl is + when cc_dout => -- condition code register + data_out <= cc; + when acca_dout => -- accumulator a + data_out <= acca; + when accb_dout => -- accumulator b + data_out <= accb; + when dp_dout => -- direct page register + data_out <= dp; + when ix_lo_dout => -- X index reg + data_out <= xreg(7 downto 0); + when ix_hi_dout => -- X index reg + data_out <= xreg(15 downto 8); + when iy_lo_dout => -- Y index reg + data_out <= yreg(7 downto 0); + when iy_hi_dout => -- Y index reg + data_out <= yreg(15 downto 8); + when up_lo_dout => -- U stack pointer + data_out <= up(7 downto 0); + when up_hi_dout => -- U stack pointer + data_out <= up(15 downto 8); + when sp_lo_dout => -- S stack pointer + data_out <= sp(7 downto 0); + when sp_hi_dout => -- S stack pointer + data_out <= sp(15 downto 8); + when md_lo_dout => -- alu output + data_out <= md(7 downto 0); + when md_hi_dout => -- alu output + data_out <= md(15 downto 8); + when pc_lo_dout => -- low order pc + data_out <= pc(7 downto 0); + when pc_hi_dout => -- high order pc + data_out <= pc(15 downto 8); + end case; +end process; + +---------------------------------- +-- +-- Left Mux +-- +---------------------------------- + +left_mux: process( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md ) +begin + case left_ctrl is + when cc_left => + left(15 downto 8) <= "00000000"; + left(7 downto 0) <= cc; + when acca_left => + left(15 downto 8) <= "00000000"; + left(7 downto 0) <= acca; + when accb_left => + left(15 downto 8) <= "00000000"; + left(7 downto 0) <= accb; + when dp_left => + left(15 downto 8) <= "00000000"; + left(7 downto 0) <= dp; + when accd_left => + left(15 downto 8) <= acca; + left(7 downto 0) <= accb; + when md_left => + left <= md; + when ix_left => + left <= xreg; + when iy_left => + left <= yreg; + when sp_left => + left <= sp; + when up_left => + left <= up; + when pc_left => + left <= pc; + when others => +-- when ea_left => + left <= ea; + end case; +end process; + +---------------------------------- +-- +-- Right Mux +-- +---------------------------------- + +right_mux: process( right_ctrl, md, acca, accb, ea ) +begin + case right_ctrl is + when ea_right => + right <= ea; + when zero_right => + right <= "0000000000000000"; + when one_right => + right <= "0000000000000001"; + when two_right => + right <= "0000000000000010"; + when acca_right => + if acca(7) = '0' then + right <= "00000000" & acca(7 downto 0); + else + right <= "11111111" & acca(7 downto 0); + end if; + when accb_right => + if accb(7) = '0' then + right <= "00000000" & accb(7 downto 0); + else + right <= "11111111" & accb(7 downto 0); + end if; + when accd_right => + right <= acca & accb; + when md_sign5_right => + if md(4) = '0' then + right <= "00000000000" & md(4 downto 0); + else + right <= "11111111111" & md(4 downto 0); + end if; + when md_sign8_right => + if md(7) = '0' then + right <= "00000000" & md(7 downto 0); + else + right <= "11111111" & md(7 downto 0); + end if; + when others => +-- when md_right => + right <= md; + end case; +end process; + +---------------------------------- +-- +-- Arithmetic Logic Unit +-- +---------------------------------- + +alu: process( alu_ctrl, cc, left, right, out_alu, cc_out ) +variable valid_lo, valid_hi : boolean; +variable carry_in : std_logic; +variable daa_reg : std_logic_vector(7 downto 0); +begin + + case alu_ctrl is + when alu_adc | alu_sbc | + alu_rol8 | alu_ror8 => + carry_in := cc(CBIT); + when alu_asr8 => + carry_in := left(7); + when others => + carry_in := '0'; + end case; + + valid_lo := left(3 downto 0) <= 9; + valid_hi := left(7 downto 4) <= 9; + + -- + -- CBIT HBIT VHI VLO DAA + -- 0 0 0 0 66 (!VHI : hi_nybble>8) + -- 0 0 0 1 60 + -- 0 0 1 1 00 + -- 0 0 1 0 06 ( VHI : hi_nybble<=8) + -- + -- 0 1 1 0 06 + -- 0 1 1 1 06 + -- 0 1 0 1 66 + -- 0 1 0 0 66 + -- + -- 1 1 0 0 66 + -- 1 1 0 1 66 + -- 1 1 1 1 66 + -- 1 1 1 0 66 + -- + -- 1 0 1 0 66 + -- 1 0 1 1 60 + -- 1 0 0 1 60 + -- 1 0 0 0 66 + -- + -- 66 = (!VHI & !VLO) + (CBIT & HBIT) + (HBIT & !VHI) + (CBIT & !VLO) + -- = (CBIT & (HBIT + !VLO)) + (!VHI & (HBIT + !VLO)) + -- = (!VLO & (CBIT + !VHI)) + (HBIT & (CBIT + !VHI)) + -- 60 = (CBIT & !HBIT & VLO) + (!HBIT & !VHI & VLO) + -- = (!HBIT & VLO & (CBIT + !VHI)) + -- 06 = (!CBIT & VHI & (!VLO + VHI) + -- 00 = (!CBIT & !HBIT & VHI & VLO) + -- + if (cc(CBIT) = '0') then + -- CBIT=0 + if( cc(HBIT) = '0' ) then + -- HBIT=0 + if valid_lo then + -- lo <= 9 (no overflow in low nybble) + if valid_hi then + -- hi <= 9 (no overflow in either low or high nybble) + daa_reg := "00000000"; + else + -- hi > 9 (overflow in high nybble only) + daa_reg := "01100000"; + end if; + else + -- lo > 9 (overflow in low nybble) + -- + -- since there is already an overflow in the low nybble + -- you need to make room in the high nybble for the low nybble carry + -- so compare the high nybble with 8 rather than 9 + -- if the high nybble is 9 there will be an overflow on the high nybble + -- after the decimal adjust which means it will roll over to an invalid BCD digit + -- + if( left(7 downto 4) <= 8 ) then + -- hi <= 8 (overflow in low nybble only) + daa_reg := "00000110"; + else + -- hi > 8 (overflow in low and high nybble) + daa_reg := "01100110"; + end if; + end if; + else + -- HBIT=1 (overflow in low nybble) + if valid_hi then + -- hi <= 9 (overflow in low nybble only) + daa_reg := "00000110"; + else + -- hi > 9 (overflow in low and high nybble) + daa_reg := "01100110"; + end if; + end if; + else + -- CBIT=1 (carry => overflow in high nybble) + if ( cc(HBIT) = '0' )then + -- HBIT=0 (half carry clear => may or may not be an overflow in the low nybble) + if valid_lo then + -- lo <=9 (overflow in high nybble only) + daa_reg := "01100000"; + else + -- lo >9 (overflow in low and high nybble) + daa_reg := "01100110"; + end if; + else + -- HBIT=1 (overflow in low and high nybble) + daa_reg := "01100110"; + end if; + end if; + + case alu_ctrl is + when alu_add8 | alu_inc | + alu_add16 | alu_adc | alu_mul => + out_alu <= left + right + ("000000000000000" & carry_in); + when alu_sub8 | alu_dec | + alu_sub16 | alu_sbc => + out_alu <= left - right - ("000000000000000" & carry_in); + when alu_abx => + out_alu <= left + ("00000000" & right(7 downto 0)) ; + when alu_and => + out_alu <= left and right; -- and/bit + when alu_ora => + out_alu <= left or right; -- or + when alu_eor => + out_alu <= left xor right; -- eor/xor + when alu_lsl16 | alu_asl8 | alu_rol8 => + out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16 + when alu_lsr16 => + out_alu <= carry_in & left(15 downto 1); -- lsr16 + when alu_lsr8 | alu_asr8 | alu_ror8 => + out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror8/asr8/lsr8 + when alu_neg => + out_alu <= right - left; -- neg (right=0) + when alu_com => + out_alu <= not left; + when alu_clr | alu_ld8 | alu_ld16 | alu_lea => + out_alu <= right; -- clr, ld + when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr => + out_alu <= left; + when alu_daa => + out_alu <= left + ("00000000" & daa_reg); + when alu_sex => + if left(7) = '0' then + out_alu <= "00000000" & left(7 downto 0); + else + out_alu <= "11111111" & left(7 downto 0); + end if; + when others => + out_alu <= left; -- nop + end case; + + -- + -- carry bit + -- + case alu_ctrl is + when alu_add8 | alu_adc => + cc_out(CBIT) <= (left(7) and right(7)) or + (left(7) and not out_alu(7)) or + (right(7) and not out_alu(7)); + when alu_sub8 | alu_sbc => + cc_out(CBIT) <= ((not left(7)) and right(7)) or + ((not left(7)) and out_alu(7)) or + (right(7) and out_alu(7)); + when alu_add16 => + cc_out(CBIT) <= (left(15) and right(15)) or + (left(15) and not out_alu(15)) or + (right(15) and not out_alu(15)); + when alu_sub16 => + cc_out(CBIT) <= ((not left(15)) and right(15)) or + ((not left(15)) and out_alu(15)) or + (right(15) and out_alu(15)); + when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 => + cc_out(CBIT) <= left(0); + when alu_rol8 | alu_asl8 => + cc_out(CBIT) <= left(7); + when alu_lsl16 => + cc_out(CBIT) <= left(15); + when alu_com => + cc_out(CBIT) <= '1'; + when alu_neg | alu_clr => + cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or + out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0); + when alu_mul => + cc_out(CBIT) <= out_alu(7); + when alu_daa => + if ( daa_reg(7 downto 4) = "0110" ) then + cc_out(CBIT) <= '1'; + else + cc_out(CBIT) <= '0'; + end if; + when alu_andcc => + cc_out(CBIT) <= left(CBIT) and cc(CBIT); + when alu_orcc => + cc_out(CBIT) <= left(CBIT) or cc(CBIT); + when alu_tfr => + cc_out(CBIT) <= left(CBIT); + when others => + cc_out(CBIT) <= cc(CBIT); + end case; + -- + -- Zero flag + -- + case alu_ctrl is + when alu_add8 | alu_sub8 | + alu_adc | alu_sbc | + alu_and | alu_ora | alu_eor | + alu_inc | alu_dec | + alu_neg | alu_com | alu_clr | + alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 | + alu_ld8 | alu_st8 | alu_sex | alu_daa => + cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or + out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) ); + when alu_add16 | alu_sub16 | alu_mul | + alu_lsl16 | alu_lsr16 | + alu_ld16 | alu_st16 | alu_lea => + cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or + out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or + out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or + out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) ); + when alu_andcc => + cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT); + when alu_orcc => + cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT); + when alu_tfr => + cc_out(ZBIT) <= left(ZBIT); + when others => + cc_out(ZBIT) <= cc(ZBIT); + end case; + + -- + -- negative flag + -- + case alu_ctrl is + when alu_add8 | alu_sub8 | + alu_adc | alu_sbc | + alu_and | alu_ora | alu_eor | + alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 | + alu_inc | alu_dec | alu_neg | alu_com | alu_clr | + alu_ld8 | alu_st8 | alu_sex | alu_daa => + cc_out(NBIT) <= out_alu(7); + when alu_add16 | alu_sub16 | + alu_lsl16 | alu_lsr16 | + alu_ld16 | alu_st16 => + cc_out(NBIT) <= out_alu(15); + when alu_andcc => + cc_out(NBIT) <= left(NBIT) and cc(NBIT); + when alu_orcc => + cc_out(NBIT) <= left(NBIT) or cc(NBIT); + when alu_tfr => + cc_out(NBIT) <= left(NBIT); + when others => + cc_out(NBIT) <= cc(NBIT); + end case; + + -- + -- Interrupt mask flag + -- + case alu_ctrl is + when alu_andcc => + cc_out(IBIT) <= left(IBIT) and cc(IBIT); + when alu_orcc => + cc_out(IBIT) <= left(IBIT) or cc(IBIT); + when alu_tfr => + cc_out(IBIT) <= left(IBIT); + when alu_seif | alu_sei => + cc_out(IBIT) <= '1'; + when others => + cc_out(IBIT) <= cc(IBIT); -- interrupt mask + end case; + + -- + -- Half Carry flag + -- + case alu_ctrl is + when alu_add8 | alu_adc => + cc_out(HBIT) <= (left(3) and right(3)) or + (right(3) and not out_alu(3)) or + (left(3) and not out_alu(3)); + when alu_andcc => + cc_out(HBIT) <= left(HBIT) and cc(HBIT); + when alu_orcc => + cc_out(HBIT) <= left(HBIT) or cc(HBIT); + when alu_tfr => + cc_out(HBIT) <= left(HBIT); + when others => + cc_out(HBIT) <= cc(HBIT); + end case; + + -- + -- Overflow flag + -- + case alu_ctrl is + when alu_add8 | alu_adc => + cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or + ((not left(7)) and (not right(7)) and out_alu(7)); + when alu_sub8 | alu_sbc => + cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or + ((not left(7)) and right(7) and out_alu(7)); + when alu_add16 => + cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or + ((not left(15)) and (not right(15)) and out_alu(15)); + when alu_sub16 => + cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or + ((not left(15)) and right(15) and out_alu(15)); + when alu_inc => + cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and + left(3) and left(2) and left(1) and left(0)); + when alu_dec | alu_neg => + cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and + (not left(3)) and (not left(2)) and (not left(1)) and (not left(0))); +-- 6809 Programming reference manual says +-- V not affected by ASR, LSR and ROR +-- This is different to the 6800 +-- John Kent 6th June 2006 +-- when alu_asr8 => +-- cc_out(VBIT) <= left(0) xor left(7); +-- when alu_lsr8 | alu_lsr16 => +-- cc_out(VBIT) <= left(0); +-- when alu_ror8 => +-- cc_out(VBIT) <= left(0) xor cc(CBIT); + when alu_lsl16 => + cc_out(VBIT) <= left(15) xor left(14); + when alu_rol8 | alu_asl8 => + cc_out(VBIT) <= left(7) xor left(6); +-- +-- 11th July 2006 - John Kent +-- What DAA does with V is anyones guess +-- It is undefined in the 6809 programming manual +-- + when alu_daa => + cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT); +-- CLR resets V Bit +-- John Kent 6th June 2006 + when alu_and | alu_ora | alu_eor | alu_com | alu_clr | + alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex => + cc_out(VBIT) <= '0'; + when alu_andcc => + cc_out(VBIT) <= left(VBIT) and cc(VBIT); + when alu_orcc => + cc_out(VBIT) <= left(VBIT) or cc(VBIT); + when alu_tfr => + cc_out(VBIT) <= left(VBIT); + when others => + cc_out(VBIT) <= cc(VBIT); + end case; + + case alu_ctrl is + when alu_andcc => + cc_out(FBIT) <= left(FBIT) and cc(FBIT); + when alu_orcc => + cc_out(FBIT) <= left(FBIT) or cc(FBIT); + when alu_tfr => + cc_out(FBIT) <= left(FBIT); + when alu_seif => + cc_out(FBIT) <= '1'; + when others => + cc_out(FBIT) <= cc(FBIT); + end case; + + case alu_ctrl is + when alu_andcc => + cc_out(EBIT) <= left(EBIT) and cc(EBIT); + when alu_orcc => + cc_out(EBIT) <= left(EBIT) or cc(EBIT); + when alu_tfr => + cc_out(EBIT) <= left(EBIT); + when alu_see => + cc_out(EBIT) <= '1'; + when alu_cle => + cc_out(EBIT) <= '0'; + when others => + cc_out(EBIT) <= cc(EBIT); + end case; +end process; + +------------------------------------ +-- +-- state sequencer +-- +------------------------------------ +process( state, saved_state, + op_code, pre_code, + cc, ea, md, iv, fic, halt, + nmi_req, firq, irq, lic ) +variable cond_true : boolean; -- variable used to evaluate coditional branches +begin + cond_true := (1=1); + ba <= '0'; + bs <= '0'; + lic <= '0'; + opfetch <= '0'; + iv_ctrl <= latch_iv; + -- Registers preserved + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + dp_ctrl <= latch_dp; + ix_ctrl <= latch_ix; + iy_ctrl <= latch_iy; + up_ctrl <= latch_up; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + ea_ctrl <= latch_ea; + op_ctrl <= latch_op; + pre_ctrl <= latch_pre; + -- ALU Idle + left_ctrl <= pc_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + -- Bus idle + addr_ctrl <= idle_ad; + dout_ctrl <= cc_dout; + -- Next State Fetch + st_ctrl <= idle_st; + return_state <= fetch_state; + next_state <= fetch_state; + + case state is + when reset_state => -- released from reset + -- reset the registers + iv_ctrl <= reset_iv; + op_ctrl <= reset_op; + pre_ctrl <= reset_pre; + cc_ctrl <= reset_cc; + acca_ctrl <= reset_acca; + accb_ctrl <= reset_accb; + dp_ctrl <= reset_dp; + ix_ctrl <= reset_ix; + iy_ctrl <= reset_iy; + up_ctrl <= reset_up; + sp_ctrl <= reset_sp; + pc_ctrl <= reset_pc; + ea_ctrl <= reset_ea; + md_ctrl <= reset_md; + st_ctrl <= reset_st; + next_state <= vect_hi_state; + + -- + -- Jump via interrupt vector + -- iv holds interrupt type + -- fetch PC hi from vector location + -- + when vect_hi_state => + -- fetch pc low interrupt vector + pc_ctrl <= pull_hi_pc; + addr_ctrl <= int_hi_ad; + bs <= '1'; + next_state <= vect_lo_state; + + -- + -- jump via interrupt vector + -- iv holds vector type + -- fetch PC lo from vector location + -- + when vect_lo_state => + -- fetch the vector low byte + pc_ctrl <= pull_lo_pc; + addr_ctrl <= int_lo_ad; + bs <= '1'; + next_state <= fetch_state; + + when vect_idle_state => + -- + -- Last Instruction Cycle for SWI, SWI2 & SWI3 + -- + if op_code = "00111111" then + lic <= '1'; + end if; + next_state <= fetch_state; + + -- + -- Here to fetch an instruction + -- PC points to opcode + -- + when fetch_state => + -- fetch the op code + opfetch <= '1'; + op_ctrl <= fetch_op; + pre_ctrl <= fetch_pre; + ea_ctrl <= reset_ea; + -- Fetch op code + addr_ctrl <= fetch_ad; + -- Advance the PC to fetch next instruction byte + pc_ctrl <= incr_pc; + next_state <= decode1_state; + + -- + -- Here to decode instruction + -- and fetch next byte of intruction + -- whether it be necessary or not + -- + when decode1_state => + -- fetch first byte of address or immediate data + ea_ctrl <= fetch_first_ea; + md_ctrl <= fetch_first_md; + addr_ctrl <= fetch_ad; + case op_code(7 downto 4) is + -- + -- direct single op (2 bytes) + -- 6809 => 6 cycles + -- cpu09 => 5 cycles + -- 1 op=(pc) / pc=pc+1 + -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1 + -- 3 md_lo=(ea) / pc=pc + -- 4 alu_left=md / md=alu_out / pc=pc + -- 5 (ea)=md_lo / pc=pc + -- + -- Exception is JMP + -- 6809 => 3 cycles + -- cpu09 => 3 cycles + -- 1 op=(pc) / pc=pc+1 + -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1 + -- 3 pc=ea + -- + when "0000" => + -- advance the PC + pc_ctrl <= incr_pc; + + case op_code(3 downto 0) is + when "1110" => -- jmp + next_state <= jmp_state; + + when "1111" => -- clr + next_state <= single_op_exec_state; + + when others => + next_state <= single_op_read_state; + + end case; + + -- acca / accb inherent instructions + when "0001" => + case op_code(3 downto 0) is + -- + -- Page2 pre byte + -- pre=(pc) / pc=pc+1 + -- op=(pc) / pc=pc+1 + -- + when "0000" => -- page2 + opfetch <= '1'; + op_ctrl <= fetch_op; + -- advance pc + pc_ctrl <= incr_pc; + next_state <= decode2_state; + + -- + -- Page3 pre byte + -- pre=(pc) / pc=pc+1 + -- op=(pc) / pc=pc+1 + -- + when "0001" => -- page3 + opfetch <= '1'; + op_ctrl <= fetch_op; + -- advance pc + pc_ctrl <= incr_pc; + next_state <= decode3_state; + + -- + -- nop - No operation ( 1 byte ) + -- 6809 => 2 cycles + -- cpu09 => 2 cycles + -- 1 op=(pc) / pc=pc+1 + -- 2 decode + -- + when "0010" => -- nop + lic <= '1'; + next_state <= fetch_state; + + -- + -- sync - halt execution until an interrupt is received + -- interrupt may be NMI, IRQ or FIRQ + -- program execution continues if the + -- interrupt is asserted for 3 clock cycles + -- note that registers are not pushed onto the stack + -- CPU09 => Interrupts need only be asserted for one clock cycle + -- + when "0011" => -- sync + next_state <= sync_state; + + -- + -- lbra -- long branch (3 bytes) + -- 6809 => 5 cycles + -- cpu09 => 4 cycles + -- 1 op=(pc) / pc=pc+1 + -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 + -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1 + -- 4 pc=pc+md + -- + when "0110" => + -- increment the pc + pc_ctrl <= incr_pc; + next_state <= lbranch_state; + + -- + -- lbsr - long branch to subroutine (3 bytes) + -- 6809 => 9 cycles + -- cpu09 => 6 cycles + -- 1 op=(pc) /pc=pc+1 + -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1 + -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1 + -- 4 (sp)= pc_lo / sp=sp-1 / pc=pc + -- 5 (sp)=pc_hi / pc=pc + -- 6 pc=pc+md + -- + when "0111" => + -- pre decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- increment the pc + pc_ctrl <= incr_pc; + next_state <= lbranch_state; + + -- + -- Decimal Adjust Accumulator + -- + when "1001" => -- daa + left_ctrl <= acca_left; + right_ctrl <= accb_right; + alu_ctrl <= alu_daa; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + lic <= '1'; + next_state <= fetch_state; + + -- + -- OR Condition Codes + -- + when "1010" => -- orcc + -- increment the pc + pc_ctrl <= incr_pc; + next_state <= orcc_state; + + -- + -- AND Condition Codes + -- + when "1100" => -- andcc + -- increment the pc + pc_ctrl <= incr_pc; + next_state <= andcc_state; + + -- + -- Sign Extend + -- + when "1101" => -- sex + left_ctrl <= accb_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sex; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + lic <= '1'; + next_state <= fetch_state; + + -- + -- Exchange Registers + -- + when "1110" => -- exg + -- increment the pc + pc_ctrl <= incr_pc; + next_state <= exg_state; + + -- + -- Transfer Registers + -- + when "1111" => -- tfr + -- increment the pc + pc_ctrl <= incr_pc; + next_state <= tfr_state; + + when others => + -- increment the pc + pc_ctrl <= incr_pc; + lic <= '1'; + next_state <= fetch_state; + end case; + + -- + -- Short branch conditional + -- 6809 => always 3 cycles + -- cpu09 => always = 3 cycles + -- 1 op=(pc) / pc=pc+1 + -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc + -- 3 if cc tru pc=pc+md else pc=pc + -- + when "0010" => -- branch conditional + -- increment the pc + pc_ctrl <= incr_pc; + next_state <= sbranch_state; + + -- + -- Single byte stack operators + -- Do not advance PC + -- + when "0011" => + -- + -- lea - load effective address (2+ bytes) + -- 6809 => 4 cycles + addressing mode + -- cpu09 => 4 cycles + addressing mode + -- 1 op=(pc) / pc=pc+1 + -- 2 md_lo=(pc) / pc=pc+1 + -- 3 calculate ea + -- 4 ix/iy/sp/up = ea + -- + case op_code(3 downto 0) is + when "0000" | -- leax + "0001" | -- leay + "0010" | -- leas + "0011" => -- leau + -- advance PC + pc_ctrl <= incr_pc; + st_ctrl <= push_st; + return_state <= lea_state; + next_state <= indexed_state; + + -- + -- pshs - push registers onto sp stack + -- 6809 => 5 cycles + registers + -- cpu09 => 3 cycles + registers + -- 1 op=(pc) / pc=pc+1 + -- 2 ea_lo=(pc) / pc=pc+1 + -- 3 if ea(7 downto 0) != "00000000" then sp=sp-1 + -- 4 if ea(7) = 1 (sp)=pcl, sp=sp-1 + -- 5 if ea(7) = 1 (sp)=pch + -- if ea(6 downto 0) != "0000000" then sp=sp-1 + -- 6 if ea(6) = 1 (sp)=upl, sp=sp-1 + -- 7 if ea(6) = 1 (sp)=uph + -- if ea(5 downto 0) != "000000" then sp=sp-1 + -- 8 if ea(5) = 1 (sp)=iyl, sp=sp-1 + -- 9 if ea(5) = 1 (sp)=iyh + -- if ea(4 downto 0) != "00000" then sp=sp-1 + -- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1 + -- 11 if ea(4) = 1 (sp)=ixh + -- if ea(3 downto 0) != "0000" then sp=sp-1 + -- 12 if ea(3) = 1 (sp)=dp + -- if ea(2 downto 0) != "000" then sp=sp-1 + -- 13 if ea(2) = 1 (sp)=accb + -- if ea(1 downto 0) != "00" then sp=sp-1 + -- 14 if ea(1) = 1 (sp)=acca + -- if ea(0 downto 0) != "0" then sp=sp-1 + -- 15 if ea(0) = 1 (sp)=cc + -- + when "0100" => -- pshs + -- advance PC + pc_ctrl <= incr_pc; + next_state <= pshs_state; + + -- + -- puls - pull registers of sp stack + -- 6809 => 5 cycles + registers + -- cpu09 => 3 cycles + registers + -- + when "0101" => -- puls + -- advance PC + pc_ctrl <= incr_pc; + next_state <= puls_state; + + -- + -- pshu - push registers onto up stack + -- 6809 => 5 cycles + registers + -- cpu09 => 3 cycles + registers + -- + when "0110" => -- pshu + -- advance PC + pc_ctrl <= incr_pc; + next_state <= pshu_state; + + -- + -- pulu - pull registers of up stack + -- 6809 => 5 cycles + registers + -- cpu09 => 3 cycles + registers + -- + when "0111" => -- pulu + -- advance PC + pc_ctrl <= incr_pc; + next_state <= pulu_state; + + -- + -- rts - return from subroutine + -- 6809 => 5 cycles + -- cpu09 => 4 cycles + -- 1 op=(pc) / pc=pc+1 + -- 2 decode op + -- 3 pc_hi = (sp) / sp=sp+1 + -- 4 pc_lo = (sp) / sp=sp+1 + -- + when "1001" => + next_state <= pull_return_hi_state; + + -- + -- ADD accb to index register + -- *** Note: this is an unsigned addition. + -- does not affect any condition codes + -- 6809 => 3 cycles + -- cpu09 => 2 cycles + -- 1 op=(pc) / pc=pc+1 + -- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc + -- + when "1010" => -- abx + lic <= '1'; + left_ctrl <= ix_left; + right_ctrl <= accb_right; + alu_ctrl <= alu_abx; + ix_ctrl <= load_ix; + next_state <= fetch_state; + + -- + -- Return From Interrupt + -- + when "1011" => -- rti + next_state <= rti_cc_state; + + -- + -- CWAI + -- + when "1100" => -- cwai #$ + -- pre decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- increment pc + pc_ctrl <= incr_pc; + next_state <= cwai_state; + + -- + -- MUL Multiply + -- + when "1101" => -- mul + next_state <= mul_state; + + -- + -- SWI Software Interrupt + -- + when "1111" => -- swi + -- predecrement SP + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + iv_ctrl <= swi_iv; + st_ctrl <= push_st; + return_state <= int_swimask_state; + next_state <= int_entire_state; + + when others => + lic <= '1'; + next_state <= fetch_state; + + end case; + -- + -- Accumulator A Single operand + -- source = acca, dest = acca + -- Do not advance PC + -- Typically 2 cycles 1 bytes + -- 1 opcode fetch + -- 2 post byte fetch / instruction decode + -- Note that there is no post byte + -- so do not advance PC in decode cycle + -- Re-run opcode fetch cycle after decode + -- + when "0100" => -- acca single op + left_ctrl <= acca_left; + case op_code(3 downto 0) is + + when "0000" => -- neg + right_ctrl <= zero_right; + alu_ctrl <= alu_neg; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + + when "0011" => -- com + right_ctrl <= zero_right; + alu_ctrl <= alu_com; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + + when "0100" => -- lsr + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + + when "0110" => -- ror + right_ctrl <= zero_right; + alu_ctrl <= alu_ror8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + + when "0111" => -- asr + right_ctrl <= zero_right; + alu_ctrl <= alu_asr8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + + when "1000" => -- asl + right_ctrl <= zero_right; + alu_ctrl <= alu_asl8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + + when "1001" => -- rol + right_ctrl <= zero_right; + alu_ctrl <= alu_rol8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + + when "1010" => -- dec + right_ctrl <= one_right; + alu_ctrl <= alu_dec; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + + when "1011" => -- undefined + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + acca_ctrl <= latch_acca; + cc_ctrl <= latch_cc; + + when "1100" => -- inc + right_ctrl <= one_right; + alu_ctrl <= alu_inc; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + + when "1101" => -- tst + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + acca_ctrl <= latch_acca; + cc_ctrl <= load_cc; + + when "1110" => -- jmp (not defined) + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + acca_ctrl <= latch_acca; + cc_ctrl <= latch_cc; + + when "1111" => -- clr + right_ctrl <= zero_right; + alu_ctrl <= alu_clr; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + + when others => + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + acca_ctrl <= latch_acca; + cc_ctrl <= latch_cc; + + end case; + lic <= '1'; + next_state <= fetch_state; + + -- + -- Single Operand accb + -- source = accb, dest = accb + -- Typically 2 cycles 1 bytes + -- 1 opcode fetch + -- 2 post byte fetch / instruction decode + -- Note that there is no post byte + -- so do not advance PC in decode cycle + -- Re-run opcode fetch cycle after decode + -- + when "0101" => + left_ctrl <= accb_left; + case op_code(3 downto 0) is + when "0000" => -- neg + right_ctrl <= zero_right; + alu_ctrl <= alu_neg; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + + when "0011" => -- com + right_ctrl <= zero_right; + alu_ctrl <= alu_com; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + + when "0100" => -- lsr + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + + when "0110" => -- ror + right_ctrl <= zero_right; + alu_ctrl <= alu_ror8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + + when "0111" => -- asr + right_ctrl <= zero_right; + alu_ctrl <= alu_asr8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + + when "1000" => -- asl + right_ctrl <= zero_right; + alu_ctrl <= alu_asl8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + + when "1001" => -- rol + right_ctrl <= zero_right; + alu_ctrl <= alu_rol8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + + when "1010" => -- dec + right_ctrl <= one_right; + alu_ctrl <= alu_dec; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + + when "1011" => -- undefined + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + accb_ctrl <= latch_accb; + cc_ctrl <= latch_cc; + + when "1100" => -- inc + right_ctrl <= one_right; + alu_ctrl <= alu_inc; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + + when "1101" => -- tst + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + accb_ctrl <= latch_accb; + cc_ctrl <= load_cc; + + when "1110" => -- jmp (undefined) + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + accb_ctrl <= latch_accb; + cc_ctrl <= latch_cc; + + when "1111" => -- clr + right_ctrl <= zero_right; + alu_ctrl <= alu_clr; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + + when others => + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + accb_ctrl <= latch_accb; + cc_ctrl <= latch_cc; + end case; + lic <= '1'; + next_state <= fetch_state; + + -- + -- Single operand indexed + -- Two byte instruction so advance PC + -- EA should hold index offset + -- + when "0110" => -- indexed single op + -- increment the pc + pc_ctrl <= incr_pc; + st_ctrl <= push_st; + + case op_code(3 downto 0) is + when "1110" => -- jmp + return_state <= jmp_state; + + when "1111" => -- clr + return_state <= single_op_exec_state; + + when others => + return_state <= single_op_read_state; + + end case; + next_state <= indexed_state; + + -- + -- Single operand extended addressing + -- three byte instruction so advance the PC + -- Low order EA holds high order address + -- + when "0111" => -- extended single op + -- increment PC + pc_ctrl <= incr_pc; + st_ctrl <= push_st; + + case op_code(3 downto 0) is + when "1110" => -- jmp + return_state <= jmp_state; + + when "1111" => -- clr + return_state <= single_op_exec_state; + + when others => + return_state <= single_op_read_state; + + end case; + next_state <= extended_state; + + when "1000" => -- acca immediate + -- increment the pc + pc_ctrl <= incr_pc; + + case op_code(3 downto 0) is + when "0011" | -- subd # + "1100" | -- cmpx # + "1110" => -- ldx # + next_state <= imm16_state; + + -- + -- bsr offset - Branch to subroutine (2 bytes) + -- 6809 => 7 cycles + -- cpu09 => 5 cycles + -- 1 op=(pc) / pc=pc+1 + -- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1 + -- 3 (sp)=pc_lo / sp=sp-1 + -- 4 (sp)=pc_hi + -- 5 pc=pc+md + -- + when "1101" => -- bsr + -- pre decrement SP + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- + st_ctrl <= push_st; + return_state <= sbranch_state; + next_state <= push_return_lo_state; + + when others => + lic <= '1'; + next_state <= fetch_state; + + end case; + + when "1001" => -- acca direct + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- subd + "1100" | -- cmpx + "1110" => -- ldx + next_state <= dual_op_read16_state; + + when "0111" => -- sta direct + next_state <= dual_op_write8_state; + + -- + -- jsr direct - Jump to subroutine in direct page (2 bytes) + -- 6809 => 7 cycles + -- cpu09 => 5 cycles + -- 1 op=(pc) / pc=pc+1 + -- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1 + -- 3 (sp)=pc_lo / sp=sp-1 + -- 4 (sp)=pc_hi + -- 5 pc=ea + -- + when "1101" => -- jsr direct + -- pre decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- + st_ctrl <= push_st; + return_state <= jmp_state; + next_state <= push_return_lo_state; + + + when "1111" => -- stx direct + -- idle ALU + left_ctrl <= ix_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + next_state <= dual_op_write16_state; + + when others => + next_state <= dual_op_read8_state; + + end case; + + when "1010" => -- acca indexed + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- subd + "1100" | -- cmpx + "1110" => -- ldx + st_ctrl <= push_st; + return_state <= dual_op_read16_state; + next_state <= indexed_state; + + when "0111" => -- staa ,x + st_ctrl <= push_st; + return_state <= dual_op_write8_state; + next_state <= indexed_state; + + when "1101" => -- jsr ,x + -- DO NOT pre decrement SP + st_ctrl <= push_st; + return_state <= jsr_state; + next_state <= indexed_state; + + when "1111" => -- stx ,x + st_ctrl <= push_st; + return_state <= dual_op_write16_state; + next_state <= indexed_state; + + when others => + st_ctrl <= push_st; + return_state <= dual_op_read8_state; + next_state <= indexed_state; + + end case; + + when "1011" => -- acca extended + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- subd + "1100" | -- cmpx + "1110" => -- ldx + st_ctrl <= push_st; + return_state <= dual_op_read16_state; + next_state <= extended_state; + + when "0111" => -- staa > + st_ctrl <= push_st; + return_state <= dual_op_write8_state; + next_state <= extended_state; + + when "1101" => -- jsr >extended + -- DO NOT pre decrement sp + st_ctrl <= push_st; + return_state <= jsr_state; + next_state <= extended_state; + + when "1111" => -- stx > + st_ctrl <= push_st; + return_state <= dual_op_write16_state; + next_state <= extended_state; + + when others => + st_ctrl <= push_st; + return_state <= dual_op_read8_state; + next_state <= extended_state; + + end case; + + when "1100" => -- accb immediate + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- addd # + "1100" | -- ldd # + "1110" => -- ldu # + next_state <= imm16_state; + + when others => + lic <= '1'; + next_state <= fetch_state; + + end case; + + when "1101" => -- accb direct + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- addd + "1100" | -- ldd + "1110" => -- ldu + next_state <= dual_op_read16_state; + + when "0111" => -- stab direct + next_state <= dual_op_write8_state; + + when "1101" => -- std direct + next_state <= dual_op_write16_state; + + when "1111" => -- stu direct + next_state <= dual_op_write16_state; + + when others => + next_state <= dual_op_read8_state; + + end case; + + when "1110" => -- accb indexed + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- addd + "1100" | -- ldd + "1110" => -- ldu + st_ctrl <= push_st; + return_state <= dual_op_read16_state; + next_state <= indexed_state; + + when "0111" => -- stab indexed + st_ctrl <= push_st; + return_state <= dual_op_write8_state; + next_state <= indexed_state; + + when "1101" => -- std indexed + st_ctrl <= push_st; + return_state <= dual_op_write16_state; + next_state <= indexed_state; + + when "1111" => -- stu indexed + st_ctrl <= push_st; + return_state <= dual_op_write16_state; + next_state <= indexed_state; + + when others => + st_ctrl <= push_st; + return_state <= dual_op_read8_state; + next_state <= indexed_state; + + end case; + + when "1111" => -- accb extended + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- addd + "1100" | -- ldd + "1110" => -- ldu + st_ctrl <= push_st; + return_state <= dual_op_read16_state; + next_state <= extended_state; + + when "0111" => -- stab extended + st_ctrl <= push_st; + return_state <= dual_op_write8_state; + next_state <= extended_state; + + when "1101" => -- std extended + st_ctrl <= push_st; + return_state <= dual_op_write16_state; + next_state <= extended_state; + + when "1111" => -- stu extended + st_ctrl <= push_st; + return_state <= dual_op_write16_state; + next_state <= extended_state; + + when others => + st_ctrl <= push_st; + return_state <= dual_op_read8_state; + next_state <= extended_state; + end case; + -- + -- not sure why I need this + -- + when others => + lic <= '1'; + next_state <= fetch_state; + end case; + + -- + -- Here to decode prefix 2 instruction + -- and fetch next byte of intruction + -- whether it be necessary or not + -- + when decode2_state => + -- fetch first byte of address or immediate data + ea_ctrl <= fetch_first_ea; + md_ctrl <= fetch_first_md; + addr_ctrl <= fetch_ad; + case op_code(7 downto 4) is + -- + -- lbcc -- long branch conditional + -- 6809 => branch 6 cycles, no branch 5 cycles + -- cpu09 => always 5 cycles + -- 1 pre=(pc) / pc=pc+1 + -- 2 op=(pc) / pc=pc+1 + -- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 + -- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1 + -- 5 if cond pc=pc+md else pc=pc + -- + when "0010" => + -- increment the pc + pc_ctrl <= incr_pc; + next_state <= lbranch_state; + + -- + -- Single byte stack operators + -- Do not advance PC + -- + when "0011" => + case op_code(3 downto 0) is + when "1111" => -- swi 2 + -- predecrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + iv_ctrl <= swi2_iv; + st_ctrl <= push_st; + return_state <= vect_hi_state; + next_state <= int_entire_state; + + when others => + lic <= '1'; + next_state <= fetch_state; + end case; + + when "1000" => -- acca immediate + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- cmpd # + "1100" | -- cmpy # + "1110" => -- ldy # + next_state <= imm16_state; + + when others => + lic <= '1'; + next_state <= fetch_state; + + end case; + + when "1001" => -- acca direct + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- cmpd < + "1100" | -- cmpy < + "1110" => -- ldy < + next_state <= dual_op_read16_state; + + when "1111" => -- sty < + next_state <= dual_op_write16_state; + + when others => + lic <= '1'; + next_state <= fetch_state; + + end case; + + when "1010" => -- acca indexed + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- cmpd ,ind + "1100" | -- cmpy ,ind + "1110" => -- ldy ,ind + st_ctrl <= push_st; + return_state <= dual_op_read16_state; + next_state <= indexed_state; + + when "1111" => -- sty ,ind + st_ctrl <= push_st; + return_state <= dual_op_write16_state; + next_state <= indexed_state; + + when others => + lic <= '1'; + next_state <= fetch_state; + end case; + + when "1011" => -- acca extended + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- cmpd < + "1100" | -- cmpy < + "1110" => -- ldy < + st_ctrl <= push_st; + return_state <= dual_op_read16_state; + next_state <= extended_state; + + when "1111" => -- sty > + st_ctrl <= push_st; + return_state <= dual_op_write16_state; + next_state <= extended_state; + + when others => + lic <= '1'; + next_state <= fetch_state; + + end case; + + when "1100" => -- accb immediate + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- undef # + "1100" | -- undef # + "1110" => -- lds # + next_state <= imm16_state; + + when others => + next_state <= fetch_state; + + end case; + + when "1101" => -- accb direct + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- undef < + "1100" | -- undef < + "1110" => -- lds < + next_state <= dual_op_read16_state; + + when "1111" => -- sts < + next_state <= dual_op_write16_state; + + when others => + lic <= '1'; + next_state <= fetch_state; + + end case; + + when "1110" => -- accb indexed + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- undef ,ind + "1100" | -- undef ,ind + "1110" => -- lds ,ind + st_ctrl <= push_st; + return_state <= dual_op_read16_state; + next_state <= indexed_state; + + when "1111" => -- sts ,ind + st_ctrl <= push_st; + return_state <= dual_op_write16_state; + next_state <= indexed_state; + + when others => + lic <= '1'; + next_state <= fetch_state; + + end case; + + when "1111" => -- accb extended + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- undef > + "1100" | -- undef > + "1110" => -- lds > + st_ctrl <= push_st; + return_state <= dual_op_read16_state; + next_state <= extended_state; + + when "1111" => -- sts > + st_ctrl <= push_st; + return_state <= dual_op_write16_state; + next_state <= extended_state; + + when others => + lic <= '1'; + next_state <= fetch_state; + end case; + + when others => + lic <= '1'; + next_state <= fetch_state; + end case; + -- + -- Here to decode instruction + -- and fetch next byte of intruction + -- whether it be necessary or not + -- + when decode3_state => + ea_ctrl <= fetch_first_ea; + md_ctrl <= fetch_first_md; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + case op_code(7 downto 4) is + -- + -- Single byte stack operators + -- Do not advance PC + -- + when "0011" => + case op_code(3 downto 0) is + when "1111" => -- swi3 + -- predecrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + iv_ctrl <= swi3_iv; + st_ctrl <= push_st; + return_state <= vect_hi_state; + next_state <= int_entire_state; + when others => + lic <= '1'; + next_state <= fetch_state; + end case; + + when "1000" => -- acca immediate + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- cmpu # + "1100" | -- cmps # + "1110" => -- undef # + next_state <= imm16_state; + when others => + lic <= '1'; + next_state <= fetch_state; + end case; + + when "1001" => -- acca direct + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- cmpu < + "1100" | -- cmps < + "1110" => -- undef < + next_state <= dual_op_read16_state; + + when others => + lic <= '1'; + next_state <= fetch_state; + + end case; + + when "1010" => -- acca indexed + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- cmpu ,X + "1100" | -- cmps ,X + "1110" => -- undef ,X + st_ctrl <= push_st; + return_state <= dual_op_read16_state; + next_state <= indexed_state; + + when others => + lic <= '1'; + next_state <= fetch_state; + + end case; + + when "1011" => -- acca extended + -- increment the pc + pc_ctrl <= incr_pc; + case op_code(3 downto 0) is + when "0011" | -- cmpu > + "1100" | -- cmps > + "1110" => -- undef > + st_ctrl <= push_st; + return_state <= dual_op_read16_state; + next_state <= extended_state; + when others => + lic <= '1'; + next_state <= fetch_state; + end case; + + when others => + lic <= '1'; + next_state <= fetch_state; + end case; + + -- + -- here if ea holds low byte + -- Direct + -- Extended + -- Indexed + -- read memory location + -- + when single_op_read_state => + -- read memory into md + md_ctrl <= fetch_first_md; + addr_ctrl <= read_ad; + dout_ctrl <= md_lo_dout; + next_state <= single_op_exec_state; + + when single_op_exec_state => + case op_code(3 downto 0) is + when "0000" => -- neg + left_ctrl <= md_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_neg; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= single_op_write_state; + when "0011" => -- com + left_ctrl <= md_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_com; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= single_op_write_state; + when "0100" => -- lsr + left_ctrl <= md_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= single_op_write_state; + when "0110" => -- ror + left_ctrl <= md_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_ror8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= single_op_write_state; + when "0111" => -- asr + left_ctrl <= md_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_asr8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= single_op_write_state; + when "1000" => -- asl + left_ctrl <= md_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_asl8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= single_op_write_state; + when "1001" => -- rol + left_ctrl <= md_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_rol8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= single_op_write_state; + when "1010" => -- dec + left_ctrl <= md_left; + right_ctrl <= one_right; + alu_ctrl <= alu_dec; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= single_op_write_state; + when "1011" => -- undefined + lic <= '1'; + next_state <= fetch_state; + when "1100" => -- inc + left_ctrl <= md_left; + right_ctrl <= one_right; + alu_ctrl <= alu_inc; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= single_op_write_state; + when "1101" => -- tst + left_ctrl <= md_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + lic <= '1'; + next_state <= fetch_state; + when "1110" => -- jmp + left_ctrl <= md_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_ld16; + pc_ctrl <= load_pc; + lic <= '1'; + next_state <= fetch_state; + when "1111" => -- clr + left_ctrl <= md_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_clr; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= single_op_write_state; + when others => + lic <= '1'; + next_state <= fetch_state; + end case; + -- + -- single operand 8 bit write + -- Write low 8 bits of ALU output + -- EA holds address + -- MD holds data + -- + when single_op_write_state => + -- write ALU low byte output + addr_ctrl <= write_ad; + dout_ctrl <= md_lo_dout; + lic <= '1'; + next_state <= fetch_state; + + -- + -- here if ea holds address of low byte + -- read memory location + -- + when dual_op_read8_state => + -- read first data byte from ea + md_ctrl <= fetch_first_md; + addr_ctrl <= read_ad; + lic <= '1'; + next_state <= fetch_state; + + -- + -- Here to read a 16 bit value into MD + -- pointed to by the EA register + -- The first byte is read + -- and the EA is incremented + -- + when dual_op_read16_state => + -- increment the effective address + left_ctrl <= ea_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + -- read the high byte of the 16 bit data + md_ctrl <= fetch_first_md; + addr_ctrl <= read_ad; + next_state <= dual_op_read16_2_state; + + -- + -- here to read the second byte + -- pointed to by EA into MD + -- + when dual_op_read16_2_state => + -- read the low byte of the 16 bit data + md_ctrl <= fetch_next_md; + addr_ctrl <= read_ad; + lic <= '1'; + next_state <= fetch_state; + + -- + -- 16 bit Write state + -- EA hold address of memory to write to + -- Advance the effective address in ALU + -- decode op_code to determine which + -- register to write + -- + when dual_op_write16_state => + -- increment the effective address + left_ctrl <= ea_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + -- write the ALU hi byte at ea + addr_ctrl <= write_ad; + if op_code(6) = '0' then + case op_code(3 downto 0) is + when "1111" => -- stx / sty + case pre_code is + when "00010000" => -- page 2 -- sty + dout_ctrl <= iy_hi_dout; + when others => -- page 1 -- stx + dout_ctrl <= ix_hi_dout; + end case; + when others => + dout_ctrl <= md_hi_dout; + end case; + else + case op_code(3 downto 0) is + when "1101" => -- std + dout_ctrl <= acca_dout; -- acca is high byte of ACCD + when "1111" => -- stu / sts + case pre_code is + when "00010000" => -- page 2 -- sts + dout_ctrl <= sp_hi_dout; + when others => -- page 1 -- stu + dout_ctrl <= up_hi_dout; + end case; + when others => + dout_ctrl <= md_hi_dout; + end case; + end if; + next_state <= dual_op_write8_state; + + -- + -- Dual operand 8 bit write + -- Write 8 bit accumulator + -- or low byte of 16 bit register + -- EA holds address + -- decode opcode to determine + -- which register to apply to the bus + -- Also set the condition codes here + -- + when dual_op_write8_state => + if op_code(6) = '0' then + case op_code(3 downto 0) is + when "0111" => -- sta + dout_ctrl <= acca_dout; + when "1111" => -- stx / sty + case pre_code is + when "00010000" => -- page 2 -- sty + dout_ctrl <= iy_lo_dout; + when others => -- page 1 -- stx + dout_ctrl <= ix_lo_dout; + end case; + when others => + dout_ctrl <= md_lo_dout; + end case; + else + case op_code(3 downto 0) is + when "0111" => -- stb + dout_ctrl <= accb_dout; + when "1101" => -- std + dout_ctrl <= accb_dout; -- accb is low byte of accd + when "1111" => -- stu / sts + case pre_code is + when "00010000" => -- page 2 -- sts + dout_ctrl <= sp_lo_dout; + when others => -- page 1 -- stu + dout_ctrl <= up_lo_dout; + end case; + when others => + dout_ctrl <= md_lo_dout; + end case; + end if; + -- write ALU low byte output + addr_ctrl <= write_ad; + lic <= '1'; + next_state <= fetch_state; + + -- + -- 16 bit immediate addressing mode + -- + when imm16_state => + -- increment pc + pc_ctrl <= incr_pc; + -- fetch next immediate byte + md_ctrl <= fetch_next_md; + addr_ctrl <= fetch_ad; + lic <= '1'; + next_state <= fetch_state; + + -- + -- md & ea holds 8 bit index offset + -- calculate the effective memory address + -- using the alu + -- + when indexed_state => + -- + -- decode indexing mode + -- + if md(7) = '0' then + case md(6 downto 5) is + when "00" => + left_ctrl <= ix_left; + when "01" => + left_ctrl <= iy_left; + when "10" => + left_ctrl <= up_left; + when others => + -- when "11" => + left_ctrl <= sp_left; + end case; + right_ctrl <= md_sign5_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + next_state <= saved_state; + + else + case md(3 downto 0) is + when "0000" => -- ,R+ + case md(6 downto 5) is + when "00" => + left_ctrl <= ix_left; + when "01" => + left_ctrl <= iy_left; + when "10" => + left_ctrl <= up_left; + when others => + left_ctrl <= sp_left; + end case; + -- + right_ctrl <= zero_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + next_state <= postincr1_state; + + when "0001" => -- ,R++ + case md(6 downto 5) is + when "00" => + left_ctrl <= ix_left; + when "01" => + left_ctrl <= iy_left; + when "10" => + left_ctrl <= up_left; + when others => + -- when "11" => + left_ctrl <= sp_left; + end case; + right_ctrl <= zero_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + next_state <= postincr2_state; + + when "0010" => -- ,-R + case md(6 downto 5) is + when "00" => + left_ctrl <= ix_left; + ix_ctrl <= load_ix; + when "01" => + left_ctrl <= iy_left; + iy_ctrl <= load_iy; + when "10" => + left_ctrl <= up_left; + up_ctrl <= load_up; + when others => + -- when "11" => + left_ctrl <= sp_left; + sp_ctrl <= load_sp; + end case; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + ea_ctrl <= load_ea; + next_state <= saved_state; + + when "0011" => -- ,--R + case md(6 downto 5) is + when "00" => + left_ctrl <= ix_left; + ix_ctrl <= load_ix; + when "01" => + left_ctrl <= iy_left; + iy_ctrl <= load_iy; + when "10" => + left_ctrl <= up_left; + up_ctrl <= load_up; + when others => + -- when "11" => + left_ctrl <= sp_left; + sp_ctrl <= load_sp; + end case; + right_ctrl <= two_right; + alu_ctrl <= alu_sub16; + ea_ctrl <= load_ea; + if md(4) = '0' then + next_state <= saved_state; + else + next_state <= indirect_state; + end if; + + when "0100" => -- ,R (zero offset) + case md(6 downto 5) is + when "00" => + left_ctrl <= ix_left; + when "01" => + left_ctrl <= iy_left; + when "10" => + left_ctrl <= up_left; + when others => + -- when "11" => + left_ctrl <= sp_left; + end case; + right_ctrl <= zero_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + if md(4) = '0' then + next_state <= saved_state; + else + next_state <= indirect_state; + end if; + + when "0101" => -- ACCB,R + case md(6 downto 5) is + when "00" => + left_ctrl <= ix_left; + when "01" => + left_ctrl <= iy_left; + when "10" => + left_ctrl <= up_left; + when others => + -- when "11" => + left_ctrl <= sp_left; + end case; + right_ctrl <= accb_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + if md(4) = '0' then + next_state <= saved_state; + else + next_state <= indirect_state; + end if; + + when "0110" => -- ACCA,R + case md(6 downto 5) is + when "00" => + left_ctrl <= ix_left; + when "01" => + left_ctrl <= iy_left; + when "10" => + left_ctrl <= up_left; + when others => + -- when "11" => + left_ctrl <= sp_left; + end case; + right_ctrl <= acca_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + if md(4) = '0' then + next_state <= saved_state; + else + next_state <= indirect_state; + end if; + + when "0111" => -- undefined + case md(6 downto 5) is + when "00" => + left_ctrl <= ix_left; + when "01" => + left_ctrl <= iy_left; + when "10" => + left_ctrl <= up_left; + when others => + -- when "11" => + left_ctrl <= sp_left; + end case; + right_ctrl <= zero_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + if md(4) = '0' then + next_state <= saved_state; + else + next_state <= indirect_state; + end if; + + when "1000" => -- offset8,R + md_ctrl <= fetch_first_md; -- pick up 8 bit offset + addr_ctrl <= fetch_ad; + pc_ctrl <= incr_pc; + next_state <= index8_state; + + when "1001" => -- offset16,R + md_ctrl <= fetch_first_md; -- pick up first byte of 16 bit offset + addr_ctrl <= fetch_ad; + pc_ctrl <= incr_pc; + next_state <= index16_state; + + when "1010" => -- undefined + case md(6 downto 5) is + when "00" => + left_ctrl <= ix_left; + when "01" => + left_ctrl <= iy_left; + when "10" => + left_ctrl <= up_left; + when others => + -- when "11" => + left_ctrl <= sp_left; + end case; + right_ctrl <= zero_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + -- + if md(4) = '0' then + next_state <= saved_state; + else + next_state <= indirect_state; + end if; + + when "1011" => -- ACCD,R + case md(6 downto 5) is + when "00" => + left_ctrl <= ix_left; + when "01" => + left_ctrl <= iy_left; + when "10" => + left_ctrl <= up_left; + when others => + -- when "11" => + left_ctrl <= sp_left; + end case; + right_ctrl <= accd_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + if md(4) = '0' then + next_state <= saved_state; + else + next_state <= indirect_state; + end if; + + when "1100" => -- offset8,PC + -- fetch 8 bit offset + md_ctrl <= fetch_first_md; + addr_ctrl <= fetch_ad; + pc_ctrl <= incr_pc; + next_state <= pcrel8_state; + + when "1101" => -- offset16,PC + -- fetch offset + md_ctrl <= fetch_first_md; + addr_ctrl <= fetch_ad; + pc_ctrl <= incr_pc; + next_state <= pcrel16_state; + + when "1110" => -- undefined + case md(6 downto 5) is + when "00" => + left_ctrl <= ix_left; + when "01" => + left_ctrl <= iy_left; + when "10" => + left_ctrl <= up_left; + when others => + -- when "11" => + left_ctrl <= sp_left; + end case; + right_ctrl <= zero_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + if md(4) = '0' then + next_state <= saved_state; + else + next_state <= indirect_state; + end if; + + when others => +-- when "1111" => -- [,address] + -- advance PC to pick up address + md_ctrl <= fetch_first_md; + addr_ctrl <= fetch_ad; + pc_ctrl <= incr_pc; + next_state <= indexaddr_state; + end case; + end if; + + -- load index register with ea plus one + when postincr1_state => + left_ctrl <= ea_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + case md(6 downto 5) is + when "00" => + ix_ctrl <= load_ix; + when "01" => + iy_ctrl <= load_iy; + when "10" => + up_ctrl <= load_up; + when others => + -- when "11" => + sp_ctrl <= load_sp; + end case; + -- return to previous state + if md(4) = '0' then + next_state <= saved_state; + else + next_state <= indirect_state; + end if; + + -- load index register with ea plus two + when postincr2_state => + -- increment register by two (address) + left_ctrl <= ea_left; + right_ctrl <= two_right; + alu_ctrl <= alu_add16; + case md(6 downto 5) is + when "00" => + ix_ctrl <= load_ix; + when "01" => + iy_ctrl <= load_iy; + when "10" => + up_ctrl <= load_up; + when others => + -- when "11" => + sp_ctrl <= load_sp; + end case; + -- return to previous state + if md(4) = '0' then + next_state <= saved_state; + else + next_state <= indirect_state; + end if; + -- + -- ea = index register + md (8 bit signed offset) + -- ea holds post byte + -- + when index8_state => + case ea(6 downto 5) is + when "00" => + left_ctrl <= ix_left; + when "01" => + left_ctrl <= iy_left; + when "10" => + left_ctrl <= up_left; + when others => + -- when "11" => + left_ctrl <= sp_left; + end case; + -- ea = index reg + md + right_ctrl <= md_sign8_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + -- return to previous state + if ea(4) = '0' then + next_state <= saved_state; + else + next_state <= indirect_state; + end if; + + -- fetch low byte of 16 bit indexed offset + when index16_state => + -- advance pc + pc_ctrl <= incr_pc; + -- fetch low byte + md_ctrl <= fetch_next_md; + addr_ctrl <= fetch_ad; + next_state <= index16_2_state; + + -- ea = index register + md (16 bit offset) + -- ea holds post byte + when index16_2_state => + case ea(6 downto 5) is + when "00" => + left_ctrl <= ix_left; + when "01" => + left_ctrl <= iy_left; + when "10" => + left_ctrl <= up_left; + when others => + -- when "11" => + left_ctrl <= sp_left; + end case; + -- ea = index reg + md + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + -- return to previous state + if ea(4) = '0' then + next_state <= saved_state; + else + next_state <= indirect_state; + end if; + -- + -- pc relative with 8 bit signed offest + -- md holds signed offset + -- + when pcrel8_state => + -- ea = pc + signed md + left_ctrl <= pc_left; + right_ctrl <= md_sign8_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + -- return to previous state + if ea(4) = '0' then + next_state <= saved_state; + else + next_state <= indirect_state; + end if; + + -- pc relative addressing with 16 bit offset + -- pick up the low byte of the offset in md + -- advance the pc + when pcrel16_state => + -- advance pc + pc_ctrl <= incr_pc; + -- fetch low byte + md_ctrl <= fetch_next_md; + addr_ctrl <= fetch_ad; + next_state <= pcrel16_2_state; + + -- pc relative with16 bit signed offest + -- md holds signed offset + when pcrel16_2_state => + -- ea = pc + md + left_ctrl <= pc_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + -- return to previous state + if ea(4) = '0' then + next_state <= saved_state; + else + next_state <= indirect_state; + end if; + + -- indexed to address + -- pick up the low byte of the address + -- advance the pc + when indexaddr_state => + -- advance pc + pc_ctrl <= incr_pc; + -- fetch low byte + md_ctrl <= fetch_next_md; + addr_ctrl <= fetch_ad; + next_state <= indexaddr2_state; + + -- indexed to absolute address + -- md holds address + -- ea hold indexing mode byte + when indexaddr2_state => + -- ea = md + left_ctrl <= pc_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + ea_ctrl <= load_ea; + -- return to previous state + if ea(4) = '0' then + next_state <= saved_state; + else + next_state <= indirect_state; + end if; + + -- + -- load md with high byte of indirect address + -- pointed to by ea + -- increment ea + -- + when indirect_state => + -- increment ea + left_ctrl <= ea_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + ea_ctrl <= load_ea; + -- fetch high byte + md_ctrl <= fetch_first_md; + addr_ctrl <= read_ad; + next_state <= indirect2_state; + -- + -- load md with low byte of indirect address + -- pointed to by ea + -- ea has previously been incremented + -- + when indirect2_state => + -- fetch high byte + md_ctrl <= fetch_next_md; + addr_ctrl <= read_ad; + dout_ctrl <= md_lo_dout; + next_state <= indirect3_state; + -- + -- complete idirect addressing + -- by loading ea with md + -- + when indirect3_state => + -- load ea with md + left_ctrl <= ea_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + ea_ctrl <= load_ea; + -- return to previous state + next_state <= saved_state; + + -- + -- ea holds the low byte of the absolute address + -- Move ea low byte into ea high byte + -- load new ea low byte to for absolute 16 bit address + -- advance the program counter + -- + when extended_state => -- fetch ea low byte + -- increment pc + pc_ctrl <= incr_pc; + -- fetch next effective address bytes + ea_ctrl <= fetch_next_ea; + addr_ctrl <= fetch_ad; + -- return to previous state + next_state <= saved_state; + + when lea_state => -- here on load effective address + -- load index register with effective address + left_ctrl <= pc_left; + right_ctrl <= ea_right; + alu_ctrl <= alu_lea; + case op_code(3 downto 0) is + when "0000" => -- leax + cc_ctrl <= load_cc; + ix_ctrl <= load_ix; + when "0001" => -- leay + cc_ctrl <= load_cc; + iy_ctrl <= load_iy; + when "0010" => -- leas + sp_ctrl <= load_sp; + when "0011" => -- leau + up_ctrl <= load_up; + when others => + null; + end case; + lic <= '1'; + next_state <= fetch_state; + + -- + -- jump to subroutine + -- sp=sp-1 + -- call push_return_lo_state to save pc + -- return to jmp_state + -- + when jsr_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- call push_return_state + st_ctrl <= push_st; + return_state <= jmp_state; + next_state <= push_return_lo_state; + + -- + -- Load pc with ea + -- (JMP) + -- + when jmp_state => + -- load PC with effective address + left_ctrl <= pc_left; + right_ctrl <= ea_right; + alu_ctrl <= alu_ld16; + pc_ctrl <= load_pc; + lic <= '1'; + next_state <= fetch_state; + + -- + -- long branch or branch to subroutine + -- pick up next md byte + -- md_hi = md_lo + -- md_lo = (pc) + -- pc=pc+1 + -- if a lbsr push return address + -- continue to sbranch_state + -- to evaluate conditional branches + -- + when lbranch_state => + pc_ctrl <= incr_pc; + -- fetch the next byte into md_lo + md_ctrl <= fetch_next_md; + addr_ctrl <= fetch_ad; + -- if lbsr - push return address + -- then continue on to short branch + if op_code = "00010111" then + st_ctrl <= push_st; + return_state <= sbranch_state; + next_state <= push_return_lo_state; + else + next_state <= sbranch_state; + end if; + + -- + -- here to execute conditional branch + -- short conditional branch md = signed 8 bit offset + -- long branch md = 16 bit offset + -- + when sbranch_state => + left_ctrl <= pc_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + -- Test condition for branch + if op_code(7 downto 4) = "0010" then -- conditional branch + case op_code(3 downto 0) is + when "0000" => -- bra + cond_true := (1 = 1); + when "0001" => -- brn + cond_true := (1 = 0); + when "0010" => -- bhi + cond_true := ((cc(CBIT) or cc(ZBIT)) = '0'); + when "0011" => -- bls + cond_true := ((cc(CBIT) or cc(ZBIT)) = '1'); + when "0100" => -- bcc/bhs + cond_true := (cc(CBIT) = '0'); + when "0101" => -- bcs/blo + cond_true := (cc(CBIT) = '1'); + when "0110" => -- bne + cond_true := (cc(ZBIT) = '0'); + when "0111" => -- beq + cond_true := (cc(ZBIT) = '1'); + when "1000" => -- bvc + cond_true := (cc(VBIT) = '0'); + when "1001" => -- bvs + cond_true := (cc(VBIT) = '1'); + when "1010" => -- bpl + cond_true := (cc(NBIT) = '0'); + when "1011" => -- bmi + cond_true := (cc(NBIT) = '1'); + when "1100" => -- bge + cond_true := ((cc(NBIT) xor cc(VBIT)) = '0'); + when "1101" => -- blt + cond_true := ((cc(NBIT) xor cc(VBIT)) = '1'); + when "1110" => -- bgt + cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0'); + when "1111" => -- ble + cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1'); + when others => + null; + end case; + end if; + if cond_true then + pc_ctrl <= load_pc; + end if; + lic <= '1'; + next_state <= fetch_state; + + -- + -- push return address onto the S stack + -- + -- (sp) = pc_lo + -- sp = sp - 1 + -- + when push_return_lo_state => + -- decrement the sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write PC low + addr_ctrl <= pushs_ad; + dout_ctrl <= pc_lo_dout; + next_state <= push_return_hi_state; + + -- + -- push program counter hi byte onto the stack + -- (sp) = pc_hi + -- sp = sp + -- return to originating state + -- + when push_return_hi_state => + -- write pc hi bytes + addr_ctrl <= pushs_ad; + dout_ctrl <= pc_hi_dout; + next_state <= saved_state; + + -- + -- RTS pull return address from stack + -- + when pull_return_hi_state => + -- increment the sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read pc hi + pc_ctrl <= pull_hi_pc; + addr_ctrl <= pulls_ad; + next_state <= pull_return_lo_state; + + when pull_return_lo_state => + -- increment the SP + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read pc low + pc_ctrl <= pull_lo_pc; + addr_ctrl <= pulls_ad; + dout_ctrl <= pc_lo_dout; + -- + lic <= '1'; + next_state <= fetch_state; + + when andcc_state => + -- AND CC with md + left_ctrl <= md_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_andcc; + cc_ctrl <= load_cc; + -- + lic <= '1'; + next_state <= fetch_state; + + when orcc_state => + -- OR CC with md + left_ctrl <= md_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_orcc; + cc_ctrl <= load_cc; + -- + lic <= '1'; + next_state <= fetch_state; + + when tfr_state => + -- select source register + case md(7 downto 4) is + when "0000" => + left_ctrl <= accd_left; + when "0001" => + left_ctrl <= ix_left; + when "0010" => + left_ctrl <= iy_left; + when "0011" => + left_ctrl <= up_left; + when "0100" => + left_ctrl <= sp_left; + when "0101" => + left_ctrl <= pc_left; + when "1000" => + left_ctrl <= acca_left; + when "1001" => + left_ctrl <= accb_left; + when "1010" => + left_ctrl <= cc_left; + when "1011" => + left_ctrl <= dp_left; + when others => + left_ctrl <= md_left; + end case; + right_ctrl <= zero_right; + alu_ctrl <= alu_tfr; + -- select destination register + case md(3 downto 0) is + when "0000" => -- accd + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + when "0001" => -- ix + ix_ctrl <= load_ix; + when "0010" => -- iy + iy_ctrl <= load_iy; + when "0011" => -- up + up_ctrl <= load_up; + when "0100" => -- sp + sp_ctrl <= load_sp; + when "0101" => -- pc + pc_ctrl <= load_pc; + when "1000" => -- acca + acca_ctrl <= load_acca; + when "1001" => -- accb + accb_ctrl <= load_accb; + when "1010" => -- cc + cc_ctrl <= load_cc; + when "1011" => --dp + dp_ctrl <= load_dp; + when others => + null; + end case; + -- + lic <= '1'; + next_state <= fetch_state; + + when exg_state => + -- save destination register + case md(3 downto 0) is + when "0000" => + left_ctrl <= accd_left; + when "0001" => + left_ctrl <= ix_left; + when "0010" => + left_ctrl <= iy_left; + when "0011" => + left_ctrl <= up_left; + when "0100" => + left_ctrl <= sp_left; + when "0101" => + left_ctrl <= pc_left; + when "1000" => + left_ctrl <= acca_left; + when "1001" => + left_ctrl <= accb_left; + when "1010" => + left_ctrl <= cc_left; + when "1011" => + left_ctrl <= dp_left; + when others => + left_ctrl <= md_left; + end case; + right_ctrl <= zero_right; + alu_ctrl <= alu_tfr; + ea_ctrl <= load_ea; + -- call tranfer microcode + next_state <= exg1_state; + + when exg1_state => + -- select source register + case md(7 downto 4) is + when "0000" => + left_ctrl <= accd_left; + when "0001" => + left_ctrl <= ix_left; + when "0010" => + left_ctrl <= iy_left; + when "0011" => + left_ctrl <= up_left; + when "0100" => + left_ctrl <= sp_left; + when "0101" => + left_ctrl <= pc_left; + when "1000" => + left_ctrl <= acca_left; + when "1001" => + left_ctrl <= accb_left; + when "1010" => + left_ctrl <= cc_left; + when "1011" => + left_ctrl <= dp_left; + when others => + left_ctrl <= md_left; + end case; + right_ctrl <= zero_right; + alu_ctrl <= alu_tfr; + -- select destination register + case md(3 downto 0) is + when "0000" => -- accd + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + when "0001" => -- ix + ix_ctrl <= load_ix; + when "0010" => -- iy + iy_ctrl <= load_iy; + when "0011" => -- up + up_ctrl <= load_up; + when "0100" => -- sp + sp_ctrl <= load_sp; + when "0101" => -- pc + pc_ctrl <= load_pc; + when "1000" => -- acca + acca_ctrl <= load_acca; + when "1001" => -- accb + accb_ctrl <= load_accb; + when "1010" => -- cc + cc_ctrl <= load_cc; + when "1011" => --dp + dp_ctrl <= load_dp; + when others => + null; + end case; + next_state <= exg2_state; + + when exg2_state => + -- restore destination + left_ctrl <= ea_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_tfr; + -- save as source register + case md(7 downto 4) is + when "0000" => -- accd + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + when "0001" => -- ix + ix_ctrl <= load_ix; + when "0010" => -- iy + iy_ctrl <= load_iy; + when "0011" => -- up + up_ctrl <= load_up; + when "0100" => -- sp + sp_ctrl <= load_sp; + when "0101" => -- pc + pc_ctrl <= load_pc; + when "1000" => -- acca + acca_ctrl <= load_acca; + when "1001" => -- accb + accb_ctrl <= load_accb; + when "1010" => -- cc + cc_ctrl <= load_cc; + when "1011" => --dp + dp_ctrl <= load_dp; + when others => + null; + end case; + lic <= '1'; + next_state <= fetch_state; + + when mul_state => + -- move acca to md + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + md_ctrl <= load_md; + next_state <= mulea_state; + + when mulea_state => + -- move accb to ea + left_ctrl <= accb_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + ea_ctrl <= load_ea; + next_state <= muld_state; + + when muld_state => + -- clear accd + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_ld8; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + next_state <= mul0_state; + + when mul0_state => + -- if bit 0 of ea set, add accd to md + left_ctrl <= accd_left; + if ea(0) = '1' then + right_ctrl <= md_right; + else + right_ctrl <= zero_right; + end if; + alu_ctrl <= alu_mul; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + md_ctrl <= shiftl_md; + next_state <= mul1_state; + + when mul1_state => + -- if bit 1 of ea set, add accd to md + left_ctrl <= accd_left; + if ea(1) = '1' then + right_ctrl <= md_right; + else + right_ctrl <= zero_right; + end if; + alu_ctrl <= alu_mul; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + md_ctrl <= shiftl_md; + next_state <= mul2_state; + + when mul2_state => + -- if bit 2 of ea set, add accd to md + left_ctrl <= accd_left; + if ea(2) = '1' then + right_ctrl <= md_right; + else + right_ctrl <= zero_right; + end if; + alu_ctrl <= alu_mul; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + md_ctrl <= shiftl_md; + next_state <= mul3_state; + + when mul3_state => + -- if bit 3 of ea set, add accd to md + left_ctrl <= accd_left; + if ea(3) = '1' then + right_ctrl <= md_right; + else + right_ctrl <= zero_right; + end if; + alu_ctrl <= alu_mul; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + md_ctrl <= shiftl_md; + next_state <= mul4_state; + + when mul4_state => + -- if bit 4 of ea set, add accd to md + left_ctrl <= accd_left; + if ea(4) = '1' then + right_ctrl <= md_right; + else + right_ctrl <= zero_right; + end if; + alu_ctrl <= alu_mul; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + md_ctrl <= shiftl_md; + next_state <= mul5_state; + + when mul5_state => + -- if bit 5 of ea set, add accd to md + left_ctrl <= accd_left; + if ea(5) = '1' then + right_ctrl <= md_right; + else + right_ctrl <= zero_right; + end if; + alu_ctrl <= alu_mul; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + md_ctrl <= shiftl_md; + next_state <= mul6_state; + + when mul6_state => + -- if bit 6 of ea set, add accd to md + left_ctrl <= accd_left; + if ea(6) = '1' then + right_ctrl <= md_right; + else + right_ctrl <= zero_right; + end if; + alu_ctrl <= alu_mul; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + md_ctrl <= shiftl_md; + next_state <= mul7_state; + + when mul7_state => + -- if bit 7 of ea set, add accd to md + left_ctrl <= accd_left; + if ea(7) = '1' then + right_ctrl <= md_right; + else + right_ctrl <= zero_right; + end if; + alu_ctrl <= alu_mul; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + md_ctrl <= shiftl_md; + lic <= '1'; + next_state <= fetch_state; + + -- + -- Enter here on pushs + -- ea holds post byte + -- + when pshs_state => + -- decrement sp if any registers to be pushed + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + -- idle address + addr_ctrl <= idle_ad; + dout_ctrl <= cc_dout; + if ea(7 downto 0) = "00000000" then + sp_ctrl <= latch_sp; + else + sp_ctrl <= load_sp; + end if; + if ea(7) = '1' then + next_state <= pshs_pcl_state; + elsif ea(6) = '1' then + next_state <= pshs_upl_state; + elsif ea(5) = '1' then + next_state <= pshs_iyl_state; + elsif ea(4) = '1' then + next_state <= pshs_ixl_state; + elsif ea(3) = '1' then + next_state <= pshs_dp_state; + elsif ea(2) = '1' then + next_state <= pshs_accb_state; + elsif ea(1) = '1' then + next_state <= pshs_acca_state; + elsif ea(0) = '1' then + next_state <= pshs_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pshs_pcl_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write pc low + addr_ctrl <= pushs_ad; + dout_ctrl <= pc_lo_dout; + next_state <= pshs_pch_state; + + when pshs_pch_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + if ea(6 downto 0) = "0000000" then + sp_ctrl <= latch_sp; + else + sp_ctrl <= load_sp; + end if; + -- write pc hi + addr_ctrl <= pushs_ad; + dout_ctrl <= pc_hi_dout; + if ea(6) = '1' then + next_state <= pshs_upl_state; + elsif ea(5) = '1' then + next_state <= pshs_iyl_state; + elsif ea(4) = '1' then + next_state <= pshs_ixl_state; + elsif ea(3) = '1' then + next_state <= pshs_dp_state; + elsif ea(2) = '1' then + next_state <= pshs_accb_state; + elsif ea(1) = '1' then + next_state <= pshs_acca_state; + elsif ea(0) = '1' then + next_state <= pshs_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + + when pshs_upl_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write pc low + addr_ctrl <= pushs_ad; + dout_ctrl <= up_lo_dout; + next_state <= pshs_uph_state; + + when pshs_uph_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + if ea(5 downto 0) = "000000" then + sp_ctrl <= latch_sp; + else + sp_ctrl <= load_sp; + end if; + -- write pc hi + addr_ctrl <= pushs_ad; + dout_ctrl <= up_hi_dout; + if ea(5) = '1' then + next_state <= pshs_iyl_state; + elsif ea(4) = '1' then + next_state <= pshs_ixl_state; + elsif ea(3) = '1' then + next_state <= pshs_dp_state; + elsif ea(2) = '1' then + next_state <= pshs_accb_state; + elsif ea(1) = '1' then + next_state <= pshs_acca_state; + elsif ea(0) = '1' then + next_state <= pshs_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pshs_iyl_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write iy low + addr_ctrl <= pushs_ad; + dout_ctrl <= iy_lo_dout; + next_state <= pshs_iyh_state; + + when pshs_iyh_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + if ea(4 downto 0) = "00000" then + sp_ctrl <= latch_sp; + else + sp_ctrl <= load_sp; + end if; + -- write iy hi + addr_ctrl <= pushs_ad; + dout_ctrl <= iy_hi_dout; + if ea(4) = '1' then + next_state <= pshs_ixl_state; + elsif ea(3) = '1' then + next_state <= pshs_dp_state; + elsif ea(2) = '1' then + next_state <= pshs_accb_state; + elsif ea(1) = '1' then + next_state <= pshs_acca_state; + elsif ea(0) = '1' then + next_state <= pshs_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pshs_ixl_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write ix low + addr_ctrl <= pushs_ad; + dout_ctrl <= ix_lo_dout; + next_state <= pshs_ixh_state; + + when pshs_ixh_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + if ea(3 downto 0) = "0000" then + sp_ctrl <= latch_sp; + else + sp_ctrl <= load_sp; + end if; + -- write ix hi + addr_ctrl <= pushs_ad; + dout_ctrl <= ix_hi_dout; + if ea(3) = '1' then + next_state <= pshs_dp_state; + elsif ea(2) = '1' then + next_state <= pshs_accb_state; + elsif ea(1) = '1' then + next_state <= pshs_acca_state; + elsif ea(0) = '1' then + next_state <= pshs_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pshs_dp_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + if ea(2 downto 0) = "000" then + sp_ctrl <= latch_sp; + else + sp_ctrl <= load_sp; + end if; + -- write dp + addr_ctrl <= pushs_ad; + dout_ctrl <= dp_dout; + if ea(2) = '1' then + next_state <= pshs_accb_state; + elsif ea(1) = '1' then + next_state <= pshs_acca_state; + elsif ea(0) = '1' then + next_state <= pshs_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pshs_accb_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + if ea(1 downto 0) = "00" then + sp_ctrl <= latch_sp; + else + sp_ctrl <= load_sp; + end if; + -- write accb + addr_ctrl <= pushs_ad; + dout_ctrl <= accb_dout; + if ea(1) = '1' then + next_state <= pshs_acca_state; + elsif ea(0) = '1' then + next_state <= pshs_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pshs_acca_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + if ea(0) = '1' then + sp_ctrl <= load_sp; + else + sp_ctrl <= latch_sp; + end if; + -- write acca + addr_ctrl <= pushs_ad; + dout_ctrl <= acca_dout; + if ea(0) = '1' then + next_state <= pshs_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pshs_cc_state => + -- idle sp + -- write cc + addr_ctrl <= pushs_ad; + dout_ctrl <= cc_dout; + lic <= '1'; + next_state <= fetch_state; + + -- + -- enter here on PULS + -- ea hold register mask + -- + when puls_state => + if ea(0) = '1' then + next_state <= puls_cc_state; + elsif ea(1) = '1' then + next_state <= puls_acca_state; + elsif ea(2) = '1' then + next_state <= puls_accb_state; + elsif ea(3) = '1' then + next_state <= puls_dp_state; + elsif ea(4) = '1' then + next_state <= puls_ixh_state; + elsif ea(5) = '1' then + next_state <= puls_iyh_state; + elsif ea(6) = '1' then + next_state <= puls_uph_state; + elsif ea(7) = '1' then + next_state <= puls_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when puls_cc_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read cc + cc_ctrl <= pull_cc; + addr_ctrl <= pulls_ad; + if ea(1) = '1' then + next_state <= puls_acca_state; + elsif ea(2) = '1' then + next_state <= puls_accb_state; + elsif ea(3) = '1' then + next_state <= puls_dp_state; + elsif ea(4) = '1' then + next_state <= puls_ixh_state; + elsif ea(5) = '1' then + next_state <= puls_iyh_state; + elsif ea(6) = '1' then + next_state <= puls_uph_state; + elsif ea(7) = '1' then + next_state <= puls_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when puls_acca_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read acca + acca_ctrl <= pull_acca; + addr_ctrl <= pulls_ad; + if ea(2) = '1' then + next_state <= puls_accb_state; + elsif ea(3) = '1' then + next_state <= puls_dp_state; + elsif ea(4) = '1' then + next_state <= puls_ixh_state; + elsif ea(5) = '1' then + next_state <= puls_iyh_state; + elsif ea(6) = '1' then + next_state <= puls_uph_state; + elsif ea(7) = '1' then + next_state <= puls_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when puls_accb_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read accb + accb_ctrl <= pull_accb; + addr_ctrl <= pulls_ad; + if ea(3) = '1' then + next_state <= puls_dp_state; + elsif ea(4) = '1' then + next_state <= puls_ixh_state; + elsif ea(5) = '1' then + next_state <= puls_iyh_state; + elsif ea(6) = '1' then + next_state <= puls_uph_state; + elsif ea(7) = '1' then + next_state <= puls_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when puls_dp_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read dp + dp_ctrl <= pull_dp; + addr_ctrl <= pulls_ad; + if ea(4) = '1' then + next_state <= puls_ixh_state; + elsif ea(5) = '1' then + next_state <= puls_iyh_state; + elsif ea(6) = '1' then + next_state <= puls_uph_state; + elsif ea(7) = '1' then + next_state <= puls_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when puls_ixh_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- pull ix hi + ix_ctrl <= pull_hi_ix; + addr_ctrl <= pulls_ad; + next_state <= puls_ixl_state; + + when puls_ixl_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read ix low + ix_ctrl <= pull_lo_ix; + addr_ctrl <= pulls_ad; + if ea(5) = '1' then + next_state <= puls_iyh_state; + elsif ea(6) = '1' then + next_state <= puls_uph_state; + elsif ea(7) = '1' then + next_state <= puls_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when puls_iyh_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- pull iy hi + iy_ctrl <= pull_hi_iy; + addr_ctrl <= pulls_ad; + next_state <= puls_iyl_state; + + when puls_iyl_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read iy low + iy_ctrl <= pull_lo_iy; + addr_ctrl <= pulls_ad; + if ea(6) = '1' then + next_state <= puls_uph_state; + elsif ea(7) = '1' then + next_state <= puls_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when puls_uph_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- pull up hi + up_ctrl <= pull_hi_up; + addr_ctrl <= pulls_ad; + next_state <= puls_upl_state; + + when puls_upl_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read up low + up_ctrl <= pull_lo_up; + addr_ctrl <= pulls_ad; + if ea(7) = '1' then + next_state <= puls_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when puls_pch_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- pull pc hi + pc_ctrl <= pull_hi_pc; + addr_ctrl <= pulls_ad; + next_state <= puls_pcl_state; + + when puls_pcl_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read pc low + pc_ctrl <= pull_lo_pc; + addr_ctrl <= pulls_ad; + lic <= '1'; + next_state <= fetch_state; + + -- + -- Enter here on pshu + -- ea holds post byte + -- + when pshu_state => + -- decrement up if any registers to be pushed + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + if ea(7 downto 0) = "00000000" then + up_ctrl <= latch_up; + else + up_ctrl <= load_up; + end if; + -- write idle bus + if ea(7) = '1' then + next_state <= pshu_pcl_state; + elsif ea(6) = '1' then + next_state <= pshu_spl_state; + elsif ea(5) = '1' then + next_state <= pshu_iyl_state; + elsif ea(4) = '1' then + next_state <= pshu_ixl_state; + elsif ea(3) = '1' then + next_state <= pshu_dp_state; + elsif ea(2) = '1' then + next_state <= pshu_accb_state; + elsif ea(1) = '1' then + next_state <= pshu_acca_state; + elsif ea(0) = '1' then + next_state <= pshu_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + -- + -- push PC onto U stack + -- + when pshu_pcl_state => + -- decrement up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + up_ctrl <= load_up; + -- write pc low + addr_ctrl <= pushu_ad; + dout_ctrl <= pc_lo_dout; + next_state <= pshu_pch_state; + + when pshu_pch_state => + -- decrement up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + if ea(6 downto 0) = "0000000" then + up_ctrl <= latch_up; + else + up_ctrl <= load_up; + end if; + -- write pc hi + addr_ctrl <= pushu_ad; + dout_ctrl <= pc_hi_dout; + if ea(6) = '1' then + next_state <= pshu_spl_state; + elsif ea(5) = '1' then + next_state <= pshu_iyl_state; + elsif ea(4) = '1' then + next_state <= pshu_ixl_state; + elsif ea(3) = '1' then + next_state <= pshu_dp_state; + elsif ea(2) = '1' then + next_state <= pshu_accb_state; + elsif ea(1) = '1' then + next_state <= pshu_acca_state; + elsif ea(0) = '1' then + next_state <= pshu_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pshu_spl_state => + -- decrement up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + up_ctrl <= load_up; + -- write sp low + addr_ctrl <= pushu_ad; + dout_ctrl <= sp_lo_dout; + next_state <= pshu_sph_state; + + when pshu_sph_state => + -- decrement up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + if ea(5 downto 0) = "000000" then + up_ctrl <= latch_up; + else + up_ctrl <= load_up; + end if; + -- write sp hi + addr_ctrl <= pushu_ad; + dout_ctrl <= sp_hi_dout; + if ea(5) = '1' then + next_state <= pshu_iyl_state; + elsif ea(4) = '1' then + next_state <= pshu_ixl_state; + elsif ea(3) = '1' then + next_state <= pshu_dp_state; + elsif ea(2) = '1' then + next_state <= pshu_accb_state; + elsif ea(1) = '1' then + next_state <= pshu_acca_state; + elsif ea(0) = '1' then + next_state <= pshu_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pshu_iyl_state => + -- decrement up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + up_ctrl <= load_up; + -- write iy low + addr_ctrl <= pushu_ad; + dout_ctrl <= iy_lo_dout; + next_state <= pshu_iyh_state; + + when pshu_iyh_state => + -- decrement up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + if ea(4 downto 0) = "00000" then + up_ctrl <= latch_up; + else + up_ctrl <= load_up; + end if; + -- write iy hi + addr_ctrl <= pushu_ad; + dout_ctrl <= iy_hi_dout; + if ea(4) = '1' then + next_state <= pshu_ixl_state; + elsif ea(3) = '1' then + next_state <= pshu_dp_state; + elsif ea(2) = '1' then + next_state <= pshu_accb_state; + elsif ea(1) = '1' then + next_state <= pshu_acca_state; + elsif ea(0) = '1' then + next_state <= pshu_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pshu_ixl_state => + -- decrement up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + up_ctrl <= load_up; + -- write ix low + addr_ctrl <= pushu_ad; + dout_ctrl <= ix_lo_dout; + next_state <= pshu_ixh_state; + + when pshu_ixh_state => + -- decrement up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + if ea(3 downto 0) = "0000" then + up_ctrl <= latch_up; + else + up_ctrl <= load_up; + end if; + -- write ix hi + addr_ctrl <= pushu_ad; + dout_ctrl <= ix_hi_dout; + if ea(3) = '1' then + next_state <= pshu_dp_state; + elsif ea(2) = '1' then + next_state <= pshu_accb_state; + elsif ea(1) = '1' then + next_state <= pshu_acca_state; + elsif ea(0) = '1' then + next_state <= pshu_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pshu_dp_state => + -- decrement up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + if ea(2 downto 0) = "000" then + up_ctrl <= latch_up; + else + up_ctrl <= load_up; + end if; + -- write dp + addr_ctrl <= pushu_ad; + dout_ctrl <= dp_dout; + if ea(2) = '1' then + next_state <= pshu_accb_state; + elsif ea(1) = '1' then + next_state <= pshu_acca_state; + elsif ea(0) = '1' then + next_state <= pshu_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pshu_accb_state => + -- decrement up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + if ea(1 downto 0) = "00" then + up_ctrl <= latch_up; + else + up_ctrl <= load_up; + end if; + -- write accb + addr_ctrl <= pushu_ad; + dout_ctrl <= accb_dout; + if ea(1) = '1' then + next_state <= pshu_acca_state; + elsif ea(0) = '1' then + next_state <= pshu_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pshu_acca_state => + -- decrement up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + if ea(0) = '0' then + up_ctrl <= latch_up; + else + up_ctrl <= load_up; + end if; + -- write acca + addr_ctrl <= pushu_ad; + dout_ctrl <= acca_dout; + if ea(0) = '1' then + next_state <= pshu_cc_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pshu_cc_state => + -- idle up + -- write cc + addr_ctrl <= pushu_ad; + dout_ctrl <= cc_dout; + lic <= '1'; + next_state <= fetch_state; + + -- + -- enter here on PULU + -- ea hold register mask + -- + when pulu_state => + -- idle UP + -- idle bus + if ea(0) = '1' then + next_state <= pulu_cc_state; + elsif ea(1) = '1' then + next_state <= pulu_acca_state; + elsif ea(2) = '1' then + next_state <= pulu_accb_state; + elsif ea(3) = '1' then + next_state <= pulu_dp_state; + elsif ea(4) = '1' then + next_state <= pulu_ixh_state; + elsif ea(5) = '1' then + next_state <= pulu_iyh_state; + elsif ea(6) = '1' then + next_state <= pulu_sph_state; + elsif ea(7) = '1' then + next_state <= pulu_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pulu_cc_state => + -- increment up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + up_ctrl <= load_up; + -- read cc + cc_ctrl <= pull_cc; + addr_ctrl <= pullu_ad; + if ea(1) = '1' then + next_state <= pulu_acca_state; + elsif ea(2) = '1' then + next_state <= pulu_accb_state; + elsif ea(3) = '1' then + next_state <= pulu_dp_state; + elsif ea(4) = '1' then + next_state <= pulu_ixh_state; + elsif ea(5) = '1' then + next_state <= pulu_iyh_state; + elsif ea(6) = '1' then + next_state <= pulu_sph_state; + elsif ea(7) = '1' then + next_state <= pulu_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pulu_acca_state => + -- increment up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + up_ctrl <= load_up; + -- read acca + acca_ctrl <= pull_acca; + addr_ctrl <= pullu_ad; + if ea(2) = '1' then + next_state <= pulu_accb_state; + elsif ea(3) = '1' then + next_state <= pulu_dp_state; + elsif ea(4) = '1' then + next_state <= pulu_ixh_state; + elsif ea(5) = '1' then + next_state <= pulu_iyh_state; + elsif ea(6) = '1' then + next_state <= pulu_sph_state; + elsif ea(7) = '1' then + next_state <= pulu_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pulu_accb_state => + -- increment up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + up_ctrl <= load_up; + -- read accb + accb_ctrl <= pull_accb; + addr_ctrl <= pullu_ad; + if ea(3) = '1' then + next_state <= pulu_dp_state; + elsif ea(4) = '1' then + next_state <= pulu_ixh_state; + elsif ea(5) = '1' then + next_state <= pulu_iyh_state; + elsif ea(6) = '1' then + next_state <= pulu_sph_state; + elsif ea(7) = '1' then + next_state <= pulu_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pulu_dp_state => + -- increment up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + up_ctrl <= load_up; + -- read dp + dp_ctrl <= pull_dp; + addr_ctrl <= pullu_ad; + if ea(4) = '1' then + next_state <= pulu_ixh_state; + elsif ea(5) = '1' then + next_state <= pulu_iyh_state; + elsif ea(6) = '1' then + next_state <= pulu_sph_state; + elsif ea(7) = '1' then + next_state <= pulu_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pulu_ixh_state => + -- increment up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + up_ctrl <= load_up; + -- read ix hi + ix_ctrl <= pull_hi_ix; + addr_ctrl <= pullu_ad; + next_state <= pulu_ixl_state; + + when pulu_ixl_state => + -- increment up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + up_ctrl <= load_up; + -- read ix low + ix_ctrl <= pull_lo_ix; + addr_ctrl <= pullu_ad; + if ea(5) = '1' then + next_state <= pulu_iyh_state; + elsif ea(6) = '1' then + next_state <= pulu_sph_state; + elsif ea(7) = '1' then + next_state <= pulu_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pulu_iyh_state => + -- increment up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + up_ctrl <= load_up; + -- read iy hi + iy_ctrl <= pull_hi_iy; + addr_ctrl <= pullu_ad; + next_state <= pulu_iyl_state; + + when pulu_iyl_state => + -- increment up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + up_ctrl <= load_up; + -- read iy low + iy_ctrl <= pull_lo_iy; + addr_ctrl <= pullu_ad; + if ea(6) = '1' then + next_state <= pulu_sph_state; + elsif ea(7) = '1' then + next_state <= pulu_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pulu_sph_state => + -- increment up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + up_ctrl <= load_up; + -- read sp hi + sp_ctrl <= pull_hi_sp; + addr_ctrl <= pullu_ad; + next_state <= pulu_spl_state; + + when pulu_spl_state => + -- increment up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + up_ctrl <= load_up; + -- read sp low + sp_ctrl <= pull_lo_sp; + addr_ctrl <= pullu_ad; + if ea(7) = '1' then + next_state <= pulu_pch_state; + else + lic <= '1'; + next_state <= fetch_state; + end if; + + when pulu_pch_state => + -- increment up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + up_ctrl <= load_up; + -- pull pc hi + pc_ctrl <= pull_hi_pc; + addr_ctrl <= pullu_ad; + next_state <= pulu_pcl_state; + + when pulu_pcl_state => + -- increment up + left_ctrl <= up_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + up_ctrl <= load_up; + -- read pc low + pc_ctrl <= pull_lo_pc; + addr_ctrl <= pullu_ad; + lic <= '1'; + next_state <= fetch_state; + + -- + -- pop the Condition codes + -- + when rti_cc_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read cc + cc_ctrl <= pull_cc; + addr_ctrl <= pulls_ad; + next_state <= rti_entire_state; + + -- + -- Added RTI cycle 11th July 2006 John Kent. + -- test the "Entire" Flag + -- that has just been popped off the stack + -- + when rti_entire_state => + -- + -- The Entire flag must be recovered from the stack + -- before testing. + -- + if cc(EBIT) = '1' then + next_state <= rti_acca_state; + else + next_state <= rti_pch_state; + end if; + + when rti_acca_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read acca + acca_ctrl <= pull_acca; + addr_ctrl <= pulls_ad; + next_state <= rti_accb_state; + + when rti_accb_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read accb + accb_ctrl <= pull_accb; + addr_ctrl <= pulls_ad; + next_state <= rti_dp_state; + + when rti_dp_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read dp + dp_ctrl <= pull_dp; + addr_ctrl <= pulls_ad; + next_state <= rti_ixh_state; + + when rti_ixh_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read ix hi + ix_ctrl <= pull_hi_ix; + addr_ctrl <= pulls_ad; + next_state <= rti_ixl_state; + + when rti_ixl_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read ix low + ix_ctrl <= pull_lo_ix; + addr_ctrl <= pulls_ad; + next_state <= rti_iyh_state; + + when rti_iyh_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read iy hi + iy_ctrl <= pull_hi_iy; + addr_ctrl <= pulls_ad; + next_state <= rti_iyl_state; + + when rti_iyl_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read iy low + iy_ctrl <= pull_lo_iy; + addr_ctrl <= pulls_ad; + next_state <= rti_uph_state; + + + when rti_uph_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read up hi + up_ctrl <= pull_hi_up; + addr_ctrl <= pulls_ad; + next_state <= rti_upl_state; + + when rti_upl_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read up low + up_ctrl <= pull_lo_up; + addr_ctrl <= pulls_ad; + next_state <= rti_pch_state; + + when rti_pch_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- pull pc hi + pc_ctrl <= pull_hi_pc; + addr_ctrl <= pulls_ad; + next_state <= rti_pcl_state; + + when rti_pcl_state => + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- pull pc low + pc_ctrl <= pull_lo_pc; + addr_ctrl <= pulls_ad; + lic <= '1'; + next_state <= fetch_state; + + -- + -- here on NMI interrupt + -- Complete execute cycle of the last instruction. + -- If it was a dual operand instruction + -- + when int_nmi_state => + next_state <= int_nmi1_state; + + -- Idle bus cycle + when int_nmi1_state => + -- pre decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + iv_ctrl <= nmi_iv; + st_ctrl <= push_st; + return_state <= int_nmimask_state; + next_state <= int_entire_state; + + -- + -- here on IRQ interrupt + -- Complete execute cycle of the last instruction. + -- If it was a dual operand instruction + -- + when int_irq_state => + next_state <= int_irq1_state; + + -- pre decrement the sp + -- Idle bus cycle + when int_irq1_state => + -- pre decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + iv_ctrl <= irq_iv; + st_ctrl <= push_st; + return_state <= int_irqmask_state; + next_state <= int_entire_state; + + -- + -- here on FIRQ interrupt + -- Complete execution cycle of the last instruction + -- if it was a dual operand instruction + -- + when int_firq_state => + next_state <= int_firq1_state; + + -- Idle bus cycle + when int_firq1_state => + -- pre decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + iv_ctrl <= firq_iv; + st_ctrl <= push_st; + return_state <= int_firqmask_state; + next_state <= int_fast_state; + + -- + -- CWAI entry point + -- stack pointer already pre-decremented + -- mask condition codes + -- + when cwai_state => + -- AND CC with md + left_ctrl <= md_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_andcc; + cc_ctrl <= load_cc; + st_ctrl <= push_st; + return_state <= int_cwai_state; + next_state <= int_entire_state; + + -- + -- wait here for an interrupt + -- + when int_cwai_state => + if (nmi_req = '1') then + iv_ctrl <= nmi_iv; + next_state <= int_nmimask_state; + -- + -- FIRQ & IRQ are level sensitive + -- + elsif (firq = '1') and (cc(FBIT) = '0') then + iv_ctrl <= firq_iv; + next_state <= int_firqmask_state; + + elsif (irq = '1') and (cc(IBIT) = '0') then + iv_ctrl <= irq_iv; + next_state <= int_irqmask_state; + else + next_state <= int_cwai_state; + end if; + + -- + -- State to mask I Flag and F Flag (NMI) + -- + when int_nmimask_state => + alu_ctrl <= alu_seif; + cc_ctrl <= load_cc; + next_state <= vect_hi_state; + + -- + -- State to mask I Flag and F Flag (FIRQ) + -- + when int_firqmask_state => + alu_ctrl <= alu_seif; + cc_ctrl <= load_cc; + next_state <= vect_hi_state; + + + -- + -- State to mask I Flag and F Flag (SWI) + -- + when int_swimask_state => + alu_ctrl <= alu_seif; + cc_ctrl <= load_cc; + next_state <= vect_hi_state; + + -- + -- State to mask I Flag only (IRQ) + -- + when int_irqmask_state => + alu_ctrl <= alu_sei; + cc_ctrl <= load_cc; + next_state <= vect_hi_state; + + -- + -- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI + -- before stacking all registers + -- + when int_entire_state => + -- set entire flag + alu_ctrl <= alu_see; + cc_ctrl <= load_cc; + next_state <= int_pcl_state; + + -- + -- clear Entire Flag on FIRQ + -- before stacking all registers + -- + when int_fast_state => + -- clear entire flag + alu_ctrl <= alu_cle; + cc_ctrl <= load_cc; + next_state <= int_pcl_state; + + when int_pcl_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write pc low + addr_ctrl <= pushs_ad; + dout_ctrl <= pc_lo_dout; + next_state <= int_pch_state; + + when int_pch_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write pc hi + addr_ctrl <= pushs_ad; + dout_ctrl <= pc_hi_dout; + if cc(EBIT) = '1' then + next_state <= int_upl_state; + else + next_state <= int_cc_state; + end if; + + when int_upl_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write up low + addr_ctrl <= pushs_ad; + dout_ctrl <= up_lo_dout; + next_state <= int_uph_state; + + when int_uph_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write ix hi + addr_ctrl <= pushs_ad; + dout_ctrl <= up_hi_dout; + next_state <= int_iyl_state; + + when int_iyl_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write ix low + addr_ctrl <= pushs_ad; + dout_ctrl <= iy_lo_dout; + next_state <= int_iyh_state; + + when int_iyh_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write ix hi + addr_ctrl <= pushs_ad; + dout_ctrl <= iy_hi_dout; + next_state <= int_ixl_state; + + when int_ixl_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write ix low + addr_ctrl <= pushs_ad; + dout_ctrl <= ix_lo_dout; + next_state <= int_ixh_state; + + when int_ixh_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write ix hi + addr_ctrl <= pushs_ad; + dout_ctrl <= ix_hi_dout; + next_state <= int_dp_state; + + when int_dp_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write accb + addr_ctrl <= pushs_ad; + dout_ctrl <= dp_dout; + next_state <= int_accb_state; + + when int_accb_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write accb + addr_ctrl <= pushs_ad; + dout_ctrl <= accb_dout; + next_state <= int_acca_state; + + when int_acca_state => + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= one_right; + alu_ctrl <= alu_sub16; + sp_ctrl <= load_sp; + -- write acca + addr_ctrl <= pushs_ad; + dout_ctrl <= acca_dout; + next_state <= int_cc_state; + + when int_cc_state => + -- write cc + addr_ctrl <= pushs_ad; + dout_ctrl <= cc_dout; + next_state <= saved_state; + + -- + -- According to the 6809 programming manual: + -- If an interrupt is received and is masked + -- or lasts for less than three cycles, the PC + -- will advance to the next instruction. + -- If an interrupt is unmasked and lasts + -- for more than three cycles, an interrupt + -- will be generated. + -- Note that I don't wait 3 clock cycles. + -- John Kent 11th July 2006 + -- + when sync_state => + lic <= '1'; + ba <= '1'; + -- + -- Version 1.28 2015-05-30 + -- Exit sync_state on interrupt. + -- If the interrupts are active + -- they will be caught in the state_machine process + -- and the interrupt service routine microcode will be executed. + -- Masked interrupts will exit the sync_state. + -- Moved from the state_machine process to the state_sequencer process + -- + if (firq = '1') or (irq = '1') then + next_state <= fetch_state; + else + next_state <= sync_state; + end if; + + when halt_state => + -- + -- 2011-10-30 John Kent + -- ba & bs should be high + ba <= '1'; + bs <= '1'; + if halt = '1' then + next_state <= halt_state; + else + next_state <= fetch_state; + end if; + + end case; + +-- +-- Ver 1.23 2011-10-30 John Kent +-- First instruction cycle might be +-- fetch_state +-- halt_state +-- int_nmirq_state +-- int_firq_state +-- + if fic = '1' then + -- + case op_code(7 downto 6) is + when "10" => -- acca + case op_code(3 downto 0) is + when "0000" => -- suba + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + when "0001" => -- cmpa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + when "0010" => -- sbca + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sbc; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + when "0011" => + case pre_code is + when "00010000" => -- page 2 -- cmpd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= load_cc; + when "00010001" => -- page 3 -- cmpu + left_ctrl <= up_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= load_cc; + when others => -- page 1 -- subd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + end case; + when "0100" => -- anda + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + when "0101" => -- bita + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + when "0110" => -- ldaa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + when "0111" => -- staa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + when "1000" => -- eora + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_eor; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + when "1001" => -- adca + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_adc; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + when "1010" => -- oraa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ora; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + when "1011" => -- adda + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + when "1100" => + case pre_code is + when "00010000" => -- page 2 -- cmpy + left_ctrl <= iy_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= load_cc; + when "00010001" => -- page 3 -- cmps + left_ctrl <= sp_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= load_cc; + when others => -- page 1 -- cmpx + left_ctrl <= ix_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= load_cc; + end case; + when "1101" => -- bsr / jsr + null; + when "1110" => -- ldx + case pre_code is + when "00010000" => -- page 2 -- ldy + left_ctrl <= iy_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + iy_ctrl <= load_iy; + when others => -- page 1 -- ldx + left_ctrl <= ix_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + ix_ctrl <= load_ix; + end case; + when "1111" => -- stx + case pre_code is + when "00010000" => -- page 2 -- sty + left_ctrl <= iy_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + when others => -- page 1 -- stx + left_ctrl <= ix_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + end case; + when others => + null; + end case; + when "11" => -- accb dual op + case op_code(3 downto 0) is + when "0000" => -- subb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + accb_ctrl <= load_accb; + when "0001" => -- cmpb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + when "0010" => -- sbcb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sbc; + cc_ctrl <= load_cc; + accb_ctrl <= load_accb; + when "0011" => -- addd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + when "0100" => -- andb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + accb_ctrl <= load_accb; + when "0101" => -- bitb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + when "0110" => -- ldab + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld8; + cc_ctrl <= load_cc; + accb_ctrl <= load_accb; + when "0111" => -- stab + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + when "1000" => -- eorb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_eor; + cc_ctrl <= load_cc; + accb_ctrl <= load_accb; + when "1001" => -- adcb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_adc; + cc_ctrl <= load_cc; + accb_ctrl <= load_accb; + when "1010" => -- orab + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ora; + cc_ctrl <= load_cc; + accb_ctrl <= load_accb; + when "1011" => -- addb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add8; + cc_ctrl <= load_cc; + accb_ctrl <= load_accb; + when "1100" => -- ldd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + when "1101" => -- std + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + when "1110" => -- ldu + case pre_code is + when "00010000" => -- page 2 -- lds + left_ctrl <= sp_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + sp_ctrl <= load_sp; + when others => -- page 1 -- ldu + left_ctrl <= up_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + up_ctrl <= load_up; + end case; + when "1111" => + case pre_code is + when "00010000" => -- page 2 -- sts + left_ctrl <= sp_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + when others => -- page 1 -- stu + left_ctrl <= up_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + end case; + when others => + null; + end case; + when others => + null; + end case; + + end if; -- first instruction cycle (fic) + lic_out <= lic; +end process; + +end rtl; + diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/cpu68.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/cpu68.vhd new file mode 100644 index 00000000..016bd9a9 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/cpu68.vhd @@ -0,0 +1,3963 @@ +--===========================================================================-- +-- +-- S Y N T H E Z I A B L E CPU68 C O R E +-- +-- www.OpenCores.Org - December 2002 +-- This core adheres to the GNU public license +-- +-- File name : cpu68.vhd +-- +-- Purpose : Implements a 6800 compatible CPU core with some +-- additional instructions found in the 6801 +-- +-- Dependencies : ieee.Std_Logic_1164 +-- ieee.std_logic_unsigned +-- +-- Author : John E. Kent +-- +--===========================================================================---- +-- +-- Revision History: +-- +-- Date: Revision Author +-- 22 Sep 2002 0.1 John Kent +-- +-- 30 Oct 2002 0.2 John Kent +-- made NMI edge triggered +-- +-- 30 Oct 2002 0.3 John Kent +-- more corrections to NMI +-- added wai_wait_state to prevent stack overflow on wai. +-- +-- 1 Nov 2002 0.4 John Kent +-- removed WAI states and integrated WAI with the interrupt service routine +-- replace Data out (do) and Data in (di) register with a single Memory Data (md) reg. +-- Added Multiply instruction states. +-- run ALU and CC out of CPU module for timing measurements. +-- +-- 3 Nov 2002 0.5 John Kent +-- Memory Data Register was not loaded on Store instructions +-- SEV and CLV were not defined in the ALU +-- Overflow Flag on NEG was incorrect +-- +-- 16th Feb 2003 0.6 John Kent +-- Rearranged the execution cycle for dual operand instructions +-- so that occurs during the following fetch cycle. +-- This allows the reduction of one clock cycle from dual operand +-- instruction. Note that this also necessitated re-arranging the +-- program counter so that it is no longer incremented in the ALU. +-- The effective address has also been re-arranged to include a +-- separate added. The STD (store accd) now sets the condition codes. +-- +-- 28th Jun 2003 0.7 John Kent +-- Added Hold and Halt signals. Hold is used to steal cycles from the +-- CPU or add wait states. Halt puts the CPU in the inactive state +-- and is only honoured in the fetch cycle. Both signals are active high. +-- +-- 9th Jan 2004 0.8 John Kent +-- Clear instruction did an alu_ld8 rather than an alu_clr, so +-- the carry bit was not cleared correctly. +-- This error was picked up by Michael Hassenfratz. +-- + +library ieee; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity cpu68 is + port ( + clk: in std_logic; + rst: in std_logic; + rw: out std_logic; + vma: out std_logic; + address: out std_logic_vector(15 downto 0); + data_in: in std_logic_vector(7 downto 0); + data_out: out std_logic_vector(7 downto 0); + hold: in std_logic; + halt: in std_logic; + irq: in std_logic; + nmi: in std_logic; + test_alu: out std_logic_vector(15 downto 0); + test_cc: out std_logic_vector(7 downto 0) + ); +end; + +architecture CPU_ARCH of cpu68 is + + constant SBIT : integer := 7; + constant XBIT : integer := 6; + constant HBIT : integer := 5; + constant IBIT : integer := 4; + constant NBIT : integer := 3; + constant ZBIT : integer := 2; + constant VBIT : integer := 1; + constant CBIT : integer := 0; + + type state_type is (reset_state, fetch_state, decode_state, + extended_state, indexed_state, read8_state, read16_state, immediate16_state, + write8_state, write16_state, + execute_state, halt_state, error_state, + mul_state, mulea_state, muld_state, + mul0_state, mul1_state, mul2_state, mul3_state, + mul4_state, mul5_state, mul6_state, mul7_state, + jmp_state, jsr_state, jsr1_state, + branch_state, bsr_state, bsr1_state, + rts_hi_state, rts_lo_state, + int_pcl_state, int_pch_state, + int_ixl_state, int_ixh_state, + int_cc_state, int_acca_state, int_accb_state, + int_wai_state, int_mask_state, + rti_state, rti_cc_state, rti_acca_state, rti_accb_state, + rti_ixl_state, rti_ixh_state, + rti_pcl_state, rti_pch_state, + pula_state, psha_state, pulb_state, pshb_state, + pulx_lo_state, pulx_hi_state, pshx_lo_state, pshx_hi_state, + vect_lo_state, vect_hi_state ); + type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, push_ad, pull_ad, int_hi_ad, int_lo_ad ); + type dout_type is (md_lo_dout, md_hi_dout, acca_dout, accb_dout, ix_lo_dout, ix_hi_dout, cc_dout, pc_lo_dout, pc_hi_dout ); + type op_type is (reset_op, fetch_op, latch_op ); + type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca ); + type accb_type is (reset_accb, load_accb, pull_accb, latch_accb ); + type cc_type is (reset_cc, load_cc, pull_cc, latch_cc ); + type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix ); + type sp_type is (reset_sp, latch_sp, load_sp ); + type pc_type is (reset_pc, latch_pc, load_ea_pc, add_ea_pc, pull_lo_pc, pull_hi_pc, inc_pc ); + type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md ); + type ea_type is (reset_ea, latch_ea, add_ix_ea, load_accb_ea, inc_ea, fetch_first_ea, fetch_next_ea ); + type iv_type is (reset_iv, latch_iv, swi_iv, nmi_iv, irq_iv ); + type nmi_type is (reset_nmi, set_nmi, latch_nmi ); + type left_type is (acca_left, accb_left, accd_left, md_left, ix_left, sp_left ); + type right_type is (md_right, zero_right, plus_one_right, accb_right ); + type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc, + alu_and, alu_ora, alu_eor, + alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com, + alu_inx, alu_dex, alu_cpx, + alu_lsr16, alu_lsl16, + alu_ror8, alu_rol8, + alu_asr8, alu_asl8, alu_lsr8, + alu_sei, alu_cli, alu_sec, alu_clc, alu_sev, alu_clv, alu_tpa, alu_tap, + alu_ld8, alu_st8, alu_ld16, alu_st16, alu_nop, alu_daa ); + + signal op_code: std_logic_vector(7 downto 0); + signal acca: std_logic_vector(7 downto 0); + signal accb: std_logic_vector(7 downto 0); + signal cc: std_logic_vector(7 downto 0); + signal cc_out: std_logic_vector(7 downto 0); + signal xreg: std_logic_vector(15 downto 0); + signal sp: std_logic_vector(15 downto 0); + signal ea: std_logic_vector(15 downto 0); + signal pc: std_logic_vector(15 downto 0); + signal md: std_logic_vector(15 downto 0); + signal left: std_logic_vector(15 downto 0); + signal right: std_logic_vector(15 downto 0); + signal out_alu: std_logic_vector(15 downto 0); + signal iv: std_logic_vector(1 downto 0); + signal nmi_req: std_logic; + signal nmi_ack: std_logic; + + signal state: state_type; + signal next_state: state_type; + signal pc_ctrl: pc_type; + signal ea_ctrl: ea_type; + signal op_ctrl: op_type; + signal md_ctrl: md_type; + signal acca_ctrl: acca_type; + signal accb_ctrl: accb_type; + signal ix_ctrl: ix_type; + signal cc_ctrl: cc_type; + signal sp_ctrl: sp_type; + signal iv_ctrl: iv_type; + signal left_ctrl: left_type; + signal right_ctrl: right_type; + signal alu_ctrl: alu_type; + signal addr_ctrl: addr_type; + signal dout_ctrl: dout_type; + signal nmi_ctrl: nmi_type; + + +begin + +---------------------------------- +-- +-- Address bus multiplexer +-- +---------------------------------- + +addr_mux: process( clk, addr_ctrl, pc, ea, sp, iv ) +begin + case addr_ctrl is + when idle_ad => + address <= "1111111111111111"; + vma <= '0'; + rw <= '1'; + when fetch_ad => + address <= pc; + vma <= '1'; + rw <= '1'; + when read_ad => + address <= ea; + vma <= '1'; + rw <= '1'; + when write_ad => + address <= ea; + vma <= '1'; + rw <= '0'; + when push_ad => + address <= sp; + vma <= '1'; + rw <= '0'; + when pull_ad => + address <= sp; + vma <= '1'; + rw <= '1'; + when int_hi_ad => + address <= "1111111111111" & iv & "0"; + vma <= '1'; + rw <= '1'; + when int_lo_ad => + address <= "1111111111111" & iv & "1"; + vma <= '1'; + rw <= '1'; + when others => + address <= "1111111111111111"; + vma <= '0'; + rw <= '1'; + end case; +end process; + +-------------------------------- +-- +-- Data Bus output +-- +-------------------------------- +dout_mux : process( clk, dout_ctrl, md, acca, accb, xreg, pc, cc ) +begin + case dout_ctrl is + when md_hi_dout => -- alu output + data_out <= md(15 downto 8); + when md_lo_dout => + data_out <= md(7 downto 0); + when acca_dout => -- accumulator a + data_out <= acca; + when accb_dout => -- accumulator b + data_out <= accb; + when ix_lo_dout => -- index reg + data_out <= xreg(7 downto 0); + when ix_hi_dout => -- index reg + data_out <= xreg(15 downto 8); + when cc_dout => -- condition codes + data_out <= cc; + when pc_lo_dout => -- low order pc + data_out <= pc(7 downto 0); + when pc_hi_dout => -- high order pc + data_out <= pc(15 downto 8); + when others => + data_out <= "00000000"; + end case; +end process; + + +---------------------------------- +-- +-- Program Counter Control +-- +---------------------------------- + +pc_mux: process( clk, pc_ctrl, pc, out_alu, data_in, ea, hold ) +variable tempof : std_logic_vector(15 downto 0); +variable temppc : std_logic_vector(15 downto 0); +begin + case pc_ctrl is + when add_ea_pc => + if ea(7) = '0' then + tempof := "00000000" & ea(7 downto 0); + else + tempof := "11111111" & ea(7 downto 0); + end if; + when inc_pc => + tempof := "0000000000000001"; + when others => + tempof := "0000000000000000"; + end case; + + case pc_ctrl is + when reset_pc => + temppc := "1111111111111110"; + when load_ea_pc => + temppc := ea; + when pull_lo_pc => + temppc(7 downto 0) := data_in; + temppc(15 downto 8) := pc(15 downto 8); + when pull_hi_pc => + temppc(7 downto 0) := pc(7 downto 0); + temppc(15 downto 8) := data_in; + when others => + temppc := pc; + end case; + + if clk'event and clk = '0' then + if hold = '1' then + pc <= pc; + else + pc <= temppc + tempof; + end if; + end if; +end process; + +---------------------------------- +-- +-- Effective Address Control +-- +---------------------------------- + +ea_mux: process( clk, ea_ctrl, ea, out_alu, data_in, accb, xreg, hold ) +variable tempind : std_logic_vector(15 downto 0); +variable tempea : std_logic_vector(15 downto 0); +begin + case ea_ctrl is + when add_ix_ea => + tempind := "00000000" & ea(7 downto 0); + when inc_ea => + tempind := "0000000000000001"; + when others => + tempind := "0000000000000000"; + end case; + + case ea_ctrl is + when reset_ea => + tempea := "0000000000000000"; + when load_accb_ea => + tempea := "00000000" & accb(7 downto 0); + when add_ix_ea => + tempea := xreg; + when fetch_first_ea => + tempea(7 downto 0) := data_in; + tempea(15 downto 8) := "00000000"; + when fetch_next_ea => + tempea(7 downto 0) := data_in; + tempea(15 downto 8) := ea(7 downto 0); + when others => + tempea := ea; + end case; + + if clk'event and clk = '0' then + if hold = '1' then + ea <= ea; + else + ea <= tempea + tempind; + end if; + end if; +end process; + +-------------------------------- +-- +-- Accumulator A +-- +-------------------------------- +acca_mux : process( clk, acca_ctrl, out_alu, acca, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + acca <= acca; + else + case acca_ctrl is + when reset_acca => + acca <= "00000000"; + when load_acca => + acca <= out_alu(7 downto 0); + when load_hi_acca => + acca <= out_alu(15 downto 8); + when pull_acca => + acca <= data_in; + when others => +-- when latch_acca => + acca <= acca; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- Accumulator B +-- +-------------------------------- +accb_mux : process( clk, accb_ctrl, out_alu, accb, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + accb <= accb; + else + case accb_ctrl is + when reset_accb => + accb <= "00000000"; + when load_accb => + accb <= out_alu(7 downto 0); + when pull_accb => + accb <= data_in; + when others => +-- when latch_accb => + accb <= accb; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- X Index register +-- +-------------------------------- +ix_mux : process( clk, ix_ctrl, out_alu, xreg, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + xreg <= xreg; + else + case ix_ctrl is + when reset_ix => + xreg <= "0000000000000000"; + when load_ix => + xreg <= out_alu(15 downto 0); + when pull_hi_ix => + xreg(15 downto 8) <= data_in; + when pull_lo_ix => + xreg(7 downto 0) <= data_in; + when others => +-- when latch_ix => + xreg <= xreg; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- stack pointer +-- +-------------------------------- +sp_mux : process( clk, sp_ctrl, out_alu, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + sp <= sp; + else + case sp_ctrl is + when reset_sp => + sp <= "0000000000000000"; + when load_sp => + sp <= out_alu(15 downto 0); + when others => +-- when latch_sp => + sp <= sp; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- Memory Data +-- +-------------------------------- +md_mux : process( clk, md_ctrl, out_alu, data_in, md, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + md <= md; + else + case md_ctrl is + when reset_md => + md <= "0000000000000000"; + when load_md => + md <= out_alu(15 downto 0); + when fetch_first_md => + md(15 downto 8) <= "00000000"; + md(7 downto 0) <= data_in; + when fetch_next_md => + md(15 downto 8) <= md(7 downto 0); + md(7 downto 0) <= data_in; + when shiftl_md => + md(15 downto 1) <= md(14 downto 0); + md(0) <= '0'; + when others => +-- when latch_md => + md <= md; + end case; + end if; + end if; +end process; + + +---------------------------------- +-- +-- Condition Codes +-- +---------------------------------- + +cc_mux: process( clk, cc_ctrl, cc_out, cc, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + cc <= cc; + else + case cc_ctrl is + when reset_cc => + cc <= "11000000"; + when load_cc => + cc <= cc_out; + when pull_cc => + cc <= data_in; + when others => +-- when latch_cc => + cc <= cc; + end case; + end if; + end if; +end process; + +---------------------------------- +-- +-- interrupt vector +-- +---------------------------------- + +iv_mux: process( clk, iv_ctrl, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + iv <= iv; + else + case iv_ctrl is + when reset_iv => + iv <= "11"; + when nmi_iv => + iv <= "10"; + when swi_iv => + iv <= "01"; + when irq_iv => + iv <= "00"; + when others => + iv <= iv; + end case; + end if; + end if; +end process; + +---------------------------------- +-- +-- op code fetch +-- +---------------------------------- + +op_fetch: process( clk, data_in, op_ctrl, op_code, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + op_code <= op_code; + else + case op_ctrl is + when reset_op => + op_code <= "00000001"; -- nop + when fetch_op => + op_code <= data_in; + when others => +-- when latch_op => + op_code <= op_code; + end case; + end if; + end if; +end process; + +---------------------------------- +-- +-- Left Mux +-- +---------------------------------- + +left_mux: process( left_ctrl, acca, accb, xreg, sp, pc, ea, md ) +begin + case left_ctrl is + when acca_left => + left(15 downto 8) <= "00000000"; + left(7 downto 0) <= acca; + when accb_left => + left(15 downto 8) <= "00000000"; + left(7 downto 0) <= accb; + when accd_left => + left(15 downto 8) <= acca; + left(7 downto 0) <= accb; + when ix_left => + left <= xreg; + when sp_left => + left <= sp; + when others => +-- when md_left => + left <= md; + end case; +end process; +---------------------------------- +-- +-- Right Mux +-- +---------------------------------- + +right_mux: process( right_ctrl, data_in, md, accb, ea ) +begin + case right_ctrl is + when zero_right => + right <= "0000000000000000"; + when plus_one_right => + right <= "0000000000000001"; + when accb_right => + right <= "00000000" & accb; + when others => +-- when md_right => + right <= md; + end case; +end process; + +---------------------------------- +-- +-- Arithmetic Logic Unit +-- +---------------------------------- + +mux_alu: process( alu_ctrl, cc, left, right, out_alu, cc_out ) +variable valid_lo, valid_hi : boolean; +variable carry_in : std_logic; +variable daa_reg : std_logic_vector(7 downto 0); +begin + + case alu_ctrl is + when alu_adc | alu_sbc | + alu_rol8 | alu_ror8 => + carry_in := cc(CBIT); + when others => + carry_in := '0'; + end case; + + valid_lo := left(3 downto 0) <= 9; + valid_hi := left(7 downto 4) <= 9; + + if (cc(CBIT) = '0') then + if( cc(HBIT) = '1' ) then + if valid_hi then + daa_reg := "00000110"; + else + daa_reg := "01100110"; + end if; + else + if valid_lo then + if valid_hi then + daa_reg := "00000000"; + else + daa_reg := "01100000"; + end if; + else + if( left(7 downto 4) <= 8 ) then + daa_reg := "00000110"; + else + daa_reg := "01100110"; + end if; + end if; + end if; + else + if ( cc(HBIT) = '1' )then + daa_reg := "01100110"; + else + if valid_lo then + daa_reg := "01100000"; + else + daa_reg := "01100110"; + end if; + end if; + end if; + + case alu_ctrl is + when alu_add8 | alu_inc | + alu_add16 | alu_inx | + alu_adc => + out_alu <= left + right + ("000000000000000" & carry_in); + when alu_sub8 | alu_dec | + alu_sub16 | alu_dex | + alu_sbc | alu_cpx => + out_alu <= left - right - ("000000000000000" & carry_in); + when alu_and => + out_alu <= left and right; -- and/bit + when alu_ora => + out_alu <= left or right; -- or + when alu_eor => + out_alu <= left xor right; -- eor/xor + when alu_lsl16 | alu_asl8 | alu_rol8 => + out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16 + when alu_lsr16 | alu_lsr8 => + out_alu <= carry_in & left(15 downto 1); -- lsr + when alu_ror8 => + out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror + when alu_asr8 => + out_alu <= "00000000" & left(7) & left(7 downto 1); -- asr + when alu_neg => + out_alu <= right - left; -- neg (right=0) + when alu_com => + out_alu <= not left; + when alu_clr | alu_ld8 | alu_ld16 => + out_alu <= right; -- clr, ld + when alu_st8 | alu_st16 => + out_alu <= left; + when alu_daa => + out_alu <= left + ("00000000" & daa_reg); + when alu_tpa => + out_alu <= "00000000" & cc; + when others => + out_alu <= left; -- nop + end case; + + -- + -- carry bit + -- + case alu_ctrl is + when alu_add8 | alu_adc => + cc_out(CBIT) <= (left(7) and right(7)) or + (left(7) and not out_alu(7)) or + (right(7) and not out_alu(7)); + when alu_sub8 | alu_sbc => + cc_out(CBIT) <= ((not left(7)) and right(7)) or + ((not left(7)) and out_alu(7)) or + (right(7) and out_alu(7)); + when alu_add16 => + cc_out(CBIT) <= (left(15) and right(15)) or + (left(15) and not out_alu(15)) or + (right(15) and not out_alu(15)); + when alu_sub16 => + cc_out(CBIT) <= ((not left(15)) and right(15)) or + ((not left(15)) and out_alu(15)) or + (right(15) and out_alu(15)); + when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 => + cc_out(CBIT) <= left(0); + when alu_rol8 | alu_asl8 => + cc_out(CBIT) <= left(7); + when alu_lsl16 => + cc_out(CBIT) <= left(15); + when alu_com => + cc_out(CBIT) <= '1'; + when alu_neg | alu_clr => + cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or + out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0); + when alu_daa => + if ( daa_reg(7 downto 4) = "0110" ) then + cc_out(CBIT) <= '1'; + else + cc_out(CBIT) <= '0'; + end if; + when alu_sec => + cc_out(CBIT) <= '1'; + when alu_clc => + cc_out(CBIT) <= '0'; + when alu_tap => + cc_out(CBIT) <= left(CBIT); + when others => -- carry is not affected by cpx + cc_out(CBIT) <= cc(CBIT); + end case; + -- + -- Zero flag + -- + case alu_ctrl is + when alu_add8 | alu_sub8 | + alu_adc | alu_sbc | + alu_and | alu_ora | alu_eor | + alu_inc | alu_dec | + alu_neg | alu_com | alu_clr | + alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 | + alu_ld8 | alu_st8 => + cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or + out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) ); + when alu_add16 | alu_sub16 | + alu_lsl16 | alu_lsr16 | + alu_inx | alu_dex | + alu_ld16 | alu_st16 | alu_cpx => + cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or + out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or + out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or + out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) ); + when alu_tap => + cc_out(ZBIT) <= left(ZBIT); + when others => + cc_out(ZBIT) <= cc(ZBIT); + end case; + + -- + -- negative flag + -- + case alu_ctrl is + when alu_add8 | alu_sub8 | + alu_adc | alu_sbc | + alu_and | alu_ora | alu_eor | + alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 | + alu_inc | alu_dec | alu_neg | alu_com | alu_clr | + alu_ld8 | alu_st8 => + cc_out(NBIT) <= out_alu(7); + when alu_add16 | alu_sub16 | + alu_lsl16 | alu_lsr16 | + alu_ld16 | alu_st16 | alu_cpx => + cc_out(NBIT) <= out_alu(15); + when alu_tap => + cc_out(NBIT) <= left(NBIT); + when others => + cc_out(NBIT) <= cc(NBIT); + end case; + + -- + -- Interrupt mask flag + -- + case alu_ctrl is + when alu_sei => + cc_out(IBIT) <= '1'; -- set interrupt mask + when alu_cli => + cc_out(IBIT) <= '0'; -- clear interrupt mask + when alu_tap => + cc_out(IBIT) <= left(IBIT); + when others => + cc_out(IBIT) <= cc(IBIT); -- interrupt mask + end case; + + -- + -- Half Carry flag + -- + case alu_ctrl is + when alu_add8 | alu_adc => + cc_out(HBIT) <= (left(3) and right(3)) or + (right(3) and not out_alu(3)) or + (left(3) and not out_alu(3)); + when alu_tap => + cc_out(HBIT) <= left(HBIT); + when others => + cc_out(HBIT) <= cc(HBIT); + end case; + + -- + -- Overflow flag + -- + case alu_ctrl is + when alu_add8 | alu_adc => + cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or + ((not left(7)) and (not right(7)) and out_alu(7)); + when alu_sub8 | alu_sbc => + cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or + ((not left(7)) and right(7) and out_alu(7)); + when alu_add16 => + cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or + ((not left(15)) and (not right(15)) and out_alu(15)); + when alu_sub16 | alu_cpx => + cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or + ((not left(15)) and right(15) and out_alu(15)); + when alu_inc => + cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and + left(3) and left(2) and left(1) and left(0)); + when alu_dec | alu_neg => + cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and + (not left(3)) and (not left(2)) and (not left(1)) and (not left(0))); + when alu_asr8 => + cc_out(VBIT) <= left(0) xor left(7); + when alu_lsr8 | alu_lsr16 => + cc_out(VBIT) <= left(0); + when alu_ror8 => + cc_out(VBIT) <= left(0) xor cc(CBIT); + when alu_lsl16 => + cc_out(VBIT) <= left(15) xor left(14); + when alu_rol8 | alu_asl8 => + cc_out(VBIT) <= left(7) xor left(6); + when alu_tap => + cc_out(VBIT) <= left(VBIT); + when alu_and | alu_ora | alu_eor | alu_com | + alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | + alu_clv => + cc_out(VBIT) <= '0'; + when alu_sev => + cc_out(VBIT) <= '1'; + when others => + cc_out(VBIT) <= cc(VBIT); + end case; + + case alu_ctrl is + when alu_tap => + cc_out(XBIT) <= cc(XBIT) and left(XBIT); + cc_out(SBIT) <= left(SBIT); + when others => + cc_out(XBIT) <= cc(XBIT) and left(XBIT); + cc_out(SBIT) <= cc(SBIT); + end case; + + test_alu <= out_alu; + test_cc <= cc_out; +end process; + +------------------------------------ +-- +-- Detect Edge of NMI interrupt +-- +------------------------------------ + +nmi_handler : process( clk, rst, nmi, nmi_ack ) +begin + if clk'event and clk='0' then + if hold = '1' then + nmi_req <= nmi_req; + else + if rst='1' then + nmi_req <= '0'; + else + if (nmi='1') and (nmi_ack='0') then + nmi_req <= '1'; + else + if (nmi='0') and (nmi_ack='1') then + nmi_req <= '0'; + else + nmi_req <= nmi_req; + end if; + end if; + end if; + end if; + end if; +end process; + +------------------------------------ +-- +-- Nmi mux +-- +------------------------------------ + +nmi_mux: process( clk, nmi_ctrl, nmi_ack, hold ) +begin + if clk'event and clk='0' then + if hold = '1' then + nmi_ack <= nmi_ack; + else + case nmi_ctrl is + when set_nmi => + nmi_ack <= '1'; + when reset_nmi => + nmi_ack <= '0'; + when others => +-- when latch_nmi => + nmi_ack <= nmi_ack; + end case; + end if; + end if; +end process; + +------------------------------------ +-- +-- state sequencer +-- +------------------------------------ +process( state, op_code, cc, ea, irq, nmi_req, nmi_ack, hold, halt ) + begin + case state is + when reset_state => -- released from reset + -- reset the registers + op_ctrl <= reset_op; + acca_ctrl <= reset_acca; + accb_ctrl <= reset_accb; + ix_ctrl <= reset_ix; + sp_ctrl <= reset_sp; + pc_ctrl <= reset_pc; + ea_ctrl <= reset_ea; + md_ctrl <= reset_md; + iv_ctrl <= reset_iv; + nmi_ctrl <= reset_nmi; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= reset_cc; + -- idle the bus + dout_ctrl <= md_lo_dout; + addr_ctrl <= idle_ad; + next_state <= vect_hi_state; + + -- + -- Jump via interrupt vector + -- iv holds interrupt type + -- fetch PC hi from vector location + -- + when vect_hi_state => + -- default the registers + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + ea_ctrl <= latch_ea; + iv_ctrl <= latch_iv; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- fetch pc low interrupt vector + pc_ctrl <= pull_hi_pc; + addr_ctrl <= int_hi_ad; + dout_ctrl <= pc_hi_dout; + next_state <= vect_lo_state; + -- + -- jump via interrupt vector + -- iv holds vector type + -- fetch PC lo from vector location + -- + when vect_lo_state => + -- default the registers + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + ea_ctrl <= latch_ea; + iv_ctrl <= latch_iv; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- fetch the vector low byte + pc_ctrl <= pull_lo_pc; + addr_ctrl <= int_lo_ad; + dout_ctrl <= pc_lo_dout; + next_state <= fetch_state; + + -- + -- Here to fetch an instruction + -- PC points to opcode + -- Should service interrupt requests at this point + -- either from the timer + -- or from the external input. + -- + when fetch_state => + case op_code(7 downto 4) is + when "0000" | + "0001" | + "0010" | -- branch conditional + "0011" | + "0100" | -- acca single op + "0101" | -- accb single op + "0110" | -- indexed single op + "0111" => -- extended single op + -- idle ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + + when "1000" | -- acca immediate + "1001" | -- acca direct + "1010" | -- acca indexed + "1011" => -- acca extended + case op_code(3 downto 0) is + when "0000" => -- suba + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0001" => -- cmpa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0010" => -- sbca + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sbc; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0011" => -- subd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0100" => -- anda + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0101" => -- bita + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0110" => -- ldaa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0111" => -- staa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1000" => -- eora + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_eor; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1001" => -- adca + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_adc; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1010" => -- oraa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ora; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1011" => -- adda + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1100" => -- cpx + left_ctrl <= ix_left; + right_ctrl <= md_right; + alu_ctrl <= alu_cpx; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1101" => -- bsr / jsr + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1110" => -- lds + left_ctrl <= sp_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + when "1111" => -- sts + left_ctrl <= sp_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when others => + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + end case; + when "1100" | -- accb immediate + "1101" | -- accb direct + "1110" | -- accb indexed + "1111" => -- accb extended + case op_code(3 downto 0) is + when "0000" => -- subb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0001" => -- cmpb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0010" => -- sbcb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sbc; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0011" => -- addd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0100" => -- andb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0101" => -- bitb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0110" => -- ldab + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0111" => -- stab + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1000" => -- eorb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_eor; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1001" => -- adcb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_adc; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1010" => -- orab + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ora; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1011" => -- addb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1100" => -- ldd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1101" => -- std + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1110" => -- ldx + left_ctrl <= ix_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= load_ix; + sp_ctrl <= latch_sp; + when "1111" => -- stx + left_ctrl <= ix_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when others => + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + end case; + when others => + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + end case; + md_ctrl <= latch_md; + -- fetch the op code + op_ctrl <= fetch_op; + ea_ctrl <= reset_ea; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + iv_ctrl <= latch_iv; + if halt = '1' then + pc_ctrl <= latch_pc; + nmi_ctrl <= latch_nmi; + next_state <= halt_state; + -- service non maskable interrupts + elsif (nmi_req = '1') and (nmi_ack = '0') then + pc_ctrl <= latch_pc; + nmi_ctrl <= set_nmi; + next_state <= int_pcl_state; + -- service maskable interrupts + else + -- + -- nmi request is not cleared until nmi input goes low + -- + if(nmi_req = '0') and (nmi_ack='1') then + nmi_ctrl <= reset_nmi; + else + nmi_ctrl <= latch_nmi; + end if; + -- + -- IRQ is level sensitive + -- + if (irq = '1') and (cc(IBIT) = '0') then + pc_ctrl <= latch_pc; + next_state <= int_pcl_state; + else + -- Advance the PC to fetch next instruction byte + pc_ctrl <= inc_pc; + next_state <= decode_state; + end if; + end if; + -- + -- Here to decode instruction + -- and fetch next byte of intruction + -- whether it be necessary or not + -- + when decode_state => + -- fetch first byte of address or immediate data + ea_ctrl <= fetch_first_ea; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + iv_ctrl <= latch_iv; + case op_code(7 downto 4) is + when "0000" => + md_ctrl <= fetch_first_md; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + case op_code(3 downto 0) is + when "0001" => -- nop + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "0100" => -- lsrd + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + when "0101" => -- lsld + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_lsl16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + when "0110" => -- tap + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_tap; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "0111" => -- tpa + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_tpa; + cc_ctrl <= latch_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1000" => -- inx + left_ctrl <= ix_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inx; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= load_ix; + when "1001" => -- dex + left_ctrl <= ix_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dex; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= load_ix; + when "1010" => -- clv + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_clv; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1011" => -- sev + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sev; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1100" => -- clc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_clc; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1101" => -- sec + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sec; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1110" => -- cli + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_cli; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1111" => -- sei + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sei; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + end case; + next_state <= fetch_state; + -- acca / accb inherent instructions + when "0001" => + md_ctrl <= fetch_first_md; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + left_ctrl <= acca_left; + right_ctrl <= accb_right; + case op_code(3 downto 0) is + when "0000" => -- sba + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when "0001" => -- cba + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + when "0110" => -- tab + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + when "0111" => -- tba + alu_ctrl <= alu_ld8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when "1001" => -- daa + alu_ctrl <= alu_daa; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when "1011" => -- aba + alu_ctrl <= alu_add8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when others => + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end case; + next_state <= fetch_state; + when "0010" => -- branch conditional + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- increment the pc + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0000" => -- bra + next_state <= branch_state; + when "0001" => -- brn + next_state <= fetch_state; + when "0010" => -- bhi + if (cc(CBIT) or cc(ZBIT)) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0011" => -- bls + if (cc(CBIT) or cc(ZBIT)) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0100" => -- bcc/bhs + if cc(CBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0101" => -- bcs/blo + if cc(CBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0110" => -- bne + if cc(ZBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0111" => -- beq + if cc(ZBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1000" => -- bvc + if cc(VBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1001" => -- bvs + if cc(VBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1010" => -- bpl + if cc(NBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1011" => -- bmi + if cc(NBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1100" => -- bge + if (cc(NBIT) xor cc(VBIT)) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1101" => -- blt + if (cc(NBIT) xor cc(VBIT)) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1110" => -- bgt + if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1111" => -- ble + if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when others => + next_state <= fetch_state; + end case; + -- + -- Single byte stack operators + -- Do not advance PC + -- + when "0011" => + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + case op_code(3 downto 0) is + when "0000" => -- tsx + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= load_ix; + sp_ctrl <= latch_sp; + next_state <= fetch_state; + when "0001" => -- ins + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= fetch_state; + when "0010" => -- pula + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= pula_state; + when "0011" => -- pulb + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= pulb_state; + when "0100" => -- des + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= fetch_state; + when "0101" => -- txs + left_ctrl <= ix_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= fetch_state; + when "0110" => -- psha + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= psha_state; + when "0111" => -- pshb + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= pshb_state; + when "1000" => -- pulx + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= pulx_hi_state; + when "1001" => -- rts + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= rts_hi_state; + when "1010" => -- abx + left_ctrl <= ix_left; + right_ctrl <= accb_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= load_ix; + sp_ctrl <= latch_sp; + next_state <= fetch_state; + when "1011" => -- rti + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= rti_cc_state; + when "1100" => -- pshx + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= pshx_lo_state; + when "1101" => -- mul + left_ctrl <= acca_left; + right_ctrl <= accb_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= mul_state; + when "1110" => -- wai + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= int_pcl_state; + when "1111" => -- swi + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= int_pcl_state; + when others => + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= fetch_state; + end case; + -- + -- Accumulator A Single operand + -- source = Acc A dest = Acc A + -- Do not advance PC + -- + when "0100" => -- acca single op + md_ctrl <= fetch_first_md; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + left_ctrl <= acca_left; + case op_code(3 downto 0) is + when "0000" => -- neg + right_ctrl <= zero_right; + alu_ctrl <= alu_neg; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0011" => -- com + right_ctrl <= zero_right; + alu_ctrl <= alu_com; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0100" => -- lsr + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0110" => -- ror + right_ctrl <= zero_right; + alu_ctrl <= alu_ror8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0111" => -- asr + right_ctrl <= zero_right; + alu_ctrl <= alu_asr8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1000" => -- asl + right_ctrl <= zero_right; + alu_ctrl <= alu_asl8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1001" => -- rol + right_ctrl <= zero_right; + alu_ctrl <= alu_rol8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1010" => -- dec + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dec; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1011" => -- undefined + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + acca_ctrl <= latch_acca; + cc_ctrl <= latch_cc; + when "1100" => -- inc + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inc; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1101" => -- tst + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + acca_ctrl <= latch_acca; + cc_ctrl <= load_cc; + when "1110" => -- jmp + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + acca_ctrl <= latch_acca; + cc_ctrl <= latch_cc; + when "1111" => -- clr + right_ctrl <= zero_right; + alu_ctrl <= alu_clr; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when others => + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + acca_ctrl <= latch_acca; + cc_ctrl <= latch_cc; + end case; + next_state <= fetch_state; + -- + -- single operand acc b + -- Do not advance PC + -- + when "0101" => + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + pc_ctrl <= latch_pc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + left_ctrl <= accb_left; + case op_code(3 downto 0) is + when "0000" => -- neg + right_ctrl <= zero_right; + alu_ctrl <= alu_neg; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0011" => -- com + right_ctrl <= zero_right; + alu_ctrl <= alu_com; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0100" => -- lsr + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0110" => -- ror + right_ctrl <= zero_right; + alu_ctrl <= alu_ror8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0111" => -- asr + right_ctrl <= zero_right; + alu_ctrl <= alu_asr8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1000" => -- asl + right_ctrl <= zero_right; + alu_ctrl <= alu_asl8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1001" => -- rol + right_ctrl <= zero_right; + alu_ctrl <= alu_rol8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1010" => -- dec + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dec; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1011" => -- undefined + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + accb_ctrl <= latch_accb; + cc_ctrl <= latch_cc; + when "1100" => -- inc + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inc; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1101" => -- tst + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + accb_ctrl <= latch_accb; + cc_ctrl <= load_cc; + when "1110" => -- jmp + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + accb_ctrl <= latch_accb; + cc_ctrl <= latch_cc; + when "1111" => -- clr + right_ctrl <= zero_right; + alu_ctrl <= alu_clr; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when others => + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + accb_ctrl <= latch_accb; + cc_ctrl <= latch_cc; + end case; + next_state <= fetch_state; + -- + -- Single operand indexed + -- Two byte instruction so advance PC + -- EA should hold index offset + -- + when "0110" => -- indexed single op + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= indexed_state; + -- + -- Single operand extended addressing + -- three byte instruction so advance the PC + -- Low order EA holds high order address + -- + when "0111" => -- extended single op + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= extended_state; + + when "1000" => -- acca immediate + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0011" | -- subdd # + "1100" | -- cpx # + "1110" => -- lds # + next_state <= immediate16_state; + when "1101" => -- bsr + next_state <= bsr_state; + when others => + next_state <= fetch_state; + end case; + + when "1001" => -- acca direct + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0111" => -- staa direct + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1111" => -- sts direct + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1101" => -- jsr direct + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + next_state <= jsr_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + next_state <= read8_state; + end case; + + when "1010" => -- acca indexed + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= indexed_state; + + when "1011" => -- acca extended + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= extended_state; + + when "1100" => -- accb immediate + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0011" | -- addd # + "1100" | -- ldd # + "1110" => -- ldx # + next_state <= immediate16_state; + when others => + next_state <= fetch_state; + end case; + + when "1101" => -- accb direct + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0111" => -- stab direct + left_ctrl <= accb_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- std direct + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1111" => -- stx direct + left_ctrl <= ix_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + next_state <= read8_state; + end case; + + when "1110" => -- accb indexed + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= indexed_state; + + when "1111" => -- accb extended + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= extended_state; + + when others => + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- idle the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= latch_pc; + next_state <= fetch_state; + end case; + + when immediate16_state => + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + op_ctrl <= latch_op; + iv_ctrl <= latch_iv; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + -- fetch next immediate byte + md_ctrl <= fetch_next_md; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + -- + -- ea holds 8 bit index offet + -- calculate the effective memory address + -- using the alu + -- + when indexed_state => + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- calculate effective address from index reg + -- index offest is not sign extended + ea_ctrl <= add_ix_ea; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + -- work out next state + case op_code(7 downto 4) is + when "0110" => -- single op indexed + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + case op_code(3 downto 0) is + when "1011" => -- undefined + next_state <= fetch_state; + when "1110" => -- jmp + next_state <= jmp_state; + when others => + next_state <= read8_state; + end case; + when "1010" => -- acca indexed + case op_code(3 downto 0) is + when "0111" => -- staa + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- jsr + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= jsr_state; + when "1111" => -- sts + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when "1110" => -- accb indexed + case op_code(3 downto 0) is + when "0111" => -- stab direct + left_ctrl <= accb_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- std direct + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1111" => -- stx direct + left_ctrl <= ix_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when others => + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + next_state <= fetch_state; + end case; + -- + -- ea holds the low byte of the absolute address + -- Move ea low byte into ea high byte + -- load new ea low byte to for absolute 16 bit address + -- advance the program counter + -- + when extended_state => -- fetch ea low byte + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- increment pc + pc_ctrl <= inc_pc; + -- fetch next effective address bytes + ea_ctrl <= fetch_next_ea; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + -- work out the next state + case op_code(7 downto 4) is + when "0111" => -- single op extended + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + case op_code(3 downto 0) is + when "1011" => -- undefined + next_state <= fetch_state; + when "1110" => -- jmp + next_state <= jmp_state; + when others => + next_state <= read8_state; + end case; + when "1011" => -- acca extended + case op_code(3 downto 0) is + when "0111" => -- staa + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- jsr + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= jsr_state; + when "1111" => -- sts + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when "1111" => -- accb extended + case op_code(3 downto 0) is + when "0111" => -- stab + left_ctrl <= accb_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- std + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1111" => -- stx + left_ctrl <= ix_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when others => + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + next_state <= fetch_state; + end case; + -- + -- here if ea holds low byte (direct page) + -- can enter here from extended addressing + -- read memory location + -- note that reads may be 8 or 16 bits + -- + when read8_state => -- read data + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- + addr_ctrl <= read_ad; + dout_ctrl <= md_lo_dout; + case op_code(7 downto 4) is + when "0110" | "0111" => -- single operand + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= execute_state; + + when "1001" | "1010" | "1011" => -- acca + case op_code(3 downto 0) is + when "0011" | -- subd + "1110" | -- lds + "1100" => -- cpx + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + -- increment the effective address in case of 16 bit load + ea_ctrl <= inc_ea; + next_state <= read16_state; +-- when "0111" => -- staa +-- left_ctrl <= acca_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st8; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write8_state; +-- when "1101" => -- jsr +-- left_ctrl <= acca_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_nop; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= latch_md; +-- ea_ctrl <= latch_ea; +-- next_state <= jsr_state; +-- when "1111" => -- sts +-- left_ctrl <= sp_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st16; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= fetch_state; + end case; + + when "1101" | "1110" | "1111" => -- accb + case op_code(3 downto 0) is + when "0011" | -- addd + "1100" | -- ldd + "1110" => -- ldx + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + -- increment the effective address in case of 16 bit load + ea_ctrl <= inc_ea; + next_state <= read16_state; +-- when "0111" => -- stab +-- left_ctrl <= accb_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st8; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write8_state; +-- when "1101" => -- std +-- left_ctrl <= accd_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st16; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write16_state; +-- when "1111" => -- stx +-- left_ctrl <= ix_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st16; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= execute_state; + end case; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= fetch_state; + end case; + + when read16_state => -- read second data byte from ea + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- idle the effective address + ea_ctrl <= latch_ea; + -- read the low byte of the 16 bit data + md_ctrl <= fetch_next_md; + addr_ctrl <= read_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + -- + -- 16 bit Write state + -- write high byte of ALU output. + -- EA hold address of memory to write to + -- Advance the effective address in ALU + -- + when write16_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- increment the effective address + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ea_ctrl <= inc_ea; + -- write the ALU hi byte to ea + addr_ctrl <= write_ad; + dout_ctrl <= md_hi_dout; + next_state <= write8_state; + -- + -- 8 bit write + -- Write low 8 bits of ALU output + -- + when write8_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- write ALU low byte output + addr_ctrl <= write_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when jmp_state => + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- load PC with effective address + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= load_ea_pc; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when jsr_state => -- JSR + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc low + addr_ctrl <= push_ad; + dout_ctrl <= pc_lo_dout; + next_state <= jsr1_state; + + when jsr1_state => -- JSR + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc hi + addr_ctrl <= push_ad; + dout_ctrl <= pc_hi_dout; + next_state <= jmp_state; + + when branch_state => -- Bcc + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- calculate signed branch + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= add_ea_pc; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when bsr_state => -- BSR + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc low + addr_ctrl <= push_ad; + dout_ctrl <= pc_lo_dout; + next_state <= bsr1_state; + + when bsr1_state => -- BSR + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc hi + addr_ctrl <= push_ad; + dout_ctrl <= pc_hi_dout; + next_state <= branch_state; + + when rts_hi_state => -- RTS + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment the sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read pc hi + pc_ctrl <= pull_hi_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_hi_dout; + next_state <= rts_lo_state; + + when rts_lo_state => -- RTS1 + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- read pc low + pc_ctrl <= pull_lo_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_lo_dout; + next_state <= fetch_state; + + when mul_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- move acca to md + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mulea_state; + + when mulea_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + md_ctrl <= latch_md; + -- idle ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- move accb to ea + ea_ctrl <= load_accb_ea; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= muld_state; + + when muld_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + md_ctrl <= latch_md; + -- clear accd + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_ld8; + cc_ctrl <= latch_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul0_state; + + when mul0_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 0 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(0) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul1_state; + + when mul1_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 1 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(1) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul2_state; + + when mul2_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 2 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(2) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul3_state; + + when mul3_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 3 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(3) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul4_state; + + when mul4_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 4 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(4) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul5_state; + + when mul5_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 5 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(5) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul6_state; + + when mul6_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 6 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(6) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul7_state; + + when mul7_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 7 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(7) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when execute_state => -- execute single operand instruction + -- default + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + case op_code(7 downto 4) is + when "0110" | -- indexed single op + "0111" => -- extended single op + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + ea_ctrl <= latch_ea; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + left_ctrl <= md_left; + case op_code(3 downto 0) is + when "0000" => -- neg + right_ctrl <= zero_right; + alu_ctrl <= alu_neg; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0011" => -- com + right_ctrl <= zero_right; + alu_ctrl <= alu_com; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0100" => -- lsr + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0110" => -- ror + right_ctrl <= zero_right; + alu_ctrl <= alu_ror8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0111" => -- asr + right_ctrl <= zero_right; + alu_ctrl <= alu_asr8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1000" => -- asl + right_ctrl <= zero_right; + alu_ctrl <= alu_asl8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1001" => -- rol + right_ctrl <= zero_right; + alu_ctrl <= alu_rol8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1010" => -- dec + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dec; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1011" => -- undefined + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + when "1100" => -- inc + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inc; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- tst + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + when "1110" => -- jmp + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + when "1111" => -- clr + right_ctrl <= zero_right; + alu_ctrl <= alu_clr; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when others => + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + end case; + + when others => + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + ea_ctrl <= latch_ea; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + end case; + + when psha_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write acca + addr_ctrl <= push_ad; + dout_ctrl <= acca_dout; + next_state <= fetch_state; + + when pula_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- read acca + acca_ctrl <= pull_acca; + addr_ctrl <= pull_ad; + dout_ctrl <= acca_dout; + next_state <= fetch_state; + + when pshb_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write accb + addr_ctrl <= push_ad; + dout_ctrl <= accb_dout; + next_state <= fetch_state; + + when pulb_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- read accb + accb_ctrl <= pull_accb; + addr_ctrl <= pull_ad; + dout_ctrl <= accb_dout; + next_state <= fetch_state; + + when pshx_lo_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix low + addr_ctrl <= push_ad; + dout_ctrl <= ix_lo_dout; + next_state <= pshx_hi_state; + + when pshx_hi_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix hi + addr_ctrl <= push_ad; + dout_ctrl <= ix_hi_dout; + next_state <= fetch_state; + + when pulx_hi_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- pull ix hi + ix_ctrl <= pull_hi_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_hi_dout; + next_state <= pulx_lo_state; + + when pulx_lo_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- read ix low + ix_ctrl <= pull_lo_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_lo_dout; + next_state <= fetch_state; + + -- + -- return from interrupt + -- enter here from bogus interrupts + -- + when rti_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- idle address bus + cc_ctrl <= latch_cc; + addr_ctrl <= idle_ad; + dout_ctrl <= cc_dout; + next_state <= rti_cc_state; + + when rti_cc_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read cc + cc_ctrl <= pull_cc; + addr_ctrl <= pull_ad; + dout_ctrl <= cc_dout; + next_state <= rti_accb_state; + + when rti_accb_state => + -- default registers + acca_ctrl <= latch_acca; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read accb + accb_ctrl <= pull_accb; + addr_ctrl <= pull_ad; + dout_ctrl <= accb_dout; + next_state <= rti_acca_state; + + when rti_acca_state => + -- default registers + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read acca + acca_ctrl <= pull_acca; + addr_ctrl <= pull_ad; + dout_ctrl <= acca_dout; + next_state <= rti_ixh_state; + + when rti_ixh_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read ix hi + ix_ctrl <= pull_hi_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_hi_dout; + next_state <= rti_ixl_state; + + when rti_ixl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read ix low + ix_ctrl <= pull_lo_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_lo_dout; + next_state <= rti_pch_state; + + when rti_pch_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- pull pc hi + pc_ctrl <= pull_hi_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_hi_dout; + next_state <= rti_pcl_state; + + when rti_pcl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- pull pc low + pc_ctrl <= pull_lo_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_lo_dout; + next_state <= fetch_state; + + -- + -- here on interrupt + -- iv register hold interrupt type + -- + when int_pcl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc low + addr_ctrl <= push_ad; + dout_ctrl <= pc_lo_dout; + next_state <= int_pch_state; + + when int_pch_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc hi + addr_ctrl <= push_ad; + dout_ctrl <= pc_hi_dout; + next_state <= int_ixl_state; + + when int_ixl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix low + addr_ctrl <= push_ad; + dout_ctrl <= ix_lo_dout; + next_state <= int_ixh_state; + + when int_ixh_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix hi + addr_ctrl <= push_ad; + dout_ctrl <= ix_hi_dout; + next_state <= int_acca_state; + + when int_acca_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write acca + addr_ctrl <= push_ad; + dout_ctrl <= acca_dout; + next_state <= int_accb_state; + + + when int_accb_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write accb + addr_ctrl <= push_ad; + dout_ctrl <= accb_dout; + next_state <= int_cc_state; + + when int_cc_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write cc + addr_ctrl <= push_ad; + dout_ctrl <= cc_dout; + nmi_ctrl <= latch_nmi; + -- + -- nmi is edge triggered + -- nmi_req is cleared when nmi goes low. + -- + if nmi_req = '1' then + iv_ctrl <= nmi_iv; + next_state <= vect_hi_state; + else + -- + -- IRQ is level sensitive + -- + if (irq = '1') and (cc(IBIT) = '0') then + iv_ctrl <= irq_iv; + next_state <= int_mask_state; + else + case op_code is + when "00111110" => -- WAI (wait for interrupt) + iv_ctrl <= latch_iv; + next_state <= int_wai_state; + when "00111111" => -- SWI (Software interrupt) + iv_ctrl <= swi_iv; + next_state <= vect_hi_state; + when others => -- bogus interrupt (return) + iv_ctrl <= latch_iv; + next_state <= rti_state; + end case; + end if; + end if; + + when int_wai_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + op_ctrl <= latch_op; + ea_ctrl <= latch_ea; + -- enable interrupts + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_cli; + cc_ctrl <= load_cc; + sp_ctrl <= latch_sp; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= cc_dout; + if (nmi_req = '1') and (nmi_ack='0') then + iv_ctrl <= nmi_iv; + nmi_ctrl <= set_nmi; + next_state <= vect_hi_state; + else + -- + -- nmi request is not cleared until nmi input goes low + -- + if (nmi_req = '0') and (nmi_ack='1') then + nmi_ctrl <= reset_nmi; + else + nmi_ctrl <= latch_nmi; + end if; + -- + -- IRQ is level sensitive + -- + if (irq = '1') and (cc(IBIT) = '0') then + iv_ctrl <= irq_iv; + next_state <= int_mask_state; + else + iv_ctrl <= latch_iv; + next_state <= int_wai_state; + end if; + end if; + + when int_mask_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- Mask IRQ + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sei; + cc_ctrl <= load_cc; + sp_ctrl <= latch_sp; + -- idle bus cycle + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= vect_hi_state; + + when halt_state => -- halt CPU. + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- do nothing in ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- idle bus cycle + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + if halt = '1' then + next_state <= halt_state; + else + next_state <= fetch_state; + end if; + + when others => -- error state halt on undefine states + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- do nothing in ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- idle bus cycle + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= error_state; + end case; +end process; + +-------------------------------- +-- +-- state machine +-- +-------------------------------- + +change_state: process( clk, rst, state, hold ) +begin + if clk'event and clk = '0' then + if rst = '1' then + state <= reset_state; + elsif hold = '1' then + state <= state; + else + state <= next_state; + end if; + end if; +end process; + -- output + +end CPU_ARCH; + diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/dac.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/dac.vhd new file mode 100644 index 00000000..47b2185e --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 10 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/data_io.v b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/data_io.v new file mode 100644 index 00000000..4ca9518c --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/data_io.v @@ -0,0 +1,115 @@ +// +// data_io.v +// +// data_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +module data_io +( + input clk_sys, + input SPI_SCK, + input SPI_SS2, + input SPI_DI, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender.vhd new file mode 100644 index 00000000..2ac38c26 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender.vhd @@ -0,0 +1,780 @@ +--------------------------------------------------------------------------------- +-- Defender by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- cpu09l - Version : 0128 +-- Synthesizable 6809 instruction compatible VHDL CPU core +-- Copyright (C) 2003 - 2010 John Kent +--------------------------------------------------------------------------------- +-- cpu68 - Version 9th Jan 2004 0.8 +-- 6800/01 compatible CPU core +-- GNU public license - December 2002 : John E. Kent +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- Version 0.0 -- 15/10/2017 -- +-- initial version +--------------------------------------------------------------------------------- +-- Features : +-- TV 15KHz mode only (atm) +-- Cocktail mode : OK +-- +-- Use with MAME roms from defender.zip +-- +-- Use make_defender_proms.bat to build vhd file and bin from binaries +-- +-- Defender Hardware caracteristics : +-- +-- 1x6809 CPU accessing program rom and shared ram/devices +-- 3x16Ko video and working ram +-- 26Ko program roms +-- 1 pia for player I/O +-- 1 pia service switches, irq and sound selection to sound board +-- +-- 384 pixels x 260 line video scan, 16 colors per pixel +-- Ram palette 16 colors among 256 colors (3 red bits,3 green bits, 2 blue bits) +-- +-- 2 decoder proms for video scan and cocktail/upright flip +-- +-- No sprites, no char tiles +-- +-- 128x4 cmos ram (see defender_cmos_ram.vhd for initial values) +-- No save when power off (see also defender_cmos_ram.vhd) +-- +-- 1x6808/02 +-- 128x8 working ram +-- 4k program rom +-- 1 pia for sound selection cmd input and audio samples output + +--------------------------------------------------------------------------------- + +--------------------------------------------------------------------------------- +-- defender cmos data (see also defender_cmos_ram.vhd) +-- (ram is 128x4 => only 4 bits/address, that is only 1 hex digit/address) +-- +-- @ values - (fonction) meaning + +-- 0 0 - ? +-- 1 0005 - (01) coins left +-- 5 0000 - (02) coins center +-- 9 0000 - (03) coins right +-- 13 0005 - (04) total paid +-- 17 0000 - (05) ships won +---21 0000 - (06) total time +-- 25 0003 - (07) total ships + +-- -- 8 entries of 6 digits highscore + 3 ascii letters + +-- 29 021270 44 52 4A +-- 41 018315 53 41 4D +-- 53 015920 4C 45 44 +-- 65 014285 50 47 44 +-- 77 012520 43 52 42 +-- 89 011035 4D 52 53 +-- 101 008265 53 53 52 +-- 113 006010 54 4D 48 + +-- 125 00 - credits +-- 127 5 - ? + +-- -- protected data writeable only with coin door opened + +-- 128 A - ? +-- 129 0100 - (08) bonus ship level +-- 133 03 - (09) nb ships +-- 135 03 - (10) coinage select +-- 137 01 - (11) left coin mult +-- 139 04 - (12) center coin mult +-- 141 01 - (13) right coin mult +-- 143 01 - (14) coins for credit +-- 145 00 - (15) coins for bonus +-- 147 00 - (16) minimum coins +-- 149 00 - (17) free play +-- 151 05 - (18) game adjust 1 Stating difficulty 0=lib; 1=mod; 2=cons +-- 153 15 - (19) game adjust 2 Progessive wave diff. limit > 4-25 +-- 155 01 - (20) game adjust 3 Background sound 0=off; 1=on +-- 157 05 - (21) game adjust 4 Planet restore wave number +-- 159 00 - (22) game adjust 5 +-- 161 00 - (23) game adjust 6 +-- 163 00 - (24) game adjust 7 +-- 165 00 - (25) game adjust 8 +-- 167 00 - (26) game adjust 9 +-- 169 00 - (27) game adjust 10 + +-- 171 00000 - ? +-- 176 0000000000000000 - ? +-- 192 0000000000000000 - ? +-- 208 0000000000000000 - ? +-- 224 0000000000000000 - ? +-- 240 0000000000000000 - ? + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity defender is +port( + clk_sys : in std_logic; + clock_6 : in std_logic; + clk_1p79 : in std_logic; + clk_0p89 : in std_logic; + reset : in std_logic; + + dbg_cpu_addr : out std_logic_vector(15 downto 0); +-- tv15Khz_mode : in std_logic; + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(1 downto 0); +-- video_clk : out std_logic; + video_csync : out std_logic; + video_blankn : out std_logic; + video_hs : out std_logic; + video_vs : out std_logic; + + audio_out : out std_logic_vector(7 downto 0); + + roms_addr : out std_logic_vector(14 downto 0); + roms_do : in std_logic_vector( 7 downto 0); + + btn_left_coin : in std_logic; + btn_one_player : in std_logic; + btn_two_players: in std_logic; + + btn_fire : in std_logic; + btn_fire2 : in std_logic; + btn_right : in std_logic; + btn_left : in std_logic; + btn_down : in std_logic; + btn_up : in std_logic; + + sw_coktail_table : in std_logic; + + cmd_select_players_btn : out std_logic + +); +end defender; + +architecture struct of defender is + + signal reset_n: std_logic; + signal clock_div : std_logic_vector(1 downto 0); + + signal clock_6n : std_logic; + + signal cpu_clock : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_rw : std_logic; + signal cpu_irq : std_logic; + + signal wram_addr : std_logic_vector(13 downto 0); + signal wram_we : std_logic; + signal wram0_do : std_logic_vector( 7 downto 0); + signal wram0_we : std_logic; + signal wram1_do : std_logic_vector( 7 downto 0); + signal wram1_we : std_logic; + signal wram2_do : std_logic_vector( 7 downto 0); + signal wram2_we : std_logic; + + --signal roms_addr : std_logic_vector(14 downto 0); + --signal roms_do : std_logic_vector( 7 downto 0); + + signal roms_io_do : std_logic_vector( 7 downto 0); + + signal io_we : std_logic; + signal io_CS : std_logic; + + signal rom_page : std_logic_vector( 2 downto 0); + signal rom_page_we : std_logic; + + signal screen_ctrl : std_logic; + signal screen_ctrl_we : std_logic; + + signal cmos_do : std_logic_vector(3 downto 0); + signal cmos_we : std_logic; + + signal palette_addr : std_logic_vector(3 downto 0); + signal palette_we : std_logic; + signal palette_di : std_logic_vector( 7 downto 0); + signal palette_do : std_logic_vector( 7 downto 0); + + signal pias_clock : std_logic; + +-- pia io port a +-- bit 0 Fire +-- bit 1 Thrust +-- bit 2 Smart Bomb +-- bit 3 HyperSpace +-- bit 4 2 Players +-- bit 5 1 Player +-- bit 6 Reverse +-- bit 7 Down + +-- pia io port b +-- bit 0 Up +-- bit 7 1 for coktail table, 0 for upright cabinet +-- other <= GND + +-- pia io ca/cb +-- ca1, ca2, cb1 <= GND +-- cb2 ouput + w2_jumper => select player 1/2 buttons for COCktail table + + signal pia_io_CS : std_logic; + signal pia_io_rw_n : std_logic; + signal pia_io_do : std_logic_vector( 7 downto 0); + signal pia_io_pa_i : std_logic_vector( 7 downto 0); + signal pia_io_pb_i : std_logic_vector( 7 downto 0); + signal pia_io_cb2_o : std_logic; + +-- pia rom board port a +-- bit 0 Auto Up / manual Down +-- bit 1 Advance +-- bit 2 Right Coin (nc) +-- bit 3 High Score Reset +-- bit 4 Left Coin +-- bit 5 Center Coin (nc) +-- bit 6 led 2 (output) +-- bit 7 led 1 (output) + +-- pia rom board port b +-- bit 0-5 to sound board (output) +-- bit 6 led 4 (output) +-- bit 7 led 3 (output) + +-- pia rom board ca/cb +-- ca1 count 240 +-- ca2 coin door pin 7 (nc) +-- cb1 4ms +-- cb2 sound board pin 8 (H5-nc) + + signal pia_ROM_CS : std_logic; + signal pia_rom_rw_n : std_logic; + signal pia_rom_do : std_logic_vector( 7 downto 0); + signal pia_rom_irqa : std_logic; + signal pia_rom_irqb : std_logic; + signal pia_rom_pa_i : std_logic_vector( 7 downto 0); + signal pia_rom_pa_o : std_logic_vector( 7 downto 0); + signal pia_rom_pb_o : std_logic_vector( 7 downto 0); + + signal vcnt_240 : std_logic; + signal cnt_4ms : std_logic; + + signal cpu_to_video_addr : std_logic_vector(8 downto 0); + signal cpu_to_video_do : std_logic_vector(7 downto 0); + + signal video_scan_addr : std_logic_vector(8 downto 0); + signal video_scan_do : std_logic_vector(7 downto 0); + + signal pixel_cnt : std_logic_vector(2 downto 0); + signal hcnt : std_logic_vector(5 downto 0); + signal vcnt : std_logic_vector(8 downto 0); + + signal pixels : std_logic_vector(23 downto 0); + + signal hsync0,hsync1,hsync2,csync,hblank,vblank : std_logic; + + signal select_sound : std_logic_vector(5 downto 0); + +begin + +clock_6n <= not clock_6; +reset_n <= not reset; + +-- for debug +dbg_cpu_addr <= cpu_addr; + + +-- make pixels counters and cpu clock +-- in original hardware cpu clock = 1us = 6pixels +-- here one make 2 cpu clock within 1us +process (reset, clock_6n) +begin + if reset='1' then + pixel_cnt <= "000"; + cpu_clock <= '0'; + else + if rising_edge(clock_6n) then + + if pixel_cnt = "101" then + pixel_cnt <= "000"; + cpu_clock <= '0'; + else + pixel_cnt <= pixel_cnt + '1'; + end if; + + if pixel_cnt = "010" then + cpu_clock <= '1'; + end if; + + if pixel_cnt = "011" then -- speed up processor (two clocks / 1us) + cpu_clock <= '0'; + end if; + + if pixel_cnt = "100" then + cpu_clock <= '1'; + end if; + + + end if; + end if; +end process; + +-- make hcnt and vcnt video scanner from pixel clocks and counts +-- +-- pixels |0|1|2|3|4|5|0|1|2|3|4|5| +-- hcnt | N | N+1 | +-- +-- hcnt [0..63] => 64 x 6 = 384 pixels, 1 pixel is 1us => 1 line is 64us (15.625KHz) +-- vcnt [252..255,256..511] => 260 lines, 1 frame is 260 x 64us = 16.640ms (60.1Hz) +-- +process (reset, clock_6n) +begin + if reset='1' then + hcnt <= "000000"; + vcnt <= '0'&X"FC"; + else + if rising_edge(clock_6n) then + + if pixel_cnt = "101" then + hcnt <= hcnt + '1'; + if hcnt = "111111" then + if vcnt = '1'&X"FF" then + vcnt <= '0'&X"FC"; + else + vcnt <= vcnt + '1'; + end if; + end if; + end if; + + end if; + end if; +end process; + +-- rom address multiplexer +-- should reflect content of defender_prog.bin +-- +-- 4k 0000-0FFF cpu_space D000-DFFF defend.1 + defend.4 +-- 4k 1000-1FFF E000-EFFF defend.2 +-- 4k 2000-2FFF F000-FFFF defend.3 +-- 4k 3000-3FFF page=1 C000-CFFF defend.9 + defend.12 +-- 4k 4000-4FFF page=2 C000-CFFF defend.8 + defend.11 +-- 4k 5000-5FFF page=3 C000-CFFF defend.7 + defend.10 +-- 4k 6000-6FFF page=7 C000-C7FF defend.6 + 2k empty +-- 4k 7000-7FFF N.A 4k empty + +roms_addr <= + "011" & cpu_addr(11 downto 0) when cpu_addr(15 downto 12) = X"C" and rom_page = "001" else + "100" & cpu_addr(11 downto 0) when cpu_addr(15 downto 12) = X"C" and rom_page = "010" else + "101" & cpu_addr(11 downto 0) when cpu_addr(15 downto 12) = X"C" and rom_page = "011" else + "110" & cpu_addr(11 downto 0) when cpu_addr(15 downto 12) = X"C" and rom_page = "111" else + "000" & cpu_addr(11 downto 0) when cpu_addr(15 downto 12) = X"D" else + "001" & cpu_addr(11 downto 0) when cpu_addr(15 downto 12) = X"E" else + "010" & cpu_addr(11 downto 0) ;--when cpu_addr(15 downto 12) = X"F"; + +-- encoded cpu addr (decoder.2) and encoded scan addr (decoder.3) +-- and screen control for cocktail table flip +cpu_to_video_addr <= screen_ctrl & cpu_addr(15 downto 8); +video_scan_addr <= screen_ctrl & vcnt(7 downto 0); + +-- mux cpu addr/scan addr to wram +wram_addr <= + cpu_addr(7 downto 0) & cpu_to_video_do(5 downto 0) when cpu_clock = '1' else + video_scan_do & hcnt; + +-- mux cpu addr/pixels data to palette addr +palette_addr <= + cpu_addr(3 downto 0) when palette_we = '1' else + pixels(23 downto 20) when screen_ctrl = '0' else pixels(3 downto 0); + +-- only cpu can write to palette +palette_di <= cpu_do; + +-- palette output to colors bits +video_r <= palette_do(2 downto 0); +video_g <= palette_do(5 downto 3); +video_b <= palette_do(7 downto 6); + + +-- 24 bits pixels shift register +-- 6 pixels of 4 bits +process (clock_6) +begin + if rising_edge(clock_6) then + if screen_ctrl = '0' then + if pixel_cnt = "001" then + pixels <= wram0_do & wram1_do & wram2_do; + else + pixels <= pixels(19 downto 0) & X"0" ; + end if; + else + if pixel_cnt = "001" then + pixels <= wram2_do & wram1_do & wram0_do; + else + pixels <= X"0" & pixels(23 downto 4); + end if; + end if; + end if; +end process; + +-- pias cs +io_cs <= '1' when cpu_clock = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; +pia_rom_cs <= '1' when io_cs = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '0' else '0'; -- CC00-CC03 +pia_io_cs <= '1' when io_cs = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '1' else '0'; -- CC04-CC07 + +-- write enables +wram_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) < X"C" else '0'; +io_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; +rom_page_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) = X"D" else '0'; + +palette_we <= '1' when io_we = '1' and cpu_addr(11 downto 10) = "00" and cpu_addr(4) = '0' else '0'; -- C000-C00F +screen_ctrl_we <= '1' when io_we = '1' and cpu_addr(11 downto 10) = "00" and cpu_addr(4) = '1' else '0'; -- C010-C01F +cmos_we <= '1' when io_we = '1' and cpu_addr(11 downto 10) = "01" else '0'; -- C400-C7FF +pia_rom_rw_n <= '0' when io_we = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '0' else '1'; -- CC00-CC03 +pia_io_rw_n <= '0' when io_we = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '1' else '1'; -- CC04-CC07 + +-- mux io data between cmos/video register/pias/c000_rom_page +roms_io_do <= + X"0"&cmos_do when rom_page = "000" and cpu_addr(11 downto 10) = "01" else -- C400-C7FF + vcnt(7 downto 2)&"00" when rom_page = "000" and cpu_addr(11 downto 10) = "10" else -- C800-cBFF + pia_rom_do when rom_page = "000" and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '0' else -- CC00-CC03 (A2n.A3n.A4n) + pia_io_do when rom_page = "000" and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '1' else -- CC04-CC07 (A2.A3n) + roms_do; + +-- mux cpu in data between roms/io/wram +cpu_di <= + roms_do when cpu_addr(15 downto 12) >= X"D" else + roms_io_do when cpu_addr(15 downto 12) >= X"C" else + wram0_do when cpu_to_video_do(7 downto 6) = "00" else + wram1_do when cpu_to_video_do(7 downto 6) = "01" else + wram2_do when cpu_to_video_do(7 downto 6) = "10" else X"00"; + + +-- dispatch cpu we to devices with respect to decoder2 bits 7-6 +wram0_we <= '1' when wram_we = '1' and cpu_to_video_do(7 downto 6) = "00" else '0'; +wram1_we <= '1' when wram_we = '1' and cpu_to_video_do(7 downto 6) = "01" else '0'; +wram2_we <= '1' when wram_we = '1' and cpu_to_video_do(7 downto 6) = "10" else '0'; + + +-- rom bank page (and IO) select register +-- screen control register +process (reset, clock_6) +begin + if reset='1' then + rom_page <= "000"; + screen_ctrl <= '0'; + else + if rising_edge(clock_6) then + if rom_page_we = '1' then rom_page <= cpu_do(2 downto 0); end if; + if screen_ctrl_we = '1' then screen_ctrl <= cpu_do(0); end if; + end if; + end if; +end process; + +-- pia rom board port a +-- bit 0 Auto Up / manual Down +-- bit 1 Advance +-- bit 2 Right Coin (nc) +-- bit 3 High Score Reset +-- bit 4 Left Coin +-- bit 5 Center Coin (nc) +-- bit 6 led 2 (output) +-- bit 7 led 1 (output) + +pias_clock <= clock_6; --not cpu_clock; + +pia_rom_pa_i(0) <= '0'; +pia_rom_pa_i(1) <= '0'; +pia_rom_pa_i(2) <= '0'; +pia_rom_pa_i(3) <= '0'; +pia_rom_pa_i(4) <= btn_left_coin; +pia_rom_pa_i(5) <= '0'; +pia_rom_pa_i(6) <= '0'; +pia_rom_pa_i(7) <= '0'; + +-- IN0 +pia_io_pa_i(0) <= btn_up; +pia_io_pa_i(1) <= btn_down; +pia_io_pa_i(2) <= btn_left; +pia_io_pa_i(3) <= btn_right; +pia_io_pa_i(4) <= btn_two_players; +pia_io_pa_i(5) <= btn_one_player; +pia_io_pa_i(6) <= btn_fire; +pia_io_pa_i(7) <= btn_fire2; + +-- IN1 +pia_io_pb_i <= "00000000";--unknown/Level completed/Level completed/unknown/Lives/Coinage/Coinage/Coinage + +-- IN2 +-- pia io ca/cb +cmd_select_players_btn <= pia_io_cb2_o; + +-- pia rom ca1/Cb1 +vcnt_240 <= '1' when vcnt(7 downto 4) = X"F" else '0'; +cnt_4ms <= vcnt(5); + +-- pia rom irqs to cpu +cpu_irq <= pia_rom_irqa or pia_rom_irqb; + +-- pia rom to sound board +select_sound <= pia_rom_pb_o(5 downto 0); + + +-- microprocessor 6809 +main_cpu : entity work.cpu09 +port map( + clk => cpu_clock,-- E clock input (falling edge) + rst => reset, -- reset input (active high) + vma => open, -- valid memory address (active high) + lic_out => open, -- last instruction cycle (active high) + ifetch => open, -- instruction fetch cycle (active high) + opfetch => open, -- opcode fetch (active high) + ba => open, -- bus available (high on sync wait or DMA grant) + bs => open, -- bus status (high on interrupt or reset vector fetch or DMA grant) + addr => cpu_addr, -- address bus output + rw => cpu_rw, -- read not write output + data_out => cpu_do, -- data bus output + data_in => cpu_di, -- data bus input + irq => cpu_irq, -- interrupt request input (active high) + firq => '0', -- fast interrupt request input (active high) + nmi => '0', -- non maskable interrupt request input (active high) + halt => '0', -- halt input (active high) grants DMA + hold => '0' -- hold input (active high) extend bus cycle +); + +-- cpu program rom +-- 4k D000-DFFF +-- 4k E000-EFFF +-- 4k F000-FFFF +-- 4K C000-CFFF page=1 +-- 4K C000-CFFF page=2 +-- 4K C000-CFFF page=3 +-- 2K C000-C7FF page=7 +-- 6K N.A. + + + +--cpu_prog_rom : entity work.defender_prog +--port map( +-- clk => clock_6, +-- addr => roms_addr(14 downto 0), +-- data => roms_do +--); + +-- cpu/video wram 0 +cpu_video_ram0 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 14) +port map( + clk => clock_6, + we => wram0_we, + addr => wram_addr(13 downto 0), + d => cpu_do, + q => wram0_do +); + +-- cpu/video wram 1 +cpu_video_ram1 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 14) +port map( + clk => clock_6, + we => wram1_we, + addr => wram_addr(13 downto 0), + d => cpu_do, + q => wram1_do +); + +-- cpu/video wram 2 +cpu_video_ram2 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 14) +port map( + clk => clock_6, + we => wram2_we, + addr => wram_addr(13 downto 0), + d => cpu_do, + q => wram2_do +); + +-- palette ram +palette_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 4) +port map( + clk => clock_6, + we => palette_we, + addr => palette_addr, + d => palette_di, + q => palette_do +); + +-- cmos ram +cmos_ram : entity work.defender_cmos_ram +generic map( dWidth => 4, aWidth => 8) +port map( + clk => clock_6, + we => cmos_we, + addr => cpu_addr(7 downto 0), + d => cpu_do(3 downto 0), + q => cmos_do +); + +-- cpu to video addr decoder +cpu_video_addr_decoder : entity work.defender_decoder_2 +port map( + clk => clock_6, + addr => cpu_to_video_addr, + data => cpu_to_video_do +); + +-- video scan addr decoder +video_scan_addr_decoder : entity work.defender_decoder_3 +port map( + clk => clock_6, + addr => video_scan_addr, + data => video_scan_do +); + +-- pia i/O board +pia_io : entity work.pia6821 +port map +( + clk => pias_clock, -- rising edge + rst => reset, -- active high + cs => pia_io_cs, + rw => pia_io_rw_n, -- write low + addr => cpu_addr(1 downto 0), + data_in => cpu_do, + data_out => pia_io_do, + irqa => open, -- active high + irqb => open, -- active high + pa_i => pia_io_pa_i, + pa_o => open, + pa_oe => open, + ca1 => '0', + ca2_i => '0', + ca2_o => open, + ca2_oe => open, + pb_i => pia_io_pb_i, + pb_o => open, + pb_oe => open, + cb1 => '0', + cb2_i => '0', + cb2_o => pia_io_cb2_o, + cb2_oe => open +); + +-- pia rom board +pia_rom : entity work.pia6821 +port map +( + clk => pias_clock, + rst => reset, + cs => pia_rom_cs, + rw => pia_rom_rw_n, + addr => cpu_addr(1 downto 0), + data_in => cpu_do, + data_out => pia_rom_do, + irqa => pia_rom_irqa, + irqb => pia_rom_irqb, + pa_i => pia_rom_pa_i, + pa_o => open, + pa_oe => open, + ca1 => vcnt_240, + ca2_i => '0', + ca2_o => open, + ca2_oe => open, + pb_i => (others => '0'), + pb_o => pia_rom_pb_o, + pb_oe => open, + cb1 => cnt_4ms, + cb2_i => '0', + cb2_o => open, + cb2_oe => open +); + +-- video syncs and blanks +video_csync <= csync; + +process(clock_6n) + constant hcnt_base : integer := 54; + variable vsync_cnt : std_logic_vector(3 downto 0); +begin + +if rising_edge(clock_6n) then + + if hcnt = hcnt_base+0 then hsync0 <= '0'; + elsif hcnt = hcnt_base+6 then hsync0 <= '1'; + end if; + + if hcnt = hcnt_base+0 then hsync1 <= '0'; + elsif hcnt = hcnt_base+3 then hsync1 <= '1'; + elsif hcnt = hcnt_base+32-64 then hsync1 <= '0'; + elsif hcnt = hcnt_base+35-64 then hsync1 <= '1'; + end if; + + if hcnt = hcnt_base+0 then hsync2 <= '0'; + elsif hcnt = hcnt_base+32-3-64 then hsync2 <= '1'; + elsif hcnt = hcnt_base+32-64 then hsync2 <= '0'; + elsif hcnt = hcnt_base+64-3-128 then hsync2 <= '1'; + end if; + + if hcnt = 63 and pixel_cnt = 5 then + if vcnt = 495 then -- 503 with vcnt max = F4 + vsync_cnt := X"0"; -- 499 with F8, 495 with FC + else + if vsync_cnt < X"F" then vsync_cnt := vsync_cnt + '1'; end if; + end if; + end if; + + if vsync_cnt = 0 then csync <= hsync1; + elsif vsync_cnt = 1 then csync <= hsync1; + elsif vsync_cnt = 2 then csync <= hsync1; + elsif vsync_cnt = 3 then csync <= hsync2; + elsif vsync_cnt = 4 then csync <= hsync2; + elsif vsync_cnt = 5 then csync <= hsync2; + elsif vsync_cnt = 6 then csync <= hsync1; + elsif vsync_cnt = 7 then csync <= hsync1; + elsif vsync_cnt = 8 then csync <= hsync1; + else csync <= hsync0; + end if; + + if hcnt = hcnt_base-2 then hblank <= '1'; + elsif hcnt = hcnt_base+11-64 then hblank <= '0'; + end if; + + if vcnt = 492 then vblank <= '1'; -- 492 ok + elsif vcnt = 262 then vblank <= '0'; -- 262 ok + end if; + + -- external sync and blank outputs + video_blankn <= not (hblank or vblank); + + video_hs <= hsync0; + + if vsync_cnt = 0 then video_vs <= '0'; + elsif vsync_cnt = 8 then video_vs <= '1'; + end if; + +end if; +end process; + +-- sound board +defender_sound_board : entity work.defender_sound_board +port map( + clk_1p79 => clk_1p79, + clk_0p89 => clk_0p89, + reset => reset, + select_sound => select_sound, + audio_out => audio_out, + + dbg_cpu_addr => open --dbg_cpu_addr +); + +end struct; \ No newline at end of file diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_cmos_ram.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_cmos_ram.vhd new file mode 100644 index 00000000..f74b9b02 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_cmos_ram.vhd @@ -0,0 +1,163 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- Modifies Octiber 2017 by Dar +-- Add init data with defender cmos value +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd init with defender cmos value +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity defender_cmos_ram is + generic ( + dWidth : integer := 8; -- must be 4 for defender_cmos_ram + aWidth : integer := 10 -- must be 8 for defender_cmos_ram + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- +-- defender cmos data +-- (ram is 128x4 => only 4 bits/address, that is only 1 hex digit/address) +-- +-- @ values - (fonction) meaning + +-- 0 0 - ? +-- 1 0005 - (01) coins left +-- 5 0000 - (02) coins center +-- 9 0000 - (03) coins right +-- 13 0005 - (04) total paid +-- 17 0000 - (05) ships won +---21 0000 - (06) total time +-- 25 0003 - (07) total ships + +-- -- 8 entries of 6 digits highscore + 3 ascii letters + +-- 29 021270 44 52 4A +-- 41 018315 53 41 4D +-- 53 015920 4C 45 44 +-- 65 014285 50 47 44 +-- 77 012520 43 52 42 +-- 89 011035 4D 52 53 +-- 101 008265 53 53 52 +-- 113 006010 54 4D 48 + +-- 125 00 - credits +-- 127 5 - ? + +-- -- protected data writeable only with coin door opened + +-- 128 A - ? +-- 129 0100 - (08) bonus ship level +-- 133 03 - (09) nb ships +-- 135 03 - (10) coinage select +-- 137 01 - (11) left coin mult +-- 139 04 - (12) center coin mult +-- 141 01 - (13) right coin mult +-- 143 01 - (14) coins for credit +-- 145 00 - (15) coins for bonus +-- 147 00 - (16) minimum coins +-- 149 00 - (17) free play +-- 151 05 - (18) game adjust 1 Stating difficulty 0=lib; 1=mod; 2=cons +-- 153 15 - (19) game adjust 2 Progessive wave diff. limit > 4-25 +-- 155 01 - (20) game adjust 3 Background sound 0=off; 1=on +-- 157 05 - (21) game adjust 4 Planet restore wave number +-- 159 00 - (22) game adjust 5 +-- 161 00 - (23) game adjust 6 +-- 163 00 - (24) game adjust 7 +-- 165 00 - (25) game adjust 8 +-- 167 00 - (26) game adjust 9 +-- 169 00 - (27) game adjust 10 + +-- 171 00000 - ? +-- 176 0000000000000000 - ? +-- 192 0000000000000000 - ? +-- 208 0000000000000000 - ? +-- 224 0000000000000000 - ? +-- 240 0000000000000000 - ? + + +architecture rtl of defender_cmos_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + + signal ram: ramDef := ( + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"2",X"1", + X"2",X"7",X"0",X"4",X"4",X"5",X"2",X"4",X"A",X"0",X"1",X"8",X"3",X"1",X"5",X"5", + X"3",X"4",X"1",X"4",X"D",X"0",X"1",X"5",X"9",X"2",X"0",X"4",X"C",X"4",X"5",X"4", + X"4",X"0",X"1",X"4",X"2",X"8",X"5",X"5",X"0",X"4",X"7",X"4",X"4",X"0",X"1",X"2", + X"5",X"2",X"0",X"4",X"3",X"5",X"2",X"4",X"2",X"0",X"1",X"1",X"0",X"3",X"5",X"4", + X"D",X"5",X"2",X"5",X"3",X"0",X"0",X"8",X"2",X"6",X"5",X"5",X"3",X"5",X"3",X"5", + X"2",X"0",X"0",X"6",X"0",X"1",X"0",X"5",X"4",X"4",X"D",X"4",X"8",X"0",X"0",X"5", + X"A",X"0",X"1",X"0",X"0",X"0",X"3",X"0",X"3",X"0",X"1",X"0",X"4",X"0",X"1",X"0", + X"1",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"5",X"1",X"5",X"0",X"1",X"0",X"5",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0"); + + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_decoder_2.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_decoder_2.vhd new file mode 100644 index 00000000..db3514d9 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_decoder_2.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity defender_decoder_2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(8 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of defender_decoder_2 is + type rom is array(0 to 511) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"40",X"80",X"01",X"41",X"81",X"02",X"42",X"82",X"03",X"43",X"83",X"04",X"44",X"84",X"05", + X"45",X"85",X"06",X"46",X"86",X"07",X"47",X"87",X"08",X"48",X"88",X"09",X"49",X"89",X"0A",X"4A", + X"8A",X"0B",X"4B",X"8B",X"0C",X"4C",X"8C",X"0D",X"4D",X"8D",X"0E",X"4E",X"8E",X"0F",X"4F",X"8F", + X"10",X"50",X"90",X"11",X"51",X"91",X"12",X"52",X"92",X"13",X"53",X"93",X"14",X"54",X"94",X"15", + X"55",X"95",X"16",X"56",X"96",X"17",X"57",X"97",X"18",X"58",X"98",X"19",X"59",X"99",X"1A",X"5A", + X"9A",X"1B",X"5B",X"9B",X"1C",X"5C",X"9C",X"1D",X"5D",X"9D",X"1E",X"5E",X"9E",X"1F",X"5F",X"9F", + X"20",X"60",X"A0",X"21",X"61",X"A1",X"22",X"62",X"A2",X"23",X"63",X"A3",X"24",X"64",X"A4",X"25", + X"65",X"A5",X"26",X"66",X"A6",X"27",X"67",X"A7",X"28",X"68",X"A8",X"29",X"69",X"A9",X"2A",X"6A", + X"AA",X"2B",X"6B",X"AB",X"2C",X"6C",X"AC",X"2D",X"6D",X"AD",X"2E",X"6E",X"AE",X"2F",X"6F",X"AF", + X"30",X"70",X"B0",X"31",X"71",X"B1",X"32",X"72",X"B2",X"33",X"73",X"B3",X"34",X"74",X"B4",X"35", + X"75",X"B5",X"36",X"76",X"B6",X"37",X"77",X"B7",X"38",X"78",X"B8",X"39",X"79",X"B9",X"3A",X"7A", + X"BA",X"3B",X"7B",X"BB",X"3C",X"7C",X"BC",X"3D",X"7D",X"BD",X"3E",X"7E",X"BE",X"3F",X"7F",X"BF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"40",X"80",X"01",X"41",X"72",X"32",X"B1",X"71",X"31",X"B0",X"70",X"30",X"AF",X"6F",X"2F", + X"AE",X"6E",X"2E",X"AD",X"6D",X"2D",X"AC",X"6C",X"2C",X"AB",X"6B",X"2B",X"AA",X"6A",X"2A",X"A9", + X"69",X"29",X"A8",X"68",X"28",X"A7",X"67",X"27",X"A6",X"66",X"26",X"A5",X"65",X"25",X"A4",X"64", + X"24",X"A3",X"63",X"23",X"A2",X"62",X"22",X"A1",X"61",X"21",X"A0",X"60",X"20",X"9F",X"5F",X"1F", + X"9E",X"5E",X"1E",X"9D",X"5D",X"1D",X"9C",X"5C",X"1C",X"9B",X"5B",X"1B",X"9A",X"5A",X"1A",X"99", + X"59",X"19",X"98",X"58",X"18",X"97",X"57",X"17",X"96",X"56",X"16",X"95",X"55",X"15",X"94",X"54", + X"14",X"93",X"53",X"13",X"92",X"52",X"12",X"91",X"51",X"11",X"90",X"50",X"10",X"8F",X"4F",X"0F", + X"8E",X"4E",X"0E",X"8D",X"4D",X"0D",X"8C",X"4C",X"0C",X"8B",X"4B",X"0B",X"8A",X"4A",X"0A",X"89", + X"49",X"09",X"88",X"48",X"08",X"87",X"47",X"07",X"86",X"46",X"06",X"85",X"45",X"05",X"84",X"44", + X"04",X"83",X"43",X"03",X"82",X"42",X"02",X"81",X"B2",X"33",X"73",X"B3",X"34",X"74",X"B4",X"35", + X"75",X"B5",X"36",X"76",X"B6",X"37",X"77",X"B7",X"38",X"78",X"B8",X"39",X"79",X"B9",X"3A",X"7A", + X"BA",X"3B",X"7B",X"BB",X"3C",X"7C",X"BC",X"3D",X"7D",X"BD",X"3E",X"7E",X"BE",X"3F",X"7F",X"BF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_decoder_3.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_decoder_3.vhd new file mode 100644 index 00000000..d5751938 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_decoder_3.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity defender_decoder_3 is +port ( + clk : in std_logic; + addr : in std_logic_vector(8 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of defender_decoder_3 is + type rom is array(0 to 511) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"10",X"11",X"12",X"13",X"14",X"15",X"16",X"17",X"18",X"19",X"1A",X"1B",X"1C",X"1D",X"1E",X"1F", + X"20",X"21",X"22",X"23",X"24",X"25",X"26",X"27",X"28",X"29",X"2A",X"2B",X"2C",X"2D",X"2E",X"2F", + X"30",X"31",X"32",X"33",X"34",X"35",X"36",X"37",X"38",X"39",X"3A",X"3B",X"3C",X"3D",X"3E",X"3F", + X"40",X"41",X"42",X"43",X"44",X"45",X"46",X"47",X"48",X"49",X"4A",X"4B",X"4C",X"4D",X"4E",X"4F", + X"50",X"51",X"52",X"53",X"54",X"55",X"56",X"57",X"58",X"59",X"5A",X"5B",X"5C",X"5D",X"5E",X"5F", + X"60",X"61",X"62",X"63",X"64",X"65",X"66",X"67",X"68",X"69",X"6A",X"6B",X"6C",X"6D",X"6E",X"6F", + X"70",X"71",X"72",X"73",X"74",X"75",X"76",X"77",X"78",X"79",X"7A",X"7B",X"7C",X"7D",X"7E",X"7F", + X"80",X"81",X"82",X"83",X"84",X"85",X"86",X"87",X"88",X"89",X"8A",X"8B",X"8C",X"8D",X"8E",X"8F", + X"90",X"91",X"92",X"93",X"94",X"95",X"96",X"97",X"98",X"99",X"9A",X"9B",X"9C",X"9D",X"9E",X"9F", + X"A0",X"A1",X"A2",X"A3",X"A4",X"A5",X"A6",X"A7",X"A8",X"A9",X"AA",X"AB",X"AC",X"AD",X"AE",X"AF", + X"B0",X"B1",X"B2",X"B3",X"B4",X"B5",X"B6",X"B7",X"B8",X"B9",X"BA",X"BB",X"BC",X"BD",X"BE",X"BF", + X"C0",X"C1",X"C2",X"C3",X"C4",X"C5",X"C6",X"C7",X"C8",X"C9",X"CA",X"CB",X"CC",X"CD",X"CE",X"CF", + X"D0",X"D1",X"D2",X"D3",X"D4",X"D5",X"D6",X"D7",X"D8",X"D9",X"DA",X"DB",X"DC",X"DD",X"DE",X"DF", + X"E0",X"E1",X"E2",X"E3",X"E4",X"E5",X"E6",X"E7",X"E8",X"E9",X"EA",X"EB",X"EC",X"ED",X"EE",X"EF", + X"F0",X"F1",X"F2",X"F3",X"F4",X"F5",X"F6",X"F7",X"F8",X"F9",X"FA",X"FB",X"FC",X"FD",X"FE",X"FF", + X"FB",X"FA",X"F9",X"F8",X"F7",X"F6",X"F5",X"F4",X"F3",X"F2",X"F1",X"F0",X"EF",X"EE",X"ED",X"EC", + X"EB",X"EA",X"E9",X"E8",X"E7",X"E6",X"E5",X"E4",X"E3",X"E2",X"E1",X"E0",X"DF",X"DE",X"DD",X"DC", + X"DB",X"DA",X"D9",X"D8",X"D7",X"D6",X"D5",X"D4",X"D3",X"D2",X"D1",X"D0",X"CF",X"CE",X"CD",X"CC", + X"CB",X"CA",X"C9",X"C8",X"C7",X"C6",X"C5",X"C4",X"C3",X"C2",X"C1",X"C0",X"BF",X"BE",X"BD",X"BC", + X"BB",X"BA",X"B9",X"B8",X"B7",X"B6",X"B5",X"B4",X"B3",X"B2",X"B1",X"B0",X"AF",X"AE",X"AD",X"AC", + X"AB",X"AA",X"A9",X"A8",X"A7",X"A6",X"A5",X"A4",X"A3",X"A2",X"A1",X"A0",X"9F",X"9E",X"9D",X"9C", + X"9B",X"9A",X"99",X"98",X"97",X"96",X"95",X"94",X"93",X"92",X"91",X"90",X"8F",X"8E",X"8D",X"8C", + X"8B",X"8A",X"89",X"88",X"87",X"86",X"85",X"84",X"83",X"82",X"81",X"80",X"7F",X"7E",X"7D",X"7C", + X"7B",X"7A",X"79",X"78",X"77",X"76",X"75",X"74",X"73",X"72",X"71",X"70",X"6F",X"6E",X"6D",X"6C", + X"6B",X"6A",X"69",X"68",X"67",X"66",X"65",X"64",X"63",X"62",X"61",X"60",X"5F",X"5E",X"5D",X"5C", + X"5B",X"5A",X"59",X"58",X"57",X"56",X"55",X"54",X"53",X"52",X"51",X"50",X"4F",X"4E",X"4D",X"4C", + X"4B",X"4A",X"49",X"48",X"47",X"46",X"45",X"44",X"43",X"42",X"41",X"40",X"3F",X"3E",X"3D",X"3C", + X"3B",X"3A",X"39",X"38",X"37",X"36",X"35",X"34",X"33",X"32",X"31",X"30",X"2F",X"2E",X"2D",X"2C", + X"2B",X"2A",X"29",X"28",X"27",X"26",X"25",X"24",X"23",X"22",X"21",X"20",X"1F",X"1E",X"1D",X"1C", + X"1B",X"1A",X"19",X"18",X"17",X"16",X"15",X"14",X"13",X"12",X"11",X"10",X"0F",X"0E",X"0D",X"0C", + X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00",X"FC",X"FD",X"FE",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_prog.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_prog.vhd new file mode 100644 index 00000000..9c4b00c3 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_prog.vhd @@ -0,0 +1,1686 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity defender_prog is +port ( + clk : in std_logic; + addr : in std_logic_vector(14 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of defender_prog is + type rom is array(0 to 26623) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"4A",X"DE",X"63",X"A7",X"44",X"AF",X"42",X"7E",X"E8",X"56",X"9E",X"63",X"8D",X"07",X"33",X"84", + X"7E",X"E8",X"56",X"AE",X"06",X"34",X"46",X"CE",X"A0",X"5F",X"AC",X"C4",X"26",X"18",X"EC",X"84", + X"ED",X"C4",X"A6",X"06",X"27",X"06",X"DC",X"69",X"9F",X"69",X"20",X"04",X"DC",X"61",X"9F",X"61", + X"ED",X"84",X"30",X"C4",X"35",X"C6",X"EE",X"C4",X"26",X"E0",X"12",X"7E",X"D7",X"38",X"34",X"62", + X"DE",X"69",X"26",X"01",X"BD",X"D0",X"3A",X"10",X"AE",X"C4",X"10",X"9F",X"69",X"86",X"01",X"A7", + X"46",X"A6",X"E4",X"20",X"11",X"34",X"62",X"DE",X"61",X"26",X"03",X"BD",X"D0",X"3A",X"10",X"AE", + X"C4",X"10",X"9F",X"61",X"6F",X"46",X"AF",X"42",X"A7",X"45",X"86",X"01",X"A7",X"44",X"AE",X"9F", + X"A0",X"63",X"EF",X"9F",X"A0",X"63",X"AF",X"C4",X"30",X"C4",X"35",X"E2",X"34",X"12",X"8E",X"A0", + X"5F",X"AE",X"84",X"27",X"0E",X"9C",X"63",X"27",X"F8",X"A6",X"05",X"81",X"02",X"27",X"F2",X"8D", + X"84",X"20",X"EE",X"35",X"92",X"8D",X"16",X"34",X"66",X"EF",X"06",X"EE",X"66",X"37",X"26",X"ED", + X"02",X"10",X"AF",X"08",X"37",X"06",X"ED",X"88",X"12",X"EF",X"66",X"35",X"E6",X"34",X"46",X"9E", + X"67",X"26",X"03",X"BD",X"D0",X"3A",X"EC",X"84",X"DD",X"67",X"DC",X"65",X"ED",X"84",X"4F",X"5F", + X"ED",X"04",X"A7",X"88",X"14",X"35",X"C6",X"34",X"70",X"CE",X"A0",X"65",X"AC",X"C4",X"26",X"10", + X"10",X"AE",X"D4",X"10",X"AF",X"C4",X"10",X"9E",X"67",X"9F",X"67",X"10",X"AF",X"84",X"35",X"F0", + X"EE",X"C4",X"26",X"E8",X"CE",X"A0",X"6B",X"AC",X"C4",X"27",X"E5",X"EE",X"C4",X"26",X"F8",X"BD", + X"D0",X"3A",X"34",X"70",X"CE",X"A0",X"6D",X"20",X"EE",X"34",X"18",X"10",X"DF",X"77",X"24",X"02", + X"31",X"22",X"10",X"EE",X"22",X"CB",X"08",X"1F",X"03",X"20",X"4E",X"34",X"18",X"CB",X"08",X"1F", + X"03",X"CC",X"00",X"00",X"8E",X"00",X"00",X"31",X"84",X"1F",X"8B",X"1C",X"00",X"20",X"6A",X"34", + X"18",X"CB",X"08",X"1F",X"03",X"CC",X"00",X"00",X"8E",X"00",X"00",X"31",X"84",X"1F",X"8B",X"1C", + X"00",X"36",X"3F",X"33",X"C9",X"01",X"08",X"20",X"44",X"34",X"18",X"10",X"DF",X"77",X"24",X"02", + X"31",X"22",X"10",X"EE",X"22",X"CB",X"08",X"1F",X"03",X"35",X"3F",X"36",X"3F",X"33",X"C9",X"01", + X"08",X"35",X"3F",X"36",X"3F",X"33",X"C9",X"01",X"08",X"35",X"3F",X"36",X"3F",X"33",X"C9",X"01", + X"08",X"35",X"3F",X"36",X"3F",X"10",X"FE",X"A0",X"77",X"35",X"98",X"34",X"18",X"CB",X"08",X"1F", + X"03",X"CC",X"00",X"00",X"8E",X"00",X"00",X"31",X"84",X"1F",X"8B",X"1C",X"00",X"36",X"3F",X"33", + X"C9",X"01",X"08",X"36",X"3F",X"33",X"C9",X"01",X"08",X"36",X"3F",X"33",X"C9",X"01",X"08",X"36", + X"3F",X"35",X"98",X"34",X"18",X"10",X"DF",X"77",X"24",X"02",X"31",X"22",X"10",X"EE",X"22",X"CB", + X"08",X"1F",X"03",X"35",X"3F",X"36",X"3F",X"33",X"C9",X"01",X"08",X"20",X"9C",X"24",X"02",X"31", + X"22",X"10",X"AE",X"22",X"1F",X"03",X"EC",X"A4",X"ED",X"C4",X"EC",X"22",X"ED",X"42",X"EC",X"24", + X"ED",X"C9",X"01",X"00",X"EC",X"26",X"ED",X"C9",X"01",X"02",X"EC",X"28",X"ED",X"C9",X"02",X"00", + X"EC",X"2A",X"ED",X"C9",X"02",X"02",X"39",X"1F",X"03",X"CC",X"00",X"00",X"ED",X"C4",X"ED",X"42", + X"ED",X"C9",X"01",X"00",X"ED",X"C9",X"01",X"02",X"ED",X"C9",X"02",X"00",X"ED",X"C9",X"02",X"02", + X"39",X"24",X"02",X"31",X"22",X"10",X"AE",X"22",X"1F",X"03",X"EC",X"A4",X"ED",X"C4",X"EC",X"22", + X"A7",X"42",X"E7",X"C9",X"01",X"00",X"EC",X"24",X"ED",X"C9",X"01",X"01",X"39",X"1F",X"03",X"CC", + X"00",X"00",X"ED",X"C4",X"A7",X"42",X"ED",X"C9",X"01",X"00",X"A7",X"C9",X"01",X"02",X"39",X"34", + X"56",X"10",X"DF",X"77",X"24",X"02",X"31",X"22",X"10",X"EE",X"22",X"CB",X"04",X"1F",X"03",X"35", + X"16",X"36",X"16",X"33",X"C9",X"01",X"04",X"35",X"16",X"36",X"16",X"33",X"C9",X"01",X"04",X"35", + X"16",X"36",X"16",X"33",X"C9",X"01",X"04",X"35",X"16",X"36",X"16",X"33",X"C9",X"01",X"04",X"35", + X"16",X"36",X"16",X"33",X"C9",X"01",X"04",X"35",X"16",X"36",X"16",X"10",X"DE",X"77",X"35",X"D6", + X"34",X"56",X"CB",X"04",X"1F",X"03",X"CC",X"00",X"00",X"8E",X"00",X"00",X"36",X"16",X"33",X"C9", + X"01",X"04",X"36",X"16",X"33",X"C9",X"01",X"04",X"36",X"16",X"33",X"C9",X"01",X"04",X"36",X"16", + X"33",X"C9",X"01",X"04",X"36",X"16",X"33",X"C9",X"01",X"04",X"36",X"16",X"35",X"D6",X"34",X"10", + X"10",X"DF",X"77",X"24",X"02",X"31",X"22",X"10",X"EE",X"22",X"CB",X"06",X"1F",X"03",X"35",X"36", + X"36",X"36",X"33",X"C9",X"01",X"06",X"35",X"36",X"36",X"36",X"33",X"C9",X"01",X"06",X"35",X"36", + X"36",X"36",X"33",X"C9",X"01",X"06",X"35",X"36",X"36",X"36",X"33",X"C9",X"01",X"06",X"35",X"36", + X"36",X"36",X"33",X"C9",X"01",X"06",X"35",X"36",X"36",X"36",X"33",X"C9",X"01",X"06",X"35",X"36", + X"36",X"36",X"33",X"C9",X"01",X"06",X"35",X"36",X"36",X"36",X"10",X"DE",X"77",X"35",X"90",X"34", + X"10",X"CB",X"06",X"1F",X"03",X"CC",X"00",X"00",X"8E",X"00",X"00",X"31",X"84",X"36",X"36",X"33", + X"C9",X"01",X"06",X"36",X"36",X"33",X"C9",X"01",X"06",X"36",X"36",X"33",X"C9",X"01",X"06",X"36", + X"36",X"33",X"C9",X"01",X"06",X"36",X"36",X"33",X"C9",X"01",X"06",X"36",X"36",X"33",X"C9",X"01", + X"06",X"36",X"36",X"33",X"C9",X"01",X"06",X"36",X"36",X"35",X"90",X"34",X"10",X"10",X"DF",X"77", + X"24",X"02",X"31",X"22",X"10",X"EE",X"22",X"CB",X"06",X"1F",X"03",X"20",X"89",X"34",X"10",X"CB", + X"06",X"1F",X"03",X"CC",X"00",X"00",X"8E",X"00",X"00",X"31",X"84",X"20",X"C2",X"34",X"10",X"10", + X"DF",X"77",X"24",X"02",X"31",X"22",X"10",X"EE",X"22",X"CB",X"06",X"1F",X"03",X"7E",X"D2",X"AE", + X"34",X"10",X"CB",X"06",X"1F",X"03",X"CC",X"00",X"00",X"8E",X"00",X"00",X"31",X"84",X"20",X"99", + X"34",X"76",X"1A",X"01",X"09",X"8A",X"44",X"34",X"02",X"86",X"00",X"24",X"08",X"58",X"49",X"58", + X"49",X"58",X"49",X"58",X"49",X"BD",X"D6",X"FE",X"DD",X"73",X"C6",X"03",X"E0",X"E0",X"A6",X"85", + X"9B",X"74",X"19",X"A7",X"85",X"5A",X"2B",X"0E",X"A6",X"85",X"99",X"73",X"19",X"A7",X"85",X"86", + X"00",X"97",X"73",X"5A",X"2A",X"F2",X"DC",X"AB",X"27",X"2B",X"30",X"01",X"31",X"03",X"8D",X"2A", + X"25",X"23",X"A6",X"21",X"9B",X"AC",X"19",X"A7",X"21",X"A6",X"A4",X"99",X"AB",X"19",X"A7",X"A4", + X"6C",X"06",X"6C",X"08",X"BD",X"D6",X"29",X"BD",X"D6",X"80",X"CC",X"D4",X"B0",X"BD",X"D5",X"4D", + X"C6",X"05",X"BD",X"F5",X"1C",X"8D",X"12",X"35",X"76",X"39",X"34",X"06",X"EC",X"84",X"10",X"A3", + X"A4",X"26",X"04",X"A6",X"02",X"A1",X"22",X"35",X"86",X"96",X"8B",X"34",X"02",X"4A",X"26",X"08", + X"8E",X"0F",X"1C",X"CE",X"A1",X"C3",X"20",X"06",X"8E",X"71",X"1C",X"CE",X"A2",X"00",X"0F",X"73", + X"C6",X"06",X"96",X"36",X"34",X"02",X"86",X"02",X"97",X"36",X"B7",X"D0",X"00",X"A6",X"C0",X"10", + X"BE",X"C0",X"00",X"C5",X"01",X"26",X"06",X"33",X"5F",X"44",X"44",X"44",X"44",X"84",X"0F",X"26", + X"0F",X"C1",X"02",X"23",X"0B",X"0D",X"73",X"26",X"07",X"1E",X"10",X"BD",X"F5",X"7B",X"20",X"0B", + X"0C",X"73",X"48",X"48",X"31",X"A6",X"1E",X"10",X"BD",X"F5",X"22",X"1E",X"10",X"30",X"89",X"04", + X"00",X"5A",X"26",X"C9",X"35",X"02",X"97",X"36",X"B7",X"D0",X"00",X"35",X"82",X"96",X"BA",X"2A", + X"2A",X"BD",X"F5",X"07",X"BD",X"C0",X"33",X"7C",X"A1",X"62",X"20",X"1F",X"96",X"BA",X"2A",X"1B", + X"1A",X"90",X"7F",X"D0",X"00",X"86",X"04",X"B7",X"CC",X"03",X"B6",X"CC",X"02",X"BD",X"F5",X"07", + X"96",X"79",X"44",X"25",X"03",X"7E",X"C0",X"27",X"7E",X"C0",X"21",X"7E",X"D0",X"0A",X"8E",X"A0", + X"7F",X"C6",X"12",X"20",X"0C",X"8E",X"A0",X"80",X"C6",X"15",X"20",X"05",X"8E",X"A0",X"81",X"C6", + X"18",X"96",X"7E",X"26",X"E6",X"A6",X"84",X"26",X"E2",X"86",X"16",X"A7",X"84",X"86",X"C0",X"ED", + X"49",X"86",X"0A",X"8E",X"D4",X"99",X"7E",X"D0",X"01",X"96",X"7E",X"26",X"CE",X"CC",X"D4",X"AB", + X"BD",X"D5",X"4D",X"BD",X"F5",X"07",X"AD",X"D8",X"09",X"20",X"C0",X"FF",X"01",X"18",X"19",X"00", + X"FF",X"01",X"20",X"1E",X"00",X"F0",X"02",X"08",X"11",X"01",X"20",X"17",X"00",X"F0",X"01",X"40", + X"0A",X"00",X"F0",X"01",X"10",X"0B",X"00",X"E8",X"01",X"04",X"14",X"02",X"06",X"11",X"02",X"0A", + X"17",X"00",X"E8",X"06",X"04",X"11",X"01",X"10",X"17",X"00",X"E0",X"03",X"0A",X"08",X"00",X"E0", + X"01",X"18",X"1F",X"00",X"E0",X"01",X"18",X"11",X"00",X"D8",X"01",X"10",X"1A",X"00",X"D0",X"01", + X"30",X"15",X"00",X"D0",X"01",X"10",X"05",X"00",X"D0",X"01",X"08",X"17",X"00",X"D0",X"01",X"08", + X"07",X"00",X"D0",X"01",X"0A",X"01",X"00",X"D0",X"01",X"0A",X"06",X"00",X"D0",X"01",X"10",X"0B", + X"00",X"C8",X"0A",X"01",X"0E",X"00",X"C0",X"01",X"08",X"07",X"00",X"C0",X"01",X"30",X"14",X"00", + X"C0",X"01",X"20",X"18",X"00",X"C0",X"01",X"08",X"03",X"00",X"C0",X"01",X"30",X"09",X"00",X"C0", + X"01",X"08",X"03",X"00",X"C0",X"01",X"18",X"0C",X"00",X"34",X"07",X"1A",X"FF",X"7F",X"D0",X"00", + X"86",X"3F",X"B7",X"CC",X"02",X"53",X"C4",X"3F",X"F7",X"CC",X"02",X"35",X"87",X"34",X"17",X"0F", + X"AD",X"1F",X"01",X"A6",X"84",X"91",X"B2",X"25",X"0D",X"97",X"B2",X"30",X"1E",X"1A",X"10",X"9F", + X"B0",X"CC",X"01",X"01",X"DD",X"B3",X"35",X"97",X"96",X"B3",X"27",X"14",X"0A",X"B3",X"26",X"38", + X"9E",X"B0",X"0A",X"B4",X"26",X"2C",X"30",X"03",X"9F",X"B0",X"A6",X"84",X"26",X"22",X"97",X"B2", + X"96",X"7B",X"85",X"02",X"26",X"0A",X"96",X"AD",X"27",X"1E",X"0F",X"AD",X"C6",X"0F",X"20",X"16", + X"96",X"AD",X"26",X"14",X"96",X"BA",X"85",X"98",X"26",X"0E",X"C6",X"16",X"D7",X"AD",X"20",X"06", + X"97",X"B4",X"EC",X"01",X"97",X"B3",X"8D",X"91",X"B6",X"CC",X"01",X"85",X"40",X"27",X"04",X"86", + X"3C",X"97",X"7E",X"96",X"7E",X"27",X"02",X"0A",X"7E",X"96",X"7F",X"27",X"02",X"0A",X"7F",X"96", + X"81",X"27",X"02",X"0A",X"81",X"96",X"80",X"27",X"02",X"0A",X"80",X"96",X"7B",X"9A",X"7C",X"43", + X"D6",X"7B",X"D7",X"7C",X"F6",X"CC",X"04",X"D7",X"7B",X"F6",X"CC",X"06",X"D7",X"7D",X"94",X"7B", + X"27",X"1B",X"CE",X"F8",X"82",X"5F",X"CB",X"04",X"44",X"24",X"FB",X"33",X"C5",X"37",X"16",X"DE", + X"82",X"26",X"05",X"DD",X"82",X"9F",X"84",X"39",X"DD",X"86",X"9F",X"88",X"39",X"96",X"79",X"9A", + X"7A",X"43",X"D6",X"79",X"D7",X"7A",X"F6",X"CC",X"00",X"C4",X"3F",X"D7",X"79",X"95",X"79",X"27", + X"17",X"8E",X"00",X"78",X"30",X"1F",X"26",X"FC",X"F6",X"CC",X"00",X"D4",X"79",X"D7",X"79",X"94", + X"79",X"27",X"05",X"CE",X"F8",X"A2",X"8D",X"BD",X"39",X"34",X"76",X"8E",X"0F",X"14",X"B6",X"A1", + X"C9",X"8D",X"0F",X"96",X"8C",X"4A",X"27",X"08",X"8E",X"71",X"14",X"B6",X"A2",X"06",X"8D",X"02", + X"35",X"F6",X"81",X"05",X"23",X"02",X"86",X"05",X"34",X"02",X"CC",X"20",X"06",X"BD",X"F5",X"C7", + X"A6",X"E4",X"27",X"0F",X"10",X"8E",X"F9",X"D5",X"1F",X"10",X"BD",X"F5",X"22",X"8B",X"06",X"6A", + X"E4",X"26",X"F7",X"35",X"82",X"34",X"76",X"CC",X"40",X"20",X"8E",X"30",X"08",X"BD",X"F5",X"C7", + X"8D",X"4A",X"8D",X"B5",X"8D",X"0A",X"96",X"8C",X"BD",X"D3",X"DB",X"4A",X"26",X"FA",X"35",X"F6", + X"34",X"76",X"8E",X"29",X"1B",X"B6",X"A1",X"CB",X"8D",X"0F",X"96",X"8C",X"4A",X"27",X"08",X"8E", + X"8B",X"1B",X"B6",X"A2",X"08",X"8D",X"02",X"35",X"F6",X"81",X"03",X"23",X"02",X"86",X"03",X"34", + X"02",X"CC",X"03",X"0B",X"BD",X"F5",X"C7",X"A6",X"E4",X"27",X"0F",X"10",X"8E",X"F9",X"D9",X"1F", + X"10",X"BD",X"F5",X"22",X"CB",X"04",X"6A",X"E4",X"26",X"F7",X"35",X"82",X"CC",X"55",X"55",X"8E", + X"00",X"28",X"ED",X"84",X"30",X"89",X"01",X"00",X"8C",X"9C",X"00",X"25",X"F5",X"8E",X"2F",X"08", + X"ED",X"89",X"41",X"00",X"ED",X"81",X"8C",X"2F",X"28",X"26",X"F5",X"8E",X"2F",X"07",X"A7",X"84", + X"30",X"89",X"01",X"00",X"8C",X"71",X"07",X"26",X"F5",X"8E",X"4C",X"07",X"CC",X"99",X"99",X"ED", + X"84",X"ED",X"88",X"21",X"30",X"89",X"01",X"00",X"8C",X"54",X"07",X"26",X"F2",X"39",X"34",X"02", + X"96",X"8B",X"8E",X"A1",X"C2",X"4A",X"27",X"03",X"8E",X"A1",X"FF",X"35",X"82",X"34",X"02",X"20", + X"F1",X"34",X"04",X"D6",X"DF",X"86",X"03",X"3D",X"CB",X"11",X"96",X"E1",X"44",X"44",X"44",X"98", + X"E1",X"44",X"06",X"E0",X"06",X"E1",X"DB",X"E1",X"D9",X"E0",X"D7",X"DF",X"96",X"DF",X"35",X"84", + X"C0",X"FF",X"00",X"00",X"14",X"05",X"34",X"3E",X"1A",X"FF",X"10",X"CE",X"BF",X"FF",X"86",X"A0", + X"1F",X"8B",X"7F",X"D0",X"00",X"C6",X"04",X"CE",X"CC",X"00",X"8E",X"D7",X"30",X"6F",X"41",X"A6", + X"80",X"A7",X"C1",X"A6",X"03",X"A7",X"5F",X"5A",X"26",X"F3",X"BD",X"F5",X"D1",X"8E",X"9C",X"00", + X"6F",X"80",X"C6",X"38",X"F7",X"C3",X"FC",X"8C",X"C0",X"00",X"26",X"F4",X"7F",X"CC",X"00",X"7F", + X"CC",X"02",X"8E",X"C4",X"7D",X"BD",X"F8",X"3A",X"1F",X"98",X"81",X"20",X"22",X"06",X"84",X"0F", + X"81",X"09",X"23",X"01",X"5F",X"D7",X"37",X"CC",X"A5",X"5A",X"DD",X"E0",X"CC",X"FF",X"70",X"DD", + X"A1",X"0F",X"A3",X"C6",X"FF",X"DD",X"79",X"BD",X"D8",X"DC",X"BD",X"F5",X"07",X"BD",X"C0",X"33", + X"8D",X"24",X"8D",X"12",X"BD",X"F8",X"00",X"8E",X"D8",X"25",X"86",X"01",X"BD",X"D0",X"55",X"03", + X"BA",X"1C",X"00",X"7E",X"E7",X"BE",X"8D",X"3D",X"BD",X"E6",X"9F",X"BD",X"E0",X"52",X"8D",X"45", + X"BD",X"E5",X"4B",X"7E",X"E1",X"49",X"34",X"16",X"4F",X"5F",X"8E",X"AA",X"C5",X"9F",X"61",X"30", + X"0F",X"AF",X"11",X"8C",X"AF",X"1B",X"26",X"F7",X"ED",X"84",X"DD",X"5F",X"8E",X"AF",X"2A",X"9F", + X"69",X"30",X"88",X"17",X"AF",X"88",X"E9",X"8C",X"AF",X"86",X"26",X"F5",X"ED",X"84",X"8E",X"A0", + X"5F",X"9F",X"63",X"35",X"96",X"8E",X"F8",X"BE",X"CE",X"A0",X"26",X"C6",X"10",X"A6",X"80",X"A7", + X"C0",X"5A",X"26",X"F9",X"39",X"34",X"17",X"1A",X"FF",X"8E",X"A2",X"3C",X"9F",X"67",X"30",X"88", + X"17",X"AF",X"88",X"E9",X"8C",X"AA",X"AE",X"26",X"F5",X"4F",X"5F",X"ED",X"84",X"DD",X"6B",X"DD", + X"65",X"DD",X"6D",X"35",X"97",X"BD",X"F5",X"0B",X"7E",X"C0",X"00",X"8E",X"C4",X"95",X"BD",X"F8", + X"22",X"4A",X"26",X"04",X"86",X"02",X"97",X"37",X"39",X"96",X"BA",X"2A",X"0E",X"8D",X"EC",X"96", + X"37",X"27",X"08",X"CC",X"D4",X"BD",X"BD",X"D5",X"4D",X"8D",X"16",X"7E",X"D0",X"0A",X"96",X"BA", + X"2A",X"F9",X"8D",X"D7",X"96",X"37",X"81",X"02",X"25",X"F1",X"8D",X"05",X"CC",X"D4",X"C2",X"20", + X"E5",X"0F",X"38",X"12",X"96",X"B7",X"27",X"73",X"96",X"BA",X"2A",X"58",X"BD",X"D0",X"7C",X"BD", + X"F5",X"D1",X"86",X"7F",X"97",X"BA",X"86",X"01",X"97",X"8B",X"97",X"25",X"0F",X"8C",X"8E",X"A1", + X"C2",X"6F",X"80",X"8C",X"A2",X"3C",X"26",X"F9",X"8E",X"C4",X"85",X"BD",X"F8",X"22",X"84",X"0F", + X"B7",X"A1",X"C9",X"C6",X"0A",X"FD",X"A1",X"CB",X"0F",X"39",X"12",X"8E",X"A1",X"C2",X"BD",X"DE", + X"7C",X"8E",X"C4",X"81",X"BD",X"F8",X"38",X"DD",X"AB",X"FD",X"A1",X"C6",X"7F",X"A1",X"C8",X"8E", + X"A1",X"C2",X"A6",X"80",X"A7",X"88",X"3C",X"8C",X"A1",X"FF",X"26",X"F6",X"8E",X"D9",X"19",X"86", + X"00",X"BD",X"D0",X"55",X"0C",X"8C",X"96",X"37",X"8B",X"99",X"19",X"97",X"37",X"8E",X"C4",X"7D", + X"BD",X"F8",X"4E",X"96",X"8C",X"4A",X"27",X"03",X"BD",X"D6",X"65",X"39",X"34",X"12",X"96",X"36", + X"34",X"02",X"8E",X"DF",X"17",X"CC",X"38",X"3C",X"20",X"15",X"34",X"12",X"96",X"36",X"34",X"02", + X"4F",X"BD",X"F5",X"0D",X"B6",X"CC",X"06",X"2A",X"E9",X"8E",X"DF",X"C3",X"CC",X"39",X"34",X"9F", + X"90",X"0F",X"36",X"7F",X"D0",X"00",X"F7",X"CC",X"07",X"B7",X"C3",X"FC",X"86",X"7E",X"97",X"8F", + X"35",X"02",X"97",X"36",X"B7",X"D0",X"00",X"35",X"92",X"C6",X"07",X"BD",X"F5",X"1C",X"BD",X"D7", + X"B6",X"BD",X"D0",X"7C",X"86",X"7F",X"97",X"BA",X"9E",X"63",X"9C",X"5F",X"26",X"04",X"AE",X"84", + X"27",X"10",X"86",X"0F",X"8E",X"D9",X"3A",X"7E",X"D0",X"01",X"96",X"7F",X"9A",X"80",X"9A",X"7F", + X"26",X"F0",X"BD",X"D7",X"C6",X"8E",X"D9",X"50",X"86",X"00",X"BD",X"D0",X"55",X"7E",X"E7",X"BE", + X"4F",X"BD",X"F5",X"0D",X"B6",X"CC",X"06",X"2A",X"15",X"BD",X"F5",X"D1",X"96",X"8B",X"4A",X"26", + X"05",X"BD",X"D8",X"DC",X"20",X"02",X"8D",X"82",X"86",X"FF",X"97",X"7B",X"97",X"7C",X"4F",X"5F", + X"DD",X"20",X"DD",X"22",X"BD",X"F4",X"FF",X"BD",X"C0",X"06",X"BD",X"C0",X"00",X"BD",X"F5",X"F1", + X"CC",X"03",X"00",X"DD",X"BD",X"DD",X"BB",X"0F",X"AD",X"0F",X"B5",X"0F",X"8A",X"0F",X"AF",X"0F", + X"9A",X"0F",X"99",X"8E",X"A1",X"1A",X"9F",X"9B",X"BD",X"D6",X"FE",X"9F",X"8D",X"A6",X"08",X"84", + X"07",X"CE",X"DB",X"53",X"A6",X"C6",X"97",X"2B",X"6A",X"07",X"BD",X"D6",X"65",X"CC",X"20",X"80", + X"DD",X"C1",X"DD",X"BF",X"CC",X"20",X"00",X"DD",X"C3",X"CC",X"08",X"00",X"D3",X"20",X"DD",X"CC", + X"CC",X"80",X"00",X"DD",X"C5",X"4F",X"5F",X"DD",X"C7",X"97",X"C9",X"DD",X"CA",X"8E",X"E9",X"E3", + X"86",X"00",X"BD",X"D0",X"55",X"8E",X"E7",X"82",X"86",X"00",X"BD",X"D0",X"55",X"8E",X"F4",X"93", + X"86",X"00",X"BD",X"D0",X"55",X"8E",X"E9",X"BF",X"86",X"00",X"BD",X"D0",X"55",X"8E",X"F4",X"64", + X"86",X"00",X"BD",X"D0",X"55",X"8E",X"F4",X"3D",X"86",X"00",X"BD",X"D0",X"55",X"96",X"25",X"27", + X"1E",X"D6",X"8C",X"5A",X"27",X"19",X"CE",X"C0",X"EF",X"96",X"8B",X"4A",X"27",X"03",X"CE",X"C0", + X"F1",X"8E",X"3C",X"80",X"BD",X"F5",X"13",X"86",X"80",X"8E",X"DA",X"1F",X"7E",X"D0",X"01",X"BD", + X"F5",X"F1",X"C6",X"05",X"9E",X"8D",X"A6",X"0A",X"8D",X"15",X"86",X"60",X"8E",X"DA",X"32",X"7E", + X"D0",X"01",X"BD",X"DC",X"1E",X"8D",X"05",X"0F",X"25",X"7E",X"DC",X"D9",X"5F",X"96",X"FA",X"26", + X"02",X"CA",X"02",X"D7",X"BA",X"39",X"C6",X"58",X"8D",X"F3",X"DC",X"20",X"DD",X"22",X"9E",X"BF", + X"CC",X"08",X"06",X"BD",X"F5",X"C7",X"BD",X"DB",X"B6",X"CC",X"D4",X"B5",X"BD",X"D5",X"4D",X"10", + X"8E",X"F9",X"C1",X"96",X"BB",X"2A",X"04",X"10",X"8E",X"F9",X"CB",X"8E",X"DB",X"4B",X"AF",X"47", + X"CE",X"AF",X"DD",X"BD",X"DB",X"5C",X"1F",X"31",X"DE",X"63",X"AF",X"4B",X"DC",X"C1",X"10",X"AE", + X"4B",X"BD",X"F5",X"7B",X"86",X"02",X"8E",X"DA",X"8C",X"7E",X"D0",X"01",X"DC",X"C1",X"10",X"AE", + X"4B",X"BD",X"F5",X"22",X"AE",X"47",X"A6",X"80",X"27",X"0E",X"97",X"31",X"0F",X"26",X"AF",X"47", + X"86",X"02",X"8E",X"DA",X"7C",X"7E",X"D0",X"01",X"86",X"7F",X"97",X"BA",X"86",X"FF",X"97",X"26", + X"86",X"02",X"8E",X"DA",X"B8",X"7E",X"D0",X"01",X"0F",X"26",X"BD",X"D0",X"7C",X"9E",X"C1",X"30", + X"89",X"04",X"03",X"BD",X"F4",X"FF",X"BD",X"C0",X"0E",X"BD",X"D3",X"D9",X"0F",X"B3",X"C6",X"13", + X"BD",X"D5",X"39",X"BD",X"DD",X"AE",X"26",X"06",X"BD",X"DD",X"EC",X"BD",X"F5",X"F1",X"96",X"8B", + X"9E",X"8D",X"E6",X"07",X"26",X"2F",X"D6",X"8C",X"5A",X"27",X"41",X"88",X"03",X"BD",X"D7",X"0D", + X"E6",X"07",X"27",X"38",X"CE",X"C0",X"EF",X"81",X"02",X"27",X"03",X"CE",X"C0",X"F1",X"8E",X"3C", + X"78",X"BD",X"F5",X"13",X"CE",X"C0",X"75",X"8E",X"3E",X"88",X"BD",X"F5",X"13",X"86",X"60",X"8E", + X"DB",X"15",X"7E",X"D0",X"01",X"96",X"8B",X"4C",X"91",X"8C",X"23",X"02",X"86",X"01",X"BD",X"D7", + X"0D",X"E6",X"07",X"27",X"F2",X"97",X"8B",X"0C",X"25",X"7E",X"D9",X"19",X"CE",X"C0",X"75",X"8E", + X"3E",X"80",X"86",X"FF",X"97",X"BA",X"BD",X"F5",X"13",X"0F",X"B3",X"C6",X"13",X"BD",X"D5",X"39", + X"86",X"28",X"8E",X"DB",X"48",X"7E",X"D0",X"01",X"7E",X"D8",X"25",X"07",X"07",X"07",X"0F",X"3F", + X"7F",X"FF",X"FF",X"00",X"81",X"28",X"07",X"16",X"2F",X"84",X"15",X"00",X"34",X"56",X"BD",X"F5", + X"03",X"EC",X"A4",X"ED",X"C4",X"3D",X"30",X"4A",X"AF",X"42",X"30",X"8B",X"AF",X"44",X"34",X"10", + X"30",X"8B",X"34",X"10",X"EC",X"26",X"ED",X"46",X"EC",X"28",X"ED",X"48",X"AE",X"22",X"33",X"4A", + X"8D",X"0E",X"AE",X"24",X"EE",X"62",X"EC",X"E4",X"ED",X"62",X"8D",X"04",X"32",X"64",X"35",X"D6", + X"EC",X"81",X"85",X"F0",X"27",X"02",X"8A",X"F0",X"85",X"0F",X"27",X"02",X"8A",X"0F",X"C5",X"F0", + X"27",X"02",X"CA",X"F0",X"C5",X"0F",X"27",X"02",X"CA",X"0F",X"84",X"BB",X"C4",X"BB",X"ED",X"C1", + X"11",X"A3",X"64",X"25",X"DB",X"39",X"34",X"56",X"DE",X"8D",X"33",X"4A",X"86",X"33",X"6F",X"C0", + X"4A",X"26",X"FB",X"DE",X"8D",X"96",X"FA",X"A7",X"4A",X"33",X"4B",X"8E",X"A0",X"FB",X"A6",X"80", + X"8C",X"A1",X"00",X"22",X"03",X"AB",X"88",X"16",X"A7",X"C0",X"8C",X"A1",X"12",X"26",X"EF",X"35", + X"D6",X"34",X"06",X"97",X"74",X"BD",X"D0",X"95",X"F9",X"01",X"ED",X"70",X"66",X"66",X"BD",X"D7", + X"11",X"DC",X"E0",X"84",X"1F",X"AB",X"61",X"ED",X"0A",X"54",X"24",X"05",X"CC",X"F9",X"15",X"ED", + X"02",X"86",X"E0",X"A7",X"0C",X"86",X"10",X"A7",X"88",X"14",X"4F",X"5F",X"ED",X"88",X"10",X"ED", + X"0E",X"ED",X"06",X"9F",X"65",X"AF",X"A1",X"0A",X"74",X"26",X"CA",X"35",X"86",X"0C",X"8E",X"EC", + X"C9",X"86",X"00",X"BD",X"D0",X"55",X"CE",X"A1",X"1A",X"31",X"C4",X"EF",X"07",X"6F",X"C0",X"11", + X"83",X"A1",X"42",X"26",X"F8",X"DE",X"8D",X"A6",X"4A",X"97",X"FA",X"27",X"20",X"81",X"07",X"23", + X"10",X"44",X"44",X"5F",X"8D",X"9B",X"CB",X"40",X"26",X"FA",X"48",X"48",X"40",X"AB",X"4A",X"27", + X"0C",X"97",X"73",X"D6",X"E0",X"86",X"01",X"8D",X"88",X"0A",X"73",X"26",X"F6",X"DE",X"8D",X"33", + X"4B",X"8E",X"A0",X"FB",X"A6",X"C0",X"A7",X"80",X"8C",X"A1",X"12",X"26",X"F7",X"8E",X"A1",X"12", + X"6F",X"80",X"8C",X"A1",X"1A",X"26",X"F9",X"BD",X"D0",X"AD",X"96",X"DF",X"44",X"8B",X"2A",X"A7", + X"0C",X"BD",X"D7",X"11",X"84",X"3F",X"8B",X"80",X"D3",X"20",X"ED",X"0A",X"96",X"FF",X"27",X"19", + X"81",X"06",X"23",X"02",X"86",X"06",X"31",X"84",X"BD",X"EB",X"9E",X"9E",X"67",X"AF",X"A4",X"10", + X"9F",X"67",X"40",X"9B",X"FF",X"97",X"FF",X"26",X"CE",X"96",X"FE",X"27",X"05",X"BD",X"EF",X"15", + X"0F",X"FE",X"96",X"FD",X"B7",X"A1",X"14",X"27",X"05",X"0F",X"FD",X"BD",X"EB",X"36",X"96",X"FC", + X"B7",X"A1",X"13",X"27",X"13",X"81",X"03",X"23",X"02",X"86",X"03",X"34",X"02",X"BD",X"F2",X"9D", + X"96",X"FC",X"A0",X"E0",X"97",X"FC",X"26",X"ED",X"39",X"DE",X"63",X"86",X"28",X"A7",X"47",X"B6", + X"A1",X"0F",X"B7",X"A1",X"18",X"86",X"01",X"B7",X"A1",X"17",X"96",X"BA",X"85",X"08",X"26",X"7C", + X"BD",X"DD",X"AE",X"26",X"14",X"86",X"77",X"97",X"BA",X"BD",X"D0",X"7C",X"BD",X"DB",X"B6",X"BD", + X"DD",X"EC",X"9E",X"8D",X"6C",X"07",X"7E",X"D9",X"1E",X"81",X"08",X"22",X"12",X"F6",X"A1",X"0F", + X"54",X"81",X"03",X"22",X"01",X"54",X"5C",X"F1",X"A1",X"18",X"24",X"03",X"F7",X"A1",X"18",X"7A", + X"A1",X"18",X"26",X"1C",X"81",X"04",X"B6",X"A1",X"0F",X"24",X"05",X"44",X"44",X"BD",X"DD",X"9E", + X"B7",X"A1",X"18",X"B6",X"A1",X"19",X"81",X"0C",X"24",X"06",X"BD",X"EA",X"80",X"7C",X"A1",X"19", + X"7A",X"A1",X"17",X"27",X"05",X"B6",X"A1",X"12",X"26",X"22",X"B6",X"A1",X"00",X"B7",X"A1",X"17", + X"96",X"FB",X"27",X"18",X"B6",X"A1",X"12",X"81",X"08",X"24",X"11",X"B6",X"A1",X"01",X"91",X"FB", + X"23",X"02",X"96",X"FB",X"BD",X"EF",X"9C",X"40",X"9B",X"FB",X"97",X"FB",X"96",X"AE",X"81",X"10", + X"24",X"02",X"0C",X"AE",X"96",X"24",X"4C",X"81",X"F0",X"23",X"06",X"C6",X"06",X"BD",X"F5",X"1C", + X"4F",X"97",X"24",X"DE",X"63",X"6A",X"47",X"26",X"0D",X"C6",X"02",X"10",X"8E",X"A0",X"FB",X"BD", + X"DE",X"EC",X"86",X"28",X"A7",X"47",X"86",X"0F",X"8E",X"DC",X"EA",X"7E",X"D0",X"01",X"34",X"02", + X"BD",X"D7",X"11",X"A1",X"E4",X"23",X"03",X"44",X"20",X"F9",X"4C",X"32",X"61",X"39",X"B6",X"A1", + X"12",X"9B",X"FB",X"BB",X"A1",X"13",X"BB",X"A1",X"14",X"BB",X"A1",X"16",X"BB",X"A1",X"15",X"9B", + X"FE",X"39",X"34",X"04",X"5F",X"81",X"10",X"25",X"06",X"CB",X"0A",X"80",X"10",X"20",X"F6",X"34", + X"04",X"AB",X"E0",X"35",X"84",X"34",X"04",X"1F",X"89",X"4F",X"C1",X"0A",X"25",X"07",X"8B",X"10", + X"19",X"C0",X"0A",X"20",X"F5",X"34",X"04",X"AB",X"E0",X"19",X"35",X"84",X"0F",X"26",X"DE",X"63", + X"35",X"10",X"AF",X"4D",X"BD",X"F5",X"F1",X"CE",X"C0",X"F9",X"8E",X"38",X"50",X"BD",X"F5",X"13", + X"9E",X"8D",X"A6",X"08",X"8D",X"CF",X"1F",X"89",X"4F",X"9E",X"50",X"BD",X"C0",X"0E",X"8E",X"3D", + X"60",X"CE",X"C0",X"FB",X"BD",X"F5",X"13",X"CE",X"C0",X"F3",X"8E",X"3C",X"90",X"BD",X"F5",X"13", + X"9E",X"8D",X"5F",X"A6",X"08",X"81",X"05",X"23",X"02",X"86",X"05",X"9E",X"50",X"BD",X"C0",X"0E", + X"DE",X"63",X"8E",X"3C",X"A0",X"96",X"FA",X"A7",X"49",X"27",X"31",X"1F",X"10",X"10",X"8E",X"F9", + X"15",X"BD",X"F5",X"22",X"30",X"89",X"04",X"00",X"86",X"01",X"10",X"9E",X"8D",X"E6",X"28",X"C1", + X"05",X"25",X"02",X"C6",X"05",X"58",X"58",X"58",X"58",X"BD",X"D3",X"60",X"AF",X"47",X"86",X"04", + X"8E",X"DE",X"66",X"7E",X"D0",X"01",X"AE",X"47",X"6A",X"49",X"26",X"CF",X"9E",X"8D",X"BD",X"DE", + X"7C",X"86",X"80",X"8E",X"DE",X"79",X"7E",X"D0",X"01",X"6E",X"D8",X"0D",X"34",X"56",X"6C",X"08", + X"8E",X"C4",X"9D",X"BD",X"F8",X"22",X"97",X"73",X"AE",X"62",X"4D",X"27",X"0C",X"A6",X"08",X"90", + X"73",X"25",X"06",X"26",X"FA",X"86",X"0A",X"A7",X"0A",X"BD",X"F4",X"FF",X"A6",X"08",X"34",X"02", + X"81",X"04",X"23",X"02",X"86",X"04",X"FE",X"C0",X"11",X"8B",X"03",X"30",X"0B",X"E6",X"C6",X"E7", + X"80",X"33",X"48",X"11",X"B3",X"C0",X"13",X"26",X"F4",X"35",X"02",X"80",X"04",X"24",X"01",X"4F", + X"97",X"73",X"8E",X"C4",X"97",X"BD",X"F8",X"38",X"BD",X"DD",X"C2",X"9B",X"73",X"97",X"73",X"27", + X"19",X"1F",X"98",X"BD",X"DD",X"C2",X"91",X"73",X"24",X"02",X"97",X"73",X"96",X"73",X"C6",X"03", + X"BD",X"D6",X"FE",X"31",X"0B",X"8D",X"05",X"4A",X"26",X"F4",X"35",X"D6",X"34",X"32",X"BD",X"F4", + X"FF",X"BE",X"C0",X"11",X"A6",X"85",X"2B",X"0A",X"AB",X"A4",X"25",X"10",X"A1",X"84",X"22",X"0C", + X"20",X"08",X"AB",X"A4",X"24",X"06",X"A1",X"01",X"25",X"02",X"A7",X"A4",X"31",X"21",X"30",X"08", + X"BC",X"C0",X"13",X"26",X"DF",X"35",X"B2",X"7F",X"D0",X"00",X"86",X"A0",X"1F",X"8B",X"86",X"04", + X"B7",X"CC",X"03",X"B6",X"CC",X"02",X"B6",X"C8",X"00",X"81",X"80",X"25",X"30",X"96",X"92",X"26", + X"7B",X"0C",X"92",X"BD",X"D5",X"68",X"BD",X"E2",X"63",X"BD",X"E0",X"7E",X"B6",X"C8",X"00",X"80", + X"08",X"81",X"A8",X"23",X"02",X"86",X"A8",X"97",X"A2",X"86",X"02",X"B7",X"D0",X"00",X"DC",X"A2", + X"BD",X"E3",X"9F",X"DC",X"A2",X"BD",X"E2",X"13",X"BD",X"E4",X"53",X"20",X"4F",X"D6",X"92",X"27", + X"4B",X"0F",X"92",X"0C",X"5D",X"C6",X"38",X"F7",X"C3",X"FC",X"81",X"08",X"22",X"1B",X"CE",X"C0", + X"10",X"DC",X"30",X"9E",X"32",X"10",X"9E",X"34",X"36",X"36",X"DC",X"2A",X"9E",X"2C",X"10",X"9E", + X"2E",X"36",X"36",X"DC",X"26",X"9E",X"28",X"36",X"16",X"BD",X"D5",X"FD",X"86",X"07",X"B7",X"D0", + X"00",X"96",X"BA",X"85",X"02",X"26",X"03",X"BD",X"C0",X"03",X"86",X"02",X"B7",X"D0",X"00",X"DC", + X"A1",X"BD",X"E2",X"13",X"DC",X"A1",X"BD",X"E3",X"9F",X"BD",X"E3",X"76",X"1A",X"FF",X"7F",X"D0", + X"00",X"86",X"05",X"B7",X"CC",X"03",X"96",X"36",X"B7",X"D0",X"00",X"A6",X"E4",X"84",X"6F",X"A7", + X"E4",X"35",X"FF",X"7F",X"D0",X"00",X"86",X"A0",X"1F",X"8B",X"86",X"04",X"B7",X"CC",X"03",X"B6", + X"CC",X"02",X"B6",X"C8",X"00",X"81",X"58",X"25",X"2C",X"D6",X"92",X"26",X"CF",X"0C",X"92",X"43", + X"12",X"97",X"A2",X"BD",X"D5",X"FD",X"86",X"07",X"B7",X"D0",X"00",X"96",X"BA",X"85",X"02",X"26", + X"03",X"BD",X"C0",X"03",X"86",X"02",X"B7",X"D0",X"00",X"DC",X"A1",X"BD",X"E2",X"13",X"DC",X"A1", + X"BD",X"E3",X"9F",X"20",X"A7",X"D6",X"92",X"27",X"A3",X"0F",X"92",X"0C",X"5D",X"C6",X"39",X"F7", + X"C3",X"FC",X"81",X"04",X"22",X"1B",X"CE",X"C0",X"10",X"DC",X"30",X"9E",X"32",X"10",X"9E",X"34", + X"36",X"36",X"DC",X"2A",X"9E",X"2C",X"10",X"9E",X"2E",X"36",X"36",X"DC",X"26",X"9E",X"28",X"36", + X"16",X"BD",X"D5",X"68",X"BD",X"E2",X"63",X"BD",X"E0",X"7E",X"86",X"02",X"B7",X"D0",X"00",X"DC", + X"A2",X"BD",X"E2",X"13",X"DC",X"A2",X"BD",X"E3",X"9F",X"BD",X"E4",X"53",X"BD",X"E3",X"76",X"7E", + X"DF",X"AC",X"8E",X"AF",X"9D",X"C6",X"10",X"D7",X"AE",X"5F",X"BD",X"D7",X"11",X"81",X"9C",X"24", + X"F9",X"A7",X"84",X"BD",X"D7",X"11",X"81",X"A8",X"22",X"F9",X"81",X"2A",X"23",X"F5",X"A7",X"01", + X"E7",X"02",X"CB",X"11",X"C4",X"77",X"30",X"04",X"8C",X"AF",X"DD",X"26",X"DD",X"39",X"96",X"BA", + X"85",X"20",X"26",X"F9",X"8E",X"AF",X"9D",X"DC",X"20",X"C4",X"80",X"DD",X"6F",X"DC",X"22",X"C4", + X"80",X"93",X"6F",X"58",X"49",X"97",X"6F",X"C6",X"F0",X"96",X"21",X"85",X"40",X"26",X"01",X"53", + X"D7",X"71",X"4F",X"A7",X"94",X"A7",X"98",X"04",X"A7",X"98",X"08",X"A7",X"98",X"0C",X"A7",X"98", + X"10",X"A7",X"98",X"14",X"A7",X"98",X"18",X"A7",X"98",X"1C",X"A7",X"98",X"20",X"A7",X"98",X"24", + X"A7",X"98",X"28",X"A7",X"98",X"2C",X"A7",X"98",X"30",X"A7",X"98",X"34",X"A7",X"98",X"38",X"A7", + X"98",X"3C",X"D6",X"AE",X"A6",X"84",X"9B",X"6F",X"81",X"9C",X"25",X"0A",X"81",X"C0",X"23",X"04", + X"86",X"9B",X"20",X"02",X"86",X"00",X"A7",X"84",X"A6",X"02",X"94",X"71",X"A7",X"98",X"00",X"30", + X"04",X"5A",X"26",X"E0",X"D6",X"DF",X"C4",X"3C",X"8E",X"AF",X"9D",X"3A",X"A6",X"02",X"8B",X"11", + X"84",X"77",X"A7",X"02",X"96",X"DF",X"85",X"01",X"26",X"3E",X"81",X"98",X"25",X"24",X"CE",X"A1", + X"02",X"33",X"C8",X"B6",X"EE",X"C4",X"11",X"83",X"62",X"45",X"27",X"14",X"0D",X"BA",X"2B",X"10", + X"81",X"A0",X"25",X"0C",X"81",X"A1",X"24",X"08",X"D6",X"E1",X"1F",X"01",X"D6",X"E0",X"E7",X"84", + X"80",X"84",X"6F",X"98",X"00",X"A7",X"84",X"96",X"BA",X"85",X"02",X"27",X"0B",X"96",X"E1",X"84", + X"3F",X"C6",X"03",X"3D",X"CB",X"2A",X"E7",X"01",X"39",X"8E",X"A1",X"62",X"9F",X"9F",X"BD",X"D7", + X"11",X"A7",X"88",X"20",X"A7",X"80",X"8C",X"A1",X"83",X"26",X"F3",X"39",X"9E",X"9F",X"DE",X"BF", + X"33",X"C9",X"FF",X"01",X"EC",X"84",X"ED",X"C4",X"A6",X"05",X"E6",X"09",X"ED",X"42",X"A6",X"0C", + X"A7",X"44",X"96",X"7B",X"85",X"02",X"27",X"22",X"A6",X"03",X"E6",X"06",X"ED",X"C9",X"FF",X"01", + X"A6",X"0A",X"A7",X"C9",X"FF",X"03",X"A6",X"04",X"E6",X"07",X"ED",X"C9",X"FE",X"01",X"A6",X"0B", + X"A7",X"C9",X"FE",X"03",X"A6",X"08",X"A7",X"C9",X"FD",X"02",X"39",X"DE",X"9F",X"9E",X"BF",X"30", + X"89",X"08",X"01",X"37",X"26",X"ED",X"84",X"10",X"AF",X"02",X"37",X"26",X"A7",X"04",X"96",X"7B", + X"85",X"02",X"27",X"18",X"E7",X"89",X"01",X"01",X"10",X"AF",X"89",X"01",X"02",X"37",X"26",X"10", + X"AF",X"89",X"02",X"01",X"A7",X"89",X"02",X"03",X"E7",X"89",X"03",X"02",X"39",X"DE",X"BF",X"5F", + X"8E",X"00",X"00",X"31",X"84",X"33",X"C9",X"08",X"06",X"36",X"34",X"AF",X"C9",X"01",X"01",X"E7", + X"C9",X"01",X"03",X"AF",X"C9",X"02",X"01",X"E7",X"C9",X"02",X"03",X"E7",X"C9",X"03",X"02",X"39", + X"DE",X"BF",X"5F",X"8E",X"00",X"00",X"31",X"84",X"33",X"C9",X"FF",X"06",X"36",X"34",X"AF",X"C9", + X"FF",X"01",X"E7",X"C9",X"FF",X"03",X"AF",X"C9",X"FE",X"01",X"E7",X"C9",X"FE",X"03",X"E7",X"C9", + X"FD",X"02",X"39",X"97",X"77",X"96",X"BA",X"85",X"10",X"26",X"28",X"96",X"77",X"91",X"C0",X"23", + X"22",X"D1",X"C0",X"22",X"1E",X"96",X"BD",X"2B",X"08",X"BD",X"E2",X"5E",X"BD",X"E1",X"F0",X"20", + X"06",X"BD",X"E2",X"5E",X"BD",X"E1",X"CD",X"DC",X"BB",X"DD",X"BD",X"2B",X"07",X"BD",X"E2",X"4A", + X"BD",X"E1",X"5C",X"39",X"BD",X"E2",X"58",X"7E",X"E1",X"9B",X"10",X"8E",X"F9",X"C1",X"96",X"C4", + X"48",X"DC",X"C1",X"DD",X"BF",X"7E",X"D2",X"8E",X"10",X"8E",X"F9",X"CB",X"20",X"F0",X"DC",X"BF", + X"7E",X"D2",X"DF",X"96",X"BA",X"85",X"40",X"10",X"26",X"01",X"0A",X"0F",X"6F",X"DC",X"C7",X"43", + X"53",X"C3",X"00",X"01",X"2A",X"02",X"03",X"6F",X"58",X"49",X"58",X"49",X"D3",X"C8",X"DD",X"C8", + X"96",X"6F",X"99",X"C7",X"97",X"C7",X"DC",X"C7",X"96",X"7B",X"85",X"02",X"27",X"12",X"0F",X"6F", + X"DC",X"BD",X"2A",X"02",X"03",X"6F",X"D3",X"C8",X"DD",X"C8",X"96",X"6F",X"99",X"C7",X"97",X"C7", + X"DC",X"C7",X"47",X"56",X"47",X"56",X"4F",X"57",X"46",X"97",X"94",X"D7",X"93",X"96",X"BD",X"2B", + X"07",X"86",X"20",X"5D",X"2B",X"07",X"20",X"09",X"86",X"70",X"5D",X"2B",X"04",X"0F",X"94",X"0F", + X"93",X"D6",X"94",X"9B",X"93",X"97",X"93",X"93",X"C3",X"27",X"26",X"25",X"12",X"10",X"83",X"01", + X"00",X"23",X"1E",X"CC",X"00",X"40",X"DD",X"95",X"CC",X"01",X"00",X"D3",X"C3",X"20",X"18",X"10", + X"83",X"FF",X"00",X"2E",X"0C",X"CC",X"FF",X"C0",X"DD",X"95",X"CC",X"FF",X"00",X"D3",X"C3",X"20", + X"06",X"4F",X"5F",X"DD",X"95",X"DC",X"93",X"DD",X"C3",X"97",X"C1",X"DC",X"20",X"DD",X"22",X"DC", + X"C7",X"10",X"83",X"01",X"00",X"2D",X"03",X"CC",X"01",X"00",X"10",X"83",X"FF",X"00",X"2E",X"03", + X"CC",X"FF",X"00",X"DD",X"C7",X"D3",X"20",X"93",X"95",X"DD",X"20",X"DC",X"C3",X"44",X"56",X"44", + X"56",X"C4",X"E0",X"D3",X"20",X"DD",X"CC",X"D6",X"C5",X"96",X"7D",X"44",X"25",X"09",X"96",X"7B", + X"2B",X"20",X"CC",X"00",X"00",X"20",X"36",X"C1",X"2B",X"23",X"3A",X"DC",X"CA",X"2A",X"0E",X"C3", + X"FF",X"F8",X"10",X"83",X"FE",X"00",X"2C",X"25",X"CC",X"FE",X"00",X"20",X"20",X"CC",X"FF",X"00", + X"20",X"1B",X"C1",X"EE",X"24",X"1F",X"DC",X"CA",X"2F",X"0E",X"C3",X"00",X"08",X"10",X"83",X"02", + X"00",X"23",X"0A",X"CC",X"02",X"00",X"20",X"05",X"CC",X"01",X"00",X"20",X"00",X"DD",X"CA",X"D3", + X"C5",X"DD",X"C5",X"97",X"C2",X"39",X"96",X"BA",X"85",X"20",X"26",X"22",X"8E",X"A0",X"65",X"20", + X"19",X"EC",X"0A",X"E3",X"0E",X"ED",X"0A",X"EC",X"0C",X"E3",X"88",X"10",X"81",X"2A",X"24",X"02", + X"86",X"F0",X"81",X"F0",X"23",X"02",X"86",X"2A",X"ED",X"0C",X"AE",X"84",X"26",X"E3",X"39",X"34", + X"06",X"96",X"BA",X"85",X"20",X"26",X"4A",X"8E",X"A0",X"65",X"20",X"41",X"EC",X"04",X"27",X"12", + X"E1",X"E4",X"22",X"39",X"E1",X"61",X"23",X"35",X"10",X"AE",X"02",X"AD",X"B8",X"08",X"4F",X"5F", + X"ED",X"04",X"E6",X"0C",X"E1",X"E4",X"22",X"25",X"E1",X"61",X"23",X"21",X"EC",X"0A",X"93",X"20", + X"10",X"83",X"25",X"80",X"24",X"17",X"10",X"AE",X"02",X"58",X"49",X"58",X"49",X"AB",X"A4",X"81", + X"9C",X"22",X"0A",X"A0",X"A4",X"58",X"E6",X"0C",X"ED",X"04",X"AD",X"B8",X"06",X"AE",X"84",X"26", + X"BB",X"35",X"86",X"34",X"66",X"96",X"99",X"81",X"14",X"24",X"4F",X"EC",X"0A",X"93",X"20",X"10", + X"83",X"25",X"80",X"24",X"45",X"58",X"49",X"58",X"49",X"E6",X"0C",X"C1",X"2A",X"23",X"3B",X"9E", + X"67",X"27",X"37",X"ED",X"04",X"ED",X"0A",X"1E",X"89",X"ED",X"0C",X"EF",X"06",X"4F",X"5F",X"ED", + X"0E",X"ED",X"88",X"10",X"EE",X"66",X"37",X"26",X"ED",X"88",X"12",X"10",X"AF",X"02",X"37",X"06", + X"EF",X"66",X"ED",X"08",X"86",X"14",X"A7",X"88",X"15",X"A7",X"88",X"16",X"EC",X"84",X"DD",X"67", + X"DC",X"6D",X"ED",X"84",X"0C",X"99",X"9F",X"6D",X"35",X"E6",X"EE",X"66",X"33",X"46",X"EF",X"66", + X"4F",X"35",X"E6",X"96",X"BA",X"85",X"20",X"26",X"3E",X"DC",X"20",X"C4",X"E0",X"DD",X"9D",X"DC", + X"22",X"C4",X"E0",X"93",X"9D",X"58",X"49",X"58",X"49",X"DD",X"9D",X"8E",X"A0",X"6D",X"20",X"23", + X"10",X"AE",X"04",X"EC",X"88",X"10",X"E3",X"0C",X"81",X"2A",X"23",X"4A",X"ED",X"0C",X"EC",X"0E", + X"D3",X"9D",X"E3",X"0A",X"81",X"98",X"24",X"3E",X"ED",X"0A",X"E6",X"0C",X"ED",X"04",X"EE",X"04", + X"6E",X"98",X"12",X"AE",X"84",X"26",X"D9",X"39",X"DE",X"A6",X"E6",X"0B",X"2A",X"02",X"33",X"46", + X"CC",X"00",X"00",X"ED",X"A4",X"A7",X"22",X"ED",X"A9",X"01",X"00",X"A7",X"A9",X"01",X"02",X"10", + X"AE",X"04",X"EC",X"C4",X"ED",X"A4",X"EC",X"42",X"A7",X"22",X"E7",X"A9",X"01",X"00",X"EC",X"44", + X"ED",X"A9",X"01",X"01",X"20",X"CD",X"4F",X"5F",X"A7",X"88",X"16",X"ED",X"A4",X"A7",X"22",X"ED", + X"A9",X"01",X"00",X"A7",X"A9",X"01",X"02",X"20",X"BA",X"DE",X"A8",X"E6",X"0B",X"58",X"CC",X"00", + X"00",X"ED",X"A4",X"A7",X"22",X"ED",X"A9",X"01",X"00",X"A7",X"A9",X"01",X"02",X"10",X"AE",X"04", + X"25",X"15",X"EC",X"C4",X"84",X"0F",X"ED",X"A4",X"EC",X"42",X"84",X"0F",X"A7",X"22",X"C4",X"F0", + X"E7",X"A9",X"01",X"01",X"7E",X"E4",X"93",X"EC",X"C4",X"C4",X"0F",X"E7",X"21",X"84",X"F0",X"A7", + X"A9",X"01",X"02",X"EC",X"42",X"84",X"F0",X"ED",X"A9",X"01",X"00",X"7E",X"E4",X"93",X"CC",X"00", + X"25",X"BD",X"D3",X"60",X"0A",X"99",X"BD",X"D0",X"F2",X"BD",X"F3",X"FE",X"EC",X"0A",X"44",X"56", + X"44",X"56",X"D3",X"20",X"ED",X"0A",X"A6",X"0C",X"80",X"02",X"A7",X"0C",X"CC",X"F9",X"51",X"ED", + X"02",X"BD",X"FC",X"63",X"CC",X"D4",X"E4",X"7E",X"D5",X"4D",X"5E",X"8E",X"A1",X"A2",X"9F",X"A8", + X"C6",X"0A",X"BD",X"D7",X"11",X"2B",X"02",X"C6",X"09",X"44",X"25",X"04",X"CB",X"A0",X"20",X"02", + X"CB",X"90",X"E7",X"80",X"8C",X"A1",X"C2",X"26",X"E7",X"39",X"8E",X"A0",X"6D",X"20",X"1B",X"A6", + X"88",X"16",X"27",X"05",X"6A",X"88",X"15",X"26",X"11",X"EE",X"84",X"EF",X"A4",X"DE",X"67",X"EF", + X"84",X"9F",X"67",X"BD",X"F3",X"FE",X"0A",X"99",X"30",X"A4",X"31",X"84",X"AE",X"84",X"26",X"DF", + X"39",X"96",X"B5",X"81",X"04",X"24",X"11",X"0C",X"B5",X"CC",X"D5",X"1B",X"BD",X"D5",X"4D",X"9E", + X"C1",X"96",X"BB",X"2A",X"1C",X"7E",X"E6",X"30",X"7E",X"D0",X"0A",X"34",X"46",X"86",X"02",X"97", + X"36",X"B7",X"D0",X"00",X"35",X"06",X"12",X"12",X"12",X"CE",X"F9",X"6F",X"BD",X"E6",X"BA",X"35", + X"C0",X"30",X"89",X"07",X"04",X"AF",X"47",X"AF",X"49",X"AF",X"4B",X"96",X"BA",X"85",X"40",X"26", + X"50",X"86",X"04",X"AE",X"47",X"C6",X"11",X"8C",X"98",X"00",X"24",X"45",X"E7",X"84",X"30",X"89", + X"01",X"00",X"4A",X"26",X"F7",X"C6",X"99",X"E7",X"84",X"AF",X"47",X"10",X"9E",X"A4",X"10",X"8C", + X"A1",X"5F",X"25",X"04",X"10",X"8E",X"A1",X"42",X"AE",X"49",X"86",X"03",X"E6",X"A0",X"E7",X"84", + X"30",X"89",X"01",X"00",X"4A",X"26",X"F5",X"10",X"9F",X"A4",X"AF",X"49",X"6F",X"D8",X"0B",X"6C", + X"4B",X"EC",X"47",X"80",X"06",X"8D",X"94",X"26",X"08",X"86",X"01",X"8E",X"E5",X"CB",X"7E",X"D0", + X"01",X"AE",X"4B",X"4F",X"A7",X"84",X"30",X"89",X"01",X"00",X"AC",X"47",X"23",X"F6",X"20",X"6A", + X"30",X"04",X"AF",X"47",X"AF",X"49",X"AF",X"4B",X"96",X"BA",X"85",X"40",X"26",X"4F",X"86",X"04", + X"AE",X"47",X"C6",X"11",X"8C",X"05",X"00",X"23",X"44",X"E7",X"84",X"30",X"89",X"FF",X"00",X"4A", + X"26",X"F7",X"C6",X"99",X"E7",X"84",X"AF",X"47",X"10",X"9E",X"A4",X"10",X"8C",X"A1",X"5F",X"25", + X"04",X"10",X"8E",X"A1",X"42",X"AE",X"49",X"86",X"03",X"E6",X"A0",X"E7",X"84",X"30",X"89",X"FF", + X"00",X"4A",X"26",X"F5",X"10",X"9F",X"A4",X"AF",X"49",X"6F",X"D8",X"0B",X"6A",X"4B",X"EC",X"47", + X"BD",X"E5",X"AB",X"26",X"08",X"86",X"01",X"8E",X"E6",X"38",X"7E",X"D0",X"01",X"AE",X"4B",X"4F", + X"A7",X"84",X"30",X"89",X"FF",X"00",X"AC",X"47",X"24",X"F6",X"0A",X"B5",X"7E",X"D0",X"0A",X"8E", + X"A1",X"42",X"9F",X"A4",X"BD",X"D7",X"11",X"5F",X"44",X"24",X"02",X"CB",X"01",X"44",X"24",X"02", + X"CB",X"10",X"E7",X"80",X"8C",X"A1",X"62",X"26",X"EB",X"39",X"8E",X"A0",X"65",X"DD",X"D6",X"E3", + X"C4",X"DD",X"D8",X"20",X"17",X"EC",X"04",X"27",X"13",X"91",X"D8",X"24",X"0F",X"D1",X"D9",X"24", + X"0B",X"E3",X"98",X"02",X"91",X"D6",X"23",X"04",X"D1",X"D7",X"22",X"05",X"AE",X"84",X"26",X"E5", + X"39",X"DF",X"DC",X"10",X"AE",X"02",X"A3",X"A4",X"DD",X"73",X"4F",X"5F",X"DD",X"D0",X"DD",X"D2", + X"DC",X"73",X"D0",X"D7",X"22",X"05",X"50",X"D7",X"D1",X"20",X"02",X"D7",X"D3",X"90",X"D6",X"22", + X"05",X"40",X"97",X"D0",X"20",X"02",X"97",X"D2",X"DC",X"73",X"E3",X"A4",X"D0",X"D9",X"22",X"01", + X"5F",X"90",X"D8",X"22",X"01",X"4F",X"DD",X"DA",X"EC",X"A4",X"93",X"D0",X"93",X"DA",X"DD",X"CE", + X"A6",X"41",X"97",X"D5",X"D6",X"D2",X"3D",X"EE",X"42",X"33",X"CB",X"A6",X"21",X"97",X"D4",X"10", + X"AE",X"22",X"D6",X"D0",X"3D",X"31",X"AB",X"96",X"D1",X"31",X"A6",X"96",X"D3",X"33",X"C6",X"D6", + X"CF",X"5A",X"A6",X"C5",X"27",X"2A",X"A6",X"A5",X"27",X"26",X"31",X"A5",X"1F",X"20",X"EE",X"02", + X"A3",X"42",X"10",X"AE",X"04",X"E0",X"41",X"82",X"00",X"25",X"06",X"31",X"A9",X"01",X"00",X"20", + X"F4",X"EB",X"41",X"89",X"00",X"31",X"A5",X"10",X"9F",X"F8",X"AD",X"98",X"08",X"86",X"01",X"39", + X"5A",X"2A",X"CF",X"DC",X"D4",X"31",X"A6",X"33",X"C5",X"0A",X"CE",X"26",X"C2",X"DE",X"DC",X"7E", + X"E6",X"DC",X"0F",X"B6",X"8E",X"E7",X"99",X"96",X"B6",X"E6",X"86",X"27",X"F5",X"0C",X"B6",X"D7", + X"27",X"86",X"02",X"8E",X"E7",X"84",X"7E",X"D0",X"01",X"38",X"39",X"3A",X"3B",X"3C",X"3D",X"3E", + X"3F",X"37",X"2F",X"27",X"1F",X"17",X"47",X"47",X"87",X"87",X"C7",X"C7",X"C6",X"C5",X"CC",X"CB", + X"CA",X"DA",X"E8",X"F8",X"F9",X"FA",X"FB",X"FD",X"FF",X"BF",X"3F",X"3E",X"3C",X"00",X"8E",X"A0", + X"5F",X"9F",X"63",X"96",X"5D",X"27",X"FC",X"0F",X"5D",X"D6",X"BA",X"C5",X"7D",X"27",X"04",X"0F", + X"5E",X"20",X"47",X"48",X"9B",X"5E",X"80",X"04",X"2A",X"01",X"4F",X"97",X"5E",X"81",X"02",X"25", + X"39",X"C6",X"03",X"D7",X"AE",X"81",X"02",X"23",X"31",X"86",X"02",X"97",X"5E",X"10",X"8E",X"A0", + X"65",X"AE",X"A4",X"27",X"25",X"A6",X"88",X"14",X"27",X"04",X"31",X"84",X"20",X"F3",X"EE",X"84", + X"EF",X"A4",X"DC",X"DF",X"84",X"3F",X"8B",X"60",X"E3",X"0A",X"ED",X"0A",X"BD",X"F3",X"FE",X"CC", + X"00",X"00",X"ED",X"04",X"DE",X"6B",X"9F",X"6B",X"EF",X"84",X"86",X"02",X"97",X"36",X"B7",X"D0", + X"00",X"8D",X"3E",X"BD",X"FC",X"66",X"BD",X"D7",X"11",X"9E",X"82",X"26",X"0C",X"9E",X"86",X"27", + X"17",X"DC",X"88",X"0F",X"86",X"0F",X"87",X"20",X"06",X"DC",X"84",X"0F",X"82",X"0F",X"83",X"D4", + X"BA",X"26",X"E6",X"BD",X"D0",X"55",X"20",X"E1",X"CE",X"A0",X"5F",X"20",X"09",X"6A",X"44",X"26", + X"05",X"DF",X"63",X"6E",X"D8",X"02",X"EE",X"C4",X"26",X"F3",X"10",X"CE",X"BF",X"FF",X"7E",X"E7", + X"BE",X"96",X"BA",X"85",X"10",X"26",X"2D",X"DC",X"BF",X"CE",X"F9",X"C1",X"0D",X"BD",X"2A",X"03", + X"CE",X"F9",X"CB",X"34",X"46",X"0C",X"DE",X"BD",X"E6",X"BA",X"35",X"46",X"26",X"08",X"8E",X"A0", + X"6D",X"BD",X"E6",X"BD",X"27",X"0E",X"8E",X"DA",X"46",X"86",X"00",X"BD",X"D0",X"55",X"96",X"BA", + X"8A",X"08",X"97",X"BA",X"0F",X"DE",X"39",X"96",X"AF",X"26",X"23",X"0C",X"AF",X"DC",X"BD",X"53", + X"43",X"C3",X"00",X"01",X"DD",X"BB",X"86",X"02",X"8E",X"E8",X"AE",X"7E",X"D0",X"01",X"96",X"7B", + X"85",X"40",X"26",X"F2",X"86",X"05",X"8E",X"E8",X"BC",X"7E",X"D0",X"01",X"0F",X"AF",X"7E",X"D0", + X"0A",X"96",X"9A",X"26",X"57",X"9E",X"8D",X"A6",X"09",X"27",X"51",X"0C",X"9A",X"6A",X"09",X"BD", + X"D6",X"80",X"CC",X"D4",X"D2",X"BD",X"D5",X"4D",X"9E",X"65",X"27",X"14",X"EC",X"04",X"27",X"0C", + X"A6",X"88",X"14",X"81",X"02",X"24",X"05",X"AD",X"98",X"08",X"20",X"EC",X"AE",X"84",X"20",X"EA", + X"DE",X"63",X"86",X"04",X"A7",X"47",X"03",X"26",X"86",X"02",X"8E",X"E9",X"00",X"7E",X"D0",X"01", + X"6A",X"47",X"26",X"F2",X"86",X"0A",X"8E",X"E9",X"0C",X"7E",X"D0",X"01",X"96",X"7B",X"85",X"04", + X"26",X"F2",X"86",X"0A",X"8E",X"E9",X"1A",X"7E",X"D0",X"01",X"0F",X"9A",X"7E",X"D0",X"0A",X"96", + X"BA",X"85",X"FD",X"10",X"26",X"00",X"95",X"86",X"77",X"97",X"BA",X"BD",X"F5",X"F1",X"86",X"0F", + X"8E",X"E9",X"36",X"7E",X"D0",X"01",X"9E",X"6D",X"27",X"05",X"BD",X"D0",X"F2",X"20",X"F7",X"0F", + X"99",X"DC",X"DF",X"DD",X"20",X"DD",X"22",X"54",X"24",X"08",X"CC",X"20",X"00",X"8E",X"03",X"00", + X"20",X"06",X"8E",X"FD",X"00",X"CC",X"70",X"00",X"DD",X"C3",X"9F",X"BB",X"D6",X"E0",X"54",X"CB", + X"2A",X"D7",X"C5",X"DD",X"C1",X"4F",X"5F",X"97",X"C9",X"DD",X"C7",X"DD",X"CA",X"BD",X"F4",X"FA", + X"C6",X"50",X"BD",X"DA",X"3D",X"BD",X"D0",X"95",X"F9",X"C1",X"ED",X"BC",X"00",X"00",X"CC",X"00", + X"00",X"ED",X"0E",X"ED",X"88",X"10",X"DC",X"C5",X"ED",X"0C",X"DC",X"C3",X"44",X"56",X"44",X"56", + X"D3",X"20",X"ED",X"0A",X"96",X"BB",X"2A",X"05",X"CE",X"F9",X"CB",X"EF",X"02",X"DE",X"63",X"AF", + X"47",X"BD",X"FC",X"60",X"86",X"28",X"8E",X"E9",X"AC",X"7E",X"D0",X"01",X"AE",X"47",X"BD",X"F3", + X"FB",X"BD",X"DA",X"3C",X"96",X"E1",X"81",X"C0",X"10",X"22",X"F0",X"8A",X"7E",X"D0",X"0A",X"9E", + X"9F",X"30",X"01",X"8C",X"A1",X"82",X"23",X"03",X"8E",X"A1",X"62",X"9F",X"9F",X"9E",X"A8",X"30", + X"01",X"8C",X"A1",X"BA",X"23",X"03",X"8E",X"A1",X"A2",X"9F",X"A8",X"86",X"04",X"8E",X"E9",X"BF", + X"7E",X"D0",X"01",X"BD",X"EA",X"33",X"86",X"02",X"8E",X"E9",X"EE",X"7E",X"D0",X"01",X"BD",X"EA", + X"0A",X"BD",X"E5",X"6A",X"86",X"02",X"8E",X"E9",X"FC",X"7E",X"D0",X"01",X"BD",X"F5",X"0B",X"BD", + X"C0",X"03",X"86",X"04",X"8E",X"E9",X"E3",X"7E",X"D0",X"01",X"DC",X"20",X"83",X"0C",X"80",X"DD", + X"73",X"8E",X"A0",X"65",X"20",X"16",X"EC",X"0A",X"93",X"73",X"10",X"83",X"3E",X"80",X"25",X"0C", + X"EE",X"84",X"EF",X"A4",X"DE",X"6B",X"EF",X"84",X"9F",X"6B",X"30",X"A4",X"31",X"84",X"AE",X"84", + X"26",X"E4",X"39",X"DC",X"20",X"83",X"0C",X"80",X"DD",X"73",X"8E",X"A0",X"6B",X"20",X"39",X"EC", + X"88",X"10",X"58",X"49",X"58",X"49",X"58",X"49",X"E3",X"0C",X"81",X"2A",X"24",X"02",X"86",X"F0", + X"81",X"F0",X"23",X"02",X"86",X"2A",X"ED",X"0C",X"EC",X"0E",X"58",X"49",X"58",X"49",X"58",X"49", + X"E3",X"0A",X"ED",X"0A",X"93",X"73",X"10",X"83",X"3E",X"80",X"24",X"0C",X"EE",X"84",X"EF",X"A4", + X"DE",X"65",X"EF",X"84",X"9F",X"65",X"30",X"A4",X"31",X"84",X"AE",X"84",X"26",X"C1",X"39",X"40", + X"8E",X"EA",X"B4",X"86",X"00",X"BD",X"D0",X"55",X"33",X"84",X"BD",X"D0",X"95",X"F9",X"A3",X"EB", + X"2B",X"33",X"33",X"AF",X"47",X"EF",X"06",X"DC",X"DF",X"84",X"1F",X"D3",X"20",X"ED",X"0A",X"54", + X"CB",X"2A",X"E7",X"0C",X"4F",X"5F",X"ED",X"88",X"10",X"ED",X"0E",X"86",X"08",X"A7",X"49",X"8D", + X"44",X"7E",X"FC",X"60",X"AE",X"47",X"EC",X"02",X"10",X"83",X"F8",X"EC",X"27",X"28",X"6A",X"49", + X"26",X"13",X"B6",X"A1",X"10",X"BD",X"DD",X"9E",X"A7",X"49",X"BD",X"EE",X"BA",X"27",X"06",X"CC", + X"D5",X"2F",X"BD",X"D5",X"4D",X"EE",X"02",X"33",X"4A",X"11",X"83",X"F9",X"B7",X"23",X"05",X"CE", + X"F9",X"A3",X"8D",X"0A",X"EF",X"02",X"86",X"06",X"8E",X"EA",X"B4",X"7E",X"D0",X"01",X"96",X"DF", + X"B1",X"A1",X"11",X"23",X"35",X"CC",X"40",X"01",X"DD",X"73",X"EC",X"0A",X"93",X"CC",X"2B",X"02", + X"00",X"73",X"C3",X"02",X"80",X"10",X"83",X"05",X"00",X"23",X"07",X"D6",X"73",X"1D",X"D3",X"C7", + X"ED",X"0E",X"A6",X"0C",X"90",X"C0",X"2B",X"02",X"00",X"74",X"8B",X"0A",X"81",X"14",X"23",X"0A", + X"5F",X"96",X"74",X"D3",X"CA",X"47",X"56",X"ED",X"88",X"10",X"39",X"7A",X"A1",X"19",X"BD",X"F4", + X"16",X"01",X"20",X"D4",X"FD",X"39",X"97",X"73",X"BD",X"D0",X"95",X"F8",X"F7",X"EB",X"74",X"CC", + X"CC",X"BD",X"D7",X"11",X"DC",X"E0",X"84",X"3F",X"8B",X"10",X"ED",X"0A",X"54",X"CB",X"2A",X"E7", + X"0C",X"D6",X"DF",X"C4",X"3F",X"CB",X"E0",X"1D",X"ED",X"0E",X"D6",X"E1",X"C4",X"7F",X"C0",X"40", + X"1D",X"2B",X"04",X"CA",X"20",X"20",X"02",X"C4",X"DF",X"ED",X"88",X"10",X"BD",X"FC",X"60",X"0A", + X"73",X"26",X"C5",X"39",X"BD",X"F4",X"1D",X"02",X"10",X"D4",X"F3",X"86",X"06",X"BD",X"DD",X"9E", + X"31",X"84",X"BD",X"EB",X"9E",X"7A",X"A1",X"14",X"39",X"BD",X"D7",X"11",X"D6",X"DF",X"1D",X"58", + X"49",X"ED",X"88",X"10",X"D6",X"E1",X"C4",X"3F",X"CB",X"E0",X"1D",X"ED",X"0E",X"39",X"34",X"76", + X"97",X"73",X"B6",X"A1",X"16",X"4C",X"81",X"14",X"22",X"3D",X"B7",X"A1",X"16",X"8E",X"EC",X"17", + X"86",X"00",X"BD",X"D0",X"55",X"33",X"84",X"BD",X"D0",X"95",X"F9",X"7B",X"EB",X"E9",X"24",X"24", + X"EC",X"2A",X"ED",X"0A",X"EC",X"2C",X"ED",X"0C",X"AF",X"47",X"EF",X"06",X"8D",X"BB",X"DC",X"E0", + X"F4",X"A1",X"0E",X"E7",X"49",X"84",X"1F",X"A7",X"44",X"B6",X"A1",X"0D",X"BD",X"DD",X"9E",X"A7", + X"4B",X"9F",X"65",X"0A",X"73",X"26",X"BB",X"35",X"F6",X"7A",X"A1",X"16",X"BD",X"F3",X"FB",X"34", + X"10",X"BD",X"D0",X"13",X"35",X"10",X"EC",X"0A",X"83",X"00",X"40",X"ED",X"0A",X"EC",X"0C",X"80", + X"02",X"A7",X"0C",X"CE",X"F8",X"E2",X"EF",X"02",X"BD",X"FC",X"63",X"CC",X"01",X"15",X"BD",X"D3", + X"60",X"CC",X"D5",X"16",X"7E",X"D5",X"4D",X"AE",X"47",X"F6",X"A1",X"0C",X"10",X"9E",X"CC",X"10", + X"AC",X"0A",X"24",X"01",X"50",X"1D",X"ED",X"0E",X"20",X"54",X"E6",X"49",X"AE",X"47",X"96",X"C0", + X"A1",X"0C",X"22",X"01",X"50",X"1D",X"E3",X"88",X"10",X"10",X"83",X"02",X"00",X"2D",X"03",X"CC", + X"02",X"00",X"10",X"83",X"FE",X"00",X"2E",X"03",X"CC",X"FE",X"00",X"ED",X"88",X"10",X"43",X"53", + X"58",X"49",X"58",X"49",X"1F",X"89",X"1D",X"E3",X"88",X"10",X"ED",X"88",X"10",X"D6",X"DF",X"C4", + X"1F",X"CB",X"F0",X"1D",X"E3",X"88",X"10",X"ED",X"88",X"10",X"DC",X"CC",X"A3",X"0A",X"C3",X"12", + X"C0",X"10",X"83",X"25",X"80",X"22",X"A0",X"6A",X"4B",X"26",X"03",X"BD",X"EC",X"86",X"86",X"03", + X"8E",X"EC",X"2A",X"7E",X"D0",X"01",X"34",X"10",X"DC",X"CC",X"A3",X"0A",X"A8",X"0E",X"2B",X"2F", + X"31",X"84",X"BD",X"E3",X"F3",X"E4",X"D9",X"F9",X"5B",X"E5",X"1E",X"27",X"22",X"EC",X"2E",X"58", + X"49",X"58",X"49",X"58",X"49",X"ED",X"0E",X"CC",X"D5",X"34",X"BD",X"D5",X"4D",X"5F",X"96",X"C0", + X"A0",X"0C",X"47",X"56",X"47",X"56",X"47",X"56",X"47",X"56",X"47",X"56",X"ED",X"88",X"10",X"B6", + X"A1",X"0D",X"BD",X"DD",X"9E",X"A7",X"4B",X"35",X"90",X"AE",X"47",X"30",X"02",X"8C",X"A1",X"3A", + X"25",X"03",X"8E",X"A1",X"1A",X"AF",X"47",X"AE",X"84",X"27",X"76",X"EC",X"04",X"27",X"72",X"EC", + X"08",X"10",X"83",X"ED",X"70",X"26",X"6A",X"EC",X"02",X"10",X"83",X"F9",X"0B",X"22",X"2F",X"96", + X"DF",X"81",X"08",X"23",X"50",X"BD",X"ED",X"59",X"8B",X"04",X"81",X"E8",X"23",X"02",X"86",X"E8", + X"C6",X"01",X"A1",X"0C",X"27",X"07",X"22",X"01",X"50",X"EB",X"0C",X"E7",X"0C",X"EE",X"02",X"33", + X"4A",X"11",X"83",X"F9",X"0B",X"23",X"03",X"CE",X"F9",X"01",X"C6",X"E0",X"20",X"2C",X"96",X"DF", + X"81",X"08",X"23",X"F3",X"8D",X"33",X"8B",X"0F",X"81",X"E8",X"23",X"02",X"86",X"E8",X"C6",X"01", + X"A1",X"0C",X"27",X"07",X"22",X"01",X"50",X"EB",X"0C",X"E7",X"0C",X"EE",X"02",X"33",X"4A",X"11", + X"83",X"F9",X"1F",X"23",X"03",X"CE",X"F9",X"15",X"C6",X"20",X"EF",X"02",X"1D",X"E3",X"0A",X"ED", + X"0A",X"86",X"02",X"8E",X"EC",X"C9",X"7E",X"D0",X"01",X"34",X"14",X"EC",X"0A",X"44",X"56",X"44", + X"56",X"44",X"56",X"44",X"56",X"44",X"56",X"44",X"56",X"8E",X"B3",X"00",X"A6",X"8B",X"35",X"94", + X"96",X"DE",X"27",X"03",X"4F",X"35",X"86",X"8D",X"4B",X"BD",X"F3",X"FB",X"CC",X"F8",X"D8",X"ED", + X"02",X"EC",X"0A",X"83",X"00",X"40",X"ED",X"0A",X"BD",X"FC",X"63",X"CC",X"D4",X"E4",X"7E",X"D5", + X"4D",X"EE",X"06",X"27",X"DB",X"96",X"DE",X"27",X"26",X"EC",X"42",X"10",X"83",X"F2",X"4C",X"27", + X"16",X"CC",X"D4",X"DA",X"BD",X"D5",X"4D",X"34",X"10",X"8E",X"EE",X"73",X"86",X"00",X"BD",X"D0", + X"55",X"31",X"84",X"35",X"10",X"AF",X"27",X"CC",X"F2",X"4C",X"ED",X"42",X"4F",X"35",X"86",X"8D", + X"B6",X"7E",X"D0",X"13",X"31",X"84",X"34",X"52",X"CE",X"A1",X"1A",X"86",X"40",X"10",X"AC",X"C1", + X"27",X"06",X"4A",X"26",X"F8",X"BD",X"D0",X"3A",X"4F",X"5F",X"ED",X"5E",X"0A",X"FA",X"26",X"08", + X"8E",X"ED",X"EA",X"86",X"00",X"BD",X"D0",X"55",X"35",X"D2",X"96",X"BA",X"8A",X"02",X"97",X"BA", + X"6F",X"47",X"BD",X"F4",X"FF",X"BD",X"C0",X"09",X"8E",X"B1",X"25",X"CE",X"00",X"00",X"86",X"40", + X"EF",X"91",X"4A",X"26",X"FB",X"9E",X"67",X"CC",X"F9",X"F1",X"ED",X"02",X"C6",X"02",X"D7",X"73", + X"BD",X"D7",X"11",X"84",X"3F",X"D3",X"20",X"ED",X"0A",X"BD",X"ED",X"59",X"A7",X"0C",X"80",X"0A", + X"BD",X"FC",X"63",X"0A",X"73",X"26",X"E9",X"96",X"DF",X"84",X"1F",X"8E",X"E7",X"99",X"A6",X"86", + X"97",X"26",X"CC",X"D4",X"E4",X"BD",X"D5",X"4D",X"8E",X"EE",X"44",X"86",X"02",X"C6",X"08",X"D7", + X"5E",X"7E",X"D0",X"01",X"0F",X"26",X"A6",X"47",X"44",X"44",X"44",X"4C",X"BD",X"DD",X"9E",X"8E", + X"EE",X"54",X"20",X"E9",X"6C",X"47",X"A6",X"47",X"81",X"10",X"26",X"A9",X"CC",X"D4",X"C7",X"BD", + X"D5",X"4D",X"7E",X"D0",X"0A",X"BD",X"D0",X"95",X"F9",X"DD",X"ED",X"BC",X"00",X"00",X"CC",X"01", + X"25",X"20",X"0C",X"BD",X"D0",X"95",X"F9",X"E7",X"ED",X"BC",X"00",X"00",X"CC",X"01",X"50",X"BD", + X"D3",X"60",X"10",X"AE",X"47",X"DC",X"C7",X"ED",X"0E",X"CC",X"00",X"00",X"ED",X"88",X"10",X"86", + X"11",X"A7",X"88",X"14",X"EC",X"2A",X"ED",X"0A",X"EC",X"2C",X"2B",X"05",X"C3",X"18",X"00",X"20", + X"03",X"83",X"20",X"00",X"ED",X"0C",X"9F",X"65",X"AF",X"47",X"86",X"32",X"8E",X"EE",X"B2",X"7E", + X"D0",X"01",X"AE",X"47",X"BD",X"F3",X"FB",X"7E",X"D0",X"0A",X"34",X"10",X"BD",X"E3",X"F3",X"E4", + X"D9",X"F9",X"5B",X"E5",X"1E",X"27",X"35",X"D6",X"DF",X"C4",X"1F",X"CB",X"F0",X"DB",X"BF",X"E0", + X"04",X"1D",X"58",X"49",X"58",X"49",X"ED",X"0E",X"D6",X"DF",X"C1",X"78",X"23",X"0A",X"DC",X"C7", + X"58",X"49",X"58",X"49",X"E3",X"0E",X"ED",X"0E",X"D6",X"E1",X"C4",X"1F",X"CB",X"F0",X"DB",X"C0", + X"E0",X"05",X"1D",X"58",X"49",X"58",X"49",X"ED",X"88",X"10",X"86",X"01",X"35",X"90",X"6A",X"4D", + X"26",X"12",X"B6",X"A1",X"05",X"BD",X"DD",X"9E",X"A7",X"4D",X"8D",X"AE",X"27",X"06",X"CC",X"D5", + X"25",X"BD",X"D5",X"4D",X"39",X"34",X"02",X"97",X"73",X"8E",X"F1",X"5E",X"86",X"00",X"BD",X"D0", + X"55",X"33",X"84",X"BD",X"D0",X"95",X"F8",X"CE",X"EF",X"6D",X"CC",X"33",X"BD",X"D7",X"11",X"DC", + X"20",X"83",X"25",X"80",X"DD",X"75",X"DC",X"E0",X"93",X"75",X"10",X"83",X"4B",X"00",X"24",X"03", + X"C3",X"80",X"00",X"D3",X"75",X"ED",X"0A",X"96",X"DF",X"44",X"8B",X"2A",X"A7",X"0C",X"4F",X"5F", + X"ED",X"88",X"10",X"ED",X"0E",X"B6",X"A1",X"0B",X"BD",X"DD",X"9E",X"A7",X"47",X"BD",X"FC",X"60", + X"EF",X"06",X"AF",X"47",X"7C",X"A1",X"15",X"0A",X"73",X"26",X"AE",X"35",X"82",X"7A",X"A1",X"15", + X"BD",X"F4",X"16",X"01",X"15",X"D4",X"F8",X"39",X"34",X"10",X"96",X"FA",X"27",X"1C",X"9E",X"9B", + X"30",X"02",X"8C",X"A1",X"5A",X"25",X"03",X"8E",X"A1",X"1A",X"EC",X"84",X"26",X"06",X"9C",X"9B", + X"26",X"EE",X"35",X"90",X"9F",X"9B",X"ED",X"49",X"AF",X"4B",X"35",X"90",X"34",X"02",X"97",X"73", + X"0D",X"FA",X"26",X"03",X"7E",X"EF",X"19",X"8E",X"EF",X"F6",X"86",X"00",X"BD",X"D0",X"55",X"33", + X"84",X"BD",X"D0",X"95",X"F9",X"85",X"F2",X"0B",X"44",X"33",X"BD",X"D7",X"11",X"DC",X"E0",X"ED", + X"0A",X"86",X"2C",X"A7",X"0C",X"FC",X"A1",X"03",X"ED",X"88",X"10",X"B6",X"A1",X"05",X"BD",X"DD", + X"9E",X"A7",X"4D",X"B6",X"A1",X"02",X"BD",X"DD",X"9E",X"1F",X"89",X"4F",X"C5",X"01",X"27",X"02", + X"53",X"43",X"ED",X"0E",X"EF",X"06",X"BD",X"FC",X"60",X"AF",X"47",X"8D",X"8B",X"7C",X"A1",X"12", + X"0A",X"73",X"26",X"AC",X"35",X"82",X"AE",X"47",X"10",X"AE",X"49",X"EC",X"D8",X"0B",X"27",X"16", + X"A6",X"29",X"81",X"70",X"26",X"10",X"A6",X"0A",X"84",X"FC",X"97",X"73",X"A6",X"2A",X"84",X"FC", + X"91",X"73",X"27",X"51",X"20",X"0F",X"A6",X"88",X"14",X"84",X"FE",X"A7",X"88",X"14",X"BD",X"EF", + X"78",X"10",X"27",X"01",X"19",X"BD",X"ED",X"59",X"80",X"32",X"A0",X"0C",X"22",X"0F",X"81",X"EC", + X"2D",X"04",X"4F",X"5F",X"20",X"0A",X"FC",X"A1",X"03",X"43",X"53",X"20",X"03",X"FC",X"A1",X"03", + X"ED",X"88",X"10",X"EC",X"02",X"10",X"83",X"F8",X"EC",X"27",X"12",X"BD",X"EE",X"FE",X"EE",X"02", + X"33",X"4A",X"11",X"83",X"F9",X"99",X"23",X"03",X"CE",X"F9",X"85",X"EF",X"02",X"86",X"06",X"8E", + X"EF",X"F6",X"7E",X"D0",X"01",X"4F",X"5F",X"6C",X"88",X"14",X"ED",X"0E",X"ED",X"88",X"10",X"CC", + X"F9",X"85",X"ED",X"02",X"AE",X"47",X"10",X"AE",X"49",X"EC",X"D8",X"0B",X"27",X"98",X"A6",X"29", + X"81",X"70",X"26",X"92",X"EC",X"2A",X"C4",X"E0",X"DD",X"75",X"EC",X"0A",X"C4",X"E0",X"10",X"93", + X"75",X"27",X"0D",X"2D",X"04",X"C6",X"E0",X"20",X"02",X"C6",X"20",X"1D",X"E3",X"0A",X"ED",X"0A", + X"A6",X"2C",X"80",X"0C",X"A1",X"0C",X"27",X"16",X"FC",X"A1",X"03",X"24",X"02",X"43",X"53",X"E3", + X"0C",X"ED",X"0C",X"BD",X"EE",X"FE",X"86",X"01",X"8E",X"F0",X"74",X"7E",X"D0",X"01",X"EC",X"0A", + X"C3",X"00",X"40",X"A3",X"2A",X"10",X"83",X"00",X"80",X"22",X"E8",X"CC",X"F1",X"E0",X"ED",X"08", + X"FC",X"A1",X"03",X"53",X"43",X"ED",X"88",X"10",X"ED",X"A8",X"10",X"CC",X"D5",X"0C",X"BD",X"D5", + X"4D",X"CC",X"ED",X"91",X"ED",X"28",X"DE",X"63",X"AE",X"47",X"A6",X"0C",X"81",X"32",X"23",X"0B", + X"BD",X"EE",X"FE",X"86",X"04",X"8E",X"F0",X"E6",X"7E",X"D0",X"01",X"CC",X"D5",X"11",X"BD",X"D5", + X"4D",X"AE",X"47",X"10",X"AE",X"49",X"EC",X"D8",X"0B",X"26",X"0B",X"BD",X"F3",X"FB",X"7A",X"A1", + X"12",X"0C",X"FB",X"7E",X"D0",X"0A",X"4F",X"5F",X"ED",X"88",X"10",X"ED",X"A8",X"10",X"A6",X"2C", + X"A1",X"0C",X"23",X"0F",X"6A",X"2C",X"86",X"12",X"BD",X"D5",X"39",X"86",X"01",X"8E",X"F1",X"01", + X"7E",X"D0",X"01",X"30",X"A4",X"EC",X"24",X"8B",X"01",X"DD",X"F8",X"BD",X"ED",X"77",X"7A",X"A1", + X"12",X"7C",X"A1",X"15",X"AE",X"47",X"6F",X"88",X"14",X"CC",X"F8",X"CE",X"ED",X"02",X"CC",X"CC", + X"33",X"ED",X"88",X"12",X"CC",X"EF",X"6D",X"ED",X"08",X"B6",X"A1",X"0B",X"A7",X"49",X"AE",X"47", + X"F6",X"A1",X"0A",X"10",X"9E",X"CC",X"10",X"AC",X"0A",X"2C",X"01",X"50",X"1D",X"ED",X"0E",X"DC", + X"CC",X"A3",X"0A",X"C3",X"01",X"7C",X"10",X"83",X"07",X"00",X"23",X"21",X"96",X"C0",X"A0",X"0C", + X"23",X"0B",X"81",X"08",X"22",X"0B",X"FC",X"A1",X"08",X"43",X"53",X"20",X"0B",X"81",X"F8",X"2E", + X"04",X"4F",X"5F",X"20",X"03",X"FC",X"A1",X"08",X"ED",X"88",X"10",X"20",X"12",X"96",X"C0",X"A1", + X"0C",X"FC",X"A1",X"08",X"24",X"02",X"43",X"53",X"ED",X"88",X"10",X"EC",X"04",X"27",X"29",X"F6", + X"A1",X"07",X"96",X"DF",X"2B",X"01",X"50",X"EB",X"0C",X"C1",X"2A",X"24",X"02",X"C6",X"F0",X"E7", + X"0C",X"6A",X"49",X"26",X"13",X"B6",X"A1",X"0B",X"BD",X"DD",X"9E",X"A7",X"49",X"BD",X"EE",X"BA", + X"27",X"06",X"CC",X"D5",X"2A",X"BD",X"D5",X"4D",X"86",X"03",X"8E",X"F1",X"5E",X"7E",X"D0",X"01", + X"EE",X"06",X"EC",X"D8",X"0B",X"27",X"24",X"CC",X"00",X"00",X"CC",X"00",X"00",X"34",X"10",X"8E", + X"F2",X"16",X"86",X"00",X"BD",X"D0",X"55",X"EE",X"49",X"EF",X"07",X"CC",X"D4",X"E9",X"BD",X"D5", + X"4D",X"CC",X"00",X"00",X"ED",X"C8",X"10",X"AF",X"46",X"35",X"10",X"7A",X"A1",X"12",X"BD",X"F4", + X"16",X"01",X"15",X"D5",X"07",X"39",X"AE",X"47",X"CC",X"00",X"08",X"E3",X"88",X"10",X"10",X"83", + X"03",X"00",X"24",X"03",X"ED",X"88",X"10",X"BD",X"ED",X"59",X"A1",X"0C",X"22",X"16",X"EC",X"88", + X"10",X"10",X"83",X"00",X"E0",X"23",X"39",X"EC",X"04",X"C3",X"01",X"07",X"DD",X"F8",X"BD",X"ED", + X"77",X"7E",X"D0",X"0A",X"86",X"04",X"8E",X"F2",X"16",X"7E",X"D0",X"01",X"AE",X"47",X"CC",X"00", + X"00",X"ED",X"88",X"10",X"96",X"C5",X"8B",X"0A",X"A7",X"0C",X"DC",X"CC",X"C3",X"00",X"80",X"ED", + X"0A",X"BD",X"ED",X"59",X"A1",X"0C",X"25",X"0F",X"86",X"01",X"8E",X"F2",X"4C",X"7E",X"D0",X"01", + X"34",X"10",X"8E",X"EE",X"65",X"20",X"05",X"34",X"10",X"8E",X"EE",X"73",X"86",X"00",X"BD",X"D0", + X"55",X"31",X"84",X"35",X"10",X"AF",X"27",X"CC",X"00",X"00",X"ED",X"06",X"ED",X"88",X"10",X"CC", + X"ED",X"70",X"ED",X"08",X"CC",X"D4",X"DF",X"BD",X"D5",X"4D",X"7E",X"D0",X"0A",X"97",X"73",X"F6", + X"A1",X"06",X"03",X"AA",X"2B",X"01",X"50",X"D7",X"74",X"8E",X"F2",X"F7",X"86",X"00",X"BD",X"D0", + X"3E",X"33",X"84",X"96",X"73",X"A7",X"4F",X"4F",X"5F",X"ED",X"47",X"ED",X"49",X"ED",X"4B",X"ED", + X"4D",X"BD",X"D0",X"95",X"F9",X"29",X"F3",X"BC",X"88",X"88",X"D6",X"74",X"1D",X"ED",X"0E",X"4F", + X"5F",X"ED",X"88",X"10",X"96",X"73",X"44",X"56",X"9B",X"73",X"D3",X"CC",X"8B",X"80",X"ED",X"0A", + X"86",X"50",X"A7",X"0C",X"A7",X"C8",X"10",X"EF",X"06",X"9F",X"65",X"96",X"73",X"48",X"8B",X"05", + X"AF",X"C6",X"0A",X"73",X"26",X"CB",X"39",X"96",X"DF",X"84",X"06",X"8B",X"07",X"AE",X"C6",X"10", + X"27",X"00",X"B1",X"D6",X"DF",X"86",X"0A",X"C4",X"3F",X"CB",X"E0",X"2B",X"01",X"40",X"10",X"AE", + X"02",X"31",X"A6",X"10",X"8C",X"F9",X"29",X"24",X"04",X"10",X"8E",X"F9",X"29",X"10",X"8C",X"F9", + X"47",X"23",X"04",X"10",X"8E",X"F9",X"47",X"10",X"AF",X"02",X"1D",X"E3",X"88",X"10",X"ED",X"88", + X"10",X"58",X"49",X"58",X"49",X"58",X"49",X"1F",X"89",X"50",X"1D",X"E3",X"88",X"10",X"ED",X"88", + X"10",X"A6",X"05",X"26",X"3B",X"96",X"DF",X"81",X"40",X"22",X"16",X"84",X"03",X"8B",X"FE",X"AB", + X"C8",X"10",X"81",X"40",X"24",X"02",X"86",X"40",X"81",X"68",X"25",X"02",X"86",X"68",X"A7",X"C8", + X"10",X"A6",X"C8",X"10",X"A0",X"0C",X"8B",X"10",X"81",X"20",X"23",X"48",X"80",X"10",X"2B",X"05", + X"CC",X"FF",X"F0",X"20",X"03",X"CC",X"00",X"10",X"E3",X"88",X"10",X"ED",X"88",X"10",X"20",X"34", + X"90",X"C0",X"2B",X"12",X"81",X"20",X"25",X"05",X"CC",X"FF",X"F0",X"20",X"19",X"81",X"10",X"22", + X"1B",X"CC",X"00",X"10",X"20",X"10",X"81",X"E0",X"2E",X"05",X"CC",X"00",X"10",X"20",X"07",X"81", + X"F0",X"2D",X"09",X"CC",X"FF",X"F0",X"E3",X"88",X"10",X"ED",X"88",X"10",X"96",X"E1",X"84",X"07", + X"26",X"02",X"8D",X"28",X"86",X"01",X"8E",X"F2",X"F7",X"7E",X"D0",X"01",X"BD",X"F4",X"1D",X"01", + X"25",X"D5",X"02",X"7A",X"A1",X"13",X"EE",X"06",X"31",X"47",X"AC",X"A1",X"26",X"FC",X"4F",X"5F", + X"ED",X"3E",X"6A",X"4F",X"26",X"05",X"30",X"C4",X"BD",X"D0",X"15",X"39",X"96",X"99",X"81",X"0A", + X"24",X"18",X"BD",X"E3",X"F3",X"E4",X"98",X"F9",X"5B",X"E5",X"1E",X"27",X"0D",X"D6",X"E0",X"1D", + X"58",X"49",X"96",X"DF",X"84",X"1F",X"4C",X"A7",X"88",X"15",X"39",X"BD",X"D0",X"C7",X"34",X"76", + X"BD",X"F5",X"03",X"EC",X"04",X"10",X"AE",X"02",X"AD",X"B8",X"08",X"35",X"F6",X"34",X"10",X"BD", + X"D0",X"13",X"35",X"10",X"20",X"0A",X"34",X"10",X"BD",X"D0",X"13",X"35",X"10",X"BD",X"D0",X"C7", + X"34",X"46",X"EE",X"64",X"37",X"06",X"BD",X"D3",X"60",X"8D",X"09",X"37",X"06",X"EF",X"64",X"BD", + X"D5",X"4D",X"35",X"C6",X"34",X"76",X"8D",X"C6",X"BD",X"FC",X"63",X"35",X"F6",X"8E",X"F4",X"5B", + X"AF",X"47",X"86",X"06",X"8E",X"F4",X"4A",X"7E",X"D0",X"01",X"AE",X"47",X"EC",X"81",X"DD",X"33", + X"A6",X"80",X"97",X"35",X"8C",X"F4",X"64",X"25",X"E7",X"20",X"E2",X"81",X"81",X"2F",X"81",X"2F", + X"07",X"2F",X"81",X"07",X"86",X"FF",X"97",X"30",X"0F",X"32",X"86",X"03",X"8E",X"F4",X"72",X"7E", + X"D0",X"01",X"96",X"DF",X"84",X"1F",X"8E",X"E7",X"99",X"A6",X"86",X"97",X"30",X"97",X"32",X"8E", + X"CC",X"B0",X"9C",X"A6",X"26",X"03",X"8E",X"CC",X"BC",X"9F",X"A6",X"86",X"06",X"8E",X"F4",X"64", + X"7E",X"D0",X"01",X"96",X"8A",X"26",X"24",X"8E",X"0F",X"1C",X"96",X"8B",X"4A",X"27",X"03",X"8E", + X"71",X"1C",X"CC",X"18",X"08",X"BD",X"F5",X"C7",X"86",X"08",X"8E",X"F4",X"B0",X"7E",X"D0",X"01", + X"BD",X"D3",X"D9",X"86",X"0C",X"8E",X"F4",X"93",X"7E",X"D0",X"01",X"7E",X"D0",X"0A",X"DE",X"63", + X"AF",X"4D",X"D6",X"36",X"E7",X"4C",X"8E",X"F4",X"CC",X"7E",X"D0",X"01",X"A6",X"4C",X"8D",X"3D", + X"6E",X"D8",X"0D",X"32",X"7D",X"34",X"42",X"96",X"36",X"A7",X"65",X"EE",X"66",X"A6",X"42",X"EE", + X"C4",X"EF",X"63",X"8D",X"28",X"35",X"42",X"AD",X"F4",X"34",X"42",X"A6",X"65",X"8D",X"1E",X"EE", + X"66",X"33",X"43",X"EF",X"66",X"35",X"42",X"32",X"63",X"39",X"8D",X"03",X"7E",X"C0",X"00",X"86", + X"07",X"20",X"0A",X"86",X"02",X"20",X"06",X"86",X"03",X"20",X"02",X"86",X"01",X"97",X"36",X"B7", + X"D0",X"00",X"39",X"34",X"7F",X"8D",X"EC",X"BD",X"C0",X"02",X"35",X"FF",X"8D",X"E9",X"7E",X"C0", + X"0F",X"39",X"34",X"76",X"1F",X"01",X"96",X"36",X"34",X"02",X"86",X"02",X"97",X"36",X"B7",X"D0", + X"00",X"EC",X"A4",X"10",X"AE",X"22",X"34",X"06",X"C5",X"01",X"26",X"17",X"C0",X"02",X"EE",X"A5", + X"EF",X"85",X"C0",X"02",X"2A",X"F8",X"E6",X"61",X"30",X"89",X"01",X"00",X"31",X"A5",X"4A",X"26", + X"EB",X"20",X"1D",X"5A",X"A6",X"A5",X"A7",X"85",X"C0",X"02",X"2B",X"08",X"EE",X"A5",X"EF",X"85", + X"C0",X"02",X"2A",X"F8",X"E6",X"61",X"30",X"89",X"01",X"00",X"31",X"A5",X"6A",X"E4",X"26",X"E3", + X"32",X"62",X"35",X"02",X"97",X"36",X"B7",X"D0",X"00",X"35",X"F6",X"34",X"56",X"1F",X"01",X"96", + X"36",X"34",X"02",X"86",X"02",X"97",X"36",X"B7",X"D0",X"00",X"EC",X"A4",X"CE",X"00",X"00",X"34", + X"04",X"C5",X"01",X"26",X"13",X"C0",X"02",X"EF",X"85",X"C0",X"02",X"2A",X"FA",X"E6",X"E4",X"30", + X"89",X"01",X"00",X"4A",X"26",X"EF",X"20",X"16",X"5A",X"6F",X"85",X"C0",X"02",X"2B",X"06",X"EF", + X"85",X"C0",X"02",X"2A",X"FA",X"E6",X"E4",X"30",X"89",X"01",X"00",X"4A",X"26",X"EA",X"35",X"06", + X"D7",X"36",X"F7",X"D0",X"00",X"35",X"D6",X"34",X"56",X"96",X"36",X"34",X"02",X"A6",X"61",X"20", + X"BB",X"34",X"76",X"CE",X"9C",X"00",X"8E",X"00",X"00",X"1F",X"12",X"1F",X"10",X"36",X"36",X"36", + X"36",X"36",X"36",X"36",X"36",X"36",X"36",X"36",X"10",X"11",X"83",X"00",X"00",X"26",X"EE",X"35", + X"F6",X"34",X"7E",X"CE",X"9C",X"00",X"8E",X"00",X"00",X"1F",X"12",X"1F",X"10",X"1F",X"8B",X"C6", + X"08",X"36",X"3A",X"36",X"3A",X"36",X"3A",X"36",X"3A",X"5A",X"26",X"F5",X"36",X"3A",X"36",X"3A", + X"36",X"3A",X"36",X"30",X"33",X"C8",X"D6",X"11",X"83",X"00",X"00",X"26",X"E2",X"35",X"FE",X"7F", + X"D0",X"00",X"8E",X"CC",X"00",X"6F",X"01",X"6F",X"03",X"6F",X"05",X"6F",X"07",X"86",X"C0",X"A7", + X"84",X"86",X"FF",X"A7",X"02",X"6F",X"04",X"6F",X"06",X"86",X"04",X"A7",X"03",X"A7",X"05",X"A7", + X"07",X"8A",X"10",X"A7",X"01",X"8E",X"C0",X"00",X"86",X"C0",X"A7",X"80",X"C6",X"B5",X"3D",X"8C", + X"C0",X"10",X"26",X"F6",X"1A",X"80",X"1C",X"EF",X"10",X"8E",X"00",X"02",X"4F",X"1F",X"8B",X"1C", + X"BF",X"5F",X"1F",X"03",X"8E",X"00",X"00",X"53",X"C5",X"09",X"26",X"05",X"53",X"46",X"56",X"20", + X"0B",X"53",X"C5",X"09",X"26",X"04",X"46",X"56",X"20",X"02",X"44",X"56",X"ED",X"81",X"1E",X"10", + X"5D",X"26",X"17",X"C6",X"38",X"F7",X"C3",X"FC",X"1F",X"A9",X"C5",X"10",X"27",X"0B",X"7F",X"D0", + X"00",X"F6",X"CC",X"00",X"53",X"C5",X"03",X"27",X"51",X"5F",X"1E",X"10",X"8C",X"C0",X"00",X"26", + X"C6",X"1F",X"30",X"8E",X"00",X"00",X"53",X"C5",X"09",X"26",X"05",X"53",X"46",X"56",X"20",X"0B", + X"53",X"C5",X"09",X"26",X"04",X"46",X"56",X"20",X"02",X"44",X"56",X"10",X"A3",X"81",X"27",X"17", + X"1E",X"02",X"1F",X"A8",X"85",X"10",X"27",X"0A",X"86",X"03",X"97",X"36",X"B7",X"D0",X"00",X"7E", + X"C0",X"2A",X"4F",X"1E",X"20",X"1A",X"40",X"1E",X"10",X"5D",X"26",X"42",X"1F",X"A9",X"C5",X"10", + X"27",X"12",X"F6",X"CC",X"00",X"53",X"C5",X"03",X"26",X"2E",X"86",X"03",X"97",X"36",X"B7",X"D0", + X"00",X"7E",X"C0",X"2D",X"1F",X"A9",X"C5",X"40",X"27",X"1E",X"1C",X"BF",X"1F",X"B9",X"1F",X"8B", + X"80",X"03",X"24",X"FC",X"4C",X"26",X"04",X"CA",X"02",X"20",X"09",X"4C",X"26",X"04",X"CA",X"01", + X"20",X"02",X"CA",X"04",X"1F",X"B8",X"1F",X"9B",X"C6",X"38",X"F7",X"C3",X"FC",X"5F",X"1E",X"10", + X"8C",X"C0",X"00",X"10",X"26",X"FF",X"7F",X"31",X"3F",X"10",X"26",X"FF",X"35",X"1F",X"A9",X"5D", + X"2B",X"0B",X"C6",X"03",X"F7",X"D0",X"00",X"BD",X"F8",X"00",X"7E",X"C0",X"30",X"C5",X"10",X"10", + X"26",X"FF",X"1F",X"86",X"9E",X"1F",X"B9",X"5D",X"27",X"04",X"4C",X"54",X"25",X"FC",X"1F",X"8B", + X"8B",X"01",X"5F",X"1F",X"04",X"BD",X"F8",X"00",X"CE",X"F8",X"6E",X"7F",X"D0",X"00",X"86",X"38", + X"B7",X"C3",X"FC",X"A6",X"C4",X"E6",X"C4",X"27",X"2A",X"C4",X"0F",X"F7",X"D0",X"00",X"84",X"70", + X"44",X"8B",X"C0",X"5F",X"1F",X"01",X"10",X"8E",X"08",X"00",X"1F",X"30",X"C0",X"6C",X"54",X"4F", + X"E9",X"80",X"31",X"3F",X"26",X"FA",X"C1",X"80",X"27",X"09",X"1F",X"A8",X"85",X"10",X"27",X"3E", + X"7E",X"F5",X"07",X"33",X"41",X"11",X"83",X"F8",X"86",X"26",X"C0",X"1F",X"A8",X"85",X"10",X"26", + X"EF",X"1F",X"B8",X"81",X"9E",X"26",X"08",X"BD",X"F5",X"07",X"BD",X"C0",X"00",X"20",X"26",X"C6", + X"40",X"8D",X"05",X"BD",X"C0",X"03",X"20",X"1D",X"8E",X"CC",X"00",X"E7",X"84",X"E7",X"02",X"7F", + X"D0",X"00",X"86",X"38",X"B7",X"C3",X"FC",X"30",X"1F",X"26",X"F7",X"7E",X"F5",X"07",X"C6",X"80", + X"8D",X"E6",X"BD",X"C0",X"06",X"BD",X"C0",X"09",X"7E",X"D7",X"38",X"34",X"03",X"96",X"36",X"34", + X"02",X"0F",X"36",X"7F",X"D0",X"00",X"E7",X"84",X"35",X"02",X"97",X"36",X"B7",X"D0",X"00",X"35", + X"83",X"34",X"03",X"96",X"36",X"34",X"02",X"0F",X"36",X"7F",X"D0",X"00",X"E6",X"84",X"20",X"E8", + X"34",X"06",X"0F",X"52",X"0F",X"49",X"86",X"03",X"97",X"36",X"97",X"48",X"CC",X"FF",X"FF",X"DD", + X"59",X"35",X"86",X"A6",X"01",X"84",X"0F",X"34",X"02",X"A6",X"81",X"48",X"48",X"48",X"48",X"AB", + X"E0",X"39",X"34",X"04",X"D6",X"36",X"34",X"04",X"0F",X"36",X"7F",X"D0",X"00",X"8D",X"E4",X"35", + X"04",X"D7",X"36",X"F7",X"D0",X"00",X"35",X"84",X"8D",X"E8",X"34",X"02",X"8D",X"E4",X"1F",X"89", + X"35",X"82",X"34",X"02",X"A7",X"01",X"44",X"44",X"44",X"44",X"A7",X"81",X"35",X"82",X"34",X"04", + X"D6",X"36",X"34",X"04",X"0F",X"36",X"7F",X"D0",X"00",X"8D",X"E7",X"35",X"04",X"D7",X"36",X"F7", + X"D0",X"00",X"35",X"84",X"8D",X"E8",X"34",X"02",X"1F",X"98",X"8D",X"E2",X"35",X"82",X"20",X"00", + X"40",X"50",X"60",X"70",X"30",X"00",X"00",X"00",X"07",X"00",X"03",X"00",X"02",X"00",X"01",X"00", + X"13",X"00",X"12",X"00",X"11",X"00",X"E5",X"91",X"00",X"E8",X"00",X"00",X"00",X"00",X"E8",X"C1", + X"00",X"F8",X"E9",X"1F",X"00",X"F8",X"D8",X"4E",X"00",X"00",X"D8",X"39",X"00",X"00",X"E8",X"97", + X"00",X"E8",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"D4",X"4C",X"00",X"00",X"D4",X"75", + X"02",X"00",X"D4",X"3D",X"00",X"00",X"D4",X"6E",X"02",X"00",X"D4",X"7C",X"02",X"00",X"00",X"00", + X"07",X"28",X"2F",X"81",X"A4",X"15",X"C7",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"08", + X"F9",X"FB",X"FA",X"23",X"D1",X"93",X"D1",X"1F",X"04",X"08",X"FA",X"4B",X"FA",X"4B",X"D1",X"39", + X"D1",X"6B",X"04",X"08",X"FA",X"6B",X"FA",X"6B",X"D1",X"39",X"D1",X"6B",X"01",X"01",X"F8",X"F6", + X"F8",X"F6",X"D8",X"DB",X"D8",X"DB",X"00",X"04",X"08",X"FA",X"8B",X"FA",X"AB",X"D1",X"39",X"D1", + X"6B",X"02",X"08",X"FA",X"CB",X"FA",X"DB",X"D0",X"F9",X"D1",X"0B",X"02",X"08",X"FA",X"EB",X"FA", + X"FB",X"D0",X"F9",X"D1",X"0B",X"02",X"08",X"FB",X"0B",X"FB",X"1B",X"D0",X"F9",X"D1",X"0B",X"02", + X"08",X"FB",X"2B",X"FB",X"3B",X"D0",X"F9",X"D1",X"0B",X"04",X"08",X"FB",X"4B",X"FB",X"6B",X"D1", + X"39",X"D1",X"6B",X"04",X"08",X"FB",X"8B",X"FB",X"AB",X"D1",X"39",X"D1",X"6B",X"04",X"08",X"FB", + X"CB",X"FB",X"EB",X"D1",X"39",X"D1",X"6B",X"04",X"08",X"FC",X"0B",X"FC",X"2B",X"D1",X"39",X"D1", + X"6B",X"04",X"08",X"CC",X"90",X"CC",X"90",X"D1",X"39",X"D1",X"6B",X"02",X"03",X"CC",X"B0",X"CC", + X"B6",X"D1",X"F1",X"D2",X"0D",X"02",X"03",X"CC",X"BC",X"CC",X"C2",X"D1",X"F1",X"D2",X"0D",X"08", + X"01",X"F9",X"73",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"03",X"04",X"CC",X"C8",X"CC", + X"D4",X"D1",X"AD",X"D1",X"D7",X"05",X"08",X"CC",X"E0",X"CD",X"08",X"D1",X"93",X"D1",X"1F",X"05", + X"08",X"CD",X"30",X"CD",X"58",X"D1",X"93",X"D1",X"1F",X"05",X"08",X"CD",X"80",X"CD",X"A8",X"D1", + X"93",X"D1",X"1F",X"06",X"04",X"CD",X"D0",X"CD",X"E8",X"D2",X"1F",X"D2",X"60",X"06",X"04",X"CE", + X"00",X"CE",X"18",X"D2",X"1F",X"D2",X"60",X"06",X"04",X"CE",X"30",X"CE",X"48",X"D2",X"1F",X"D2", + X"60",X"08",X"06",X"CE",X"60",X"CE",X"90",X"D2",X"8E",X"D2",X"DF",X"08",X"06",X"CE",X"C0",X"CE", + X"F0",X"D2",X"8E",X"D2",X"DF",X"05",X"04",X"CF",X"20",X"03",X"03",X"CF",X"34",X"06",X"06",X"CF", + X"3D",X"CF",X"61",X"D3",X"3D",X"D3",X"50",X"06",X"06",X"CF",X"85",X"CF",X"A9",X"D3",X"3D",X"D3", + X"50",X"08",X"06",X"CF",X"CD",X"CF",X"CD",X"F5",X"22",X"F5",X"7B",X"00",X"00",X"03",X"03",X"00", + X"00",X"03",X"30",X"0C",X"3C",X"0C",X"08",X"38",X"30",X"00",X"00",X"C0",X"C0",X"C8",X"78",X"78", + X"70",X"70",X"70",X"00",X"30",X"03",X"03",X"30",X"30",X"03",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"00",X"03",X"30",X"30",X"03", + X"03",X"30",X"00",X"CC",X"CC",X"CC",X"87",X"87",X"07",X"07",X"07",X"00",X"03",X"80",X"80",X"83", + X"03",X"00",X"00",X"00",X"00",X"30",X"30",X"00",X"00",X"30",X"03",X"00",X"00",X"0D",X"6C",X"6C", + X"0D",X"00",X"00",X"06",X"E6",X"C8",X"83",X"82",X"C8",X"EC",X"06",X"60",X"6D",X"8C",X"28",X"28", + X"8C",X"6D",X"60",X"00",X"00",X"E0",X"C6",X"C6",X"E0",X"00",X"00",X"00",X"00",X"02",X"22",X"24", + X"02",X"00",X"00",X"02",X"22",X"44",X"44",X"24",X"42",X"22",X"00",X"20",X"22",X"44",X"44",X"24", + X"42",X"22",X"00",X"00",X"00",X"20",X"22",X"22",X"20",X"00",X"00",X"00",X"0E",X"00",X"D8",X"00", + X"0E",X"00",X"00",X"0F",X"08",X"8C",X"C8",X"8C",X"08",X"0F",X"00",X"00",X"0E",X"80",X"C8",X"80", + X"0E",X"00",X"00",X"00",X"00",X"00",X"D0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"00", + X"00",X"00",X"00",X"00",X"E0",X"08",X"8C",X"08",X"E0",X"00",X"00",X"F0",X"80",X"C8",X"8C",X"C8", + X"80",X"F0",X"00",X"00",X"E0",X"00",X"8D",X"00",X"E0",X"00",X"00",X"33",X"43",X"43",X"87",X"87", + X"07",X"07",X"07",X"00",X"00",X"80",X"80",X"80",X"00",X"00",X"00",X"03",X"04",X"04",X"08",X"08", + X"00",X"00",X"00",X"30",X"30",X"38",X"78",X"78",X"70",X"70",X"70",X"33",X"43",X"43",X"87",X"87", + X"77",X"77",X"77",X"00",X"00",X"80",X"80",X"80",X"00",X"00",X"00",X"03",X"04",X"04",X"08",X"08", + X"07",X"07",X"07",X"30",X"30",X"38",X"78",X"78",X"70",X"70",X"70",X"03",X"03",X"83",X"87",X"87", + X"07",X"07",X"07",X"30",X"40",X"40",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"08", + X"00",X"00",X"00",X"33",X"34",X"34",X"78",X"78",X"70",X"70",X"70",X"03",X"03",X"83",X"87",X"87", + X"07",X"07",X"07",X"30",X"40",X"40",X"80",X"80",X"70",X"70",X"70",X"00",X"00",X"08",X"08",X"08", + X"00",X"00",X"00",X"33",X"34",X"34",X"78",X"78",X"77",X"77",X"77",X"08",X"08",X"DD",X"DE",X"DE", + X"DE",X"DD",X"00",X"88",X"88",X"DD",X"EE",X"FE",X"EE",X"DD",X"00",X"88",X"88",X"D8",X"D8",X"D8", + X"D0",X"D0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"0D",X"0D", + X"0D",X"0D",X"00",X"88",X"88",X"DD",X"EE",X"EF",X"EE",X"DD",X"00",X"88",X"88",X"DD",X"ED",X"ED", + X"ED",X"DD",X"00",X"80",X"80",X"80",X"80",X"80",X"00",X"00",X"00",X"00",X"08",X"DD",X"DE",X"DE", + X"DE",X"DD",X"00",X"00",X"88",X"DD",X"EE",X"FE",X"EE",X"DD",X"00",X"00",X"88",X"D8",X"D8",X"D8", + X"D8",X"D0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"0D",X"0D", + X"0D",X"0D",X"00",X"00",X"88",X"DD",X"EE",X"EF",X"EE",X"DD",X"00",X"00",X"88",X"DD",X"ED",X"ED", + X"ED",X"DD",X"00",X"00",X"80",X"80",X"80",X"80",X"80",X"00",X"00",X"00",X"00",X"DD",X"DE",X"DE", + X"DE",X"DD",X"00",X"00",X"00",X"DD",X"EE",X"FE",X"EE",X"DD",X"00",X"00",X"00",X"D8",X"D8",X"D8", + X"D8",X"D8",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"0D",X"0D", + X"0D",X"0D",X"00",X"00",X"00",X"DD",X"EE",X"EF",X"EE",X"DD",X"00",X"00",X"00",X"DD",X"ED",X"ED", + X"ED",X"DD",X"00",X"00",X"00",X"80",X"80",X"80",X"80",X"80",X"00",X"00",X"00",X"DD",X"DE",X"DE", + X"DE",X"DD",X"00",X"00",X"00",X"DD",X"EE",X"FE",X"EE",X"DD",X"88",X"00",X"00",X"D0",X"D8",X"D8", + X"D8",X"D8",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"0D",X"0D", + X"0D",X"0D",X"00",X"00",X"00",X"DD",X"EE",X"EF",X"EE",X"DD",X"88",X"00",X"00",X"DD",X"ED",X"ED", + X"ED",X"DD",X"88",X"00",X"00",X"00",X"80",X"80",X"80",X"80",X"80",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"7E",X"FC",X"69",X"7E",X"FC",X"CC",X"7E",X"FD",X"2D",X"34",X"66",X"EC",X"02",X"34",X"06",X"FC", + X"FF",X"9D",X"ED",X"02",X"9F",X"65",X"EC",X"0A",X"93",X"20",X"10",X"83",X"26",X"00",X"22",X"17", + X"10",X"9E",X"E2",X"27",X"09",X"31",X"A8",X"40",X"10",X"8C",X"A0",X"00",X"26",X"04",X"10",X"8E", + X"9C",X"00",X"10",X"9C",X"E2",X"26",X"06",X"35",X"06",X"ED",X"02",X"20",X"2D",X"A6",X"A4",X"2B", + X"E4",X"27",X"03",X"BD",X"FD",X"D5",X"96",X"BA",X"85",X"80",X"26",X"06",X"FC",X"FF",X"DD",X"BD", + X"FF",X"DA",X"A6",X"88",X"14",X"8A",X"02",X"A7",X"88",X"14",X"CC",X"AF",X"00",X"ED",X"A4",X"35", + X"06",X"ED",X"22",X"33",X"A8",X"40",X"EF",X"24",X"AF",X"2A",X"35",X"E6",X"34",X"66",X"EC",X"0A", + X"93",X"20",X"81",X"26",X"22",X"55",X"DD",X"E9",X"10",X"9E",X"E2",X"27",X"09",X"31",X"A8",X"40", + X"10",X"8C",X"A0",X"00",X"26",X"04",X"10",X"8E",X"9C",X"00",X"10",X"9C",X"E2",X"27",X"3C",X"A6", + X"A4",X"2B",X"EA",X"27",X"03",X"BD",X"FD",X"D5",X"10",X"9F",X"E2",X"CC",X"01",X"00",X"ED",X"A4", + X"EC",X"02",X"ED",X"22",X"33",X"A8",X"40",X"EF",X"24",X"DC",X"E9",X"58",X"49",X"58",X"49",X"E6", + X"0C",X"ED",X"28",X"93",X"F8",X"EE",X"22",X"AB",X"C4",X"24",X"08",X"EB",X"41",X"24",X"04",X"DC", + X"F8",X"20",X"06",X"EC",X"C4",X"44",X"54",X"E3",X"28",X"ED",X"26",X"35",X"E6",X"10",X"8E",X"9C", + X"00",X"96",X"BA",X"85",X"04",X"27",X"0C",X"A6",X"A4",X"2B",X"56",X"CC",X"00",X"00",X"ED",X"A4", + X"7E",X"FD",X"C9",X"EC",X"A4",X"10",X"27",X"00",X"80",X"2B",X"33",X"C3",X"00",X"AA",X"ED",X"A4", + X"81",X"30",X"23",X"0A",X"BD",X"FD",X"D5",X"CC",X"00",X"00",X"ED",X"A4",X"20",X"6B",X"DC",X"20", + X"C4",X"C0",X"34",X"06",X"DC",X"22",X"C4",X"C0",X"A3",X"E1",X"58",X"49",X"58",X"49",X"34",X"02", + X"A6",X"26",X"AB",X"E4",X"A7",X"26",X"A6",X"28",X"AB",X"E0",X"A7",X"28",X"20",X"45",X"83",X"01", + X"00",X"ED",X"A4",X"2A",X"0C",X"AE",X"2A",X"EC",X"0A",X"93",X"20",X"8B",X"0C",X"85",X"C0",X"27", + X"18",X"CC",X"00",X"00",X"ED",X"A4",X"EC",X"22",X"AE",X"2A",X"ED",X"02",X"A6",X"88",X"14",X"84", + X"FD",X"A7",X"88",X"14",X"BD",X"FD",X"D5",X"20",X"20",X"80",X"0C",X"58",X"49",X"58",X"49",X"E6", + X"0C",X"ED",X"28",X"C6",X"DA",X"3D",X"48",X"EE",X"22",X"E6",X"C4",X"3D",X"E6",X"41",X"54",X"E3", + X"28",X"ED",X"26",X"BD",X"FD",X"D5",X"BD",X"FD",X"EF",X"31",X"A8",X"40",X"10",X"8C",X"A0",X"00", + X"10",X"26",X"FF",X"5D",X"39",X"34",X"16",X"CC",X"00",X"00",X"30",X"A8",X"40",X"9F",X"F3",X"AE", + X"24",X"9C",X"F3",X"27",X"08",X"ED",X"91",X"9C",X"F3",X"26",X"FA",X"AF",X"24",X"35",X"96",X"34", + X"76",X"10",X"9F",X"F6",X"A6",X"A4",X"84",X"7F",X"97",X"E7",X"33",X"A8",X"40",X"0F",X"E6",X"AE", + X"22",X"EC",X"02",X"DD",X"F3",X"EC",X"84",X"97",X"F1",X"D7",X"F2",X"C5",X"01",X"26",X"05",X"8E", + X"FF",X"27",X"20",X"03",X"8E",X"FE",X"F3",X"9F",X"ED",X"EC",X"26",X"A3",X"28",X"97",X"E4",X"54", + X"D7",X"E5",X"09",X"E6",X"96",X"E7",X"D6",X"E4",X"3D",X"DD",X"E9",X"E6",X"26",X"4F",X"93",X"E9", + X"DD",X"E9",X"4D",X"27",X"18",X"DC",X"F3",X"DB",X"F2",X"89",X"00",X"DD",X"F3",X"0A",X"F1",X"10", + X"27",X"00",X"F2",X"DC",X"E9",X"DB",X"E7",X"89",X"00",X"DD",X"E9",X"20",X"E5",X"C1",X"98",X"10", + X"22",X"00",X"E2",X"96",X"E7",X"48",X"97",X"E8",X"D6",X"E5",X"3D",X"DD",X"EB",X"E6",X"27",X"4F", + X"93",X"EB",X"D0",X"E6",X"89",X"00",X"0F",X"F5",X"4D",X"26",X"04",X"C1",X"2A",X"24",X"10",X"0C", + X"F5",X"0A",X"F2",X"0A",X"F2",X"10",X"2F",X"00",X"BC",X"DB",X"E8",X"89",X"00",X"20",X"E9",X"DD", + X"EB",X"96",X"F2",X"84",X"FE",X"8E",X"FF",X"48",X"AE",X"86",X"9F",X"EF",X"9E",X"F3",X"08",X"F5", + X"96",X"EA",X"D6",X"F5",X"3A",X"D6",X"EC",X"6E",X"9F",X"A0",X"EF",X"ED",X"C3",X"10",X"AE",X"81", + X"10",X"AF",X"D4",X"DB",X"E8",X"25",X"56",X"ED",X"C3",X"10",X"AE",X"81",X"10",X"AF",X"D4",X"DB", + X"E8",X"25",X"50",X"ED",X"C3",X"10",X"AE",X"81",X"10",X"AF",X"D4",X"DB",X"E8",X"25",X"4A",X"ED", + X"C3",X"10",X"AE",X"81",X"10",X"AF",X"D4",X"DB",X"E8",X"25",X"44",X"ED",X"C3",X"10",X"AE",X"81", + X"10",X"AF",X"D4",X"DB",X"E8",X"25",X"3E",X"ED",X"C3",X"10",X"AE",X"81",X"10",X"AF",X"D4",X"DB", + X"E8",X"25",X"38",X"ED",X"C3",X"10",X"AE",X"81",X"10",X"AF",X"D4",X"DB",X"E8",X"25",X"32",X"6E", + X"9F",X"A0",X"ED",X"25",X"30",X"ED",X"C3",X"E6",X"80",X"E7",X"D4",X"20",X"2A",X"30",X"0C",X"6E", + X"9F",X"A0",X"ED",X"30",X"0A",X"6E",X"9F",X"A0",X"ED",X"30",X"08",X"6E",X"9F",X"A0",X"ED",X"30", + X"06",X"6E",X"9F",X"A0",X"ED",X"30",X"04",X"6E",X"9F",X"A0",X"ED",X"30",X"02",X"6E",X"9F",X"A0", + X"ED",X"6E",X"9F",X"A0",X"ED",X"30",X"01",X"0A",X"F1",X"27",X"0A",X"9B",X"E7",X"25",X"06",X"81", + X"98",X"10",X"23",X"FF",X"5D",X"9E",X"F6",X"EF",X"04",X"EC",X"06",X"81",X"98",X"22",X"07",X"D0", + X"E6",X"8E",X"00",X"00",X"AF",X"8B",X"35",X"F6",X"FE",X"EF",X"FE",X"E3",X"FE",X"D7",X"FE",X"CB", + X"FE",X"BF",X"FE",X"B3",X"FE",X"A7",X"FE",X"9B",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F8",X"EC",X"F8", + X"6E",X"7E",X"F8",X"22",X"7E",X"F8",X"3A",X"7E",X"F8",X"38",X"7E",X"F8",X"4E",X"7E",X"F8",X"66", + X"7E",X"F8",X"64",X"7E",X"F5",X"22",X"7E",X"F5",X"7B",X"7E",X"F5",X"C7",X"7E",X"F5",X"D1",X"7E", + X"F7",X"58",X"7E",X"F7",X"93",X"7E",X"F6",X"62",X"7E",X"F7",X"D5",X"7E",X"F4",X"FA",X"7E",X"F4", + X"D3",X"7E",X"F4",X"BE",X"7E",X"F7",X"DB",X"7E",X"F7",X"F1",X"7E",X"D5",X"4D",X"D4",X"EE",X"2A", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"F6",X"1F",X"F6",X"1F",X"F6",X"1F",X"F6",X"1F",X"A0",X"8F",X"F6",X"1F",X"F6",X"1F",X"F6",X"1F", + X"7E",X"C0",X"06",X"7E",X"CC",X"AD",X"BD",X"D0",X"7C",X"86",X"FF",X"97",X"BA",X"BD",X"E0",X"52", + X"96",X"37",X"B7",X"A1",X"83",X"4F",X"B7",X"A1",X"84",X"B7",X"A1",X"78",X"96",X"B7",X"10",X"27", + X"06",X"55",X"8E",X"C8",X"F4",X"86",X"00",X"BD",X"D0",X"55",X"10",X"8E",X"A1",X"C2",X"86",X"01", + X"97",X"06",X"10",X"BF",X"A1",X"7B",X"8E",X"B2",X"B4",X"BD",X"C1",X"47",X"10",X"24",X"00",X"EA", + X"7C",X"A1",X"78",X"BD",X"F5",X"D1",X"96",X"06",X"4A",X"26",X"05",X"BD",X"D8",X"DC",X"20",X"03", + X"BD",X"D8",X"EA",X"C6",X"85",X"D7",X"27",X"86",X"3E",X"8E",X"B2",X"60",X"BD",X"C1",X"47",X"24", + X"02",X"86",X"3D",X"8E",X"CC",X"02",X"C6",X"3F",X"BD",X"FF",X"D4",X"C6",X"24",X"BD",X"FF",X"D4", + X"5A",X"26",X"FD",X"C6",X"3F",X"BD",X"FF",X"D4",X"1F",X"89",X"BD",X"FF",X"D4",X"CE",X"C0",X"ED", + X"96",X"06",X"48",X"33",X"C6",X"8E",X"3E",X"38",X"BD",X"FF",X"CE",X"C0",X"02",X"02",X"CE",X"C0", + X"FD",X"8E",X"14",X"58",X"BD",X"FF",X"CE",X"C0",X"02",X"02",X"CC",X"41",X"2F",X"DD",X"00",X"86", + X"40",X"DD",X"02",X"DD",X"04",X"BD",X"C1",X"58",X"86",X"28",X"B7",X"A1",X"7D",X"8E",X"C1",X"DC", + X"86",X"00",X"BD",X"D0",X"55",X"8E",X"C1",X"E7",X"86",X"00",X"BD",X"D0",X"55",X"8E",X"C1",X"FA", + X"86",X"00",X"BD",X"D0",X"55",X"7F",X"A1",X"7A",X"BD",X"C1",X"6B",X"4F",X"B7",X"A1",X"86",X"B7", + X"A1",X"85",X"86",X"01",X"8E",X"C0",X"DA",X"7E",X"F4",X"BE",X"96",X"7B",X"85",X"01",X"26",X"14", + X"7D",X"A1",X"7D",X"27",X"29",X"7C",X"A1",X"86",X"B6",X"A1",X"86",X"81",X"05",X"26",X"E3",X"B7", + X"A1",X"85",X"20",X"DE",X"7F",X"A1",X"86",X"7D",X"A1",X"85",X"27",X"D6",X"86",X"14",X"B7",X"A1", + X"7D",X"7C",X"A1",X"7A",X"BD",X"C1",X"6B",X"B6",X"A1",X"7A",X"81",X"03",X"26",X"BD",X"BD",X"D0", + X"7C",X"8E",X"B2",X"A8",X"CE",X"B2",X"54",X"BD",X"C1",X"94",X"8E",X"C4",X"71",X"8D",X"28",X"24", + X"09",X"8E",X"C4",X"65",X"CE",X"C4",X"11",X"BD",X"C1",X"94",X"10",X"8E",X"A1",X"FF",X"96",X"06", + X"4C",X"81",X"03",X"10",X"26",X"FE",X"F9",X"7D",X"A1",X"78",X"26",X"08",X"86",X"FF",X"8E",X"C1", + X"44",X"7E",X"F4",X"BE",X"7E",X"C2",X"63",X"34",X"16",X"BD",X"F8",X"38",X"10",X"A3",X"21",X"26", + X"05",X"BD",X"F8",X"22",X"A1",X"23",X"35",X"96",X"8E",X"46",X"AC",X"CC",X"14",X"08",X"BD",X"F5", + X"C7",X"CE",X"C0",X"FF",X"BD",X"FF",X"CE",X"C0",X"02",X"02",X"39",X"7F",X"A1",X"62",X"8E",X"45", + X"B7",X"CE",X"11",X"11",X"B6",X"A1",X"62",X"B1",X"A1",X"7A",X"26",X"03",X"CE",X"DD",X"DD",X"CC", + X"04",X"00",X"EF",X"8B",X"4A",X"26",X"FB",X"7C",X"A1",X"62",X"30",X"89",X"08",X"00",X"8C",X"5D", + X"B7",X"26",X"DE",X"39",X"FF",X"A1",X"64",X"10",X"BE",X"A1",X"7B",X"8D",X"AA",X"24",X"09",X"8D", + X"24",X"30",X"14",X"BC",X"A1",X"64",X"22",X"F3",X"30",X"0C",X"EC",X"21",X"BD",X"F8",X"64",X"A6", + X"23",X"BD",X"F8",X"4E",X"CE",X"A0",X"00",X"A6",X"C4",X"BD",X"F8",X"4E",X"33",X"42",X"11",X"83", + X"A0",X"06",X"26",X"F3",X"39",X"34",X"10",X"BD",X"F8",X"38",X"30",X"08",X"BD",X"F8",X"64",X"30", + X"88",X"E8",X"AC",X"E4",X"27",X"04",X"30",X"0C",X"20",X"ED",X"35",X"90",X"7A",X"A1",X"7D",X"86", + X"3C",X"8E",X"C1",X"DC",X"7E",X"F4",X"BE",X"96",X"33",X"26",X"04",X"96",X"27",X"20",X"01",X"4F", + X"97",X"33",X"86",X"0F",X"8E",X"C1",X"E7",X"7E",X"F4",X"BE",X"7F",X"A1",X"79",X"96",X"7B",X"85", + X"80",X"27",X"04",X"86",X"FF",X"20",X"0F",X"96",X"7D",X"85",X"01",X"27",X"04",X"86",X"01",X"20", + X"05",X"7F",X"A1",X"79",X"20",X"34",X"B1",X"A1",X"79",X"26",X"37",X"7A",X"A1",X"7F",X"26",X"2A", + X"8E",X"A0",X"00",X"F6",X"A1",X"7A",X"58",X"3A",X"A6",X"84",X"BB",X"A1",X"79",X"81",X"3F",X"26", + X"02",X"86",X"5A",X"81",X"5B",X"26",X"02",X"86",X"40",X"A7",X"84",X"BD",X"C1",X"58",X"B6",X"A1", + X"7E",X"44",X"8B",X"05",X"B7",X"A1",X"7E",X"B7",X"A1",X"7F",X"86",X"01",X"8E",X"C1",X"FD",X"7E", + X"F4",X"BE",X"B7",X"A1",X"79",X"86",X"37",X"B7",X"A1",X"7E",X"86",X"03",X"B7",X"A1",X"7F",X"20", + X"E9",X"DE",X"FF",X"7F",X"A1",X"62",X"BD",X"D0",X"7C",X"BD",X"C8",X"6F",X"BD",X"F5",X"D1",X"BD", + X"D8",X"DC",X"0F",X"27",X"8E",X"C8",X"F4",X"86",X"00",X"BD",X"D0",X"55",X"BD",X"C9",X"36",X"CE", + X"C1",X"01",X"8E",X"38",X"54",X"BD",X"FF",X"CE",X"C0",X"02",X"02",X"CE",X"11",X"11",X"8E",X"1E", + X"7B",X"CC",X"5F",X"00",X"EF",X"8B",X"81",X"41",X"26",X"02",X"86",X"1F",X"4A",X"2A",X"F5",X"86", + X"2F",X"97",X"07",X"97",X"0B",X"97",X"12",X"CE",X"C1",X"03",X"8E",X"18",X"86",X"BF",X"A1",X"81", + X"8E",X"B2",X"60",X"BF",X"A1",X"64",X"8D",X"4E",X"8E",X"59",X"86",X"BF",X"A1",X"81",X"8E",X"C4", + X"1D",X"BF",X"A1",X"64",X"8D",X"40",X"86",X"3F",X"97",X"32",X"10",X"8E",X"B3",X"00",X"CC",X"3C", + X"18",X"ED",X"A4",X"CC",X"B4",X"12",X"ED",X"22",X"CC",X"30",X"38",X"BD",X"F5",X"22",X"8E",X"E7", + X"82",X"86",X"00",X"BD",X"D0",X"55",X"86",X"3C",X"B7",X"A1",X"7D",X"7D",X"A1",X"84",X"26",X"14", + X"7D",X"A1",X"62",X"10",X"26",X"FF",X"6C",X"7A",X"A1",X"7D",X"27",X"08",X"86",X"0A",X"8E",X"C2", + X"EB",X"7E",X"F4",X"BE",X"20",X"4B",X"86",X"31",X"97",X"06",X"4F",X"10",X"8E",X"A0",X"0C",X"BE", + X"A1",X"64",X"BD",X"FF",X"D7",X"30",X"01",X"C4",X"0F",X"26",X"07",X"4D",X"26",X"04",X"C6",X"40", + X"20",X"03",X"4C",X"CB",X"30",X"E7",X"A0",X"10",X"8C",X"A0",X"12",X"26",X"E5",X"BD",X"F8",X"38", + X"DD",X"08",X"BD",X"F8",X"22",X"97",X"0A",X"BF",X"A1",X"64",X"BE",X"A1",X"81",X"BD",X"FF",X"CE", + X"C0",X"02",X"02",X"30",X"0A",X"BF",X"A1",X"81",X"0C",X"06",X"96",X"06",X"81",X"39",X"26",X"BA", + X"39",X"BD",X"D0",X"7C",X"BD",X"C4",X"3C",X"86",X"D9",X"97",X"BA",X"BD",X"C9",X"36",X"8E",X"C8", + X"F4",X"86",X"00",X"BD",X"D0",X"55",X"BD",X"D6",X"BC",X"8E",X"CC",X"63",X"BF",X"A1",X"96",X"8E", + X"E7",X"82",X"86",X"00",X"BD",X"D0",X"55",X"8E",X"F4",X"64",X"86",X"00",X"BD",X"D0",X"55",X"8E", + X"F4",X"3D",X"86",X"00",X"BD",X"D0",X"55",X"8E",X"E9",X"E3",X"86",X"00",X"BD",X"D0",X"55",X"8E", + X"C6",X"4F",X"86",X"00",X"BD",X"D0",X"55",X"BD",X"D0",X"AD",X"CC",X"00",X"00",X"ED",X"0E",X"ED", + X"88",X"10",X"CC",X"1E",X"00",X"ED",X"0A",X"CC",X"DB",X"00",X"ED",X"0C",X"CC",X"F9",X"01",X"ED", + X"02",X"9F",X"65",X"CC",X"66",X"66",X"ED",X"88",X"12",X"BF",X"A1",X"89",X"BD",X"D0",X"AD",X"CC", + X"00",X"00",X"ED",X"0E",X"ED",X"88",X"10",X"CC",X"08",X"00",X"ED",X"0A",X"CC",X"50",X"00",X"ED", + X"0C",X"CC",X"F9",X"C1",X"ED",X"02",X"9F",X"65",X"CC",X"00",X"00",X"ED",X"88",X"12",X"BF",X"A1", + X"8B",X"BD",X"D0",X"AD",X"CC",X"F9",X"85",X"ED",X"02",X"CC",X"1D",X"A0",X"ED",X"0A",X"CC",X"40", + X"00",X"ED",X"0C",X"CC",X"00",X"A0",X"ED",X"88",X"10",X"CC",X"00",X"00",X"ED",X"0E",X"CC",X"44", + X"33",X"ED",X"88",X"12",X"BD",X"FC",X"60",X"BF",X"A1",X"8D",X"86",X"E6",X"8E",X"C4",X"12",X"7E", + X"F4",X"BE",X"CC",X"FF",X"50",X"BE",X"A1",X"8D",X"ED",X"88",X"10",X"BE",X"A1",X"89",X"ED",X"88", + X"10",X"86",X"A0",X"8E",X"C4",X"29",X"7E",X"F4",X"BE",X"8E",X"C5",X"F5",X"86",X"00",X"BD",X"D0", + X"55",X"BF",X"A1",X"87",X"86",X"15",X"8E",X"C4",X"75",X"7E",X"F4",X"BE",X"86",X"FF",X"97",X"BA", + X"BD",X"D8",X"05",X"BD",X"F5",X"D1",X"CC",X"00",X"00",X"DD",X"20",X"DD",X"22",X"BD",X"FF",X"CE", + X"F4",X"FA",X"00",X"BD",X"D7",X"F5",X"86",X"DB",X"97",X"BA",X"8E",X"10",X"30",X"9F",X"BF",X"39", + X"BE",X"A1",X"87",X"FE",X"A1",X"94",X"4F",X"A7",X"C4",X"33",X"C9",X"01",X"00",X"11",X"A3",X"07", + X"23",X"F5",X"7E",X"D0",X"15",X"8D",X"E9",X"BE",X"A1",X"8D",X"BD",X"D0",X"C7",X"BD",X"FC",X"63", + X"BE",X"A1",X"8B",X"CC",X"00",X"40",X"ED",X"0E",X"CC",X"00",X"D4",X"ED",X"88",X"10",X"86",X"2D", + X"B7",X"A1",X"8F",X"BE",X"A1",X"89",X"CC",X"00",X"00",X"ED",X"88",X"10",X"BE",X"A1",X"89",X"EC", + X"88",X"10",X"C3",X"00",X"08",X"ED",X"88",X"10",X"7A",X"A1",X"8F",X"27",X"08",X"86",X"02",X"8E", + X"C4",X"9C",X"7E",X"F4",X"BE",X"BD",X"D0",X"AD",X"CC",X"00",X"00",X"ED",X"0E",X"ED",X"88",X"10", + X"CC",X"1D",X"FF",X"ED",X"0A",X"CC",X"90",X"00",X"ED",X"0C",X"CC",X"F9",X"E7",X"ED",X"02",X"9F", + X"65",X"CC",X"00",X"00",X"ED",X"88",X"12",X"BF",X"A1",X"90",X"CC",X"00",X"00",X"CE",X"00",X"C0", + X"BE",X"A1",X"8B",X"ED",X"0E",X"EF",X"88",X"10",X"BE",X"A1",X"89",X"CC",X"1E",X"80",X"ED",X"0A", + X"CC",X"A2",X"E0",X"ED",X"0C",X"EF",X"88",X"10",X"86",X"50",X"8E",X"C5",X"00",X"7E",X"F4",X"BE", + X"BE",X"A1",X"90",X"CC",X"E0",X"00",X"ED",X"0C",X"CC",X"1C",X"00",X"ED",X"0A",X"BE",X"A1",X"89", + X"CC",X"00",X"00",X"ED",X"88",X"10",X"BE",X"A1",X"8B",X"CC",X"F9",X"CB",X"ED",X"02",X"CC",X"FF", + X"C0",X"ED",X"0E",X"CC",X"FE",X"80",X"ED",X"88",X"10",X"86",X"60",X"8E",X"C5",X"31",X"7E",X"F4", + X"BE",X"BE",X"A1",X"8B",X"CC",X"F9",X"C1",X"ED",X"02",X"CC",X"00",X"00",X"ED",X"0E",X"ED",X"88", + X"10",X"BE",X"A1",X"90",X"EC",X"04",X"BD",X"D0",X"C7",X"BD",X"D3",X"50",X"CE",X"CC",X"7D",X"BD", + X"D0",X"AD",X"EC",X"C9",X"00",X"0C",X"ED",X"02",X"EC",X"C9",X"00",X"24",X"ED",X"88",X"12",X"CC", + X"1F",X"00",X"ED",X"0A",X"CC",X"A0",X"00",X"ED",X"0C",X"CC",X"FF",X"40",X"ED",X"88",X"10",X"CC", + X"00",X"00",X"ED",X"0E",X"BD",X"FC",X"60",X"FF",X"A1",X"92",X"BF",X"A1",X"8D",X"86",X"5F",X"8E", + X"C5",X"85",X"7E",X"F4",X"BE",X"8E",X"C5",X"F5",X"86",X"00",X"BD",X"D0",X"55",X"BF",X"A1",X"87", + X"86",X"17",X"8E",X"C5",X"98",X"7E",X"F4",X"BE",X"BD",X"C4",X"60",X"BE",X"A1",X"8D",X"BD",X"D0", + X"C7",X"BD",X"D0",X"AD",X"BD",X"FC",X"63",X"FE",X"A1",X"92",X"EC",X"C9",X"00",X"18",X"ED",X"0A", + X"EC",X"C1",X"ED",X"0C",X"CC",X"00",X"00",X"ED",X"88",X"10",X"ED",X"0E",X"BD",X"FC",X"60",X"FF", + X"A1",X"92",X"86",X"20",X"8E",X"C5",X"CA",X"7E",X"F4",X"BE",X"BE",X"A1",X"96",X"30",X"02",X"BF", + X"A1",X"96",X"86",X"20",X"8E",X"C5",X"DA",X"7E",X"F4",X"BE",X"FE",X"A1",X"92",X"11",X"83",X"CC", + X"89",X"10",X"26",X"FF",X"6A",X"86",X"FF",X"8E",X"C5",X"ED",X"7E",X"F4",X"BE",X"86",X"FF",X"8E", + X"C6",X"77",X"7E",X"F4",X"BE",X"BE",X"A1",X"8B",X"AE",X"04",X"30",X"89",X"07",X"04",X"AF",X"47", + X"AF",X"49",X"BF",X"A1",X"94",X"86",X"04",X"AE",X"47",X"C6",X"11",X"E7",X"84",X"30",X"89",X"01", + X"00",X"4A",X"26",X"F7",X"C6",X"99",X"E7",X"84",X"AF",X"47",X"10",X"9E",X"A4",X"10",X"8C",X"A1", + X"5F",X"25",X"04",X"10",X"8E",X"A1",X"42",X"AE",X"49",X"86",X"03",X"E6",X"A0",X"E7",X"84",X"30", + X"89",X"01",X"00",X"4A",X"26",X"F5",X"10",X"9F",X"A4",X"AF",X"49",X"BE",X"A1",X"94",X"6F",X"84", + X"30",X"89",X"01",X"00",X"BF",X"A1",X"94",X"86",X"01",X"8E",X"C6",X"05",X"7E",X"F4",X"BE",X"10", + X"8E",X"CC",X"61",X"EE",X"A9",X"00",X"0E",X"AE",X"A1",X"BD",X"FF",X"CE",X"C0",X"02",X"02",X"10", + X"BF",X"A1",X"98",X"86",X"06",X"8E",X"C6",X"6B",X"7E",X"F4",X"BE",X"10",X"BE",X"A1",X"98",X"10", + X"BC",X"A1",X"96",X"26",X"DE",X"20",X"D8",X"BD",X"D0",X"7C",X"7F",X"A1",X"84",X"86",X"FB",X"97", + X"BA",X"BD",X"F5",X"D1",X"0F",X"52",X"CC",X"FF",X"FF",X"DD",X"59",X"8E",X"E7",X"82",X"86",X"00", + X"BD",X"D0",X"55",X"8E",X"F4",X"3D",X"86",X"00",X"BD",X"D0",X"55",X"86",X"3F",X"97",X"32",X"7E", + X"C6",X"A2",X"BD",X"C8",X"6F",X"86",X"03",X"B7",X"A1",X"6A",X"8E",X"C9",X"41",X"BF",X"A1",X"6B", + X"B6",X"A1",X"6A",X"B7",X"A1",X"63",X"10",X"BE",X"A1",X"6B",X"A6",X"A0",X"81",X"AA",X"23",X"0E", + X"43",X"27",X"F7",X"4A",X"26",X"4B",X"EC",X"A1",X"FD",X"A1",X"66",X"4F",X"20",X"18",X"48",X"24", + X"03",X"7A",X"A1",X"66",X"48",X"24",X"03",X"7C",X"A1",X"66",X"48",X"24",X"03",X"7A",X"A1",X"67", + X"48",X"24",X"03",X"7C",X"A1",X"67",X"B7",X"A1",X"62",X"FC",X"A1",X"66",X"44",X"1F",X"01",X"E6", + X"84",X"25",X"04",X"CA",X"F0",X"20",X"02",X"CA",X"0F",X"E7",X"84",X"B6",X"A1",X"62",X"26",X"CE", + X"7A",X"A1",X"63",X"26",X"B5",X"10",X"BF",X"A1",X"6B",X"86",X"02",X"8E",X"C6",X"B0",X"BD",X"F4", + X"BE",X"BF",X"A1",X"68",X"86",X"03",X"B1",X"A1",X"6A",X"26",X"0D",X"86",X"0A",X"B7",X"A1",X"6A", + X"8E",X"C7",X"30",X"86",X"00",X"BD",X"D0",X"55",X"8E",X"C9",X"41",X"BF",X"A1",X"6B",X"20",X"80", + X"8E",X"C7",X"4C",X"86",X"00",X"BD",X"D0",X"55",X"8E",X"32",X"58",X"CE",X"C0",X"ED",X"BD",X"FF", + X"CE",X"C0",X"02",X"02",X"86",X"05",X"8E",X"C7",X"38",X"BD",X"F4",X"BE",X"86",X"30",X"8E",X"C7", + X"54",X"7E",X"F4",X"BE",X"CC",X"B3",X"D6",X"FD",X"A1",X"6D",X"CC",X"B4",X"12",X"FD",X"A1",X"6F", + X"CC",X"00",X"00",X"DD",X"20",X"CC",X"0C",X"00",X"FD",X"A1",X"71",X"CC",X"B3",X"04",X"FD",X"A1", + X"73",X"BE",X"A1",X"73",X"10",X"BE",X"A1",X"6D",X"CC",X"04",X"0C",X"ED",X"A4",X"FC",X"A1",X"6F", + X"ED",X"22",X"C3",X"00",X"60",X"FD",X"A1",X"6F",X"10",X"AF",X"02",X"FC",X"A1",X"71",X"ED",X"0A", + X"C3",X"01",X"00",X"FD",X"A1",X"71",X"CC",X"98",X"00",X"ED",X"0C",X"BD",X"FC",X"60",X"30",X"0E", + X"BF",X"A1",X"73",X"31",X"24",X"10",X"BF",X"A1",X"6D",X"10",X"8C",X"B4",X"12",X"26",X"C2",X"86", + X"2E",X"8E",X"C7",X"B7",X"7E",X"F4",X"BE",X"8E",X"B3",X"00",X"CC",X"3C",X"18",X"ED",X"84",X"CC", + X"B4",X"12",X"ED",X"02",X"8E",X"C8",X"48",X"86",X"00",X"BD",X"D0",X"55",X"86",X"28",X"8E",X"C7", + X"D4",X"7E",X"F4",X"BE",X"8E",X"F4",X"64",X"86",X"00",X"BD",X"D0",X"55",X"FE",X"A1",X"68",X"10", + X"8E",X"CC",X"11",X"8E",X"3B",X"D0",X"EC",X"A1",X"FD",X"A1",X"64",X"86",X"01",X"5F",X"B5",X"A1", + X"64",X"27",X"02",X"C6",X"10",X"B5",X"A1",X"65",X"27",X"02",X"CA",X"01",X"E7",X"80",X"48",X"26", + X"EC",X"30",X"89",X"00",X"F8",X"10",X"8C",X"CC",X"61",X"26",X"DB",X"8E",X"A0",X"26",X"F6",X"C6", + X"F8",X"A6",X"85",X"43",X"84",X"07",X"26",X"08",X"8E",X"80",X"18",X"CC",X"20",X"A0",X"EF",X"8B", + X"86",X"01",X"97",X"B7",X"8E",X"C8",X"F4",X"86",X"00",X"BD",X"D0",X"55",X"86",X"3C",X"B7",X"A1", + X"7D",X"7D",X"A1",X"84",X"10",X"26",X"FB",X"19",X"7A",X"A1",X"7D",X"27",X"08",X"86",X"0A",X"8E", + X"C8",X"31",X"7E",X"F4",X"BE",X"7E",X"C2",X"63",X"10",X"8E",X"B3",X"00",X"CC",X"30",X"90",X"BD", + X"F5",X"22",X"7D",X"9C",X"00",X"26",X"10",X"7D",X"9C",X"40",X"26",X"0B",X"8E",X"C9",X"21",X"86", + X"00",X"BD",X"D0",X"55",X"7E",X"D0",X"0A",X"86",X"01",X"8E",X"C8",X"48",X"7E",X"F4",X"BE",X"8E", + X"B4",X"12",X"10",X"8E",X"CA",X"A0",X"4F",X"B7",X"A1",X"77",X"B7",X"A1",X"76",X"A6",X"A4",X"44", + X"44",X"44",X"44",X"8D",X"0C",X"A6",X"A0",X"84",X"0F",X"8D",X"06",X"10",X"8C",X"CC",X"0E",X"26", + X"EC",X"85",X"0C",X"26",X"09",X"BB",X"A1",X"76",X"48",X"48",X"B7",X"A1",X"76",X"39",X"34",X"02", + X"84",X"03",X"BB",X"A1",X"76",X"B7",X"A1",X"76",X"35",X"02",X"84",X"0C",X"44",X"44",X"CE",X"CC", + X"0D",X"E6",X"C6",X"F7",X"A1",X"75",X"8C",X"B9",X"B2",X"25",X"04",X"30",X"89",X"FA",X"61",X"B6", + X"A1",X"77",X"27",X"14",X"A6",X"84",X"84",X"F0",X"A7",X"84",X"B6",X"A1",X"75",X"84",X"0F",X"AA", + X"84",X"A7",X"84",X"B6",X"A1",X"75",X"20",X"0D",X"73",X"A1",X"77",X"B6",X"A1",X"75",X"A7",X"84", + X"7A",X"A1",X"76",X"2B",X"0B",X"30",X"88",X"18",X"7A",X"A1",X"76",X"2A",X"F1",X"7F",X"A1",X"77", + X"7F",X"A1",X"76",X"39",X"D6",X"37",X"27",X"21",X"F1",X"A1",X"83",X"23",X"06",X"F7",X"A1",X"83", + X"7C",X"A1",X"84",X"CE",X"C0",X"E9",X"8E",X"28",X"E5",X"BD",X"FF",X"CE",X"C0",X"02",X"02",X"4F", + X"8E",X"48",X"E5",X"BD",X"FF",X"CE",X"C0",X"0E",X"02",X"86",X"10",X"8E",X"C8",X"F4",X"7E",X"F4", + X"BE",X"86",X"FF",X"B7",X"A1",X"6A",X"86",X"02",X"8E",X"C9",X"2E",X"7E",X"F4",X"BE",X"86",X"0A", + X"B7",X"A1",X"6A",X"7E",X"D0",X"0A",X"96",X"8C",X"27",X"06",X"BD",X"D3",X"DB",X"4A",X"20",X"F8", + X"39",X"FE",X"74",X"40",X"11",X"11",X"85",X"81",X"81",X"81",X"88",X"82",X"82",X"22",X"24",X"22", + X"42",X"24",X"24",X"24",X"44",X"24",X"44",X"49",X"44",X"94",X"41",X"88",X"14",X"41",X"88",X"14", + X"41",X"88",X"94",X"41",X"88",X"94",X"49",X"88",X"14",X"98",X"58",X"94",X"98",X"18",X"94",X"46", + X"66",X"62",X"42",X"42",X"42",X"42",X"25",X"24",X"24",X"68",X"24",X"24",X"24",X"26",X"11",X"18", + X"18",X"58",X"18",X"58",X"81",X"44",X"98",X"81",X"44",X"98",X"81",X"44",X"98",X"14",X"94",X"94", + X"16",X"22",X"24",X"24",X"A4",X"24",X"A4",X"24",X"24",X"24",X"24",X"24",X"FE",X"81",X"4A",X"42", + X"42",X"42",X"42",X"44",X"99",X"99",X"41",X"88",X"14",X"41",X"88",X"14",X"46",X"24",X"24",X"24", + X"24",X"24",X"24",X"A4",X"24",X"24",X"A4",X"22",X"42",X"4A",X"42",X"42",X"44",X"99",X"19",X"91", + X"19",X"91",X"91",X"81",X"81",X"41",X"81",X"49",X"46",X"42",X"42",X"42",X"42",X"42",X"42",X"24", + X"22",X"42",X"62",X"62",X"42",X"24",X"49",X"19",X"91",X"91",X"91",X"91",X"91",X"85",X"88",X"14", + X"94",X"14",X"24",X"24",X"24",X"24",X"24",X"24",X"A4",X"24",X"24",X"41",X"81",X"81",X"18",X"18", + X"94",X"41",X"88",X"14",X"14",X"24",X"42",X"24",X"24",X"24",X"24",X"24",X"24",X"24",X"44",X"98", + X"18",X"18",X"18",X"58",X"89",X"44",X"18",X"85",X"14",X"24",X"14",X"24",X"A4",X"24",X"24",X"24", + X"A4",X"24",X"28",X"24",X"44",X"18",X"19",X"19",X"81",X"41",X"81",X"14",X"24",X"24",X"24",X"24", + X"22",X"42",X"42",X"64",X"41",X"85",X"81",X"81",X"18",X"19",X"41",X"89",X"44",X"42",X"22",X"42", + X"24",X"24",X"24",X"24",X"24",X"44",X"18",X"14",X"98",X"11",X"81",X"81",X"41",X"89",X"44",X"42", + X"22",X"42",X"24",X"24",X"24",X"24",X"24",X"44",X"18",X"94",X"41",X"88",X"89",X"44",X"49",X"88", + X"14",X"41",X"88",X"14",X"14",X"24",X"24",X"24",X"26",X"62",X"66",X"26",X"24",X"18",X"91",X"91", + X"19",X"18",X"14",X"18",X"14",X"14",X"24",X"14",X"2A",X"45",X"24",X"68",X"88",X"24",X"44",X"42", + X"18",X"A8",X"82",X"44",X"A8",X"22",X"20",X"FE",X"87",X"40",X"44",X"11",X"88",X"24",X"FE",X"9A", + X"3F",X"44",X"11",X"88",X"24",X"FE",X"C1",X"3F",X"44",X"44",X"44",X"11",X"11",X"11",X"11",X"88", + X"88",X"88",X"22",X"22",X"22",X"20",X"FE",X"C3",X"45",X"22",X"22",X"44",X"11",X"81",X"50",X"FD", + X"10",X"D1",X"BD",X"29",X"C2",X"9C",X"29",X"CB",X"EA",X"C2",X"8C",X"29",X"C2",X"81",X"0D",X"10", + X"C2",X"8D",X"29",X"C2",X"9C",X"29",X"CB",X"EA",X"42",X"94",X"29",X"42",X"81",X"0C",X"3F",X"29", + X"C2",X"94",X"C2",X"9C",X"29",X"C1",X"8D",X"A4",X"29",X"42",X"94",X"29",X"3F",X"3E",X"29",X"42", + X"A4",X"29",X"4C",X"29",X"C1",X"8D",X"A4",X"2A",X"42",X"94",X"29",X"3E",X"3D",X"B6",X"B4",X"A2", + X"4A",X"17",X"CA",X"16",X"C1",X"9C",X"B4",X"A7",X"A4",X"B1",X"7A",X"7A",X"3D",X"3C",X"B6",X"B4", + X"B1",X"71",X"81",X"6B",X"16",X"C1",X"AC",X"A4",X"B6",X"B4",X"A2",X"4A",X"6B",X"3C",X"2F",X"B6", + X"B4",X"29",X"62",X"85",X"C2",X"85",X"C1",X"AC",X"A4",X"B6",X"B4",X"28",X"62",X"A2",X"F2",X"EB", + X"61",X"84",X"29",X"62",X"8E",X"28",X"E2",X"A4",X"B7",X"B4",X"28",X"62",X"A2",X"E2",X"DB",X"7B", + X"42",X"96",X"28",X"4E",X"28",X"E2",X"B4",X"B6",X"B4",X"29",X"62",X"92",X"E2",X"CB",X"7B",X"52", + X"96",X"28",X"4E",X"28",X"EB",X"41",X"A4",X"B7",X"B4",X"28",X"62",X"92",X"E1",X"FB",X"7B",X"5B", + X"24",X"B1",X"6D",X"18",X"14",X"EB",X"51",X"94",X"B7",X"B4",X"18",X"17",X"29",X"2D",X"1E",X"B1", + X"4B",X"4B",X"25",X"B1",X"6D",X"B1",X"5E",X"B5",X"1A",X"4B",X"61",X"84",X"B2",X"4B",X"41",X"82", + X"C1",X"DB",X"14",X"B5",X"18",X"17",X"18",X"16",X"D1",X"81",X"4E",X"B6",X"19",X"4B",X"61",X"84", + X"18",X"24",X"B4",X"18",X"1F",X"1C",X"38",X"53",X"84",X"B1",X"6E",X"2B",X"CB",X"61",X"94",X"38", + X"42",X"B4",X"18",X"41",X"81",X"EF",X"39",X"43",X"85",X"B1",X"6E",X"2B",X"CB",X"71",X"84",X"38", + X"43",X"84",X"B6",X"18",X"1C",X"E3",X"95",X"38",X"41",X"81",X"6D",X"38",X"CB",X"C6",X"19",X"42", + X"B5",X"38",X"4B",X"61",X"8F",X"D3",X"95",X"38",X"5B",X"51",X"F3",X"8C",X"BD",X"61",X"84",X"2A", + X"63",X"85",X"B6",X"18",X"ED",X"38",X"53",X"94",X"18",X"51",X"F3",X"8C",X"BD",X"7B",X"42",X"91", + X"42",X"B5",X"18",X"7B",X"DC",X"21",X"51",X"F3",X"4C",X"7E",X"30",X"6C",X"C2",X"14",X"2C",X"34", + X"C7",X"E1",X"07",X"C1",X"35",X"CC",X"21",X"42",X"C3",X"4C",X"7F",X"10",X"6C",X"13",X"5C",X"C1", + X"35",X"C1",X"52",X"C3",X"4C",X"7F",X"15",X"C2",X"7D",X"34",X"C1",X"5C",X"17",X"CC",X"36",X"C3", + X"5C",X"14",X"2D",X"34",X"C7",X"1C",X"14",X"C2",X"6E",X"34",X"D1",X"4E",X"15",X"CC",X"36",X"C3", + X"5C",X"14",X"2D",X"34",X"C7",X"1C",X"14",X"C2",X"51",X"C2",X"7D",X"14",X"F1",X"4C",X"22",X"CC", + X"00",X"3E",X"41",X"41",X"22",X"00",X"3E",X"41",X"41",X"3E",X"00",X"7F",X"09",X"09",X"06",X"00", + X"03",X"04",X"78",X"04",X"03",X"00",X"7F",X"09",X"19",X"66",X"00",X"41",X"7F",X"41",X"00",X"3E", + X"41",X"49",X"3A",X"00",X"7F",X"08",X"08",X"7F",X"00",X"01",X"01",X"7F",X"01",X"01",X"00",X"1C", + X"22",X"5D",X"63",X"55",X"22",X"1C",X"22",X"7F",X"4B",X"45",X"22",X"1C",X"00",X"00",X"00",X"42", + X"7F",X"40",X"00",X"26",X"49",X"49",X"3E",X"00",X"36",X"49",X"49",X"36",X"00",X"3E",X"41",X"41", + X"3E",X"43",X"30",X"1C",X"70",X"3C",X"70",X"5F",X"70",X"1C",X"A8",X"40",X"A8",X"5C",X"A8",X"C0", + X"EB",X"C0",X"DD",X"C0",X"DF",X"C0",X"E7",X"C0",X"E3",X"C0",X"E1",X"C0",X"E5",X"60",X"00",X"60", + X"00",X"62",X"00",X"98",X"00",X"98",X"00",X"9A",X"00",X"F9",X"85",X"F8",X"CE",X"F9",X"A3",X"F9", + X"29",X"F8",X"F7",X"F9",X"7B",X"09",X"00",X"11",X"00",X"19",X"80",X"09",X"60",X"11",X"60",X"19", + X"E0",X"44",X"33",X"CC",X"33",X"33",X"33",X"88",X"88",X"CC",X"CC",X"24",X"24",X"CE",X"00",X"00", + X"C6",X"08",X"8E",X"B0",X"5D",X"EF",X"94",X"EF",X"98",X"02",X"EF",X"98",X"04",X"EF",X"98",X"06", + X"3A",X"9C",X"97",X"25",X"F0",X"AE",X"9F",X"A0",X"97",X"27",X"08",X"EF",X"84",X"6F",X"02",X"EF", + X"89",X"FF",X"00",X"DC",X"20",X"83",X"6D",X"40",X"DD",X"73",X"44",X"44",X"CE",X"CD",X"69",X"C6", + X"03",X"3D",X"33",X"CB",X"96",X"BA",X"85",X"02",X"26",X"22",X"86",X"30",X"10",X"8E",X"B1",X"25", + X"8E",X"00",X"00",X"AF",X"B4",X"37",X"14",X"ED",X"A4",X"AF",X"B1",X"4C",X"8E",X"00",X"00",X"AF", + X"B4",X"37",X"14",X"ED",X"A4",X"AF",X"B1",X"4C",X"81",X"70",X"26",X"E4",X"8E",X"4C",X"09",X"CC", + X"90",X"90",X"ED",X"84",X"ED",X"88",X"1D",X"8E",X"53",X"09",X"CC",X"09",X"09",X"ED",X"84",X"ED", + X"88",X"1D",X"8E",X"A0",X"65",X"CE",X"B0",X"5D",X"8D",X"3A",X"8E",X"A0",X"6B",X"8D",X"35",X"DF", + X"97",X"DC",X"BF",X"44",X"44",X"44",X"44",X"54",X"54",X"54",X"C3",X"4B",X"07",X"ED",X"C4",X"AE", + X"C4",X"CC",X"90",X"99",X"ED",X"84",X"A7",X"02",X"86",X"09",X"A7",X"89",X"FF",X"01",X"39",X"EC", + X"0A",X"93",X"73",X"44",X"44",X"E6",X"0C",X"54",X"54",X"54",X"C3",X"30",X"07",X"ED",X"C4",X"EC", + X"88",X"12",X"ED",X"D1",X"AE",X"84",X"26",X"E7",X"39",X"25",X"70",X"07",X"26",X"77",X"00",X"26", + X"07",X"70",X"24",X"07",X"70",X"23",X"07",X"70",X"23",X"70",X"07",X"24",X"07",X"70",X"25",X"70", + X"07",X"26",X"77",X"00",X"25",X"07",X"70",X"24",X"07",X"70",X"23",X"07",X"70",X"21",X"07",X"70", + X"22",X"70",X"07",X"24",X"77",X"00",X"24",X"70",X"07",X"26",X"77",X"00",X"26",X"77",X"00",X"25", + X"77",X"00",X"25",X"70",X"07",X"26",X"77",X"00",X"24",X"07",X"70",X"23",X"70",X"07",X"25",X"77", + X"00",X"26",X"70",X"07",X"26",X"77",X"00",X"26",X"77",X"00",X"25",X"07",X"70",X"23",X"07",X"70", + X"22",X"07",X"70",X"21",X"77",X"00",X"21",X"70",X"07",X"23",X"70",X"07",X"25",X"70",X"07",X"25", + X"07",X"70",X"25",X"77",X"00",X"25",X"77",X"00",X"24",X"77",X"00",X"22",X"07",X"70",X"20",X"07", + X"70",X"1E",X"07",X"70",X"1C",X"07",X"70",X"1D",X"70",X"07",X"1F",X"70",X"07",X"21",X"70",X"07", + X"22",X"70",X"07",X"24",X"70",X"07",X"26",X"70",X"07",X"26",X"77",X"00",X"26",X"77",X"00",X"26", + X"77",X"00",X"26",X"77",X"00",X"26",X"77",X"00",X"25",X"77",X"00",X"25",X"70",X"07",X"26",X"77", + X"00",X"24",X"07",X"70",X"23",X"77",X"00",X"24",X"77",X"00",X"22",X"07",X"70",X"23",X"70",X"07", + X"22",X"07",X"70",X"21",X"70",X"07",X"23",X"70",X"07",X"25",X"70",X"07",X"26",X"77",X"00",X"26", + X"07",X"70",X"24",X"07",X"70",X"23",X"07",X"70",X"23",X"70",X"07",X"24",X"07",X"70",X"25",X"70", + X"07",X"26",X"77",X"00",X"25",X"07",X"70",X"24",X"07",X"70",X"23",X"07",X"70",X"21",X"07",X"70", + X"22",X"70",X"07",X"24",X"77",X"00",X"24",X"70",X"07",X"26",X"77",X"00",X"26",X"77",X"00",X"25", + X"77",X"00",X"25",X"70",X"07",X"26",X"77",X"00",X"24",X"07",X"70",X"23",X"70",X"07",X"25",X"77", + X"00",X"26",X"70",X"07",X"26",X"77",X"00",X"26",X"77",X"00",X"25",X"07",X"70",X"23",X"07",X"70", + X"22",X"07",X"70",X"21",X"77",X"00",X"21",X"70",X"07",X"23",X"70",X"07",X"25",X"70",X"07",X"25", + X"07",X"70",X"25",X"77",X"00",X"25",X"77",X"00",X"24",X"77",X"00",X"22",X"07",X"70",X"20",X"07", + X"70",X"1E",X"07",X"70",X"1C",X"07",X"70",X"1D",X"70",X"07",X"1F",X"70",X"07",X"21",X"70",X"07", + X"22",X"70",X"07",X"24",X"70",X"07",X"26",X"70",X"07",X"26",X"77",X"00",X"26",X"77",X"00",X"26", + X"77",X"00",X"26",X"77",X"00",X"26",X"77",X"00",X"25",X"77",X"00",X"25",X"70",X"07",X"26",X"77", + X"00",X"24",X"07",X"70",X"23",X"77",X"00",X"24",X"77",X"00",X"22",X"07",X"70",X"23",X"70",X"07", + X"22",X"07",X"70",X"21",X"70",X"07",X"23",X"70",X"07",X"80",X"00",X"00",X"30",X"00",X"30",X"00", + X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"96",X"00",X"00",X"00",X"00",X"FE", + X"C3",X"00",X"00",X"00",X"00",X"D6",X"66",X"00",X"00",X"00",X"00",X"66",X"66",X"39",X"00",X"06", + X"66",X"66",X"88",X"68",X"66",X"66",X"66",X"88",X"88",X"88",X"00",X"60",X"63",X"30",X"63",X"00", + X"06",X"26",X"68",X"28",X"60",X"66",X"66",X"86",X"00",X"00",X"66",X"66",X"00",X"00",X"ED",X"66", + X"00",X"00",X"00",X"63",X"90",X"09",X"90",X"99",X"99",X"99",X"90",X"CC",X"90",X"11",X"00",X"11", + X"10",X"11",X"00",X"10",X"10",X"10",X"00",X"10",X"00",X"11",X"10",X"11",X"00",X"11",X"00",X"10", + X"00",X"10",X"10",X"10",X"00",X"11",X"10",X"10",X"10",X"11",X"00",X"10",X"10",X"10",X"10",X"10", + X"00",X"01",X"00",X"01",X"01",X"01",X"00",X"11",X"01",X"11",X"00",X"11",X"00",X"01",X"01",X"01", + X"00",X"01",X"00",X"11",X"00",X"11",X"01",X"11",X"00",X"01",X"01",X"01",X"01",X"01",X"00",X"11", + X"01",X"01",X"01",X"11",X"00",X"FF",X"F0",X"FF",X"00",X"FF",X"00",X"F0",X"00",X"F0",X"F0",X"F0", + X"00",X"EE",X"E0",X"E0",X"E0",X"EE",X"00",X"E0",X"E0",X"E0",X"E0",X"E0",X"00",X"DD",X"D0",X"D0", + X"D0",X"DD",X"00",X"D0",X"D0",X"D0",X"D0",X"D0",X"00",X"0F",X"0F",X"0F",X"00",X"0F",X"00",X"FF", + X"00",X"FF",X"0F",X"FF",X"00",X"0E",X"0E",X"0E",X"0E",X"0E",X"00",X"EE",X"0E",X"0E",X"0E",X"EE", + X"00",X"0D",X"0D",X"0D",X"0D",X"0D",X"00",X"DD",X"0D",X"0D",X"0D",X"DD",X"00",X"1C",X"0D",X"7F", + X"E7",X"70",X"00",X"0F",X"71",X"71",X"07",X"DC",X"77",X"7C",X"0D",X"71",X"C7",X"77",X"DE",X"07", + X"71",X"17",X"17",X"DE",X"F7",X"71",X"17",X"71",X"7C",X"DE",X"F0",X"07",X"77",X"C7",X"71",X"17", + X"70",X"70",X"7C",X"D7",X"77",X"77",X"70",X"01",X"CD",X"FF",X"D7",X"70",X"F0",X"00",X"00",X"00", + X"C5",X"FB",X"7E",X"CA",X"A7",X"7E",X"CA",X"B2",X"7E",X"CA",X"BD",X"7E",X"CA",X"C8",X"7E",X"CB", + X"C1",X"7E",X"CB",X"CC",X"7E",X"CB",X"D7",X"7E",X"CB",X"E2",X"7E",X"CA",X"79",X"7E",X"CA",X"81", + X"7E",X"CA",X"51",X"7E",X"CA",X"58",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"5B", + X"FF",X"C0",X"BD",X"C0",X"BF",X"C0",X"C1",X"00",X"00",X"C0",X"C1",X"00",X"00",X"C0",X"C3",X"00", + X"00",X"C0",X"C5",X"00",X"00",X"C0",X"C5",X"00",X"00",X"C0",X"C7",X"00",X"00",X"C0",X"C3",X"00", + X"00",X"C0",X"C9",X"00",X"00",X"C0",X"CB",X"C0",X"CD",X"C0",X"CF",X"00",X"00",X"C0",X"BD",X"C0", + X"D1",X"C0",X"D3",X"C0",X"D5",X"C0",X"DB",X"00",X"00",X"C1",X"07",X"C1",X"0D",X"C1",X"11",X"C1", + X"13",X"C1",X"15",X"C1",X"19",X"C1",X"1D",X"C1",X"21",X"C1",X"27",X"C1",X"2B",X"C1",X"33",X"C1", + X"4D",X"C1",X"53",X"C1",X"6D",X"C1",X"88",X"C1",X"92",X"C1",X"96",X"C1",X"9C",X"C1",X"A0",X"C1", + X"A2",X"C1",X"A6",X"C1",X"A8",X"C1",X"AC",X"C1",X"B0",X"C1",X"B2",X"C1",X"B4",X"C1",X"B6",X"C1", + X"B8",X"C1",X"BC",X"C1",X"BE",X"C1",X"C2",X"C1",X"C6",X"C1",X"C8",X"C1",X"CA",X"C1",X"CC",X"C1", + X"CE",X"C1",X"D0",X"C1",X"D2",X"C1",X"D4",X"C1",X"D6",X"C1",X"D8",X"C1",X"DA",X"C1",X"EA",X"C1", + X"F8",X"C2",X"00",X"C2",X"08",X"C2",X"10",X"C2",X"1A",X"C2",X"24",X"C2",X"2C",X"C2",X"34",X"C2", + X"3E",X"C2",X"48",X"C2",X"52",X"C2",X"5A",X"C2",X"64",X"C2",X"68",X"C2",X"74",X"C2",X"7E",X"C2", + X"85",X"C2",X"8C",X"C2",X"93",X"C2",X"9A",X"C2",X"A1",X"C2",X"A8",X"C2",X"AA",X"C2",X"AC",X"C2", + X"B4",X"C2",X"B8",X"C2",X"BC",X"C2",X"BE",X"C2",X"C6",X"C2",X"D2",X"C2",X"D6",X"C2",X"D8",X"C3", + X"01",X"C3",X"0B",X"C3",X"21",X"C3",X"2B",X"C4",X"64",X"C5",X"8D",X"C4",X"50",X"C5",X"BB",X"C4", + X"D1",X"C5",X"2D",X"C5",X"1B",X"C5",X"2D",X"C4",X"04",X"C5",X"1B",X"C4",X"04",X"C4",X"15",X"C4", + X"E0",X"C3",X"3E",X"C5",X"31",X"C4",X"D1",X"C5",X"1B",X"C5",X"81",X"C4",X"CA",X"C5",X"1B",X"C3", + X"F8",X"C3",X"C6",X"C3",X"93",X"C5",X"1B",X"C4",X"04",X"06",X"28",X"A0",X"C5",X"81",X"C4",X"AD", + X"C3",X"66",X"C3",X"F0",X"07",X"C5",X"DA",X"C3",X"98",X"C3",X"CF",X"C4",X"D8",X"C3",X"93",X"C5", + X"1B",X"C4",X"D1",X"C4",X"A4",X"C5",X"1B",X"C4",X"04",X"03",X"FE",X"C3",X"81",X"04",X"10",X"02", + X"F8",X"C3",X"93",X"C5",X"1B",X"C3",X"7D",X"C4",X"CD",X"C3",X"66",X"C5",X"86",X"C3",X"9D",X"C5", + X"1B",X"C5",X"81",X"04",X"30",X"02",X"E8",X"C5",X"C3",X"C3",X"9D",X"C3",X"61",X"C4",X"50",X"07", + X"03",X"FC",X"C3",X"9D",X"C5",X"1B",X"C4",X"04",X"C3",X"49",X"C5",X"81",X"07",X"07",X"03",X"04", + X"C5",X"54",X"C5",X"7A",X"C5",X"81",X"C4",X"9C",X"C5",X"81",X"C4",X"E5",X"C3",X"55",X"C5",X"C0", + X"C3",X"36",X"C5",X"27",X"C3",X"98",X"C4",X"35",X"C4",X"8B",X"C3",X"98",X"C3",X"85",X"C3",X"98", + X"C4",X"75",X"C4",X"75",X"C4",X"0C",X"C5",X"9C",X"C5",X"4E",X"C3",X"69",X"C4",X"45",X"C5",X"B7", + X"C4",X"F5",X"C4",X"D4",X"C4",X"EE",X"C5",X"1F",X"C3",X"D4",X"C5",X"C0",X"C4",X"75",X"C4",X"75", + X"C4",X"75",X"C4",X"75",X"C4",X"75",X"C4",X"75",X"C4",X"75",X"C5",X"0B",X"C3",X"36",X"C5",X"DA", + X"C5",X"7A",X"C5",X"45",X"C4",X"11",X"03",X"FE",X"C3",X"83",X"C3",X"55",X"C4",X"11",X"C3",X"4F", + X"03",X"FE",X"C3",X"81",X"C4",X"15",X"C3",X"2B",X"C4",X"95",X"C4",X"11",X"C5",X"2D",X"C5",X"81", + X"C3",X"55",X"C4",X"11",X"C5",X"1B",X"C5",X"81",X"C3",X"55",X"C5",X"AD",X"C3",X"FF",X"C5",X"81", + X"C3",X"55",X"C4",X"11",X"C3",X"93",X"C5",X"1B",X"C5",X"81",X"C3",X"55",X"C4",X"11",X"C3",X"9D", + X"C5",X"1B",X"C5",X"81",X"C3",X"55",X"C4",X"11",X"C3",X"49",X"C5",X"81",X"C3",X"55",X"C4",X"11", + X"C5",X"7A",X"C5",X"81",X"C4",X"95",X"C5",X"AD",X"C5",X"81",X"C4",X"59",X"C5",X"5A",X"C3",X"55", + X"C4",X"11",X"C4",X"9C",X"C5",X"81",X"C4",X"E5",X"C4",X"95",X"C5",X"AD",X"C5",X"67",X"C5",X"97", + X"C4",X"E5",X"C3",X"55",X"C4",X"11",X"C4",X"15",X"C4",X"E0",X"C4",X"95",X"C5",X"AD",X"C5",X"67", + X"C5",X"97",X"C3",X"2B",X"C5",X"D1",X"C3",X"BD",X"C5",X"0B",X"C3",X"36",X"C5",X"AD",X"C5",X"67", + X"C5",X"97",X"C5",X"81",X"C5",X"0B",X"C4",X"35",X"C5",X"AD",X"C4",X"90",X"C3",X"8C",X"C4",X"84", + X"07",X"03",X"06",X"C4",X"B9",X"C4",X"B2",X"07",X"03",X"06",X"C4",X"B9",X"C4",X"FD",X"07",X"03", + X"00",X"C4",X"C5",X"C3",X"6E",X"07",X"03",X"06",X"C4",X"C1",X"C5",X"72",X"07",X"03",X"08",X"C4", + X"B9",X"C3",X"5A",X"07",X"03",X"06",X"C4",X"BD",X"C3",X"B4",X"C5",X"36",X"C3",X"D9",X"07",X"07", + X"03",X"0C",X"C5",X"02",X"C4",X"EE",X"C4",X"D4",X"C4",X"EE",X"C5",X"B7",X"C3",X"75",X"C5",X"0B", + X"C4",X"D4",X"C4",X"EE",X"C5",X"61",X"C5",X"0B",X"C4",X"D4",X"C4",X"DD",X"C5",X"B7",X"C4",X"EE", + X"C5",X"61",X"C3",X"42",X"C5",X"CC",X"C3",X"A3",X"C5",X"DF",X"C4",X"30",X"C5",X"11",X"C4",X"11", + X"07",X"C5",X"93",X"C3",X"BD",X"C4",X"23",X"07",X"07",X"C5",X"3E",X"C4",X"6C",X"C5",X"DA",X"C5", + X"C0",X"C3",X"D4",X"C5",X"6C",X"07",X"07",X"C5",X"0B",X"C4",X"0C",X"C5",X"AD",X"C3",X"EA",X"C4", + X"64",X"A0",X"00",X"02",X"08",X"A0",X"02",X"02",X"10",X"A0",X"04",X"C4",X"23",X"06",X"22",X"68", + X"C5",X"B0",X"02",X"3E",X"C3",X"3E",X"C5",X"A8",X"07",X"03",X"FC",X"C4",X"1A",X"02",X"3D",X"C4", + X"1A",X"A0",X"06",X"02",X"05",X"A0",X"08",X"02",X"13",X"A0",X"0C",X"41",X"44",X"4A",X"55",X"53", + X"54",X"4D",X"45",X"4E",X"54",X"2F",X"41",X"44",X"56",X"41",X"4E",X"43",X"45",X"2F",X"41",X"4C", + X"4C",X"2F",X"41",X"54",X"54",X"41",X"43",X"4B",X"2F",X"41",X"55",X"44",X"49",X"4F",X"2F",X"41", + X"55",X"44",X"49",X"54",X"2F",X"41",X"55",X"54",X"4F",X"2F",X"42",X"41",X"49",X"54",X"45",X"52", + X"2F",X"42",X"41",X"52",X"53",X"2F",X"42",X"45",X"2F",X"42",X"4F",X"4D",X"42",X"2F",X"42",X"4F", + X"4D",X"42",X"45",X"52",X"2F",X"42",X"4F",X"4E",X"55",X"53",X"20",X"58",X"2F",X"43",X"41",X"4E", + X"2F",X"2C",X"2F",X"3A",X"2F",X"43",X"45",X"4E",X"54",X"45",X"52",X"2F",X"43",X"48",X"41",X"4E", + X"47",X"45",X"2F",X"43",X"4D",X"4F",X"53",X"2F",X"43",X"4F",X"49",X"4E",X"2F",X"43",X"4F",X"4C", + X"4F",X"52",X"2F",X"43",X"4F",X"4D",X"50",X"4C",X"45",X"54",X"45",X"44",X"2F",X"43",X"52",X"45", + X"44",X"49",X"54",X"2F",X"43",X"52",X"45",X"44",X"49",X"54",X"53",X"3A",X"2F",X"44",X"45",X"46", + X"45",X"4E",X"44",X"45",X"52",X"2F",X"44",X"45",X"54",X"45",X"43",X"54",X"45",X"44",X"2F",X"44", + X"4F",X"4F",X"52",X"2F",X"44",X"4F",X"57",X"4E",X"2F",X"45",X"4C",X"45",X"43",X"54",X"52",X"4F", + X"4E",X"49",X"43",X"53",X"20",X"49",X"4E",X"43",X"2E",X"2F",X"45",X"4E",X"54",X"45",X"52",X"2F", + X"45",X"4E",X"54",X"45",X"52",X"45",X"44",X"2F",X"45",X"52",X"52",X"4F",X"52",X"53",X"2F",X"45", + X"58",X"49",X"54",X"2F",X"46",X"41",X"49",X"4C",X"55",X"52",X"45",X"2F",X"46",X"49",X"52",X"45", + X"2F",X"46",X"4F",X"52",X"2F",X"47",X"41",X"4D",X"45",X"2F",X"47",X"52",X"45",X"41",X"54",X"45", + X"53",X"54",X"2F",X"48",X"41",X"4C",X"4C",X"20",X"4F",X"46",X"20",X"46",X"41",X"4D",X"45",X"2F", + X"48",X"41",X"56",X"45",X"2F",X"48",X"49",X"47",X"48",X"53",X"43",X"4F",X"52",X"45",X"20",X"52", + X"45",X"53",X"45",X"54",X"2F",X"48",X"59",X"50",X"45",X"52",X"53",X"50",X"41",X"43",X"45",X"2F", + X"49",X"4E",X"44",X"49",X"43",X"41",X"54",X"45",X"2F",X"49",X"4E",X"44",X"49",X"56",X"49",X"44", + X"55",X"41",X"4C",X"2F",X"49",X"4E",X"49",X"54",X"49",X"41",X"4C",X"2F",X"49",X"4E",X"49",X"54", + X"49",X"41",X"4C",X"53",X"2F",X"49",X"4E",X"56",X"41",X"4C",X"49",X"44",X"20",X"53",X"57",X"49", + X"54",X"43",X"48",X"2F",X"4C",X"41",X"4E",X"44",X"45",X"52",X"2F",X"4C",X"45",X"46",X"54",X"2F", + X"4D",X"41",X"4B",X"45",X"2F",X"4D",X"41",X"4E",X"55",X"41",X"4C",X"2F",X"4D",X"4F",X"4E",X"49", + X"54",X"4F",X"52",X"2F",X"4D",X"55",X"4C",X"54",X"49",X"50",X"4C",X"45",X"2F",X"4D",X"55",X"53", + X"54",X"2F",X"4D",X"55",X"54",X"41",X"4E",X"54",X"2F",X"31",X"35",X"30",X"2F",X"32",X"30",X"30", + X"2F",X"32",X"35",X"30",X"2F",X"31",X"30",X"30",X"30",X"2F",X"4E",X"4F",X"2F",X"4E",X"4F",X"54", + X"2F",X"4F",X"4B",X"2F",X"4F",X"4E",X"45",X"2F",X"4F",X"50",X"45",X"4E",X"2F",X"4F",X"52",X"2F", + X"4F",X"56",X"45",X"52",X"2F",X"50",X"41",X"54",X"54",X"45",X"52",X"4E",X"53",X"2F",X"50",X"4C", + X"41",X"59",X"45",X"52",X"2F",X"50",X"4C",X"41",X"59",X"45",X"52",X"53",X"2F",X"20",X"50",X"4F", + X"44",X"2F",X"50",X"52",X"45",X"53",X"45",X"4E",X"54",X"53",X"2F",X"50",X"52",X"45",X"53",X"53", + X"2F",X"51",X"55",X"41",X"4C",X"49",X"46",X"49",X"45",X"44",X"2F",X"52",X"41",X"4D",X"2F",X"52", + X"45",X"56",X"45",X"52",X"53",X"45",X"2F",X"52",X"49",X"47",X"48",X"54",X"2F",X"52",X"4F",X"4D", + X"2F",X"52",X"4F",X"4D",X"53",X"2F",X"53",X"43",X"41",X"4E",X"4E",X"45",X"52",X"2F",X"53",X"45", + X"4C",X"45",X"43",X"54",X"2F",X"53",X"45",X"54",X"2F",X"53",X"4C",X"41",X"4D",X"2F",X"53",X"4D", + X"41",X"52",X"54",X"2F",X"53",X"4F",X"55",X"4E",X"44",X"2F",X"53",X"4F",X"55",X"4E",X"44",X"53", + X"2F",X"53",X"54",X"41",X"52",X"54",X"2F",X"53",X"54",X"45",X"50",X"2F",X"53",X"54",X"49",X"43", + X"4B",X"2F",X"53",X"57",X"41",X"52",X"4D",X"45",X"52",X"2F",X"53",X"57",X"49",X"54",X"43",X"48", + X"2F",X"54",X"45",X"53",X"54",X"2F",X"54",X"45",X"53",X"54",X"45",X"44",X"2F",X"54",X"45",X"53", + X"54",X"53",X"2F",X"54",X"48",X"45",X"2F",X"54",X"48",X"52",X"55",X"2F",X"54",X"48",X"52",X"55", + X"53",X"54",X"2F",X"54",X"49",X"4C",X"54",X"2F",X"54",X"49",X"4D",X"45",X"2F",X"54",X"4F",X"2F", + X"54",X"4F",X"44",X"41",X"59",X"53",X"2F",X"54",X"57",X"4F",X"2F",X"55",X"4E",X"49",X"54",X"2F", + X"55",X"50",X"2F",X"56",X"45",X"52",X"54",X"49",X"43",X"41",X"4C",X"2F",X"57",X"41",X"56",X"45", + X"2F",X"57",X"49",X"4C",X"4C",X"49",X"41",X"4D",X"53",X"2F",X"57",X"49",X"54",X"48",X"2F",X"59", + X"4F",X"55",X"2F",X"01",X"08",X"C6",X"97",X"01",X"08",X"C6",X"AF",X"01",X"08",X"C6",X"B7",X"03", + X"08",X"C7",X"BF",X"01",X"08",X"C6",X"BF",X"03",X"08",X"C7",X"BF",X"03",X"08",X"C6",X"C7",X"03", + X"08",X"C6",X"DF",X"03",X"08",X"C6",X"F7",X"03",X"08",X"C7",X"0F",X"03",X"08",X"C7",X"27",X"03", + X"08",X"C7",X"3F",X"03",X"08",X"C7",X"57",X"03",X"08",X"C7",X"6F",X"03",X"08",X"C7",X"87",X"03", + X"08",X"C7",X"9F",X"01",X"08",X"C7",X"B7",X"03",X"08",X"C7",X"BF",X"03",X"08",X"C6",X"97",X"03", + X"08",X"C7",X"D7",X"03",X"08",X"C7",X"EF",X"03",X"08",X"C8",X"07",X"03",X"08",X"C8",X"1F",X"03", + X"08",X"C8",X"37",X"03",X"08",X"C8",X"4F",X"03",X"08",X"C8",X"67",X"03",X"08",X"C8",X"7F",X"02", + X"08",X"C8",X"97",X"03",X"08",X"C8",X"A7",X"03",X"08",X"C8",X"BF",X"03",X"08",X"C8",X"D7",X"04", + X"08",X"C8",X"EF",X"03",X"08",X"C9",X"0F",X"03",X"08",X"C9",X"27",X"03",X"08",X"C9",X"3F",X"03", + X"08",X"C9",X"57",X"03",X"08",X"C9",X"6F",X"03",X"08",X"C9",X"87",X"03",X"08",X"C9",X"9F",X"03", + X"08",X"C9",X"B7",X"03",X"08",X"C9",X"CF",X"04",X"08",X"C9",X"E7",X"03",X"08",X"CA",X"07",X"03", + X"08",X"CA",X"1F",X"03",X"08",X"CA",X"37",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01", + X"01",X"01",X"01",X"01",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"10",X"00", + X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"11", + X"00",X"00",X"00",X"00",X"00",X"11",X"00",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"00",X"00", + X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"01",X"11",X"10",X"00",X"00",X"00",X"00",X"00",X"11", + X"11",X"11",X"11",X"11",X"11",X"11",X"00",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"00",X"11", + X"00",X"00",X"01",X"10",X"00",X"11",X"00",X"11",X"11",X"11",X"10",X"00",X"00",X"11",X"00",X"01", + X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"11",X"00",X"00",X"11",X"00",X"00",X"11",X"00",X"11", + X"11",X"11",X"11",X"11",X"11",X"11",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"01", + X"10",X"00",X"11",X"00",X"00",X"00",X"00",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"00",X"01", + X"01",X"01",X"01",X"00",X"00",X"01",X"00",X"11",X"10",X"10",X"11",X"00",X"00",X"11",X"00",X"11", + X"00",X"00",X"11",X"01",X"01",X"11",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"11", + X"10",X"10",X"11",X"10",X"10",X"11",X"00",X"11",X"00",X"00",X"11",X"01",X"01",X"11",X"00",X"01", + X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"11",X"00",X"00",X"01",X"11",X"10",X"10",X"00",X"11", + X"11",X"11",X"10",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"00",X"01",X"01",X"01",X"00",X"11", + X"10",X"10",X"11",X"10",X"10",X"11",X"00",X"11",X"01",X"01",X"10",X"01",X"01",X"11",X"00",X"01", + X"01",X"01",X"01",X"00",X"00",X"01",X"00",X"11",X"10",X"10",X"11",X"00",X"00",X"11",X"00",X"11", + X"01",X"01",X"11",X"01",X"01",X"11",X"00",X"00",X"00",X"01",X"00",X"00",X"01",X"00",X"00",X"01", + X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"00",X"00",X"01",X"01",X"00",X"01",X"00",X"11", + X"11",X"11",X"10",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"11", + X"00",X"00",X"11",X"00",X"00",X"00",X"00",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"00",X"01", + X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"11",X"00",X"00",X"11",X"00",X"00",X"11",X"00",X"11", + X"11",X"11",X"11",X"11",X"11",X"11",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"11", + X"10",X"10",X"10",X"10",X"10",X"11",X"00",X"11",X"00",X"00",X"00",X"00",X"00",X"11",X"00",X"01", + X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"11",X"00",X"00",X"00",X"00",X"00",X"11",X"00",X"10", + X"11",X"11",X"11",X"11",X"11",X"10",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"11", + X"10",X"10",X"11",X"10",X"10",X"11",X"00",X"11",X"00",X"00",X"10",X"00",X"00",X"11",X"00",X"01", + X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"11",X"10",X"10",X"11",X"10",X"10",X"10",X"00",X"11", + X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"11", + X"10",X"10",X"10",X"10",X"10",X"11",X"00",X"11",X"00",X"00",X"11",X"01",X"01",X"11",X"00",X"01", + X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"10",X"10",X"10",X"11",X"10",X"10",X"10",X"00",X"01", + X"01",X"01",X"11",X"01",X"01",X"01",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"11",X"00",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"00",X"01", + X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"01",X"11",X"01",X"00",X"00",X"00",X"01", + X"10",X"00",X"00",X"00",X"10",X"01",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"10", + X"10",X"10",X"10",X"10",X"10",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"00",X"01", + X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"11",X"10",X"10",X"10",X"10",X"10",X"10",X"00",X"11", + X"10",X"10",X"10",X"00",X"00",X"00",X"00",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"00",X"01", + X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"11",X"10",X"10",X"10",X"10",X"10",X"10",X"00",X"11", + X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"11", + X"10",X"10",X"10",X"10",X"10",X"11",X"00",X"11",X"01",X"01",X"01",X"01",X"01",X"11",X"00",X"01", + X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"11",X"10",X"10",X"11",X"10",X"10",X"10",X"00",X"11", + X"01",X"01",X"11",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"11", + X"10",X"10",X"10",X"10",X"10",X"11",X"00",X"11",X"01",X"01",X"01",X"01",X"11",X"11",X"10",X"01", + X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"11",X"10",X"10",X"11",X"10",X"10",X"10",X"00",X"11", + X"01",X"01",X"11",X"10",X"01",X"01",X"00",X"01",X"01",X"01",X"01",X"00",X"00",X"01",X"00",X"11", + X"10",X"10",X"11",X"00",X"00",X"11",X"00",X"11",X"00",X"00",X"11",X"11",X"11",X"11",X"00",X"11", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"00",X"11", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"10", + X"10",X"10",X"10",X"10",X"10",X"11",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"00",X"01", + X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"01",X"00",X"01", + X"01",X"01",X"01",X"01",X"10",X"00",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"00",X"10", + X"10",X"10",X"10",X"10",X"10",X"01",X"00",X"10",X"10",X"10",X"10",X"10",X"10",X"01",X"00",X"10", + X"10",X"10",X"10",X"10",X"10",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"00",X"00", + X"00",X"10",X"01",X"10",X"00",X"00",X"00",X"01",X"01",X"10",X"00",X"10",X"01",X"01",X"00",X"01", + X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"01",X"01",X"01",X"01",X"00",X"01", + X"01",X"10",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"01",X"01",X"01",X"00",X"11", + X"00",X"01",X"10",X"00",X"00",X"11",X"00",X"11",X"10",X"00",X"00",X"00",X"00",X"11",X"00",X"84", + X"FF",X"34",X"70",X"CE",X"C0",X"D9",X"20",X"05",X"34",X"70",X"CE",X"C0",X"BB",X"8E",X"18",X"CE", + X"BD",X"CA",X"A7",X"EE",X"A1",X"27",X"06",X"8E",X"10",X"DA",X"BD",X"CA",X"A7",X"EE",X"A1",X"27", + X"06",X"8E",X"10",X"E4",X"BD",X"CA",X"A7",X"35",X"F0",X"34",X"77",X"10",X"8E",X"FF",X"B6",X"20", + X"06",X"34",X"77",X"10",X"8E",X"FF",X"B3",X"CC",X"CA",X"ED",X"10",X"9F",X"3D",X"DD",X"3F",X"9F", + X"50",X"9F",X"4E",X"8E",X"01",X"0A",X"9F",X"4C",X"0F",X"58",X"EE",X"65",X"DF",X"54",X"33",X"C8", + X"20",X"DF",X"56",X"DF",X"52",X"20",X"46",X"34",X"77",X"10",X"8E",X"FF",X"B3",X"CC",X"CA",X"ED", + X"20",X"1F",X"34",X"77",X"10",X"8E",X"FF",X"B6",X"CC",X"CA",X"ED",X"20",X"14",X"34",X"77",X"10", + X"8E",X"FF",X"B3",X"CC",X"CB",X"5F",X"20",X"09",X"34",X"77",X"10",X"8E",X"FF",X"B6",X"CC",X"CB", + X"5F",X"10",X"9F",X"3D",X"DD",X"3F",X"0D",X"52",X"26",X"13",X"9F",X"50",X"9F",X"4E",X"8E",X"01", + X"0A",X"9F",X"4C",X"0F",X"58",X"AE",X"42",X"9F",X"56",X"AE",X"C4",X"20",X"21",X"0D",X"58",X"26", + X"0E",X"9E",X"54",X"E6",X"80",X"C1",X"2F",X"26",X"30",X"C6",X"20",X"D7",X"58",X"20",X"2A",X"0F", + X"58",X"9E",X"52",X"9C",X"56",X"26",X"07",X"0F",X"52",X"35",X"77",X"1A",X"01",X"39",X"EE",X"81", + X"2B",X"11",X"30",X"1F",X"1F",X"30",X"81",X"08",X"22",X"ED",X"48",X"10",X"8E",X"CB",X"64",X"AD", + X"B6",X"20",X"E0",X"9F",X"52",X"DF",X"54",X"20",X"C4",X"9F",X"54",X"C0",X"20",X"C1",X"01",X"23", + X"16",X"C1",X"0B",X"23",X"10",X"C0",X"0A",X"C1",X"10",X"23",X"0C",X"C1",X"14",X"23",X"06",X"C0", + X"04",X"C1",X"2C",X"23",X"02",X"C6",X"03",X"58",X"58",X"8E",X"C5",X"E3",X"3A",X"1F",X"12",X"DC", + X"50",X"9E",X"3D",X"AD",X"84",X"AB",X"A4",X"9B",X"4C",X"97",X"50",X"9E",X"3F",X"6E",X"84",X"35", + X"77",X"1C",X"FE",X"39",X"CB",X"76",X"CB",X"7B",X"CB",X"80",X"CB",X"87",X"CB",X"8E",X"CB",X"95", + X"CB",X"9C",X"CB",X"A3",X"CB",X"AC",X"A6",X"80",X"97",X"4C",X"39",X"E6",X"80",X"D7",X"4D",X"39", + X"96",X"4E",X"AB",X"80",X"97",X"50",X"39",X"96",X"50",X"AB",X"80",X"97",X"50",X"39",X"D6",X"4F", + X"EB",X"80",X"D7",X"51",X"39",X"D6",X"51",X"EB",X"80",X"D7",X"51",X"39",X"EC",X"81",X"DD",X"4E", + X"DD",X"50",X"39",X"96",X"4E",X"D6",X"51",X"DB",X"4D",X"DD",X"50",X"39",X"10",X"AE",X"81",X"9F", + X"52",X"9E",X"3D",X"AD",X"84",X"AB",X"A4",X"9B",X"4C",X"97",X"50",X"32",X"62",X"9E",X"3F",X"6E", + X"84",X"34",X"77",X"10",X"8E",X"FF",X"B3",X"CE",X"CC",X"0F",X"20",X"1F",X"34",X"77",X"10",X"8E", + X"FF",X"B6",X"CE",X"CC",X"0F",X"20",X"14",X"34",X"77",X"10",X"8E",X"FF",X"B3",X"CE",X"CC",X"39", + X"20",X"09",X"34",X"77",X"10",X"8E",X"FF",X"B6",X"CE",X"CC",X"39",X"10",X"9F",X"3D",X"DF",X"3F", + X"DE",X"59",X"11",X"83",X"FF",X"FF",X"26",X"15",X"9F",X"50",X"DD",X"59",X"26",X"05",X"CC",X"0F", + X"FF",X"20",X"08",X"85",X"F0",X"26",X"04",X"8D",X"35",X"20",X"F8",X"DD",X"59",X"DC",X"59",X"84", + X"F0",X"81",X"F0",X"26",X"07",X"35",X"77",X"9E",X"50",X"1A",X"01",X"39",X"44",X"44",X"8E",X"C5", + X"FB",X"31",X"86",X"DC",X"50",X"9E",X"3D",X"AD",X"84",X"AB",X"A4",X"9B",X"4C",X"97",X"50",X"DC", + X"59",X"8D",X"0B",X"DD",X"59",X"9E",X"3F",X"6E",X"84",X"35",X"77",X"1C",X"FE",X"39",X"58",X"49", + X"58",X"49",X"58",X"49",X"58",X"49",X"CA",X"0F",X"39",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"05",X"38",X"4E",X"CE",X"96",X"09",X"AC",X"42",X"90",X"16",X"52",X"A8",X"F2",X"12",X"96",X"6A", + X"08",X"C0",X"DE",X"CA",X"A5",X"54",X"1B",X"88",X"2D",X"59",X"A3",X"96",X"41",X"DC",X"EF",X"A3", + X"27",X"03",X"B6",X"1C",X"EF",X"5E",X"FF",X"D7",X"B0",X"56",X"A4",X"76",X"C3",X"A0",X"90",X"9B", + X"D9",X"08",X"D3",X"04",X"CB",X"99",X"C8",X"70",X"43",X"94",X"33",X"7B",X"6B",X"8D",X"B2",X"F8", + X"00",X"0C",X"CC",X"CC",X"CC",X"CC",X"0C",X"00",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC", + X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"00",X"C0",X"CC",X"CC",X"CC",X"CC",X"C0",X"00", + X"A0",X"0A",X"A0",X"A0",X"00",X"A0",X"0A",X"00",X"0A",X"0A",X"A0",X"0A",X"0A",X"AA",X"0A",X"00", + X"A0",X"00",X"00",X"0A",X"00",X"A0",X"AA",X"A0",X"00",X"02",X"23",X"02",X"20",X"22",X"23",X"22", + X"00",X"00",X"20",X"00",X"00",X"00",X"02",X"00",X"02",X"22",X"32",X"22",X"00",X"20",X"32",X"20", + X"00",X"00",X"03",X"03",X"00",X"00",X"03",X"30",X"04",X"34",X"30",X"30",X"34",X"30",X"00",X"00", + X"44",X"44",X"33",X"33",X"34",X"30",X"30",X"30",X"00",X"30",X"03",X"03",X"30",X"30",X"03",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03", + X"00",X"03",X"33",X"33",X"03",X"03",X"30",X"00",X"44",X"44",X"03",X"03",X"43",X"03",X"03",X"03", + X"40",X"43",X"30",X"30",X"43",X"03",X"00",X"00",X"00",X"00",X"30",X"30",X"00",X"00",X"30",X"03", + X"00",X"00",X"03",X"03",X"00",X"00",X"03",X"30",X"04",X"34",X"03",X"03",X"34",X"30",X"00",X"00", + X"44",X"44",X"30",X"30",X"34",X"30",X"30",X"30",X"00",X"30",X"33",X"33",X"30",X"30",X"03",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03", + X"00",X"03",X"30",X"30",X"03",X"03",X"30",X"00",X"44",X"44",X"33",X"33",X"43",X"03",X"03",X"03", + X"40",X"43",X"03",X"03",X"43",X"03",X"00",X"00",X"00",X"00",X"30",X"30",X"00",X"00",X"30",X"03", + X"00",X"00",X"03",X"03",X"00",X"00",X"03",X"30",X"00",X"33",X"33",X"33",X"33",X"30",X"00",X"00", + X"00",X"33",X"03",X"03",X"33",X"30",X"30",X"30",X"00",X"30",X"33",X"33",X"30",X"30",X"03",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03", + X"00",X"03",X"33",X"33",X"03",X"03",X"30",X"00",X"00",X"33",X"30",X"30",X"03",X"03",X"03",X"03", + X"00",X"33",X"33",X"33",X"33",X"03",X"00",X"00",X"00",X"00",X"30",X"30",X"00",X"00",X"30",X"03", + X"00",X"03",X"34",X"03",X"33",X"70",X"40",X"33",X"33",X"07",X"44",X"33",X"33",X"00",X"04",X"33", + X"30",X"73",X"40",X"33",X"00",X"00",X"30",X"00",X"00",X"00",X"03",X"00",X"03",X"37",X"44",X"33", + X"33",X"00",X"04",X"33",X"33",X"70",X"40",X"33",X"33",X"07",X"44",X"33",X"00",X"30",X"03",X"30", + X"00",X"03",X"30",X"03",X"33",X"00",X"44",X"33",X"33",X"70",X"04",X"33",X"33",X"07",X"40",X"33", + X"30",X"03",X"44",X"33",X"00",X"00",X"30",X"00",X"00",X"00",X"03",X"00",X"03",X"30",X"04",X"33", + X"33",X"07",X"40",X"33",X"33",X"00",X"44",X"33",X"33",X"70",X"04",X"33",X"00",X"30",X"43",X"30", + X"00",X"03",X"34",X"03",X"33",X"07",X"04",X"33",X"33",X"00",X"40",X"33",X"33",X"70",X"44",X"33", + X"30",X"03",X"04",X"33",X"00",X"00",X"30",X"00",X"00",X"00",X"03",X"00",X"03",X"30",X"40",X"33", + X"33",X"70",X"44",X"33",X"33",X"07",X"04",X"33",X"33",X"00",X"40",X"33",X"00",X"30",X"43",X"30", + X"00",X"06",X"26",X"06",X"26",X"00",X"66",X"66",X"66",X"88",X"88",X"88",X"00",X"60",X"66",X"66", + X"88",X"86",X"00",X"00",X"00",X"66",X"66",X"93",X"00",X"00",X"00",X"6D",X"66",X"00",X"00",X"00", + X"00",X"EF",X"66",X"00",X"00",X"00",X"00",X"00",X"69",X"00",X"00",X"00",X"00",X"00",X"30",X"00", + X"00",X"00",X"02",X"00",X"02",X"00",X"06",X"66",X"66",X"28",X"68",X"08",X"60",X"66",X"66",X"86", + X"88",X"88",X"00",X"00",X"60",X"66",X"86",X"69",X"00",X"00",X"00",X"66",X"66",X"30",X"00",X"00", + X"00",X"DE",X"66",X"00",X"00",X"00",X"00",X"F0",X"66",X"00",X"00",X"00",X"00",X"00",X"93",X"00", + X"00",X"00",X"00",X"00",X"39",X"00",X"00",X"00",X"00",X"0F",X"66",X"00",X"00",X"00",X"00",X"ED", + X"66",X"00",X"00",X"00",X"00",X"66",X"66",X"03",X"00",X"00",X"06",X"66",X"68",X"96",X"06",X"66", + X"66",X"68",X"88",X"88",X"60",X"66",X"66",X"83",X"86",X"80",X"00",X"00",X"30",X"00",X"30",X"00", + X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"96",X"00",X"00",X"00",X"00",X"FE", + X"66",X"00",X"00",X"00",X"00",X"D6",X"66",X"00",X"00",X"00",X"00",X"66",X"66",X"39",X"00",X"06", + X"66",X"66",X"88",X"68",X"66",X"66",X"66",X"88",X"88",X"88",X"00",X"60",X"63",X"30",X"63",X"00", + X"06",X"26",X"68",X"28",X"60",X"66",X"66",X"86",X"00",X"00",X"66",X"66",X"00",X"00",X"ED",X"66", + X"00",X"00",X"00",X"63",X"90",X"09",X"90",X"99",X"99",X"99",X"90",X"CC",X"90",X"11",X"00",X"11", + X"10",X"11",X"00",X"10",X"10",X"10",X"00",X"10",X"00",X"11",X"10",X"11",X"00",X"11",X"00",X"10", + X"00",X"10",X"10",X"10",X"00",X"11",X"10",X"10",X"10",X"11",X"00",X"10",X"10",X"10",X"10",X"10", + X"00",X"01",X"00",X"01",X"01",X"01",X"00",X"11",X"01",X"11",X"00",X"11",X"00",X"01",X"01",X"01", + X"00",X"01",X"00",X"11",X"00",X"11",X"01",X"11",X"00",X"01",X"01",X"01",X"01",X"01",X"00",X"11", + X"01",X"01",X"01",X"11",X"00",X"FF",X"F0",X"FF",X"00",X"FF",X"00",X"F0",X"00",X"F0",X"F0",X"F0", + X"00",X"EE",X"E0",X"E0",X"E0",X"EE",X"00",X"E0",X"E0",X"E0",X"E0",X"E0",X"00",X"DD",X"D0",X"D0", + X"D0",X"DD",X"00",X"D0",X"D0",X"D0",X"D0",X"D0",X"00",X"0F",X"0F",X"0F",X"00",X"0F",X"00",X"FF", + X"00",X"FF",X"0F",X"FF",X"00",X"0E",X"0E",X"0E",X"0E",X"0E",X"00",X"EE",X"0E",X"0E",X"0E",X"EE", + X"00",X"0D",X"0D",X"0D",X"0D",X"0D",X"00",X"DD",X"0D",X"0D",X"0D",X"DD",X"00",X"1C",X"0D",X"7F", + X"E7",X"70",X"00",X"0F",X"71",X"71",X"07",X"DC",X"77",X"7C",X"0D",X"71",X"C7",X"77",X"DE",X"07", + X"71",X"17",X"17",X"DE",X"F7",X"71",X"17",X"71",X"7C",X"DE",X"F0",X"07",X"77",X"C7",X"71",X"17", + X"70",X"70",X"7C",X"D7",X"77",X"77",X"70",X"01",X"CD",X"FF",X"D7",X"70",X"F0",X"00",X"00",X"00", + X"7E",X"C0",X"76",X"7E",X"C0",X"9C",X"7E",X"C0",X"B8",X"7E",X"C0",X"FC",X"7E",X"CB",X"E6",X"7E", + X"CB",X"E0",X"7E",X"CC",X"2C",X"7E",X"CC",X"20",X"7E",X"CC",X"26",X"7E",X"CC",X"AF",X"7E",X"CB", + X"AF",X"7E",X"C7",X"99",X"7E",X"C1",X"27",X"7E",X"C1",X"46",X"7E",X"C2",X"3D",X"7E",X"C2",X"C3", + X"7E",X"C4",X"06",X"7E",X"CC",X"C1",X"7E",X"FF",X"D4",X"7E",X"FF",X"D7",X"BD",X"FF",X"CE",X"C0", + X"02",X"02",X"39",X"BD",X"FF",X"CE",X"C0",X"05",X"02",X"39",X"BD",X"FF",X"CE",X"C0",X"0E",X"02", + X"39",X"BD",X"FF",X"CE",X"C0",X"11",X"02",X"39",X"BD",X"FF",X"CE",X"C0",X"1A",X"02",X"39",X"BD", + X"FF",X"CE",X"C0",X"1D",X"02",X"39",X"BD",X"FF",X"CE",X"C0",X"20",X"02",X"39",X"BD",X"FF",X"CE", + X"C0",X"23",X"02",X"39",X"D9",X"FF",X"BD",X"CA",X"2A",X"C6",X"7A",X"BD",X"C7",X"93",X"CE",X"C0", + X"69",X"8E",X"28",X"70",X"BD",X"C0",X"3C",X"CE",X"C0",X"6B",X"8E",X"40",X"90",X"BD",X"C0",X"3C", + X"C6",X"0F",X"BD",X"CA",X"C8",X"10",X"8E",X"0B",X"B8",X"7E",X"CA",X"44",X"BD",X"CA",X"2A",X"C6", + X"57",X"BD",X"C7",X"93",X"CE",X"C0",X"69",X"8E",X"28",X"70",X"BD",X"C0",X"3C",X"CE",X"C0",X"73", + X"8E",X"38",X"90",X"BD",X"C0",X"3C",X"20",X"29",X"BD",X"CA",X"2A",X"C6",X"57",X"BD",X"C7",X"93", + X"CE",X"C0",X"69",X"8E",X"28",X"60",X"BD",X"C0",X"3C",X"CE",X"C0",X"71",X"8E",X"38",X"80",X"BD", + X"C0",X"3C",X"1F",X"B8",X"81",X"9E",X"27",X"09",X"CE",X"C0",X"73",X"8E",X"38",X"A0",X"BD",X"C0", + X"3C",X"10",X"8E",X"0B",X"B8",X"BD",X"CA",X"57",X"8E",X"CC",X"00",X"BD",X"C0",X"39",X"C5",X"02", + X"27",X"05",X"54",X"25",X"06",X"20",X"4F",X"31",X"3F",X"26",X"EA",X"39",X"1C",X"EF",X"8E",X"C4", + X"7F",X"BD",X"FF",X"A4",X"C1",X"5A",X"26",X"36",X"8E",X"C4",X"00",X"BD",X"C0",X"39",X"C4",X"0F", + X"26",X"01",X"39",X"5F",X"BD",X"C0",X"36",X"8E",X"C4",X"7D",X"BD",X"FF",X"A4",X"4F",X"30",X"1E", + X"BD",X"FF",X"AA",X"C1",X"15",X"26",X"04",X"1C",X"7F",X"20",X"1B",X"C1",X"25",X"26",X"03",X"7E", + X"CC",X"AF",X"C1",X"35",X"26",X"03",X"7E",X"CB",X"BF",X"C1",X"45",X"27",X"01",X"39",X"32",X"62", + X"BD",X"CB",X"CF",X"7E",X"C7",X"99",X"1A",X"10",X"BD",X"CA",X"2A",X"BD",X"FF",X"BF",X"34",X"40", + X"FE",X"FF",X"9F",X"33",X"C8",X"18",X"DF",X"43",X"35",X"40",X"11",X"93",X"43",X"27",X"70",X"DF", + X"5B",X"C6",X"08",X"BD",X"CA",X"AA",X"C6",X"57",X"BD",X"C7",X"93",X"CE",X"C0",X"71",X"8E",X"38", + X"60",X"BD",X"C0",X"3C",X"10",X"8E",X"C0",X"35",X"BD",X"C0",X"6D",X"CC",X"42",X"66",X"DD",X"4A", + X"9E",X"4A",X"30",X"0A",X"9F",X"4A",X"CE",X"C0",X"6D",X"BD",X"C0",X"3C",X"FE",X"FF",X"9F",X"DF", + X"43",X"DE",X"5B",X"DC",X"5B",X"93",X"43",X"54",X"25",X"02",X"33",X"41",X"5C",X"D7",X"3A",X"BD", + X"CB",X"23",X"9E",X"50",X"BD",X"C0",X"4A",X"BD",X"CA",X"69",X"BD",X"FF",X"C2",X"DF",X"5B",X"FE", + X"FF",X"9F",X"33",X"C8",X"18",X"11",X"93",X"5B",X"26",X"C6",X"BD",X"CA",X"0E",X"0D",X"49",X"26", + X"30",X"D6",X"3A",X"BD",X"CA",X"AA",X"10",X"8E",X"C0",X"39",X"BD",X"C0",X"6D",X"20",X"1F",X"1F", + X"A9",X"5D",X"2A",X"3E",X"C6",X"7A",X"BD",X"C7",X"93",X"CE",X"C0",X"77",X"8E",X"38",X"80",X"BD", + X"C0",X"3C",X"10",X"8E",X"C0",X"39",X"BD",X"C0",X"6D",X"C6",X"08",X"BD",X"CA",X"C8",X"BD",X"CA", + X"39",X"BD",X"CA",X"2A",X"5F",X"BD",X"CA",X"AA",X"BD",X"C7",X"91",X"CE",X"C0",X"79",X"8E",X"40", + X"80",X"BD",X"C0",X"3C",X"10",X"8E",X"C0",X"3D",X"BD",X"C0",X"6D",X"10",X"8E",X"13",X"88",X"BD", + X"CA",X"44",X"BD",X"CA",X"57",X"0D",X"49",X"10",X"26",X"00",X"D7",X"0D",X"47",X"26",X"F3",X"8E", + X"C0",X"00",X"C6",X"C0",X"BD",X"C0",X"36",X"86",X"B5",X"3D",X"1E",X"89",X"30",X"01",X"8C",X"C0", + X"10",X"26",X"F1",X"CC",X"00",X"00",X"10",X"8E",X"00",X"0A",X"7E",X"FF",X"C5",X"1F",X"20",X"E8", + X"82",X"A8",X"82",X"DD",X"41",X"9F",X"43",X"BD",X"CA",X"F9",X"BD",X"FF",X"BC",X"BD",X"CA",X"E4", + X"BD",X"CA",X"69",X"C6",X"04",X"BD",X"CA",X"AA",X"C6",X"57",X"BD",X"C7",X"93",X"CE",X"C0",X"73", + X"8E",X"38",X"70",X"BD",X"C0",X"3C",X"10",X"8E",X"C0",X"41",X"BD",X"C0",X"6D",X"DC",X"41",X"4D", + X"26",X"02",X"1F",X"98",X"5F",X"5C",X"44",X"24",X"FC",X"D7",X"3A",X"DC",X"43",X"80",X"03",X"24", + X"FC",X"8B",X"04",X"97",X"3B",X"CE",X"C0",X"6F",X"8E",X"42",X"90",X"BD",X"C0",X"3C",X"D6",X"3B", + X"58",X"58",X"58",X"58",X"DB",X"3A",X"4F",X"9E",X"50",X"BD",X"C0",X"4A",X"BD",X"CA",X"0E",X"0D", + X"49",X"26",X"4F",X"96",X"3B",X"C6",X"10",X"54",X"4A",X"26",X"FC",X"BD",X"CA",X"AA",X"BD",X"CA", + X"0E",X"0D",X"49",X"26",X"3D",X"D6",X"3A",X"BD",X"CA",X"AA",X"10",X"8E",X"C0",X"45",X"BD",X"C0", + X"6D",X"20",X"2C",X"BD",X"CA",X"F9",X"BD",X"FF",X"BC",X"BD",X"CA",X"E4",X"BD",X"CA",X"69",X"10", + X"8C",X"00",X"0A",X"27",X"1D",X"C6",X"7A",X"BD",X"C7",X"93",X"CE",X"C0",X"7B",X"8E",X"28",X"80", + X"BD",X"C0",X"3C",X"10",X"8E",X"C0",X"45",X"BD",X"C0",X"6D",X"C6",X"04",X"BD",X"CA",X"C8",X"BD", + X"CA",X"39",X"BD",X"CA",X"2A",X"1F",X"B8",X"81",X"A2",X"26",X"1D",X"C6",X"02",X"BD",X"CA",X"AA", + X"C6",X"57",X"BD",X"C7",X"93",X"CE",X"C0",X"81",X"8E",X"28",X"80",X"BD",X"C0",X"3C",X"10",X"8E", + X"C0",X"49",X"BD",X"C0",X"6D",X"7E",X"C3",X"BB",X"8B",X"03",X"5F",X"DD",X"41",X"DE",X"41",X"8E", + X"C4",X"00",X"BD",X"C0",X"39",X"E7",X"C0",X"30",X"01",X"8C",X"C5",X"00",X"26",X"F4",X"CC",X"00", + X"10",X"D7",X"3A",X"4F",X"8E",X"C4",X"00",X"D6",X"3A",X"BD",X"C0",X"36",X"30",X"01",X"5C",X"D1", + X"3A",X"26",X"F6",X"8E",X"C4",X"00",X"4C",X"BD",X"C0",X"39",X"D7",X"3B",X"30",X"01",X"BD",X"C0", + X"39",X"D0",X"3B",X"5A",X"C4",X"0F",X"26",X"0E",X"4C",X"26",X"EC",X"BD",X"CA",X"69",X"0D",X"49", + X"26",X"04",X"0A",X"3A",X"26",X"CE",X"DE",X"41",X"8E",X"C4",X"00",X"E6",X"C0",X"BD",X"C0",X"36", + X"30",X"01",X"8C",X"C5",X"00",X"26",X"F4",X"0D",X"49",X"26",X"43",X"96",X"3A",X"27",X"22",X"C6", + X"02",X"BD",X"CA",X"AA",X"C6",X"57",X"BD",X"C7",X"93",X"BD",X"CA",X"69",X"CE",X"C0",X"7D",X"8E", + X"30",X"80",X"BD",X"C0",X"3C",X"BD",X"CA",X"69",X"10",X"8E",X"C0",X"49",X"BD",X"C0",X"6D",X"20", + X"1A",X"C6",X"7A",X"BD",X"C7",X"93",X"CE",X"C0",X"7F",X"8E",X"38",X"80",X"BD",X"C0",X"3C",X"10", + X"8E",X"C0",X"49",X"BD",X"C0",X"6D",X"C6",X"02",X"BD",X"CA",X"C8",X"BD",X"CA",X"39",X"BD",X"CA", + X"2A",X"C6",X"01",X"BD",X"CA",X"AA",X"BD",X"C7",X"91",X"CE",X"C0",X"83",X"8E",X"38",X"80",X"BD", + X"C0",X"3C",X"10",X"8E",X"C0",X"4D",X"BD",X"C0",X"6D",X"10",X"8E",X"13",X"88",X"BD",X"CA",X"44", + X"BD",X"CB",X"67",X"10",X"8E",X"07",X"D0",X"CE",X"C9",X"D8",X"E6",X"C0",X"8E",X"C0",X"00",X"BD", + X"C0",X"36",X"30",X"01",X"8C",X"C0",X"10",X"26",X"F6",X"BD",X"CA",X"44",X"11",X"83",X"C9",X"E0", + X"26",X"E8",X"0D",X"49",X"27",X"E1",X"BD",X"CA",X"2A",X"5F",X"D7",X"41",X"D7",X"42",X"BD",X"CA", + X"AA",X"BD",X"C7",X"91",X"CE",X"C0",X"85",X"8E",X"40",X"78",X"BD",X"C0",X"3C",X"10",X"8E",X"C0", + X"55",X"BD",X"C0",X"6D",X"10",X"8E",X"00",X"01",X"CE",X"C9",X"F0",X"4F",X"8E",X"CC",X"00",X"BD", + X"C0",X"39",X"C5",X"01",X"26",X"09",X"C5",X"02",X"26",X"15",X"BD",X"CA",X"57",X"20",X"ED",X"BD", + X"CA",X"44",X"4C",X"A1",X"C4",X"26",X"04",X"33",X"41",X"20",X"F7",X"97",X"3A",X"88",X"3F",X"C6", + X"13",X"BD",X"CB",X"0B",X"0D",X"49",X"26",X"2E",X"D6",X"3A",X"BD",X"CB",X"0B",X"10",X"8E",X"03", + X"E8",X"DC",X"41",X"8E",X"5A",X"8C",X"BD",X"C0",X"51",X"D6",X"3A",X"BD",X"CB",X"23",X"4F",X"DD", + X"41",X"8E",X"5A",X"8C",X"BD",X"C0",X"4A",X"96",X"3A",X"81",X"1F",X"26",X"AF",X"1F",X"A9",X"5D", + X"10",X"2A",X"01",X"01",X"20",X"A2",X"BD",X"CA",X"2A",X"BD",X"C7",X"91",X"CE",X"C0",X"87",X"8E", + X"38",X"20",X"BD",X"C0",X"3C",X"10",X"8E",X"C0",X"59",X"BD",X"C0",X"6D",X"1F",X"B8",X"C6",X"62", + X"DD",X"41",X"CB",X"26",X"1F",X"01",X"86",X"FF",X"A7",X"82",X"9C",X"41",X"26",X"FA",X"0F",X"5D", + X"0F",X"5E",X"0F",X"5F",X"0F",X"60",X"0F",X"61",X"86",X"01",X"97",X"3C",X"8E",X"CC",X"00",X"DE", + X"41",X"33",X"5B",X"4F",X"BD",X"C0",X"39",X"8C",X"CC",X"06",X"26",X"02",X"C4",X"7F",X"81",X"18", + X"26",X"02",X"C4",X"CF",X"D7",X"3A",X"E8",X"C0",X"26",X"38",X"8B",X"08",X"30",X"02",X"8C",X"CC", + X"02",X"27",X"F9",X"8C",X"CC",X"08",X"26",X"DC",X"81",X"28",X"27",X"15",X"30",X"1E",X"BD",X"C0", + X"39",X"5D",X"2A",X"0D",X"C6",X"34",X"30",X"01",X"BD",X"C0",X"36",X"30",X"1D",X"0C",X"3C",X"20", + X"C3",X"C6",X"3C",X"8E",X"CC",X"07",X"BD",X"C0",X"36",X"BD",X"CA",X"69",X"0D",X"49",X"27",X"A8", + X"20",X"73",X"D7",X"3B",X"C6",X"01",X"D5",X"3B",X"26",X"04",X"4C",X"58",X"20",X"F8",X"9E",X"41", + X"D5",X"3A",X"26",X"14",X"E8",X"C2",X"E7",X"C4",X"A1",X"80",X"26",X"FC",X"63",X"82",X"8D",X"3C", + X"CC",X"38",X"08",X"BD",X"FF",X"B9",X"20",X"C9",X"E8",X"C2",X"E7",X"C4",X"C6",X"08",X"BD",X"CB", + X"0B",X"6D",X"80",X"2A",X"FC",X"A7",X"82",X"34",X"02",X"8D",X"21",X"BD",X"C0",X"3C",X"35",X"02", + X"81",X"08",X"25",X"AD",X"44",X"81",X"06",X"27",X"A8",X"8E",X"CC",X"06",X"BD",X"C0",X"39",X"5D", + X"2A",X"9F",X"9E",X"50",X"4F",X"D6",X"3C",X"BD",X"C0",X"4A",X"20",X"95",X"CE",X"C0",X"8B",X"81", + X"18",X"25",X"02",X"80",X"10",X"48",X"33",X"C6",X"1F",X"10",X"93",X"41",X"86",X"0A",X"3D",X"C3", + X"38",X"30",X"1F",X"01",X"39",X"BD",X"CA",X"2A",X"BD",X"C7",X"91",X"CE",X"C0",X"89",X"8E",X"28", + X"80",X"BD",X"C0",X"3C",X"10",X"8E",X"C0",X"5D",X"BD",X"C0",X"6D",X"8E",X"CC",X"00",X"CE",X"C9", + X"F4",X"BD",X"C0",X"39",X"C5",X"01",X"27",X"14",X"10",X"8E",X"13",X"88",X"BD",X"CA",X"44",X"0D", + X"49",X"10",X"26",X"01",X"E4",X"BD",X"C0",X"39",X"C5",X"01",X"26",X"09",X"BD",X"CA",X"0E",X"0D", + X"49",X"10",X"26",X"01",X"D4",X"34",X"70",X"AD",X"D4",X"35",X"70",X"33",X"42",X"11",X"83",X"C9", + X"FE",X"26",X"CE",X"10",X"8E",X"13",X"88",X"BD",X"CA",X"44",X"1F",X"A9",X"5D",X"10",X"2A",X"FB", + X"65",X"20",X"BB",X"BD",X"CA",X"69",X"BD",X"FF",X"BC",X"BD",X"CA",X"F9",X"8E",X"C0",X"01",X"C6", + X"FF",X"BD",X"C0",X"36",X"8E",X"C0",X"02",X"C6",X"C0",X"BD",X"C0",X"36",X"8E",X"C0",X"03",X"C6", + X"38",X"BD",X"C0",X"36",X"8E",X"C0",X"04",X"C6",X"07",X"BD",X"C0",X"36",X"BD",X"CA",X"69",X"10", + X"8E",X"C6",X"F7",X"CC",X"01",X"01",X"AE",X"A4",X"ED",X"81",X"AC",X"22",X"26",X"FA",X"31",X"24", + X"10",X"8C",X"C7",X"1F",X"26",X"F0",X"BD",X"CA",X"69",X"86",X"11",X"10",X"8E",X"C6",X"D7",X"AE", + X"A4",X"9F",X"45",X"A7",X"84",X"0C",X"45",X"9E",X"45",X"AC",X"22",X"26",X"F6",X"31",X"24",X"10", + X"8C",X"C6",X"F7",X"26",X"EA",X"BD",X"CA",X"69",X"10",X"8E",X"C7",X"1F",X"AE",X"A4",X"9F",X"45", + X"A6",X"24",X"A7",X"84",X"0C",X"45",X"9E",X"45",X"AC",X"22",X"26",X"F6",X"31",X"25",X"10",X"8C", + X"C7",X"5B",X"26",X"E8",X"BD",X"CA",X"69",X"10",X"8E",X"C7",X"5B",X"AE",X"A4",X"A6",X"24",X"A7", + X"80",X"AC",X"22",X"26",X"FA",X"31",X"25",X"10",X"8C",X"C7",X"6F",X"26",X"EE",X"BD",X"CA",X"69", + X"86",X"21",X"B7",X"46",X"7E",X"86",X"20",X"B7",X"96",X"7E",X"8E",X"4E",X"0A",X"A6",X"84",X"84", + X"F0",X"8A",X"02",X"A7",X"80",X"8C",X"4E",X"6D",X"26",X"F3",X"8E",X"4E",X"90",X"A6",X"84",X"84", + X"F0",X"8A",X"02",X"A7",X"80",X"8C",X"4E",X"F3",X"26",X"F3",X"BD",X"CA",X"69",X"8E",X"0E",X"18", + X"9F",X"45",X"9E",X"45",X"A6",X"84",X"84",X"F0",X"8A",X"01",X"A7",X"84",X"D6",X"46",X"CB",X"22", + X"25",X"04",X"D7",X"46",X"20",X"EC",X"C6",X"18",X"D7",X"46",X"D6",X"45",X"CB",X"10",X"D7",X"45", + X"C1",X"9E",X"26",X"DE",X"7E",X"CA",X"69",X"07",X"07",X"97",X"07",X"07",X"29",X"97",X"29",X"07", + X"4B",X"97",X"4B",X"07",X"6D",X"97",X"6D",X"07",X"8F",X"97",X"8F",X"07",X"B1",X"97",X"B1",X"07", + X"D3",X"97",X"D3",X"07",X"F5",X"97",X"F5",X"06",X"07",X"06",X"F5",X"16",X"07",X"16",X"F5",X"26", + X"07",X"26",X"F5",X"36",X"07",X"36",X"F5",X"46",X"07",X"46",X"F5",X"56",X"07",X"56",X"F5",X"66", + X"07",X"66",X"F5",X"76",X"07",X"76",X"F5",X"86",X"07",X"86",X"F5",X"96",X"07",X"96",X"F5",X"48", + X"05",X"55",X"05",X"44",X"48",X"06",X"55",X"06",X"44",X"48",X"07",X"55",X"07",X"00",X"48",X"08", + X"55",X"08",X"33",X"48",X"09",X"55",X"09",X"33",X"48",X"F3",X"55",X"F3",X"33",X"48",X"F4",X"55", + X"F4",X"33",X"48",X"F5",X"55",X"F5",X"00",X"48",X"F6",X"55",X"F6",X"44",X"48",X"F7",X"55",X"F7", + X"44",X"07",X"7E",X"46",X"7E",X"22",X"57",X"7E",X"96",X"7E",X"22",X"05",X"6F",X"05",X"8E",X"04", + X"06",X"6F",X"06",X"8E",X"30",X"96",X"6F",X"96",X"8E",X"00",X"97",X"6F",X"97",X"8E",X"34",X"BD", + X"FF",X"BC",X"C6",X"05",X"8E",X"C0",X"00",X"8D",X"03",X"8E",X"C0",X"0C",X"7E",X"C0",X"36",X"C6", + X"28",X"20",X"F1",X"C6",X"80",X"20",X"ED",X"10",X"8E",X"C9",X"FE",X"BD",X"CA",X"97",X"7E",X"CB", + X"3B",X"C6",X"A5",X"8E",X"C0",X"01",X"7E",X"C0",X"36",X"BD",X"CA",X"69",X"BD",X"CA",X"2A",X"8D", + X"F0",X"CE",X"C0",X"D7",X"8E",X"28",X"20",X"BD",X"CA",X"69",X"BD",X"C0",X"3C",X"10",X"8E",X"C0", + X"61",X"BD",X"C0",X"6D",X"10",X"8E",X"05",X"DC",X"BD",X"CA",X"44",X"0D",X"49",X"26",X"60",X"0F", + X"3C",X"86",X"01",X"97",X"3B",X"32",X"E8",X"E0",X"BD",X"FF",X"BC",X"CE",X"C0",X"D7",X"8E",X"28", + X"20",X"BD",X"CA",X"69",X"BD",X"C0",X"3C",X"0F",X"3A",X"10",X"8E",X"C0",X"65",X"BD",X"C0",X"66", + X"BD",X"CA",X"69",X"86",X"20",X"1F",X"89",X"5A",X"30",X"E4",X"A7",X"80",X"5A",X"26",X"FB",X"86", + X"2F",X"A7",X"80",X"30",X"E4",X"BD",X"CA",X"57",X"8E",X"CC",X"00",X"BD",X"C0",X"39",X"C5",X"02", + X"27",X"23",X"C5",X"01",X"26",X"0C",X"0C",X"3B",X"0A",X"3C",X"2A",X"19",X"C6",X"1B",X"D7",X"3C", + X"20",X"13",X"0C",X"3C",X"0C",X"3B",X"86",X"1C",X"91",X"3C",X"26",X"09",X"32",X"E8",X"20",X"BD", + X"CA",X"69",X"7E",X"FF",X"C8",X"BD",X"C9",X"7A",X"0D",X"3B",X"27",X"C9",X"D6",X"3C",X"C1",X"09", + X"26",X"25",X"8E",X"C4",X"87",X"BD",X"FF",X"A4",X"5D",X"27",X"1C",X"C1",X"08",X"22",X"05",X"BD", + X"CB",X"99",X"20",X"13",X"8E",X"C4",X"87",X"34",X"10",X"C6",X"01",X"BD",X"FF",X"AD",X"BD",X"CB", + X"99",X"5F",X"35",X"10",X"BD",X"FF",X"AD",X"8D",X"38",X"96",X"3A",X"81",X"06",X"27",X"0E",X"4D", + X"26",X"04",X"86",X"64",X"20",X"02",X"86",X"06",X"97",X"3A",X"4C",X"C6",X"FF",X"BD",X"CA",X"57", + X"4A",X"27",X"19",X"8E",X"CC",X"00",X"34",X"04",X"BD",X"C0",X"39",X"C5",X"0A",X"26",X"04",X"1C", + X"FE",X"20",X"02",X"1A",X"01",X"35",X"04",X"56",X"26",X"E3",X"0F",X"3A",X"0F",X"3B",X"7E",X"C7", + X"F5",X"31",X"62",X"8E",X"10",X"80",X"BD",X"C0",X"58",X"BD",X"C9",X"1F",X"96",X"3C",X"4C",X"BD", + X"C9",X"02",X"BD",X"C9",X"10",X"ED",X"84",X"D6",X"3C",X"58",X"58",X"8E",X"CC",X"D6",X"3A",X"10", + X"AE",X"84",X"EE",X"02",X"30",X"6E",X"A6",X"A0",X"81",X"2F",X"27",X"04",X"A7",X"80",X"20",X"F6", + X"1F",X"30",X"33",X"62",X"8E",X"C4",X"00",X"3A",X"BD",X"FF",X"A4",X"34",X"06",X"D6",X"3C",X"5C", + X"C1",X"07",X"22",X"13",X"35",X"06",X"1F",X"98",X"BD",X"C9",X"10",X"ED",X"47",X"BD",X"FF",X"A1", + X"BD",X"C9",X"10",X"ED",X"49",X"20",X"13",X"C1",X"08",X"26",X"09",X"CC",X"30",X"30",X"ED",X"49", + X"33",X"5E",X"20",X"E0",X"35",X"06",X"1F",X"98",X"20",X"E6",X"8E",X"10",X"80",X"31",X"62",X"7E", + X"C0",X"5F",X"34",X"04",X"1F",X"89",X"86",X"99",X"8B",X"01",X"19",X"5A",X"2A",X"FA",X"35",X"84", + X"1F",X"89",X"84",X"F0",X"44",X"44",X"44",X"44",X"8B",X"30",X"C4",X"0F",X"CB",X"30",X"39",X"86", + X"20",X"1F",X"89",X"5A",X"30",X"64",X"A7",X"80",X"5A",X"26",X"FB",X"86",X"2F",X"A7",X"80",X"30", + X"64",X"39",X"8C",X"C4",X"81",X"26",X"1A",X"BD",X"FF",X"A7",X"30",X"1C",X"1E",X"89",X"8B",X"10", + X"19",X"24",X"07",X"1E",X"89",X"8B",X"01",X"19",X"1E",X"89",X"1E",X"89",X"0C",X"3B",X"7E",X"FF", + X"B0",X"BD",X"FF",X"A1",X"8B",X"01",X"19",X"30",X"1E",X"0C",X"3B",X"7E",X"FF",X"AA",X"8C",X"C4", + X"81",X"26",X"10",X"BD",X"FF",X"A7",X"30",X"1C",X"1E",X"89",X"8B",X"90",X"19",X"1E",X"89",X"89", + X"99",X"20",X"D4",X"BD",X"FF",X"A1",X"8B",X"99",X"20",X"DC",X"D6",X"3C",X"5C",X"C1",X"07",X"22", + X"01",X"39",X"C1",X"09",X"23",X"11",X"C1",X"10",X"22",X"0D",X"C1",X"0A",X"27",X"09",X"8E",X"C4", + X"87",X"BD",X"FF",X"A1",X"4D",X"26",X"EA",X"5A",X"58",X"58",X"8E",X"CC",X"D6",X"3A",X"E6",X"03", + X"8E",X"C4",X"00",X"3A",X"34",X"10",X"BD",X"CA",X"57",X"8E",X"CC",X"00",X"BD",X"C0",X"39",X"C5", + X"02",X"27",X"02",X"35",X"90",X"C5",X"08",X"26",X"04",X"0F",X"3A",X"20",X"E9",X"35",X"10",X"8C", + X"C4",X"7D",X"26",X"0C",X"34",X"14",X"8E",X"C4",X"00",X"C6",X"01",X"BD",X"C0",X"36",X"35",X"14", + X"54",X"10",X"25",X"FF",X"5D",X"7E",X"C9",X"5E",X"02",X"03",X"04",X"10",X"18",X"20",X"40",X"80", + X"00",X"FF",X"11",X"EE",X"22",X"DD",X"33",X"CC",X"44",X"BB",X"55",X"AA",X"66",X"99",X"77",X"88", + X"13",X"1B",X"1C",X"00",X"C5",X"E3",X"C7",X"6F",X"C7",X"7F",X"C7",X"83",X"C7",X"87",X"05",X"05", + X"28",X"28",X"80",X"80",X"00",X"00",X"AD",X"AD",X"2D",X"2D",X"A8",X"A8",X"85",X"85",X"8E",X"CC", + X"00",X"10",X"8E",X"00",X"64",X"BD",X"CA",X"44",X"BD",X"C0",X"39",X"C5",X"02",X"26",X"F6",X"BD", + X"CA",X"44",X"BD",X"C0",X"39",X"C5",X"02",X"27",X"F6",X"39",X"BD",X"FF",X"BC",X"8D",X"3A",X"BD", + X"CA",X"F9",X"0A",X"49",X"2A",X"02",X"0F",X"49",X"39",X"10",X"8E",X"00",X"01",X"8D",X"05",X"0D", + X"49",X"27",X"FA",X"39",X"34",X"23",X"8D",X"21",X"0D",X"49",X"26",X"09",X"86",X"B2",X"4A",X"26", + X"FD",X"31",X"3F",X"26",X"F1",X"35",X"A3",X"34",X"24",X"D6",X"49",X"0F",X"49",X"10",X"8E",X"00", + X"0A",X"8D",X"E1",X"DB",X"49",X"D7",X"49",X"35",X"A4",X"34",X"15",X"C6",X"38",X"8E",X"C3",X"FC", + X"BD",X"C0",X"36",X"8E",X"CC",X"00",X"BD",X"C0",X"39",X"53",X"C4",X"03",X"27",X"02",X"1C",X"FE", + X"D6",X"47",X"56",X"D7",X"47",X"26",X"02",X"D7",X"48",X"53",X"26",X"09",X"D6",X"48",X"26",X"05", + X"53",X"D7",X"48",X"0C",X"49",X"35",X"95",X"34",X"34",X"8E",X"C0",X"00",X"E6",X"A0",X"BD",X"C0", + X"36",X"30",X"01",X"8C",X"C0",X"10",X"26",X"F4",X"35",X"B4",X"34",X"14",X"54",X"56",X"56",X"56", + X"2A",X"01",X"5C",X"56",X"56",X"8E",X"CC",X"00",X"BD",X"C0",X"36",X"58",X"58",X"58",X"CA",X"3F", + X"8E",X"CC",X"02",X"BD",X"C0",X"36",X"35",X"94",X"34",X"26",X"86",X"02",X"10",X"8E",X"01",X"F4", + X"BD",X"CA",X"AA",X"BD",X"CA",X"44",X"5F",X"BD",X"CA",X"AA",X"BD",X"CA",X"44",X"E6",X"61",X"4A", + X"26",X"EE",X"35",X"26",X"34",X"06",X"0F",X"52",X"0F",X"49",X"86",X"01",X"97",X"48",X"86",X"03", + X"97",X"36",X"CC",X"FF",X"FF",X"DD",X"59",X"35",X"86",X"34",X"14",X"5F",X"8E",X"C0",X"00",X"BD", + X"C0",X"36",X"30",X"01",X"8C",X"C0",X"10",X"26",X"F6",X"35",X"94",X"34",X"14",X"53",X"C4",X"3F", + X"8E",X"CC",X"02",X"BD",X"C0",X"36",X"BD",X"CA",X"57",X"C6",X"3F",X"BD",X"C0",X"36",X"BD",X"CA", + X"57",X"35",X"94",X"34",X"02",X"1F",X"98",X"84",X"0F",X"8B",X"00",X"19",X"C4",X"F0",X"27",X"07", + X"8B",X"16",X"19",X"C0",X"10",X"20",X"F7",X"1F",X"89",X"35",X"82",X"34",X"16",X"CC",X"00",X"00", + X"8E",X"00",X"00",X"9F",X"3D",X"30",X"89",X"0F",X"00",X"ED",X"83",X"9C",X"3D",X"26",X"FA",X"30", + X"89",X"09",X"00",X"4D",X"26",X"03",X"8E",X"0F",X"00",X"BD",X"CA",X"69",X"0D",X"49",X"26",X"05", + X"C3",X"11",X"11",X"24",X"DE",X"35",X"96",X"BD",X"CA",X"F9",X"8E",X"00",X"00",X"10",X"8E",X"C9", + X"E0",X"9F",X"3D",X"30",X"89",X"0F",X"00",X"A6",X"A0",X"1F",X"89",X"ED",X"83",X"9C",X"3D",X"26", + X"FA",X"30",X"89",X"09",X"00",X"4D",X"26",X"03",X"8E",X"0F",X"00",X"BD",X"CA",X"69",X"0D",X"49", + X"26",X"06",X"10",X"8C",X"C9",X"F0",X"26",X"D9",X"39",X"8E",X"C4",X"87",X"BD",X"FF",X"AD",X"58", + X"34",X"04",X"58",X"EB",X"E0",X"8E",X"CF",X"10",X"3A",X"10",X"8E",X"C4",X"89",X"C6",X"06",X"34", + X"02",X"A6",X"80",X"1E",X"12",X"BD",X"FF",X"AA",X"1E",X"12",X"5A",X"26",X"F4",X"35",X"82",X"C6", + X"0E",X"20",X"01",X"5F",X"8E",X"C4",X"00",X"4F",X"BD",X"FF",X"AA",X"5A",X"26",X"FA",X"39",X"34", + X"36",X"8D",X"F0",X"8E",X"CE",X"CF",X"10",X"8E",X"C4",X"1D",X"C6",X"47",X"8D",X"D1",X"35",X"B6", + X"34",X"16",X"86",X"01",X"20",X"02",X"34",X"16",X"C4",X"07",X"27",X"1F",X"58",X"58",X"8E",X"C3", + X"FD",X"3A",X"BD",X"FF",X"A4",X"34",X"04",X"BD",X"FF",X"A4",X"34",X"04",X"AB",X"E0",X"19",X"1E", + X"89",X"35",X"02",X"89",X"00",X"19",X"30",X"1C",X"BD",X"FF",X"B0",X"35",X"96",X"34",X"12",X"9B", + X"37",X"19",X"24",X"02",X"86",X"99",X"97",X"37",X"8E",X"C4",X"7D",X"BD",X"FF",X"AA",X"35",X"92", + X"34",X"16",X"C6",X"03",X"20",X"0A",X"34",X"16",X"C6",X"02",X"20",X"04",X"34",X"16",X"C6",X"01", + X"BD",X"CB",X"E0",X"58",X"8E",X"C4",X"87",X"3A",X"BD",X"FF",X"A4",X"8D",X"62",X"96",X"39",X"34", + X"04",X"AB",X"E4",X"97",X"39",X"96",X"38",X"AB",X"E0",X"97",X"38",X"8E",X"C4",X"93",X"BD",X"FF", + X"A4",X"8D",X"4C",X"34",X"04",X"A1",X"E0",X"24",X"02",X"35",X"96",X"8E",X"C4",X"8F",X"BD",X"FF", + X"A4",X"8D",X"3C",X"8D",X"24",X"34",X"02",X"D7",X"38",X"8E",X"C4",X"91",X"BD",X"FF",X"A4",X"96", + X"39",X"8D",X"2C",X"8D",X"14",X"4D",X"27",X"04",X"0F",X"38",X"0F",X"39",X"AB",X"E0",X"19",X"C6", + X"04",X"BD",X"CB",X"E6",X"BD",X"CC",X"0D",X"35",X"96",X"34",X"04",X"5D",X"26",X"03",X"4F",X"35", + X"84",X"1E",X"89",X"86",X"99",X"8B",X"01",X"19",X"E0",X"E4",X"24",X"F9",X"EB",X"E0",X"39",X"34", + X"02",X"1E",X"89",X"5F",X"4D",X"26",X"02",X"35",X"82",X"8B",X"99",X"19",X"5C",X"20",X"F5",X"34", + X"36",X"8E",X"CE",X"CF",X"10",X"8E",X"C4",X"1D",X"C6",X"30",X"BD",X"CB",X"AF",X"8D",X"02",X"35", + X"B6",X"34",X"36",X"10",X"8E",X"CE",X"CF",X"8E",X"B2",X"60",X"C6",X"30",X"A6",X"A0",X"BD",X"FF", + X"AA",X"5A",X"26",X"F8",X"35",X"B6",X"CD",X"46",X"00",X"01",X"CD",X"51",X"00",X"05",X"CD",X"5E", + X"00",X"09",X"CD",X"6A",X"00",X"0D",X"CD",X"75",X"00",X"11",X"CD",X"7F",X"00",X"15",X"CD",X"8A", + X"00",X"19",X"CD",X"96",X"00",X"81",X"CD",X"A7",X"00",X"85",X"CD",X"B7",X"00",X"87",X"CD",X"C6", + X"00",X"89",X"CD",X"D5",X"00",X"8B",X"CD",X"E6",X"00",X"8D",X"CD",X"F6",X"00",X"8F",X"CE",X"07", + X"00",X"91",X"CE",X"17",X"00",X"93",X"CE",X"25",X"00",X"95",X"CE",X"2F",X"00",X"97",X"CE",X"3D", + X"00",X"99",X"CE",X"4B",X"00",X"9B",X"CE",X"59",X"00",X"9D",X"CE",X"67",X"00",X"9F",X"CE",X"75", + X"00",X"A1",X"CE",X"83",X"00",X"A3",X"CE",X"91",X"00",X"A5",X"CE",X"9F",X"00",X"A7",X"CE",X"AD", + X"00",X"A9",X"CE",X"BC",X"00",X"7D",X"43",X"4F",X"49",X"4E",X"53",X"20",X"4C",X"45",X"46",X"54", + X"2F",X"43",X"4F",X"49",X"4E",X"53",X"20",X"43",X"45",X"4E",X"54",X"45",X"52",X"2F",X"43",X"4F", + X"49",X"4E",X"53",X"20",X"52",X"49",X"47",X"48",X"54",X"2F",X"54",X"4F",X"54",X"41",X"4C",X"20", + X"50",X"41",X"49",X"44",X"2F",X"53",X"48",X"49",X"50",X"53",X"20",X"57",X"4F",X"4E",X"2F",X"54", + X"4F",X"54",X"41",X"4C",X"20",X"54",X"49",X"4D",X"45",X"2F",X"54",X"4F",X"54",X"41",X"4C",X"20", + X"53",X"48",X"49",X"50",X"53",X"2F",X"42",X"4F",X"4E",X"55",X"53",X"20",X"53",X"48",X"49",X"50", + X"20",X"4C",X"45",X"56",X"45",X"4C",X"2F",X"4E",X"55",X"4D",X"42",X"45",X"52",X"20",X"4F",X"46", + X"20",X"53",X"48",X"49",X"50",X"53",X"2F",X"43",X"4F",X"49",X"4E",X"41",X"47",X"45",X"20",X"53", + X"45",X"4C",X"45",X"43",X"54",X"2F",X"4C",X"45",X"46",X"54",X"20",X"43",X"4F",X"49",X"4E",X"20", + X"4D",X"55",X"4C",X"54",X"2F",X"43",X"45",X"4E",X"54",X"45",X"52",X"20",X"43",X"4F",X"49",X"4E", + X"20",X"4D",X"55",X"4C",X"54",X"2F",X"52",X"49",X"47",X"48",X"54",X"20",X"43",X"4F",X"49",X"4E", + X"20",X"4D",X"55",X"4C",X"54",X"2F",X"43",X"4F",X"49",X"4E",X"53",X"20",X"46",X"4F",X"52",X"20", + X"43",X"52",X"45",X"44",X"49",X"54",X"2F",X"43",X"4F",X"49",X"4E",X"53",X"20",X"46",X"4F",X"52", + X"20",X"42",X"4F",X"4E",X"55",X"53",X"2F",X"4D",X"49",X"4E",X"49",X"4D",X"55",X"4D",X"20",X"43", + X"4F",X"49",X"4E",X"53",X"2F",X"46",X"52",X"45",X"45",X"20",X"50",X"4C",X"41",X"59",X"2F",X"47", + X"41",X"4D",X"45",X"20",X"41",X"44",X"4A",X"55",X"53",X"54",X"20",X"31",X"2F",X"47",X"41",X"4D", + X"45",X"20",X"41",X"44",X"4A",X"55",X"53",X"54",X"20",X"32",X"2F",X"47",X"41",X"4D",X"45",X"20", + X"41",X"44",X"4A",X"55",X"53",X"54",X"20",X"33",X"2F",X"47",X"41",X"4D",X"45",X"20",X"41",X"44", + X"4A",X"55",X"53",X"54",X"20",X"34",X"2F",X"47",X"41",X"4D",X"45",X"20",X"41",X"44",X"4A",X"55", + X"53",X"54",X"20",X"35",X"2F",X"47",X"41",X"4D",X"45",X"20",X"41",X"44",X"4A",X"55",X"53",X"54", + X"20",X"36",X"2F",X"47",X"41",X"4D",X"45",X"20",X"41",X"44",X"4A",X"55",X"53",X"54",X"20",X"37", + X"2F",X"47",X"41",X"4D",X"45",X"20",X"41",X"44",X"4A",X"55",X"53",X"54",X"20",X"38",X"2F",X"47", + X"41",X"4D",X"45",X"20",X"41",X"44",X"4A",X"55",X"53",X"54",X"20",X"39",X"2F",X"47",X"41",X"4D", + X"45",X"20",X"41",X"44",X"4A",X"55",X"53",X"54",X"20",X"31",X"30",X"2F",X"53",X"50",X"45",X"43", + X"49",X"41",X"4C",X"20",X"46",X"55",X"4E",X"43",X"54",X"49",X"4F",X"4E",X"2F",X"FF",X"FF",X"02", + X"12",X"70",X"44",X"52",X"4A",X"01",X"83",X"15",X"53",X"41",X"4D",X"01",X"59",X"20",X"4C",X"45", + X"44",X"01",X"42",X"85",X"50",X"47",X"44",X"01",X"25",X"20",X"43",X"52",X"42",X"01",X"10",X"35", + X"4D",X"52",X"53",X"00",X"82",X"65",X"53",X"53",X"52",X"00",X"60",X"10",X"54",X"4D",X"48",X"00", + X"5A",X"01",X"00",X"03",X"03",X"01",X"04",X"01",X"01",X"00",X"00",X"00",X"05",X"15",X"01",X"05", + X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"04",X"01",X"02",X"04",X"00",X"06",X"00",X"01",X"01", + X"00",X"00",X"01",X"04",X"01",X"01",X"00",X"00",X"01",X"16",X"06",X"02",X"00",X"00",X"01",X"04", + X"01",X"02",X"00",X"00",X"01",X"00",X"04",X"01",X"00",X"00",X"01",X"00",X"02",X"01",X"00",X"00", + X"01",X"00",X"02",X"02",X"00",X"00",X"43",X"4F",X"50",X"59",X"52",X"49",X"47",X"48",X"54",X"20", + X"31",X"39",X"38",X"30",X"20",X"2D",X"20",X"57",X"49",X"4C",X"4C",X"49",X"41",X"4D",X"53",X"20", + X"45",X"4C",X"45",X"43",X"54",X"52",X"4F",X"4E",X"49",X"43",X"53",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"4A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"7E",X"C0",X"15",X"7E",X"C0",X"92",X"7E",X"C2",X"62",X"7E",X"C2",X"9A",X"C4",X"50",X"7E",X"C5", + X"D0",X"C6",X"BA",X"C7",X"72",X"DC",X"20",X"C4",X"E0",X"DD",X"17",X"C3",X"26",X"10",X"DD",X"15", + X"0F",X"0F",X"8E",X"C3",X"4F",X"9F",X"09",X"86",X"E0",X"97",X"11",X"BD",X"C2",X"AA",X"8E",X"00", + X"10",X"9C",X"15",X"27",X"12",X"96",X"0D",X"2A",X"04",X"0A",X"11",X"20",X"02",X"0C",X"11",X"BD", + X"C2",X"AA",X"30",X"88",X"20",X"20",X"EA",X"DC",X"09",X"DD",X"03",X"96",X"0F",X"97",X"00",X"96", + X"0D",X"97",X"01",X"96",X"11",X"97",X"02",X"8E",X"B7",X"00",X"9F",X"05",X"8E",X"BA",X"90",X"9F", + X"07",X"DC",X"15",X"83",X"00",X"20",X"DD",X"15",X"10",X"93",X"17",X"2B",X"05",X"BD",X"C1",X"2C", + X"20",X"EF",X"DC",X"03",X"DD",X"0B",X"96",X"00",X"97",X"10",X"96",X"01",X"97",X"0E",X"96",X"02", + X"97",X"12",X"10",X"8E",X"BE",X"20",X"8E",X"00",X"00",X"AF",X"A1",X"10",X"8C",X"BF",X"50",X"26", + X"F8",X"39",X"DC",X"20",X"C4",X"E0",X"93",X"15",X"58",X"49",X"58",X"49",X"58",X"49",X"97",X"00", + X"27",X"20",X"2B",X"10",X"DC",X"15",X"C3",X"00",X"20",X"DD",X"15",X"BD",X"C1",X"CD",X"0A",X"00", + X"26",X"F2",X"20",X"0E",X"DC",X"15",X"83",X"00",X"20",X"DD",X"15",X"BD",X"C1",X"2C",X"0C",X"00", + X"26",X"F2",X"DC",X"20",X"C4",X"E0",X"DD",X"15",X"8E",X"00",X"00",X"10",X"8E",X"BE",X"20",X"10", + X"DF",X"13",X"10",X"DE",X"05",X"C5",X"20",X"26",X"03",X"10",X"DE",X"07",X"86",X"98",X"AF",X"B4", + X"35",X"44",X"ED",X"A4",X"EF",X"B1",X"4A",X"AF",X"B4",X"35",X"44",X"ED",X"A4",X"EF",X"B1",X"4A", + X"AF",X"B4",X"35",X"44",X"ED",X"A4",X"EF",X"B1",X"4A",X"AF",X"B4",X"35",X"44",X"ED",X"A4",X"EF", + X"B1",X"4A",X"AF",X"B4",X"35",X"44",X"ED",X"A4",X"EF",X"B1",X"4A",X"AF",X"B4",X"35",X"44",X"ED", + X"A4",X"EF",X"B1",X"4A",X"AF",X"B4",X"35",X"44",X"ED",X"A4",X"EF",X"B1",X"4A",X"AF",X"B4",X"35", + X"44",X"ED",X"A4",X"EF",X"B1",X"4A",X"26",X"B6",X"10",X"DE",X"13",X"39",X"BD",X"C3",X"23",X"2B", + X"04",X"0A",X"12",X"20",X"02",X"0C",X"12",X"86",X"20",X"95",X"16",X"26",X"48",X"9E",X"07",X"BD", + X"C2",X"F6",X"2B",X"20",X"0A",X"11",X"96",X"11",X"A7",X"84",X"A7",X"89",X"01",X"C8",X"CC",X"70", + X"07",X"ED",X"01",X"ED",X"89",X"01",X"C9",X"30",X"03",X"8C",X"BC",X"58",X"26",X"03",X"8E",X"BA", + X"90",X"9F",X"07",X"39",X"96",X"11",X"A7",X"84",X"A7",X"89",X"01",X"C8",X"4C",X"97",X"11",X"CC", + X"07",X"70",X"ED",X"01",X"ED",X"89",X"01",X"C9",X"30",X"03",X"8C",X"BC",X"58",X"26",X"03",X"8E", + X"BA",X"90",X"9F",X"07",X"39",X"9E",X"05",X"BD",X"C2",X"F6",X"2B",X"20",X"0A",X"11",X"96",X"11", + X"A7",X"84",X"A7",X"89",X"01",X"C8",X"CC",X"70",X"07",X"ED",X"01",X"ED",X"89",X"01",X"C9",X"30", + X"03",X"8C",X"B8",X"C8",X"26",X"03",X"8E",X"B7",X"00",X"9F",X"05",X"39",X"96",X"11",X"A7",X"84", + X"A7",X"89",X"01",X"C8",X"4C",X"97",X"11",X"CC",X"07",X"70",X"ED",X"01",X"ED",X"89",X"01",X"C9", + X"30",X"03",X"8C",X"B8",X"C8",X"26",X"03",X"8E",X"B7",X"00",X"9F",X"05",X"39",X"96",X"0D",X"2A", + X"04",X"0A",X"11",X"20",X"02",X"0C",X"11",X"BD",X"C2",X"AA",X"86",X"20",X"95",X"16",X"27",X"41", + X"9E",X"07",X"30",X"1D",X"8C",X"BA",X"8D",X"26",X"03",X"8E",X"BC",X"55",X"9F",X"07",X"96",X"0E", + X"2A",X"17",X"0A",X"12",X"96",X"12",X"A7",X"84",X"A7",X"89",X"01",X"C8",X"CC",X"07",X"70",X"ED", + X"01",X"ED",X"89",X"01",X"C9",X"BD",X"C2",X"D0",X"39",X"96",X"12",X"A7",X"84",X"A7",X"89",X"01", + X"C8",X"4C",X"97",X"12",X"CC",X"70",X"07",X"ED",X"01",X"ED",X"89",X"01",X"C9",X"BD",X"C2",X"D0", + X"39",X"9E",X"05",X"30",X"1D",X"8C",X"B6",X"FD",X"26",X"03",X"8E",X"B8",X"C5",X"9F",X"05",X"96", + X"0E",X"2A",X"17",X"0A",X"12",X"96",X"12",X"A7",X"84",X"A7",X"89",X"01",X"C8",X"CC",X"07",X"70", + X"ED",X"01",X"ED",X"89",X"01",X"C9",X"BD",X"C2",X"D0",X"39",X"96",X"12",X"A7",X"84",X"A7",X"89", + X"01",X"C8",X"4C",X"97",X"12",X"CC",X"70",X"07",X"ED",X"01",X"ED",X"89",X"01",X"C9",X"BD",X"C2", + X"D0",X"39",X"8E",X"C3",X"50",X"9F",X"0B",X"A6",X"84",X"97",X"0E",X"86",X"07",X"97",X"10",X"86", + X"E0",X"97",X"12",X"8E",X"B3",X"00",X"96",X"12",X"A7",X"80",X"96",X"0E",X"2A",X"04",X"0A",X"12", + X"20",X"02",X"0C",X"12",X"BD",X"C2",X"D0",X"96",X"0E",X"2A",X"04",X"0A",X"12",X"20",X"02",X"0C", + X"12",X"BD",X"C2",X"D0",X"8C",X"B7",X"00",X"26",X"DD",X"39",X"8E",X"00",X"00",X"10",X"8E",X"BE", + X"20",X"AF",X"B1",X"10",X"8C",X"BF",X"50",X"26",X"F8",X"39",X"96",X"0F",X"27",X"0A",X"0A",X"0F", + X"96",X"0D",X"48",X"89",X"00",X"97",X"0D",X"39",X"DE",X"09",X"33",X"41",X"11",X"83",X"C4",X"50", + X"26",X"03",X"CE",X"C3",X"50",X"DF",X"09",X"86",X"07",X"97",X"0F",X"A6",X"C4",X"97",X"0D",X"39", + X"96",X"10",X"27",X"0A",X"0A",X"10",X"96",X"0E",X"48",X"89",X"00",X"97",X"0E",X"39",X"DE",X"0B", + X"33",X"41",X"11",X"83",X"C4",X"50",X"26",X"03",X"CE",X"C3",X"50",X"DF",X"0B",X"86",X"07",X"97", + X"10",X"A6",X"C4",X"97",X"0E",X"39",X"96",X"0F",X"81",X"07",X"27",X"0C",X"0C",X"0F",X"96",X"0D", + X"44",X"24",X"02",X"8B",X"80",X"97",X"0D",X"39",X"DE",X"09",X"11",X"83",X"C3",X"50",X"26",X"03", + X"CE",X"C4",X"50",X"33",X"5F",X"DF",X"09",X"0F",X"0F",X"A6",X"C4",X"44",X"24",X"02",X"8B",X"80", + X"97",X"0D",X"39",X"96",X"10",X"81",X"07",X"27",X"0C",X"0C",X"10",X"96",X"0E",X"44",X"24",X"02", + X"8B",X"80",X"97",X"0E",X"39",X"DE",X"0B",X"11",X"83",X"C3",X"50",X"26",X"03",X"CE",X"C4",X"50", + X"33",X"5F",X"DF",X"0B",X"0F",X"10",X"A6",X"C4",X"44",X"24",X"02",X"8B",X"80",X"97",X"0E",X"39", + X"2A",X"AA",X"AA",X"AA",X"AA",X"AA",X"AB",X"A1",X"D5",X"55",X"55",X"55",X"55",X"55",X"AA",X"BF", + X"FF",X"FF",X"FF",X"C0",X"00",X"00",X"00",X"55",X"55",X"57",X"FF",X"C0",X"01",X"55",X"55",X"55", + X"55",X"55",X"55",X"5F",X"E0",X"15",X"55",X"55",X"57",X"FF",X"F0",X"00",X"15",X"55",X"5F",X"FF", + X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"05",X"55",X"7F",X"FF",X"E0",X"00",X"05",X"55",X"55", + X"55",X"55",X"FC",X"05",X"55",X"55",X"50",X"01",X"FF",X"FF",X"FF",X"C0",X"00",X"0A",X"AA",X"AA", + X"AA",X"FF",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"F0",X"00",X"00",X"1F",X"E0",X"00",X"55",X"55", + X"55",X"40",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"B5",X"57",X"AA",X"AA",X"AA",X"F5",X"7F",X"D5", + X"55",X"55",X"57",X"FF",X"80",X"07",X"E0",X"7F",X"F1",X"55",X"7F",X"FF",X"FF",X"00",X"00",X"00", + X"00",X"00",X"0F",X"EF",X"76",X"91",X"11",X"11",X"5E",X"DB",X"E9",X"84",X"77",X"EC",X"C4",X"87", + X"47",X"98",X"08",X"98",X"3F",X"C3",X"CB",X"DB",X"9F",X"C7",X"5F",X"2F",X"C7",X"7D",X"EF",X"BF", + X"FA",X"4C",X"57",X"2B",X"61",X"EF",X"EF",X"FB",X"F7",X"E8",X"00",X"20",X"40",X"00",X"14",X"04", + X"04",X"3C",X"06",X"00",X"1D",X"07",X"3C",X"E1",X"A5",X"55",X"55",X"45",X"2A",X"AA",X"AA",X"AA", + X"A8",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"56",X"AA",X"AA",X"FE",X"AA", + X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"EA",X"AA",X"AA",X"A8",X"02",X"AA",X"AA",X"AA",X"AA", + X"BF",X"BE",X"3E",X"63",X"FF",X"E0",X"D8",X"1C",X"18",X"2A",X"AB",X"1E",X"77",X"7A",X"AF",X"A8", + X"40",X"70",X"7D",X"40",X"0B",X"FB",X"FA",X"FF",X"C1",X"53",X"54",X"75",X"70",X"03",X"00",X"00", + X"25",X"70",X"07",X"26",X"77",X"00",X"26",X"07",X"70",X"24",X"07",X"70",X"23",X"07",X"70",X"23", + X"70",X"07",X"24",X"07",X"70",X"25",X"70",X"07",X"26",X"77",X"00",X"25",X"07",X"70",X"24",X"07", + X"70",X"23",X"07",X"70",X"21",X"07",X"70",X"22",X"70",X"07",X"24",X"77",X"00",X"24",X"70",X"07", + X"26",X"77",X"00",X"26",X"77",X"00",X"25",X"77",X"00",X"25",X"70",X"07",X"26",X"77",X"00",X"24", + X"07",X"70",X"23",X"70",X"07",X"25",X"77",X"00",X"26",X"70",X"07",X"26",X"77",X"00",X"26",X"77", + X"00",X"25",X"07",X"70",X"23",X"07",X"70",X"22",X"07",X"70",X"21",X"77",X"00",X"21",X"70",X"07", + X"23",X"70",X"07",X"25",X"70",X"07",X"25",X"07",X"70",X"25",X"77",X"00",X"25",X"77",X"00",X"24", + X"77",X"00",X"22",X"07",X"70",X"20",X"07",X"70",X"1E",X"07",X"70",X"1C",X"07",X"70",X"1D",X"70", + X"07",X"1F",X"70",X"07",X"21",X"70",X"07",X"22",X"70",X"07",X"24",X"70",X"07",X"26",X"70",X"07", + X"26",X"77",X"00",X"26",X"77",X"00",X"26",X"77",X"00",X"26",X"77",X"00",X"26",X"77",X"00",X"25", + X"77",X"00",X"25",X"70",X"07",X"26",X"77",X"00",X"24",X"07",X"70",X"23",X"77",X"00",X"24",X"77", + X"00",X"22",X"07",X"70",X"23",X"70",X"07",X"22",X"07",X"70",X"21",X"70",X"07",X"23",X"70",X"07", + X"25",X"70",X"07",X"26",X"77",X"00",X"26",X"07",X"70",X"24",X"07",X"70",X"23",X"07",X"70",X"23", + X"70",X"07",X"24",X"07",X"70",X"25",X"70",X"07",X"26",X"77",X"00",X"25",X"07",X"70",X"24",X"07", + X"70",X"23",X"07",X"70",X"21",X"07",X"70",X"22",X"70",X"07",X"24",X"77",X"00",X"24",X"70",X"07", + X"26",X"77",X"00",X"26",X"77",X"00",X"25",X"77",X"00",X"25",X"70",X"07",X"26",X"77",X"00",X"24", + X"07",X"70",X"23",X"70",X"07",X"25",X"77",X"00",X"26",X"70",X"07",X"26",X"77",X"00",X"26",X"77", + X"00",X"25",X"07",X"70",X"23",X"07",X"70",X"22",X"07",X"70",X"21",X"77",X"00",X"21",X"70",X"07", + X"23",X"70",X"07",X"25",X"70",X"07",X"25",X"07",X"70",X"25",X"77",X"00",X"25",X"77",X"00",X"24", + X"77",X"00",X"22",X"07",X"70",X"20",X"07",X"70",X"1E",X"07",X"70",X"1C",X"07",X"70",X"1D",X"70", + X"07",X"1F",X"70",X"07",X"21",X"70",X"07",X"22",X"70",X"07",X"24",X"70",X"07",X"26",X"70",X"07", + X"26",X"77",X"00",X"26",X"77",X"00",X"26",X"77",X"00",X"26",X"77",X"00",X"26",X"77",X"00",X"25", + X"77",X"00",X"25",X"70",X"07",X"26",X"77",X"00",X"24",X"07",X"70",X"23",X"77",X"00",X"24",X"77", + X"00",X"22",X"07",X"70",X"23",X"70",X"07",X"22",X"07",X"70",X"21",X"70",X"07",X"23",X"70",X"07", + X"35",X"06",X"ED",X"49",X"9F",X"00",X"CC",X"08",X"08",X"DD",X"04",X"CC",X"17",X"32",X"DD",X"06", + X"10",X"8E",X"B3",X"00",X"96",X"00",X"5F",X"ED",X"22",X"96",X"01",X"ED",X"24",X"96",X"05",X"44", + X"98",X"05",X"44",X"44",X"06",X"04",X"06",X"05",X"96",X"04",X"84",X"01",X"80",X"01",X"D6",X"05", + X"ED",X"26",X"2A",X"02",X"43",X"53",X"34",X"06",X"96",X"07",X"44",X"98",X"07",X"44",X"44",X"06", + X"06",X"06",X"07",X"96",X"06",X"84",X"03",X"80",X"02",X"D6",X"07",X"ED",X"28",X"2A",X"02",X"43", + X"53",X"44",X"56",X"E3",X"E1",X"10",X"83",X"01",X"6A",X"24",X"B9",X"8E",X"00",X"00",X"AF",X"A4", + X"31",X"2A",X"10",X"8C",X"B8",X"00",X"26",X"AC",X"8E",X"C6",X"AB",X"9F",X"02",X"86",X"38",X"97", + X"01",X"86",X"01",X"8E",X"C6",X"49",X"7E",X"FF",X"D1",X"8E",X"00",X"00",X"10",X"8E",X"B3",X"00", + X"A6",X"9F",X"A0",X"02",X"97",X"31",X"27",X"50",X"EE",X"A4",X"AF",X"C4",X"AF",X"C9",X"01",X"00", + X"EC",X"28",X"E3",X"24",X"81",X"2A",X"25",X"28",X"ED",X"24",X"A7",X"21",X"EC",X"26",X"E3",X"22", + X"81",X"98",X"22",X"1C",X"ED",X"22",X"A7",X"A4",X"5D",X"2B",X"07",X"CC",X"BB",X"BB",X"ED",X"B4", + X"20",X"0E",X"EE",X"A4",X"CC",X"0B",X"0B",X"ED",X"C4",X"CC",X"B0",X"B0",X"ED",X"C9",X"01",X"00", + X"31",X"2A",X"10",X"8C",X"B8",X"00",X"26",X"C0",X"0A",X"01",X"26",X"A5",X"DE",X"02",X"33",X"41", + X"DF",X"02",X"86",X"04",X"97",X"01",X"20",X"99",X"6E",X"D8",X"09",X"FF",X"7F",X"3F",X"37",X"2F", + X"27",X"1F",X"17",X"07",X"06",X"05",X"04",X"03",X"02",X"00",X"14",X"00",X"00",X"00",X"0F",X"14", + X"14",X"14",X"03",X"00",X"00",X"00",X"00",X"03",X"04",X"05",X"06",X"00",X"00",X"00",X"00",X"01", + X"03",X"04",X"0A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0A",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"1E",X"00",X"00",X"00",X"1E",X"19",X"14",X"10",X"05",X"00",X"00",X"00",X"05",X"05", + X"05",X"05",X"60",X"00",X"03",X"02",X"16",X"1E",X"26",X"2E",X"01",X"00",X"00",X"00",X"00",X"00", + X"01",X"01",X"FF",X"00",X"10",X"00",X"70",X"B0",X"00",X"00",X"80",X"10",X"FC",X"FE",X"4A",X"3A", + X"2A",X"2A",X"30",X"00",X"00",X"00",X"20",X"28",X"2C",X"30",X"02",X"00",X"00",X"00",X"01",X"01", + X"02",X"02",X"01",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"FF",X"00",X"08",X"06",X"62",X"E0", + X"02",X"12",X"60",X"00",X"08",X"04",X"0C",X"1C",X"24",X"28",X"FF",X"08",X"FE",X"FE",X"2A",X"22", + X"1E",X"1C",X"60",X"00",X"08",X"02",X"16",X"1E",X"20",X"22",X"28",X"0A",X"FE",X"FF",X"19",X"19", + X"19",X"19",X"3F",X"00",X"00",X"00",X"1F",X"1F",X"1F",X"3F",X"C0",X"18",X"F4",X"FC",X"D4",X"C4", + X"A4",X"94",X"0A",X"03",X"FF",X"FF",X"0F",X"0D",X"0C",X"0A",X"C8",X"28",X"F4",X"F8",X"F0",X"DC", + X"C8",X"C8",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"8E",X"C0",X"0C",X"7E",X"C0",X"36",X"C6", + X"28",X"20",X"F1",X"C6",X"80",X"20",X"ED",X"10",X"8E",X"C9",X"FE",X"BD",X"CA",X"97",X"7E",X"CB", + X"3B",X"C6",X"A5",X"8E",X"C0",X"01",X"7E",X"C0",X"36",X"BD",X"CA",X"69",X"BD",X"CA",X"2A",X"8D", + X"F0",X"CE",X"C0",X"D7",X"8E",X"28",X"20",X"BD",X"CA",X"69",X"BD",X"C0",X"3C",X"10",X"8E",X"C0", + X"61",X"BD",X"C0",X"6D",X"10",X"8E",X"05",X"DC",X"BD",X"CA",X"44",X"0D",X"49",X"26",X"60",X"0F", + X"3C",X"86",X"01",X"97",X"3B",X"32",X"E8",X"E0",X"BD",X"FF",X"BC",X"CE",X"C0",X"D7",X"8E",X"28", + X"20",X"BD",X"CA",X"69",X"BD",X"C0",X"3C",X"0F",X"3A",X"10",X"8E",X"C0",X"65",X"BD",X"C0",X"66", + X"BD",X"CA",X"69",X"86",X"20",X"1F",X"89",X"5A",X"30",X"E4",X"A7",X"80",X"5A",X"26",X"FB",X"86", + X"17",X"A7",X"80",X"30",X"E4",X"BD",X"CA",X"57",X"8E",X"CC",X"00",X"BD",X"C0",X"39",X"C5",X"02"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_sound.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_sound.vhd new file mode 100644 index 00000000..fc2af25c --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_sound.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity defender_sound is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of defender_sound is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"FF",X"0F",X"8E",X"00",X"7F",X"CE",X"04",X"00",X"6F",X"01",X"6F",X"03",X"86",X"FF",X"A7",X"00", + X"6F",X"02",X"86",X"37",X"A7",X"03",X"86",X"3C",X"A7",X"01",X"97",X"09",X"4F",X"97",X"07",X"97", + X"04",X"97",X"05",X"97",X"06",X"97",X"08",X"0E",X"20",X"FE",X"16",X"48",X"48",X"48",X"1B",X"CE", + X"00",X"13",X"DF",X"0F",X"CE",X"FD",X"76",X"BD",X"FD",X"21",X"C6",X"09",X"7E",X"FB",X"0A",X"96", + X"1B",X"B7",X"04",X"00",X"96",X"13",X"97",X"1C",X"96",X"14",X"97",X"1D",X"DE",X"18",X"96",X"1C", + X"73",X"04",X"00",X"09",X"27",X"10",X"4A",X"26",X"FA",X"73",X"04",X"00",X"96",X"1D",X"09",X"27", + X"05",X"4A",X"26",X"FA",X"20",X"E8",X"B6",X"04",X"00",X"2B",X"01",X"43",X"8B",X"00",X"B7",X"04", + X"00",X"96",X"1C",X"9B",X"15",X"97",X"1C",X"96",X"1D",X"9B",X"16",X"97",X"1D",X"91",X"17",X"26", + X"CB",X"96",X"1A",X"27",X"06",X"9B",X"13",X"97",X"13",X"26",X"B9",X"39",X"86",X"01",X"97",X"1A", + X"C6",X"03",X"20",X"0A",X"86",X"FE",X"97",X"1A",X"86",X"C0",X"C6",X"10",X"20",X"00",X"97",X"19", + X"86",X"FF",X"B7",X"04",X"00",X"D7",X"15",X"D6",X"15",X"96",X"0A",X"44",X"44",X"44",X"98",X"0A", + X"44",X"76",X"00",X"09",X"76",X"00",X"0A",X"24",X"03",X"73",X"04",X"00",X"96",X"19",X"4A",X"26", + X"FD",X"5A",X"26",X"E5",X"96",X"19",X"9B",X"1A",X"97",X"19",X"26",X"DB",X"39",X"86",X"20",X"97", + X"15",X"97",X"18",X"86",X"01",X"CE",X"00",X"01",X"C6",X"FF",X"20",X"00",X"97",X"13",X"DF",X"16", + X"D7",X"14",X"D6",X"15",X"96",X"0A",X"44",X"44",X"44",X"98",X"0A",X"44",X"76",X"00",X"09",X"76", + X"00",X"0A",X"86",X"00",X"24",X"02",X"96",X"14",X"B7",X"04",X"00",X"DE",X"16",X"09",X"26",X"FD", + X"5A",X"26",X"E1",X"D6",X"14",X"D0",X"13",X"27",X"09",X"DE",X"16",X"08",X"96",X"18",X"27",X"D0", + X"20",X"CC",X"39",X"C6",X"01",X"D7",X"04",X"4F",X"97",X"19",X"20",X"14",X"4F",X"97",X"19",X"C6", + X"03",X"20",X"0D",X"86",X"01",X"97",X"19",X"CE",X"03",X"E8",X"86",X"01",X"C6",X"FF",X"20",X"00", + X"97",X"18",X"D7",X"13",X"DF",X"16",X"7F",X"00",X"15",X"DE",X"16",X"B6",X"04",X"00",X"16",X"54", + X"54",X"54",X"D8",X"0A",X"54",X"76",X"00",X"09",X"76",X"00",X"0A",X"D6",X"13",X"7D",X"00",X"19", + X"27",X"02",X"D4",X"09",X"D7",X"14",X"D6",X"15",X"91",X"0A",X"22",X"12",X"09",X"27",X"26",X"B7", + X"04",X"00",X"DB",X"15",X"99",X"14",X"25",X"16",X"91",X"0A",X"23",X"F0",X"20",X"10",X"09",X"27", + X"14",X"B7",X"04",X"00",X"D0",X"15",X"92",X"14",X"25",X"04",X"91",X"0A",X"22",X"F0",X"96",X"0A", + X"B7",X"04",X"00",X"20",X"B9",X"D6",X"18",X"27",X"B5",X"96",X"13",X"D6",X"15",X"44",X"56",X"44", + X"56",X"44",X"56",X"43",X"50",X"82",X"FF",X"DB",X"15",X"99",X"13",X"D7",X"15",X"97",X"13",X"26", + X"98",X"C1",X"07",X"26",X"94",X"39",X"86",X"FD",X"97",X"0F",X"CE",X"00",X"64",X"DF",X"0B",X"DB", + X"0C",X"96",X"11",X"99",X"0B",X"97",X"11",X"DE",X"0B",X"25",X"04",X"20",X"00",X"20",X"03",X"08", + X"27",X"11",X"DF",X"0B",X"84",X"0F",X"8B",X"9A",X"97",X"10",X"DE",X"0F",X"A6",X"00",X"B7",X"04", + X"00",X"20",X"DC",X"39",X"4F",X"B7",X"04",X"00",X"97",X"11",X"4F",X"91",X"11",X"26",X"03",X"73", + X"04",X"00",X"C6",X"12",X"5A",X"26",X"FD",X"4C",X"2A",X"F1",X"73",X"04",X"00",X"7C",X"00",X"11", + X"2A",X"E8",X"39",X"CE",X"00",X"13",X"6F",X"00",X"08",X"8C",X"00",X"1B",X"26",X"F8",X"86",X"40", + X"97",X"13",X"CE",X"00",X"13",X"86",X"80",X"97",X"11",X"5F",X"A6",X"01",X"AB",X"00",X"A7",X"01", + X"2A",X"02",X"DB",X"11",X"74",X"00",X"11",X"08",X"08",X"8C",X"00",X"1B",X"26",X"EC",X"F7",X"04", + X"00",X"7C",X"00",X"12",X"26",X"DC",X"CE",X"00",X"13",X"5F",X"A6",X"00",X"27",X"0B",X"81",X"37", + X"26",X"04",X"C6",X"41",X"E7",X"02",X"6A",X"00",X"5C",X"08",X"08",X"8C",X"00",X"1B",X"26",X"EA", + X"5D",X"26",X"BF",X"39",X"7A",X"00",X"08",X"39",X"7F",X"00",X"08",X"97",X"11",X"CE",X"FD",X"AA", + X"A6",X"00",X"27",X"2D",X"7A",X"00",X"11",X"27",X"06",X"4C",X"BD",X"FD",X"21",X"20",X"F1",X"08", + X"DF",X"0F",X"BD",X"FD",X"21",X"DF",X"0D",X"DE",X"0F",X"A6",X"00",X"97",X"15",X"A6",X"01",X"EE", + X"02",X"DF",X"13",X"8D",X"3E",X"DE",X"0F",X"08",X"08",X"08",X"08",X"DF",X"0F",X"9C",X"0D",X"26", + X"E8",X"7E",X"FD",X"0E",X"86",X"03",X"97",X"08",X"39",X"7A",X"00",X"08",X"27",X"0C",X"D6",X"15", + X"58",X"58",X"58",X"58",X"1B",X"97",X"15",X"4F",X"20",X"FE",X"4A",X"81",X"0B",X"23",X"01",X"4F", + X"CE",X"FE",X"41",X"BD",X"FD",X"21",X"A6",X"00",X"CE",X"FF",X"FF",X"DF",X"13",X"8D",X"04",X"8D", + X"2A",X"20",X"FC",X"CE",X"00",X"16",X"81",X"00",X"27",X"15",X"81",X"03",X"27",X"09",X"C6",X"01", + X"E7",X"00",X"08",X"80",X"02",X"20",X"EF",X"C6",X"91",X"E7",X"00",X"6F",X"01",X"08",X"08",X"C6", + X"7E",X"E7",X"00",X"C6",X"FA",X"E7",X"01",X"C6",X"DD",X"E7",X"02",X"DE",X"13",X"4F",X"F6",X"00", + X"12",X"5C",X"D7",X"12",X"D4",X"15",X"54",X"89",X"00",X"54",X"89",X"00",X"54",X"89",X"00",X"54", + X"89",X"00",X"54",X"89",X"00",X"54",X"89",X"00",X"54",X"89",X"00",X"1B",X"48",X"48",X"48",X"48", + X"B7",X"04",X"00",X"09",X"27",X"03",X"7E",X"00",X"16",X"39",X"36",X"A6",X"00",X"DF",X"0D",X"DE", + X"0F",X"A7",X"00",X"08",X"DF",X"0F",X"DE",X"0D",X"08",X"5A",X"26",X"EF",X"32",X"39",X"4F",X"97", + X"04",X"97",X"05",X"39",X"7F",X"00",X"04",X"96",X"05",X"84",X"7F",X"81",X"1D",X"26",X"01",X"4F", + X"4C",X"97",X"05",X"39",X"86",X"0E",X"BD",X"FB",X"81",X"96",X"05",X"48",X"48",X"43",X"BD",X"FC", + X"39",X"7C",X"00",X"17",X"BD",X"FC",X"3B",X"20",X"F8",X"86",X"03",X"BD",X"F8",X"2A",X"D6",X"06", + X"C1",X"1F",X"26",X"01",X"5F",X"5C",X"D7",X"06",X"86",X"20",X"10",X"5F",X"81",X"14",X"23",X"05", + X"CB",X"0E",X"4A",X"20",X"F7",X"CB",X"05",X"4A",X"26",X"FB",X"D7",X"13",X"BD",X"F8",X"3F",X"20", + X"FB",X"96",X"07",X"26",X"09",X"7C",X"00",X"07",X"86",X"0D",X"8D",X"05",X"20",X"69",X"7E",X"FC", + X"2E",X"16",X"58",X"1B",X"1B",X"1B",X"CE",X"FE",X"EC",X"BD",X"FD",X"21",X"A6",X"00",X"16",X"84", + X"0F",X"97",X"14",X"54",X"54",X"54",X"54",X"D7",X"13",X"A6",X"01",X"16",X"54",X"54",X"54",X"54", + X"D7",X"15",X"84",X"0F",X"97",X"11",X"DF",X"0B",X"CE",X"FE",X"4D",X"7A",X"00",X"11",X"2B",X"08", + X"A6",X"00",X"4C",X"BD",X"FD",X"21",X"20",X"F3",X"DF",X"18",X"BD",X"FC",X"75",X"DE",X"0B",X"A6", + X"02",X"97",X"1A",X"BD",X"FC",X"87",X"DE",X"0B",X"A6",X"03",X"97",X"16",X"A6",X"04",X"97",X"17", + X"A6",X"05",X"16",X"A6",X"06",X"CE",X"FF",X"55",X"BD",X"FD",X"21",X"17",X"DF",X"1B",X"7F",X"00", + X"23",X"BD",X"FD",X"21",X"DF",X"1D",X"39",X"96",X"13",X"97",X"22",X"DE",X"1B",X"DF",X"0D",X"DE", + X"0D",X"A6",X"00",X"9B",X"23",X"97",X"21",X"9C",X"1D",X"27",X"26",X"D6",X"14",X"08",X"DF",X"0D", + X"CE",X"00",X"24",X"96",X"21",X"4A",X"26",X"FD",X"A6",X"00",X"B7",X"04",X"00",X"08",X"9C",X"1F", + X"26",X"F1",X"5A",X"27",X"DA",X"08",X"09",X"08",X"09",X"08",X"09",X"08",X"09",X"01",X"01",X"20", + X"DF",X"96",X"15",X"8D",X"62",X"7A",X"00",X"22",X"26",X"C1",X"96",X"07",X"26",X"46",X"96",X"16", + X"27",X"42",X"7A",X"00",X"17",X"27",X"3D",X"9B",X"23",X"97",X"23",X"DE",X"1B",X"5F",X"96",X"23", + X"7D",X"00",X"16",X"2B",X"06",X"AB",X"00",X"25",X"08",X"20",X"0B",X"AB",X"00",X"27",X"02",X"25", + X"05",X"5D",X"27",X"08",X"20",X"0F",X"5D",X"26",X"03",X"DF",X"1B",X"5C",X"08",X"9C",X"1D",X"26", + X"DD",X"5D",X"26",X"01",X"39",X"DF",X"1D",X"96",X"15",X"27",X"06",X"8D",X"08",X"96",X"1A",X"8D", + X"16",X"7E",X"FB",X"E7",X"39",X"CE",X"00",X"24",X"DF",X"0F",X"DE",X"18",X"E6",X"00",X"08",X"BD", + X"FB",X"0A",X"DE",X"0F",X"DF",X"1F",X"39",X"4D",X"27",X"2B",X"DE",X"18",X"DF",X"0D",X"CE",X"00", + X"24",X"97",X"12",X"DF",X"0F",X"DE",X"0D",X"D6",X"12",X"D7",X"11",X"E6",X"01",X"54",X"54",X"54", + X"54",X"08",X"DF",X"0D",X"DE",X"0F",X"A6",X"00",X"10",X"7A",X"00",X"11",X"26",X"FA",X"A7",X"00", + X"08",X"9C",X"1F",X"26",X"DE",X"39",X"8E",X"00",X"7F",X"B6",X"04",X"02",X"0E",X"43",X"84",X"1F", + X"D6",X"08",X"27",X"09",X"2A",X"03",X"BD",X"FA",X"48",X"4A",X"BD",X"FA",X"89",X"5F",X"81",X"0E", + X"27",X"02",X"D7",X"06",X"81",X"12",X"27",X"02",X"D7",X"07",X"F6",X"EF",X"FD",X"C1",X"7E",X"26", + X"03",X"BD",X"EF",X"FD",X"4D",X"27",X"27",X"4A",X"81",X"0C",X"22",X"08",X"BD",X"FB",X"81",X"BD", + X"FB",X"E7",X"20",X"1A",X"81",X"1B",X"22",X"0E",X"80",X"0D",X"48",X"CE",X"FD",X"58",X"8D",X"21", + X"EE",X"00",X"AD",X"00",X"20",X"08",X"80",X"1C",X"BD",X"F8",X"2A",X"BD",X"F8",X"3F",X"96",X"04", + X"9A",X"05",X"27",X"FE",X"4F",X"97",X"07",X"96",X"04",X"27",X"03",X"7E",X"F9",X"13",X"7E",X"FB", + X"34",X"DF",X"0D",X"9B",X"0E",X"97",X"0E",X"24",X"03",X"7C",X"00",X"0D",X"DE",X"0D",X"39",X"0F", + X"8E",X"00",X"7F",X"CE",X"FF",X"FF",X"5F",X"E9",X"00",X"09",X"8C",X"F8",X"00",X"26",X"F8",X"E1", + X"00",X"27",X"01",X"3E",X"86",X"01",X"BD",X"F8",X"2A",X"BD",X"F8",X"3F",X"F6",X"EF",X"FA",X"C1", + X"7E",X"26",X"DC",X"BD",X"EF",X"FA",X"20",X"D7",X"FB",X"49",X"F9",X"13",X"FB",X"24",X"F8",X"8C", + X"FB",X"71",X"FB",X"1E",X"F8",X"CD",X"F8",X"94",X"F9",X"1C",X"F9",X"23",X"F9",X"A6",X"F9",X"D4", + X"F9",X"F3",X"FA",X"44",X"FA",X"84",X"40",X"01",X"00",X"10",X"E1",X"00",X"80",X"FF",X"FF",X"28", + X"01",X"00",X"08",X"81",X"02",X"00",X"FF",X"FF",X"28",X"81",X"00",X"FC",X"01",X"02",X"00",X"FC", + X"FF",X"FF",X"01",X"00",X"18",X"41",X"04",X"80",X"00",X"FF",X"8C",X"5B",X"B6",X"40",X"BF",X"49", + X"A4",X"73",X"73",X"A4",X"49",X"BF",X"40",X"B6",X"5B",X"8C",X"0C",X"7F",X"1D",X"0F",X"FB",X"7F", + X"23",X"0F",X"15",X"FE",X"08",X"50",X"8B",X"88",X"3E",X"3F",X"02",X"3E",X"7C",X"04",X"03",X"FF", + X"3E",X"3F",X"2C",X"E2",X"7C",X"12",X"0D",X"74",X"7C",X"0D",X"0E",X"41",X"7C",X"23",X"0B",X"50", + X"7C",X"1D",X"29",X"F2",X"7C",X"3F",X"02",X"3E",X"F8",X"04",X"03",X"FF",X"7C",X"3F",X"2C",X"E2", + X"F8",X"12",X"0D",X"74",X"F8",X"0D",X"0E",X"41",X"F8",X"23",X"0B",X"50",X"F8",X"1D",X"2F",X"F2", + X"F8",X"23",X"05",X"A8",X"F8",X"12",X"06",X"BA",X"F8",X"04",X"07",X"FF",X"7C",X"37",X"04",X"C1", + X"7C",X"23",X"05",X"A8",X"7C",X"12",X"06",X"BA",X"3E",X"04",X"07",X"FF",X"3E",X"37",X"04",X"C1", + X"3E",X"23",X"05",X"A8",X"1F",X"12",X"06",X"BA",X"1F",X"04",X"07",X"FF",X"1F",X"37",X"04",X"C1", + X"1F",X"23",X"16",X"A0",X"FE",X"1D",X"17",X"F9",X"7F",X"37",X"13",X"06",X"7F",X"3F",X"08",X"FA", + X"FE",X"04",X"0F",X"FF",X"FE",X"0D",X"0E",X"41",X"FE",X"23",X"0B",X"50",X"FE",X"1D",X"5F",X"E4", + X"00",X"47",X"3F",X"37",X"30",X"29",X"23",X"1D",X"17",X"12",X"0D",X"08",X"04",X"08",X"7F",X"D9", + X"FF",X"D9",X"7F",X"24",X"00",X"24",X"08",X"00",X"40",X"80",X"00",X"FF",X"00",X"80",X"40",X"10", + X"7F",X"B0",X"D9",X"F5",X"FF",X"F5",X"D9",X"B0",X"7F",X"4E",X"24",X"09",X"00",X"09",X"24",X"4E", + X"10",X"7F",X"C5",X"EC",X"E7",X"BF",X"8D",X"6D",X"6A",X"7F",X"94",X"92",X"71",X"40",X"17",X"12", + X"39",X"10",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"00",X"00", + X"00",X"00",X"48",X"8A",X"95",X"A0",X"AB",X"B5",X"BF",X"C8",X"D1",X"DA",X"E1",X"E8",X"EE",X"F3", + X"F7",X"FB",X"FD",X"FE",X"FF",X"FE",X"FD",X"FB",X"F7",X"F3",X"EE",X"E8",X"E1",X"DA",X"D1",X"C8", + X"BF",X"B5",X"AB",X"A0",X"95",X"8A",X"7F",X"75",X"6A",X"5F",X"54",X"4A",X"40",X"37",X"2E",X"25", + X"1E",X"17",X"11",X"0C",X"08",X"04",X"02",X"01",X"00",X"01",X"02",X"04",X"08",X"0C",X"11",X"17", + X"1E",X"25",X"2E",X"37",X"40",X"4A",X"54",X"5F",X"6A",X"75",X"7F",X"10",X"59",X"7B",X"98",X"AC", + X"B3",X"AC",X"98",X"7B",X"59",X"37",X"19",X"06",X"00",X"06",X"19",X"37",X"81",X"24",X"00",X"00", + X"00",X"16",X"31",X"12",X"05",X"1A",X"FF",X"00",X"27",X"6D",X"11",X"05",X"11",X"01",X"0F",X"01", + X"47",X"11",X"31",X"00",X"01",X"00",X"0D",X"1B",X"F4",X"12",X"00",X"00",X"00",X"14",X"47",X"41", + X"45",X"00",X"00",X"00",X"0F",X"5B",X"21",X"35",X"11",X"FF",X"00",X"0D",X"1B",X"15",X"00",X"00", + X"FD",X"00",X"01",X"69",X"31",X"11",X"00",X"01",X"00",X"03",X"6A",X"01",X"15",X"01",X"01",X"01", + X"01",X"47",X"F6",X"53",X"03",X"00",X"02",X"06",X"94",X"6A",X"10",X"02",X"00",X"02",X"06",X"9A", + X"1F",X"12",X"00",X"FF",X"10",X"04",X"69",X"31",X"11",X"00",X"FF",X"00",X"0D",X"00",X"12",X"06", + X"00",X"FF",X"01",X"09",X"28",X"A0",X"98",X"90",X"88",X"80",X"78",X"70",X"68",X"60",X"58",X"50", + X"44",X"40",X"01",X"01",X"02",X"02",X"04",X"04",X"08",X"08",X"10",X"10",X"30",X"60",X"C0",X"E0", + X"01",X"01",X"02",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0C",X"80",X"7C",X"78", + X"74",X"70",X"74",X"78",X"7C",X"80",X"01",X"01",X"02",X"02",X"04",X"04",X"08",X"08",X"10",X"20", + X"28",X"30",X"38",X"40",X"48",X"50",X"60",X"70",X"80",X"A0",X"B0",X"C0",X"08",X"40",X"08",X"40", + X"08",X"40",X"08",X"40",X"08",X"40",X"08",X"40",X"08",X"40",X"08",X"40",X"08",X"40",X"08",X"40", + X"01",X"02",X"04",X"08",X"09",X"0A",X"0B",X"0C",X"0E",X"0F",X"10",X"12",X"14",X"16",X"40",X"10", + X"08",X"01",X"01",X"01",X"01",X"01",X"02",X"02",X"03",X"03",X"04",X"04",X"05",X"06",X"08",X"0A", + X"0C",X"10",X"14",X"18",X"20",X"30",X"40",X"50",X"40",X"30",X"20",X"10",X"0C",X"0A",X"08",X"07", + X"06",X"05",X"04",X"03",X"02",X"02",X"01",X"01",X"01",X"07",X"08",X"09",X"0A",X"0C",X"08",X"17", + X"18",X"19",X"1A",X"1B",X"1C",X"00",X"00",X"00",X"FC",X"B6",X"F8",X"01",X"FD",X"2F",X"F8",X"01"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_sound_board.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_sound_board.vhd new file mode 100644 index 00000000..5fdd8293 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_sound_board.vhd @@ -0,0 +1,186 @@ +--------------------------------------------------------------------------------- +-- Defender sound board by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- gen_ram.vhd +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- cpu68 - Version 9th Jan 2004 0.8 +-- 6800/01 compatible CPU core +-- GNU public license - December 2002 : John E. Kent +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- Version 0.0 -- 15/10/2017 -- +-- initial version +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity defender_sound_board is +port( + clk_1p79 : in std_logic; + clk_0p89 : in std_logic; + reset : in std_logic; + + select_sound : in std_logic_vector(5 downto 0); + audio_out : out std_logic_vector( 7 downto 0); + + dbg_cpu_addr : out std_logic_vector(15 downto 0) +); +end defender_sound_board; + +architecture struct of defender_sound_board is + + signal reset_n : std_logic; + + signal cpu_clock : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_rw : std_logic; + signal cpu_irq : std_logic; + + signal wram_cs : std_logic; + signal wram_we : std_logic; + signal wram_do : std_logic_vector( 7 downto 0); + + signal rom_cs : std_logic; + signal rom_do : std_logic_vector( 7 downto 0); + +-- pia port a +-- bit 0-7 audio output + +-- pia port b +-- bit 0-4 select sound input (sel0-4) +-- bit 5-6 switch sound/notes/speech on/off +-- bit 7 sel5 + +-- pia io ca/cb +-- ca1 vdd +-- cb1 sound trigger (sel0-5 = 1) +-- ca2 speech data N/C +-- cb2 speech clock N/C + + signal pia_clock : std_logic; + signal pia_rw_n : std_logic; + signal pia_cs : std_logic; + signal pia_irqa : std_logic; + signal pia_irqb : std_logic; + signal pia_do : std_logic_vector( 7 downto 0); + signal pia_pa_o : std_logic_vector( 7 downto 0); + signal pia_pb_i : std_logic_vector( 7 downto 0); + signal pia_cb1_i : std_logic; + +begin + +reset_n <= not reset; + +dbg_cpu_addr <= cpu_addr; +cpu_clock <= clk_0p89; + + +-- pia cs +wram_cs <= '1' when cpu_addr(15 downto 8) = X"00" else '0'; -- 0000-007F +pia_cs <= '1' when cpu_addr(15 downto 12) = X"0" and cpu_addr(10) = '1' else '0'; -- 8400-8403 ? => 0400-0403 +rom_cs <= '1' when cpu_addr(15 downto 12) = X"F" else '0'; -- F800-FFFF + +-- write enables +wram_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and wram_cs = '1' else '0'; +pia_rw_n <= '0' when cpu_rw = '0' and cpu_clock = '1' and pia_cs = '1' else '1'; + +-- mux cpu in data between roms/io/wram +cpu_di <= + wram_do when wram_cs = '1' else + pia_do when pia_cs = '1' else + rom_do when rom_cs = '1' else X"55"; + +-- pia I/O +pia_clock <= clk_1p79; -- 3p58/2 +audio_out <= pia_pa_o; + +pia_pb_i(4 downto 0) <= select_sound(4 downto 0); +pia_pb_i(6 downto 5) <= "11"; -- assume DS1-1 and DS1-2 open +pia_pb_i(7) <= '1'; -- Handshake to ? from rom board (drawings are confusing) + +-- pia Cb1 +pia_cb1_i <= '0' when select_sound = "111111" else '1'; + +-- pia irqs to cpu +cpu_irq <= pia_irqa or pia_irqb; + +-- microprocessor 6800 +main_cpu : entity work.cpu68 +port map( + clk => cpu_clock,-- E clock input (falling edge) + rst => reset, -- reset input (active high) + rw => cpu_rw, -- read not write output + vma => open, -- valid memory address (active high) + address => cpu_addr, -- address bus output + data_in => cpu_di, -- data bus input + data_out => cpu_do, -- data bus output + hold => '0', -- hold input (active high) extend bus cycle + halt => '0', -- halt input (active high) grants DMA + irq => cpu_irq, -- interrupt request input (active high) + nmi => '0', -- non maskable interrupt request input (active high) + test_alu => open, + test_cc => open +); + +-- cpu program rom +cpu_prog_rom : entity work.defender_sound +port map( + clk => clk_1p79, + addr => cpu_addr(10 downto 0), + data => rom_do +); + +-- cpu wram +cpu_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 7) +port map( + clk => clk_1p79, + we => wram_we, + addr => cpu_addr(6 downto 0), + d => cpu_do, + q => wram_do +); + +-- pia +pia : entity work.pia6821 +port map +( + clk => clk_1p79, + rst => reset, + cs => pia_cs, + rw => pia_rw_n, + addr => cpu_addr(1 downto 0), + data_in => cpu_do, + data_out => pia_do, + irqa => pia_irqa, + irqb => pia_irqb, + pa_i => (others => '0'), + pa_o => pia_pa_o, + pa_oe => open, + ca1 => '1', + ca2_i => '0', + ca2_o => open, + ca2_oe => open, + pb_i => pia_pb_i, + pb_o => open, + pb_oe => open, + cb1 => pia_cb1_i, + cb2_i => '0', + cb2_o => open, + cb2_oe => open +); + +end struct; \ No newline at end of file diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/gen_ram.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pia6821.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pia6821.vhd new file mode 100644 index 00000000..d565ae36 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pia6821.vhd @@ -0,0 +1,553 @@ +--===========================================================================-- +-- +-- S Y N T H E Z I A B L E I/O Port C O R E +-- +-- www.OpenCores.Org - May 2004 +-- This core adheres to the GNU public license +-- +-- File name : pia6821.vhd +-- +-- Purpose : Implements 2 x 8 bit parallel I/O ports +-- with programmable data direction registers +-- +-- Dependencies : ieee.Std_Logic_1164 +-- ieee.std_logic_unsigned +-- +-- Author : John E. Kent +-- +--===========================================================================---- +-- +-- Revision History: +-- +-- Date: Revision Author +-- 1 May 2004 0.0 John Kent +-- Initial version developed from ioport.vhd +-- +-- +-- Unkown date 0.0.1 found at Pacedev repository +-- remove High Z output and and oe signal +-- +-- 18 October 2017 0.0.2 DarFpga +-- Set output to low level when in data is in input mode +-- (to avoid infered latch warning) +-- +--===========================================================================---- +-- +-- Memory Map +-- +-- IO + $00 - Port A Data & Direction register +-- IO + $01 - Port A Control register +-- IO + $02 - Port B Data & Direction Direction Register +-- IO + $03 - Port B Control Register +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity pia6821 is + port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic_vector(1 downto 0); + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0); + irqa : out std_logic; + irqb : out std_logic; + pa_i : in std_logic_vector(7 downto 0); + pa_o : out std_logic_vector(7 downto 0); + pa_oe : out std_logic_vector(7 downto 0); + ca1 : in std_logic; + ca2_i : in std_logic; + ca2_o : out std_logic; + ca2_oe : out std_logic; + pb_i : in std_logic_vector(7 downto 0); + pb_o : out std_logic_vector(7 downto 0); + pb_oe : out std_logic_vector(7 downto 0); + cb1 : in std_logic; + cb2_i : in std_logic; + cb2_o : out std_logic; + cb2_oe : out std_logic + ); +end; + +architecture pia_arch of pia6821 is + +signal porta_ddr : std_logic_vector(7 downto 0); +signal porta_data : std_logic_vector(7 downto 0); +signal porta_ctrl : std_logic_vector(5 downto 0); +signal porta_read : std_logic; + +signal portb_ddr : std_logic_vector(7 downto 0); +signal portb_data : std_logic_vector(7 downto 0); +signal portb_ctrl : std_logic_vector(5 downto 0); +signal portb_read : std_logic; +signal portb_write : std_logic; + +signal ca1_del : std_logic; +signal ca1_rise : std_logic; +signal ca1_fall : std_logic; +signal ca1_edge : std_logic; +signal irqa1 : std_logic; + +signal ca2_del : std_logic; +signal ca2_rise : std_logic; +signal ca2_fall : std_logic; +signal ca2_edge : std_logic; +signal irqa2 : std_logic; +signal ca2_out : std_logic; + +signal cb1_del : std_logic; +signal cb1_rise : std_logic; +signal cb1_fall : std_logic; +signal cb1_edge : std_logic; +signal irqb1 : std_logic; + +signal cb2_del : std_logic; +signal cb2_rise : std_logic; +signal cb2_fall : std_logic; +signal cb2_edge : std_logic; +signal irqb2 : std_logic; +signal cb2_out : std_logic; + +begin + +-------------------------------- +-- +-- read I/O port +-- +-------------------------------- + +pia_read : process( addr, cs, + irqa1, irqa2, irqb1, irqb2, + porta_ddr, portb_ddr, + porta_data, portb_data, + porta_ctrl, portb_ctrl, + pa_i, pb_i ) +variable count : integer; +begin + case addr is + when "00" => + for count in 0 to 7 loop + if porta_ctrl(2) = '0' then + data_out(count) <= porta_ddr(count); + porta_read <= '0'; + else + if porta_ddr(count) = '1' then + data_out(count) <= porta_data(count); + else + data_out(count) <= pa_i(count); + end if; + porta_read <= cs; + end if; + end loop; + portb_read <= '0'; + + when "01" => + data_out <= irqa1 & irqa2 & porta_ctrl; + porta_read <= '0'; + portb_read <= '0'; + + when "10" => + for count in 0 to 7 loop + if portb_ctrl(2) = '0' then + data_out(count) <= portb_ddr(count); + portb_read <= '0'; + else + if portb_ddr(count) = '1' then + data_out(count) <= portb_data(count); + else + data_out(count) <= pb_i(count); + end if; + portb_read <= cs; + end if; + end loop; + porta_read <= '0'; + + when "11" => + data_out <= irqb1 & irqb2 & portb_ctrl; + porta_read <= '0'; + portb_read <= '0'; + + when others => + data_out <= "00000000"; + porta_read <= '0'; + portb_read <= '0'; + + end case; +end process; + +--------------------------------- +-- +-- Write I/O ports +-- +--------------------------------- + +pia_write : process( clk, rst, addr, cs, rw, data_in, + porta_ctrl, portb_ctrl, + porta_data, portb_data, + porta_ddr, portb_ddr ) +begin + if rst = '1' then + porta_ddr <= "00000000"; + porta_data <= "00000000"; + porta_ctrl <= "000000"; + portb_ddr <= "00000000"; + portb_data <= "00000000"; + portb_ctrl <= "000000"; + portb_write <= '0'; + elsif clk'event and clk = '1' then + if cs = '1' and rw = '0' then + case addr is + when "00" => + if porta_ctrl(2) = '0' then + porta_ddr <= data_in; + porta_data <= porta_data; + else + porta_ddr <= porta_ddr; + porta_data <= data_in; + end if; + porta_ctrl <= porta_ctrl; + portb_ddr <= portb_ddr; + portb_data <= portb_data; + portb_ctrl <= portb_ctrl; + portb_write <= '0'; + when "01" => + porta_ddr <= porta_ddr; + porta_data <= porta_data; + porta_ctrl <= data_in(5 downto 0); + portb_ddr <= portb_ddr; + portb_data <= portb_data; + portb_ctrl <= portb_ctrl; + portb_write <= '0'; + when "10" => + porta_ddr <= porta_ddr; + porta_data <= porta_data; + porta_ctrl <= porta_ctrl; + if portb_ctrl(2) = '0' then + portb_ddr <= data_in; + portb_data <= portb_data; + portb_write <= '0'; + else + portb_ddr <= portb_ddr; + portb_data <= data_in; + portb_write <= '1'; + end if; + portb_ctrl <= portb_ctrl; + when "11" => + porta_ddr <= porta_ddr; + porta_data <= porta_data; + porta_ctrl <= porta_ctrl; + portb_ddr <= portb_ddr; + portb_data <= portb_data; + portb_ctrl <= data_in(5 downto 0); + portb_write <= '0'; + when others => + porta_ddr <= porta_ddr; + porta_data <= porta_data; + porta_ctrl <= porta_ctrl; + portb_ddr <= portb_ddr; + portb_data <= portb_data; + portb_ctrl <= portb_ctrl; + portb_write <= '0'; + end case; + else + porta_ddr <= porta_ddr; + porta_data <= porta_data; + porta_ctrl <= porta_ctrl; + portb_data <= portb_data; + portb_ddr <= portb_ddr; + portb_ctrl <= portb_ctrl; + portb_write <= '0'; + end if; + end if; +end process; + +--------------------------------- +-- +-- direction control port a +-- +--------------------------------- +porta_direction : process ( porta_data, porta_ddr ) +variable count : integer; +begin + for count in 0 to 7 loop + if porta_ddr(count) = '1' then + pa_o(count) <= porta_data(count); + pa_oe(count) <= '1'; + else + pa_o(count) <= '0'; + pa_oe(count) <= '0'; + end if; + end loop; +end process; + +--------------------------------- +-- +-- CA1 Edge detect +-- +--------------------------------- +ca1_input : process( clk, rst, ca1, ca1_del, + ca1_rise, ca1_fall, ca1_edge, + irqa1, porta_ctrl, porta_read ) +begin + if rst = '1' then + ca1_del <= '0'; + ca1_rise <= '0'; + ca1_fall <= '0'; + ca1_edge <= '0'; + irqa1 <= '0'; + elsif clk'event and clk = '0' then + ca1_del <= ca1; + ca1_rise <= (not ca1_del) and ca1; + ca1_fall <= ca1_del and (not ca1); + if ca1_edge = '1' then + irqa1 <= '1'; + elsif porta_read = '1' then + irqa1 <= '0'; + else + irqa1 <= irqa1; + end if; + end if; + + if porta_ctrl(1) = '0' then + ca1_edge <= ca1_fall; + else + ca1_edge <= ca1_rise; + end if; +end process; + +--------------------------------- +-- +-- CA2 Edge detect +-- +--------------------------------- +ca2_input : process( clk, rst, ca2_i, ca2_del, + ca2_rise, ca2_fall, ca2_edge, + irqa2, porta_ctrl, porta_read ) +begin + if rst = '1' then + ca2_del <= '0'; + ca2_rise <= '0'; + ca2_fall <= '0'; + ca2_edge <= '0'; + irqa2 <= '0'; + elsif clk'event and clk = '0' then + ca2_del <= ca2_i; + ca2_rise <= (not ca2_del) and ca2_i; + ca2_fall <= ca2_del and (not ca2_i); + if porta_ctrl(5) = '0' and ca2_edge = '1' then + irqa2 <= '1'; + elsif porta_read = '1' then + irqa2 <= '0'; + else + irqa2 <= irqa2; + end if; + end if; + + if porta_ctrl(4) = '0' then + ca2_edge <= ca2_fall; + else + ca2_edge <= ca2_rise; + end if; +end process; + +--------------------------------- +-- +-- CA2 output control +-- +--------------------------------- +ca2_output : process( clk, rst, porta_ctrl, porta_read, ca1_edge, ca2_out ) +begin + if rst='1' then + ca2_out <= '0'; + elsif clk'event and clk='0' then + case porta_ctrl(5 downto 3) is + when "100" => -- read PA clears, CA1 edge sets + if porta_read = '1' then + ca2_out <= '0'; + elsif ca1_edge = '1' then + ca2_out <= '1'; + else + ca2_out <= ca2_out; + end if; + when "101" => -- read PA clears, E sets + ca2_out <= not porta_read; + when "110" => -- set low + ca2_out <= '0'; + when "111" => -- set high + ca2_out <= '1'; + when others => -- no change + ca2_out <= ca2_out; + end case; + end if; +end process; + +--------------------------------- +-- +-- CA2 direction control +-- +--------------------------------- +ca2_direction : process( porta_ctrl, ca2_out ) +begin + if porta_ctrl(5) = '0' then + ca2_oe <= '0'; + ca2_o <= '0'; + else + ca2_o <= ca2_out; + ca2_oe <= '1'; + end if; +end process; + +--------------------------------- +-- +-- direction control port b +-- +--------------------------------- +portb_direction : process ( portb_data, portb_ddr ) +variable count : integer; +begin + for count in 0 to 7 loop + if portb_ddr(count) = '1' then + pb_o(count) <= portb_data(count); + pb_oe(count) <= '1'; + else + pb_o(count) <= '0'; + pb_oe(count) <= '0'; + end if; + end loop; +end process; + +--------------------------------- +-- +-- CB1 Edge detect +-- +--------------------------------- +cb1_input : process( clk, rst, cb1, cb1_del, + cb1_rise, cb1_fall, cb1_edge, + irqb1, portb_ctrl, portb_read ) +begin + if rst = '1' then + cb1_del <= '0'; + cb1_rise <= '0'; + cb1_fall <= '0'; + cb1_edge <= '0'; + irqb1 <= '0'; + elsif clk'event and clk = '0' then + cb1_del <= cb1; + cb1_rise <= (not cb1_del) and cb1; + cb1_fall <= cb1_del and (not cb1); + if cb1_edge = '1' then + irqb1 <= '1'; + elsif portb_read = '1' then + irqb1 <= '0'; + else + irqb1 <= irqb1; + end if; + end if; + + if portb_ctrl(1) = '0' then + cb1_edge <= cb1_fall; + else + cb1_edge <= cb1_rise; + end if; +end process; + +--------------------------------- +-- +-- CB2 Edge detect +-- +--------------------------------- +cb2_input : process( clk, rst, cb2_i, cb2_del, + cb2_rise, cb2_fall, cb2_edge, + irqb2, portb_ctrl, portb_read ) +begin + if rst = '1' then + cb2_del <= '0'; + cb2_rise <= '0'; + cb2_fall <= '0'; + cb2_edge <= '0'; + irqb2 <= '0'; + elsif clk'event and clk = '0' then + cb2_del <= cb2_i; + cb2_rise <= (not cb2_del) and cb2_i; + cb2_fall <= cb2_del and (not cb2_i); + if portb_ctrl(5) = '0' and cb2_edge = '1' then + irqb2 <= '1'; + elsif portb_read = '1' then + irqb2 <= '0'; + else + irqb2 <= irqb2; + end if; + end if; + + if portb_ctrl(4) = '0' then + cb2_edge <= cb2_fall; + else + cb2_edge <= cb2_rise; + end if; + +end process; + +--------------------------------- +-- +-- CB2 output control +-- +--------------------------------- +cb2_output : process( clk, rst, portb_ctrl, portb_write, cb1_edge, cb2_out ) +begin + if rst='1' then + cb2_out <= '0'; + elsif clk'event and clk='0' then + case portb_ctrl(5 downto 3) is + when "100" => -- write PB clears, CA1 edge sets + if portb_write = '1' then + cb2_out <= '0'; + elsif cb1_edge = '1' then + cb2_out <= '1'; + else + cb2_out <= cb2_out; + end if; + when "101" => -- write PB clears, E sets + cb2_out <= not portb_write; + when "110" => -- set low + cb2_out <= '0'; + when "111" => -- set high + cb2_out <= '1'; + when others => -- no change + cb2_out <= cb2_out; + end case; + end if; +end process; + +--------------------------------- +-- +-- CB2 direction control +-- +--------------------------------- +cb2_direction : process( portb_ctrl, cb2_out ) +begin + if portb_ctrl(5) = '0' then + cb2_oe <= '0'; + cb2_o <= '0'; + else + cb2_o <= cb2_out; + cb2_oe <= '1'; + end if; +end process; + +--------------------------------- +-- +-- IRQ control +-- +--------------------------------- +pia_irq : process( irqa1, irqa2, irqb1, irqb2, porta_ctrl, portb_ctrl ) +begin + irqa <= (irqa1 and porta_ctrl(0)) or (irqa2 and porta_ctrl(3)); + irqb <= (irqb1 and portb_ctrl(0)) or (irqb2 and portb_ctrl(3)); +end process; + +end pia_arch; + diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.ppf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.ppf new file mode 100644 index 00000000..db79bfc9 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.ppf @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.qip b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.qip new file mode 100644 index 00000000..d4720390 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"] diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.vhd new file mode 100644 index 00000000..b54b7a75 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.vhd @@ -0,0 +1,461 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll_mist.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll_mist IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll_mist; + + +ARCHITECTURE SYN OF pll_mist IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC ; + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire8_bv(0 DOWNTO 0) <= "0"; + sub_wire8 <= To_stdlogicvector(sub_wire8_bv); + sub_wire5 <= sub_wire0(2); + sub_wire4 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + locked <= sub_wire3; + c0 <= sub_wire4; + c2 <= sub_wire5; + sub_wire6 <= inclk0; + sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 3, + clk0_duty_cycle => 50, + clk0_multiply_by => 4, + clk0_phase_shift => "0", + clk1_divide_by => 9, + clk1_duty_cycle => 50, + clk1_multiply_by => 2, + clk1_phase_shift => "0", + clk2_divide_by => 181, + clk2_duty_cycle => 50, + clk2_multiply_by => 12, + clk2_phase_shift => "0", + clk3_divide_by => 91, + clk3_duty_cycle => 50, + clk3_multiply_by => 3, + clk3_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll_mist", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire7, + clk => sub_wire0, + locked => sub_wire3 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "181" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "91" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "1.790055" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.890110" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "12" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "3" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "1.79000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.89000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "181" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "91" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/sdram.sv b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/sdram.sv new file mode 100644 index 00000000..8f927d05 --- /dev/null +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/sdram.sv @@ -0,0 +1,254 @@ +// +// sdram.v +// +// Static RAM controller implementation using SDRAM MT48LC16M16A2 +// +// Copyright (c) 2015,2016 Sorgelig +// +// Some parts of SDRAM code used from project: +// http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// ------------------------------------------ +// +// v2.1 - Add universal 8/16 bit mode. +// + +module sdram +( + input init, // reset to initialize RAM + input clk, // clock ~100MHz + // + // SDRAM_* - signals to the MT48LC16M16 chip + inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus + output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus + output reg SDRAM_DQML, // two byte masks + output reg SDRAM_DQMH, // + output reg [1:0] SDRAM_BA, // two banks + output SDRAM_nCS, // a single chip select + output SDRAM_nWE, // write enable + output SDRAM_nRAS, // row address select + output SDRAM_nCAS, // columns address select + output SDRAM_CKE, // clock enable + // + input [1:0] wtbt, // 16bit mode: bit1 - write high byte, bit0 - write low byte, + // 8bit mode: 2'b00 - use addr[0] to decide which byte to write + // Ignored while reading. + // + input [24:0] addr, // 25 bit address for 8bit mode. addr[0] = 0 for 16bit mode for correct operations. + output [15:0] dout, // data output to cpu + input [15:0] din, // data input from cpu + input we, // cpu requests write + input rd, // cpu requests read + output reg ready // dout is valid. Ready to accept new read/write. +); + +assign SDRAM_nCS = command[3]; +assign SDRAM_nRAS = command[2]; +assign SDRAM_nCAS = command[1]; +assign SDRAM_nWE = command[0]; +assign SDRAM_CKE = cke; + +// no burst configured +localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd2; // 2 for < 100MHz, 3 for >100MHz +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write +localparam MODE = {3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + +localparam sdram_startup_cycles= 14'd12100;// 100us, plus a little more, @ 100MHz +localparam cycles_per_refresh = 14'd186; // (64000*36)/8192-1 Calc'd as (64ms @ 36MHz)/8192 rose +localparam startup_refresh_max = 14'b11111111111111; + +// SDRAM commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg [13:0] refresh_count = startup_refresh_max - sdram_startup_cycles; +reg [3:0] command = CMD_INHIBIT; +reg cke = 0; +reg [24:0] save_addr; +reg [15:0] data; + +assign dout = save_addr[0] ? {data[7:0], data[15:8]} : {data[15:8], data[7:0]}; +typedef enum +{ + STATE_STARTUP, + STATE_OPEN_1, + STATE_WRITE, + STATE_READ, + STATE_IDLE, STATE_IDLE_1, STATE_IDLE_2, STATE_IDLE_3, + STATE_IDLE_4, STATE_IDLE_5, STATE_IDLE_6, STATE_IDLE_7 +} state_t; + +state_t state = STATE_STARTUP; + +always @(posedge clk) begin + reg old_we, old_rd; + reg [CAS_LATENCY:0] data_ready_delay; + + reg [15:0] new_data; + reg [1:0] new_wtbt; + reg new_we; + reg new_rd; + reg save_we = 1; + + + command <= CMD_NOP; + refresh_count <= refresh_count+1'b1; + + data_ready_delay <= {1'b0, data_ready_delay[CAS_LATENCY:1]}; + + if(data_ready_delay[0]) data <= SDRAM_DQ; + + case(state) + STATE_STARTUP: begin + //------------------------------------------------------------------------ + //-- This is the initial startup state, where we wait for at least 100us + //-- before starting the start sequence + //-- + //-- The initialisation is sequence is + //-- * de-assert SDRAM_CKE + //-- * 100us wait, + //-- * assert SDRAM_CKE + //-- * wait at least one cycle, + //-- * PRECHARGE + //-- * wait 2 cycles + //-- * REFRESH, + //-- * tREF wait + //-- * REFRESH, + //-- * tREF wait + //-- * LOAD_MODE_REG + //-- * 2 cycles wait + //------------------------------------------------------------------------ + cke <= 1; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + SDRAM_DQML <= 1; + SDRAM_DQMH <= 1; + SDRAM_A <= 0; + SDRAM_BA <= 0; + + // All the commands during the startup are NOPS, except these + if(refresh_count == startup_refresh_max-31) begin + // ensure all rows are closed + command <= CMD_PRECHARGE; + SDRAM_A[10] <= 1; // all banks + SDRAM_BA <= 2'b00; + end else if (refresh_count == startup_refresh_max-23) begin + // these refreshes need to be at least tREF (66ns) apart + command <= CMD_AUTO_REFRESH; + end else if (refresh_count == startup_refresh_max-15) + command <= CMD_AUTO_REFRESH; + else if (refresh_count == startup_refresh_max-7) begin + // Now load the mode register + command <= CMD_LOAD_MODE; + SDRAM_A <= MODE; + end + + //------------------------------------------------------ + //-- if startup is complete then go into idle mode, + //-- get prepared to accept a new command, and schedule + //-- the first refresh cycle + //------------------------------------------------------ + if(!refresh_count) begin + state <= STATE_IDLE; + ready <= 1; + refresh_count <= 0; + end + end + + STATE_IDLE_7: state <= STATE_IDLE_6; + STATE_IDLE_6: state <= STATE_IDLE_5; + STATE_IDLE_5: state <= STATE_IDLE_4; + STATE_IDLE_4: state <= STATE_IDLE_3; + STATE_IDLE_3: state <= STATE_IDLE_2; + STATE_IDLE_2: state <= STATE_IDLE_1; + STATE_IDLE_1: begin + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + state <= STATE_IDLE; + // mask possible refresh to reduce colliding. + if(refresh_count > cycles_per_refresh) begin + //------------------------------------------------------------------------ + //-- Start the refresh cycle. + //-- This tasks tRFC (66ns), so 2 idle cycles are needed @ 36MHz + //------------------------------------------------------------------------ + state <= STATE_IDLE_2; + command <= CMD_AUTO_REFRESH; + refresh_count <= refresh_count - cycles_per_refresh + 1'd1; + end + end + + STATE_IDLE: begin + // Priority is to issue a refresh if one is outstanding + if(refresh_count > (cycles_per_refresh<<1)) state <= STATE_IDLE_1; + else if(new_rd | new_we) begin + new_we <= 0; + new_rd <= 0; + save_addr<= addr; + save_we <= new_we; + state <= STATE_OPEN_1; + command <= CMD_ACTIVE; + SDRAM_A <= addr[13:1]; + SDRAM_BA <= addr[24:23]; + end + end + + // ACTIVE-to-READ or WRITE delay >20ns (1 cycle @ 36 MHz)(-75) + STATE_OPEN_1: begin + SDRAM_A <= {4'b0010, save_addr[22:14]}; + SDRAM_DQML <= save_we & (new_wtbt ? ~new_wtbt[0] : save_addr[0]); + SDRAM_DQMH <= save_we & (new_wtbt ? ~new_wtbt[1] : ~save_addr[0]); + state <= save_we ? STATE_WRITE : STATE_READ; + end + + STATE_READ: begin + state <= STATE_IDLE_5; + command <= CMD_READ; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + + // Schedule reading the data values off the bus + data_ready_delay[CAS_LATENCY] <= 1; + end + + STATE_WRITE: begin + state <= STATE_IDLE_5; + command <= CMD_WRITE; + SDRAM_DQ <= new_wtbt ? new_data : {new_data[7:0], new_data[7:0]}; + ready <= 1; + end + endcase + + if(init) begin + state <= STATE_STARTUP; + refresh_count <= startup_refresh_max - sdram_startup_cycles; + end + + old_we <= we; + old_rd <= rd; + if(we & ~old_we) {ready, new_we, new_data, new_wtbt} <= {1'b0, 1'b1, din, wtbt}; + else + if((rd & ~old_rd) || (rd & old_rd & (save_addr != addr))) {ready, new_rd} <= {1'b0, 1'b1}; + +end + +endmodule