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https://github.com/Gehstock/Mist_FPGA.git
synced 2026-05-04 15:26:01 +00:00
Moon Patrol: register async reset signals
This commit is contained in:
@@ -65,7 +65,6 @@ architecture struct of moon_patrol_sound_board is
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);
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);
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end component;
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end component;
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signal reset_n : std_logic;
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signal cpu_addr : std_logic_vector(15 downto 0);
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signal cpu_addr : std_logic_vector(15 downto 0);
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signal cpu_di : std_logic_vector( 7 downto 0);
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signal cpu_di : std_logic_vector( 7 downto 0);
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signal cpu_do : std_logic_vector( 7 downto 0);
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signal cpu_do : std_logic_vector( 7 downto 0);
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@@ -152,8 +151,6 @@ architecture struct of moon_patrol_sound_board is
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begin
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begin
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reset_n <= not reset;
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dbg_cpu_addr <= cpu_addr;
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dbg_cpu_addr <= cpu_addr;
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-- cs
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-- cs
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@@ -363,7 +360,7 @@ port map(
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port map (
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port map (
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CLK => clock_E,
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CLK => clock_E,
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CE => '1',
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CE => '1',
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RESET => not reset_n,
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RESET => reset,
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A8 => '1',
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A8 => '1',
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A9_L => port2_data(4),
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A9_L => port2_data(4),
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BDIR => port2_data(0),
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BDIR => port2_data(0),
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@@ -392,7 +389,7 @@ port map(
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port map (
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port map (
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CLK => clock_E,
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CLK => clock_E,
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CE => '1',
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CE => '1',
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RESET => not reset_n,
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RESET => reset,
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A8 => '1',
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A8 => '1',
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A9_L => port2_data(3),
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A9_L => port2_data(3),
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BDIR => port2_data(0),
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BDIR => port2_data(0),
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@@ -38,6 +38,8 @@ architecture SYN of mpatrol is
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signal clk_sys : std_logic;
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signal clk_sys : std_logic;
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signal clk_aud : std_logic;
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signal clk_aud : std_logic;
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signal clk_vid : std_logic;
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signal clk_vid : std_logic;
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signal rst_audD : std_logic;
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signal rst_aud : std_logic;
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signal clkrst_i : from_CLKRST_t;
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signal clkrst_i : from_CLKRST_t;
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signal buttons_i : from_BUTTONS_t;
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signal buttons_i : from_BUTTONS_t;
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signal switches_i : from_SWITCHES_t;
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signal switches_i : from_SWITCHES_t;
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@@ -218,8 +220,19 @@ Clock_inst : entity work.Clock
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end if;
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end if;
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end process;
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end process;
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clkrst_i.arst <= init or status(0) or buttons(1);
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process (clk_sys) begin
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clkrst_i.arst_n <= not clkrst_i.arst;
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if rising_edge(clk_sys) then
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clkrst_i.arst <= init or status(0) or buttons(1);
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clkrst_i.arst_n <= not clkrst_i.arst;
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end if;
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end process;
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process (clk_aud) begin
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if rising_edge(clk_aud) then
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rst_audD <= clkrst_i.arst;
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rst_aud <= rst_audD;
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end if;
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end process;
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GEN_RESETS : for i in 0 to 3 generate
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GEN_RESETS : for i in 0 to 3 generate
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@@ -300,7 +313,7 @@ u_keyboard : keyboard
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moon_patrol_sound_board : entity work.moon_patrol_sound_board
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moon_patrol_sound_board : entity work.moon_patrol_sound_board
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port map(
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port map(
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clock_E => clk_aud,
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clock_E => clk_aud,
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reset => clkrst_i.arst,
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reset => rst_aud,
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select_sound => sound_data,
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select_sound => sound_data,
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audio_out => audio_out,
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audio_out => audio_out,
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dbg_cpu_addr => open
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dbg_cpu_addr => open
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@@ -309,7 +322,7 @@ moon_patrol_sound_board : entity work.moon_patrol_sound_board
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dac : entity work.dac
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dac : entity work.dac
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port map (
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port map (
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clk_i => clk_aud,
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clk_i => clk_aud,
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res_n_i => '1',
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res_n_i => not rst_aud,
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dac_i => audio_out,
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dac_i => audio_out,
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dac_o => audio
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dac_o => audio
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);
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);
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