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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-05-04 15:26:01 +00:00

Moon Patrol: register async reset signals

This commit is contained in:
Gyorgy Szombathelyi
2019-05-30 23:07:50 +02:00
parent 9ee1248e0e
commit b40cd1d3f8
2 changed files with 19 additions and 9 deletions

View File

@@ -65,7 +65,6 @@ architecture struct of moon_patrol_sound_board is
); );
end component; end component;
signal reset_n : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0); signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_di : std_logic_vector( 7 downto 0); signal cpu_di : std_logic_vector( 7 downto 0);
signal cpu_do : std_logic_vector( 7 downto 0); signal cpu_do : std_logic_vector( 7 downto 0);
@@ -152,8 +151,6 @@ architecture struct of moon_patrol_sound_board is
begin begin
reset_n <= not reset;
dbg_cpu_addr <= cpu_addr; dbg_cpu_addr <= cpu_addr;
-- cs -- cs
@@ -363,7 +360,7 @@ port map(
port map ( port map (
CLK => clock_E, CLK => clock_E,
CE => '1', CE => '1',
RESET => not reset_n, RESET => reset,
A8 => '1', A8 => '1',
A9_L => port2_data(4), A9_L => port2_data(4),
BDIR => port2_data(0), BDIR => port2_data(0),
@@ -392,7 +389,7 @@ port map(
port map ( port map (
CLK => clock_E, CLK => clock_E,
CE => '1', CE => '1',
RESET => not reset_n, RESET => reset,
A8 => '1', A8 => '1',
A9_L => port2_data(3), A9_L => port2_data(3),
BDIR => port2_data(0), BDIR => port2_data(0),

View File

@@ -38,6 +38,8 @@ architecture SYN of mpatrol is
signal clk_sys : std_logic; signal clk_sys : std_logic;
signal clk_aud : std_logic; signal clk_aud : std_logic;
signal clk_vid : std_logic; signal clk_vid : std_logic;
signal rst_audD : std_logic;
signal rst_aud : std_logic;
signal clkrst_i : from_CLKRST_t; signal clkrst_i : from_CLKRST_t;
signal buttons_i : from_BUTTONS_t; signal buttons_i : from_BUTTONS_t;
signal switches_i : from_SWITCHES_t; signal switches_i : from_SWITCHES_t;
@@ -218,8 +220,19 @@ Clock_inst : entity work.Clock
end if; end if;
end process; end process;
clkrst_i.arst <= init or status(0) or buttons(1); process (clk_sys) begin
clkrst_i.arst_n <= not clkrst_i.arst; if rising_edge(clk_sys) then
clkrst_i.arst <= init or status(0) or buttons(1);
clkrst_i.arst_n <= not clkrst_i.arst;
end if;
end process;
process (clk_aud) begin
if rising_edge(clk_aud) then
rst_audD <= clkrst_i.arst;
rst_aud <= rst_audD;
end if;
end process;
GEN_RESETS : for i in 0 to 3 generate GEN_RESETS : for i in 0 to 3 generate
@@ -300,7 +313,7 @@ u_keyboard : keyboard
moon_patrol_sound_board : entity work.moon_patrol_sound_board moon_patrol_sound_board : entity work.moon_patrol_sound_board
port map( port map(
clock_E => clk_aud, clock_E => clk_aud,
reset => clkrst_i.arst, reset => rst_aud,
select_sound => sound_data, select_sound => sound_data,
audio_out => audio_out, audio_out => audio_out,
dbg_cpu_addr => open dbg_cpu_addr => open
@@ -309,7 +322,7 @@ moon_patrol_sound_board : entity work.moon_patrol_sound_board
dac : entity work.dac dac : entity work.dac
port map ( port map (
clk_i => clk_aud, clk_i => clk_aud,
res_n_i => '1', res_n_i => not rst_aud,
dac_i => audio_out, dac_i => audio_out,
dac_o => audio dac_o => audio
); );