diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/robotron_cpu.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/robotron_cpu.vhd
index 901b252a..d2eee8b4 100644
--- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/robotron_cpu.vhd	
+++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/robotron_cpu.vhd	
@@ -329,7 +329,8 @@ architecture Behavioral of robotron_cpu is
     signal blt_data_out         : std_logic_vector(7 downto 0);
     signal blt_en_lower         : boolean := false;
     signal blt_en_upper         : boolean := false;
-    
+    signal blt_win_en           : std_logic := '0';
+
     -------------------------------------------------------------------
 
     function to_std_logic(L: boolean) return std_logic is
@@ -408,7 +409,7 @@ begin
     
     address <= blt_address_out when mpu_halted else
                mpu_address;
-    write <= blt_write when mpu_halted else
+    write <= blt_write  when mpu_halted and (blt_win_en = '0' or blt_address_out<x"7400" or blt_address_out>=x"C000") else
              mpu_write;
     read <= blt_read when mpu_halted else
             mpu_read;
@@ -670,6 +671,7 @@ begin
                     end if;
 
                     if control_access and write then
+                        blt_win_en     <= mpu_data_in(2) and sinistar;
                         screen_control <= mpu_data_in(1);
                         e_rom <= mpu_data_in(0);
                     end if;
diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/sc1.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/sc1.vhd
index e3269afb..d40a0fe2 100644
--- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/sc1.vhd	
+++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/sc1.vhd	
@@ -177,6 +177,9 @@ begin
 						blt_shift <= (others => '0');
 
 						state <= state_src;
+						if reg_width = 0 or reg_height = 0 then
+							state <= state_idle;
+						end if;
 					end if;
 
 				when state_src =>
@@ -214,18 +217,18 @@ begin
 							x_count <= (others => '0');
 							y_count <= y_count_next;
 
-							if y_count_next = reg_height then
+							if y_count_next >= reg_height then
 								state <= state_idle;
 							end if;
 
 							if ctrl_span_src = '1' then
-								src_address <= reg_src_base + y_count_next;
+								src_address <= reg_src_base(15 downto 8) & (reg_src_base(7 downto 0) + y_count_next(7 downto 0));
 							else
 								src_address <= src_address + 1;
 							end if;
 
 							if ctrl_span_dst = '1' then
-								dst_address <= reg_dst_base + y_count_next;
+								dst_address <= reg_dst_base(15 downto 8) & (reg_dst_base(7 downto 0) + y_count_next(7 downto 0));
 							else
 								dst_address <= dst_address + 1;
 							end if;