diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/Snapshot/System1.rbf b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/Snapshot/System1.rbf new file mode 100644 index 00000000..ba71e41c Binary files /dev/null and b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/Snapshot/System1.rbf differ diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/Snapshot/System1_MiST.rbf b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/Snapshot/System1_MiST.rbf deleted file mode 100644 index 894d24a1..00000000 Binary files a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/Snapshot/System1_MiST.rbf and /dev/null differ diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1_MiST.qpf b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1.qpf similarity index 97% rename from Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1_MiST.qpf rename to Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1.qpf index a2476c99..24b6f1e3 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1_MiST.qpf +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1.qpf @@ -27,5 +27,5 @@ DATE = "00:21:03 December 03, 2019" # Revisions -PROJECT_REVISION = "System1_MiST" +PROJECT_REVISION = "System1" diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1_MiST.qsf b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1.qsf similarity index 95% rename from Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1_MiST.qsf rename to Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1.qsf index de0cc880..d27cc801 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1_MiST.qsf +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1.qsf @@ -1,6 +1,6 @@ # -------------------------------------------------------------------------- # # -# Copyright (C) 1991-2013 Altera Corporation +# Copyright (C) 1991-2014 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing @@ -17,15 +17,15 @@ # -------------------------------------------------------------------------- # # # Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 04:44:25 May 18, 2020 +# Version 13.1.4 Build 182 03/12/2014 SJ Full Version +# Date created = 23:55:41 May 24, 2020 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: -# System1_MiST_assignment_defaults.qdf +# System1_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # @@ -43,24 +43,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/System1_MiST.sv -set_global_assignment -name VERILOG_FILE rtl/System1_Top.v -set_global_assignment -name VERILOG_FILE rtl/System1_Main.v -set_global_assignment -name VERILOG_FILE rtl/System1_Video.v -set_global_assignment -name VERILOG_FILE rtl/System1_Sound.v -set_global_assignment -name VERILOG_FILE rtl/System1_Sprite.v -set_global_assignment -name VERILOG_FILE rtl/System1_Parts.v -set_global_assignment -name VERILOG_FILE rtl/System1_hvgen.v -set_global_assignment -name VERILOG_FILE rtl/SN76496.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv -set_global_assignment -name VERILOG_FILE rtl/pll_mist.v -set_global_assignment -name VERILOG_FILE rtl/z80ip.v -set_global_assignment -name VERILOG_FILE rtl/DPRAM1024_11B.v -set_global_assignment -name VHDL_FILE rtl/rom/clut.vhd -set_global_assignment -name VHDL_FILE rtl/rom/dec_315_5041.vhd -set_global_assignment -name VHDL_FILE rtl/rom/dec_315_5051.vhd -set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip -set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip # Pin & Location Assignments # ========================== @@ -234,10 +216,26 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # end ENTITY(System1_MiST) -# ------------------------ \ No newline at end of file +# ------------------------ +set_global_assignment -name SYSTEMVERILOG_FILE rtl/System1_MiST.sv +set_global_assignment -name VERILOG_FILE rtl/System1_Top.v +set_global_assignment -name VERILOG_FILE rtl/System1_Main.v +set_global_assignment -name VERILOG_FILE rtl/System1_Video.v +set_global_assignment -name VERILOG_FILE rtl/System1_Sound.v +set_global_assignment -name VERILOG_FILE rtl/System1_Sprite.v +set_global_assignment -name VERILOG_FILE rtl/System1_Parts.v +set_global_assignment -name VERILOG_FILE rtl/System1_hvgen.v +set_global_assignment -name VERILOG_FILE rtl/SN76496.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv +set_global_assignment -name VERILOG_FILE rtl/pll_mist.v +set_global_assignment -name VERILOG_FILE rtl/z80ip.v +set_global_assignment -name VERILOG_FILE rtl/DPRAM1024_11B.v +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1_MiST.sdc b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1.sdc similarity index 100% rename from Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1_MiST.sdc rename to Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1.sdc diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Flicky.mra b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Flicky.mra index c0e311e5..1a897d49 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Flicky.mra +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Flicky.mra @@ -4,11 +4,11 @@ 202001010000 1984 Sega -´ System1_MiST +´ System1 Action flicky - 0 + FF diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/MrViking.mra b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/MrViking.mra index 494a3944..526826f9 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/MrViking.mra +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/MrViking.mra @@ -4,11 +4,11 @@ 202001010000 1985 Sega -´ System1_MiST +´ System1 Action mrviking - 7 + diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/MyHero.mra b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/MyHero.mra index 8eaf7570..7451b15e 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/MyHero.mra +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/MyHero.mra @@ -4,9 +4,10 @@ 202001010000 1985 Sega -´ System1_MiST +´ System1 Action myhero + 5 @@ -30,5 +31,4 @@ FF - 5 \ No newline at end of file diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Main.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Main.v index fcb94e0d..3163cebe 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Main.v +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Main.v @@ -25,7 +25,11 @@ module System1_Main output SNDRQ, output [15:0] cpu_rom_addr, - input [7:0] cpu_rom_do + input [7:0] cpu_rom_do, + input [17:0] dl_addr, + input [7:0] dl_data, + input dl_wr, + input dl_clk ); wire AXSCL = CLK48M; @@ -78,7 +82,7 @@ wire [7:0] cpu_rd_portB = DSW1; wire [7:0] cpu_rd_mrom; wire cpu_cs_mrom = (CPUAD[15:12] < 4'b1100); -PRGROM prom(AXSCL, cpu_m1, CPUAD[14:0], cpu_rd_mrom, cpu_rom_addr,cpu_rom_do ); +PRGROM prom(AXSCL, cpu_m1, CPUAD[14:0], cpu_rd_mrom, cpu_rom_addr[14:0],cpu_rom_do,dl_addr,dl_data,dl_wr,dl_clk ); wire [7:0] cpu_rd_mram; wire cpu_cs_mram = (CPUAD[15:12] == 4'b1100); @@ -120,7 +124,11 @@ module PRGROM input [14:0] mrom_ad, output reg [7:0] mrom_dt, output [14:0] cpu_rom_addr, - input [7:0] cpu_rom_do + input [7:0] cpu_rom_do, + input [17:0] dl_addr, + input [7:0] dl_data, + input dl_wr, + input dl_clk ); reg [15:0] madr; @@ -135,19 +143,18 @@ wire [7:0] dectbl; wire [7:0] mdec = ( mdat & andv ) | ( dectbl ^ xorv ); //DLROM #( 7,8) decrom( clk, decidx, dectbl, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16: 7]==10'b1_1110_0001_0) ); // $1E100-$1E17F -dec_315_5051 dec_315_5051(//todo move to sdram - .clk(clk), - .addr(decidx), - .data(dectbl) -); +wire dec_we = dl_addr[17:7] == 11'b10111000010;//2E100 +dpram#(8,7)decrom( + .clk_a(clk), + .addr_a(decidx), + .q_a(dectbl), + .clk_b(dl_clk), + .addr_b(dl_addr[6:0]), + .we_b(dec_we & dl_wr), + .d_b(dl_data) + ); -//DLROM #(15,8) mainir( clk, madr[14:0], mdat, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2'b0_0) ); // $00000-$07FFF -//prg_rom pgr_rom( -// .clk(clk), -// .addr(madr[14:0]), -// .data(mdat) -//); -assign cpu_rom_addr = madr[15:0]; +assign cpu_rom_addr = madr[14:0]; assign mdat = cpu_rom_do; reg phase = 1'b0; diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_MiST.sv b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_MiST.sv index e1624baa..6300fb26 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_MiST.sv +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_MiST.sv @@ -223,6 +223,7 @@ wire [7:0] ioctl_index; wire ioctl_wr; wire [24:0] ioctl_addr; wire [7:0] ioctl_dout; +wire dl_wr = ioctl_wr && ioctl_addr < 18'h2E180; data_io data_io( .clk_sys ( clk_sys ), @@ -275,7 +276,6 @@ sdram sdram( always @(posedge clk_sys) begin reg ioctl_wr_last = 0; - ioctl_wr_last <= ioctl_wr; if (ioctl_downl) begin if (~ioctl_wr_last && ioctl_wr) begin @@ -320,6 +320,10 @@ System1_Top System1_Top( .spr_rom_do(spr_rom_addr[0] ? spr_rom_do[15:8] : spr_rom_do[7:0] ), .tile_rom_addr(tile_rom_addr), .tile_rom_do(tile_rom_do), + .dl_addr ( ioctl_addr[17:0] ), + .dl_data ( ioctl_dout ), + .dl_wr ( dl_wr ), + .dl_clk(clk_sys), .SOUT(audio) ); diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Parts.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Parts.v index ddb4bd8c..59503a4f 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Parts.v +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Parts.v @@ -95,7 +95,6 @@ end endmodule - module DPRAM1024 ( input clk0, diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Top.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Top.v index 9d77cfd3..496dd259 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Top.v +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Top.v @@ -30,7 +30,11 @@ module System1_Top output [12:0] snd_rom_addr, input [7:0] snd_rom_do, output [13:0] tile_rom_addr, - input [23:0] tile_rom_do + input [23:0] tile_rom_do, + input [17:0] dl_addr, + input [7:0] dl_data, + input dl_wr, + input dl_clk ); // Clocks @@ -63,7 +67,11 @@ System1_Main System1_Main( .VIDDO(VIDDO), .SNDRQ(SNDRQ), .cpu_rom_addr(cpu_rom_addr), - .cpu_rom_do(cpu_rom_do) + .cpu_rom_do(cpu_rom_do), + .dl_addr(dl_addr), + .dl_data(dl_data), + .dl_wr(dl_wr), + .dl_clk(dl_clk) ); System1_Video System1_Video( @@ -85,7 +93,11 @@ System1_Video System1_Video( .spr_rom_addr(spr_rom_addr), .spr_rom_do(spr_rom_do), .tile_rom_addr(tile_rom_addr), - .tile_rom_do(tile_rom_do) + .tile_rom_do(tile_rom_do), + .dl_addr(dl_addr), + .dl_data(dl_data), + .dl_wr(dl_wr), + .dl_clk(dl_clk) ); assign PCLK = clk6M; diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Video.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Video.v index 08c45369..d3a837c7 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Video.v +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Video.v @@ -24,7 +24,11 @@ module System1_Video output [15:0] spr_rom_addr, input [7:0] spr_rom_do, output [13:0] tile_rom_addr, - input [23:0] tile_rom_do + input [23:0] tile_rom_do, + input [17:0] dl_addr, + input [7:0] dl_data, + input dl_wr, + input dl_clk ); // CPU Interface @@ -82,11 +86,6 @@ wire [10:0] SPRPX; wire [15:0] sprchad; wire [7:0] sprchdt; //DLROM #(15,8) sprchr(VCLKx8,sprchad,sprchdt, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2'b0_1)); // $08000-$0FFFF -//spr_rom spr_rom( -// .clk(VCLKx8), -// .addr(sprchad), -// .data(sprchdt) -//); assign spr_rom_addr = sprchad; assign sprchdt = spr_rom_do; @@ -122,11 +121,16 @@ BGGEN bg1(VCLK,BG1HP,BG1VP,vram1ad,vram1dt,tile1ad,tile1dt,BG1PX); // Color Mixer & RGB Output wire [7:0] cltidx,cltval; //DLROM #(8,8) clut(VCLKx2, cltidx, cltval, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:8]==9'b1_1110_0000) ); // $1E000-$1E0FF -clut clut(//todo move to sdram - .clk(VCLKx2), - .addr(cltidx), - .data(cltval) -); +wire clut_we = dl_addr[17:8] == 10'b1011100000;//2E000 +dpram#(8,8)decrom( + .clk_a(VCLKx2), + .addr_a(cltidx), + .q_a(cltval), + .clk_b(dl_clk), + .addr_b(dl_addr[7:0]), + .we_b(clut_we & dl_wr), + .d_b(dl_data) + ); COLMIX cmix( VCLK, diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/dpram.vhd b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..284194c5 --- /dev/null +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/dpram.vhd @@ -0,0 +1,81 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- dpram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity dpram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk_a : in std_logic; + we_a : in std_logic := '0'; + addr_a : in std_logic_vector((aWidth-1) downto 0); + d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0'); + q_a : out std_logic_vector((dWidth-1) downto 0); + + clk_b : in std_logic; + we_b : in std_logic := '0'; + addr_b : in std_logic_vector((aWidth-1) downto 0); + d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0'); + q_b : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of dpram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + signal addr_a_reg: std_logic_vector((aWidth-1) downto 0); + signal addr_b_reg: std_logic_vector((aWidth-1) downto 0); +begin + +-- ----------------------------------------------------------------------- + process(clk_a) + begin + if rising_edge(clk_a) then + if we_a = '1' then + ram(to_integer(unsigned(addr_a))) <= d_a; + end if; + q_a <= ram(to_integer(unsigned(addr_a))); + end if; + end process; + + process(clk_b) + begin + if rising_edge(clk_b) then + if we_b = '1' then + ram(to_integer(unsigned(addr_b))) <= d_b; + end if; + q_b <= ram(to_integer(unsigned(addr_b))); + end if; + end process; + +end architecture; + diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/pll_mist.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/pll_mist.v index cb06e165..82b6f255 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/pll_mist.v +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/pll_mist.v @@ -14,11 +14,11 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// 13.1.4 Build 182 03/12/2014 SJ Full Version // ************************************************************ -//Copyright (C) 1991-2013 Altera Corporation +//Copyright (C) 1991-2014 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/rom/clut.vhd b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/rom/clut.vhd deleted file mode 100644 index c4034af7..00000000 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/rom/clut.vhd +++ /dev/null @@ -1,38 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity clut is -port ( - clk : in std_logic; - addr : in std_logic_vector(7 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of clut is - type rom is array(0 to 255) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"0C",X"0E",X"0C",X"0E",X"0D",X"0D",X"0C",X"0E",X"00",X"0E",X"0C",X"0E",X"01",X"0D",X"0C",X"0E", - X"0C",X"0D",X"0C",X"0E",X"0D",X"0D",X"0C",X"0E",X"00",X"0D",X"0C",X"0E",X"01",X"0D",X"0C",X"0E", - X"0E",X"0E",X"0E",X"0E",X"0D",X"0D",X"0E",X"0E",X"02",X"0E",X"0E",X"0E",X"01",X"0D",X"0E",X"0E", - X"0C",X"0D",X"0C",X"0E",X"0D",X"0D",X"0C",X"0E",X"00",X"0D",X"0C",X"0E",X"01",X"0D",X"0C",X"0E", - X"08",X"0E",X"08",X"0E",X"09",X"0D",X"08",X"0E",X"08",X"0E",X"08",X"0E",X"09",X"0D",X"08",X"0E", - X"0C",X"0D",X"0C",X"0E",X"0D",X"0D",X"0C",X"0E",X"00",X"0D",X"0C",X"0E",X"01",X"0D",X"0C",X"0E", - X"0A",X"0E",X"0A",X"0E",X"09",X"0D",X"0A",X"0E",X"0A",X"0E",X"0A",X"0E",X"09",X"0D",X"0A",X"0E", - X"0C",X"0D",X"0C",X"0E",X"0D",X"0D",X"0C",X"0E",X"00",X"0D",X"0C",X"0E",X"01",X"0D",X"0C",X"0E", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/rom/dec_315_5041.vhd b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/rom/dec_315_5041.vhd deleted file mode 100644 index 76f953d0..00000000 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/rom/dec_315_5041.vhd +++ /dev/null @@ -1,30 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity dec_315_5041 is -port ( - clk : in std_logic; - addr : in std_logic_vector(6 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of dec_315_5041 is - type rom is array(0 to 127) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"28",X"A8",X"08",X"88",X"88",X"80",X"08",X"00",X"88",X"08",X"80",X"00",X"88",X"80",X"08",X"00", - X"28",X"08",X"A8",X"88",X"28",X"A8",X"08",X"88",X"88",X"08",X"80",X"00",X"88",X"08",X"80",X"00", - X"28",X"08",X"A8",X"88",X"88",X"80",X"08",X"00",X"88",X"80",X"08",X"00",X"28",X"A8",X"08",X"88", - X"A0",X"80",X"A8",X"88",X"28",X"08",X"A8",X"88",X"A0",X"80",X"A8",X"88",X"A0",X"80",X"A8",X"88", - X"88",X"80",X"08",X"00",X"88",X"80",X"08",X"00",X"88",X"08",X"80",X"00",X"88",X"80",X"08",X"00", - X"A0",X"80",X"20",X"00",X"28",X"08",X"A8",X"88",X"A0",X"80",X"20",X"00",X"88",X"08",X"80",X"00", - X"28",X"08",X"A8",X"88",X"A0",X"80",X"20",X"00",X"A0",X"80",X"20",X"00",X"A0",X"80",X"20",X"00", - X"A0",X"80",X"A8",X"88",X"28",X"08",X"A8",X"88",X"A0",X"80",X"20",X"00",X"A0",X"80",X"A8",X"88"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/rom/dec_315_5051.vhd b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/rom/dec_315_5051.vhd deleted file mode 100644 index 7126e72a..00000000 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/rom/dec_315_5051.vhd +++ /dev/null @@ -1,30 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity dec_315_5051 is -port ( - clk : in std_logic; - addr : in std_logic_vector(6 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of dec_315_5051 is - type rom is array(0 to 127) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"08",X"88",X"00",X"80",X"A0",X"80",X"A8",X"88",X"80",X"00",X"A0",X"20",X"88",X"80",X"08",X"00", - X"A0",X"80",X"A8",X"88",X"28",X"08",X"20",X"00",X"28",X"08",X"20",X"00",X"A0",X"80",X"A8",X"88", - X"08",X"88",X"00",X"80",X"80",X"00",X"A0",X"20",X"80",X"00",X"A0",X"20",X"88",X"80",X"08",X"00", - X"28",X"08",X"20",X"00",X"28",X"08",X"20",X"00",X"28",X"08",X"20",X"00",X"88",X"80",X"08",X"00", - X"08",X"88",X"00",X"80",X"A8",X"88",X"28",X"08",X"A8",X"88",X"28",X"08",X"80",X"00",X"A0",X"20", - X"28",X"08",X"20",X"00",X"88",X"80",X"08",X"00",X"A8",X"88",X"28",X"08",X"88",X"80",X"08",X"00", - X"08",X"88",X"00",X"80",X"80",X"00",X"A0",X"20",X"A8",X"88",X"28",X"08",X"80",X"00",X"A0",X"20", - X"28",X"08",X"20",X"00",X"28",X"08",X"20",X"00",X"08",X"88",X"00",X"80",X"88",X"80",X"08",X"00"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture;