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This commit is contained in:
Marcel
2019-07-15 17:52:51 +02:00
parent b1dcd8431c
commit b8db5f353b
21 changed files with 74 additions and 417 deletions
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2
Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/clean.bat
View File

@@ -17,7 +17,7 @@ cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del /s build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws

2
Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/build_id.sv
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@@ -1,2 +0,0 @@
`define BUILD_DATE "190321"
`define BUILD_TIME "135526"

2
Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/build_id.tcl
View File

@@ -17,7 +17,7 @@ proc generateBuildID_Verilog {} {
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.sv"
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source

70
Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.qsf
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@@ -1,6 +1,6 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
@@ -17,15 +17,15 @@
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 20:09:19 June 07, 2018
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 17:36:19 July 15, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Bagman_assignment_defaults.qdf
# CrazyKong_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@@ -44,6 +44,28 @@ set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ckong_mist.sv
set_global_assignment -name VHDL_FILE rtl/ckong.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_tile_bit1.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_tile_bit0.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_samples.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_program.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_palette.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_big_sprite_tile_bit1.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_big_sprite_tile_bit0.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_big_sprite_palette.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_sound.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
set_global_assignment -name VHDL_FILE rtl/ym_2149_linmix.vhd
set_global_assignment -name VHDL_FILE rtl/video_gen.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
# Pin & Location Assignments
# ==========================
@@ -96,8 +118,6 @@ set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
#set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
#set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
@@ -130,43 +150,21 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# -------------------------
# start ENTITY(bagman_mist)
# ------------------------
# start ENTITY(ckong_mist)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(bagman_mist)
# -----------------------
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ckong_mist.sv
set_global_assignment -name VHDL_FILE rtl/ckong.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_tile_bit1.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_tile_bit0.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_samples.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_program.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_palette.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_big_sprite_tile_bit1.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_big_sprite_tile_bit0.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_big_sprite_palette.vhd
set_global_assignment -name VHDL_FILE rtl/ckong_sound.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
set_global_assignment -name VHDL_FILE rtl/ym_2149_linmix.vhd
set_global_assignment -name VHDL_FILE rtl/video_gen.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# end ENTITY(ckong_mist)
# ----------------------

9
Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.srf Normal file
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@@ -0,0 +1,9 @@
{ "" "" "" "Inferred dual-clock RAM node \"mist_video:mist_video\|osd:osd\|osd_buffer_rtl_0\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "6 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Design contains 1 input pin(s) that do not drive logic" { } { } 0 21074 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "PLL \"pll:pll\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK\[1\] is not connected" { } { } 0 15899 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "TimeQuest Timing Analyzer is analyzing 2 combinational loops as latches." { } { } 0 335093 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "8192 out of 32768 addresses are uninitialized. The Quartus II software will initialize them to \"0\". There are 1 warnings found, and 1 warnings are reported." { } { } 0 113028 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Output pins are stuck at VCC or GND" { } { } 0 13024 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447." { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "5 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}

BIN
Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/Release/CrazyKong.rbf
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Binary file not shown.

2
Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/clean.bat
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@@ -17,7 +17,7 @@ cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del /s build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws

2
Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/build_id.sv
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@@ -1,2 +0,0 @@
`define BUILD_DATE "190715"
`define BUILD_TIME "165600"

2
Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/build_id.tcl
View File

@@ -17,7 +17,7 @@ proc generateBuildID_Verilog {} {
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.sv"
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source

8
Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_mist.sv
View File

@@ -16,14 +16,14 @@ module ckong_mist (
input CLOCK_27
);
`include "rtl\build_id.sv"
`include "rtl\build_id.v"
localparam CONF_STR = {
"CrazyKong;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"T6,Reset;",
"V,v1.20.",`BUILD_DATE
"V,v1.21.",`BUILD_DATE
};
assign LED = 1;
@@ -32,9 +32,7 @@ assign AUDIO_R = AUDIO_L;
wire clock_12;
pll pll(
.inclk0(CLOCK_27),
// .c0(clock_24),
.c1(clock_12)//,
// .c2(clock_6)
.c0(clock_12)
);

89
Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/line_doubler.vhd
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@@ -1,89 +0,0 @@
---------------------------------------------------------------------------------
-- Line doubler - Dar - Feb 2014
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity line_doubler is
port(
clock_12mhz : in std_logic;
video_i : in std_logic_vector(7 downto 0);
hsync_i : in std_logic;
vsync_i : in std_logic;
video_o : out std_logic_vector(7 downto 0);
hsync_o : out std_logic;
vsync_o : out std_logic
);
end line_doubler;
architecture struct of line_doubler is
signal hsync_i_reg : std_logic;
signal vsync_i_reg : std_logic;
signal hcnt_i : integer range 0 to 1023;
signal vcnt_i : integer range 0 to 511;
signal hcnt_o : integer range 0 to 511;
signal flip_flop : std_logic;
type ram_1024x8 is array(0 to 1023) of std_logic_vector(7 downto 0);
signal ram1 : ram_1024x8;
signal ram2 : ram_1024x8;
signal video : std_logic_vector(7 downto 0);
begin
process(clock_12mhz)
begin
if rising_edge(clock_12mhz) then
hsync_i_reg <= hsync_i;
vsync_i_reg <= vsync_i;
if (vsync_i = '0' and vsync_i_reg = '1') then
vcnt_i <= 0;
else
if (hsync_i = '0' and hsync_i_reg = '1') then
vcnt_i <= vcnt_i + 1;
end if;
end if;
if (hsync_i = '0' and hsync_i_reg = '1') then
flip_flop <= not flip_flop;
hcnt_i <= 0;
else
hcnt_i <= hcnt_i + 1;
end if;
if (hsync_i = '0' and hsync_i_reg = '1') or hcnt_o = 383 then
hcnt_o <= 0;
else
hcnt_o <= hcnt_o + 1;
end if;
if hcnt_o = 0 then hsync_o <= '0';
elsif hcnt_o = 4 then hsync_o <= '1';
end if;
if vcnt_i = 0 then vsync_o <= '0';
elsif vcnt_i = 4 then vsync_o <= '1';
end if;
end if;
end process;
process(clock_12mhz, video)
begin
if rising_edge(clock_12mhz) then
if flip_flop = '0' then
ram1(hcnt_i/2) <= video_i;
video <= ram2(hcnt_o);
else
ram2(hcnt_i/2) <= video_i;
video <= ram1(hcnt_o);
end if;
end if;
video_o <= video;
end process;
end architecture;

92
Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/pll.v
View File

@@ -39,31 +39,23 @@
module pll (
inclk0,
c0,
c1,
c2,
locked);
input inclk0;
output c0;
output c1;
output c2;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire7 = 1'h0;
wire [2:2] sub_wire4 = sub_wire0[2:2];
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire c2 = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire6),
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
@@ -102,18 +94,10 @@ module pll (
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 52,
altpll_component.clk0_divide_by = 31,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 47,
altpll_component.clk0_multiply_by = 14,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 104,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 47,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 208,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 47,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
@@ -147,8 +131,8 @@ module pll (
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
@@ -187,15 +171,9 @@ endmodule
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "52"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "104"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "208"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "31"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.403847"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.201923"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.100962"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "12.193548"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -216,34 +194,18 @@ endmodule
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "47"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "47"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "47"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "14"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.39300000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.19600000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.09800000"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "12.19600000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -266,33 +228,19 @@ endmodule
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "52"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "31"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "47"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "14"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "104"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "47"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "208"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "47"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -325,8 +273,8 @@ endmodule
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
@@ -344,15 +292,11 @@ endmodule
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE

195
Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/scandoubler.sv
View File

@@ -1,195 +0,0 @@
//
// scandoubler.v
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
// TODO: Delay vsync one line
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
(
// system interface
input clk_sys,
input ce_pix,
input ce_pix_actual,
input hq2x,
// shifter video interface
input hs_in,
input vs_in,
input line_start,
input [DWIDTH:0] r_in,
input [DWIDTH:0] g_in,
input [DWIDTH:0] b_in,
input mono,
// output interface
output reg hs_out,
output vs_out,
output [DWIDTH:0] r_out,
output [DWIDTH:0] g_out,
output [DWIDTH:0] b_out
);
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
assign vs_out = vs_in;
reg [2:0] phase;
reg [2:0] ce_div;
reg [7:0] pix_len = 0;
wire [7:0] pl = pix_len + 1'b1;
reg ce_x1, ce_x4;
reg req_line_reset;
wire ls_in = hs_in | line_start;
always @(negedge clk_sys) begin
reg old_ce;
reg [2:0] ce_cnt;
reg [7:0] pixsz2, pixsz4 = 0;
old_ce <= ce_pix;
if(~&pix_len) pix_len <= pix_len + 1'd1;
ce_x4 <= 0;
ce_x1 <= 0;
// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
phase <= phase + 1'd1;
ce_x4 <= 1;
end
if(~old_ce & ce_pix) begin
pixsz2 <= {1'b0, pl[7:1]};
pixsz4 <= {2'b00, pl[7:2]};
ce_x1 <= 1;
ce_x4 <= 1;
pix_len <= 0;
phase <= phase + 1'd1;
ce_cnt <= ce_cnt + 1'd1;
if(ce_pix_actual) begin
phase <= 0;
ce_div <= ce_cnt + 1'd1;
ce_cnt <= 0;
req_line_reset <= 0;
end
if(ls_in) req_line_reset <= 1;
end
end
reg ce_sd;
always @(*) begin
case(ce_div)
2: ce_sd = !phase[0];
4: ce_sd = !phase[1:0];
default: ce_sd <= 1;
endcase
end
`define BITS_TO_FIT(N) ( \
N <= 2 ? 0 : \
N <= 4 ? 1 : \
N <= 8 ? 2 : \
N <= 16 ? 3 : \
N <= 32 ? 4 : \
N <= 64 ? 5 : \
N <= 128 ? 6 : \
N <= 256 ? 7 : \
N <= 512 ? 8 : \
N <=1024 ? 9 : 10 )
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
(
.clk(clk_sys),
.ce_x4(ce_x4 & ce_sd),
.inputpixel({b_in,g_in,r_in}),
.mono(mono),
.disable_hq2x(~hq2x),
.reset_frame(vs_in),
.reset_line(req_line_reset),
.read_y(sd_line),
.read_x(sd_h_actual),
.outpixel({b_out,g_out,r_out})
);
reg [10:0] sd_h_actual;
always @(*) begin
case(ce_div)
2: sd_h_actual = sd_h[10:1];
4: sd_h_actual = sd_h[10:2];
default: sd_h_actual = sd_h;
endcase
end
reg [10:0] sd_h;
reg [1:0] sd_line;
always @(posedge clk_sys) begin
reg [11:0] hs_max,hs_rise,hs_ls;
reg [10:0] hcnt;
reg [11:0] sd_hcnt;
reg hs, hs2, vs, ls;
if(ce_x1) begin
hs <= hs_in;
ls <= ls_in;
if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
// falling edge of hsync indicates start of line
if(hs && !hs_in) begin
hs_max <= {hcnt,1'b1};
hcnt <= 0;
if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
end else begin
hcnt <= hcnt + 1'd1;
end
// save position of rising edge
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
vs <= vs_in;
if(vs && ~vs_in) sd_line <= 0;
end
if(ce_x4) begin
hs2 <= hs_in;
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 1'd1;
sd_h <= sd_h + 1'd1;
if(hs2 && !hs_in) sd_hcnt <= hs_max;
if(sd_hcnt == hs_max) sd_hcnt <= 0;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_max) hs_out <= 0;
if(sd_hcnt == hs_rise) hs_out <= 1;
if(sd_hcnt == hs_ls) sd_h <= 0;
if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1;
end
end
endmodule

2
Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/clean.bat
View File

@@ -17,7 +17,7 @@ cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del /s build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws

2
Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/RiverPatrol_mist.sv
View File

@@ -16,7 +16,7 @@ module RiverPatrol_mist (
input CLOCK_27
);
`include "rtl\build_id.sv"
`include "rtl\build_id.v"
localparam CONF_STR = {
"RiverPat.;;",

2
Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/build_id.sv
View File

@@ -1,2 +0,0 @@
`define BUILD_DATE "190321"
`define BUILD_TIME "131156"

2
Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/build_id.tcl
View File

@@ -17,7 +17,7 @@ proc generateBuildID_Verilog {} {
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.sv"
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source

2
Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/clean.bat
View File

@@ -17,7 +17,7 @@ cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del /s build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws

2
Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/SilverLand_mist.sv
View File

@@ -16,7 +16,7 @@ module SilverLand_mist (
input CLOCK_27
);
`include "rtl\build_id.sv"
`include "rtl\build_id.v"
localparam CONF_STR = {
"SilverLand;;",

2
Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/build_id.sv
View File

@@ -1,2 +0,0 @@
`define BUILD_DATE "190418"
`define BUILD_TIME "162029"

2
Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/build_id.tcl
View File

@@ -17,7 +17,7 @@ proc generateBuildID_Verilog {} {
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.sv"
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source