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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-02-02 23:00:55 +00:00

Druaga: fix controls & DIPS for Grobda and Pac'n'Pal

This commit is contained in:
Gyorgy Szombathelyi
2022-02-13 01:07:36 +01:00
parent 823e8ef78d
commit beff3a7607
14 changed files with 182 additions and 119 deletions

View File

@@ -35,4 +35,20 @@
<part name="gr1-3.3m"/>
<part name="gr1-6.4c"/>
</rom>
<switches base="8" default="00,00,00">
<!-- DSW0 -->
<!-- dip name="Cabinet" bits="14" ids="Cocktail,Upright"/-->
<dip name="Service Mode" bits="15" ids="Off,On"/>
<!-- DSW1 -->
<dip name="Coin A" bits="1,3" ids="1/3,1/4,1/2,1/1,2/1,2/3,3/1,4/1"/>
<dip name="Coin B" bits="4,6" ids="1/3,1/4,1/2,1/1,2/1,2/3,3/1,4/1"/>
<dip name="Freeze" bits="7" ids="Off,On"/>
<!-- DSW2 -->
<dip name="Lives" bits="16,17" ids="3,1,2,5"/>
<dip name="Difficulty" bits="18,19" ids="Rank A,Rank B,Rank C,Rank D"/>
<dip name="Demo Sounds" bits="20" ids="On,Off"/>
<dip name="Level Select" bits="21" ids="On,Off"/>
<dip name="Bonus Life" bits="22,23" ids="10k,None,10k/30k,10k/50k/50k"/>
</switches>
</misterromdescription>

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@@ -8,7 +8,7 @@
<rbf>druaga</rbf>
<mratimestamp>20210326</mratimestamp>
<rom index="1">
<part>05</part>
<part>07</part>
</rom>
<rom index="0" zip="pacnpal.zip" md5="None">
<!-- CPU ROM set for the original Pac & Pal.
@@ -56,7 +56,7 @@
<dip bits="16,18" name="Coin A" ids="1 Coin 1 Credit ,1 Coin 2 Credits,1 Coin 3 Credits,1 Coin 6 Credits,1 Coin 7 Credits,2 Coins 1 Credit ,2 Coins 3 Credits,3 Coins 1 Credit "/>
<dip bits="0,1" name="Coin B" ids="1 Coin 1 Credit ,1 Coin 2 Credits,2 Coins 1 Credit ,2 Coins 3 Credits"/>
<dip bits="22,23" name="Lives" ids="1,2,3,5"/>
<dip bits="19,21" name="Bonus Life" ids="No Bonus,20k/70k/ev.70k,30k/80k/ev.80k,20k/70k,30k/70k,30k/80k,30k/100k"/>
<dip bits="19,21" name="Bonus Life" ids="Never,30k/80k/80k,40k/100k/100k,30k/80k,30k/100k,40k/120k,30k"/>
<dip bits="15" name="Service Mode" ids="Off,On"></dip>
<!-- dip bits="14" name="Cabinet" ids="Upright,Cocktail"></dip -->
</switches>

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@@ -8,7 +8,7 @@
<rbf>druaga</rbf>
<mratimestamp>20210326</mratimestamp>
<rom index="1">
<part>05</part>
<part>07</part>
</rom>
<rom index="0" zip="pacnpal.zip" md5="None">
<!-- main CPU -->
@@ -44,7 +44,7 @@
<dip bits="16,18" name="Coin A" ids="1 Coin 1 Credit ,1 Coin 2 Credits,1 Coin 3 Credits,1 Coin 6 Credits,1 Coin 7 Credits,2 Coins 1 Credit ,2 Coins 3 Credits,3 Coins 1 Credit "/>
<dip bits="0,1" name="Coin B" ids="1 Coin 1 Credit ,1 Coin 2 Credits,2 Coins 1 Credit ,2 Coins 3 Credits"/>
<dip bits="22,23" name="Lives" ids="1,2,3,5"/>
<dip bits="19,21" name="Bonus Life" ids="No Bonus,20k/70k/ev.70k,30k/80k/ev.80k,20k/70k,30k/70k,30k/80k,30k/100k"/>
<dip bits="19,21" name="Bonus Life" ids="Never,30k/80k/80k,40k/100k/100k,30k/80k,30k/100k,40k/120k,30k"/>
<dip bits="15" name="Service Mode" ids="Off,On"></dip>
<!-- dip bits="14" name="Cabinet" ids="Upright,Cocktail"></dip -->
</switches>

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@@ -66,7 +66,7 @@ always @(*) begin
DSW2 = 0;
case (core_mod)
7'h0, 7'h1, 7'h3, 7'h6: // DRUAGA, DIGDUG2, GROBDA
7'h0, 7'h1, 7'h3: // DRUAGA, DIGDUG2
begin
DSW0 = status[15:8];
DSW1 = status[23:16];
@@ -78,6 +78,13 @@ always @(*) begin
DSW1 = status[23:16];
DSW2 = { {2{status[27:24]}} };
end
7'h6: // GROBDA
begin
DSW0 = status[15:8];
DSW1 = {status[23:22], m_fire2B, m_fireB, status[19:16]};
DSW2 = status[31:24];
end
default:
begin
DSW0 = status[15:8];
@@ -113,8 +120,6 @@ wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
// assign core_mod=7'd5;
user_io #(.STRLEN($size(CONF_STR)>>3))user_io(
.clk_sys (clock_48 ),
.conf_str (CONF_STR ),

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@@ -28,8 +28,7 @@ module DRUAGA_SPRITE
input FLIP_SCREEN
);
parameter [2:0] SUPERPAC=3'd5;
parameter [2:0] GROBDA=3'd6;
`include "param.v"
reg [9:0] CLT1_A;
wire [3:0] CLT1_D;
@@ -92,7 +91,7 @@ always @(*) begin
(ox[1:0]==2'b01) ? { pn, SPCO[14], SPCO[10], SPCO[6], SPCO[2] } :
(ox[1:0]==2'b10) ? { pn, SPCO[13], SPCO[ 9], SPCO[5], SPCO[1] } :
{ pn, SPCO[12], SPCO[ 8], SPCO[4], SPCO[0] } ;
if( MODEL == SUPERPAC || MODEL == GROBDA) begin // 2bpp
if( MODEL == SUPERPAC || MODEL == GROBDA || MODEL == PACNPAL) begin // 2bpp
CLT1_A[9:2]= { 2'd0, CLT1_A[9:4] };
end
end

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@@ -35,8 +35,7 @@ module DRUAGA_VIDEO
input FLIP_SCREEN
);
parameter [2:0] SUPERPAC=3'd5;
parameter [2:0] GROBDA=3'd6;
`include "param.v"
wire [8:0] HPOS = PH-8'd16;
wire [8:0] VPOS = PV;
@@ -91,11 +90,11 @@ always @ ( posedge VCLKx8 ) begin
end
assign CLT0_A = BGPN ^ ( (MODEL==SUPERPAC || MODEL==GROBDA) ? 8'h0 : 8'h03 );
assign VRAM_A = VRAMADRS & ( (MODEL==SUPERPAC || MODEL==GROBDA) ? 11'h3FF : 11'h7FF );
assign CLT0_A = BGPN ^ ( (MODEL==SUPERPAC || MODEL==GROBDA || MODEL==PACNPAL) ? 8'h0 : 8'h03 );
assign VRAM_A = VRAMADRS & ( (MODEL==SUPERPAC || MODEL==GROBDA || MODEL==PACNPAL) ? 11'h3FF : 11'h7FF );
wire BGHI = BGH & (CLT0_D!=4'd15);
wire [4:0] BGCOL = { 1'b1, ((MODEL==SUPERPAC || MODEL==GROBDA) ? ~CLT0_D :CLT0_D) };
wire [4:0] BGCOL = { 1'b1, ((MODEL==SUPERPAC || MODEL==GROBDA || MODEL==PACNPAL) ? ~CLT0_D :CLT0_D) };
always @(*) begin
COL = HPOS[8:3] ^ {5{FLIP_SCREEN}};
@@ -103,7 +102,7 @@ always @(*) begin
// rather than the original circuit count.
ROW = (VPOS[8:3] + 6'h2) ^ {5{FLIP_SCREEN}};
if( MODEL==SUPERPAC || MODEL==GROBDA ) begin
if( MODEL==SUPERPAC || MODEL==GROBDA || MODEL==PACNPAL) begin
VRAMADRS = { 1'b0,
COL[5] ? {COL[4:0], ROW[4:0]} :
{ROW[4:0], COL[4:0]}
@@ -119,7 +118,7 @@ end
//----------------------------------------
wire [4:0] SPCOL;
DRUAGA_SPRITE #(.SUPERPAC(SUPERPAC)) spr
DRUAGA_SPRITE spr
(
VCLKx8, VCLK_EN,
HPOS, VPOS, oHB,

View File

@@ -41,8 +41,6 @@ module fpga_druaga
input FLIP_SCREEN
);
parameter [2:0] SUPERPAC=3'd5;
// Clock Generator
reg [4:0] CLKS;
@@ -79,7 +77,7 @@ wire [10:0] vram_a;
wire [15:0] vram_d;
wire [6:0] spra_a;
wire [23:0] spra_d;
MEMS #(.SUPERPAC(SUPERPAC)) mems
MEMS mems
(
MCLK,
CLKCPUx2,
@@ -101,7 +99,7 @@ wire SCPU_IRQ, SCPU_IRQEN;
wire SCPU_RESET, IO_RESET;
wire PSG_ENABLE;
REGS #(.SUPERPAC(SUPERPAC)) regs
REGS regs
(
CLKCPUx2, RESET, oVB,
MCPU_ADRS, MCPU_VMA, MCPU_WE,
@@ -117,7 +115,7 @@ REGS #(.SUPERPAC(SUPERPAC)) regs
// I/O Controler
wire IsMOTOS;
IOCTRL #(.SUPERPAC(SUPERPAC)) ioctrl(
IOCTRL ioctrl(
CLKCPUx2, oVB, IO_RESET, MCPU_CS_IO, MCPU_WE, MCPU_ADRS[5:0],
MCPU_DO,
IO_O,
@@ -241,8 +239,7 @@ module MEMS
input [2:0] MODEL
);
parameter [2:0] SUPERPAC=3'd5;
parameter [2:0] GROBDA=3'd6;
`include "param.v"
wire [7:0] mrom_d, srom_d;
//DLROM #(15,8) mcpui( CPUCLKx2, MCPU_ADRS[14:0], mrom_d, ROMCL,ROMAD[14:0],ROMDT,ROMEN & (ROMAD[16:15]==2'b0_0));
@@ -266,7 +263,7 @@ wire mrom_cs = ( MCPU_ADRS[15] ) & MCPU_VMA; // $8000-$FFFF
always @(*) begin
cram_ad = mram_ad;
if( MODEL == SUPERPAC || MODEL == GROBDA) begin
if( MODEL == SUPERPAC || MODEL == GROBDA || MODEL == PACNPAL) begin
mram_cs0 = ( MCPU_ADRS[15:10] == 6'b000000 ) && MCPU_VMA; // $0000-$03FF
mram_cs1 = ( MCPU_ADRS[15:10] == 6'b000001 ) && MCPU_VMA; // $0400-$07FF
mram_cs2 = ( MCPU_ADRS[15:11] == 5'b00001 ) && MCPU_VMA; // $1000-$17FF
@@ -352,16 +349,14 @@ module REGS
input [2:0] MODEL
);
parameter [2:0] SUPERPAC=3'd5;
parameter [2:0] GROBDA=3'd6;
`include "param.v"
// BG Scroll Register
wire MCPU_SCRWE = ( ( MCPU_ADRS[15:11] == 5'b00111 ) & MCPU_VMA & MCPU_WE );
always @ ( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) SCROLL <= 8'h0;
else begin
if( MODEL==SUPERPAC || MODEL==GROBDA)
if( MODEL==SUPERPAC || MODEL==GROBDA || MODEL==PACNPAL)
SCROLL <= 8'd0;
else if ( MCPU_SCRWE )
SCROLL <= MCPU_ADRS[10:3];

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@@ -42,13 +42,12 @@ reg [9:0] pSTKTRG12;
reg [2:0] pCSTART12;
reg bUpdate;
reg bIOMode;
parameter [2:0] SUPERPAC=3'd5;
reg [1:0] bIOMode;
`include "param.v"
assign OUT = { 4'b1111, outr };
assign IsMOTOS = bIOMode;
assign IsMOTOS = bIOMode == 1;
// Detect falling edges:
wire [11:0] iSTKTRG12 = ( STKTRG12 ^ pSTKTRG12 ) & STKTRG12;
@@ -60,13 +59,13 @@ BCDCONV creditsBCD( credits, CREDIT_ONES, CREDIT_TENS );
always @ ( posedge CLK ) begin
if ( ENABLE ) begin
if ( ADRS[5] ) begin
if ( WR ) memc[ADRS[4:0]] <= IN;
if ( WR ) memc[ADRS[4:0]] <= IN[3:0];
outr <= memc[ADRS[4:0]];
end else if ( ADRS[4] ) begin
if ( WR ) memb[ADRS[3:0]] <= IN;
if ( WR ) memb[ADRS[3:0]] <= IN[3:0];
outr <= memb[ADRS[3:0]];
end else begin
if ( WR ) mema[ADRS[3:0]] <= IN;
if ( WR ) mema[ADRS[3:0]] <= IN[3:0];
outr <= mema[ADRS[3:0]];
end
end
@@ -78,14 +77,28 @@ always @ ( posedge CLK ) begin
credits <= 0;
end else begin
if ( UPDATE & (~bUpdate) ) begin
if ( mema[4'h8] == 4'h8 || MODEL==SUPERPAC )
bIOMode <= 1'b1; // Is running "Motos" ?
if (MODEL == PACNPAL)
bIOMode <= 2'd3;
else if (MODEL == GROBDA)
bIOMode <= 2'd2;
else if ( mema[4'h8] == 4'h8 || MODEL==SUPERPAC)
bIOMode <= 2'd1; // Is running "Motos" ?
if ( bIOMode ) begin
`include "ioctrl_1.v"
if ( bIOMode == 3) begin
`include "ioctrl_1a.v"
`include "ioctrl_2b.v"
end
else if ( bIOMode == 2) begin
`include "ioctrl_0a.v"
`include "ioctrl_1b.v"
end
else if ( bIOMode == 1) begin
`include "ioctrl_1a.v"
`include "ioctrl_1b.v"
end
else begin
`include "ioctrl_0.v"
`include "ioctrl_0a.v"
`include "ioctrl_0b.v"
end
pCSTART12 <= CSTART12;

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@@ -12,21 +12,21 @@
if ( iCSTART12[2] & ( credits < 99 ) ) begin
credit_add = 8'h01;
credits = credits + 1;
credits = credits + 1'd1;
end
if ( mema[4'h9] == 0 ) begin
if ( ( credits >= 2 ) & iCSTART12[1] ) begin
credit_sub = 8'h02;
credits = credits - 2;
credits = credits - 2'd2;
end else if ( ( credits >= 1 ) & iCSTART12[0] ) begin
credit_sub = 8'h01;
credits = credits - 1;
credits = credits - 1'd1;
end
end
mema[4'h0] <= credit_add;
mema[4'h1] <= credit_sub | {7'd0,CSTART12[0]};
mema[4'h1] <= credit_sub | {3'd0,CSTART12[0]};
mema[4'h2] <= CREDIT_TENS;
mema[4'h3] <= CREDIT_ONES;
mema[4'h4] <= STKTRG12[3:0];
@@ -60,48 +60,3 @@
default:;
endcase
case ( memb[4'h8] )
4'h1,4'h3: begin
memb[4'h0] <= 0;
memb[4'h1] <= 0;
memb[4'h2] <= 0;
memb[4'h3] <= 0;
memb[4'h4] <= 0;
memb[4'h5] <= 0;
memb[4'h6] <= 0;
memb[4'h7] <= 0;
end
4'h4: begin
memb[4'h0] <= DIPSW[11: 8]; // (P0) DSW1 Mappy
memb[4'h1] <= DIPSW[15:12];
memb[4'h2] <= DIPSW[ 3: 0]; // (P1) DSW0
memb[4'h4] <= DIPSW[ 7: 4];
memb[4'h5] <={DIPSW[15:14],STKTRG12[ 5],iSTKTRG12[ 5]}; // (P2) DSW1 Druaga/DigDug2
memb[4'h6] <= DIPSW[23:20]; // IsMappy ? DIPSW[19:16] : DIPSW[11:8]
memb[4'h7] <={DIPSW[19:18],STKTRG12[11],iSTKTRG12[11]}; // (P3) DSW2
memb[4'h3] <= 0;
end
4'h5: begin
memb[4'h0] <= 4'h0;
memb[4'h1] <= 4'h8;
memb[4'h2] <= 4'h4;
memb[4'h3] <= 4'h6;
memb[4'h4] <= 4'hE;
memb[4'h5] <= 4'hD;
memb[4'h6] <= 4'h9;
memb[4'h7] <= 4'hD;
end
default:;
endcase

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@@ -0,0 +1,49 @@
//------------------------------------------
// I/O Chip for "Mappy/Druaga/DigDug2"
//
// Copyright (c) 2007,19 MiSTer-X
//------------------------------------------
case ( memb[4'h8] )
4'h1,4'h3: begin
memb[4'h0] <= 0;
memb[4'h1] <= 0;
memb[4'h2] <= 0;
memb[4'h3] <= 0;
memb[4'h4] <= 0;
memb[4'h5] <= 0;
memb[4'h6] <= 0;
memb[4'h7] <= 0;
end
4'h4: begin
memb[4'h0] <= DIPSW[11: 8]; // (P0) DSW1 Mappy
memb[4'h1] <= DIPSW[15:12];
memb[4'h2] <= DIPSW[ 3: 0]; // (P1) DSW0
memb[4'h4] <= DIPSW[ 7: 4];
memb[4'h5] <={DIPSW[15:14],STKTRG12[ 5],iSTKTRG12[ 5]}; // (P2) DSW1 Druaga/DigDug2
memb[4'h6] <= DIPSW[23:20]; // IsMappy ? DIPSW[19:16] : DIPSW[11:8]
memb[4'h7] <={DIPSW[19:18],STKTRG12[11],iSTKTRG12[11]}; // (P3) DSW2
memb[4'h3] <= 0;
end
4'h5: begin
memb[4'h0] <= 4'h0;
memb[4'h1] <= 4'h8;
memb[4'h2] <= 4'h4;
memb[4'h3] <= 4'h6;
memb[4'h4] <= 4'hE;
memb[4'h5] <= 4'hD;
memb[4'h6] <= 4'h9;
memb[4'h7] <= 4'hD;
end
default:;
endcase

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@@ -25,21 +25,21 @@
if ( iCSTART12[2] & ( credits < 99 ) ) begin
credit_add = 8'h01;
credits = credits + 1;
credits = credits + 1'd1;
end
if ( mema[4'h9] == 0 ) begin
if ( ( credits >= 2 ) && iCSTART12[1] ) begin
credit_sub = 8'h02;
credits = credits - 2;
credits = credits - 2'd2;
end else if ( ( credits >= 1 ) && iCSTART12[0] ) begin
credit_sub = 8'h01;
credits = credits - 1;
credits = credits - 1'd1;
end
end
mema[4'h0] <= credit_add;
mema[4'h1] <= credit_sub | {7'd0,CSTART12[0]};
mema[4'h1] <= credit_sub | {3'd0,CSTART12[0]};
mema[4'h2] <= CREDIT_TENS;
mema[4'h3] <= CREDIT_ONES;
mema[4'h4] <= STKTRG12[3:0];
@@ -57,28 +57,3 @@
default:;
endcase
case ( memb[4'h8] )
4'h8: begin
memb[4'h0] <= 4'h6;
memb[4'h1] <= 4'h9;
end
4'h9: begin
memb[4'h2] <= DIPSW[3:0];
memb[4'h4] <= DIPSW[7:4];
memb[4'h6] <= DIPSW[15:12];
memb[4'h0] <= 0;
memb[4'h1] <= 0;
memb[4'h3] <= 0;
memb[4'h5] <= 0;
memb[4'h7] <= 0;
end
default:;
endcase

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@@ -0,0 +1,29 @@
//------------------------------------------
// I/O Chip for "Motos"
// Namco 56xx
//
// Copyright (c) 2007,19 MiSTer-X
//------------------------------------------
case ( memb[4'h8] )
4'h8: begin
memb[4'h0] <= 4'h6;
memb[4'h1] <= 4'h9;
end
4'h9: begin
memb[4'h2] <= DIPSW[3:0];
memb[4'h4] <= DIPSW[7:4];
memb[4'h6] <= DIPSW[15:12];
memb[4'h0] <= DIPSW[19:16];
memb[4'h1] <= DIPSW[23:20];
memb[4'h3] <= 0;
memb[4'h5] <= 0;
memb[4'h7] <= 0;
end
default:;
endcase

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@@ -0,0 +1,25 @@
//------------------------------------------
// I/O Chip for "Pac & Pal"
// Namco 59xx
//
// Copyright (c) 2007,19 MiSTer-X
// Copyright (c) 2022 Slingshot
//------------------------------------------
case ( memb[4'h8] )
4'h3: begin
memb[4'h4] <= DIPSW[3:0]; //0
memb[4'h5] <= DIPSW[23:20]; //2
memb[4'h6] <= DIPSW[19:16]; //1
memb[4'h7] <= DIPSW[15:12]; //3
memb[4'h0] <= 0;
memb[4'h1] <= 0;
memb[4'h2] <= 0;
memb[4'h3] <= 0;
end
default:;
endcase

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@@ -0,0 +1,3 @@
localparam [2:0] SUPERPAC=3'd5;
localparam [2:0] GROBDA=3'd6;
localparam [2:0] PACNPAL=3'd7;