add Color Computer for MiST and WXEDA

Robotron - KC87_MiST/kc87.qsf

@@ -43,33 +43,6 @@ set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:04:18  MAY 11, 2014"
 set_global_assignment -name LAST_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name VHDL_FILE rtl/t80/T80se.vhd
-set_global_assignment -name VHDL_FILE rtl/t80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/t80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/t80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/t80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/t80/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/kc87.vhd
-set_global_assignment -name VHDL_FILE rtl/intcontroller.vhd
-set_global_assignment -name VHDL_FILE rtl/ctc.vhd
-set_global_assignment -name VHDL_FILE rtl/pio.vhd
-set_global_assignment -name VHDL_FILE rtl/pport.vhd
-set_global_assignment -name VHDL_FILE rtl/dualsram.vhd
-set_global_assignment -name VHDL_FILE rtl/video.vhd
-set_global_assignment -name VHDL_FILE rtl/ps2kc.vhd
-set_global_assignment -name VHDL_FILE rtl/uart.vhd
-set_global_assignment -name VHDL_FILE rtl/ctc_channel.vhd
-set_global_assignment -name VHDL_FILE rtl/pio_port.vhd
-set_global_assignment -name VHDL_FILE rtl/chargen.vhdl
-set_global_assignment -name VHDL_FILE rtl/ps2if.vhd
-set_global_assignment -name QIP_FILE rtl/mram.qip
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/pll.v
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/KC87_mist.sv
 
 # Classic Timing Assignments
 # ==========================
@@ -194,5 +167,32 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
 # end ENTITY(kc87)
 # ----------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/KC87_mist.sv
+set_global_assignment -name VHDL_FILE rtl/kc87.vhd
 set_global_assignment -name VHDL_FILE rtl/roms/bootloader.vhdl
+set_global_assignment -name VHDL_FILE rtl/intcontroller.vhd
+set_global_assignment -name VHDL_FILE rtl/ctc.vhd
+set_global_assignment -name VHDL_FILE rtl/pio.vhd
+set_global_assignment -name VHDL_FILE rtl/pport.vhd
+set_global_assignment -name QIP_FILE rtl/mram.qip
+set_global_assignment -name VHDL_FILE rtl/dualsram.vhd
+set_global_assignment -name VHDL_FILE rtl/video.vhd
+set_global_assignment -name VHDL_FILE rtl/ps2kc.vhd
+set_global_assignment -name VHDL_FILE rtl/ps2if.vhd
+set_global_assignment -name VHDL_FILE rtl/uart.vhd
+set_global_assignment -name VHDL_FILE rtl/ctc_channel.vhd
+set_global_assignment -name VHDL_FILE rtl/pio_port.vhd
+set_global_assignment -name VHDL_FILE rtl/chargen.vhdl
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name VHDL_FILE rtl/t80/T80se.vhd
+set_global_assignment -name VHDL_FILE rtl/t80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/t80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/t80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/t80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/t80/T80.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Robotron - KC87_MiST/rtl/KC87_mist.sv

@@ -32,7 +32,7 @@ wire 			clk_12p5;
 wire 			clk_40;
 wire        scandoubler_disable;
 wire        ypbpr;
-wire        ps2_kbd_clk, ps2_kbd_data;
+tri        ps2_kbd_clk, ps2_kbd_data;
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;

Robotron - KC87_MiST/rtl/kc87.vhd

@@ -36,8 +36,8 @@ entity kc87 is
         VGA_B       : out std_logic_vector(3 downto 0);
         VGA_HS      : out std_logic;
         VGA_VS      : out std_logic;    
-        PS2_CLK     : in std_logic;
-        PS2_DAT     : in std_logic;   
+        PS2_CLK     : inout std_logic;
+        PS2_DAT     : inout std_logic;   
         UART_TXD    : out std_logic;
         UART_RXD    : in std_logic;
         
@@ -192,24 +192,6 @@ begin
     process
     begin
         wait until rising_edge(clk);
-        
-        if (m1_n='0' and iorq_n='0') then
-            if intAckCTC='1' then 
-                testAddr1 <= (others => '0');
-                testAddr1(7 downto 0) <= cpu_di;
-            end if;
-            
-            if intAckPio1='1' then 
-                testAddr2 <= (others => '0');
-                testAddr2(7 downto 0) <= cpu_di;
-            end if;
-            
-            if intAckPio2='1' then 
-                testAddr3 <= (others => '0');
-                testAddr3(7 downto 0) <= cpu_di;
-            end if;      
-        end if;
-        
         if m1_n='0' and rd_n = '0' and ram_cs_n = '0' then
             lastIntE <= intE;
 --            lastM1Addr <= cpu_addr;
@@ -299,13 +281,11 @@ begin
     
     -- teh cpu
     cpu : entity work.T80se
-        generic map(Mode => 1, T2Write => 1, IOWait => 0)
+        generic map(Mode => 0, T2Write => 1, IOWait => 0)
         port map(
             RESET_n => resetInt,
             CLK_n   => clk,
             CLKEN   => kcSysClk or sysctl_d(1),
---            CLKEN   => clkEn,
---            CLKEN   => kcSysClk,
             WAIT_n  => wait_n,
             INT_n   => int_n,
             NMI_n   => nmi_n,
@@ -549,14 +529,14 @@ begin
         ramAddr => vgaramaddr,
         colData => vgacoldata,
         charData => vgachardata,
-        scanLine => '0'
+        scanLine => '1'
     );
     
     -- ps/2 interface
     ps2kc : entity work.ps2kc
     port map (
         clk     => clk,
-        res     => '1',
+        res     => '1',--resetInt,
         ps2clk  => PS2_CLK,
         ps2data => PS2_DAT,
         data    => open,

Robotron - KC87_MiST/rtl/mist_io.v

@@ -78,9 +78,9 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
 	output reg        sd_buff_wr,
 
 	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
+	inout            ps2_kbd_clk,
 	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
+	inout            ps2_mouse_clk,
 	output reg        ps2_mouse_data,
 
 	// ARM -> FPGA download

Robotron - KC87_MiST/rtl/ps2kc.vhd

@@ -34,8 +34,8 @@ entity ps2kc is
     port (
         clk      : in std_logic;
         res      : in std_logic;
-        ps2clk   : in std_logic;
-        ps2data  : in std_logic;
+        ps2clk   : inout std_logic;
+        ps2data  : inout std_logic;
         data     : out std_logic_vector(7 downto 0);
         ps2code  : out std_logic_vector(7 downto 0);
         ps2rcvd  : out std_logic;