diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/Midway8080.qsf b/Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/Midway8080.qsf
index 165682cc..a9e0afc3 100644
--- a/Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/Midway8080.qsf	
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/Midway8080.qsf	
@@ -161,4 +161,5 @@ set_global_assignment -name VHDL_FILE src/T80.vhd
 set_global_assignment -name VHDL_FILE src/T80_ALU.vhd
 set_global_assignment -name VHDL_FILE src/T80_Reg.vhd
 set_global_assignment -name VHDL_FILE src/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE src/invaders_video.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/invaders_video.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/invaders_video.vhd
new file mode 100644
index 00000000..77ac2478
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/invaders_video.vhd	
@@ -0,0 +1,127 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+entity invaders_video is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end invaders_video;
+
+architecture rtl of invaders_video is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_G1      : boolean;
+	signal Overlay_G2      : boolean;
+	signal Overlay_R1      : boolean;
+	signal Overlay_G1_VCnt : boolean;
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  Overlay_G1_VCnt <= false;
+	  Overlay_G1 <= false;
+	  Overlay_G2 <= false;
+	  Overlay_R1 <= false;
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt = x"1F") then
+		  Overlay_G1_VCnt <= true;
+		elsif (Vcnt = x"95") then
+		  Overlay_G1_VCnt <= false;
+		end if;
+	  end if;
+
+	  if (HCnt = x"027") and Overlay_G1_VCnt then
+		Overlay_G1 <= true;
+	  elsif (HCnt = x"046") then
+		Overlay_G1 <= false;
+	  end if;
+
+	  if (HCnt = x"046") then
+		Overlay_G2 <= true;
+	  elsif (HCnt = x"0B6") then
+		Overlay_G2 <= false;
+	  end if;
+
+	  if (HCnt = x"1A6") then
+		Overlay_R1 <= true;
+	  elsif (HCnt = x"1E6") then
+		Overlay_R1 <= false;
+	  end if;
+
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1)
+  begin
+	if (Video = '0') then
+	  VideoRGB  <= "000";
+	else
+	  if Overlay_G1 or Overlay_G2 then
+		VideoRGB  <= "010";
+	  elsif Overlay_R1 then
+		VideoRGB  <= "100";
+	  else
+		VideoRGB  <= "111";
+	  end if;
+	end if;
+  end process;
+
+
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_HSYNC   <= not HSync;
+  O_VSYNC   <= not VSync;
+
+
+end;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/platform_variant_pkg.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/platform_variant_pkg.vhd
index 3525ece3..d3e16fb8 100644
--- a/Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/platform_variant_pkg.vhd	
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/platform_variant_pkg.vhd	
@@ -10,9 +10,9 @@ package platform_variant_pkg is
 	
 --Test Area	
 	--$0000
-	constant ROM_0_NAME		: string := "../roms/jatrespecter.hex";
+	constant ROM_0_NAME		: string := "../roms/lrescue0.hex";
 	--$4000
-	constant ROM_1_NAME		: string := "";
+	constant ROM_1_NAME		: string := "../roms/lrescue1.hex";
 	constant VRAM_NAME		: string := "../roms/sivram.hex";
 
 
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Invaders_assignment_defaults.qdf b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Invaders_assignment_defaults.qdf
new file mode 100644
index 00000000..39489982
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Invaders_assignment_defaults.qdf	
@@ -0,0 +1,692 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 13:56:11  June 04, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus II software and is used
+#    to preserve global assignments across Quartus II versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT On
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone IV GX"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name SYNTHESIS_SEED 1
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE Standard
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN On
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name VREF_MODE EXTERNAL
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_LARGE_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Release/SpaceLaser.rbf b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Release/SpaceLaser.rbf
index 359da4f8..2c31f584 100644
Binary files a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Release/SpaceLaser.rbf and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Release/SpaceLaser.rbf differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Release/SuperEarthInvasion.rbf b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Release/SuperEarthInvasion.rbf
index 77a26b1b..2b677f9b 100644
Binary files a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Release/SuperEarthInvasion.rbf and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Release/SuperEarthInvasion.rbf differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/invaders_memory.sv b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/invaders_memory.sv
index ef52cf36..34ba8f30 100644
--- a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/invaders_memory.sv	
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/invaders_memory.sv	
@@ -3,7 +3,7 @@ module invaders_memory(
 input				Clock,
 input				RW_n,
 input		[15:0]Addr,
-input		[12:0]Ram_Addr,
+input		[15:0]Ram_Addr,
 output	 [7:0]Ram_out,
 input		 [7:0]Ram_in,
 output	 [7:0]Rom_out
@@ -27,11 +27,13 @@ sprom #(
 `ifdef invaders	.init_file("./roms/SpaceInvaders/invaders_h.hex"), `endif//working
 `ifdef gunfight	.init_file("./roms/Gunfight/7609_e.hex"), `endif//not working
 `ifdef supearth	.init_file("./roms/SuperEarthInvasion/earthinv_h.hex"), `endif//working
-`ifdef seawolf		.init_file("./roms/Seawolf/sw0041_h.hex"), `endif//not working
+`ifdef seawolf		.init_file("./roms/Seawolf/hg.hex"), `endif//not working
 `ifdef dogpatch	.init_file("./roms/Dogpatch/dogpatch_h.hex"), `endif//not working
 `ifdef jspecter	.init_file("./roms/jspecter/rom_h.hex"), `endif//not working
 `ifdef invadrev	.init_file("./roms/InvadersRevenge/invrvnge_e.hex"), `endif//not 
 `ifdef blueshark	.init_file("./roms/BlueShark/blueshrk_h.hex"), `endif//
+`ifdef spacewalk	.init_file("./roms/Spacewalk/hg.hex"), `endif
+`ifdef extrainning	.init_file("./roms/ExtraInning/ei.h.hex"), `endif
 `ifdef zzzap280	.widthad_a(10), `endif//
 `ifdef generic	.widthad_a(11), `endif//
 //	.widthad_a(11), 
@@ -51,11 +53,13 @@ sprom #(
 `ifdef invaders	.init_file("./roms/SpaceInvaders/invaders_g.hex"), `endif
 `ifdef gunfight	.init_file("./roms/Gunfight/7609_f.hex"), `endif//not working
 `ifdef supearth	.init_file("./roms/SuperEarthInvasion/earthinv_g.hex"), `endif//working
-`ifdef seawolf		.init_file("./roms/Seawolf/sw0042_g.hex"), `endif//not working
+`ifdef seawolf		.init_file("./roms/Seawolf/fe.hex"), `endif//not working
 `ifdef dogpatch	.init_file("./roms/Dogpatch/dogpatch_g.hex"), `endif//not working
 `ifdef jspecter	.init_file("./roms/jspecter/rom_g.hex"), `endif//not working
 `ifdef invadrev	.init_file("./roms/InvadersRevenge/invrvnge_f.hex"), `endif//not working
 `ifdef blueshark	.init_file("./roms/BlueShark/blueshrk_g.hex"), `endif//
+`ifdef spacewalk	.init_file("./roms/Spacewalk/fe.hex"), `endif
+`ifdef extrainning	.init_file("./roms/ExtraInning/ei.g.hex"), `endif
 `ifdef zzzap280	.widthad_a(10), `endif//
 `ifdef generic	.widthad_a(11), `endif//
 //	.widthad_a(11), 
@@ -67,6 +71,7 @@ u_rom_g (
 	.q(rom_data_1)
 	);
 	
+`ifndef seawolf	
 sprom #(
 `ifdef sflush	.init_file("./roms/Strightflush/fr03_sc4.hex"), `endif//
 `ifdef zzzap280	.init_file("./roms/280zzz/zzzap_e.hex"), `endif//
@@ -75,11 +80,13 @@ sprom #(
 `ifdef invaders	.init_file("./roms/SpaceInvaders/invaders_f.hex"), `endif
 `ifdef gunfight	.init_file("./roms/Gunfight/7609_g.hex"), `endif//not working
 `ifdef supearth	.init_file("./roms/SuperEarthInvasion/earthinv_f.hex"), `endif//working
-`ifdef seawolf		.init_file("./roms/Seawolf/sw0043_f.hex"), `endif//not working
+
 `ifdef dogpatch	.init_file("./roms/Dogpatch/dogpatch_f.hex"), `endif//not working
 `ifdef jspecter	.init_file("./roms/jspecter/rom_f.hex"), `endif//not working
 `ifdef invadrev	.init_file("./roms/InvadersRevenge/invrvnge_g.hex"), `endif//not working
 `ifdef blueshark	.init_file("./roms/BlueShark/blueshrk_f.hex"), `endif//
+`ifdef spacewalk	.init_file("./roms/Spacewalk/dc.hex"), `endif
+`ifdef extrainning	.init_file("./roms/ExtraInning/ei.f.hex"), `endif
 `ifdef zzzap280	.widthad_a(10), `endif//
 `ifdef generic	.widthad_a(11), `endif//
 //	.widthad_a(11), 
@@ -100,10 +107,12 @@ sprom #(
 `ifdef invaders	.init_file("./roms/SpaceInvaders/invaders_e.hex"), `endif
 `ifdef gunfight	.init_file("./roms/Gunfight/7609_h.hex"), `endif//not working
 `ifdef supearth	.init_file("./roms/SuperEarthInvasion/earthinv_e.hex"), `endif//working
-`ifdef seawolf		.init_file("./roms/Seawolf/sw0044_e.hex"), `endif//not working
+
 `ifdef dogpatch	.init_file("./roms/Dogpatch/dogpatch_e.hex"), `endif//not working
 `ifdef jspecter	.init_file("./roms/jspecter/rom_e.hex"), `endif//not working
 `ifdef invadrev	.init_file("./roms/InvadersRevenge/invrvnge_h.hex"), `endif//not working
+`ifdef spacewalk	.init_file("./roms/Spacewalk/ba.hex"), `endif
+`ifdef extrainning	.init_file("./roms/ExtraInning/ei.e.hex"), `endif
 `ifdef zzzap280	.widthad_a(10), `endif//
 `ifdef generic	.widthad_a(11), `endif//
 	.width_a(8))
@@ -113,12 +122,15 @@ u_rom_e (
 `ifdef generic	.Address(Addr[10:0]), `endif
 	.q(rom_data_3)
 	);
-	`endif//	
-`ifndef generic
+	`endif//
+	
+//`ifndef generic
+`ifdef extrainning
 sprom #(
 `ifdef sflush	.init_file("./roms/Strightflush/fr05_sc2.hex"), `endif//
 `ifdef zzzap280	.init_file("./roms/280zzz/zzzap_g.hex"), `endif//
 `ifdef lrescue		.init_file("./roms/LunarRescue/lrescue_5.hex"), `endif
+`ifdef extrainning	.init_file("./roms/ExtraInning/ei.b.hex"), `endif
 `ifdef zzzap280	.widthad_a(10), `endif//
 `ifdef generic	.widthad_a(11), `endif//
 	.width_a(8))
@@ -128,6 +140,9 @@ u_rom_i (
 `ifdef generic	.Address(Addr[10:0]), `endif
 	.q(rom_data_4)
 	);
+`endif//extrainning	
+`ifndef generic
+
 
 sprom #(
 `ifdef zzzap280	.init_file("./roms/280zzz/zzzap_h.hex"), `endif//
@@ -142,6 +157,7 @@ u_rom_j (
 	.q(rom_data_5)
 	);	
 `endif//	
+`endif//	
 always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5, rom_data_6, rom_data_7) begin
 	Rom_out = 8'b00000000;
 		case (Addr[13:11])
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/pll.ppf b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/pll.ppf
new file mode 100644
index 00000000..71e6f03a
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/pll.ppf	
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.b.bin b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.b.bin
new file mode 100644
index 00000000..1723be1b
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.b.bin differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.b.hex b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.b.hex
new file mode 100644
index 00000000..c07aa90a
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.b.hex	
@@ -0,0 +1,129 @@
+:10000000190107200103200C501BD01A0208205CA4
+:1000100050126E2000E0202020E1129C2040E020C1
+:100020008001E112CA2080E020E020E112F8208067
+:10003000FF0CC850E212262138FF0CA02EE2125409
+:100040002120FF0C582EE212822100FF0C3050E2DA
+:1000500012B02160FF0C817AE2072051126E2090CD
+:10006000E0202020F1129C20C0E0208001F112CA83
+:1000700020E0E020E020F112F820FFFF0CC850F251
+:10008000122621E0FF0CA02EF2125421D0FF0C58B2
+:100090002EF212822180FF0C3050F212B021A0FF0C
+:1000A0000C817AF207205107020820E850136E20D5
+:1000B0003090E2E1139C2030D0E2E113CA2030E01E
+:1000C000E2E113F82008FFFFE213262108E0FFE237
+:1000D00013542108D0FFE21382210880FFE213B0FD
+:1000E0002108A0FFE2072051136E203000E2F11337
+:1000F0009C203040E2F113CA203080E2F113F82056
+:100100000880FFF21326210838FFF213542108203B
+:10011000FFF21382210810FFF213B0210860FFF2F2
+:10012000198061201C09181499040F3D148F04389C
+:1001300034148F040F2D148F0426341A021C160158
+:1001400008204B5115048003D8390915078503D6BB
+:100150003909091900662019000620161900E12244
+:100160001905602015026C031A381900E1221900E4
+:10017000232315076C038D26150963030B261AA08C
+:1001800052191E61201C15096C030B26191E6120D3
+:100190001C076E51171AA0521AF9110826510800AF
+:1001A000501508780301261901FE2212962280D8E4
+:1001B000207D78E01C13962220C453E01C13962265
+:1001C00020DC23E01C13962220BC17E0150B5803FB
+:1001D00014261C139622209C31E01C139622207CAE
+:1001E00004E01C139622205431E01C139622201C9C
+:1001F00023C01C139622202C53C01C139622207D52
+:100200007DC01C193C61201C08A850193C61201CB1
+:100210000794511900E122193C61201C08A85019CB
+:100220003C61201C074552171A5714170111203A38
+:10023000521539DF030028074052152C1804002CF2
+:1002400019FF61201C1708265108005019000720CB
+:10025000190A6220010620CC1D193C662007CC1D1E
+:100260001120000A77197719030A77197719030AF9
+:1002700077197719030A77197719030A7719771904
+:10028000030A77197719030A77197719030A771977
+:100290007719030A77197719030A7719771903C9A8
+:1002A0002134200607AF772305C2A652C9530D0A91
+:1002B00042414C4C440945515509353048093B42AF
+:1002C000414C4C204449535420464F5220504954ED
+:1002D00043480D0A42504F530945515509343409DA
+:1002E0003B4241542041444445520D0A5345430981
+:1002F0004551550936300D0A3B20504F5254530D8D
+:100300000A534150094551550931093B5348494663
+:100310005420414D540D0A534E445009455155093E
+:1003200033093B534F554E44530D0A534F50094523
+:1003300051550932093B53484946542044415441E0
+:100340000D0A534950094551550933093B53484952
+:10035000465420494E0D0A5032495009455155091D
+:1003600030093B504C4159455220320D0A534554F7
+:1003700050094551550932093B4F50455241544FA0
+:10038000522053455454494E47530D0A5031495059
+:10039000094551550931093B504C415945522031CD
+:1003A0000D0A4D555031094551550935093B204D30
+:1003B0005553494320504F52540D0A4D5550320960
+:1003C0004551550936093B20222222222220222291
+:1003D00022220D0A57444F470945515509340D0A49
+:1003E0003B534F554E44530D0A43434E5452094517
+:1003F0005155093330480D0A4741534E4409455180
+:1004000055093130480D0A3B2054494D45530D0ADA
+:100410005442414C4C09455155095345432F380925
+:100420003B42414C4C20534F554E442054494D457E
+:100430000D0A5448495409455155095345432F362F
+:1004400030093B48495420534F554E442054494DA0
+:10045000450D0A544F555409455155095345430913
+:100460003B4F555420534F554E442054494D450D54
+:100470000A545354524B09455155095345432F32A1
+:10048000093B535452494B4520534F554E44205439
+:10049000494D450D0A5443524443094551550934C9
+:1004A0002A534543093B43524F574420534F554E1F
+:1004B000442054494D450D0A3B20504C415945526A
+:1004C00020504F534954494F4E530D0A585031094B
+:1004D00045515509304338480D0A595031094551A5
+:1004E00055093530480D0A585032094551550930E3
+:1004F0004130480D0A595032094551550932454895
+:100500000D0A58503309455155093538480D0A59D7
+:10051000503309455155095950320D0A5850340984
+:10052000455155092D5850312D3820414E44203029
+:100530004646480D0A59503409455155095950311C
+:100540000D0A58503509455155093831480D0A5999
+:10055000503509455155093741480D0A58504C0945
+:10056000455155093230480D0A59504C09455155ED
+:10057000093230480D0A5850430945515509383061
+:10058000480D0A5950430945515509310D0A585033
+:100590005209455155092D58504C20414E442030A8
+:1005A0004646480D0A595052094551550959504C73
+:1005B0000D0A3B204241534520504F534954494F67
+:1005C0004E530D0A584231094551550930433948B7
+:1005D0000D0A59423109455155093735480D0A5818
+:1005E000423209455155093831480D0A59423209FC
+:1005F000455155093343480D0A3B2042414C4C209C
+:10060000544F20504F534954494F4E0D0A584F46AE
+:1006100046094551550934093B58204F4646534534
+:100620005420464F522042414C4C0D0A594F4646E9
+:10063000094551550933093B59204F464653455406
+:1006400020464F522042414C4C0D0A58425031092D
+:10065000455155095850312D584F46460D0A5942BB
+:10066000503109455155095950312B594F46460DC6
+:100670000A5842503209455155095850322D584FA9
+:1006800046460D0A594250320945515509595032D2
+:100690002B594F46460D0A584250330945515509CA
+:1006A0005850332D584F46460D0A5942503309458C
+:1006B0005155095950332B594F46460D0A5842504F
+:1006C0003409455155095850342D584F46460D0AA6
+:1006D0005942503409455155095950342B594F4608
+:1006E000460D0A5842503509455155095850352D87
+:1006F000584F46460D0A594250350945515509593A
+:1007000050352B594F46460D0A5842504C09455119
+:10071000550958504C2D584F46460D0A5942504CD9
+:10072000094551550959504C2B594F46460D0A5809
+:1007300042504309455155095850432D584F46469C
+:100740000D0A5942504309455155095950432B59F7
+:100750004F46460D0A5842505209455155095850C6
+:10076000522D584F46460D0A59425052094551558F
+:10077000095950522B594F46460D0A3B2042414CD5
+:100780004C20504F534954494F4E530D0A58424242
+:100790003109455155095842312D584F46460D0AE9
+:1007A0005942423109455155095942312B594F4659
+:1007B000460D0A5842423209455155095842322DD8
+:1007C000584F46460D0A594242320945515509597A
+:1007D00042322B594F46460D0A584242350945517F
+:1007E00055095850352D584F46460D0A5942423545
+:1007F00009455155095950352B594F46460D0A3B6D
+:00000001FF
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.e.bin b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.e.bin
new file mode 100644
index 00000000..83b0b6c7
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.e.bin differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.e.hex b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.e.hex
new file mode 100644
index 00000000..9f4e1ac0
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.e.hex	
@@ -0,0 +1,129 @@
+:10000000AC1811000121CA3C3AE422F6A0CD281711
+:10001000193AE522F6A0CD2817193AE622F6A0C330
+:10002000281721B53C0106193EFFCDAC18CDA51708
+:1000300021D53D3ECDCD6A1721D53E3ECCCD6A17A8
+:1000400021B63D010401AFCDAC1821D53C111320E0
+:100050003E06CD891721D63D010410AFCDAC182145
+:10006000DA3D01010F3E7FCDAC1821BA3F360011B9
+:100070001A2021D63D3E05CD891711202021D63EDC
+:100080003E05CD891721B53E360021BA3E3600C95E
+:100090007EE6F0FEA07EC2A118E60FFE0AC2A118FD
+:1000A000AF812777E6F07EC0F6A077C91E2051E524
+:1000B00077230DC2B0184A1600E11905C2AE18C95F
+:1000C000CDF8173A08204F212520AE7977CAFF18BE
+:1000D000A7CADD18211F203A2620C3EE183A262091
+:1000E000212B20BECA22182119203C3226205F165F
+:1000F00000E519222920E111050019222720C92134
+:1001000002234E36003A0523A7C20F1979174F2A4A
+:100110002920CD90182A2720CD90183E01320523A2
+:10012000C3551800E0A0A0A0E0000040604040E0FF
+:100130000000E080E020E00000E080C080E00000FF
+:10014000A0A0E080800000E020E080E0000020200F
+:10015000E0A0E00000E0808080800000E0A0E0A05F
+:10016000E00000E0A0E0808000000000000000004F
+:100170003E0808080808080022223E222200002229
+:1001800022141408001E22221E22221E1C22223E9D
+:100190002222220202020202023E1C22021C202211
+:1001A0001C1E22221E0A12221C08080808081C22F3
+:1001B000120A060A12223E02020E02023E1C2222ED
+:1001C0002222221C2222222222221CD6D7CBCECFB0
+:1001D000D0D0D1CBD2D3D4D5EBCD470D220020EB5C
+:1001E0003A0320A7C8222C203E10D303C9EBCD47E9
+:1001F0000D220020EBE9212E207EA7CA001A35C966
+:10020000237EA7CA0D1A352B3A312077C9237EA742
+:10021000CA191A353E00D305C92A2C207EA7C23D33
+:100220001A3E00D305237EA7C22E1AD303C9E61FA8
+:10023000C8D3033E2823222C20326420C9F24C1A52
+:10024000E67F32312023222C20C31C1A322F202398
+:100250003A31203D322E203E013230207E23222CA6
+:1002600020E67F074F060021731A097ED305237EFF
+:10027000D306C900003F131D1633183F1A051D0190
+:100280001F392027221124352513272B283F290F1A
+:100290002B192C1F2D212E212F1D30153109323BFA
+:1002A00032293317343F3427350D36313611373183
+:1002B000370F382B3805391D3935390B3A213A8437
+:1002C000020801140111010F010C030F030A008041
+:1002D000830208020D02110414021104140012001A
+:1002E00080830414020F020F0411040F040004138E
+:1002F00008140080820813080F020A0A0F0400087D
+:1003000013080F02110A1104000813080F02140A3F
+:1003100014040002140613020F0611020E0C0F0043
+:1003200000EBCD470DD5CD470D220020E146234EF1
+:1003300023EBC5E51AB67713230DC2341BE1012068
+:100340000009C105C2321BC921103E0601780F47C2
+:1003500011E0FFD25D1B7DE61FCA621B1B1970C333
+:100360004D1B210F3E068078074711E0FFD2711B1D
+:1003700013197DE61FCA7C1B70C3671BCD2218C3EF
+:10038000CC17EBCD470DCD2D11220020C9EBCD4769
+:100390000DCDB411220020C921E9227EA7CAAC1BD1
+:1003A000AF32D022E5112202CDCA1BE1237EA7CABB
+:1003B000BF1B3E1032D022E5111C02CDCA1BE12327
+:1003C0007EA7C8AF32D0221116027E36002B7721CD
+:1003D000B021CD2411EBCD2D1121D022AE12C9EBCD
+:1003E0007E23CD470D22002012C919212323360078
+:1003F000CD5907E603FE01C0773E14324320324256
+:1004000020C92140240601CD8C1D3A3720214024EB
+:100410000601A7C21C1CCD651DC31F1CCD4B1D3A78
+:100420003620210024A7C2321C01FF04CD6D1DC35C
+:10043000351CCD7A1D3A3520A7C2451C01FF04CDDD
+:100440006D1DC3481CCD7A1D360623AF06067723E3
+:1004500005C24E1C3660233A3820A7C2671C01FF34
+:1004600004CD6D1DC36A1CCD7A1D3A3920A7C27A0E
+:100470001C01FF04CD6D1DC37D1CCD7A1D215F24A1
+:100480000680CD8C1D3A3A20215F240680A7C297B2
+:100490001CCD651DC39A1CCD4B1D21440411003990
+:1004A0003E06CD3701216C0311C0373E06CD370122
+:1004B000216C031180373E06CD370101CC0221C0EB
+:1004C000373A3720A7CACB1CCD605201A40221C104
+:1004D000373A3620A7CADB1CCD605201720221C216
+:1004E000373A3520A7CAEB1CCD605201300321C337
+:1004F000373A3820A7CAFB1CCD605201540221C4F0
+:10050000373A3920A7CA0B1DCD605201440321C5DB
+:10051000373A3A20A7CA1B1DCD6052213A20060661
+:100520003E01A62B05C2221DA7C87EA7CA3B1D3EC1
+:100530000C11803A214A04CD3701C92134203601FB
+:10054000212B203421052034C322180E0211200053
+:10055000CD5C1D0E480600CD5C1D0E0278B67719E5
+:100560000DC25C1DC90E4C112000C35C1D36FE235C
+:10057000712305C2701D367F23C936062301000092
+:100580007123702370237123366023C90E4C112010
+:1005900000782F4778A677190DC2941DC91C193C05
+:1005A00061201C150A6C030B3615076C030D310115
+:1005B0002423BA1D15076C038D2619002423193C2A
+:1005C0006620021F2353510207201352020623D430
+:1005D0001D1AEB1B19010623012323E31D1507A197
+:1005E000038D261A021C16111D1D051509CB030BC0
+:1005F00036079E1D15068E030D3603079E1D150436
+:1006000094030D3604079E1D1C0A0B0C1C0A0B0CD0
+:100610001C0A0B0C1C091C1504C7030E3108CF1F44
+:10062000079E1D191E61201C0616079E1D08CF1F60
+:1006300013B02106C975E213542105813CE201F093
+:10064000224A1E132621098826F201F122561E1382
+:10065000262109AF3EE201F222621E13F82009B8FA
+:1006600040F201F3226E1E13F82009D068E21C014B
+:10067000F4229E1E0104238F1E139622207D3FE04C
+:100680001C06101506BD030D311504C3030E3613E9
+:10069000962228C578E01C060F195A61201C01F526
+:1006A00022B51E139622707D3FE0060F0E1C139696
+:1006B00022607D7DE013542106582EF2191E612020
+:1006C0001C13B02106817AF201F022D41E132621D8
+:1006D00006A02EE201F122E01E13262106A02EF232
+:1006E00001F222EC1E13F82006C850E201F322F8B2
+:1006F0001E13F82006C850F2079E1D08CF1F1326B0
+:100700002105813CF213F82005C975F201EC22188D
+:100710001F138221092068F201ED22241F13822178
+:10072000093F40E201EE22301F135421094836F2FE
+:1007300001EF223C1F135421096826E21C01F42218
+:10074000671F0104235D1F139622207D3FE01C06D6
+:10075000101506BD030D311504C3030E3613962282
+:1007600028C578E01C060F01F5227E1F1396227023
+:100770007D3FE0060F0E1C139622407D7DE0132680
+:100780002106A02EE213F82006C850E201EC2298C0
+:100790001F138221063050E201ED22A41F13822193
+:1007A000063050F201EE22B01F13542106582EE2FB
+:1007B00001EF22BC1F13542106582EF202F6229E8E
+:1007C0001D139622407D7DE019006120079D1D0AC2
+:1007D0000B0C0D093146314635313130453331434B
+:1007E0004434323133463146354344463831374656
+:1007F000314436303343304433303644333035338C
+:00000001FF
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.f.bin b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.f.bin
new file mode 100644
index 00000000..044a5264
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.f.bin differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.f.hex b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.f.hex
new file mode 100644
index 00000000..71733e99
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.f.hex	
@@ -0,0 +1,129 @@
+:10000000F0E608C0EB210E23060009347EFE02C292
+:10001000141036FF4F1A210B0019EB214405E6108E
+:10002000CA2610213E0509097E2312137E12C9211A
+:1000300096227EA7F03A01233DC03A0E23FE02C865
+:100040003A02201F210A23BEC8772A992211E322EF
+:100050003A0820A7CA58101B1AE608CA621001B055
+:10006000FF091AE610CA6C100150000922992221DA
+:100070009D221AE620CA7A1036011AE640C83602D6
+:10008000C9C83A0123A7C83A1120A7CA9A103A084A
+:1000900020A7CA9A103A1220A7C81100231AA7C095
+:1000A0002F123EE032AA22C9C83206201101231ABB
+:1000B000A7C03C12326620320B2321A22211620516
+:1000C000060D1A13772B05C2C210C9CA12113A11B4
+:1000D00020A7CAE1103A0820A7C2E1103A1220A7CF
+:1000E000C8214A05C30011CA12113A1120A7CAFD3E
+:1000F000103A0820A7C2FD103A1220A7C8215605C1
+:10010000116E20CD2D11119C20CD2D1111CA20C3AF
+:100110002D11214020112E000603197EE6BF770520
+:10012000C21A11C9012E00093DC22711C9D54623A3
+:10013000EBCD6411CD64112301D0041AE610C24442
+:100140001101A6041AE607C24D1101A30471237020
+:100150001AEBD11223C9AF010300097723732309D6
+:10016000772372C92323232323E51A7713D52B96EC
+:100170005F9F57E5A767C49311CD9B116B1E00CD00
+:100180009B11557CA7C49311E12B36002B722B7366
+:10019000D1E1C97A2F577B2F5F13C90E097A577B9C
+:1001A000175F0DCAB0117A1790D29E1180C39E11AD
+:1001B0007B2F5FC9D5CD470DE3E5CD5611D1E1C306
+:1001C0002D11213220DB0247DB02B8C0E68047AEAA
+:1001D000C87078A7C03E30D303016400D30405C2C1
+:1001E000DC110DC2DC113E10D3032104203421E1C7
+:1001F0001ACDE5193A0320A7C03A0420A7C8F32175
+:100200002752220020310024C33407004B0DA913CC
+:1002100097131E13671315136F1255125E1269128E
+:10022000BB13F21309141514981B2F143514F8126C
+:100230008D1B821B211B4412C0188801481BDF1B29
+:10024000ED19D819EB7E23CD470DD5CD470D2200F2
+:1002500020E1C33701EB5E2356EB220020C9EBCD32
+:10026000470DE3E5EB220020C9E1E3220020C9119C
+:10027000E422AF121312D306D3053206233E013215
+:1002800005233E11D3033224233E3C32642021E671
+:1002900022347EF53AF522A7C2A5123A0423A7C25A
+:1002A000BC12C3A912AF3202232198031110313EB0
+:1002B00003CD3701F1F5110E31CD4213F1F5CDF833
+:1002C00017F1D603C0D306D3053202233C320720F0
+:1002D0002108203E11D3033E783264207E2F77A779
+:1002E000C021052035C0AF3203203C321F2321F44A
+:1002F0001ACDE519CDA052C921AB22AF772B36F02C
+:1003000021EB22061B772305C205132F32E1223E83
+:1003100001320523C921E5227EFE02C834C92160CD
+:1003200013CDE5193E1E32642021E522347E1114DE
+:1003300036CD4213FE03C0AF772B7721231E220058
+:1003400020C9E5F521D3034F0600093E01CD370151
+:10035000F1E1C9840416041804140408060F00808F
+:1003600081012201210080AFD3063EF0D3053E116A
+:10037000D3033E0732642021E422347E111236CDAD
+:100380004213FE04C0AF77237732F62221171E22D4
+:100390000020210E2334C9EB4E234623CD470D0AFE
+:1003A000A7CAA513EB220020C9EB4E234623CD4755
+:1003B0000D0AA7C2B713EB220020C921EA227EA7AB
+:1003C000C83AF622A7C2D1132BB6C82B7EA7C823E2
+:1003D000231102231A3C12110E027E3600237721CC
+:1003E000B021CD2411EBCDB4112161207EA7C03600
+:1003F00074C921E9227EA7C83AF622A7C203142BAA
+:10040000B6C823111402C3DA1321E8227EA7C8114B
+:100410001A02C3DA13AF3C060421E822BECA16143E
+:100420002305C21C1421E72277112002C3DA13210D
+:10043000E822C3381421E9227E36002161203600EB
+:1004400021B021CD2411EB2126023A0820A7CA545D
+:1004500014212A02C32D113A0420213915FE09D294
+:1004600075143D0747078047CD00158007074F06E5
+:10047000002109150911002C0E047EA7CAA414E559
+:10048000D5C54F21CA157E23A7F286140DC2861446
+:100490007ECD43017E23A7F29014C1D11414E12331
+:1004A0000DC27A14D3040603DB00E680CAB8140632
+:1004B00000DB01E680C2A414CD0015074F07818040
+:1004C0004F060021CA160906031104201A96F2D914
+:1004D000142305C2CC14C35714F31A96122100003A
+:1004E000220720AF32332078320520322B2032030E
+:1004F0002079E60132112021BF1ACDE519C3EE168D
+:10050000DB02E607FE06D8AFC90304050A030405AB
+:100510000B050000000500000001040509050000AE
+:10052000000304050B030000000304060A0304068D
+:100530000B0204060B01040609030000000300007F
+:1005400000050A0000050B0000050B00000509006E
+:100550000003000000030000000304060B0300007A
+:1005600000020B00000204080B030000000300005F
+:1005700000050B000003000000020B0000070B0049
+:10058000000300000003000000030000000300005F
+:1005900000020B0000060B00000300000003000037
+:1005A000000300000003000000020B0000050B0028
+:1005B000000300000003000000030000000300002F
+:1005C00000020B0000020B0000A8800550555348A4
+:1005D000404F4E4540504C4159455240425554546D
+:1005E0004FCE05505553484054574F40504C4159F9
+:1005F000455240425554544FCE4050555348404FB9
+:100600004E45404F524054574F40504C415945522F
+:1006100040425554544FCE0F4FD203494E5345528A
+:1006200054404F4E45404144444954494F4E414C3B
+:1006300040434F49CE02494E534552544054574FC0
+:10064000404144444954494F4E414C40434F494E28
+:10065000D340494E53455254405448524545404179
+:1006600044444954494F4E414C40434F494ED302B4
+:10067000494E5345525440464F55524041444449D7
+:1006800054494F4E414C40434F494ED306464F527A
+:100690004054574F40504C415945524047414DC539
+:1006A00006464F524054574F40494E4E494E4740E0
+:1006B00047414DC505464F52405448524545404973
+:1006C0004E4E494E474047414DC5030201030201CA
+:1006D00002020102020106040206040204040204EA
+:1006E00004020404020202010808040404023EAAEF
+:1006F0000612211320772305C2F516211A2022297C
+:10070000203EA077211E2022272077212420773E1B
+:1007100001322620AF322520C9D5110700211C192E
+:100720003C193DC22117D1C9C5D5E5E5F5E60FCD88
+:100730001917F1E51F1F1F1FE60FCD1917EBE10E6B
+:1007400007461A0F0F0F0FB0B8C24E170F0F0FF654
+:1007500080E3AE77D511200019D1E313230DC241F8
+:1007600017E17EEEFF77E1D1C1C9C5D5E5E5E61F0A
+:10077000CD1917EBE10120003E07F51AAE771309FA
+:10078000F13DC27A17E1D1C1C9F51A4717A82FA0C8
+:1007900078F29A17CD6A17C39D17CD28172313F146
+:1007A0003DC28917C921132036AA233A2B20473E80
+:1007B000010E04F5F6A077F13C230DCAC91705C256
+:1007C000B31736AA230DC2C21736CBC921A43C01E8
+:1007D00007193EFFCDAC1821C63C11CE193E04CD01
+:1007E000891721C43D11D2193E06CD891721C73E74
+:1007F00011CB193E03CD8917AF21CA3C010118CD99
+:00000001FF
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.g.bin b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.g.bin
new file mode 100644
index 00000000..2b0b0b5f
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.g.bin differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.g.hex b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.g.hex
new file mode 100644
index 00000000..2c346918
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.g.hex	
@@ -0,0 +1,129 @@
+:1000000007FEC0D8AF3C321220CD81103E00321224
+:1000100020C93AE322E60132E3223A0123A7CAAE1D
+:1000200008110D203A9F22FE94DA390813FEA2DA55
+:10003000390813FEAEDA3908131A32E3223A96224F
+:10004000A7F253083AFE22A7C253083A0123FE2220
+:10005000CA5808AFCDE710C93A7220473AA0204FDE
+:100060003ACE20573A9A225FB8C8DA9208B9C8DA6D
+:100070007A08BAC8DA8608C3A0087B90477993B893
+:10008000DA9208C3A0087B914F7A93B9DA9208C339
+:10009000A008AF3C321220CDCB103E00321220C956
+:1000A000AF3C321220CDE7103E00321220C9CD59AC
+:1000B00007FEFFD8CD5907FE40D8AF3CCDA810CDE4
+:1000C0005907FE30DAFE08FEA0DA2709C3CF08116F
+:1000D0000D20CD5907E608CDF4081213CD5907E6D7
+:1000E00004CDF40812131213CD5907E602CDF4081B
+:1000F00012C32108A7CAFB083E40C93E20C9110D02
+:1001000020CD5907E60CCDF40847CD5907E602CDBE
+:100110001D09B012131213121312C32108A7CA2407
+:10012000093E08C93E10C9110D20CD5907E608CD7A
+:10013000F40847CD5907E6024FCD1D09B01213123E
+:1001400013CD5907E602CDF4084779EE02CD1D091B
+:10015000B0121312C321082107237EA7C836001F3F
+:10016000DCAE091FDC80091FDCDD091FDC550A1F1E
+:10017000DC160A1FDC5C0A1FDC8A0A1FDC920AC933
+:10018000F5110B231AA7C28B093E143D1221B02191
+:10019000CAA709FE0AF2A0091F36A8DAA00936AAE2
+:1001A0003E1E326620F1C936A2CDAC10F1C9F5C5AC
+:1001B0003A2123473A2223A8C1D303322123212005
+:1001C0002335CADB097EFE07C2D6093E3C326720D2
+:1001D0003E0477C3DB093E10326720F1C9F5110DEB
+:1001E000231AA7C2ED093EE03296223E273D12CAED
+:1001F000140A4F3AFD2247C5214020CD2411C17970
+:100200001F3E0432652036A8D2140A36A178FE04B7
+:10021000FA140A34F1C9F52103237E3CFE03C222FD
+:100220000AAF7757214B203AFE22CD24117A01B72D
+:1002300000A7CA4B0A01FFE811EC043DCA420A11AB
+:10024000C2047323722B3E0B32632011F5FF197E1B
+:10025000A1B077F1C9F53E10D303F1C9F511092317
+:100260001A2F12218C03A7CA6D0A216C033A0123AD
+:10027000A73E0FCA7A0AAF218C033262203A0820C7
+:10028000111A383E02CD3701F1C92A00202322007D
+:1002900020C9219451220020C921FE227EA7C84FE7
+:1002A000237EA7C03AFD22A7C03A0220FE03F2C671
+:1002B0000A7932FD2221D803118D263E07CD370160
+:1002C0003E01326520C97911F422FE04F2D00A13EE
+:1002D000123E04326320772A002023220020AF320E
+:1002E000F622C92108237EA7C836002A002023222F
+:1002F0000020C921F9227EA7C8320023AF77237ED0
+:10030000360021F41DA7C20C0B21FE1D220020C9BE
+:1003100021FB227EA7C8360023E6F0477EA7C03621
+:10032000FF3E2CD306AFD3053E11D3033E2232014C
+:10033000233E013264203A0220E61EB032F622212A
+:10034000161EFE39DA570BFEB9D2570B212D1EFEB1
+:100350007AD2570B21FB1E22002032252301EC22EA
+:10036000213602CDAD0B0303CDAD0B0303CDAD0B99
+:100370000303CDAD0B2100782299222100CC229ECF
+:100380002221D022772336902BEB219622060ECD08
+:10039000641136FFCD641136F03AE622FE02C83A07
+:1003A000E822A73E00CAA90B2F320423C9BED823D6
+:1003B0001104021DC815BE23D2B30BF57AA7CACB10
+:1003C0000BF2CA0B03020BC3CB0B02F1C921F722BC
+:1003D0004E234678B1C8AF772B7721EA1D3AF62233
+:1003E000D639FA0C0B781603FEF6DA050C1579FEF1
+:1003F00030DA050CFED0D2050C15FE60DA050CFED5
+:10040000A0D2050C15AF3206233C3224233205233B
+:100410007AA7C24C0C3A2323A7CA8B0CAF32052310
+:10042000F5C5D5E53E0611C037216C03CD37011166
+:1004300080372156043E06CD3701110039215C0476
+:100440003E06CD3701E1D1C1F1C38B0CDB02E608DA
+:10045000CA6B0C3A2523FE7A171717E604B2FE047E
+:10046000DA640C3D213420856F36013A2523FE7A6B
+:100470003F171717E604B2FE04DA7D0C3D21342045
+:10048000856F3601DB02E610C2150C4AC56A2600EC
+:10049000292901E60C097ED303322123237E32224F
+:1004A00023237E326420237E3220233E283267209D
+:1004B000C106002A002023E3E521081E09090909D5
+:1004C00022002021E422AF772377320E23212E024F
+:1004D00009095E2356210C363E080DFAE20C3D3D1B
+:1004E0002323EBC337011E0EFF0C1A0AFF0C1A0858
+:1004F000780612004B033AE122A7C83A0820A7CA9F
+:10050000140DDB002F47DB002F21E22211270DB84D
+:10051000CC4C0DC9DB012F47DB012F21E322113722
+:100520000DB8CC4C0DC90B8110CB10E710A810A84A
+:1005300010A810A8104B0D8110CB10E710A810A820
+:1005400010A810A8104B0D5E235623C9AEC84F0645
+:1005500001790FDA5F0D4F7807471313C3510D78F8
+:10056000AE77A0EB4E236669E911AA221AA7F0E63E
+:10057000074F06001AE6F012131AD62C121BDA9354
+:100580000D21390509BE1AD28D0DF6600CB112325B
+:10059000FA22C91AF6F00CB112C923CD470D4E2329
+:1005A000467AEB09EB722B732323C921AA227EA77B
+:1005B000F0E620C8110200C3C30D7EA7F0E620C8F4
+:1005C000110D00CDDF0FC2EC0FC97EA7F0E620C8E9
+:1005D000110D00CDDF0FC83A0720A7C2EC0F114064
+:1005E00023C3EC0F7EA7F0E50600CDFD0D4ACDFD3F
+:1005F0000DE10505C2FB0D7EE6BF7737C9C5CD9A73
+:100600000DC1594F047A96CA190E05C604FE08D0CA
+:1006100079A73E01F2190E3EFF2B2B2B2B36002320
+:1006200077232323C97EA7F0F62077E640C2520E37
+:100630007EE67F77E5110B00191163041FDA4E0E79
+:100640001173041FDA4E0E1181041FD2580E73234A
+:1006500072E1CDA50FC3820FE1C97EA7F0E5E501E8
+:100660000400095E230956E17AFE2801F700D274DE
+:100670000E01FF08E37EA1B077E37BFE05DA850E6D
+:10068000FEF4DA8F0EEB22F722E17EE6BF77C97A1D
+:10069000FEFBD2850EE1FEC0DA070F7BD675FE09A0
+:1006A000D2AF0E7AD6C8FE09D2AF0E2F32FA223A56
+:1006B000FB22A7C07AFED9DAC00E32F922C38A0E15
+:1006C0007BFE73D8FE7ED03AAB22FE20D8FEE0D06F
+:1006D000FE807A01C100DADC0E01C88091D8FE08E4
+:1006E000D04F3AAA22A7F078A779FAF70EFE03D2E4
+:1006F000FE0EC601C3FE0EFE04DAFE0ED60117176B
+:100700001717B032FB22C93AFE22A7C0E52172209A
+:100710003E01F5E57BC60996FE0BD2330F010500BD
+:10072000097AC60296FE0BD2330FE1F132FE22E1C6
+:100730003600C9012E00E109F13CFE08C2120FE1AA
+:10074000C921AA227EA7F0E640C87EE6074F069F91
+:100750007EE610CA580F06007EA0772323E5AF4738
+:10076000D301211F05097E21230509095E2356E3D4
+:10077000732372237723E3D5212D0509095E2356C0
+:10078000E1C1F57E02031A13D302DB03B677237EA1
+:100790000203AFD302DB03B677D5111F0019D1F1E5
+:1007A0003DC2820FC9010400095E2309562323CDEF
+:1007B000C90F79D301D5CD470DEB7E23E3EB73232E
+:1007C00072237723444DE1EBC97BE6074F0603AF65
+:1007D0007A1F577B1F5F05C2CF0F7AC62457C919EE
+:1007E0005E23567BB2234E230600EBC91A137723F0
+:1007F0001A1377790E1F094F0DC2EC0FC94F7EA750
+:00000001FF
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.h.bin b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.h.bin
new file mode 100644
index 00000000..884a620a
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.h.bin differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.h.hex b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.h.hex
new file mode 100644
index 00000000..1780602c
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/ei.h.hex	
@@ -0,0 +1,129 @@
+:100000000000AFD303C32000F5C5D5E5C30B060040
+:10001000F5C5D5E5C36F05FFFFFFFFFFFFFFFFFF3E
+:100020000601110000210020DB02E640C20B07D3CD
+:1000300004707EA8CA46004F7DE60179C24400B232
+:1000400057C34600B35F237CFE40C22F00D3042B6E
+:100050007CFE1FCA83007EA8CA6A004F7DE6017934
+:10006000C26800B257C36A00B35F782F77AECA4D3B
+:10007000004F7DE60179C27E00B257C38000B35FB6
+:10008000C34D00D304237CFE40CAA600782FAECA1D
+:10009000A1004F7DE60179C29F00B257C3A100B312
+:1000A0005FAF77C38300780747D225007AB3CAD5FC
+:1000B00000EBF91100200600210000390E10AF29D5
+:1000C000DAC4002F12133E1812130DC2BE0005C26F
+:1000D000B800C32D01310024210C28E521000011B6
+:1000E0003201010008AF86D304230DC2E60005C229
+:1000F000E6003CCA00011AE3EBC5CD4301C1EBE3C6
+:10010000137CFE20C2E200210050010008AF86D31C
+:1001100004230DC20E0105C20E013CCA26011AE3DA
+:10012000EBC5CD4301C1E17DFE0CCA0000D304C381
+:100130002D014847464542F57ECD430123F13DC29E
+:100140003701C9E67FFE30D25E01EB01E001F52305
+:100150007DE61FC2570109F13DC24E01EBC9E5D54D
+:10016000CD7401C51A137701200009C105C26301CE
+:10017000D113E1C90600D6304F6069292929090940
+:1001800001AA0109060AEBC9E10100001EFDF331D5
+:100190000040C5C5C5C5C5C5C5C5C5C5C5C5C5C559
+:1001A000C5C51DC29201310024E93C7E66666666C3
+:1001B00066667E3C181C1818181818183C3C3C7EC3
+:1001C00066607C3E06067E7E3C7E666038786066B1
+:1001D0007E3C666666667E7E606060603E3E0606C9
+:1001E0003E7E60667E3C3C3E06063E7E66667E3C0B
+:1001F0007E7E60703038181C0C0C3C7E66663C7E3F
+:1002000066667E3C3C7E66667E7C60607C3C3975C2
+:100210000DA0E2E4773C0D3975F4BF750D773CF421
+:1002200090C00DBF75E40A90E2F40A40E2F4B50311
+:10023000AF03BD039B03394E536853686B7A7A85CD
+:10024000899D899DA2B90000000000000000000007
+:1002500000000000183C7E6666667E7E66663E7E16
+:1002600066663E7E66667E3E3C7E660606060666E0
+:100270007E3C3E7E6666666666667E3E7E7E0606E0
+:100280003E3E06067E7E7E7E06063E3E060606064E
+:100290003C7E6606067676667E3C666666667E7E92
+:1002A000666666663C3C1818181818183C3C606076
+:1002B0006060606060667E3C6666763E1E1E3E76CE
+:1002C000666606060606060606067E7EC3C3E7E7E2
+:1002D000FFFFDBC3C3C366666E6E7E7E76766666A0
+:1002E0003C7E6666666666667E3C3E7E66667E3EF2
+:1002F000060606063C7E6666666666667E5C3E7E32
+:1003000066667E3E766666663C7E66063E7C606617
+:100310007E3C7E7E181818181818181866666666CF
+:10032000666666667E3C66666666667E3C3C181857
+:10033000C3C3C3DBFFFFE7E7C3C366667E3C181891
+:100340003C7E66666666667E3C18181818187E7EC7
+:100350006070381C0E067E7E494E53455254404311
+:100360004F494E47414D45404F5645524040404011
+:1003700040404040404040404241534542414C4C47
+:10038000484F4D450F56495349544F5255505354B9
+:1003900052494B4542414C4C4F555453494E474CA2
+:1003A000455350454349414C40424F4E55534054AC
+:1003B0005249504C45484F4D454052554E444F557B
+:1003C000424C45504C415957414C4B464F554C407F
+:1003D00042414C4C31323334404552524F52400727
+:1003E000504C415945524049534056495349544F46
+:1003F000522809414E4440424154534046495253C9
+:10040000542905434F4D505554455240504954438B
+:100410004845534042414C4C0843484F4F53454098
+:10042000594F5552405349444528034D4159405472
+:1004300048454042455454455240504C415945521C
+:100440004057494E4D4944574159455854524140EF
+:10045000494E4E494E47444F55424C4553434F52E7
+:100460004540FA0F010319197FFCBC98983C7E6641
+:100470006624660D18187EFFBD999B3D7E66662436
+:10048000660D18187EFFBD995A3C7E666624660488
+:1004900002C003C003C003C0030402F00F10081021
+:1004A00008100802C0C00D1818080C1F7D0D7D7CB7
+:1004B000266602060D303010183E7B9918387C6491
+:1004C0002C600D606020307CF6B13878CFCD40C014
+:1004D0000D0C0C08187C5F58DF1F323320300D0CD8
+:1004E0000C08187CDE99181C3E2634060D060604FE
+:1004F0000C3E6F8D1C1EF3B30203030303030303BF
+:10050000030303030303030303030103070E1C3860
+:1005100070E0C080FFFF80C0E070381C0E07030150
+:10052000100A020A108F3D8F3D8F3D0F3C8F3BFA22
+:10053000040A0514051605FA04FFC0804000D00423
+:10054000DE04EC04A604B404C204180038F1183028
+:1005500001F118A801F1185801E118D001E118F7CC
+:1005600038E104A300780002000079000000C03ADE
+:100570002323A7CABD0521432035C2BD0536143A41
+:100580004220A7CA9805AF3242203E07216C0311D2
+:100590008D26CD3701C3BD053E0F3242203A0523DB
+:1005A000A7C2B2053E0721A803118D26CD3701C38E
+:1005B000BD053E0721A103118D26CD3701CD690D63
+:1005C000219622E5E5E57EE608CCBA0DCDAB0D3AE5
+:1005D00002201F2A6820DADC052A6C20E5CDBA0D3E
+:1005E000E1CD250ECD410FE17EE608CC250EE1CD13
+:1005F0005A0EE1CDE40DD2020678A7C202062F32D0
+:100600000823CD6E06E1D1C1F1FBC921412035C2DD
+:10061000350636143A0320A7CA35063A2B202105A1
+:1006200020964F06003A0820A7CA2D060421B63EA0
+:10063000093E7FAE77219622E57EE608CA4206CDC6
+:10064000BA0D2A6A20E5CDCA0DE1CD250EE17EE680
+:1006500008CA5706CD250ECDF619CDC211CDC50657
+:10066000210506E53A02201FDA8B06C3A806111EF3
+:10067000231A3CFE03C27906AF123C214020CD2450
+:1006800011226A207EE608C0C3E40D111D231A3C26
+:10069000FE04C29606AF123C21B021CD2411226C7B
+:1006A000207EE608C0C3E40D111C231A3CFE05C2DF
+:1006B000B306AF123C21CA20CD24112268207EE669
+:1006C00008C0C3E40D2107237EA7C04721022035BF
+:1006D000C2DB06363C216020CDFD06216120CDFD28
+:1006E0000623CDFD0623CDFD0623CDFD0623CDFD3E
+:1006F0000623CDFD0623CDFD06320723C97EA7CAFA
+:10070000070735C2070737781747C9310024CD8856
+:100710000121022001420070230DC21707CDEE1601
+:100720003E01322B2021FFFF220920220B202194A1
+:1007300051220020FBD304213407E5CDF60C2A001A
+:10074000207EFE1CD2800723220020EB210C120702
+:100750004F0600097E23666FE9E5C52109200608DA
+:100760007E070707AE17172109207E1777237E170C
+:1007700077237E1777237E177705C26107C1E1C90A
+:10078000CDA707CD5709CDE30A3A0320A7C83A11F0
+:1007900020A7C4C807CD2F10CD990ACDF30ACD10DC
+:1007A0000BCD5907C3CD0B3A0220E6F8211B23BE1F
+:1007B000C877214020AF112E00193CFE0DC8E5F589
+:1007C000CDFD0FF1E1C3B6073AE122A7C83A0820F0
+:1007D000A7CA12083A9F22FEC3D83A9A22FE74DAB8
+:1007E000F807FE7ED2F8073A9F22FECAD20408CD4F
+:1007F0005907FEF2D20408C9CD5907FEFFD8CD59DA
+:00000001FF
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/einning.zip b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/einning.zip
new file mode 100644
index 00000000..9ffb75d8
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/ExtraInning/einning.zip differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Seawolf/fe.hex b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Seawolf/fe.hex
new file mode 100644
index 00000000..52e31856
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Seawolf/fe.hex	
@@ -0,0 +1,66 @@
+:020000040000FA
+:20000000350801080009360E2B36A32B2B732B702B2B722B36012B36807AC651571FDA2ECB
+:20002000083A2C20D610F8322C207BC6205F010D0009C3FD07E5D523235E23232356CD004E
+:200040000AEB010210CD3F0AD1E1C30208C8AF3206203A1020A7C821E921E5013004712382
+:2000600005C25E08E111253E3E04C3300BEB2200203A0320E607FE07C27C08AF322920C909
+:20008000F3EB220020AFD302D305D301E10100001100003E10311040C513BAC29808310029
+:2000A00024E9E1220920CD80082A0920E521040F11E0273E20C3300BDB0147DB012108208A
+:2000C00011DA09B8CC050BC9C83E20D3053E0F3225203A07204721042034E604CAE2087ED0
+:2000E0000FD83600233478E608CAF4083478E604CAF408347EE60F77C83A0220A7C0210535
+:20010000207EA7CA1A0935DB010707E60311540F835F1A320220322A20C93A0720E60CFE4B
+:200120000CC02B7EA7C8C306090401B80E303E0905203338E60EF10E041ACC0E023C0A06FE
+:2001400020E921253E0A2B20E921353E020F0409C30E0B2C011E000409B80E0B2C011E00D2
+:20016000064E09030408FC0E0C2C040ACC0E023C0A0620E921253E0905203338E60EF10E82
+:20018000015A0008096020EB0D201500E00001C4015A000809EF20750E9CE0FA00A800C0C5
+:2001A00001B400066309010F00030409290F0E3C07282220070A21200B004844424188848D
+:2001C00082811814121128242221C808F808C708C7084D08C708C708C708C708C708C708A1
+:2001E000C708C7087B05C708C7087C0B720BA208220BED0A860BE10A9F0ABC0A530A6D08B4
+:200200007BE6074F0603AF7A1F577B1F5F05C2060A7AC62457C9F57E0203EBB62312F1E507
+:2002200021200019D13DC2160AC9C5E51A1377230DC22C0AE101200009C105C22A0AC9AFF6
+:20024000C5E577230DC2420AE101200009C105C2400AC9EB4E2346235E23562BCD820AEB8E
+:20026000CD7A0A23EB3E30121312CDDC0AD5CDDC0A220020E13E04C3300B2B7EE640C8360F
+:2002800030C90A1F1F1F1FE60FC28E0A3E10C63012130AE60FC29A0A3E10C6301213C9EBA5
+:2002A00046230505CDDC0A4E237E23121B79121B7E23121B05C2B00A220020C9EBCDDC0A3B
+:2002C0001ACDDC0AD5CDDC0AD5CDDC0A220020EBA7CAD50AE3E1D13E0BC3300B5E235623EE
+:2002E000C91A13EB4E23462322002002C9EB46234E237E23CDDC0A220020EB36DB23712328
+:2003000036C92B2BE9AEC84F0601790FDA180B4F7807471313C30A0B78AE77A0EB4E23663C
+:2003200069E9EB7E23CDDC0AD5CDDC0A220020E1F57E23D630F2490B471C7BE61FC2420BAD
+:20034000141404C2390BC3310BE5D5218F0BCA590B010A00093DC2540BEB0120003E0AF50E
+:200360001A137709F13DC25F0BD1E113F13DC2300BC9EB7E23220020321020C9EB7E232216
+:200380000020321120C9EB5E2356EB220020C93C7E6666666666667E3C181C1818181818D5
+:2003A000183C3C3C7E66607C3E06067E7E3C7E6660387860667E3C666666667E7E60606007
+:2003C000603E3E06063E7E60667E3C3C3E06063E7E66667E3C7E7E60703038181C0C0C3C75
+:2003E0007E66663C7E66667E3C3C7E66667E7C60607C3C0C9360000000000000006099067D
+:200400000000000000000030CD020000000000000002C078E080F001C0F07C081C3E7FFF46
+:20042000FFBF1F02400280781E07017CF80C1000000000000000000000183C7E6666667E6B
+:200440007E66663E7E66663E7E66667E3E3C7E6606060606667E3C3E7E6666666666667E90
+:200460003E7E7E06063E3E06067E7E7E7E06063E3E060606063C7E6606067676667E3C6678
+:200480006666667E7E666666663C3C1818181818183C3C60606060606060667E3C66667614
+:2004A0003E1E1E3E76666606060606060606067E7EC3C3E7E7FFFFDBC3C3C366666E6E7E7A
+:2004C0007E767666663C7E6666666666667E3C3E7E66667E3E060606063C7E6666666666FA
+:2004E000667E5C3E7E66667E3E766666663C7E66063E7C60667E3C7E7E18181818181818CC
+:200500001866666666666666667E3C66666666667E3C3C1818C3C3C3DBFFFFE7E7C3C366D9
+:20052000667E3C18183C7E666666667E3C1818181818187E7E6070381C0E067E7E050C008E
+:2005400000080000000008000000600E000000E0CE3F0000E0DE0300F8F7DFF70F80F7DF45
+:20056000F700FFFFFFFFFFFFFFFFFF7FFFFFFFFF3FFEFFFFFF1FFEFFFFFF0F040C0000039C
+:2005800000003603000036030002B6030087FFF307E2FFF700FFFFFFFFFFFFFF7FFFFFFF61
+:2005A0003FFCFFFF1FFCFFFF0FF8FFFF07050C00004000000000F000000000F0000000802C
+:2005C000F01E000000FB0600FFFFFFFFFFFCFFFFFF3FFCFFFFFF1FFCFFFFFF0FF8FFFFFFC4
+:2005E00007F8FFFFFF03F8FFFFFF03040B4000000240800002400007024000070240F00728
+:2006000002FCF007F8FCFFFF7FFCFFFF3FF8FFFF1FF0FFFF0FF0FFFF0F040B80000000009D
+:20062000000001A0010001A0010001F0010001F80100F9F8FFFF7FF0FFFF3FF0FFFF1FF0F2
+:20064000FFFF0FE0FFFF0F020600031007E0FFFF7FFF3FFF1F020F100030027001FC00F80D
+:2006600011F03BE07FC03F801F003F001E0004004800F800F80111103838383838383838C6
+:200680003838383810101038010E1818181818181818181818180018010910101010101061
+:2006A000101010011010BA7CFE7C38541000100008000004003D3E3F4040404040404040C7
+:2006C00040404047414D45404F564552484947484053434F5245404040404040594F555219
+:2006E0004053434F5245494E5345525440434F494E5055534840425554544F4E534541408B
+:20070000574F4C463A3B3C3B3C3A3B3C3A3C3B3C3A3B3A3C3B3A3C3A3B3C3A3C3B3C3A3B2C
+:200720003C3A3B3C424F4E555354494D452D53434F5245455854454E4445441654494D45D7
+:20074000440F4C0F0141043D5A2F503F0141043D572F4D3F617181910303030101070008BD
+:200760001810383020287870606840485850F8F0E0E8C0C8D8D080889890B8B0A0A80D3DB7
+:20078000201400D800020D7B201400E000020DAD201400D800020DEB201500E000010E19B0
+:2007A000201500E000010E47201A00F000030D3D403400D8D8FE0D7B403400E0E0FE0DADC1
+:2007C000403400D8D8FE0DEB403500E0E0FF0E19403500E0E0FF0E47403A00F0F0FD0604BA
+:2007E0000206030501FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF03
+:00000001FF
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Seawolf/hg.hex b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Seawolf/hg.hex
new file mode 100644
index 00000000..2f8b4131
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Seawolf/hg.hex	
@@ -0,0 +1,66 @@
+:020000040000FA
+:200000000000310024C33A04E5D5C5F5C37E0000E5D5C5F53A1F20A7C23E00CDBC03CD2EBA
+:20002000012A16207EA7F23600E620CA3600CD5B030DEBCD2A0A3EFF321F20C369002A16CE
+:20004000207EA7F26200E640C250003600C362007EF62077CD650178E52A1C20444DE1CD34
+:20006000160ACD6803AF321F20DB0247DB0221072011CA09B8CC050BF1C1D1E1FBC93A1FC6
+:2000800020A7C21901CDBC03215F210644AF772305C28E002A18203E03F57DFE58C2A300D8
+:2000A000213120B4CAA000E5CDDE01E1D2B200221820110D0019F13DC299002A1820CD0C65
+:2000C000032A1A203E03F57DFE7FC2D000215820B4CACD00E5CDDE01E1D2DF00221A201183
+:2000E0000D0019F13DC2C600AF3230202A16203E04F57DFE5FC2FB0021E720B4CAF800E542
+:20010000CD5002E1D20A01221620111E0019F13DC2F100CD3103C369002A1A20CD0C032AEA
+:200120001A20CD3A012A1820CD3A01C369002A14207EA7F0CD6501C392017EA7F0E640C2EE
+:2001400045013600C97EF62077F5CD6501F1E610CA920179856FE52130207E2FE60777E12E
+:20016000D304C3B80123235E232323562323CD000A79323020D304D55E235623EB4E234669
+:2001800023E3EB732372237134237023221C20EBD1C9C5E51A13D303DB0377230DC294017C
+:2001A000AFD303DB0377012000E109C17DE6E0C292017C1FDA9201C9C5E51A13D303DB00A8
+:2001C000772B0DC2BA01AFD303DB0077012000E109C17DE6E0C2B8017C1FDAB801C97EA776
+:2001E000F0E523E607C2ED012323C337027E115F21A7F2F8011181214723867778A77EF2DE
+:200200001002FE01D21602E37EE6BF77E3C3160223BE2BD207027E0F0F0FE61F835FE37ECE
+:20022000E3E60747237E2F3C0F0F0FE607C603EB70233DC23002EB112F201A2F12C2470258
+:20024000237E23867723BEE137C07EE6BF7737C97EA7F0E523234E23237E2346807778FE62
+:20026000C0D20903FE30D275023A2420A7CA75023C3C3224207E23BED29C023EC086772B20
+:200280002B34347E232323CA96023688FEFCCA9C023698C39C02E37EE6BF77E31130201A58
+:2002A000A7C209033C1278E610CA0903110700197EA7C2C30219788347E610CA09037EA70E
+:2002C000CA0903E37EE6BF77E378D64047DAE00221A12123237EA7C2D302702371C309039F
+:2002E00021BE212323237EA7C2E30278C620116021FAF702118221790F0F0FE61F835F1A8B
+:20030000A7CA0903772371237037E1C97EA7F0E620C8CD5B03EB41AFE577230DC21903117D
+:200320002000E119487DE6E0C217037C1FDA1703C92A1420060A7DB4C23E03217220110D71
+:20034000001905C87DFEE7C24D03217F207EA7F24103221420237E238677C9110900195EB7
+:200360002356234E234623C93A2020A7C04721032035C28E03361E2102207EA7CA8803C673
+:20038000992777C288030601211020CDAE03211120CDAE03212120CDAE0323CDAE0323CDC2
+:2003A000AE0323CDAE0323CDAE03322020C97EA7CAB80335C2B80337781747C90127200A8B
+:2003C000C60AFE1EC2C803AF02035F160021F30B19EB0A3CE61F0221E027856F0120001AB4
+:2003E0001377097DE6E0FE60C2DF03C92100001100000E02AF86234779BC78C2F503E5210E
+:20040000290419BE3E40CA0E04213204197E21E9211977E1130C0C3E12B9C2F40321E921DC
+:200420001108303E08CD300B768D79001F586DEAC52A4848474746464545CDA208DB02E67E
+:20044000E0FEE0CCEC032102203E09060070233DC24D04212909220020FB215904E52A0093
+:20046000207EA7C27D04CDA406CDCE04CDBF043A0220A7C8CD4C07CDB808C38C0423EB2154
+:20048000E809074F0600097E23666FE93A0320FE1DF801022011E921CD820AEBCD7A0A2341
+:2004A000362C23EB012B20CD820AEBCD7A0A23363023363021E921112F3E3E06C3300B21CD
+:2004C0002A207EA7C8360021A609220020C92120207EA7C836001FDC01061FDC0E061FDC44
+:2004E000F7041FDC34061FDCE9051FDC73051FDC6C051FDC1105C9F52126207EA7CA0F05CB
+:20050000353E04D3053E193223203E0F322520F1C9212E207EA7C23D0536013A07200FE61D
+:2005200070CA3D05C609212B20BED23D053E2032022021330F11033C3E0CC3300B21C9207B
+:20054000011E00097DFE5FCA5C057EA7F24305AF322120322D203E01320220C9212909229D
+:2005600000203A2B20210620BED877C9216309220020C92A002023220020C9C83A0220A7DE
+:20058000C83A2120A7C0212D207EE61FC87EE60F1F0620A7CA99050610B077D302212120BD
+:2005A0003608E610C2A905363C3E02D3053E0F32252021C920111E00197EA7FAB805110802
+:2005C0000019360E2B36752B369C2B36E02B36FA2B2B115E0FEB3A0820E61F4F0600097E4D
+:2005E000EB772B36002B36C0C9F5212D207EE610C2FF053E1FD302773E08D305CDEA07F13B
+:20060000C9F5AFD305D3013A2D20D302F1C9F521F0217EA7CA3206360023575E360023FEF8
+:200620002C01030ADA2A06010520EBCD3F0AEBC31206F1C9F53A0320E60FF65032222001CD
+:2006400029200A3CFE07C24A06AF0221DE0F856F7E47FE06C26B063E04D3053E193223205F
+:200660003E023226203E0F32252078212C20110D00193DC2710678EB211E207E34217E0F4A
+:200680001FD28B0621AE0F78F61047783D070707E638856F0E087E23121B0DC2960678F69C
+:2006A000C012F1C921C1217EA7C836002356E5212420010D00093DC2B50601080009360E9E
+:2006C0002B36552B2B2B36012B2B722B36002B4636E03A0220A7C2DB06E1C97801570FE6E7
+:2006E00007814F11E921CD820A3E301213120A212B20862777E14E234623E578C62021C28F
+:2007000009DA070721BA0979070707E607856F7ED3013E01D3053E1E322520781624C620C1
+:20072000FA25071628790F0F0FE61FCA2F073DFE1EC235073DF6A05FCDDB073E2D32242091
+:2007400021EA213E03CD300BE1C3A70621A3217EA7C823C610070707E607116720010D0060
+:20076000EB09093DC261071AD60896FEECD27107092B2B3600EB2B7EC630E6F057360023AE
+:200780005E23E5CD000A7BE61FCA96073DCA96073DFE1CF290075FCDDB074204044B0CC53D
+:2007A0007BC6605FD5420CC53E1E3225203E0F3224203E10D3057BE60221400F856F5E234D
+:2007C00056EBD17E23CD300BD17E23CD300BD121B50E3E03CD300BE1C34F0721F0217E2319
+:2007E000B623C2DE072B732B72C93A2B20FE40DAF4073E39322C20217F201150507EA7FA58
+:00000001FF
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/ba.bin b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/ba.bin
new file mode 100644
index 00000000..c1b7a358
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/ba.bin differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/ba.hex b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/ba.hex
new file mode 100644
index 00000000..1ff72ea2
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/ba.hex	
@@ -0,0 +1,129 @@
+:1000000000040BCD1B0A35061E000AF317160C2040
+:10001000571810F8080F9E170C011A211A162060A5
+:100020003E1A18207B3E0C8041210C8837210E2A75
+:100030000147200C01462018B81A18EE0D18241B91
+:100040000C1E4B200E030224210C0826210E010158
+:100050004C200C0A4F2000060F0010FE0C01062059
+:10006000189A1A041B061C022C0402211C0F3004CF
+:1000700014231C0632041B371C02340C010D2118FA
+:10008000611B060500160B21741916212194181402
+:100090000C208218160C2168190414CD1B06320A94
+:1000A0008218041B061C02280402211C0F2C041BAE
+:1000B000371C02300C0121210A7B180410231C0874
+:1000C0002818611B160C20A2180605000AC418186F
+:1000D000611B0412F41B0726041B061C02280402E1
+:1000E000211C0F2C0413BA1B0630041B371C0232D0
+:1000F000060500140C20F01818611B0C010D2104DA
+:1001000012CD1B072604012B1C0E30060500160B12
+:10011000215519160C2025191403210B19160C2131
+:1001200070190A0B1916102140190401FC1B0E301E
+:100130000405C91B14300C01102118611B0A0B198E
+:100140001603211D190412CD1B06300C01032118C2
+:10015000611B0A0B191410217419185C1B1403215C
+:100160007419185C1B0A7419162121701918611B67
+:100170000C02062018EA1A10F80E2A0147200C017A
+:1001800046200E000016200E0000182018EE0D0C60
+:10019000014D2018F71A10F8146020A41918EE0D5C
+:1001A0000C0060200CC837210CC041211A162060B9
+:1001B0003E1A18207B3E18B81A0409E11B0C3506BC
+:1001C0003C000409CD1B0C351202EA1B0C35061E3F
+:1001D000001202CD1B0C3518241B0C1E4B200E03E5
+:1001E0000224210C0B26210C014C20000C01622062
+:1001F0000604001A1620603E1A18207B3E0413CD18
+:100200001B863E063C000A96190CC837210CC041DB
+:1002100021187B1A0E341216200E907818201A1608
+:1002200020603E0402881C8F3E1A18207B3E0C0280
+:1002300006200C010D21140C20471A0404841C0E06
+:100240002618611B0A4D1A0404CD1B0E26140B211F
+:100250005B1A0411101C07290A611A0411CD1B072F
+:1002600029140C216F1A0411411C072C0A751A0459
+:1002700011CD1B072C0605000A361A210024CD904B
+:100280001A06DD111F0036011936802305C2861AB1
+:1002900001FF20712305C2931AC9DB021F1FE60369
+:1002A0004F060021B01A09095E2356EB220020C92F
+:1002B0006318A218BB18CF1811322121E51ACDD22C
+:1002C0001AB612C911362121E91ACDD21AF604B68E
+:1002D00012C906037E2B121B05C2D41ACDBB0DE634
+:1002E00003C9807F0600807B0620AFD305D307219A
+:1002F0000E207EE60177C9210E207EF604773A06AD
+:10030000203D211B1BCA0B1B211F1BDB02E6032305
+:100310003DF20F1B7E320320326220C970605040D4
+:10032000907560453A1620473A1820B8C2331BCD65
+:10033000BB0D1F114A1BD23C1B11531B21B82006B9
+:10034000091A13772305C2411BC9C080FF007980B9
+:10035000FD00ACC08000007980FD00AC210C203491
+:10036000C9210C2035C92A1820CDA61B3A06203DEC
+:10037000C27F1B2A1C20CDB41BD8EB221C20C92A0B
+:1003800016207C8227577D8B275F2A1E20CDB41B29
+:10039000DAA31BEB221E202A16202220202A182056
+:1003A0002222202A1620EB2A1A20CDB41BD8EB22B9
+:1003B0001A20EBC97BBDC07ABCC94445504F534994
+:1003C00054403340434F494E5340414E44404040D7
+:1003D000404040404040404040404040404040401D
+:1003E00040474554405245414459474F47414D4588
+:1003F0004F5645524445504F534954403140434F66
+:10040000494E40414E445052455353405448454054
+:100410004F4E4540504C4159455240425554544F1F
+:100420004E4F524445504F53495440324E4440433E
+:100430004F494E40414E4450524553534054484515
+:100440004054574F40504C415945524042555454E6
+:100450004F4E455854454E4445444D495353494FDA
+:100460004E50524556494F555340484947484053CE
+:10047000434F5245434F4D42494E454440494E53E8
+:1004800045525440434F494E353600FFFFFFFFFFB2
+:10049000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6C
+:1004A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5C
+:1004B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4C
+:1004C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3C
+:1004D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2C
+:1004E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1C
+:1004F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0C
+:10050000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB
+:10051000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEB
+:10052000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDB
+:10053000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB
+:10054000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBB
+:10055000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAB
+:10056000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9B
+:10057000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8B
+:10058000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7B
+:10059000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6B
+:1005A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5B
+:1005B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4B
+:1005C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3B
+:1005D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2B
+:1005E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1B
+:1005F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0B
+:10060000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA
+:10061000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEA
+:10062000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDA
+:10063000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCA
+:10064000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBA
+:10065000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAA
+:10066000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9A
+:10067000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8A
+:10068000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7A
+:10069000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6A
+:1006A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5A
+:1006B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4A
+:1006C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3A
+:1006D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2A
+:1006E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1A
+:1006F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0A
+:10070000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9
+:10071000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9
+:10072000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD9
+:10073000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC9
+:10074000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB9
+:10075000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA9
+:10076000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF99
+:10077000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF89
+:10078000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF79
+:10079000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF69
+:1007A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF59
+:1007B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF49
+:1007C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF39
+:1007D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF29
+:1007E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF19
+:1007F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF09
+:00000001FF
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/dc.bin b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/dc.bin
new file mode 100644
index 00000000..67dcfb99
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/dc.bin differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/dc.hex b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/dc.hex
new file mode 100644
index 00000000..84cf6525
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/dc.hex	
@@ -0,0 +1,129 @@
+:100000003910CD2610110500C36212EB7EF6407741
+:10001000E620110101CA1A1016FFCD3910CD2610A5
+:10002000111000C362123E04321221325320C92B38
+:100030007EF620773E10324A2021BA207E82773A1F
+:10004000BE20A72160FEF257101DF25A102ABD20D3
+:100050007C2F677D2F6F2322BD2021B8207EE6F7FD
+:1000600077AF321621C921B8207EE6BF77326320F0
+:100070003A0620A7CA97103E20D3073E0A324520F1
+:10008000216420347EFE05DA9110AF320320C3973D
+:100090001021EC19C29A10216617220020C93A4B90
+:1000A00020A7C02120FE22BD202AB9207CB5C2C2D3
+:1000B000103ABC20C607218000FABE1026FF22B9E4
+:1000C00020C97CFE02D8FE102602DABE10FEFED049
+:1000D00026FEC3BE10003A4B20A7C0326420EBCDF1
+:1000E0003412C03217213A1C21FE181606DAF2101B
+:1000F00016027EE6B9B277E608320D20F5213721E7
+:10010000CA06112141217EF6407721B8207EE6BF44
+:1001100077F1CA1F113A06203DC21F1132BC203EA2
+:1001200008D3073E0A3245203E06324920320E21CE
+:100130002160207EA7C8360021CD1B11863E3E13CC
+:10014000CD1E013200212133217EF640773A2F2146
+:10015000A7F4B81AC3EE0D3A4B20A7C0EBCD34126A
+:10016000C03217217EE6041E1CCA6E111EFC23231A
+:1001700046237ED61532C0202B2B2B7EE604171784
+:1001800017F605AE774F23360A21B8207EF6107792
+:100190007883FEFCDA9811AFFEF0DA9F113EF03260
+:1001A000BC203A1C215778FE04D2B71179E608CA60
+:1001B000C411161BC3C411FED4DAC41179E608C2F7
+:1001C000C41116007A1F1FE607D603C2D71111000B
+:1001D00000CD5212C3EC11DAE011CD3D12C3EC1187
+:1001E0002F3CCD3D127A2F577B2F5F1322BD20EB82
+:1001F00022B92021242135C207123602237E3CFE7B
+:1002000006D207127723353E0A324B203A0620A742
+:10021000CA1C123E10D3073E0A324520110100CD00
+:1002200062123A06203DC0CDBB0DE6033CFE03C082
+:10023000321721C97EE608C83A1721A7C957AFC6A9
+:100240004015C23F125F3A2521210000193DC24CE2
+:1002500012EB01C0FE3A2521210000093DC25B12CC
+:10026000C9003A0620A7C83A6020A7CA75127B8346
+:10027000275F7A8A573A0D20A701172021603EC2D6
+:10028000861203032E7B0A8327020B0A8A27025F4A
+:100290003A06203DC29E123A0D20A7C2FA12DB0296
+:1002A0001F1F1F1FE603CAFA12C604577BBADAFAE9
+:1002B000121161201AA7C2FA123C12E5C53A0620B3
+:1002C0003D213A13CACA12213E13DB02E603233D45
+:1002D000F2CE121103201A86271221521C11863EDB
+:1002E0003E08CD1E01131313133E07CD1E01219AA4
+:1002F0000E2214203C321320C1E1E5210621E5CD78
+:100300002013CD20133630E1D13E05326520477EE3
+:10031000FE3078C21E0123133DC20E13326520C980
+:100320000ACD2E1377230A03CD32137723C90F0F7B
+:100330000F0FE60FC69027CE4027C9353025204540
+:10034000353020002140207EA7C836001FF5DC8410
+:1003500013F11FF5DC5913F1C93A0E21A7C271132D
+:100360003A6020A7CA7613210F21347EFE07D27689
+:100370001321032034C921B8207EE6BF77216617F8
+:10038000220020C93A0A20A7C03C3209202A0420B2
+:10039000220020C92141207EA7C836001F1FF5DC9E
+:1003A000C813F11FF5DC0F14F11FF5DC2415F11F44
+:1003B000F5DC1215F11FF5DC5015F11FF5DC9E156B
+:1003C000F11FF5DC9115F1C9212F21CDD113213376
+:1003D000217EA7F0E620C87EE610C2E7137EF61065
+:1003E000773E10324A20C97EF64077235E2323569B
+:1003F000CDB2012127217EA7CAFE13212B2136026F
+:1004000023732372233A6020773E02325220C93E82
+:100410001E324920210E21354E06002125140909DE
+:100420007E23666FE9A214881475146B1449143185
+:1004300014213F14110B323E0A326220C31E0143C5
+:100440004F554E5440444F574E21CD1B110B323E59
+:100450000ACD1E012163207EA7CA6114AF773262E4
+:10046000203E19CDE4060633C37C143E1FCDE406BE
+:100470000632C37C143E19CDE406063121062170F4
+:10048000110E343E01C36C0121A80E221420219CC0
+:10049000141104343E06321320C36C014C41554EF6
+:1004A0004348AF32492032622021CD1B1104343E33
+:1004B00006CD6C012137217EE640CAC014214121BE
+:1004C0007EEE04E6FD77E60423237ECAD714C61F1A
+:1004D000FEF3DAD7143EF3D603D2DD14AF32BC20DC
+:1004E000237ED61632C02021000022B92021000030
+:1004F00022BD203A0620A7C83EC832B8203E04D309
+:10050000073E1E324520324B203E01324D2032162E
+:1005100021C9CDBB0DF61FE67F3247202166200E94
+:10052000F8C33315CDBB0DF61FE67F324820216F8F
+:10053000200E0011030006027EA7FA4A1523712B34
+:100540000C3E80F248153EA077C91905C23815C97E
+:100550003E3C3246203A0221A7C0CDBB0DF5CD6509
+:1005600015F11F1F1FE60F217420232323233DF2C3
+:100570006A157EA7F0E640C07EF62077235E2356FC
+:10058000CDB201237EA7C8EB0E2070093DC28A15AB
+:10059000C93A0920A7C02A002023220020C9AFD3CE
+:1005A00007C92142207EA7C836001FF5DCD615F109
+:1005B0001FF5DCFA15F11FF5DC4C16F11FF5DC0810
+:1005C00017F11F1FF5DC1017F11FF5DC2017F11FC5
+:1005D000F5DC4617F1C93A1320A7C021122135CA0C
+:1005E000F4153E04325320CDBB0DD618D2EA15C601
+:1005F00019C3E406AFD305D306C9212721CD0316BD
+:10060000212B217EA7C835235E235623CA25163EFB
+:100610001E3252207EA72145163E03CA22162148CB
+:10062000163CC31E017EA721CD1B3E03CA30163CDB
+:10063000CD1E013A6020A7CAB81A2100217EA7C2A8
+:10064000B81A34C9C9353030313030302104213541
+:10065000CAB5167E3DCA61162222213E5A32512069
+:10066000C921CD1B1106323E05CD6C01110E363E5F
+:1006700004CD1E013E5A32512021F5161109323E99
+:100680000DCD1E012102171104343E06326020CD2B
+:100690006C0121CD1BE511863E3E03CD1E0121FDDF
+:1006A000163E05CD1E01131313133E06CD1E01E1A8
+:1006B0003E01C31E0121CD1B1109323E0DCD1E018D
+:1006C0001104343E06CD6C01322321320521326201
+:1006D00020676F3ABC20FE0DD2DD162E40FEE4DA14
+:1006E000E51621C0FF22B92021A0FD22BD20210452
+:1006F0000B222521C9544152474554534053434F7F
+:100700005245444F55424C45210E207EE6F777C9AD
+:10071000210E207E1FD07EE6FE773E0A324E20C993
+:1007200021B8203A1621A73E1ECA2E173E06324D8A
+:1007300020C24017CDBB0DE607477EE6F8B077C96B
+:100740007E3CE6F977C93A2621324C203A1121A79E
+:10075000C02ABD203A1621A7018000CA601706FFF3
+:100760000922BD20C90018661B0C000620060200E5
+:100770000C011B210413CD1B863E1A1620603E1A65
+:1007800018207B3E0402CD1B8F3E18EA1A08059EF6
+:10079000171204EC1B08311204F01B083500160C6C
+:1007A00020571810FE080F0D180413611C06241A98
+:1007B0001A200D26040D611C0129040C0F1C0E29A2
+:1007C0000404EC1B1A291A1C200D2B0409611C05BA
+:1007D0002E0409741C0E2E04046A1C172E040C40EF
+:1007E0001C08300404EC1B14301A202009321A2291
+:1007F000201232160C200718040B7D1C0A35063C0B
+:00000001FF
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/fe.bin b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/fe.bin
new file mode 100644
index 00000000..270d08eb
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/fe.bin differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/fe.hex b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/fe.hex
new file mode 100644
index 00000000..e688f1b4
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/fe.hex	
@@ -0,0 +1,129 @@
+:1000000023702370093DC2FF07C94E237E5FD301D1
+:10001000232356CDB20179E61021B908CA2208215E
+:10002000C808C3A407350846085708660877088833
+:10003000089908A808080000C07FFAC3C07F000123
+:1000400080007E000000080000FE070002A8FFA854
+:10005000FF0002FE070000070000C007F83FBEFADD
+:10006000F83FC0070000080000E28F2288FEFF2250
+:1000700088E28F02800000080000FE03C35FFE03D9
+:1000800080000001007E0000080000E07F4000FFCB
+:1000900015FF154000E07F0000070000E003FC1F93
+:1000A0005F7DFC1FE0030000080000F1471144FFE2
+:1000B0007F1144F147014000000710046003600312
+:1000C0008000600360031004080870313EF81F18B8
+:1000D000393CFC7C3D9E0F0798003A1521A7C021B2
+:1000E000B8207EA7F03ABC204F3AC020573AC32030
+:1000F000825F3A3221C602BADA0209BB212F21DC23
+:1001000010093A3621C602BADA3209BBD0213321AE
+:100110007EA7F0E620C0237E91C610FE20D02323C8
+:100120007E92C608FE17D02B2B2213213E013215DA
+:1001300021C93E32BADA4209BBD02178201E08C359
+:100140004F093E42BADA7409BBD02198201E077EBF
+:10015000A7F26B09E640C26B09237E2B91FE10D2F9
+:100160006B092213213E02321521C9232323231DAB
+:10017000C24F09C93E52BADA8209BBD0216620C3F8
+:100180008D093E62BADAAB09BBD0216F20CD93094D
+:10019000D823237EA7F0E640C0237E91C608FE1731
+:1001A000D02B2213213E03321521C93EAEBADA15F7
+:1001B0000ABBD021372179FE6BDACA09214121FE21
+:1001C00087D2CA093E07321521C97EA7F022132122
+:1001D0007EE640CAF009232379C60C96FE30D03261
+:1001E0001C21237E92C607FE16D03E04321521C97B
+:1001F0007EE6040600CAFA09061423237990C60C89
+:1002000096FE1CD0321C21237E92C607FE16D03EDD
+:1002100005321521C93EC4BAD8BBD021412179FE8F
+:100220006BDACA09213721FE87DAC409C3CA09007B
+:100230003A1B21A7C03A0E20E602213721CA430A01
+:100240002141213A0620A7C2500ACD520BC35A0AB7
+:100250003DC25A0A7EE608C4520B7EA7F01FD26B3D
+:100260000A23352BC26B0A7EE6DE77E5CD700BE103
+:100270004EC53A1921FEAFDA7C0A3EAFFE58DA834A
+:100280000AC62847792323E60811B3C9CA920A117E
+:10029000C9B3787723FE6CDA9B0A5372235FD301CC
+:1002A000CDB20173237223791FD2BC0AE6103E0936
+:1002B00001DA0BC2C90A01AD0BC3C90AE6043E0745
+:1002C00001070CC2C90A012A0C77E5EB11DBFFF527
+:1002D0000A03D302DB0377230A03D302DB0377236A
+:1002E0000A03D302DB0377230A03D302DB0377235A
+:1002F0000A03D302DB037723AFD302DB037719F1C1
+:100300003DC2CF0AD1C179E640C0791F0120FFDA92
+:10031000150B0160FE1FD21C0B0160FF1FDA240BBE
+:100320000C0C0C0C09EB2373237217015D0CDA34EF
+:100330000B014D0C0A032377EB111F00F50A03D3C1
+:1003400002DB037723AFD302DB037719F13DC23C15
+:100350000BC97EE604CA5A0B3E0CC604473ABC20C1
+:1003600090D2650BAFFE58DA6C0BD628321921C932
+:10037000232323235E2356237EA7C84F3600E5EBB5
+:1003800011DBFFAF77237723772377237723771941
+:100390000DC2840BE1235E2356237EA7C83600EBF3
+:1003A0003D011F00702370093DC2A40BC9FFFF1F50
+:1003B0000000F0FF3F000000FFFF000000F0FF071B
+:1003C000000000FF1F000000F8FF00000018FC07FD
+:1003D000000000C01F00000000FC0000F8FFFF004C
+:1003E00000FCFF0F0000FFFF0000E0FF0F0000F81F
+:1003F000FF000000FF1F0000E03F180000F80300AE
+:1004000000003F0000000000001800000080FF0115
+:100410000000F8001F00F00F00F00F1F000000F8B0
+:10042000FFFFFFFFFF0000180000000018000000A1
+:1004300080FF010000F8FF1F00F0FFFFFF0FFFFF2C
+:10044000FFFFFFFFFFFFFFFF00001800000F384411
+:1004500028387CFEBABABA383828286C6C071038AD
+:1004600038BAFE828200AFD303D305D307CDBD0EC9
+:10047000DB02E64021091AC27D0C2166172200200A
+:1004800021800CE5FBD3042A00207EA7CAA10CF32F
+:1004900023220020EB21DB0E4F0600097E23666F2E
+:1004A000E9CD4413CDA60FCD9413CDA60FCDA21543
+:1004B000CD6E0DCDA60FCDA50DCDE60CCDD70DCDB6
+:1004C000A60F211E217E3CFE10DACD0CAF772174E1
+:1004D00020232323233DF2D10C7EA7F0E640C07EEB
+:1004E000E6DF77C30B0E3A6020A7C0060021742018
+:1004F000232323237EA7F0E640CAFD0C047EE610EA
+:10050000CAF00C78FE0CD8320221FE0FC03A062049
+:10051000A7CAEE0D2105217EA7C0342B36033E016C
+:100520003200213E013251203262203211212165F8
+:100530000D1106323E05CD6C0121000022BD2021A7
+:10054000C0207EFE41DA4A0D3641216A0D110E3679
+:100550003E04CD1E0121800E2214203C32132011B6
+:100560000001C36212424F4E5553313030303A4E83
+:1005700020A7C0210720DB012FE64047AEC87078D6
+:10058000A7C8210E207EF601773E0A324E20210CAC
+:1005900020343A0620A7C03C320920320A202157D5
+:1005A00018220020C93A0D21A7C8210B21DB012FF9
+:1005B000E6207723DB012FE61077C9E52108200E1E
+:1005C000007EA7C2C70D3D47E61DEACF0D0E80781D
+:1005D0000FE67F8177E1C90103200AA7C821062120
+:1005E000E5CD2013E1118F3E3E02C31E01002178AC
+:1005F0002011520E1A137723E6101A1377231A13B9
+:10060000772323CAF40DAF320221C97EE6034F23BC
+:100610005E2356CDB201D5E521330E09095E23567E
+:10062000E11A23774FE1131A77790E20094F0DC293
+:10063000260EC9390E420E490E08183C66C3C36621
+:100640003C180642183C3C1842083C7EFFFDF9620B
+:1006500034188000308122308244308066308188B6
+:100660003082AA3080CC3081EE308210408032401F
+:1006700081544082764080984081BA4092DC4000AC
+:10068000850100010C020F010C010D020F01000198
+:100690000C020F010C010D030F00830208020D0272
+:1006A000110414021104140081012201220122010B
+:1006B00022012201220122012204250000F3E1018E
+:1006C0000000310040C5C5C5C5C5C5C5C5C5C5C542
+:1006D000C5C5C5C5C53DC2C50E310024E9240F06F8
+:1006E0000F170F250F370F400F450FF70E000F5252
+:1006F0000F5D0F7F0F850FEB7E23220020C3BD0E01
+:10070000216C01C3090F211E01E5EB7E235E2356F8
+:1007100023D5CD770FE1C9AF320920EB7E324420DB
+:1007200023220020C9AF320A20EB7E32432023CDA2
+:10073000770FEB220420C9EB5E2356EB220020C981
+:10074000CD740F12C9EB4E234623CD770FEB7023E8
+:1007500071C9CD680FC2590FEB220020C9CD680FB7
+:10076000CA640FEB220020C9EB5E2356231A5E23D6
+:100770005623A7C9EB7E235E235623220020C9EB14
+:10078000CD770FEBE9EB4E234623E5210621CD2063
+:1007900013CD20133630E1CD770F2106213E0532EF
+:1007A0006520C30E13001115211AA7C82A13214F63
+:1007B000AF12EB4721BC0F09097E23666FE9CC0F0E
+:1007C000F40F0B10D610571166109E10EB7EE60446
+:1007D000110001CAD80F16FFCD2F103A0620A7CA64
+:1007E000EE0F210E207EF608773E3C32502011504D
+:1007F00000C36212EB7EF64077CD7C15110000CD70
+:00000001FF
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/hg.bin b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/hg.bin
new file mode 100644
index 00000000..49fe0690
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/hg.bin differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/hg.hex b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/hg.hex
new file mode 100644
index 00000000..12ee63f3
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/hg.hex	
@@ -0,0 +1,129 @@
+:100000000000310024C31700FBC9000000000000FD
+:10001000F5C5D5E5C34C03DB0217DA2000C3660C37
+:100020000601110000210020D304707EA8CA3F0001
+:100030004F7DE60179C23D00B257C33F00B35F2355
+:100040007CFE40C22800D3042B7CFE1FCA7C007EAD
+:10005000A8CA63004F7DE60179C26100B257C3634D
+:1000600000B35F782F77AECA46004F7DE60179C2B4
+:100070007700B257C37900B35FC34600D304237C33
+:10008000FE40CA9F00782FAECA9A004F7DE60179E4
+:10009000C29800B257C39A00B35FAF77C37C0078B1
+:1000A0000747D225007AB3CACE00EBF9110020062B
+:1000B00000210000390E10AF29DABD002F12133EC7
+:1000C0001812130DC2B70005C2B100C308013100F8
+:1000D00024210C36E5210000110D010100041A1342
+:1000E00086D304230DC2E00005C2E0003CCAFA003A
+:1000F000E3EB3E01CD1E01EBE31B137CFE20C2DBD4
+:1001000000E17DFE0CCA0000D304C30801004828AA
+:10011000477A460F456244BB43F242514137F57E70
+:1001200023D630F2370147137BE61FC23001141487
+:1001300004C22701C31F01E5D5CDC4010E203A65D5
+:1001400020D601F5DA490136FF09F13E0AF51A1306
+:10015000DA54012F7709F13DC24D01DA600136FF13
+:10016000D1E113F13DC21E01326520C9F57ED630C2
+:1001700023E5CDC4013E0AE5F51A13CD9C01CD9CC3
+:1001800001CD9C01CD9C01F1E10E40093DC27701FA
+:100190000184FD09EBE1F13DC26C01C91F0E00D2E3
+:1001A000A4010E0F1FF53E00D2AD013EF0B1772342
+:1001B000F1C90603AF7A1F577B1F5F05C2B4017AEE
+:1001C000C62457C93CFE0BFACC01D60621CF01014B
+:1001D0000A00093DC2D201EBC93C7E6666666666CE
+:1001E000667E3C181C1818181818183C3C3C7E6693
+:1001F000607C3E06067E7E3C7E6660387860667E69
+:100200003C666666667E7E606060603E3E06063ED8
+:100210007E60667E3C3C3E06063E7E66667E3C7E9A
+:100220007E60703038181C0C0C3C7E66663C7E6626
+:10023000667E3C3C7E66667E7C60607C3C000000A6
+:1002400000000000000000183C7E6666667E7E6648
+:10025000663E7E66663E7E66667E3E3C7E66060640
+:100260000606667E3C3E7E6666666666667E3E7E08
+:100270007E06063E3E06067E7E7E7E06063E3E06E6
+:100280000606063C7E6606067676667E3C666666F2
+:10029000667E7E666666663C3C1818181818183C20
+:1002A0003C60606060606060667E3C6666763E1EB4
+:1002B0001E3E76666606060606060606067E7EC3B1
+:1002C000C3E7E7FFFFDBC3C3C366666E6E7E7E7661
+:1002D0007666663C7E6666666666667E3C3E7E66E2
+:1002E000667E3E06060606081C1C1C1C1C1C1C0800
+:1002F0001C3E7E66667E3E766666663C7E66063E92
+:100300007C60667E3C7E7E181818181818181866CF
+:10031000666666666666667E3C66666666667E3CA1
+:100320003C1818C3C3C3DBFFFFE7E7C3C366667EA1
+:100330003C18183C7E666666667E3C1818181818CD
+:1003400018181818181899FF7E3C18003A1A21A797
+:10035000C25803DB00321921210E207EEE0277D332
+:10036000033A2221A7C283033AC020FE90DA7D031C
+:1003700021B8207EE608C27D037EE6F877CDA10491
+:10038000CDDA08CD300ACD4207216620CD1F0421E9
+:100390006920CD1F04216F20CD2704217220CD2795
+:1003A00004CDBD03CDED03CD89063A2321A7C2B705
+:1003B00003322221321121E1D1C1F1FBC9114020C8
+:1003C0001AA7C04721022035C0363C3A6220A7C296
+:1003D000E3032103207EA7CAE303C6992777C2E37C
+:1003E0000306010E01214320CD0B0412C921442034
+:1003F0001141201AA7C0470E08CD0B04121142204C
+:100400001AA7C0470E08CD0B0412C97EA7CA15044F
+:1004100035C2150437781747230DC20B04C90011E4
+:10042000FF500EFFC32C0411F9600E017E17D01788
+:10043000DA3B04237986BBC240042B3600C3720426
+:10044000775FD301CDB20123798677E60321820459
+:100450000E06093DF252040E06EB1A13D302DB031B
+:100460007723AFD302DB0377790E1F094F0DC25AF2
+:1004700004C9237E5FD301CDB2013E080E1FEB708D
+:100480002370093DC27F04C9187E18187E185020B9
+:10049000500A040A24247E7E24240A040A50205090
+:1004A000003AB820A7F0CD700521B8207EE640C202
+:1004B000B40477C97EF62077E60F3218217EE61065
+:1004C000CAD204AE77232323235E2323232356C3D8
+:1004D00023052AB920444D2ABB20097CFEF1DAEA23
+:1004E00004CD680522B920C3D5045FD30122BB2007
+:1004F0002ABD20444D2ABF20097CFEF0DA130521D5
+:10050000B8207EE6F777AF321621CD680522BD20F0
+:10051000C3F3045722BF207AFED0DA23053E063209
+:100520001521C9CDB201EB22C120E53A18214F2196
+:10053000870509095E23561A1332C3204F21020092
+:1005400039221F21E1311E001A13D302DB03772366
+:100550001A13D302DB037723AFD302DB0377390D02
+:10056000C248052A1F21F9C9782F67792F6F23C93F
+:10057000E620C82AC1203AC320111E00722372232C
+:1005800072193DC27C05C99B05BA05D705F4051152
+:10059000062E063F06BA055E0673060F800340046A
+:1005A00080028003C007E00FA00BA00BA00B80030C
+:1005B000800380028002C006C0060E8003400488CB
+:1005C000228823F83FF01F800380038003C007E0E8
+:1005D0000E600C383818300E8003400488028803FF
+:1005E000F807F01F803380238203FE1FFE1F0018D0
+:1005F000003800300E8003400480228023C03FF08A
+:100600001F980388038083F0FFF0FF300038001844
+:10061000000E18303838600CE00EC00780038003ED
+:100620008003F01FF83F882388224004800308C01D
+:1006300007C007E0EFFFFFFFAF0363800180000FFB
+:10064000C001C002C0038000C001F001F003F00748
+:10065000F00DC001C00180018001800380030A0009
+:100660000180038003A00BE00F2008A00A00010016
+:100670000000020A000180038003A00BE00F2008A5
+:100680002008000100008000003A1320A7C82110B4
+:10069000207EA7CA980635C9237EA7CAA506352B92
+:1006A0003A0F2077C9237EA7CAB00635AFD305C954
+:1006B0002A14207EA7C2BC06321320C9F2C606E661
+:1006C0007F320F20237E321120233A0F20477EA74E
+:1006D000FAD9063E0132122005783210207E2322FC
+:1006E0001420E67F4F060021F50609097ED3052375
+:1006F0007ED306C90000003F131D1633183F1A05AC
+:100700001D011F392027221124352513272B283FAF
+:10071000290F2B192C1F2D212E212F1D30153109AA
+:10072000323B32293317343F3427350D36313611F9
+:100730003731370F382B3805391D3935390B3A2108
+:100740003A00211D21347E1F212F21DA5107213348
+:10075000217E17D017DAF00717DA0A087EE6074F6E
+:10076000E6043E01CA69073EFF2386775FD301FE98
+:1007700020CA7907FEE0C27F072B7EEE0477232391
+:1007800035C2860736062356C298077A32012114ED
+:100790007BA7FA9707151572CDB201212508090923
+:1007A0007E23666FEB1A134F1A13D302DB037723F2
+:1007B0001A13D302DB037723AFD302DB0377790E5F
+:1007C0001E094F0DC2A8072100217EA7C83A0121AA
+:1007D0003DC2DA07CDE307C3C71AFE1FC0CDE3074A
+:1007E000C3BB1A713A1D211F113221D0113621C904
+:1007F0003600235E232356CDB201EB3E080E1E7059
+:00000001FF
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/spacwalk.zip b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/spacwalk.zip
new file mode 100644
index 00000000..f9b530ae
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/spacwalk.zip differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.a b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.a
new file mode 100644
index 00000000..bd675dec
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.a differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.b b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.b
new file mode 100644
index 00000000..5d164292
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.b differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.c b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.c
new file mode 100644
index 00000000..1cfd2e87
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.c differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.d b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.d
new file mode 100644
index 00000000..3bd482c3
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.d differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.e b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.e
new file mode 100644
index 00000000..efcc5800
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.e differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.f b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.f
new file mode 100644
index 00000000..07a82f8c
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.f differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.g b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.g
new file mode 100644
index 00000000..6f921f66
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.g differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.h b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.h
new file mode 100644
index 00000000..4172f1bc
Binary files /dev/null and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/Spacewalk/sw.h differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/Invaders.qsf b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/Invaders.qsf
index 3bd720e6..71dad2db 100644
--- a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/Invaders.qsf	
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/Invaders.qsf	
@@ -41,7 +41,7 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/Invaders_mist.sv
@@ -49,13 +49,6 @@ set_global_assignment -name VHDL_FILE rtl/invaders.vhd
 set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
 set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/invaders_memory.sv
-set_global_assignment -name QIP_FILE rtl/pll.qip
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/keyboard.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
 set_global_assignment -name VHDL_FILE rtl/dac.vhd
 set_global_assignment -name VHDL_FILE rtl/sprom.vhd
 set_global_assignment -name VHDL_FILE rtl/spram.vhd
@@ -177,4 +170,6 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 # -------------------------
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu8080.sv
 set_global_assignment -name VHDL_FILE rtl/invaders_video.vhd
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/Release/Invaders.rbf b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/Release/Invaders.rbf
index 45dcaa92..6d8d413a 100644
Binary files a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/Release/Invaders.rbf and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/Release/Invaders.rbf differ
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/Invaders_mist.sv b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/Invaders_mist.sv
index eada9535..cc276564 100644
--- a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/Invaders_mist.sv	
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/Invaders_mist.sv	
@@ -1,6 +1,6 @@
 `define generic
 //`define noDIP
-`define invaders
+//`define invaders
 `ifdef invaders 
 	`define dip = 8'b00000000 
 `endif
@@ -15,18 +15,21 @@
 	`define dip = 8'b00000000 //untested
 `endif
 
-//`define blueshark  Sync Problems
+//`define blueshark  //TILT(IMPUTS)  //60hz
 `ifdef blueshark 
 	`define dip = "00100100" //todo
 `endif
 
 //TODO
-//`define lrescue
+`define dip = 8'b00000000 
+`define lrescue
 
 //`define zzzap280
 //`define gunfight
 //`define sflush
-//`define seawolf
+//`define seawolf  //60hz
+//`define spacewalk  //60hz
+//`define extrainning
 //`define dogpatch
 //`define jspecter
 //`define invadrev
@@ -62,19 +65,25 @@ localparam CONF_STR = {
 `ifdef invaders "Space Inv.;;", `endif
 `ifdef supearth "SEarthInv.;;", `endif
 `ifdef slaser "Space Laser;;", `endif
-`ifdef blueshark "Blue Shark;;", `endif
-`ifdef noDIP "Midway 8080.;;", `endif
-	"O2,Joystick Control,Upright,Normal;",
-	"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
+`ifdef spacewalk "Space Walk;;", `endif
+`ifdef extrainning "Extra Inn.;;", `endif
+
+`ifdef blueshark "Blue Shark;;", `endif//NW
+`ifdef seawolf "Sea Wolf;;", `endif//NW
+`ifdef noDIP "Midway 8080;;", `endif
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
 	"O5,Overlay, On, Off;",
 	"T6,Reset;",
-	"V,v1.00.",`BUILD_DATE
+	"V,v1.10.",`BUILD_DATE
 };
 
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
 
 wire clk_sys, clk_mist;
 wire pll_locked;
-
 pll pll
 (
 	.inclk0(CLOCK_27),
@@ -90,85 +99,16 @@ wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
 wire  [7:0] kbjoy;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoubler_disable;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
 wire        ypbpr;
-wire        ps2_kbd_clk, ps2_kbd_data;
-wire [7:0] audio;
-wire hsync,vsync;
-assign LED = 1;
-
-wire hblank, vblank;
-wire ce_vid;
-wire hs, vs;
-wire r,g,b;
-
-video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
-(
-	.clk_sys(clk_mist),
-	.ce_pix(clk_sys),
-	.ce_pix_actual(clk_sys),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R({r,r,r}),
-	.G({g,g,g}),
-	.B({b,b,b}),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.scandoubler_disable(scandoubler_disable),
-	.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
-	.hq2x(status[4:3]==1),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-);
-
-mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
-(
-	.clk_sys        (clk_mist       ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoubler_disable(scandoubler_disable),
-	.ypbpr          (ypbpr          ),
-	.ps2_kbd_clk    (ps2_kbd_clk    ),
-	.ps2_kbd_data   (ps2_kbd_data   ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-);
-
-
-
-keyboard keyboard(
-	.clk(clk_mist),
-	.reset(),
-	.ps2_kbd_clk(ps2_kbd_clk),
-	.ps2_kbd_data(ps2_kbd_data),
-	.joystick(kbjoy)
-	);
-	
-//wire m_up     = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3];
-//wire m_down   = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2];
-wire m_left   = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1];
-wire m_right  = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0];
-
-wire m_fire   = kbjoy[0] | joystick_0[4] | joystick_1[4];
-wire m_start1 = kbjoy[1];
-wire m_start2 = kbjoy[2];
-wire m_coin   = kbjoy[3];
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
 
 wire [15:0]RAB;
 wire [15:0]AD;
@@ -187,9 +127,9 @@ invaderst invaderst(
 	.Rst_n(~(status[0] | status[6] | buttons[1])),
 	.Clk(clk_sys),
 	.ENA(),
-	.Coin(m_coin),
-	.Sel1Player(~m_start1),
-	.Sel2Player(~m_start2),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
 	.Fire(~m_fire),
 	.MoveLeft(~m_left),
 	.MoveRight(~m_right),
@@ -239,6 +179,48 @@ invaders_video invaders_video (
 	.O_VSYNC(vs)
 	);
 
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_mist),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({r,r,r}),
+	.G({g,g,g}),
+	.B({b,b,b}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.rotate({1'b0,status[2]}),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_mist       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
 dac dac (
 	.clk_i(clk_mist),
 	.res_n_i(1),
@@ -246,6 +228,38 @@ dac dac (
 	.dac_o(AUDIO_L)
 	);
 
-assign AUDIO_R = AUDIO_L;
+wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_fire2 = 0;
+reg btn_fire3 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_mist) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h14: btn_fire3       <= key_pressed; // ctrl
+			'h11: btn_fire2       <= key_pressed; // alt
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
 
 endmodule
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/build_id.v b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/build_id.v
index 21a4b647..c74c7f56 100644
--- a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/build_id.v	
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/build_id.v	
@@ -1,2 +1,2 @@
-`define BUILD_DATE "190102"
-`define BUILD_TIME "031130"
+`define BUILD_DATE "190604"
+`define BUILD_TIME "154728"
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/pll.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/pll.vhd
index b1553aeb..feed4923 100644
--- a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/pll.vhd	
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/pll.vhd	
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -145,9 +145,9 @@ BEGIN
 		clk0_duty_cycle => 50,
 		clk0_multiply_by => 10,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 27,
+		clk1_divide_by => 9,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 40,
+		clk1_multiply_by => 8,
 		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -232,7 +232,7 @@ END SYN;
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -261,9 +261,9 @@ END SYN;
 -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -311,9 +311,9 @@ END SYN;
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
diff --git a/Computer_MiST/Galaksija_MiST/GALAKSIJA_MiST.jpg b/Computer_MiST/Galaksija_MiST/Doc/GALAKSIJA_MiST.jpg
similarity index 100%
rename from Computer_MiST/Galaksija_MiST/GALAKSIJA_MiST.jpg
rename to Computer_MiST/Galaksija_MiST/Doc/GALAKSIJA_MiST.jpg
diff --git a/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qpf b/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qpf
index e6a13e46..ca9c65ff 100644
--- a/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qpf
+++ b/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qpf
@@ -27,5 +27,4 @@ DATE = "14:32:28  October 06, 2018"
 
 # Revisions
 
-PROJECT_REVISION = "Galaksija_Mist"
-PROJECT_REVISION = "AtomElectron_Mist"
+PROJECT_REVISION = "Galaksija_Mist"
\ No newline at end of file
diff --git a/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qsf b/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qsf
index 3b886477..7ec0d75d 100644
--- a/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qsf
+++ b/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qsf
@@ -41,7 +41,7 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:11:53  MARCH 09, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/Galaksija_MiST.sv
@@ -56,11 +56,6 @@ set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
 set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
 set_global_assignment -name VHDL_FILE rtl/spram.vhd
 set_global_assignment -name VHDL_FILE rtl/sprom.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
 set_global_assignment -name VERILOG_FILE rtl/pll.v
 set_global_assignment -name VHDL_FILE rtl/dac.vhd
 
@@ -218,7 +213,6 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
 # end ENTITY(Galaksija_MiST)
 # --------------------------
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/galaksija_keyboard1.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/galaksija_keyboard2.sv
-set_global_assignment -name VHDL_FILE rtl/keyboard.vhd
+set_global_assignment -name QIP_FILE ../../Mist_FPGA/common/mist/mist.qip
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/galaksija_keyboard.sv
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Computer_MiST/Galaksija_MiST/Galaksija_Mist.srf b/Computer_MiST/Galaksija_MiST/Galaksija_Mist.srf
index fcf54634..8daf77db 100644
--- a/Computer_MiST/Galaksija_MiST/Galaksija_Mist.srf
+++ b/Computer_MiST/Galaksija_MiST/Galaksija_Mist.srf
@@ -23,6 +23,7 @@
 { "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(307): case item expression covers a value already covered by a previous case item" {  } {  } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
 { "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(321): case item expression covers a value already covered by a previous case item" {  } {  } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
 { "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(318): case item expression covers a value already covered by a previous case item" {  } {  } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Inferred dual-clock RAM node \"mist_video:mist_video\|osd:osd\|osd_buffer_rtl_0\" from synchronous design logic.  The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." {  } {  } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
 { "" "" "" "*" {  } {  } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""}
 { "" "" "" "*" {  } {  } 0 10235 "" 0 0 "Quartus II" 0 -1 0 ""}
 { "" "" "" "*" {  } {  } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Computer_MiST/Galaksija_MiST/Galaksija_Mist_assignment_defaults.qdf b/Computer_MiST/Galaksija_MiST/Galaksija_Mist_assignment_defaults.qdf
new file mode 100644
index 00000000..fbb4920a
--- /dev/null
+++ b/Computer_MiST/Galaksija_MiST/Galaksija_Mist_assignment_defaults.qdf
@@ -0,0 +1,692 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 21:09:05  March 28, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus II software and is used
+#    to preserve global assignments across Quartus II versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT On
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone IV GX"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name SYNTHESIS_SEED 1
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE Standard
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN On
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name VREF_MODE EXTERNAL
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_LARGE_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/Computer_MiST/Galaksija_MiST/Snapshot/Galaksija_Mist.rbf b/Computer_MiST/Galaksija_MiST/Snapshot/Galaksija_Mist.rbf
index 3f029567..14500238 100644
Binary files a/Computer_MiST/Galaksija_MiST/Snapshot/Galaksija_Mist.rbf and b/Computer_MiST/Galaksija_MiST/Snapshot/Galaksija_Mist.rbf differ
diff --git a/Computer_MiST/Galaksija_MiST/rtl/Galaksija_MiST.sv b/Computer_MiST/Galaksija_MiST/rtl/Galaksija_MiST.sv
index c52a1432..ec5c169f 100644
--- a/Computer_MiST/Galaksija_MiST/rtl/Galaksija_MiST.sv
+++ b/Computer_MiST/Galaksija_MiST/rtl/Galaksija_MiST.sv
@@ -21,100 +21,90 @@ module Galaksija_MiST(
 `include "build_id.v"
 localparam CONF_STR = {
 	"Galaksija;;",
-	"O23,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
+	"O23,Scanlines,Off,25%,50%,75%;",
 	"T9,Reset;",
 	"V,v1.00.",`BUILD_DATE
 };
-wire clk_1p7, clk_25, clk_6p25;
-wire ps2_kbd_clk, ps2_kbd_data;
-wire [2:0] r, g; 
-wire [1:0] b; 
-wire hs, vs;
-wire  [1:0] buttons, switches;
-wire			ypbpr;
-wire        forced_scandoubler;
-wire [31:0] status;
-wire [7:0] audio;
-wire [10:0] ps2_key;
-wire        ps2_clk;
-wire        ps2_data;
-assign LED = 1'b1;
 
+assign LED = 1'b1;
+assign AUDIO_R = AUDIO_L;	
+
+wire 				clk_1p7, clk_25, clk_6p25;
 pll pll (
 	 .inclk0 ( CLOCK_27   ),
 	 .c0     ( clk_1p7  ),
 	 .c1     ( clk_25  ),
 	 .c2     ( clk_6p25 )
 	);
-
-
-mist_io #(
-	.STRLEN($size(CONF_STR)>>3)) 
-user_io (
-	.clk_sys(clk_25),
-	.CONF_DATA0(CONF_DATA0),
-	.SPI_SCK(SPI_SCK),
-	.SPI_DI(SPI_DI),
-	.SPI_DO(SPI_DO),
-	.SPI_SS2(SPI_SS2),	
-	.conf_str(CONF_STR),
-	.ypbpr(ypbpr),
-	.status(status),
-	.scandoubler_disable(forced_scandoubler),
-	.buttons(buttons),
-	.switches(switches),
-	.ps2_key(ps2_key),
-	.ps2_kbd_clk(ps2_clk), 
-	.ps2_kbd_data(ps2_data)
-	);
-
-video_mixer #(
-	.LINE_LENGTH(320), 
-	.HALF_DEPTH(0)) 
-video_mixer (
-	.clk_sys			( clk_25		),
-	.ce_pix			( clk_6p25		),
-	.ce_pix_actual	( clk_6p25		),
-	.SPI_SCK			( SPI_SCK		),
-	.SPI_SS3			( SPI_SS3		),
-	.SPI_DI			( SPI_DI			),
-	.R					( video[5:0] 	),
-	.G					( video[5:0] 	),
-	.B					( video[5:0] 	),
-	.HSync			( hs				),
-	.VSync			( vs	   		),
-	.VGA_R			( VGA_R			),
-	.VGA_G			( VGA_G			),
-	.VGA_B			( VGA_B			),
-	.VGA_VS			( VGA_VS			),
-	.VGA_HS			( VGA_HS			),
-	.scanlines		(forced_scandoubler ? 2'b00 : {status[3:2] == 3, status[3:2] == 2}),
-	.scandoubler_disable(1'b1),
-	.hq2x				(status[3:2]==1),
-	.ypbpr			( ypbpr			),
-	.ypbpr_full		( 1				),
-	.line_start		( 0				),
-	.mono				( 1				)
-	);
 	
-wire [7:0] video;
+wire 		[7:0] video;
+wire 				hs, vs, blank;
+wire  	[1:0] buttons, switches;
+wire				ypbpr;
+wire        	scandoublerD;
+wire 	  [31:0] status;
+wire 		[7:0] audio;
+wire       		key_pressed;
+wire 		[7:0] key_code;
+wire       		key_strobe;
+
+
 galaksija_top galaksija_top (
    .vidclk(clk_25),
 	.cpuclk(clk_6p25),
 	.audclk(clk_1p7),
    .reset_in(~(status[0] | status[9] | buttons[1])),
-   .ps2_key(ps2_key),
-	.ps2_clk(ps2_clk), 
-	.ps2_data(ps2_data),
+   .key_code(key_code),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
 	.audio(audio),
 	.cass_in(UART_RXD),
 	.cass_out(UART_TXD),
    .video_dat(video),
    .video_hs(hs),
    .video_vs(vs),
-	.video_blank()
+	.video_blank(blank)
 );	
 
+mist_video #(.COLOR_DEPTH(6)) mist_video(
+	.clk_sys(clk_25),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R(blank ? 0 :video[5:0]),
+	.G(blank ? 0 :video[5:0]),
+	.B(blank ? 0 :video[5:0]),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.scandoubler_disable(1'b1),//scandoublerD),
+	.scanlines(scandoublerD ? 2'b00 : {status[3:2] == 3, status[3:2] == 2}),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_25         ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.status         (status         )
+	);
+
 dac #(
    .msbi_g(7))
 dac (
@@ -123,6 +113,4 @@ dac (
    .dac_i(audio),
    .dac_o(AUDIO_L)
   );
-
-assign AUDIO_R = AUDIO_L;	
 endmodule
diff --git a/Computer_MiST/Galaksija_MiST/rtl/build_id.v b/Computer_MiST/Galaksija_MiST/rtl/build_id.v
index 8b8fb56a..0e492bbf 100644
--- a/Computer_MiST/Galaksija_MiST/rtl/build_id.v
+++ b/Computer_MiST/Galaksija_MiST/rtl/build_id.v
@@ -1,2 +1,2 @@
-`define BUILD_DATE "181202"
-`define BUILD_TIME "164146"
+`define BUILD_DATE "190604"
+`define BUILD_TIME "171020"
diff --git a/Computer_MiST/Galaksija_MiST/rtl/galaksija_keyboard1.sv b/Computer_MiST/Galaksija_MiST/rtl/galaksija_keyboard.sv
similarity index 96%
rename from Computer_MiST/Galaksija_MiST/rtl/galaksija_keyboard1.sv
rename to Computer_MiST/Galaksija_MiST/rtl/galaksija_keyboard.sv
index 92b943d9..1a15bc43 100644
--- a/Computer_MiST/Galaksija_MiST/rtl/galaksija_keyboard1.sv
+++ b/Computer_MiST/Galaksija_MiST/rtl/galaksija_keyboard.sv
@@ -1,8 +1,10 @@
-module galaksija_keyboard1(
+module galaksija_keyboard(
 	input 		clk,
 	input 		reset,
 	input  [5:0]addr,
-	input  [7:0]ps2_key,
+	 input [7:0] key_code,
+	 input key_strobe,
+	 input key_pressed,
 	output [7:0]key_out,
 	input 		rd_key
 );
@@ -23,7 +25,7 @@ always @(posedge clk) begin
 			begin
 				keys[num] = 1'b0;
 			end
-				case (ps2_key[7:0])					
+				case (key_code[7:0])					
 					//nix 00
 					8'h1C : keys[8'd01] = 1'b1; // A
 					8'h32 : keys[8'd02] = 1'b1; // B
@@ -93,7 +95,7 @@ always @(posedge clk) begin
 					
 				endcase
 				if (keys[8'd53] == 1'b1) begin//shift
-					case (ps2_key[7:0])	 
+					case (key_code[7:0])	 
 						8'h1C : keys[8'd01] = 1'b1; // a
 						8'h32 : keys[8'd02] = 1'b1; // b
 						8'h21 : keys[8'd03] = 1'b1; // c
diff --git a/Computer_MiST/Galaksija_MiST/rtl/galaksija_keyboard2.sv b/Computer_MiST/Galaksija_MiST/rtl/galaksija_keyboard2.sv
deleted file mode 100644
index 2fa82933..00000000
--- a/Computer_MiST/Galaksija_MiST/rtl/galaksija_keyboard2.sv
+++ /dev/null
@@ -1,256 +0,0 @@
-module galaksija_keyboard2(
-	input 		clk,
-	input 		reset_n,
-	input  [5:0]addr,
-	input 		rd_key,
-	input			RD_n,
-	input			ps2_clk, 
-	input			ps2_data,
-	input			LINE_IN,
-	output [7:0]KDatout
-	);
-	
-	
-wire [2:0]KSsel = addr[2:0];		
-wire [2:0]KRsel = addr[5:3];
-wire [7:0]KS;
-wire [2:0]KR_bin;
-//wire KSout;
-wire [7:0]scan_code, scan_code_int;
-wire scan_ready, scan_ready_int;
-wire [2:0]row, col;
-wire set, clr;
-typedef reg [0:63] arr;
-arr key_array = 8'hFF;
-wire special, special_set, special_clr;
-typedef enum  {WAIT_CODE, RELEASE} STATES;
-STATES CState, NState = WAIT_CODE;
-wire kbd_rd;
-
-// Select keyboard row or select latch
-always @(KRsel, rd_key)
-	begin
-		if (rd_key == 1'b1) begin
-			case (KRsel)//spalte
-				3'b000 : KR_bin <= 3'b000;
-				3'b001 : KR_bin <= 3'b001;
-				3'b010 : KR_bin <= 3'b010;
-				3'b011 : KR_bin <= 3'b011;
-				3'b100 : KR_bin <= 3'b100;
-				3'b101 : KR_bin <= 3'b101;
-				3'b110 : KR_bin <= 3'b110;
-				3'b111 : KR_bin <= 3'b111;
-				default : KR_bin <= 3'b000;
-			endcase
-		end else
-			KR_bin <= 3'b000;
-	end
-	
-// Multiplex the keyboard scanlines
-always @(KSsel, rd_key, KS, RD_n)
-	begin
-		KDatout <= 8'b00000000;
-			case (KSsel)//reihe
-				3'b000 : KDatout[0] <= KS[0];
-				3'b001 : KDatout[1] <= KS[1];
-				3'b010 : KDatout[2] <= KS[2];
-				3'b011 : KDatout[3] <= KS[3];
-				3'b100 : KDatout[4] <= KS[4];
-				3'b101 : KDatout[5] <= KS[5];
-				3'b110 : KDatout[6] <= KS[6];
-				3'b111 : KDatout[7] <= KS[7];
-				default : KDatout <= 8'b11111111;
-			endcase
-	end
-	
-// scan_ready_int has asynchronous reset
-always @(scan_ready_int, clk) begin
-	if (clk == 1'b1) begin
-		scan_ready = scan_ready_int;
-		scan_code = scan_code_int;
-	end
-end
-
-// Galaksija keyboard array
-always @(KR_bin, row, col, set, clr, clk, LINE_IN, key_array) begin
-{row,col} = 6'b000000;
-	if (LINE_IN == 1'b1) begin
-		if (KR_bin == ~3'b000)
-			KS[0] = {3'b000,KR_bin};
-		else
-			KS[0] = 1'b1;
-	end else
-		KS[0] = 1'b0;
-		
-		KS[1] = {3'b001,KR_bin};
-		KS[2] = {3'b010,KR_bin};
-		KS[3] = {3'b011,KR_bin};
-		KS[4] = {3'b100,KR_bin};
-		KS[5] = {3'b101,KR_bin};
-		KS[6] = {3'b110,KR_bin};
-		KS[7] = {3'b111,KR_bin};
-			
-	if (clk == 1'b1) begin
-		if (set == 1'b1)
-			{row,col} = 6'b111111;
-			else if (clr == 1'b1) begin
-				{row,col} = 6'b000000;
-			end
-		end
-end
-
-// Bit for special characters
-always @(special_set, special_clr, clk) begin
-	if (clk == 1'b1) begin
-		if (special_clr == 1'b1)
-			special = 1'b0;
-		if (special_set == 1'b1)
-			special = 1'b1;
-	end
-end
-
-// Capture special codes
-always @(scan_code, scan_ready) begin
-	if (scan_ready == 1'b1) begin
-		if (scan_code == 8'hE0) 
-			special_set = 1'b1;
-		else
-			special_set = 1'b0;
-	end else
-		special_set = 1'b0;
-end
-
-// State machine state propagation
-always @(clk, NState, reset_n) begin
-	if (reset_n == 1'b0)
-		CState = WAIT_CODE;
-	else
-		if (clk == 1'b1)
-			CState = NState;
-end
-
-// State machine
-always @(CState, scan_code, scan_ready) begin
-	case (CState)
-		WAIT_CODE : begin
-							set = 1'b0;
-							special_clr = 1'b0;
-							if (scan_ready == 1'b1) begin
-								kbd_rd <= 1'b1;
-								if (scan_code == 8'hF0) begin
-									NState = RELEASE;
-									clr = 1'b0;
-								end else begin
-									NState = WAIT_CODE;
-									clr = 1'b1;
-								end
-							end else begin
-								kbd_rd = 1'b0;
-								clr = 1'b0;
-								NState = WAIT_CODE;
-							end
-						end
-		RELEASE : 	begin
-							clr = 1'b0;
-							if (scan_ready == 1'b1) begin
-								kbd_rd = 1'b1;
-								set = 1'b1;
-								NState = WAIT_CODE;
-								special_clr = 1'b1;
-							end else begin
-								kbd_rd = 1'b0;
-								set = 1'b0;
-								NState = RELEASE;
-								special_clr = 1'b0;
-							end
-						end
-	endcase
-end
-
-always @(special, scan_code) begin
-	if (special == 1'b0)
-		case (scan_code)
-			8'h1C : begin row = "001"; row = "000"; end// A
-			8'h32 : begin row = "010"; row = "000"; end// B
-			8'h21 : begin row = "011"; row = "000"; end// C
-			8'h23 : begin row = "100"; row = "000"; end// D
-			8'h24 : begin row = "101"; row = "000"; end// E
-			8'h2B : begin row = "110"; row = "000"; end// F
-			8'h34 : begin row = "111"; row = "000"; end// G
-			
-			8'h33 : begin row = "000"; row = "001"; end// H
-			8'h43 : begin row = "001"; row = "001"; end// I
-			8'h3B : begin row = "010"; row = "001"; end// J
-			8'h42 : begin row = "011"; row = "001"; end// K 
-			8'h4B : begin row = "100"; row = "001"; end// L
-			8'h3A : begin row = "101"; row = "001"; end// M
-			8'h31 : begin row = "110"; row = "001"; end// N
-			8'h44 : begin row = "111"; row = "001"; end// O
-				
-			8'h4D : begin row = "000"; row = "010"; end// P
-			8'h15 : begin row = "001"; row = "010"; end// Q
-			8'h2D : begin row = "010"; row = "010"; end// R
-			8'h1B : begin row = "011"; row = "010"; end// S
-			8'h2C : begin row = "100"; row = "010"; end// T
-			8'h3C : begin row = "101"; row = "010"; end// U
-			8'h2A : begin row = "110"; row = "010"; end// V
-			8'h1D : begin row = "111"; row = "010"; end// W
-				
-			8'h22 : begin row = "000"; row = "011"; end// X
-			8'h35 : begin row = "001"; row = "011"; end// Y
-			8'h1A : begin row = "010"; row = "011"; end// Z					
-			8'h29 : begin row = "111"; row = "011"; end// SPACE
-				
-			8'h45 : begin row = "000"; row = "100"; end// 0
-			8'h16 : begin row = "001"; row = "100"; end// 1
-			8'h1E : begin row = "010"; row = "100"; end// 2
-			8'h26 : begin row = "011"; row = "100"; end// 3
-			8'h25 : begin row = "100"; row = "100"; end// 4
-			8'h2E : begin row = "101"; row = "100"; end// 5
-			8'h36 : begin row = "110"; row = "100"; end// 6
-			8'h3D : begin row = "111"; row = "100"; end// 7
-				
-
-			8'h3E : begin row = "000"; row = "101"; end// 8
-			8'h46 : begin row = "001"; row = "101"; end// 9
-			8'h4C : begin row = "010"; row = "101"; end// ;
-			8'h54 : begin row = "011"; row = "101"; end// : (PS2 equ = [)
-			8'h41 : begin row = "100"; row = "101"; end// ,
-			8'h55 : begin row = "101"; row = "101"; end// =				
-			8'h71 : begin row = "110"; row = "101"; end// .
-			8'h49 : begin row = "110"; row = "101"; end// .
-			8'h4A : begin row = "111"; row = "101"; end// /			
-	
-			8'h5A : begin row = "000"; row = "110"; end// ret					
-			8'h12 : begin row = "101"; row = "110"; end// shift (left)
-			8'h59 : begin row = "101"; row = "110"; end// shift (right)					
-			default : begin row = "111"; col = "111"; end
-		endcase
-	else
-		case (scan_code)
-			8'h75 : begin row = "011"; row = "011"; end// UP
-			8'h72 : begin row = "100"; row = "011"; end// DOWN
-			8'h6B : begin row = "101"; row = "011"; end// LEFT
-			8'h74 : begin row = "110"; row = "011"; end// RIGHT
-			
-			8'h4A : begin row = "111"; row = "101"; end// /			
-
-			8'h69 : begin row = "001"; row = "110"; end// brk = end
-			8'h6C : begin row = "010"; row = "110"; end// rpt = home
-			8'h71 : begin row = "011"; row = "110"; end// del
-			8'h7D : begin row = "100"; row = "110"; end// lst = page up
-			default : begin row = "111"; col = "111"; end
-		endcase
-end
-
-keyboard keyboard(	
-	.keyboard_clk(ps2_clk), 
-	.keyboard_data(ps2_data), 
-	.clock(clk), 
-	.reset(reset_n), 
-	.reads(kbd_rd), 
-	.scan_code(scan_code_int), 
-	.scan_ready(scan_ready_int)
-	);
-
-endmodule 
\ No newline at end of file
diff --git a/Computer_MiST/Galaksija_MiST/rtl/galaksija_top.sv b/Computer_MiST/Galaksija_MiST/rtl/galaksija_top.sv
index a7510744..6548a6c3 100644
--- a/Computer_MiST/Galaksija_MiST/rtl/galaksija_top.sv
+++ b/Computer_MiST/Galaksija_MiST/rtl/galaksija_top.sv
@@ -3,7 +3,9 @@ module galaksija_top(
 	 input cpuclk,
 	 input audclk,
     input reset_in,
-	 input [10:0] ps2_key,
+	 input [7:0] key_code,
+	 input key_strobe,
+	 input key_pressed,
     input ps2_clk,
     input ps2_data,
 	 output [7:0] audio,
@@ -256,27 +258,16 @@ galaksija_video(
 	
 wire [7:0]key_out;
 wire rd_key;
-galaksija_keyboard1 galaksija_keyboard1(
+galaksija_keyboard galaksija_keyboard(
 	.clk(vidclk),
 	.addr(addr[5:0]),
 	.reset(~reset_in),
-	.ps2_key(ps2_key),
+   .key_code(key_code),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
 	.key_out(key_out),
 	.rd_key(rd_key)
 	);
-/*	
-galaksija_keyboard2 galaksija_keyboard2(
-	.clk(vidclk),
-	.reset_n(reset_in),
-	.addr(addr[5:0]),
-	.rd_key(rd_key),
-	.RD_n(rd_n),
-	.ps2_clk(ps2_clk), 
-	.ps2_data(ps2_data),
-	.LINE_IN(1'b0),
-	.KDatout(key_out)
-	);*/
-
 
 wire PIN_A = (1'b1 & 1'b1 & wr_n);
 wire [7:0]chan_A, chan_B, chan_C;
@@ -297,7 +288,7 @@ AY8912 AY8912(
    .CHANNEL_A(chan_A),
    .CHANNEL_B(chan_B),
    .CHANNEL_C(chan_C),
-   .SEL(1'b1),//divider?
+   .SEL(1'b1),//
 	.IO_in(),//not used
 	.IO_out()//not used
 	);
diff --git a/Computer_MiST/Galaksija_MiST/rtl/hq2x.sv b/Computer_MiST/Galaksija_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Computer_MiST/Galaksija_MiST/rtl/hq2x.sv
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Computer_MiST/Galaksija_MiST/rtl/keyboard.vhd b/Computer_MiST/Galaksija_MiST/rtl/keyboard.vhd
deleted file mode 100644
index 406ff79e..00000000
--- a/Computer_MiST/Galaksija_MiST/rtl/keyboard.vhd
+++ /dev/null
@@ -1,81 +0,0 @@
---
--- PS2 keyboard
---
-
-LIBRARY IEEE;
-USE  IEEE.STD_LOGIC_1164.all;
-USE  IEEE.STD_LOGIC_ARITH.all;
-USE  IEEE.STD_LOGIC_UNSIGNED.all;
- 
-ENTITY keyboard IS
-	PORT(	keyboard_clk, keyboard_data, clock , 
-			reset, reads		: IN	STD_LOGIC;
-			scan_code		: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
-			scan_ready		: OUT	STD_LOGIC);
-END keyboard;
-
-ARCHITECTURE rtl OF keyboard IS
-	SIGNAL INCNT					: std_logic_vector(3 downto 0);
-	SIGNAL SHIFTIN 					: std_logic_vector(8 downto 0);
-	SIGNAL READ_CHAR, clock_enable 	: std_logic;
-	SIGNAL ready_set		: std_logic;
-	SIGNAL keyboard_clk_filtered 	: std_logic;
-	SIGNAL filter 					: std_logic_vector(7 downto 0);
-BEGIN
-
-	PROCESS (reads, ready_set)
-	BEGIN
-	  IF reads = '1' THEN scan_ready <= '0';
-	  ELSIF ready_set'EVENT and ready_set = '1' THEN
-			scan_ready <= '1';
-	  END IF;
-	END PROCESS;
-
-	--This process filters the raw clock signal coming from the keyboard using a shift register and two AND gates
-	Clock_filter: PROCESS
-	BEGIN
-		WAIT UNTIL clock'EVENT AND clock= '1';
-		clock_enable <= NOT clock_enable;
-		IF clock_enable = '1' THEN
-			filter (6 DOWNTO 0) <= filter(7 DOWNTO 1) ;
-			filter(7) <= keyboard_clk;
-			IF filter = "11111111" THEN keyboard_clk_filtered <= '1';
-			ELSIF  filter= "00000000" THEN keyboard_clk_filtered <= '0';
-			END IF;
-	  	END IF;
-	END PROCESS Clock_filter;
-
-
-	--This process reads in serial data coming from the terminal
-	PROCESS
-	BEGIN
-	WAIT UNTIL (KEYBOARD_CLK_filtered'EVENT AND KEYBOARD_CLK_filtered='1');
-	IF RESET='0' THEN
-		     INCNT <= "0000";
-		     READ_CHAR <= '0';
-		     ready_set<= '0';
-	ELSE
-	  IF KEYBOARD_DATA='0' AND READ_CHAR='0' THEN
-		     READ_CHAR<= '1';
-			ready_set<= '0';
-	  ELSE
-				-- Shift in next 8 data bits to assemble a scan code
-		 IF READ_CHAR = '1' THEN
-		     IF INCNT < "1001" THEN
-		      	INCNT 				<= INCNT + 1;
-		      	SHIFTIN(7 DOWNTO 0) <= SHIFTIN(8 DOWNTO 1);
-		      	SHIFTIN(8) 			<= KEYBOARD_DATA;
-				-- End of scan code character, so set flags and exit loop
-		     ELSE
-		 	   	scan_code 			<= SHIFTIN(7 DOWNTO 0);
-					READ_CHAR			<= '0';
-			 	ready_set 			<= '1';
-			 	INCNT 				<= "0000";
-		     END IF;
-		  END IF;
-		END IF;
-	 END IF;
-	END PROCESS;
-END rtl;
-
-
diff --git a/Computer_MiST/Galaksija_MiST/rtl/mist_io.v b/Computer_MiST/Galaksija_MiST/rtl/mist_io.v
deleted file mode 100644
index 1cfcb753..00000000
--- a/Computer_MiST/Galaksija_MiST/rtl/mist_io.v
+++ /dev/null
@@ -1,496 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg  [7:0] joystick_0,
-	output reg  [7:0] joystick_1,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoubler_disable,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	input             ioctl_wait,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [13:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoubler_disable = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						 end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						 end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [13:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-//				addr <= ioctl_index ? 14'd9 : 14'd0; //.p files loaded at $4009, ROM is at 0
-				addr <= 14'd0;
-				ioctl_download <= 1; 
-			end else begin
-				ioctl_addr <= addr;
-				ioctl_download <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			ioctl_addr <= addr;
-			ioctl_dout <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			ioctl_wr <= 1;
-		end else
-			ioctl_wr <= 0;
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-endmodule
diff --git a/Computer_MiST/Galaksija_MiST/rtl/osd.v b/Computer_MiST/Galaksija_MiST/rtl/osd.v
deleted file mode 100644
index c62c10af..00000000
--- a/Computer_MiST/Galaksija_MiST/rtl/osd.v
+++ /dev/null
@@ -1,179 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-	
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-      
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350); 
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin	
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin	
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin	
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin	
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start + 1'd1;  // one pixel offset for osd_byte register
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-
-wire osd_de = osd_enable && 
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg  [7:0] osd_byte; 
-always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
-
-wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Computer_MiST/Galaksija_MiST/rtl/scandoubler.v b/Computer_MiST/Galaksija_MiST/rtl/scandoubler.v
deleted file mode 100644
index e85cba43..00000000
--- a/Computer_MiST/Galaksija_MiST/rtl/scandoubler.v
+++ /dev/null
@@ -1,183 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Computer_MiST/Galaksija_MiST/rtl/video_mixer.sv b/Computer_MiST/Galaksija_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 04cfd4ba..00000000
--- a/Computer_MiST/Galaksija_MiST/rtl/video_mixer.sv
+++ /dev/null
@@ -1,242 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 768,
-	parameter HALF_DEPTH   = 0,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoubler_disable,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoubler_disable ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoubler_disable ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoubler_disable ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoubler_disable ? HSync : hs_sd);
-wire       vs = (scandoubler_disable ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Computer_MiST/Laser310_MiST/Laser310_MiST.qpf b/Computer_MiST/Laser310_MiST/Laser310_MiST.qpf
new file mode 100644
index 00000000..6e4b53bc
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/Laser310_MiST.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 12:11:46  March 17, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "12:11:46  March 17, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "Laser310_MiST"
diff --git a/Computer_MiST/Laser310_MiST/Laser310_MiST.qsf b/Computer_MiST/Laser310_MiST/Laser310_MiST.qsf
new file mode 100644
index 00000000..b827f781
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/Laser310_MiST.qsf
@@ -0,0 +1,433 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 17:28:40  June 04, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Laser310_MiST_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24  MAY 17, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Laser310_MiST.sv
+set_global_assignment -name VERILOG_FILE rtl/LASER310_TOP.v
+set_global_assignment -name VERILOG_FILE rtl/mc6847_vga.v
+set_global_assignment -name VERILOG_FILE rtl/PIXEL_DISPLAY.v
+set_global_assignment -name VERILOG_FILE rtl/CHAR_GEN.v
+set_global_assignment -name VERILOG_FILE rtl/PIXEL_GEN.v
+set_global_assignment -name VERILOG_FILE rtl/VIDEO_OUT.v
+set_global_assignment -name VERILOG_FILE rtl/SVGA_DEFINES.v
+set_global_assignment -name VERILOG_FILE rtl/SVGA_TIMING_GENERATION.v
+set_global_assignment -name VERILOG_FILE rtl/ps2_keyboard_glb.v
+set_global_assignment -name VERILOG_FILE rtl/tv80/tv80s.v
+set_global_assignment -name VERILOG_FILE rtl/tv80/tv80n.v
+set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_reg.v
+set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_mcode.v
+set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_core.v
+set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_alu.v
+set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_top.vhd
+set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_tone.vhd
+set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_noise.vhd
+set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_latch_ctrl.vhd
+set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_clock_div.vhd
+set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_attenuator.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VERILOG_FILE rtl/reset_de.v
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name TEXT_FILE rtl/tv80/Text1.txt
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/LaserKeyboard.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/LaserCassEmu.sv
+set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+set_location_assignment PLL_1 -to "pll27:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY Laser310_MiST
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# ---------------------------
+# start ENTITY(Laser310_MiST)
+
+	# Pin & Location Assignments
+	# ==========================
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
+
+	# Fitter Assignments
+	# ==================
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[0]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[1]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[2]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[3]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[4]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[5]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[6]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[7]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[8]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[9]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[10]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[11]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[12]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[0]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[1]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[2]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[3]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[4]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[5]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[6]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[7]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[8]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[9]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[10]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[11]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[12]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[13]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[14]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[15]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_BA[0]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_BA[1]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQML
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQMH
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nRAS
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nCAS
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nWE
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nCS
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_CKE
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_CLK
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[5]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[4]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[3]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[2]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[1]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[0]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[5]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[4]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[3]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[2]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[1]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[0]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[5]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[4]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[3]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[2]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[1]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[0]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_HS
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_VS
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to LED
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_L
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_DO
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to CONF_DATA0
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_L
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_R
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CONF_DATA0
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DI
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DO
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCK
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS2
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS3
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[8]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[9]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[10]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[11]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[12]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQMH
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQML
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nRAS
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nCAS
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nWE
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nCS
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to CLOCK_27
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_DI
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SCK
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SS2
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SS3
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(Laser310_MiST)
+# -------------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Computer_MiST/Laser310_MiST/Laser310_MiST.sdc b/Computer_MiST/Laser310_MiST/Laser310_MiST.sdc
new file mode 100644
index 00000000..3eba3b05
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/Laser310_MiST.sdc
@@ -0,0 +1,33 @@
+#************************************************************
+# THIS IS A WIZARD-GENERATED FILE.                           
+#
+# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
+#
+#************************************************************
+
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+# Clock constraints
+
+create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}]
+create_clock -name {SPI_SCK}  -period 10.000 -waveform { 0.000 0.500 } [get_ports {SPI_SCK}]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
diff --git a/Computer_MiST/Laser310_MiST/Laser310_MiST.srf b/Computer_MiST/Laser310_MiST/Laser310_MiST.srf
new file mode 100644
index 00000000..4eb6b36c
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/Laser310_MiST.srf
@@ -0,0 +1,11 @@
+{ "" "" "" "Verilog HDL warning at hq2x.sv(247): extended using \"x\" or \"z\"" {  } {  } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL warning at tv80_core.v(300): extended using \"x\" or \"z\"" {  } {  } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL macro warning at hq2x.sv(26): overriding existing definition for macro \"BITS_TO_FIT\", which was defined in \"rtl/scandoubler.v\", line 109" {  } {  } 0 10274 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10090 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 332060 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10259 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10030 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Computer_MiST/Laser310_MiST/Snapshot/Laser310_MiST.rbf b/Computer_MiST/Laser310_MiST/Snapshot/Laser310_MiST.rbf
new file mode 100644
index 00000000..519d8dab
Binary files /dev/null and b/Computer_MiST/Laser310_MiST/Snapshot/Laser310_MiST.rbf differ
diff --git a/Computer_MiST/Laser310_MiST/clean.bat b/Computer_MiST/Laser310_MiST/clean.bat
new file mode 100644
index 00000000..83fb0c47
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/clean.bat
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Computer_MiST/Laser310_MiST/compumuse.pdf b/Computer_MiST/Laser310_MiST/compumuse.pdf
new file mode 100644
index 00000000..98e067ee
Binary files /dev/null and b/Computer_MiST/Laser310_MiST/compumuse.pdf differ
diff --git a/Computer_MiST/Laser310_MiST/rtl/CHAR_GEN.v b/Computer_MiST/Laser310_MiST/rtl/CHAR_GEN.v
new file mode 100644
index 00000000..a9d45ce9
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/CHAR_GEN.v
@@ -0,0 +1,68 @@
+module CHAR_GEN(
+	// control
+	reset,
+
+	char_code,
+	subchar_line,
+	subchar_pixel,
+
+	pixel_clock,
+	pixel_on
+);
+
+input			pixel_clock;
+input			reset;
+
+input	[7:0]	char_code;
+input	[4:0]	subchar_line;			// line number within 12 line block
+input	[3:0]	subchar_pixel;			// pixel position within 8 pixel block
+
+output			pixel_on;
+
+reg		[7:0]	latched_data;
+reg				pixel_on;
+
+wire	[11:0]	rom_addr = {char_code[7:0], subchar_line[4:1]};
+wire	[7:0]	rom_data;
+ 
+
+// instantiate the character generator ROM
+//CHAR_GEN_ROM CHAR_GEN_ROM
+//(
+//	pixel_clock,
+//	rom_addr,
+//	rom_data
+//);
+
+sprom #(
+	.init_file("./roms/charrom_4k.mif"),
+	.widthad_a(12),
+	.width_a(8))
+CHAR_GEN_ROM(
+	.address(rom_addr),
+	.clock(pixel_clock),
+	.q(rom_data)
+	);
+
+
+// serialize the CHARACTER MODE data
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+ 		begin
+			pixel_on = 1'b0;
+			latched_data  = 8'h00;
+		end
+
+	else begin
+		case(subchar_pixel)
+			4'b0101:
+				latched_data [7:0] = {rom_data[0],rom_data[1],rom_data[2],rom_data[3],rom_data[4],rom_data[5],rom_data[6],rom_data[7]};
+			default:
+			if(subchar_pixel[0]==1'b0)
+				{pixel_on,latched_data [7:1]} <= latched_data [7:0];
+		endcase
+		end
+
+	end
+
+endmodule //CHAR_GEN
diff --git a/Computer_MiST/Laser310_MiST/rtl/CHAR_GEN_ROM.v b/Computer_MiST/Laser310_MiST/rtl/CHAR_GEN_ROM.v
new file mode 100644
index 00000000..691de90e
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/CHAR_GEN_ROM.v
@@ -0,0 +1,19 @@
+module CHAR_GEN_ROM
+(
+	pixel_clock,
+	address,
+	data
+);
+
+input				pixel_clock;
+input		[11:0]	address;
+output wire [7:0] 	data;
+
+// Character generator
+char_rom_4k_altera char_rom(
+	.address(address),
+	.clock(pixel_clock),
+	.q(data)
+);
+
+endmodule //CHAR_GEN_ROM
diff --git a/Computer_MiST/Laser310_MiST/rtl/LASER310_TOP.v b/Computer_MiST/Laser310_MiST/rtl/LASER310_TOP.v
new file mode 100644
index 00000000..26bd3a52
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/LASER310_TOP.v
@@ -0,0 +1,1100 @@
+`timescale 1 ns / 1 ns
+`define BASE_SYS_ROM
+`define BASE_DOS_ROM
+`define BOOT_ROM_6000
+`define BASE_RAM_78//2k
+`define BASE_RAM_16K
+//`define RAM_16K_EXPANSION
+`define VRAM_2K
+//`define VRAM_8K
+`define SHRG
+//`ifdef CASS_EMU
+//`ifdef CASS_EMU_16K
+//`ifdef CASS_EMU_8K
+//`ifdef CASS_EMU_4K
+//`ifdef CASS_EMU_2K
+
+//Switches
+//  9 Latch BANK_4000
+//  8 Latch BANK_4000
+//  7 Latch BANK_4000
+//  6 Latch BANK_0000
+//  5 Latch BANK_0000
+//  4 Latch BANK_0000
+//  3 
+//  2 SHRG_EN
+//  1 Dosrom Enable
+//  0 Turbo
+
+								
+module LASER310_TOP(
+input				CLK50MHZ,
+input				CLK25MHZ,
+input				CLK10MHZ,
+input				RESET,//Active Low
+output	[7:0]	VGA_RED,
+output	[7:0]	VGA_GREEN,
+output	[7:0]	VGA_BLUE,
+output			VGA_HS,
+output			VGA_VS,
+output			blank,
+input				VIDEO_MODE,
+output	[1:0]	AUD_ADCDAT,
+output	[7:0]	audio_s,
+input				key_strobe,
+input				key_pressed,
+input		[7:0]	key_code,
+//input 			PS2_KBCLK,
+//input				PS2_KBDAT,
+input		[9:0]	SWITCH,
+input				UART_RXD,
+output			UART_TXD
+);
+
+reg		[3:0]		CLK;
+
+reg					MEM_OP_WR;
+//reg					MEM_RD;
+(*keep*)reg				GPIO_CPU_CLK;
+// Processor
+(*keep*)reg				CPU_CLK;
+(*keep*)wire	[15:0]	CPU_A;
+(*keep*)wire	[7:0]	CPU_DI;
+(*keep*)wire	[7:0]	CPU_DO;
+(*keep*)wire			CPU_RESET;
+(*keep*)wire			CPU_HALT;
+
+(*keep*)wire			CPU_MREQ;
+(*keep*)wire			CPU_RD;
+(*keep*)wire			CPU_WR;
+(*keep*)wire			CPU_IORQ;
+(*keep*)reg				CPU_INT;
+
+(*keep*)wire			CPU_M1;
+wire					CPU_BUSRQ;
+wire					CPU_BUSAK;
+wire					CPU_RFSH;
+
+(*keep*)wire			CPU_RESET_N;
+(*keep*)wire			CPU_HALT_N;
+
+(*keep*)wire			CPU_MREQ_N;
+(*keep*)wire			CPU_RD_N;
+(*keep*)wire			CPU_WR_N;
+(*keep*)wire			CPU_IORQ_N;
+(*keep*)wire			CPU_INT_N;
+
+(*keep*)wire			CPU_M1_N;
+wire					CPU_BUSRQ_N;
+wire					CPU_BUSAK_N;
+wire					CPU_RFSH_N;
+// VRAM
+(*keep*)wire	[12:0]	VRAM_ADDRESS;
+(*keep*)wire			VRAM_WR;
+(*keep*)wire	[7:0]	VRAM_DATA_OUT;
+
+(*keep*)wire			VDG_RD;
+(*keep*)wire	[12:0]	VDG_ADDRESS;
+(*keep*)wire	[7:0]	VDG_DATA;
+
+// ROM IO RAM
+reg					LATCHED_DOSROM_EN;
+reg					LATCHED_BOOTROM_EN;
+reg					LATCHED_AUTOSTARTROM_EN;
+wire	[7:0]		SYS_ROM_DATA;
+wire	[7:0]		DOS_ROM_DATA;
+wire	[7:0]		AUTOSTART_ROM_DATA;
+wire	[7:0]		BOOT_ROM_6000_DATA;
+reg					BOOTROM_EN;
+reg		[7:0]		BOOTROM_BANK;
+reg					AUTOSTARTROM_EN;
+reg		[7:0]		AUTOSTARTROM_BANK;
+//wire	[7:0]		IO_DATA;
+//wire	[7:0]		IO_WR;
+wire				RAM_16K_WR;
+wire	[7:0]		RAM_16K_DATA_OUT;
+wire				RAM_78_WR;
+wire	[7:0]		RAM_78_DATA;
+wire				RAM_16K_EXP_WR;
+wire	[7:0]		RAM_16K_EXP_DATA_OUT;
+wire				RAM_89AB_WR;
+wire	[7:0]		RAM_89AB_DATA;
+wire				RAM_CDEF_WR;
+wire	[7:0]		RAM_CDEF_DATA;
+wire	[7:0]		MEM_CDEF_DATA_OUT;
+wire	[7:0]		RAM_89AB_DATA_OUT;
+wire	[7:0]		RAM_CDEF_DATA_OUT;
+wire				ADDRESS_ROM;
+wire				ADDRESS_DOSROM;
+wire				ADDRESS_IO;
+wire				ADDRESS_VRAM;
+wire				ADDRESS_BOOTROM_6000;
+wire				ADDRESS_AUTOSTARTROM;
+wire				ADDRESS_89AB;
+wire				ADDRESS_CDEF;
+wire				ADDRESS_RAM_78;
+wire				ADDRESS_RAM_16K;
+wire				ADDRESS_RAM_16K_EXP;
+wire				ADDRESS_IO_SHRG;
+wire				ADDRESS_IO_BANK;
+wire				ADDRESS_RAM_CHIP;
+reg		[7:0]		LATCHED_IO_DATA_WR;
+//reg	[7:0]		LATCHED_IO_DATA_RD;
+reg		[7:0]		LATCHED_BANK_0000;
+reg		[7:0]		LATCHED_BANK_4000;
+reg		[7:0]		LATCHED_BANK_C000;
+reg		[7:0]		LATCHED_BANK_4DEF;
+`ifdef SHRG
+reg					LATCHED_SHRG_EN;
+reg		[7:0]		LATCHED_IO_SHRG;
+`endif
+
+// keyboard
+reg		[4:0]		KB_CLK;
+
+wire	[7:0]		SCAN;
+wire				PRESS;
+wire				PRESS_N;
+wire				EXTENDED;
+
+reg		[63:0]		KEY;
+reg		[9:0]		KEY_EX;
+reg		[11:0]		KEY_Fxx;
+wire	[7:0]		KEY_DATA;
+//reg	[63:0]		LAST_KEY;
+//reg				CAPS_CLK;
+//reg				CAPS;
+wire				A_KEY_PRESSED;
+
+reg		[7:0]		LATCHED_KEY_DATA;
+
+// emu keyboard
+wire	[63:0]		EMU_KEY;
+wire	[9:0]		EMU_KEY_EX;
+wire				EMU_KEY_EN;
+// cassette
+
+(*keep*)wire	[1:0]	CASS_OUT;
+(*keep*)wire			CASS_IN;
+(*keep*)wire			CASS_IN_L;
+(*keep*)wire			CASS_IN_R;
+
+
+// 用于外部磁带仿真计数
+//(*keep*)reg				EMU_CASS_CLK;
+
+(*keep*)wire			EMU_CASS_EN;
+(*keep*)wire	[1:0]	EMU_CASS_DAT;
+
+
+reg		[16:0]		RESET_KEY_COUNT;
+wire				RESET_KEY_N, RESET_N;
+
+wire				TURBO_SPEED		=	SWITCH[0];
+
+
+RESET_DE RESET_DE(
+	.CLK(CLK50MHZ),
+	.SYS_RESET_N(RESET),
+	.RESET_N(RESET_N)
+);
+
+
+// 键盘 ctrl + f12 系统复位
+assign RESET_KEY_N = RESET_KEY_COUNT[16];
+
+reg 		[17:0]	INT_CNT;
+
+always @ (negedge CLK10MHZ)
+	case(INT_CNT[17:0])
+		18'd0:
+		begin
+			CPU_INT <= 1'b1;
+			INT_CNT <= 18'd1;
+		end
+		18'd640:
+		begin
+			CPU_INT <= 1'b0;
+			INT_CNT <= 18'd641;
+		end
+		18'd199999:
+		begin
+			INT_CNT <= 18'd0;
+		end
+		default:
+		begin
+			INT_CNT <= INT_CNT + 1;
+		end
+	endcase
+
+always @(posedge CLK50MHZ or negedge RESET_N)
+	if(~RESET_N)
+	begin
+		CPU_CLK					<=	1'b0;
+		GPIO_CPU_CLK			<=	1'b0;
+		// 复位期间设置，避免拨动开关引起错误
+		LATCHED_DOSROM_EN		<=	SWITCH[1];
+		LATCHED_BANK_0000		<=	{5'b0,SWITCH[6:4]};
+		LATCHED_BANK_4000		<=	{5'b0,SWITCH[9:7]};
+		LATCHED_BOOTROM_EN		<=	BOOTROM_EN;
+		LATCHED_AUTOSTARTROM_EN	<=	AUTOSTARTROM_EN;
+		//LATCHED_BOOTROM_EN		<=	1'b0;
+`ifdef SHRG
+		LATCHED_IO_SHRG			<=	8'b00001000;
+		// 复位期间设置，避免拨动开关引起错误
+		LATCHED_SHRG_EN			<=	SWITCH[2];
+`endif
+`ifdef IO_BANK
+		if(BOOTROM_EN)
+			LATCHED_BANK_C000		<=	BOOTROM_BANK;
+		else
+			LATCHED_BANK_C000		<=	8'b0;
+		if(AUTOSTARTROM_EN)
+			LATCHED_BANK_4DEF		<=	AUTOSTARTROM_BANK;
+		else
+			LATCHED_BANK_4DEF		<=	8'b0;
+`endif
+
+
+		MEM_OP_WR				<=	1'b0;
+
+		LATCHED_KEY_DATA		<=	8'b0;
+		LATCHED_IO_DATA_WR		<=	8'b0;
+		//EMU_CASS_CLK <= 1'b0;
+		CLK						<=	4'd0;
+	end
+	else
+	begin
+		case (CLK[3:0])
+		4'd0:
+			begin
+				// 同步内存，等待读写信号建立
+				CPU_CLK				<=	1'b1;
+				GPIO_CPU_CLK		<=	1'b1;
+				MEM_OP_WR			<=	1'b1;
+				//EMU_CASS_CLK <= ~EMU_CASS_CLK;
+				CLK					<=	4'd1;
+			end
+
+		4'd1:
+			begin
+				// 同步内存，锁存读写信号和地址
+				CPU_CLK				<=	1'b0;
+				MEM_OP_WR			<=	1'b0;
+				LATCHED_KEY_DATA	<=	KEY_DATA;
+				if({CPU_MREQ,CPU_RD,CPU_WR,ADDRESS_IO}==4'b1011)
+					LATCHED_IO_DATA_WR	<=	CPU_DO;
+`ifdef SHRG
+				if(LATCHED_SHRG_EN)
+					if({CPU_IORQ,CPU_RD,CPU_WR,ADDRESS_IO_SHRG}==4'b1011)
+						LATCHED_IO_SHRG		<=	CPU_DO;
+`endif
+`ifdef IO_BANK
+				if({CPU_IORQ,CPU_RD,CPU_WR,ADDRESS_IO_BANK}==4'b1011)
+					LATCHED_BANK_C000	<=	CPU_DO;
+`endif
+				CLK					<=	4'd2;
+			end
+
+		4'd2:
+			begin
+				// 完成读写操作，开始输出
+				CPU_CLK				<=	1'b0;
+				GPIO_CPU_CLK		<=	~TURBO_SPEED;
+
+				MEM_OP_WR			<=	1'b0;
+				CLK					<=	4'd3;
+			end
+		4'd3:
+			begin
+				if(TURBO_SPEED)
+					CLK				<=	4'd0;
+				else
+					CLK				<=	4'd4;
+			end
+		4'd7:
+			begin
+				CPU_CLK				<=	1'b0;
+				GPIO_CPU_CLK		<=	1'b0;
+				MEM_OP_WR			<=	1'b0;
+				CLK					<=	4'd8;
+			end
+		4'd13:// 正常速度
+			begin
+				CPU_CLK				<=	1'b0;
+				MEM_OP_WR			<=	1'b0;
+				CLK					<=	4'd0;
+			end
+		default:
+			begin
+				CPU_CLK				<=	1'b0;
+				MEM_OP_WR			<=	1'b0;
+				CLK					<=	CLK + 1'b1;
+			end
+		endcase
+	end
+
+// CPU
+assign CPU_RESET = ~RESET_N;
+assign CPU_M1 = ~CPU_M1_N;
+assign CPU_MREQ = ~CPU_MREQ_N;
+assign CPU_IORQ = ~CPU_IORQ_N;
+assign CPU_RD = ~CPU_RD_N;
+assign CPU_WR = ~CPU_WR_N;
+assign CPU_RFSH = ~CPU_RFSH_N;
+assign CPU_HALT= ~CPU_HALT_N;
+assign CPU_BUSAK = ~CPU_BUSAK_N;
+assign CPU_RESET_N = ~CPU_RESET;
+assign CPU_INT_N = VIDEO_MODE ? ~CPU_INT : ~VGA_VS;
+assign CPU_BUSRQ_N = ~CPU_BUSRQ;
+
+tv80s Z80CPU (
+	.m1_n(CPU_M1_N),
+	.mreq_n(CPU_MREQ_N),
+	.iorq_n(CPU_IORQ_N),
+	.rd_n(CPU_RD_N),
+	.wr_n(CPU_WR_N),
+	.rfsh_n(CPU_RFSH_N),
+	.halt_n(CPU_HALT_N),
+	.busak_n(CPU_BUSAK_N),
+	.A(CPU_A),
+	.dout(CPU_DO),
+	.reset_n(CPU_RESET_N),
+	.clk(CPU_CLK),
+	.wait_n(1'b1),
+	.int_n(CPU_INT_N),
+	.nmi_n(1'b1),
+	.busrq_n(CPU_BUSRQ_N),
+	.di(CPU_DI)
+);
+
+
+// 0000 -- 3FFF ROM 16KB
+// 4000 -- 5FFF DOS
+// 6000 -- 67FF BOOT ROM
+// 6800 -- 6FFF I/O
+// 7000 -- 77FF VRAM 2KB (SRAM 6116)
+// 7800 -- 7FFF RAM 2KB
+// 8000 -- B7FF RAM 14KB
+// B800 -- BFFF RAM ext 2KB
+// C000 -- F7FF RAM ext 14KB
+
+assign ADDRESS_ROM				=	(CPU_A[15:14] == 2'b00)?1'b1:1'b0;
+assign ADDRESS_DOSROM			=	(CPU_A[15:13] == 3'b010)?LATCHED_DOSROM_EN:1'b0;
+assign ADDRESS_BOOTROM_6000		=	(CPU_A[15:11] == 5'b01100)?LATCHED_BOOTROM_EN:1'b0;
+assign ADDRESS_AUTOSTARTROM		=	(CPU_A[15:12] == 4'h4||CPU_A[15:12] == 4'hD||CPU_A[15:12] == 4'hE||CPU_A[15:12] == 4'hF)?LATCHED_AUTOSTARTROM_EN:1'b0;
+assign ADDRESS_IO				=	(CPU_A[15:11] == 5'b01101)?1'b1:1'b0;
+assign ADDRESS_VRAM				=	(CPU_A[15:11] == 5'b01110)?1'b1:1'b0;
+assign ADDRESS_89AB				=	(CPU_A[15:14] == 2'b10)?1'b1:1'b0;
+assign ADDRESS_CDEF				=	(CPU_A[15:14] == 2'b11)?1'b1:1'b0;
+// 7800 -- 7FFF RAM 2KB
+assign ADDRESS_RAM_78			=	(CPU_A[15:11] == 5'b01111)?1'b1:1'b0;
+// 7800 -- 7FFF RAM 2KB
+// 8000 -- B7FF RAM 14KB
+
+assign ADDRESS_RAM_16K		=	(CPU_A[15:12] == 4'h8)?1'b1:
+								(CPU_A[15:12] == 4'h9)?1'b1:
+								(CPU_A[15:12] == 4'hA)?1'b1:
+								(CPU_A[15:11] == 5'b01111)?1'b1:
+								(CPU_A[15:11] == 5'b10110)?1'b1:
+								1'b0;
+
+// B800 -- BFFF RAM ext 2KB
+// C000 -- F7FF RAM ext 14KB
+
+assign ADDRESS_RAM_16K_EXP	=	(CPU_A[15:12] == 4'hC)?1'b1:
+								(CPU_A[15:12] == 4'hD)?1'b1:
+								(CPU_A[15:12] == 4'hE)?1'b1:
+								(CPU_A[15:11] == 5'b10111)?1'b1:
+								(CPU_A[15:11] == 5'b11110)?1'b1:
+								1'b0;
+
+assign ADDRESS_IO_SHRG		=	(CPU_A[7:0] == 8'd32)?1'b1:1'b0;
+
+// 64K RAM expansion cartridge vz300_review.pdf 中的端口号是 IO 7FH 127
+// 128K SIDEWAYS RAM SHRG2 HVVZUG23 (Mar-Apr 1989).PDF 中的端口号是 IO 112
+
+assign ADDRESS_IO_BANK	=	(CPU_A[7:0] == 8'd127 || CPU_A[7:0] == 8'd112)?1'b1:1'b0;
+
+
+
+
+`ifdef RAM_16K_EXPANSION
+assign	ADDRESS_RAM_CHIP	=	ADDRESS_RAM_16K|ADDRESS_RAM_16K_EXP;
+`else
+assign	ADDRESS_RAM_CHIP	=	ADDRESS_RAM_16K;
+`endif
+
+
+
+assign VRAM_WR			= ({ADDRESS_VRAM,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
+assign RAM_78_WR		= ({ADDRESS_RAM_78,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
+assign RAM_16K_WR		= ({ADDRESS_RAM_16K,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
+assign RAM_16K_EXP_WR	= ({ADDRESS_RAM_16K_EXP,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
+
+
+assign RAM_89AB_WR		= ({ADDRESS_89AB,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
+assign RAM_CDEF_WR		= ({ADDRESS_CDEF,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
+
+assign RAM_89AB_WR		= ({ADDRESS_89AB,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
+assign RAM_CDEF_WR		= ({ADDRESS_CDEF,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
+
+
+assign CPU_DI = 	ADDRESS_ROM				? SYS_ROM_DATA			:
+						ADDRESS_AUTOSTARTROM	? AUTOSTART_ROM_DATA	:
+						ADDRESS_DOSROM			? DOS_ROM_DATA			:
+`ifdef BOOT_ROM_6000
+						ADDRESS_BOOTROM_6000	? BOOT_ROM_6000_DATA	:
+`endif
+						ADDRESS_IO				? LATCHED_KEY_DATA		:
+						ADDRESS_VRAM			? VRAM_DATA_OUT			:
+`ifdef BASE_RAM_16K
+						ADDRESS_RAM_16K			? RAM_16K_DATA_OUT		:
+`endif
+`ifdef RAM_16K_EXPANSION
+						ADDRESS_RAM_16K_EXP		? RAM_16K_EXP_DATA_OUT	:
+`endif
+					8'hzz;
+
+
+
+
+`ifdef BASE_SYS_ROM
+sprom #(
+	.init_file("./roms/sysrom.mif"),
+	.widthad_a(14),
+	.width_a(8))
+sys_rom(
+	.address(CPU_A[13:0]),
+	.clock(CLK50MHZ),
+	.q(SYS_ROM_DATA)
+	);
+`endif
+
+`ifdef BASE_DOS_ROM
+sprom #(
+	.init_file("./roms/dosrom.mif"),
+	.widthad_a(13),
+	.width_a(8))
+DOS_ROM(
+	.address(CPU_A[12:0]),
+	.clock(CLK50MHZ),
+	.q(DOS_ROM_DATA)
+	);
+`endif
+
+`ifdef BOOT_ROM_6000
+sprom #(
+	.init_file("./roms/boot_rom_6000.mif"),
+	.widthad_a(9),
+	.width_a(8))
+BOOT_ROM(
+	.address(CPU_A[8:0]),
+	.clock(CLK50MHZ),
+	.q(BOOT_ROM_6000_DATA)
+	);
+`endif
+
+`ifdef BASE_RAM_78
+spram #(
+	. addr_width_g(11),
+	.data_width_g(8))
+BASE_RAM78(
+	.address(CPU_A[10:0]),
+	.clken(1),
+	.clock(CLK50MHZ),
+	.data(CPU_DO),
+	.wren(CPU_MREQ & RAM_78_WR),
+	.q(RAM_78_DATA)
+	);
+`endif
+
+`ifdef BASE_RAM_16K
+spram #(
+	. addr_width_g(14),
+	.data_width_g(8))
+BASE_RAM16k(
+	.address(CPU_A[13:0]),
+	.clken(1),
+	.clock(CLK50MHZ),
+	.data(CPU_DO),
+	.wren(CPU_MREQ & RAM_16K_WR),
+	.q(RAM_16K_DATA_OUT)
+	);
+`else
+assign	RAM_16K_DATA_OUT		=	8'bz;
+`endif
+
+`ifdef RAM_16K_EXPANSION
+spram #(
+	. addr_width_g(14),
+	.data_width_g(8))
+BASE_RAM16kex(
+	.address(CPU_A[13:0]),
+	.clken(1),
+	.clock(CLK50MHZ),
+	.data(CPU_DO),
+	.wren(CPU_MREQ & RAM_16K_EXP_WR),
+	.q(RAM_16K_EXP_DATA_OUT)
+	);
+`else
+assign	RAM_16K_EXP_DATA_OUT	=	8'bz;
+`endif
+
+
+`ifdef VRAM_2K
+dpram #(
+	.addr_width_g(11),
+	.data_width_g(8))
+vram_2k(
+	.clk_a_i(CLK50MHZ),
+	.en_a_i(1),
+	.we_i(CPU_MREQ & VRAM_WR),
+	.addr_a_i(CPU_A[10:0]),
+	.data_a_i(CPU_DO),
+	.data_a_o(VRAM_DATA_OUT),
+	.clk_b_i(VDG_RD),
+	.addr_b_i(VDG_ADDRESS[10:0]),
+	.data_b_o(VDG_DATA)
+	);
+`endif
+
+
+`ifdef VRAM_8K
+dpram #(
+	.addr_width_g(13),
+	.data_width_g(8))
+vram_8k(
+	.clk_a_i(CLK50MHZ),
+	.en_a_i(1),
+	.we_i(CPU_MREQ & VRAM_WR),
+	.addr_a_i({LATCHED_IO_SHRG[1:0],CPU_A[10:0]}),
+	.data_a_i(CPU_DO),
+	.data_a_o(VRAM_DATA_OUT),
+	.clk_b_i(VDG_RD),
+	.addr_b_i(VDG_ADDRESS[12:0]),
+	.data_b_o(VDG_DATA)
+	);
+`endif
+
+MC6847_VGA MC6847_VGA(
+	.PIX_CLK(CLK25MHZ),
+	.RESET_N(RESET_N),
+	.RD(VDG_RD),
+	.DD(VDG_DATA),
+	.DA(VDG_ADDRESS),
+	.AG(LATCHED_IO_DATA_WR[3]),
+	.AS(1'b0),
+	.EXT(1'b0),
+	.INV(1'b0),
+`ifdef SHRG
+	.GM(LATCHED_IO_SHRG[4:2]),
+`else
+	.GM(3'b010),
+`endif
+	.CSS(LATCHED_IO_DATA_WR[4]),
+	// vga
+	.blank(blank),
+	.VGA_OUT_HSYNC(VGA_HS),
+	.VGA_OUT_VSYNC(VGA_VS),
+	.VGA_OUT_RED(VGA_RED),
+	.VGA_OUT_GREEN(VGA_GREEN),
+	.VGA_OUT_BLUE(VGA_BLUE)
+);
+
+
+// keyboard
+
+/*****************************************************************************
+* Convert PS/2 keyboard to ASCII keyboard
+******************************************************************************/
+
+/*
+   KD5 KD4 KD3 KD2 KD1 KD0 扫描用地址
+A0  R   Q   E       W   T  68FEH       0
+A1  F   A   D  CTRL S   G  68FDH       8
+A2  V   Z   C  SHFT X   B  68FBH      16
+A3  4   1   3       2   5  68F7H      24
+A4  M  空格 ，      .   N  68EFH      32
+A5  7   0   8   -   9   6  68DFH      40
+A6  U   P   I  RETN O   Y  68BFH      48
+A7  J   ；  K   :   L   H  687FH      56
+*/
+
+//  7: 0
+// 15: 8
+// 23:16
+// 31:24
+// 39:32
+// 47:40
+// 55:48
+// 63:56
+
+
+
+// 键盘检测的方法，就是循环地问每一行线发送低电平信号，也就是用该地址线为“0”的地址去读取数据。
+// 例如，检测第一行时，使A0为0，其余为1；加上选通IC4的高五位地址01101，成为01101***11111110B（A8~A10不起作用，
+// 可为任意值，故68FEH，69FEH，6AFEH，6BFEH，6CFEH，6DFEH，6EFEH，6FFEH均可）。
+// 读 6800H 判断是否有按键按下。
+
+// The method of keyboard detection is to cyclically ask each line to send a low level signal, 
+// that is, to read the data with the address line "0".
+// For example, when detecting the first line, make A0 0 and the rest 1; plus the high five-bit address 01101 of the strobe IC4, 
+// become 01101***11111110B (A8~A10 does not work,
+// It can be any value, so 68FEH, 69FEH, 6AFEH, 6BFEH, 6CFEH, 6DFEH, 6EFEH, 6FFEH can be).
+// Read 6800H to determine if there is a button press.
+
+// 键盘选通，整个竖列有一个选通的位置被按下，对应值为0。
+// The keyboard is strobed, and a strobe position is pressed in the entire vertical column, and the corresponding value is 0.
+
+// 键盘扩展
+// 加入方向键盘
+// Keyboard extension
+
+// left:  ctrl M      37 KEY_EX[5]
+// right: ctrl ,      35 KEY_EX[6]
+// up:    ctrl .      33 KEY_EX[4]
+// down:  ctrl space  36 KEY_EX[7]
+// esc:   ctrl -      42 KEY_EX[3]
+// backspace:  ctrl M      37 KEY_EX[8]
+
+// R-Shift
+
+
+wire	[63:0]	KEY_C		=	EMU_KEY_EN?EMU_KEY:KEY;
+wire	[9:0]	KEY_EX_C	=	EMU_KEY_EN?EMU_KEY_EX:KEY_EX;
+
+//wire KEY_CTRL_ULRD = (KEY_EX[7:4]==4'b1111);
+wire KEY_CTRL_ULRD_BRK = (KEY_EX[8:3]==6'b111111);
+
+wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY_C[61], KEY_C[53], KEY_C[45],           KEY_C[37]&KEY_EX_C[5]&KEY_EX_C[8], KEY_C[29], KEY_C[21],           KEY_C[13],                   KEY_C[ 5]})==8'hff;
+wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY_C[60], KEY_C[52], KEY_C[44],           KEY_C[36]&KEY_EX_C[7], KEY_C[28], KEY_C[20],           KEY_C[12],                   KEY_C[ 4]})==8'hff;
+wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY_C[59], KEY_C[51], KEY_C[43],           KEY_C[35]&KEY_EX_C[6], KEY_C[27], KEY_C[19],           KEY_C[11],                   KEY_C[ 3]})==8'hff;
+wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY_C[58], KEY_C[50], KEY_C[42]&KEY_EX_C[3], KEY_C[34],           KEY_C[26], KEY_C[18]&KEY_EX_C[0], KEY_C[10]&KEY_CTRL_ULRD_BRK, KEY_C[ 2]})==8'hff;
+wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY_C[57], KEY_C[49], KEY_C[41],           KEY_C[33]&KEY_EX_C[4], KEY_C[25], KEY_C[17],           KEY_C[ 9],                   KEY_C[ 1]})==8'hff;
+wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY_C[56], KEY_C[48], KEY_C[40],           KEY_C[32],             KEY_C[24], KEY_C[16],           KEY_C[ 8],                   KEY_C[ 0]})==8'hff;
+
+/*
+wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY[61], KEY[53], KEY[45], KEY[37], KEY[29], KEY[21], KEY[13], KEY[ 5]})==8'hff;
+wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY[60], KEY[52], KEY[44], KEY[36], KEY[28], KEY[20], KEY[12], KEY[ 4]})==8'hff;
+wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY[59], KEY[51], KEY[43], KEY[35], KEY[27], KEY[19], KEY[11], KEY[ 3]})==8'hff;
+wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY[58], KEY[50], KEY[42], KEY[34], KEY[26], KEY[18], KEY[10], KEY[ 2]})==8'hff;
+wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY[57], KEY[49], KEY[41], KEY[33], KEY[25], KEY[17], KEY[ 9], KEY[ 1]})==8'hff;
+wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY[56], KEY[48], KEY[40], KEY[32], KEY[24], KEY[16], KEY[ 8], KEY[ 0]})==8'hff;
+*/
+
+wire KEY_DATA_BIT7 = 1'b1;	// 没有空置，具体用途没有理解
+//wire KEY_DATA_BIT6 = CASS_IN;
+wire KEY_DATA_BIT6 = ~CASS_IN;
+
+assign KEY_DATA = { KEY_DATA_BIT7, KEY_DATA_BIT6, KEY_DATA_BIT5, KEY_DATA_BIT4, KEY_DATA_BIT3, KEY_DATA_BIT2, KEY_DATA_BIT1, KEY_DATA_BIT0 };
+
+/*
+assign KEY_DATA = 	(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
+					(CPU_A[1]==1'b0) ? KEY[15: 8] :
+					(CPU_A[2]==1'b0) ? KEY[23:16] :
+					(CPU_A[3]==1'b0) ? KEY[31:24] :
+					(CPU_A[4]==1'b0) ? KEY[39:32] :
+					(CPU_A[5]==1'b0) ? KEY[47:40] :
+					(CPU_A[6]==1'b0) ? KEY[55:48] :
+					(CPU_A[7]==1'b0) ? KEY[63:56] :
+					8'hff;
+
+assign KEY_DATA =
+					(CPU_A[7]==1'b0) ? KEY[63:56] :
+					(CPU_A[6]==1'b0) ? KEY[55:48] :
+					(CPU_A[5]==1'b0) ? KEY[47:40] :
+					(CPU_A[4]==1'b0) ? KEY[39:32] :
+					(CPU_A[3]==1'b0) ? KEY[31:24] :
+					(CPU_A[2]==1'b0) ? KEY[23:16] :
+					(CPU_A[1]==1'b0) ? KEY[15: 8] :
+					(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
+					8'hff;
+*/
+
+
+assign A_KEY_PRESSED = (KEY[63:0] == 64'hFFFFFFFFFFFFFFFF) ? 1'b0:1'b1;
+
+always @(posedge KB_CLK[3] or negedge RESET)
+begin
+	if(~RESET)
+	begin
+		KEY					<=	64'hFFFFFFFFFFFFFFFF;
+		KEY_EX				<=	10'h3FF;
+		KEY_Fxx				<=	12'h000;
+//		CAPS_CLK			<=	1'b0;
+		RESET_KEY_COUNT		<=	17'h1FFFF;
+
+		BOOTROM_BANK		<=	0;
+		BOOTROM_EN			<=	1'b0;
+
+		AUTOSTARTROM_BANK	<=	0;
+		AUTOSTARTROM_EN		<=	1'b0;
+	end
+	else
+	begin
+		//KEY[?] <= CAPS;
+		if(RESET_KEY_COUNT[16]==1'b0)
+			RESET_KEY_COUNT <= RESET_KEY_COUNT+1;
+
+		case(key_code)
+		8'h07:
+		begin
+				KEY_Fxx[11]	<= PRESS;	// F12 RESET
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b0;
+					BOOTROM_BANK		<=	0;
+					AUTOSTARTROM_EN		<=	1'b0;
+					AUTOSTARTROM_BANK	<=	0;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h78:	KEY_Fxx[10] <= PRESS;	// F11
+		8'h09:	KEY_Fxx[ 9] <= PRESS;	// F10 CASS STOP
+		8'h01:	KEY_Fxx[ 8] <= PRESS;	// F9  CASS PLAY
+		8'h0A:
+		begin
+				KEY_Fxx[ 7] <= PRESS;	// F8  Ctrl or L-Shift BOOT 8
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	39;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	23;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h83:
+		begin
+				KEY_Fxx[ 6] <= PRESS;	// F7  Ctrl or L-Shift BOOT 7
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	38;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	22;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h0B:
+		begin
+				KEY_Fxx[ 5] <= PRESS;	// F6  Ctrl or L-Shift BOOT 6
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	37;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	21;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h03:
+		begin
+				KEY_Fxx[ 4] <= PRESS;	// F5  Ctrl or L-Shift BOOT 5
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	36;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	20;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h0C:
+		begin
+				KEY_Fxx[ 3] <= PRESS;	// F4  Ctrl or L-Shift BOOT 4
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	35;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	19;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h04:
+		begin
+				KEY_Fxx[ 2] <= PRESS;	// F3  Ctrl or L-Shift BOOT 3
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	34;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	18;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h06:
+		begin
+				KEY_Fxx[ 1] <= PRESS;	// F2  Ctrl or L-Shift BOOT 2
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	33;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	17;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h05:
+		begin
+				KEY_Fxx[ 0] <= PRESS;	// F1  Ctrl or L-Shift BOOT 1
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	32;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	16;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+
+		8'h16:	KEY[28] <= PRESS_N;	// 1 !
+		8'h1E:	KEY[25] <= PRESS_N;	// 2 @
+		8'h26:	KEY[27] <= PRESS_N;	// 3 #
+		8'h25:	KEY[29] <= PRESS_N;	// 4 $
+		8'h2E:	KEY[24] <= PRESS_N;	// 5 %
+		8'h36:	KEY[40] <= PRESS_N;	// 6 ^
+		8'h3D:	KEY[45] <= PRESS_N;	// 7 &
+//		8'h0D:	KEY[?] <= PRESS_N;	// TAB
+		8'h3E:	KEY[43] <= PRESS_N;	// 8 *
+		8'h46:	KEY[41] <= PRESS_N;	// 9 (
+		8'h45:	KEY[44] <= PRESS_N;	// 0 )
+		8'h4E:	KEY[42] <= PRESS_N;	// - _
+//		8'h55:	KEY[?] <= PRESS_N;	// = +
+		8'h66:	KEY_EX[8] <= PRESS_N;	// backspace
+//		8'h0E:	KEY[?] <= PRESS_N;	// ` ~
+//		8'h5D:	KEY[?] <= PRESS_N;	// \ |
+		8'h49:	KEY[33] <= PRESS_N;	// . >
+		8'h4b:	KEY[57] <= PRESS_N;	// L
+		8'h44:	KEY[49] <= PRESS_N;	// O
+//		8'h11	KEY[?] <= PRESS_N; // line feed (really right ALT (Extended) see below
+		8'h5A:	KEY[50] <= PRESS_N;	// CR
+//		8'h54:	KEY[?] <= PRESS_N;	// [ {
+//		8'h5B:	KEY[?] <= PRESS_N;	// ] }
+		8'h52:	KEY[58] <= PRESS_N;	// ' "
+		8'h1D:	KEY[ 1] <= PRESS_N;	// W
+		8'h24:	KEY[ 3] <= PRESS_N;	// E
+		8'h2D:	KEY[ 5] <= PRESS_N;	// R
+		8'h2C:	KEY[ 0] <= PRESS_N;	// T
+		8'h35:	KEY[48] <= PRESS_N;	// Y
+		8'h3C:	KEY[53] <= PRESS_N;	// U
+		8'h43:	KEY[51] <= PRESS_N;	// I
+		8'h1B:	KEY[ 9] <= PRESS_N;	// S
+		8'h23:	KEY[11] <= PRESS_N;	// D
+		8'h2B:	KEY[13] <= PRESS_N;	// F
+		8'h34:	KEY[ 8] <= PRESS_N;	// G
+		8'h33:	KEY[56] <= PRESS_N;	// H
+		8'h3B:	KEY[61] <= PRESS_N;	// J
+		8'h42:	KEY[59] <= PRESS_N;	// K
+		8'h22:	KEY[17] <= PRESS_N;	// X
+		8'h21:	KEY[19] <= PRESS_N;	// C
+		8'h2a:	KEY[21] <= PRESS_N;	// V
+		8'h32:	KEY[16] <= PRESS_N;	// B
+		8'h31:	KEY[32] <= PRESS_N;	// N
+		8'h3a:	KEY[37] <= PRESS_N;	// M
+		8'h41:	KEY[35] <= PRESS_N;	// , <
+		8'h15:	KEY[ 4] <= PRESS_N;	// Q
+		8'h1C:	KEY[12] <= PRESS_N;	// A
+		8'h1A:	KEY[20] <= PRESS_N;	// Z
+		8'h29:	KEY[36] <= PRESS_N;	// Space
+//		8'h4A:	KEY[?] <= PRESS_N;	// / ?
+		8'h4C:	KEY[60] <= PRESS_N;	// ; :
+		8'h4D:	KEY[52] <= PRESS_N;	// P
+		8'h14:	KEY[10] <= PRESS_N;	// Ctrl either left or right
+		8'h12:	KEY[18] <= PRESS_N;	// L-Shift
+		8'h59:	KEY_EX[0] <= PRESS_N;	// R-Shift
+		8'h11:
+		begin
+			if(~EXTENDED)
+					KEY_EX[1] <= PRESS_N;	// Repeat really left ALT
+			else
+					KEY_EX[2] <= PRESS_N;	// LF really right ALT
+		end
+		8'h76:	KEY_EX[3] <= PRESS_N;	// Esc
+		8'h75:	KEY_EX[4] <= PRESS_N;	// up
+		8'h6B:	KEY_EX[5] <= PRESS_N;	// left
+		8'h74:	KEY_EX[6] <= PRESS_N;	// right
+		8'h72:	KEY_EX[7] <= PRESS_N;	// down
+		endcase
+	end
+end
+
+
+
+
+always @ (posedge CLK50MHZ)				// 50MHz
+	KB_CLK <= KB_CLK + 1'b1;			// 50/32 = 1.5625 MHz
+/*
+ps2_keyboard KEYBOARD(
+		.RESET_N(RESET_N),
+		.CLK(KB_CLK[4]),
+		.key_strobe     (key_strobe     ),
+		.key_pressed    (key_pressed    ),
+		.key_code       (key_code       ),
+		.PS2_CLK(PS2_KBCLK),
+		.PS2_DATA(PS2_KBDAT),
+		.RX_SCAN(SCAN),
+		.RX_PRESSED(PRESS),
+		.RX_EXTENDED(EXTENDED)
+);*/
+
+assign PRESS_N = ~key_pressed;
+
+
+`ifdef CASS_EMU
+
+wire			CASS_BUF_RD;
+wire	[15:0]	CASS_BUF_A;
+wire			CASS_BUF_WR;
+wire	[7:0]	CASS_BUF_DAT;
+wire	[7:0]	CASS_BUF_Q;
+
+// F9    CASS PLAY
+// F10   CASS STOP
+
+EMU_CASS_KEY	EMU_CASS_KEY(
+	KEY_Fxx[8],
+	KEY_Fxx[9],
+	// cass emu
+	CASS_BUF_RD,
+	//
+	CASS_BUF_A,
+	CASS_BUF_WR,
+	CASS_BUF_DAT,
+	CASS_BUF_Q,
+	//	Control Signals
+	EMU_CASS_EN,
+	EMU_CASS_DAT,
+
+	// key emu
+	EMU_KEY,
+	EMU_KEY_EX,
+	EMU_KEY_EN,
+    /*
+     * UART: 115200 bps, 8N1
+     */
+    UART_RXD,
+    UART_TXD,
+
+	// System
+	TURBO_SPEED,
+	// Clock: 10MHz
+	CLK10MHZ,
+	RESET_N
+);
+
+
+`ifdef CASS_EMU_16K
+
+cass_ram_16k_altera cass_buf(
+	.address(CASS_BUF_A[13:0]),
+	.clock(CLK10MHZ),
+	.data(CASS_BUF_DI),
+	.wren(CASS_BUF_WR),
+	.q(CASS_BUF_Q)
+);
+
+`endif
+
+
+`ifdef CASS_EMU_8K
+
+cass_ram_8k_altera cass_buf(
+	.address(CASS_BUF_A[12:0]),
+	.clock(CLK10MHZ),
+	.data(CASS_BUF_DI),
+	.wren(CASS_BUF_WR),
+	.q(CASS_BUF_Q)
+);
+
+`endif
+
+
+`ifdef CASS_EMU_4K
+
+cass_ram_4k_altera cass_buf(
+	.address(CASS_BUF_A[11:0]),
+	.clock(CLK10MHZ),
+	.data(CASS_BUF_DAT),
+	.wren(CASS_BUF_WR),
+	.q(CASS_BUF_Q)
+);
+
+`endif
+
+
+`ifdef CASS_EMU_2K
+
+cass_ram_2k_altera cass_buf(
+	.address(CASS_BUF_A[10:0]),
+	.clock(CLK10MHZ),
+	.data(CASS_BUF_DAT),
+	.wren(CASS_BUF_WR),
+	.q(CASS_BUF_Q)
+);
+
+`endif
+
+`endif
+
+sn76489_top #(
+	.clock_div_16_g(1))
+sn76489(
+   .clock_i(CLK25MHZ),
+   .clock_en_i(CPU_CLK),
+   .res_n_i(RESET),
+   .ce_n_i(),//todo
+   .we_n_i(),//todo
+   .ready_o(),
+   .d_i(CPU_DO),
+   .aout_o(audio_s)
+  );
+
+assign	CASS_OUT = EMU_CASS_EN ? EMU_CASS_DAT : {LATCHED_IO_DATA_WR[2], 1'b0};
+
+(*keep*)wire trap = (CPU_RD|CPU_WR) && (CPU_A[15:12] == 4'h0);
+
+assign AUD_ADCDAT = {LATCHED_IO_DATA_WR[0],LATCHED_IO_DATA_WR[5]};
+endmodule
diff --git a/Computer_MiST/Laser310_MiST/rtl/Laser310_MiST.sv b/Computer_MiST/Laser310_MiST/rtl/Laser310_MiST.sv
new file mode 100644
index 00000000..52beaa2d
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/Laser310_MiST.sv
@@ -0,0 +1,134 @@
+
+module Laser310_MiST
+(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"Laser310;;",
+	"O1,Turbo,Off,On;",
+	"O2,Dos Rom,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,SHRG,Off,On;",
+	"T6,Reset;",
+	"V,v1.00.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+wire clk_50, clk_25, clk_10, clk_6p25;
+wire pll_locked;
+pll pll(
+	.inclk0(CLOCK_27),
+	.areset(0),
+	.c0(clk_50),
+	.c1(clk_25),
+	.c2(clk_10),
+	.c3(clk_6p25)
+	);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] joystick_0;
+wire  [7:0] joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire       		key_pressed;
+wire 		[7:0] key_code;
+wire       		key_strobe;
+reg  [1:0] audio;
+wire  [7:0] audio_s;
+wire 			ce_pix;
+wire 			hs, vs;
+wire  [7:0] r,g,b;
+
+LASER310_TOP LASER310_TOP(
+	.CLK50MHZ(clk_50),
+	.CLK25MHZ(clk_25),
+	.CLK10MHZ(clk_10),
+	.RESET(~(status[0] | status[6] | buttons[1])),
+	.VGA_RED(r),
+	.VGA_GREEN(g),
+	.VGA_BLUE(b),
+	.VGA_HS(hs),
+	.VGA_VS(vs),
+	.AUD_ADCDAT(audio),
+	.audio_s(audio_s),
+//	.PS2_KBCLK(ps2_kbd_clk),
+//	.PS2_KBDAT(ps2_kbd_data),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.SWITCH({"00000",!status[5],!status[2],!status[1]}),
+	.UART_RXD(),
+	.UART_TXD()
+	);
+	
+mist_video #(.COLOR_DEPTH(6)) mist_video(
+	.clk_sys(clk_25),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R(r[5:0]),
+	.G(g[5:0]),
+	.B(b[5:0]),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.scandoubler_disable(1'b1),//scandoublerD),
+	.scanlines(scandoublerD ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_25         ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.status         (status         )
+	);
+
+dac #(
+	.C_bits(15))
+dac(
+	.clk_i(clk_25),
+	.res_n_i(1),
+//	.dac_i({~audio_s[7],audio_s[6:0],{4{audio}}}),
+	.dac_i({8{audio}}),
+	.dac_o(AUDIO_L)
+	);
+
+endmodule 
\ No newline at end of file
diff --git a/Computer_MiST/Laser310_MiST/rtl/LaserCassEmu.sv b/Computer_MiST/Laser310_MiST/rtl/LaserCassEmu.sv
new file mode 100644
index 00000000..73c05ec9
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/LaserCassEmu.sv
@@ -0,0 +1,122 @@
+module LaserCassEmu(
+input wire	[15:0]	CPU_A,
+input wire				CPU_RD,
+input wire				CPU_WR
+);
+// cassette
+
+(*keep*)wire	[1:0]	CASS_OUT;
+(*keep*)wire			CASS_IN;
+(*keep*)wire			CASS_IN_L;
+(*keep*)wire			CASS_IN_R;
+
+reg		[7:0]		LATCHED_IO_DATA_WR;
+// 用于外部磁带仿真计数
+//(*keep*)reg				EMU_CASS_CLK;
+
+(*keep*)wire			EMU_CASS_EN;
+(*keep*)wire	[1:0]	EMU_CASS_DAT;
+
+`ifdef CASS_EMU
+
+wire			CASS_BUF_RD;
+wire	[15:0]	CASS_BUF_A;
+wire			CASS_BUF_WR;
+wire	[7:0]	CASS_BUF_DAT;
+wire	[7:0]	CASS_BUF_Q;
+
+// F9    CASS PLAY
+// F10   CASS STOP
+
+EMU_CASS_KEY	EMU_CASS_KEY(
+	KEY_Fxx[8],
+	KEY_Fxx[9],
+	// cass emu
+	CASS_BUF_RD,
+	//
+	CASS_BUF_A,
+	CASS_BUF_WR,
+	CASS_BUF_DAT,
+	CASS_BUF_Q,
+	//	Control Signals
+	EMU_CASS_EN,
+	EMU_CASS_DAT,
+
+	// key emu
+	EMU_KEY,
+	EMU_KEY_EX,
+	EMU_KEY_EN,
+    /*
+     * UART: 115200 bps, 8N1
+     */
+    UART_RXD,
+    UART_TXD,
+
+	// System
+	TURBO_SPEED,
+	// Clock: 10MHz
+	CLK10MHZ,
+	RESET_N
+);
+
+
+`ifdef CASS_EMU_16K
+
+cass_ram_16k_altera cass_buf(
+	.address(CASS_BUF_A[13:0]),
+	.clock(CLK10MHZ),
+	.data(CASS_BUF_DI),
+	.wren(CASS_BUF_WR),
+	.q(CASS_BUF_Q)
+);
+
+`endif
+
+
+`ifdef CASS_EMU_8K
+
+cass_ram_8k_altera cass_buf(
+	.address(CASS_BUF_A[12:0]),
+	.clock(CLK10MHZ),
+	.data(CASS_BUF_DI),
+	.wren(CASS_BUF_WR),
+	.q(CASS_BUF_Q)
+);
+
+`endif
+
+
+`ifdef CASS_EMU_4K
+
+cass_ram_4k_altera cass_buf(
+	.address(CASS_BUF_A[11:0]),
+	.clock(CLK10MHZ),
+	.data(CASS_BUF_DAT),
+	.wren(CASS_BUF_WR),
+	.q(CASS_BUF_Q)
+);
+
+`endif
+
+
+`ifdef CASS_EMU_2K
+
+cass_ram_2k_altera cass_buf(
+	.address(CASS_BUF_A[10:0]),
+	.clock(CLK10MHZ),
+	.data(CASS_BUF_DAT),
+	.wren(CASS_BUF_WR),
+	.q(CASS_BUF_Q)
+);
+
+`endif
+
+`endif
+
+
+
+assign	CASS_OUT = EMU_CASS_EN ? EMU_CASS_DAT : {LATCHED_IO_DATA_WR[2], 1'b0};
+
+(*keep*)wire trap = (CPU_RD|CPU_WR) && (CPU_A[15:12] == 4'h0);
+
+endmodule 
\ No newline at end of file
diff --git a/Computer_MiST/Laser310_MiST/rtl/LaserKeyboard.sv b/Computer_MiST/Laser310_MiST/rtl/LaserKeyboard.sv
new file mode 100644
index 00000000..f7698728
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/LaserKeyboard.sv
@@ -0,0 +1,414 @@
+module LaserKeyboard(
+input wire				CLK50MHZ,
+input wire	[15:0]	CPU_A,
+input wire				RESET,
+input wire				CASS_IN,
+input wire				PS2_KBCLK,
+input wire				PS2_KBDAT
+);
+
+
+// keyboard
+reg		[4:0]		KB_CLK;
+reg		[16:0]		RESET_KEY_COUNT;
+wire	[7:0]		SCAN;
+wire				PRESS;
+wire				PRESS_N;
+wire				EXTENDED;
+reg					BOOTROM_EN;
+reg		[7:0]		BOOTROM_BANK;
+reg					AUTOSTARTROM_EN;
+reg		[7:0]		AUTOSTARTROM_BANK;
+reg		[63:0]		KEY;
+reg		[9:0]		KEY_EX;
+reg		[11:0]		KEY_Fxx;
+wire	[7:0]		KEY_DATA;
+//reg	[63:0]		LAST_KEY;
+//reg				CAPS_CLK;
+//reg				CAPS;
+wire				A_KEY_PRESSED;
+
+reg		[7:0]		LATCHED_KEY_DATA;
+
+// emu keyboard
+wire	[63:0]		EMU_KEY;
+wire	[9:0]		EMU_KEY_EX;
+wire				EMU_KEY_EN;
+// keyboard
+
+/*****************************************************************************
+* Convert PS/2 keyboard to ASCII keyboard
+******************************************************************************/
+
+/*
+   KD5 KD4 KD3 KD2 KD1 KD0 扫描用地址
+A0  R   Q   E       W   T  68FEH       0
+A1  F   A   D  CTRL S   G  68FDH       8
+A2  V   Z   C  SHFT X   B  68FBH      16
+A3  4   1   3       2   5  68F7H      24
+A4  M  空格 ，      .   N  68EFH      32
+A5  7   0   8   -   9   6  68DFH      40
+A6  U   P   I  RETN O   Y  68BFH      48
+A7  J   ；  K   :   L   H  687FH      56
+*/
+
+//  7: 0
+// 15: 8
+// 23:16
+// 31:24
+// 39:32
+// 47:40
+// 55:48
+// 63:56
+
+
+
+// 键盘检测的方法，就是循环地问每一行线发送低电平信号，也就是用该地址线为“0”的地址去读取数据。
+// 例如，检测第一行时，使A0为0，其余为1；加上选通IC4的高五位地址01101，成为01101***11111110B（A8~A10不起作用，
+// 可为任意值，故68FEH，69FEH，6AFEH，6BFEH，6CFEH，6DFEH，6EFEH，6FFEH均可）。
+// 读 6800H 判断是否有按键按下。
+
+// The method of keyboard detection is to cyclically ask each line to send a low level signal, 
+// that is, to read the data with the address line "0".
+// For example, when detecting the first line, make A0 0 and the rest 1; plus the high five-bit address 01101 of the strobe IC4, 
+// become 01101***11111110B (A8~A10 does not work,
+// It can be any value, so 68FEH, 69FEH, 6AFEH, 6BFEH, 6CFEH, 6DFEH, 6EFEH, 6FFEH can be).
+// Read 6800H to determine if there is a button press.
+
+// 键盘选通，整个竖列有一个选通的位置被按下，对应值为0。
+// The keyboard is strobed, and a strobe position is pressed in the entire vertical column, and the corresponding value is 0.
+
+// 键盘扩展
+// 加入方向键盘
+// Keyboard extension
+
+// left:  ctrl M      37 KEY_EX[5]
+// right: ctrl ,      35 KEY_EX[6]
+// up:    ctrl .      33 KEY_EX[4]
+// down:  ctrl space  36 KEY_EX[7]
+// esc:   ctrl -      42 KEY_EX[3]
+// backspace:  ctrl M      37 KEY_EX[8]
+
+// R-Shift
+
+
+wire	[63:0]	KEY_C		=	EMU_KEY_EN?EMU_KEY:KEY;
+wire	[9:0]	KEY_EX_C	=	EMU_KEY_EN?EMU_KEY_EX:KEY_EX;
+
+//wire KEY_CTRL_ULRD = (KEY_EX[7:4]==4'b1111);
+wire KEY_CTRL_ULRD_BRK = (KEY_EX[8:3]==6'b111111);
+
+wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY_C[61], KEY_C[53], KEY_C[45],           KEY_C[37]&KEY_EX_C[5]&KEY_EX_C[8], KEY_C[29], KEY_C[21],           KEY_C[13],                   KEY_C[ 5]})==8'hff;
+wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY_C[60], KEY_C[52], KEY_C[44],           KEY_C[36]&KEY_EX_C[7], KEY_C[28], KEY_C[20],           KEY_C[12],                   KEY_C[ 4]})==8'hff;
+wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY_C[59], KEY_C[51], KEY_C[43],           KEY_C[35]&KEY_EX_C[6], KEY_C[27], KEY_C[19],           KEY_C[11],                   KEY_C[ 3]})==8'hff;
+wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY_C[58], KEY_C[50], KEY_C[42]&KEY_EX_C[3], KEY_C[34],           KEY_C[26], KEY_C[18]&KEY_EX_C[0], KEY_C[10]&KEY_CTRL_ULRD_BRK, KEY_C[ 2]})==8'hff;
+wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY_C[57], KEY_C[49], KEY_C[41],           KEY_C[33]&KEY_EX_C[4], KEY_C[25], KEY_C[17],           KEY_C[ 9],                   KEY_C[ 1]})==8'hff;
+wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY_C[56], KEY_C[48], KEY_C[40],           KEY_C[32],             KEY_C[24], KEY_C[16],           KEY_C[ 8],                   KEY_C[ 0]})==8'hff;
+
+/*
+wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY[61], KEY[53], KEY[45], KEY[37], KEY[29], KEY[21], KEY[13], KEY[ 5]})==8'hff;
+wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY[60], KEY[52], KEY[44], KEY[36], KEY[28], KEY[20], KEY[12], KEY[ 4]})==8'hff;
+wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY[59], KEY[51], KEY[43], KEY[35], KEY[27], KEY[19], KEY[11], KEY[ 3]})==8'hff;
+wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY[58], KEY[50], KEY[42], KEY[34], KEY[26], KEY[18], KEY[10], KEY[ 2]})==8'hff;
+wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY[57], KEY[49], KEY[41], KEY[33], KEY[25], KEY[17], KEY[ 9], KEY[ 1]})==8'hff;
+wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY[56], KEY[48], KEY[40], KEY[32], KEY[24], KEY[16], KEY[ 8], KEY[ 0]})==8'hff;
+*/
+
+wire KEY_DATA_BIT7 = 1'b1;	// 没有空置，具体用途没有理解
+//wire KEY_DATA_BIT6 = CASS_IN;
+wire KEY_DATA_BIT6 = ~CASS_IN;
+
+assign KEY_DATA = { KEY_DATA_BIT7, KEY_DATA_BIT6, KEY_DATA_BIT5, KEY_DATA_BIT4, KEY_DATA_BIT3, KEY_DATA_BIT2, KEY_DATA_BIT1, KEY_DATA_BIT0 };
+
+/*
+assign KEY_DATA = 	(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
+					(CPU_A[1]==1'b0) ? KEY[15: 8] :
+					(CPU_A[2]==1'b0) ? KEY[23:16] :
+					(CPU_A[3]==1'b0) ? KEY[31:24] :
+					(CPU_A[4]==1'b0) ? KEY[39:32] :
+					(CPU_A[5]==1'b0) ? KEY[47:40] :
+					(CPU_A[6]==1'b0) ? KEY[55:48] :
+					(CPU_A[7]==1'b0) ? KEY[63:56] :
+					8'hff;
+
+assign KEY_DATA =
+					(CPU_A[7]==1'b0) ? KEY[63:56] :
+					(CPU_A[6]==1'b0) ? KEY[55:48] :
+					(CPU_A[5]==1'b0) ? KEY[47:40] :
+					(CPU_A[4]==1'b0) ? KEY[39:32] :
+					(CPU_A[3]==1'b0) ? KEY[31:24] :
+					(CPU_A[2]==1'b0) ? KEY[23:16] :
+					(CPU_A[1]==1'b0) ? KEY[15: 8] :
+					(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
+					8'hff;
+*/
+
+
+assign A_KEY_PRESSED = (KEY[63:0] == 64'hFFFFFFFFFFFFFFFF) ? 1'b0:1'b1;
+
+always @(posedge KB_CLK[3] or negedge RESET)
+begin
+	if(~RESET)
+	begin
+		KEY					<=	64'hFFFFFFFFFFFFFFFF;
+		KEY_EX				<=	10'h3FF;
+		KEY_Fxx				<=	12'h000;
+//		CAPS_CLK			<=	1'b0;
+		RESET_KEY_COUNT		<=	17'h1FFFF;
+
+		BOOTROM_BANK		<=	0;
+		BOOTROM_EN			<=	1'b0;
+
+		AUTOSTARTROM_BANK	<=	0;
+		AUTOSTARTROM_EN		<=	1'b0;
+	end
+	else
+	begin
+		//KEY[?] <= CAPS;
+		if(RESET_KEY_COUNT[16]==1'b0)
+			RESET_KEY_COUNT <= RESET_KEY_COUNT+1;
+
+		case(SCAN)
+		/*8'h07:
+		begin
+				KEY_Fxx[11]	<= PRESS;	// F12 RESET
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b0;
+					BOOTROM_BANK		<=	0;
+					AUTOSTARTROM_EN		<=	1'b0;
+					AUTOSTARTROM_BANK	<=	0;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h78:	KEY_Fxx[10] <= PRESS;	// F11
+		8'h09:	KEY_Fxx[ 9] <= PRESS;	// F10 CASS STOP
+		8'h01:	KEY_Fxx[ 8] <= PRESS;	// F9  CASS PLAY
+		8'h0A:
+		begin
+				KEY_Fxx[ 7] <= PRESS;	// F8  Ctrl or L-Shift BOOT 8
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	39;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	23;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h83:
+		begin
+				KEY_Fxx[ 6] <= PRESS;	// F7  Ctrl or L-Shift BOOT 7
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	38;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	22;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h0B:
+		begin
+				KEY_Fxx[ 5] <= PRESS;	// F6  Ctrl or L-Shift BOOT 6
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	37;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	21;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h03:
+		begin
+				KEY_Fxx[ 4] <= PRESS;	// F5  Ctrl or L-Shift BOOT 5
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	36;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	20;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h0C:
+		begin
+				KEY_Fxx[ 3] <= PRESS;	// F4  Ctrl or L-Shift BOOT 4
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	35;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	19;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h04:
+		begin
+				KEY_Fxx[ 2] <= PRESS;	// F3  Ctrl or L-Shift BOOT 3
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	34;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	18;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h06:
+		begin
+				KEY_Fxx[ 1] <= PRESS;	// F2  Ctrl or L-Shift BOOT 2
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	33;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	17;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h05:
+		begin
+				KEY_Fxx[ 0] <= PRESS;	// F1  Ctrl or L-Shift BOOT 1
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	32;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	16;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end*/
+
+		8'h16:	KEY[28] <= PRESS_N;	// 1 !
+		8'h1E:	KEY[25] <= PRESS_N;	// 2 @
+		8'h26:	KEY[27] <= PRESS_N;	// 3 #
+		8'h25:	KEY[29] <= PRESS_N;	// 4 $
+		8'h2E:	KEY[24] <= PRESS_N;	// 5 %
+		8'h36:	KEY[40] <= PRESS_N;	// 6 ^
+		8'h3D:	KEY[45] <= PRESS_N;	// 7 &
+//		8'h0D:	KEY[?] <= PRESS_N;	// TAB
+		8'h3E:	KEY[43] <= PRESS_N;	// 8 *
+		8'h46:	KEY[41] <= PRESS_N;	// 9 (
+		8'h45:	KEY[44] <= PRESS_N;	// 0 )
+		8'h4E:	KEY[42] <= PRESS_N;	// - _
+//		8'h55:	KEY[?] <= PRESS_N;	// = +
+		8'h66:	KEY_EX[8] <= PRESS_N;	// backspace
+//		8'h0E:	KEY[?] <= PRESS_N;	// ` ~
+//		8'h5D:	KEY[?] <= PRESS_N;	// \ |
+		8'h49:	KEY[33] <= PRESS_N;	// . >
+		8'h4b:	KEY[57] <= PRESS_N;	// L
+		8'h44:	KEY[49] <= PRESS_N;	// O
+//		8'h11	KEY[?] <= PRESS_N; // line feed (really right ALT (Extended) see below
+		8'h5A:	KEY[50] <= PRESS_N;	// CR
+//		8'h54:	KEY[?] <= PRESS_N;	// [ {
+//		8'h5B:	KEY[?] <= PRESS_N;	// ] }
+		8'h52:	KEY[58] <= PRESS_N;	// ' "
+		8'h1D:	KEY[ 1] <= PRESS_N;	// W
+		8'h24:	KEY[ 3] <= PRESS_N;	// E
+		8'h2D:	KEY[ 5] <= PRESS_N;	// R
+		8'h2C:	KEY[ 0] <= PRESS_N;	// T
+		8'h35:	KEY[48] <= PRESS_N;	// Y
+		8'h3C:	KEY[53] <= PRESS_N;	// U
+		8'h43:	KEY[51] <= PRESS_N;	// I
+		8'h1B:	KEY[ 9] <= PRESS_N;	// S
+		8'h23:	KEY[11] <= PRESS_N;	// D
+		8'h2B:	KEY[13] <= PRESS_N;	// F
+		8'h34:	KEY[ 8] <= PRESS_N;	// G
+		8'h33:	KEY[56] <= PRESS_N;	// H
+		8'h3B:	KEY[61] <= PRESS_N;	// J
+		8'h42:	KEY[59] <= PRESS_N;	// K
+		8'h22:	KEY[17] <= PRESS_N;	// X
+		8'h21:	KEY[19] <= PRESS_N;	// C
+		8'h2a:	KEY[21] <= PRESS_N;	// V
+		8'h32:	KEY[16] <= PRESS_N;	// B
+		8'h31:	KEY[32] <= PRESS_N;	// N
+		8'h3a:	KEY[37] <= PRESS_N;	// M
+		8'h41:	KEY[35] <= PRESS_N;	// , <
+		8'h15:	KEY[ 4] <= PRESS_N;	// Q
+		8'h1C:	KEY[12] <= PRESS_N;	// A
+		8'h1A:	KEY[20] <= PRESS_N;	// Z
+		8'h29:	KEY[36] <= PRESS_N;	// Space
+//		8'h4A:	KEY[?] <= PRESS_N;	// / ?
+		8'h4C:	KEY[60] <= PRESS_N;	// ; :
+		8'h4D:	KEY[52] <= PRESS_N;	// P
+		8'h14:	KEY[10] <= PRESS_N;	// Ctrl either left or right
+		8'h12:	KEY[18] <= PRESS_N;	// L-Shift
+		8'h59:	KEY_EX[0] <= PRESS_N;	// R-Shift
+		8'h11:
+		begin
+			if(~EXTENDED)
+					KEY_EX[1] <= PRESS_N;	// Repeat really left ALT
+			else
+					KEY_EX[2] <= PRESS_N;	// LF really right ALT
+		end
+		8'h76:	KEY_EX[3] <= PRESS_N;	// Esc
+		8'h75:	KEY_EX[4] <= PRESS_N;	// up
+		8'h6B:	KEY_EX[5] <= PRESS_N;	// left
+		8'h74:	KEY_EX[6] <= PRESS_N;	// right
+		8'h72:	KEY_EX[7] <= PRESS_N;	// down
+		endcase
+	end
+end
+
+
+
+
+always @ (posedge CLK50MHZ)				// 50MHz
+	KB_CLK <= KB_CLK + 1'b1;			// 50/32 = 1.5625 MHz
+
+ps2_keyboard KEYBOARD(
+		.RESET_N(~RESET),
+		.CLK(KB_CLK[4]),
+		.PS2_CLK(PS2_KBCLK),
+		.PS2_DATA(PS2_KBDAT),
+		.RX_SCAN(SCAN),
+		.RX_PRESSED(PRESS),
+		.RX_EXTENDED(EXTENDED)
+);
+
+assign PRESS_N = ~PRESS;
+
+
+endmodule 
\ No newline at end of file
diff --git a/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80ALU.v b/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80ALU.v
new file mode 100644
index 00000000..610781a2
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80ALU.v
@@ -0,0 +1,372 @@
+//////////////////////////////////////////////////////////////////////////////////
+//
+// This file is part of the NextZ80 project
+// http://www.opencores.org/cores/nextz80/
+//
+// Filename: NextZ80ALU.v
+// Description: Implementation of Z80 compatible CPU - ALU
+// Version 1.0
+// Creation date: 28Jan2011 - 18Mar2011
+//
+// Author: Nicolae Dumitrache 
+// e-mail: ndumitrache@opencores.org
+//
+/////////////////////////////////////////////////////////////////////////////////
+// 
+// Copyright (C) 2011 Nicolae Dumitrache
+// 
+// This source file may be used and distributed without 
+// restriction provided that this copyright statement is not 
+// removed from the file and that any derivative work contains 
+// the original copyright notice and the associated disclaimer.
+// 
+// This source file is free software; you can redistribute it 
+// and/or modify it under the terms of the GNU Lesser General 
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any 
+// later version. 
+// 
+// This source is distributed in the hope that it will be 
+// useful, but WITHOUT ANY WARRANTY; without even the implied 
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
+// PURPOSE. See the GNU Lesser General Public License for more 
+// details. 
+// 
+// You should have received a copy of the GNU Lesser General 
+// Public License along with this source; if not, download it 
+// from http://www.opencores.org/lgpl.shtml 
+// 
+///////////////////////////////////////////////////////////////////////////////////
+
+//FLAGS: S Z X1 N X2 PV N C
+//	OP[4:0]
+//	00000	-	ADD	D0,D1
+//	00001	-	ADC	D0,D1
+//	00010	-	SUB	D0,D1
+//	00011	-	SBC	D0,D1
+//	00100	-	AND	D0,D1
+//	00101	-	XOR	D0,D1
+//	00110	-	OR		D0,D1
+//	00111	-	CP		D0,D1
+//	01000	-	INC	D0
+//	01001	-	CPL	D0
+// 01010	-	DEC	D0
+//	01011	-	RRD
+// 01100	-	RLD
+//	01101	-	DAA
+//	01110	-	INC16
+//	01111	-  DEC16
+// 10000	-	ADD16LO
+//	10001	-	ADD16HI
+//	10010	-	
+//	10011	-	
+//	10100	-	CCF, pass D0
+// 10101	-	SCF, pass D0
+// 10110	-	
+//	10111	-	
+//	11000	-	RLCA	D0
+//	11001	-	RRCA	D0
+//	11010	-	RLA	D0
+//	11011	- 	RRA	D0
+//	11100	-	{ROT, BIT, SET, RES} D0,EXOP 
+//				  RLC		D0			C <-- D0 <-- D0[7]
+//            RRC		D0			D0[0] --> D0 --> C
+//            RL		D0			C <-- D0 <-- C
+//            RR		D0			C --> D0 --> C
+//            SLA		D0			C <-- D0 <-- 0
+//            SRA		D0			D0[7] --> D0 --> C
+//            SLL		D0			C <-- D0 <-- 1
+//            SRL		D0			0 --> D0 --> C
+//	11101	-	IN, pass D1
+//	11110	-	FLAGS <- D0
+//	11111	-	NEG	D1	
+///////////////////////////////////////////////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module ALU8(
+    input [7:0] D0,
+    input [7:0] D1,
+	 input [7:0] FIN,
+    output reg[7:0] FOUT,
+    output reg [15:0] ALU8DOUT,
+    input [4:0] OP,
+	 input [5:0] EXOP, // EXOP[5:4] = 2'b11 for CPI/D/R
+	 input LDIFLAGS,	 // zero HF and NF on inc/dec16
+	 input DSTHI		 // destination lo
+    );
+	
+	wire [7:0] daaadjust;
+	wire cdaa, hdaa;
+	daa daa_adjust(.flags(FIN), .val(D0), .adjust(daaadjust), .cdaa(cdaa), .hdaa(hdaa));
+	
+	wire parity = ~^ALU8DOUT[15:8];
+	wire zero = ALU8DOUT[15:8] == 0;
+	reg csin, cin;
+	wire [7:0]d0mux = OP[4:1] == 4'b1111 ? 0 : D0;
+	reg [7:0]_d1mux;
+	wire [7:0]d1mux = OP[1] ? ~_d1mux : _d1mux;
+	wire [8:0]sum;
+	wire hf;
+	assign {hf, sum[3:0]} = d0mux[3:0] + d1mux[3:0] + cin;
+	assign sum[8:4] = d0mux[7:4] + d1mux[7:4] + hf;
+	wire overflow = (d0mux[7] & d1mux[7] & !sum[7]) | (!d0mux[7] & !d1mux[7] & sum[7]);
+	reg [7:0]dbit;
+
+	always @* begin
+		ALU8DOUT = 16'hxxxx;
+		FOUT = 8'hxx;
+		case({OP[4:2]})
+			0,1,4,7: _d1mux = D1;
+			2: _d1mux = 1;
+			3: _d1mux = daaadjust;		// DAA
+			6,5: _d1mux = 8'hxx;
+		endcase
+		case({OP[2:0], FIN[0]})
+			0,1,2,7,8,9,10,11,12,13:	cin = 0;
+			3,4,5,6,14,15: cin = 1;
+		endcase
+		case(EXOP[3:0])
+			0: dbit =  8'b11111110;
+			1: dbit =  8'b11111101;
+			2: dbit =  8'b11111011;
+			3: dbit =  8'b11110111;
+			4: dbit =  8'b11101111;
+			5: dbit =  8'b11011111;
+			6: dbit =  8'b10111111;
+			7: dbit =  8'b01111111;
+			8: dbit =  8'b00000001;
+			9: dbit =  8'b00000010;
+			10: dbit = 8'b00000100;
+			11: dbit = 8'b00001000;
+			12: dbit = 8'b00010000;
+			13: dbit = 8'b00100000;
+			14: dbit = 8'b01000000;
+			15: dbit = 8'b10000000;
+		endcase
+		case(OP[3] ? EXOP[2:0] : OP[2:0])
+			0,5:	csin = D0[7];
+			1: 	csin = D0[0];
+			2,3:	csin = FIN[0];
+			4,7:	csin = 0;
+			6:		csin = 1;
+		endcase
+		case(OP[4:0])
+			0,1,2,3,8,10:	begin		// ADD, ADC, SUB, SBC, INC, DEC
+				ALU8DOUT[15:8] = sum[7:0];
+				ALU8DOUT[7:0] = sum[7:0];
+				FOUT[0] = OP[3] ? FIN[0] : (sum[8] ^ OP[1]); // inc/dec
+				FOUT[1] = OP[1];
+				FOUT[2] = overflow;
+				FOUT[3] = ALU8DOUT[11];
+				FOUT[4] = hf ^ OP[1];
+				FOUT[5] = ALU8DOUT[13];
+				FOUT[6] = zero & (FIN[6] | ~EXOP[5] | ~DSTHI | OP[3]); //(EXOP[5] & DSTHI) ? (zero & FIN[6]) : zero;				// adc16/sbc16
+				FOUT[7] = ALU8DOUT[15];
+			end
+			16,17:	begin		// ADD16LO, ADD16HI
+				ALU8DOUT[15:8] = sum[7:0];
+				ALU8DOUT[7:0] = sum[7:0];
+				FOUT[0] = sum[8];
+				FOUT[1] = OP[1];
+				FOUT[2] = FIN[2];
+				FOUT[3] = ALU8DOUT[11];
+				FOUT[4] = hf ^ OP[1];
+				FOUT[5] = ALU8DOUT[13];
+				FOUT[6] = FIN[6];
+				FOUT[7] = FIN[7];
+			end
+			7: begin		// CP
+				ALU8DOUT[15:8] = sum[7:0];
+				FOUT[0] = EXOP[5] ? FIN[0] : !sum[8]; // CPI/D/R
+				FOUT[1] = OP[1];
+				FOUT[2] = overflow;
+				FOUT[3] = D1[3];
+				FOUT[4] = !hf;
+				FOUT[5] = D1[5];
+				FOUT[6] = zero;
+				FOUT[7] = ALU8DOUT[15];
+			end
+			31:	begin		// NEG
+				ALU8DOUT[15:8] = sum[7:0];
+				FOUT[0] = !sum[8];
+				FOUT[1] = OP[1];
+				FOUT[2] = overflow;
+				FOUT[3] = ALU8DOUT[11];
+				FOUT[4] = !hf;
+				FOUT[5] = ALU8DOUT[13];
+				FOUT[6] = zero;
+				FOUT[7] = ALU8DOUT[15];
+			end
+			4: begin			// AND
+				ALU8DOUT[15:8] = D0 & D1;
+				FOUT[0] = 0;
+				FOUT[1] = 0;
+				FOUT[2] = parity;
+				FOUT[3] = ALU8DOUT[11];
+				FOUT[4] = 1;
+				FOUT[5] = ALU8DOUT[13];
+				FOUT[6] = zero;
+				FOUT[7] = ALU8DOUT[15];
+			end
+			5,6: begin		//XOR, OR
+				ALU8DOUT[15:8] = OP[0] ? (D0 ^ D1) : (D0 | D1);
+				FOUT[0] = 0;
+				FOUT[1] = 0;
+				FOUT[2] = parity;
+				FOUT[3] = ALU8DOUT[11];
+				FOUT[4] = 0;
+				FOUT[5] = ALU8DOUT[13];
+				FOUT[6] = zero;
+				FOUT[7] = ALU8DOUT[15];
+			end
+			9: begin			// CPL
+				ALU8DOUT[15:8] = ~D0;
+				FOUT[0] = FIN[0];
+				FOUT[1] = 1;
+				FOUT[2] = FIN[2];
+				FOUT[3] = ALU8DOUT[11];
+				FOUT[4] = 1;
+				FOUT[5] = ALU8DOUT[13];
+				FOUT[7:6] = FIN[7:6];
+			end
+			11,12: begin					// RLD, RRD
+				if(OP[0]) ALU8DOUT = {D0[7:4], D1[3:0], D0[3:0], D1[7:4]};
+				else ALU8DOUT = {D0[7:4], D1[7:0], D0[3:0]};
+				FOUT[0] = FIN[0];
+				FOUT[1] = 0;
+				FOUT[2] = parity;
+				FOUT[3] = ALU8DOUT[11];
+				FOUT[4] = 0;
+				FOUT[5] = ALU8DOUT[13];
+				FOUT[6] = zero;
+				FOUT[7] = ALU8DOUT[15];
+			end			
+			13: begin	// DAA
+				ALU8DOUT[15:8] = sum[7:0];
+				FOUT[0] = cdaa;
+				FOUT[1] = FIN[1];
+				FOUT[2] = parity;
+				FOUT[3] = ALU8DOUT[11];
+				FOUT[4] = hdaa;
+				FOUT[5] = ALU8DOUT[13];
+				FOUT[6] = zero;
+				FOUT[7] = ALU8DOUT[15];
+			end
+			14,15: begin	// inc/dec 16
+				ALU8DOUT = {D0, D1} + (OP[0] ? 16'hffff : 16'h0001);
+				FOUT[0] = FIN[0];
+				FOUT[1] = LDIFLAGS ? 1'b0 : FIN[1];
+				FOUT[2] = ALU8DOUT != 0;
+				FOUT[3] = FIN[3];
+				FOUT[4] = LDIFLAGS ? 1'b0 : FIN[4];
+				FOUT[5] = FIN[5];
+				FOUT[6] = FIN[6];
+				FOUT[7] = FIN[7];
+			end
+			20,21: begin		// CCF, SCF
+				ALU8DOUT[15:8] = D0;
+				FOUT[0] = OP[0] ? 1'b1 : !FIN[0];
+				FOUT[1] = 1'b0;
+				FOUT[2] = FIN[2];
+				FOUT[3] = ALU8DOUT[11];
+				FOUT[4] = OP[0] ? 1'b0 : FIN[0];
+				FOUT[5] = ALU8DOUT[13];
+				FOUT[6] = FIN[6];
+				FOUT[7] = FIN[7];				
+			end
+			24,25,26,27, 28: begin 							// ROT, BIT, RES, SET
+				case({OP[2], EXOP[4:3]})
+					0,1,2,3,4:	// rot - shift
+						if(OP[2] ? EXOP[0] : OP[0]){ALU8DOUT[15:8], FOUT[0]} = {csin, D0};		// right
+						else							 	{FOUT[0], ALU8DOUT[15:8]} = {D0, csin};		// left
+					5,6: begin	// BIT, RES 
+						FOUT[0] = FIN[0]; 
+						ALU8DOUT[15:8] = D0 & dbit; 
+					end		
+					7: begin 	// SET
+						FOUT[0] = FIN[0]; 
+						ALU8DOUT[15:8] = D0 | dbit; 
+					end			
+				endcase
+				ALU8DOUT[7:0] = ALU8DOUT[15:8];
+				FOUT[1] = 0;
+				FOUT[2] = OP[2] ? (EXOP[3] ? zero : parity) : FIN[2];
+				FOUT[3] = ALU8DOUT[11];
+				FOUT[4] = OP[2] & EXOP[3];
+				FOUT[5] = ALU8DOUT[13];
+				FOUT[6] = OP[2] ? zero : FIN[6];
+				FOUT[7] = OP[2] ? ALU8DOUT[15] : FIN[7];
+			end
+			29:	begin		// IN, pass D1
+				ALU8DOUT = {D1, D1};
+				FOUT[0] = FIN[0];
+				FOUT[1] = 0;
+				FOUT[2] = parity;
+				FOUT[3] = ALU8DOUT[11];
+				FOUT[4] = 0;
+				FOUT[5] = ALU8DOUT[13];
+				FOUT[6] = zero;
+				FOUT[7] = ALU8DOUT[15];
+			end
+			30: FOUT = D0;		// FLAGS <- D0
+			default:;
+		endcase
+	end
+endmodule
+
+module daa (
+	input [7:0]flags,
+	input [7:0]val,
+	output wire [7:0]adjust,
+	output reg cdaa,
+	output reg hdaa
+	);
+	
+	wire h08 = val[7:4] < 9;
+	wire h09 = val[7:4] < 10;
+	wire l05 = val[3:0] < 6;
+	wire l09 = val[3:0] < 10;
+	reg [1:0]aa;
+	assign adjust = ({1'b0, aa[1], aa[1], 2'b0, aa[0], aa[0], 1'b0} ^ {8{flags[1]}}) + flags[1];
+	
+	always @* begin
+		case({flags[0], h08, h09, flags[4], l09})
+			5'b00101, 5'b01101:	aa = 0;
+			5'b00111, 5'b01111, 5'b01000, 5'b01010, 5'b01100, 5'b01110:	aa = 1;
+			5'b00001, 5'b01001, 5'b10001, 5'b10101, 5'b11001, 5'b11101:	aa = 2;
+			default: aa = 3;
+		endcase
+		case({flags[0], h08, h09, l09})
+			4'b0011, 4'b0111, 4'b0100, 4'b0110:	cdaa = 0;
+			default: cdaa = 1;
+		endcase
+		case({flags[1], flags[4], l05, l09})
+			4'b0000, 4'b0010, 4'b0100, 4'b0110, 4'b1110, 4'b1111:	hdaa = 1;
+			default:	hdaa = 0;
+		endcase
+	end
+endmodule
+
+
+module ALU16(
+    input [15:0] D0,
+    input [7:0] D1,
+    output wire[15:0] DOUT,
+    input [2:0]OP	// 0-NOP, 1-INC, 2-INC2, 3-ADD, 4-NOP, 5-DEC, 6-DEC2
+    );
+	
+	reg [15:0] mux;
+	always @*
+		case(OP)
+			0: mux = 0;				// post inc
+			1: mux = 1;				// post inc
+			2: mux = 2;				// post inc
+			3: mux = {D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7:0]};	// post inc
+			4: mux = 0;				// no post inc			
+			5: mux = 16'hffff;	// no post inc
+			6: mux = 16'hfffe;	// no post inc
+			default: mux = 16'hxxxx;
+		endcase
+	
+	assign DOUT = D0 + mux;
+endmodule
diff --git a/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80CPU.v b/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80CPU.v
new file mode 100644
index 00000000..25d26af8
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80CPU.v
@@ -0,0 +1,1499 @@
+//////////////////////////////////////////////////////////////////////////////////
+//
+// This file is part of the NextZ80 project
+// http://www.opencores.org/cores/nextz80/
+//
+// Filename: NextZ80CPU.v
+// Description: Implementation of Z80 compatible CPU
+// Version 1.0
+// Creation date: 28Jan2011 - 18Mar2011
+//
+// Author: Nicolae Dumitrache 
+// e-mail: ndumitrache@opencores.org
+//
+/////////////////////////////////////////////////////////////////////////////////
+// 
+// Copyright (C) 2011 Nicolae Dumitrache
+// 
+// This source file may be used and distributed without 
+// restriction provided that this copyright statement is not 
+// removed from the file and that any derivative work contains 
+// the original copyright notice and the associated disclaimer.
+// 
+// This source file is free software; you can redistribute it 
+// and/or modify it under the terms of the GNU Lesser General 
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any 
+// later version. 
+// 
+// This source is distributed in the hope that it will be 
+// useful, but WITHOUT ANY WARRANTY; without even the implied 
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
+// PURPOSE. See the GNU Lesser General Public License for more 
+// details. 
+// 
+// You should have received a copy of the GNU Lesser General 
+// Public License along with this source; if not, download it 
+// from http://www.opencores.org/lgpl.shtml 
+// 
+///////////////////////////////////////////////////////////////////////////////////
+//
+// Comments:
+// This project was developed and tested on a XILINX Spartan3AN board.
+//
+//	NextZ80 processor features:
+//		All documented/undocumented intstructions are implemented
+//		All documented/undocumented flags are implemented
+//		All (doc/undoc)flags are changed accordingly by all (doc/undoc)instructions. 
+//			The block instructions (LDx, CPx, INx, OUTx) have only the documented effects on flags. 
+//			The Bit n,(IX/IY+d) and BIT n,(HL) undocumented flags XF and YF are implemented like the BIT n,r and not actually like on the real Z80 CPU.
+//		All interrupt modes implemented: NMI, IM0, IM1, IM2
+//		R register available
+//		Fast conditional jump/call/ret takes only 1 T state if not executed
+//		Fast block instructions: LDxR - 3 T states/byte, INxR/OTxR - 2 T states/byte, CPxR - 4 T states / byte
+//		Each CPU machine cycle takes (mainly) one clock T state. This makes this processor over 4 times faster than a Z80 at the same 
+//			clock frequency (some instructions are up to 10 times faster). 
+//		Works at ~40MHZ on Spartan XC3S700AN speed grade -4)
+//		Small size ( ~12%  ~700 slices - on Spartan XC3S700AN )
+//		Tested with ZEXDOC (fully compliant).
+//		Tested with ZEXALL (all OK except CPx(R), LDx(R), BIT n, (IX/IY+d), BIT n, (HL) - fail because of the un-documented XF and YF flags).
+// 
+///////////////////////////////////////////////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module NextZ80
+(
+		input wire[7:0] DI,
+		output wire[7:0] DO,
+		output wire[15:0] ADDR,
+		output reg WR,
+		output reg MREQ,
+		output reg IORQ,
+		output reg HALT,
+		output reg M1,
+		input wire CLK,
+		input wire RESET,
+		input wire INT,
+		input wire NMI,
+		input	wire WAIT
+);
+
+// connections and registers
+	reg	[9:0] CPUStatus = 0;	// 0=AF-AF', 1=HL-HL', 2=DE-HL, 3=DE'-HL', 4=HL-X, 5=IX-IY, 6=IFF1,7=IFF2, 9:8=IMODE
+	wire	[7:0] ALU8FLAGS;
+	wire	[7:0]	FLAGS;
+	wire 	[7:0] ALU80;
+	wire 	[7:0] ALU81;
+	wire 	[15:0]ALU160;
+	wire 	[7:0] ALU161;
+	wire	[15:0]ALU8OUT;
+
+	reg 	[9:0]	FETCH = 0;
+	reg 	[2:0]	STAGE = 0;
+	wire	[5:0]	opd;
+	wire	[2:0] op16;
+	wire	op0mem = FETCH[2:0] == 6;
+	wire	op1mem = FETCH[5:3] == 6;
+	reg	[1:0]fetch98;
+
+// stage status
+	reg	[1:0]DO_SEL;			// ALU80 - th - flags - ALU8OUT[7:0]
+	reg	ALU160_SEL;				// regs - pc
+	reg	DINW_SEL;				// ALU8OUT - DI
+	reg 	[5:0]WE;					// 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo
+	reg 	[4:0] ALU8OP;
+	reg 	[2:0] ALU16OP;
+	reg 	next_stage;
+	reg 	[3:0]REG_WSEL;
+	reg 	[3:0]REG_RSEL;
+	reg	[11:0]status;			// 0=AF-AF', 1=HL-HL', 2=DE-HL, 3=DE'-HL', 4=HL-X, 5=IX-IY, 7:6=IFFVAL, 9:8=imode, 10=setIMODE, 11=set IFFVAL
+// FETCH[5:3]: 000 NZ, 001 Z, 010 NC, 011 C, 100 PO, 101 PE, 110 P, 111 M
+	wire	[7:0]FlagMux = {FLAGS[7], !FLAGS[7], FLAGS[2], !FLAGS[2], FLAGS[0], !FLAGS[0], FLAGS[6], !FLAGS[6]};
+	reg	tzf;
+	reg 	FNMI = 0, SNMI = 0;
+	reg 	SRESET = 0;
+	reg	SINT = 0;
+	wire	[2:0]intop = FETCH[1] ? 4 : (FETCH[0] ? 5 : 6);
+	reg 	xmask;
+
+	Z80Reg CPU_REGS (
+		 .rstatus(CPUStatus[7:0]), 
+		 .M1(M1), 
+		 .WE(WE), 
+		 .CLK(CLK), 
+		 .ALU8OUT(ALU8OUT), 
+		 .DI(DI), 
+		 .DO(DO), 
+		 .ADDR(ADDR), 									
+		 .CONST(FETCH[7] ? {2'b00, FETCH[5:3], 3'b000} : 8'h66),	// RST/NMI address
+		 .ALU80(ALU80), 
+		 .ALU81(ALU81), 
+		 .ALU160(ALU160), 
+		 .ALU161(ALU161), 
+		 .ALU8FLAGS(ALU8FLAGS), 
+		 .FLAGS(FLAGS),
+		 .DO_SEL(DO_SEL), 
+		 .ALU160_sel(ALU160_SEL), 
+		 .REG_WSEL(REG_WSEL), 
+		 .REG_RSEL(REG_RSEL), 
+		 .DINW_SEL(DINW_SEL),
+		 .XMASK(xmask),
+		 .ALU16OP(ALU16OP),			// used for post increment for ADDR, SP mux re-direct
+		 .WAIT(WAIT)
+		 );
+
+	ALU8 CPU_ALU8 (
+		 .D0(ALU80), 
+		 .D1(ALU81), 
+		 .FIN(FLAGS), 
+		 .FOUT(ALU8FLAGS), 
+		 .ALU8DOUT(ALU8OUT), 
+		 .OP(ALU8OP),
+		 .EXOP(FETCH[8:3]),
+		 .LDIFLAGS(REG_WSEL[2]),	// inc16 HL
+		 .DSTHI(!REG_WSEL[0])
+		 );
+
+	ALU16 CPU_ALU16 (
+		 .D0(ALU160), 
+		 .D1(ALU161), 
+		 .DOUT(ADDR), 
+		 .OP(ALU16OP)
+		 );
+
+	always @(posedge CLK)
+		if(!WAIT) begin
+			SRESET <= RESET;
+			SNMI <= NMI;
+			SINT <= INT;
+			if(!SNMI) FNMI <= 0; 
+			if(SRESET) FETCH <= 10'b1110000000;
+			else 
+				if(FETCH[9:6] == 4'b1110) {FETCH[9:7]} <= 3'b000;	// exit RESET state
+				else begin 
+					if(M1 || (fetch98 == 2'b10))	// [DD/FD CB disp op] -  M1 is inactive during <op> byte read, but FETCH is performed
+						case({MREQ, CPUStatus[9:8]})
+							3'b000, 3'b001, 3'b100, 3'b101, 3'b110, 3'b111: FETCH <= {fetch98, DI};
+							3'b010: FETCH <= {fetch98, 8'hff};	// IM1 - RST38
+							3'b011: ; // IM2 - get addrLO
+						endcase
+					if(~|{next_stage, fetch98[1:0], status[4]})				// INT or NMI sample
+						if(SNMI & !FNMI) begin						// NMI posedge
+							{FETCH[9:6], FETCH[1:0]} <= {4'b1101, HALT, M1};
+							FNMI <= 1;	// NMI acknowledged
+						end else if(SINT & CPUStatus[6] & !status[11]) {FETCH[9:6], FETCH[1:0]} <= {4'b1100, HALT, M1};	// INT request
+				end
+			if(next_stage) STAGE <= STAGE + 3'b001;
+			else STAGE <= 0;
+			if(status[4]) CPUStatus[5:4] <= status[5:4];
+			else if(~|{next_stage, fetch98[1]} | fetch98[0]) CPUStatus[4] <= 1'b0;		// clear X
+			CPUStatus[3:0] <= CPUStatus[3:0] ^ status[3:0];
+			if(status[11]) CPUStatus[7:6] <= status[7:6]; 	// IFF2:1
+			if(status[10]) CPUStatus[9:8] <= status[9:8];	// IMM
+			tzf <= ALU8FLAGS[6];
+		end
+
+	assign opd[0] = FETCH[0] ^ &FETCH[2:1];
+	assign opd[2:1] = FETCH[2:1];
+	assign opd[3] = FETCH[3] ^ &FETCH[5:4];
+	assign opd[5:4] = FETCH[5:4];
+	assign op16[2:0] = &FETCH[5:4] ? 3'b101 : {1'b0, FETCH[5:4]};
+
+	always @* begin
+		DO_SEL	= 2'bxx;						// ALU80 - th - flags - ALU8OUT[7:0]
+		ALU160_SEL = 1'bx;					// regs - pc
+		DINW_SEL = 1'bx;						// ALU8OUT - DI
+		WE 		= 6'bxxxxxx;				// 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo
+		ALU8OP	= 5'bxxxxx;
+		ALU16OP	= 3'b000;					// NOP, post inc
+		next_stage = 0;
+		REG_WSEL	= 4'bxxxx;
+		REG_RSEL	= 4'bx0xx;				// prevents default 4'b0100 which leads to incorrect P flag value in some cases (like RLA)
+		M1 		= 1;
+		MREQ		= 1;
+		WR			= 0;
+
+		HALT = 0;
+		IORQ = 0;
+		status	= 12'b00xxxxx00000;
+		fetch98 = 2'b00;
+		
+		case({FETCH[7:6], op1mem, op0mem})
+			4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b1000, 4'b1100: xmask = 1;
+			default: xmask = 0;
+		endcase
+		
+		case(FETCH[9:6])	
+//------------------------------------------- block 00 ----------------------------------------------------
+			4'b0000:
+				case(FETCH[3:0])
+//				-----------------------		NOP, EX AF, AF', DJNZ, JR, JR c --------------------
+					4'b0000, 4'b1000:	
+						case(FETCH[5:4])
+							2'b00: begin					// NOP, EX AF, AF'
+								DO_SEL	= 2'bxx;			
+								ALU160_SEL = 1;			// PC
+								WE 		= 6'b010x00;	// PC
+								status[0] = FETCH[3];
+							end
+							2'b01:				
+								if(!STAGE[0]) begin		// DJNZ, JR - stage1
+									ALU160_SEL = 1;				// pc
+									WE 		= 6'b010100;		// PC, tmpHI
+									if(!FETCH[3]) begin
+										ALU8OP	= 5'b01010;			// DEC, for tzf only
+										REG_WSEL	= 4'b0000;			// B
+									end
+									next_stage = 1;
+									M1 		= 0;
+								end else if(FETCH[3]) begin	// JR - stage2
+									ALU160_SEL = 1;				// pc
+									WE 		= 6'b010x00;		// PC
+									ALU16OP	= 3;					// ADD
+								end else begin				// DJNZ - stage2
+									ALU160_SEL = 1;				// pc
+									DINW_SEL = 0;					// ALU8OUT
+									WE 		= 6'b010x10;		// PC, hi
+									ALU8OP	= 5'b01010;			// DEC
+									ALU16OP	= tzf ? 3'd0 : 3'd3;		// NOP/ADD
+									REG_WSEL	= 4'b0000;			// B
+								end
+							2'b10, 2'b11: 							// JR cc, stage1, stage2
+								case({STAGE[0], FlagMux[{1'b0, FETCH[4:3]}]})
+									2'b00, 2'b11: begin
+										ALU160_SEL = 1;				// pc
+										WE 		= 6'b010x00;		// PC
+										ALU16OP	= STAGE[0] ? 3'd3 : 3'd1;		// ADD/ INC, post inc
+									end 
+									2'b01: begin
+										ALU160_SEL = 1;				// pc
+										WE 		= 6'b010100;		// PC, tmpHI
+										next_stage = 1; 
+										M1 		= 0;
+									end
+								endcase
+						endcase
+//				-----------------------		LD rr,nn  --------------------
+					4'b0001: 			// LD rr,nn, stage1
+						case({STAGE[1:0], op16[2]})
+							3'b00_0, 3'b00_1, 3'b01_0, 3'b01_1: begin			// LD rr,nn, stage1,2
+								ALU160_SEL = 1;			// pc
+								DINW_SEL = 1;				// DI
+								WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};	// PC, lo/HI
+								next_stage = 1;
+								REG_WSEL	= {op16, 1'bx}; 
+								M1 		= 0;
+							end
+							3'b10_0, 3'b11_1: begin		// BC, DE, HL, stage3, SP stage4
+								ALU160_SEL = 1;			// pc
+								WE 		= 6'b010x00;	// PC
+							end
+							3'b10_1: begin				// SP stage3
+								ALU160_SEL = 0;			// regs
+								WE 		= 6'b001x00;	// SP
+								ALU16OP	= 4;				// NOP
+								next_stage = 1;
+								REG_RSEL	= 4'b101x;		// tmpSP
+								M1 		= 0;
+								MREQ		= 0;
+							end
+						endcase
+//				-----------------------		LD (BC) A -  LD (DE) A - LD (nn) HL, LD (nn),A   --------------------
+//				-----------------------		LD A (BC) -  LD A (DE) - LD HL (nn), LD A (nn)   --------------------
+					4'b0010,	4'b1010:
+						case(STAGE[2:0])
+							3'b000:
+								if(FETCH[5] == 0) begin			// LD (BC) A, LD (DE) A - stage1
+									if(FETCH[3]) DINW_SEL = 1;		// DI
+									else DO_SEL	= 2'b00;				// ALU80
+									ALU160_SEL = 0;				// regs
+									WE 		= {4'b000x, FETCH[3], 1'bx};		// hi
+									next_stage = 1;
+									REG_WSEL	= FETCH[3] ? 4'b011x : 4'b0110;	// A
+									REG_RSEL	= {op16, 1'bx};
+									M1 		= 0;
+									WR = !FETCH[3];
+								end else begin						// LD (nn) A - LD (nn) HL - stage 1
+									ALU160_SEL = 1;				// PC
+									DINW_SEL = 1;					// DI
+									WE 		= 6'b010xx1;		// PC, lo
+									next_stage = 1;
+									REG_WSEL	= 4'b111x;
+									M1 		= 0;
+								end
+							3'b001:
+								if(FETCH[5] == 0) begin			// LD (BC), A, LD (DE), A - stage2
+									ALU160_SEL = 1;				// pc
+									WE 		= 6'b010x00;		// PC
+								end else begin						// LD (nn),A  - LH (nn),HL - stage 2
+									ALU160_SEL = 1;				// pc
+									DINW_SEL = 1;					// DI
+									WE 		= 6'b010x10;		// PC, hi
+									next_stage = 1;
+									REG_WSEL	= 4'b111x;
+									M1 		= 0;
+								end
+							3'b010: begin					
+								ALU160_SEL = 1'b0;		// regs
+								REG_RSEL	= 4'b111x;
+								M1 		= 0;
+								WR			= !FETCH[3];
+								next_stage = 1;
+								if(FETCH[3]) begin		// LD A (nn)  - LD HL (nn) - stage 3
+									DINW_SEL = 1;				// DI
+									WE 		= {4'b000x, FETCH[4] ? 1'b1 : 1'bx, FETCH[4] ? 1'bx : 1'b1};	// lo/hi
+									REG_WSEL = FETCH[4] ? 4'b011x : 4'b010x;	// A or L
+								end else begin				// LD (nn),A  - LD (nn),HL - stage 3
+									DO_SEL	= 2'b00;			// ALU80
+									WE 		= 6'b000x00;	// nothing
+									REG_WSEL = FETCH[4] ? 4'b0110 : 4'b0101;	// A or L
+								end
+							end
+							3'b011:
+								if(FETCH[4]) begin			// LD (nn),A - stage 4
+									ALU160_SEL = 1;			// pc
+									WE 		= 6'b010x00;	// PC
+								end else begin					
+									REG_RSEL	= 4'b111x;
+									M1 		= 0;
+									WR			= !FETCH[3];
+									ALU160_SEL = 1'b0;		// regs
+									ALU16OP	= 1;				// INC
+									next_stage = 1;
+									if(FETCH[3]) begin	// LD HL (nn) - stage 4
+										DINW_SEL = 1;				// DI
+										WE 		= 6'b000x10;	// hi
+										REG_WSEL = 4'b010x;		// H
+									end else begin			// LD (nn),HL - stage 4
+										DO_SEL	= 2'b00;			// ALU80
+										WE 		= 6'b000x00;	// nothing
+										REG_WSEL = 4'b0100;		// H
+									end
+								end
+							3'b100: begin				// LD (nn),HL - stage 5
+								ALU160_SEL = 1;			// pc
+								WE 		= 6'b010x00;	// PC
+							end
+						endcase
+//				-----------------------		inc/dec rr   --------------------
+					4'b0011, 4'b1011:
+						if(!STAGE[0])
+							if(op16[2]) begin				// SP - stage1
+								ALU160_SEL = 0;			// regs
+								WE 		= 6'b001x00;	// SP
+								ALU16OP	= {FETCH[3], 1'b0, FETCH[3]};		// post inc, dec
+								next_stage = 1;
+								REG_RSEL	= 4'b101x;		// sp
+								M1 		= 0;
+								MREQ		= 0;
+							end else begin					// BC, DE, HL - stage 1
+								ALU160_SEL = 1;			// pc
+								DINW_SEL = 0;				// ALU8OUT
+								WE 		= 6'b010x11;	// PC, hi, lo
+								ALU8OP	= {4'b0111, FETCH[3]};			// INC16 / DEC16
+								REG_WSEL	= {op16, 1'b0};	// hi
+								REG_RSEL	= {op16, 1'b1};	// lo
+							end
+						else 	begin				// SP, stage2
+							ALU160_SEL = 1;			// pc
+							WE 		= 6'b010x00;	// PC
+						end
+//				-----------------------		inc/dec 8  --------------------
+					4'b0100, 4'b0101, 4'b1100, 4'b1101: 
+						if(!op1mem) begin						//regs
+							DINW_SEL = 0;						// ALU8OUT
+							ALU160_SEL = 1;					// pc
+							WE 		= opd[3] ? 6'b110x01 : 6'b110x10;	// flags, PC, hi/lo
+							ALU8OP	= {3'b010, FETCH[0], 1'b0};		// inc / dec
+							REG_WSEL	= {1'b0, opd[5:3]};
+						end else case({STAGE[1:0], CPUStatus[4]})
+							3'b00_0, 3'b01_1: begin				// (HL) - stage1, (X) - stage2
+								ALU160_SEL = 0;					// regs
+								DINW_SEL = 1;						// DI
+								WE 		= 6'b000001;			// lo
+								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
+								next_stage = 1;
+								REG_WSEL	= 4'b011x;				// tmpLO
+								REG_RSEL	= 4'b010x;				// HL
+								M1 		= 0;
+							end
+							3'b00_1:	begin							// (X) - stage1
+								ALU160_SEL = 1;					// pc
+								WE 		= 6'b010100;			// PC, tmpHI
+								next_stage = 1;
+								M1 		= 0;
+							end 
+							3'b01_0, 3'b10_1: begin					// (HL) stage2, (X) - stage3
+								DO_SEL	= 2'b11;						// ALU80OUT
+								ALU160_SEL = 0;						// regs
+								WE 		= 6'b100x0x;				// flags
+								ALU8OP	= {3'b010, FETCH[0], 1'b0};		// inc / dec
+								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
+								next_stage = 1;
+								REG_WSEL	= 4'b0111;					// tmpLO
+								REG_RSEL	= 4'b010x;					// HL
+								M1 		= 0;
+								WR			= 1;
+							end
+							3'b10_0, 3'b11_1: begin					// (HL) - stage3, (X) - stage 4
+								ALU160_SEL = 1;						// pc
+								WE 		= 6'b010x00;				// PC
+							end
+						endcase
+//				-----------------------		ld r/(HL-X), n  --------------------						
+					4'b0110, 4'b1110: 				
+						case({STAGE[1:0], CPUStatus[4], op1mem})
+							4'b00_0_0, 4'b00_0_1, 4'b00_1_0, 4'b01_1_1: begin		// r, (HL) - stage1, (X) - stage2 (read n)
+								ALU160_SEL = 1;					// pc
+								DINW_SEL = 1;						// DI
+								WE 		= opd[3] ? 6'b010001 : 6'b010010;			// PC, hi/lo
+								next_stage = 1;
+								REG_WSEL	= {1'b0, opd[5:4], 1'bx};
+								M1 		= 0;
+							end
+							4'b01_0_0, 4'b01_1_0, 4'b10_0_1, 4'b11_1_1: begin		// r - stage2, (HL) - stage3, (X) - stage4
+								ALU160_SEL = 1;						// pc
+								WE 		= 6'b010x00;				// PC
+							end
+							4'b01_0_1, 4'b10_1_1: begin			// (HL) - stage2, (X) - stage3
+								DO_SEL	= 2'b00;						// ALU80
+								ALU160_SEL = 0;						// regs
+								WE 		= 6'b000x0x;				// nothing
+								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
+								next_stage = 1;
+								REG_WSEL	= 4'b0111;					// tmpLO
+								REG_RSEL	= 4'b010x;					// HL
+								M1 		= 0;
+								WR			= 1;
+							end
+							4'b00_1_1: begin							// (X) - stage1
+								ALU160_SEL = 1;						// pc
+								WE 		= 6'b010100;				// PC, tmpHI
+								next_stage = 1;
+								M1 		= 0;
+							end
+						endcase
+//				-----------------------		rlca, rrca, rla, rra, daa, cpl, scf, ccf  --------------------						
+					4'b0111, 4'b1111: 				
+						case(FETCH[5:3])
+							3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101: begin		// rlca, rrca, rla, rra, daa, cpl
+								ALU160_SEL = 1;					// pc
+								DINW_SEL = 0;						// ALU8OUT
+								WE 		= 6'b110x1x;			// flags, PC, hi
+								ALU8OP	= FETCH[5] ? {2'b01, !FETCH[3], 2'b01} : {3'b110, FETCH[4:3]};
+								REG_WSEL	= 4'b0110;				// A
+							end
+							3'b110, 3'b111:	begin				// scf, ccf
+								ALU160_SEL = 1;					// pc
+								DINW_SEL = 0;						// ALU8OUT
+								WE 		= 6'b110x0x;			// flags, PC
+								ALU8OP	= {4'b1010, !FETCH[3]};
+							end
+						endcase
+//				-----------------------		add 16  --------------------						
+					4'b1001: 
+						if(!STAGE[0]) begin
+							DINW_SEL = 0;						// ALU8OUT
+							WE 		= 6'b100x01;			// flags, lo
+							ALU8OP	= 5'b10000;				// ADD16LO
+							next_stage = 1;
+							REG_WSEL	= 4'b0101;				// L
+							REG_RSEL	= {op16, 1'b1};
+							M1 		= 0;
+							MREQ		= 0;
+						end else begin
+							ALU160_SEL = 1;					// pc
+							DINW_SEL = 0;						// ALU8OUT
+							WE 		= 6'b110x10;			// flags, PC, hi
+							ALU8OP	= 5'b10001;				// ADD16HI
+							REG_WSEL	= 4'b0100;				// H
+							REG_RSEL	= {op16, 1'b0};
+						end
+				endcase
+
+// ---------------------------------------------- block 01 LD8 ---------------------------------------------------
+			4'b0001:	
+				case({STAGE[1:0], CPUStatus[4], op1mem, op0mem})
+					5'b00_0_00, 5'b00_1_00,		// LD r, r 1st stage
+					5'b01_0_01,						// LD r, (HL) 2nd stage
+					5'b10_1_01:						// LD r, (X) 3rd stage
+					begin	
+						ALU160_SEL = 1;			// PC
+						DINW_SEL	  = 0;			// ALU8
+						WE = opd[3] ? 6'b010x01 : 6'b010x10;	// PC and LO or HI
+						ALU8OP = 29;				// PASS D1
+						REG_WSEL = {1'b0, opd[5:4], 1'bx};
+						REG_RSEL = {1'b0, opd[2:0]};
+					end
+					5'b00_0_01,						// LD r, (HL) 1st stage
+					5'b01_1_01:						// LD r, (X) 2nd stage
+					begin	
+						ALU160_SEL = 0;			// regs
+						DINW_SEL = 1;				// DI		
+						WE 		= 6'b000x01;	// LO
+						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;		// ADD - NOP
+						next_stage = 1;
+						REG_WSEL	= 4'b011x;		// A - tmpLO
+						REG_RSEL = 4'b010x;		// HL
+						M1 = 0;
+					end
+					5'b00_1_01,						// LD r, (X) 1st stage
+					5'b00_1_10:						// LD (X), r 1st stage
+					begin
+						ALU160_SEL = 1;			// pc
+						WE 		= 6'b010100;	// PC, tmpHI
+						next_stage = 1;
+						M1 		= 0;
+					end
+					5'b00_0_10, 					// LD (HL), r 1st stage
+					5'b01_1_10:						// LD (X), r 2nd stage
+					begin	
+						DO_SEL	= 0;				// ALU80
+						ALU160_SEL = 0;			// regs
+						WE 		= 6'b000x00;	// no write
+						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;			// ADD - NOP
+						next_stage = 1;
+						REG_WSEL	= {1'b0, opd[2:0]};
+						REG_RSEL	= 4'b010x;		// HL
+						M1 		= 0;
+						WR			= 1;			
+					end
+					5'b01_0_10, 					// LD (HL), r 2nd stage
+					5'b10_1_10:						// LD (X), r 3rd stage
+					begin	
+						ALU160_SEL = 1;			// pc
+						WE 		= 6'b010x00;	// PC
+					end
+					5'b00_0_11, 5'b00_1_11: begin	// HALT
+						WE 		= 6'b000x00;	// no write
+						M1 		= 0;
+						MREQ		= 0;
+						HALT 		= 1;
+					end
+				endcase
+// ---------------------------------------------- block 10 arith8 ---------------------------------------------------
+			4'b0010:	
+				case({STAGE[1:0], CPUStatus[4], op0mem})
+					4'b00_0_0, 4'b00_1_0,		// OP r,r 1st stage
+					4'b01_0_1,						// OP r, (HL) 2nd stage
+					4'b10_1_1:						// OP r, (X) 3rd stage
+					begin
+						ALU160_SEL = 1;			// pc
+						DINW_SEL = 0;				// ALU8OUT
+						WE 		= {4'b110x, ~&FETCH[5:3], 1'bx};	// flags, PC, hi
+						ALU8OP	= {2'b00, FETCH[5:3]};
+						REG_WSEL	= 4'b0110;		// A
+						REG_RSEL	= {1'b0, opd[2:0]};
+					end
+					4'b00_0_1,						// OP r, (HL) 1st stage
+					4'b01_1_1:						// OP r, (X) 2nd stage
+					begin
+						ALU160_SEL = 0;			// HL
+						DINW_SEL = 1;				// DI
+						WE 		= 6'b000x01;	// lo
+						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;			// ADD - NOP
+						next_stage = 1;
+						REG_WSEL	= 4'b011x;		// A-tmpLO
+						REG_RSEL	= 4'b010x;		// HL
+						M1 		= 0;
+					end
+					4'b00_1_1:						// OP r, (X) 1st stage
+					begin
+						ALU160_SEL = 1;			// pc
+						WE 		= 6'b010100;	// PC, tmpHI
+						next_stage = 1;
+						M1 		= 0;
+					end
+				endcase
+//------------------------------------------- block 11 ----------------------------------------------------
+			4'b0011:
+				case(FETCH[3:0])
+//				-----------------------		RET cc --------------------
+					4'b0000, 4'b1000:
+						case(STAGE[1:0])
+							2'b00, 2'b01:			// stage1, stage2
+								if(FlagMux[FETCH[5:3]]) begin	// POP addr
+									ALU160_SEL = 0;				// regs
+									DINW_SEL = 1;					// DI
+									WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};		// SP, lo/hi
+									next_stage = 1;
+									REG_WSEL	= 4'b111x;			// tmp16
+									REG_RSEL	= 4'b101x;			// SP
+									M1 		= 0;
+								end else begin
+									ALU160_SEL = 1;				// pc
+									WE 		= 6'b010x00;		// PC
+								end
+							2'b10: begin			// stage3
+								ALU160_SEL = 0;					// regs
+								WE 		= 6'b010x00;			// PC
+								REG_RSEL	= 4'b111x;				// tmp16
+							end
+						endcase
+//				-----------------------		POP --------------------
+					4'b0001:
+						case(STAGE[1:0])
+							2'b00, 2'b01: begin
+								if(op16[2]) begin	// AF
+									WE 		= STAGE[0] ? 6'b101x1x : 6'b001xx1;		// flags, SP, lo/hi
+									REG_WSEL	= {3'b011, STAGE[0] ? 1'b1 : 1'bx};
+									if(STAGE[0]) ALU8OP	= 30;						// FLAGS <- D0
+								end else begin		// r16
+									WE 		= STAGE[0] ? 6'b001x10 : 6'b001xx1;		// SP, lo/hi
+									REG_WSEL	= {1'b0, FETCH[5:4], 1'bx};
+								end
+								ALU160_SEL = 0;			// regs
+								DINW_SEL = 1;				// DI
+								next_stage = 1;
+								REG_RSEL	= 4'b101x;		// SP
+								M1 		= 0;
+							end
+							2'b10: begin					// stage3
+								ALU160_SEL = 1;			// PC
+								WE 		= 6'b010x00;	// PC
+							end
+						endcase
+//				-----------------------		JP cc --------------------
+					4'b0010, 4'b1010:
+						case(STAGE[1:0])
+							2'b00, 2'b01:	begin				// stage1,2
+								if(FlagMux[FETCH[5:3]]) begin
+									ALU160_SEL = 1;					// pc
+									DINW_SEL = 1;						// DI
+									WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};		// PC, hi/lo
+									next_stage = 1;
+									REG_WSEL	= 4'b111x;				// tmp7
+									M1 		= 0;
+								end else begin
+									ALU160_SEL = 1;					// pc
+									WE 		= 6'b010x00;			// PC
+									ALU16OP	= 2;						// add2
+								end
+							end
+							2'b10: begin						// stage3
+								ALU160_SEL = 0;					// regs
+								WE 		= 6'b010x00;			// PC
+								REG_RSEL	= 4'b111x;				// tmp7
+							end
+						endcase
+//				-----------------------		JP, OUT (n) A, EX (SP) HL, DI --------------------
+					4'b0011:
+						case(FETCH[5:4])
+							2'b00:					// JP
+								case(STAGE[1:0])
+									2'b00, 2'b01:	begin				// stage1,2 - read addr
+										ALU160_SEL = 1;					// pc
+										DINW_SEL = 1;						// DI
+										WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};		// PC, hi/lo
+										next_stage = 1;
+										REG_WSEL	= 4'b111x;				// tmp7
+										M1 		= 0;
+									end
+									2'b10: begin						// stage3
+										ALU160_SEL = 0;					// regs
+										WE 		= 6'b010x00;			// PC
+										REG_RSEL	= 4'b111x;				// tmp7
+									end
+								endcase
+							2'b01: 					// OUT (n), a - stage1 - read n
+								case(STAGE[1:0])
+									2'b00: begin
+										ALU160_SEL = 1;					// pc
+										DINW_SEL = 1;						// DI
+										WE 		= 6'b010x01;			// PC, lo
+										next_stage = 1;
+										REG_WSEL	= 4'b011x;				// tmpLO
+										M1 		= 0;
+									end
+									2'b01: begin		// stage2 - OUT
+										DO_SEL	= 2'b00;					// ALU80
+										ALU160_SEL = 0;					// regs
+										WE 		= 6'b000x00;			// nothing
+										next_stage = 1;
+										REG_WSEL	= 4'b0110;				// A
+										REG_RSEL	= 4'b011x;				// A-tmpLO
+										M1 		= 0;
+										MREQ		= 0;
+										WR 		= 1;
+										IORQ		= 1;
+									end
+									2'b10: begin		// stage3 - fetch
+										ALU160_SEL = 1;			// PC
+										WE 		= 6'b010x00;	// PC
+									end
+								endcase
+							2'b10:				// EX (SP), HL
+								case(STAGE[2:0])
+									3'b000, 3'b001:	begin			// stage1,2 - pop tmp16
+										ALU160_SEL = 0;					// regs
+										DINW_SEL = 1;						// DI
+										WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};			// SP, lo/hi
+										next_stage = 1;
+										REG_WSEL	= 4'b111x;				// tmp16
+										REG_RSEL	= 4'b101x;				// SP
+										M1 		= 0;
+									end
+									3'b010, 3'b011: begin			// stage3,4 - push hl
+										DO_SEL	= 2'b00;					// ALU80
+										ALU160_SEL = 0;					// regs
+										WE 		= 6'b001x00;			// SP
+										ALU16OP	= 5;						// dec
+										next_stage = 1;
+										REG_WSEL	= {3'b010, STAGE[0]};// H/L	
+										REG_RSEL	= 4'b101x;				// SP
+										M1 		= 0;
+										WR			= 1;
+									end
+									3'b100, 3'b101: begin		// stage5,6
+										ALU160_SEL = 1;					// pc
+										DINW_SEL = 0;						// ALU8OUT
+										WE 		= {1'b0, STAGE[0], 2'b0x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};	// PC, lo/hi
+										ALU8OP	= 29;		// pass D1
+										next_stage = !STAGE[0];
+										REG_WSEL	= 4'b010x;		// HL
+										REG_RSEL	= {3'b111, !STAGE[0]};		// tmp16
+										M1 		= STAGE[0];
+										MREQ		= STAGE[0];
+									end
+								endcase
+							2'b11:	begin			// DI
+								ALU160_SEL = 1;			// PC
+								WE 		= 6'b010x00;	// PC
+								status[11] = 1'b1;		// set IFF flags
+								status[7:6] = 2'b00;
+							end
+						endcase
+//				-----------------------		CALL cc --------------------
+					4'b0100, 4'b1100:	
+						case(STAGE[2:0])
+							3'b000, 3'b001:		// stage 1,2 - load addr
+								if(FlagMux[FETCH[5:3]]) begin
+									ALU160_SEL = 1;					// pc
+									DINW_SEL = 1;						// DI
+									WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};		// PC, hi/lo
+									next_stage = 1;
+									REG_WSEL	= 4'b111x;				// tmp7
+									M1 		= 0;
+								end else begin
+									ALU160_SEL = 1;					// pc
+									WE 		= 6'b010x00;			// PC
+									ALU16OP	= 2;						// add2
+								end
+							3'b010, 3'b011: begin		// stage 3,4 - push pc
+								DO_SEL	= {1'b0, STAGE[0]};	// pc hi/lo
+								ALU160_SEL = 0;					// regs
+								WE 		= 6'b001x00;			// SP
+								ALU16OP	= 5;						// DEC
+								next_stage = 1;
+								REG_WSEL	= 4'b1xxx;				// pc
+								REG_RSEL	= 4'b101x;				// sp
+								M1 		= 0;
+								WR			= 1;
+							end
+							3'b100:	begin	// stage5
+								ALU160_SEL = 0;					// regs
+								WE 		= 6'b010x00;			// PC
+								REG_RSEL	= 4'b111x;				// tmp7
+							end
+						endcase
+//				-----------------------		PUSH --------------------
+					4'b0101: 
+						case(STAGE[1:0])
+							2'b00, 2'b01: begin			// stage1,2
+								DO_SEL	= {STAGE[0] & op16[2], 1'b0};		// FLAGS/ALU80
+								ALU160_SEL = 0;				// regs
+								WE 		= 6'b001x00;		// SP
+								ALU16OP	= 5;  				// dec
+								next_stage = 1;
+								REG_WSEL	= {1'b0, FETCH[5:4], STAGE[0]};
+								REG_RSEL	= 4'b101x;				// SP
+								M1 		= 0;
+								WR			= 1;
+							end
+							2'b10: begin					//stage3
+								ALU160_SEL = 1;				// PC
+								WE 		= 6'b010x00;		// PC
+							end
+						endcase
+//				-----------------------		op A, n  --------------------
+					4'b0110, 4'b1110:
+						if(!STAGE[0]) begin			// stage1, read n
+							ALU160_SEL = 1;					// pc
+							DINW_SEL = 1;						// DI
+							WE 		= 6'b010x01;			// PC, lo
+							next_stage = 1;
+							REG_WSEL	= 4'b011x;				// tmpLO
+							M1 		= 0;
+						end else begin					// stage 2
+							DINW_SEL = 0;						// ALU8OUT[7:0]
+							ALU160_SEL = 1;					// pc
+							WE 		= {4'b110x, ~&FETCH[5:3], 1'bx};			// flags, PC, hi
+							ALU8OP	= {2'b00, FETCH[5:3]};
+							REG_WSEL	= 4'b0110;				// A
+							REG_RSEL	= 4'b0111;				// tmpLO
+						end
+//				-----------------------		RST  --------------------
+					4'b0111, 4'b1111:
+						case(STAGE[1:0])
+							2'b00, 2'b01: begin		// stage 1,2 - push pc
+								DO_SEL	= {1'b0, STAGE[0]};	// pc hi/lo
+								ALU160_SEL = 0;					// regs
+								WE 		= 6'b001x00;			// SP
+								ALU16OP	= 5;						// DEC
+								next_stage = 1;
+								REG_WSEL	= 4'b1xxx;				// pc
+								REG_RSEL	= 4'b101x;				// sp
+								M1 		= 0;
+								WR			= 1;
+							end
+							2'b10:	begin				// stage3
+								ALU160_SEL = 0;					// regs
+								WE 		= 6'b010x00;			// PC
+								REG_RSEL	= 4'b110x;				// const
+							end
+						endcase
+//				-----------------------		RET, EXX, JP (HL), LD SP HL --------------------
+					4'b1001:	
+						case(FETCH[5:4])	
+							2'b00: 				// RET
+								case(STAGE[1:0])
+									2'b00, 2'b01:	begin		// stage1, stage2 - pop addr
+										ALU160_SEL = 0;				// regs
+										DINW_SEL = 1;					// DI
+										WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};		// SP, lo/hi
+										next_stage = 1;
+										REG_WSEL	= 4'b111x;			// tmp16
+										REG_RSEL	= 4'b101x;			// SP
+										M1 		= 0;
+									end		
+									2'b10: begin			// stage3 - jump
+										ALU160_SEL = 0;					// regs
+										WE 		= 6'b010x00;			// PC
+										REG_RSEL	= 4'b111x;				// tmp16
+									end
+								endcase
+							2'b01: begin			// EXX
+								ALU160_SEL = 1;			// PC
+								WE 		= 6'b010x00;	// PC
+								status[1] = 1;			
+							end
+							2'b10:	begin		// JP (HL)
+								ALU160_SEL = 0;					// regs
+								WE 		= 6'b010x00;			// PC
+								REG_RSEL	= 4'b010x;				// HL
+							end
+							2'b11: begin	// LD SP,HL	
+								if(!STAGE[0]) begin			// stage1
+									ALU160_SEL = 0;				// regs
+									WE 		= 6'b001x00;		// SP
+									ALU16OP	= 4;					// NOP, no post inc
+									next_stage = 1;
+									REG_RSEL	= 4'b010x;			// HL
+									M1 		= 0;
+									MREQ		= 0;
+								end else begin						// stage2
+									ALU160_SEL = 1;				// pc
+									WE 		= 6'b010x00;		// PC
+								end
+							end
+						endcase
+//				-----------------------		CB, IN A (n), EX DE HL, EI --------------------
+					4'b1011:
+						case(FETCH[5:4])
+							2'b00:  					// CB prefix
+								case({STAGE[0], CPUStatus[4]})
+									2'b00, 2'b11: begin
+										ALU160_SEL = 1;			// PC
+										WE 		= 6'b010000;	// PC
+										fetch98 = 2'b10;		
+										M1 = !CPUStatus[4]; 	// [DD/FD CB disp op] -  M1 is inactive during <op> byte read
+									end
+									2'b01: begin
+										ALU160_SEL = 1;			// PC
+										WE 		= 6'b010100;	// PC, tmpHI
+										next_stage = 1;
+										M1 		= 0;
+									end
+								endcase
+							2'b01:					// IN A, (n)
+								case(STAGE[1:0])
+									2'b00: begin		//stage1 - read n
+										ALU160_SEL = 1;				// pc
+										DINW_SEL = 1;					// DI
+										WE 		= 6'b010x01;		// PC, lo
+										next_stage = 1;
+										REG_WSEL	= 4'b011x;			// tmpLO
+										M1 		= 0;
+									end
+									2'b01: begin		// stage2 - IN
+										ALU160_SEL = 0;				// regs
+										DINW_SEL = 1;					// DI
+										WE 		= 6'b000x1x;		// hi
+										next_stage = 1;
+										REG_WSEL	= 4'b011x;			// A
+										REG_RSEL	= 4'b011x;			// A - tmpLO
+										M1 		= 0;
+										MREQ		= 0;
+										IORQ		= 1;
+									end
+									2'b10: begin		// stage3 - fetch
+										ALU160_SEL = 1;			// PC
+										WE 		= 6'b010x00;	// PC
+									end
+								endcase
+							2'b10: begin			// EX DE, HL
+								ALU160_SEL = 1;			// PC
+								WE 		= 6'b010x00;	// PC
+								if(CPUStatus[1]) status[3] = 1;	
+								else status[2] = 1;
+							end
+							2'b11: begin			// EI
+								ALU160_SEL = 1;			// PC
+								WE 		= 6'b010x00;	// PC
+								status[11] = 1'b1;
+								status[7:6] = 2'b11;
+							end
+						endcase
+//				-----------------------		CALL , IX, ED, IY --------------------
+					4'b1101:	
+						case(FETCH[5:4])
+							2'b00: 					// CALL
+								case(STAGE[2:0])
+									3'b000, 3'b001: begin		// stage 1,2 - load addr
+										ALU160_SEL = 1;					// pc
+										DINW_SEL = 1;						// DI
+										WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};		// PC, hi/lo
+										next_stage = 1;
+										REG_WSEL	= 4'b111x;				// tmp7
+										M1 		= 0;
+									end
+									3'b010, 3'b011: begin		// stage 3,4 - push pc
+										DO_SEL	= {1'b0, STAGE[0]};	// pc hi/lo
+										ALU160_SEL = 0;					// regs
+										WE 		= 6'b001x00;			// SP
+										ALU16OP	= 5;						// DEC
+										next_stage = 1;
+										REG_WSEL	= 4'b1xxx;				// pc
+										REG_RSEL	= 4'b101x;				// sp
+										M1 		= 0;
+										WR			= 1;
+									end
+									3'b100:	begin	// stage5 - jump
+										ALU160_SEL = 0;					// regs
+										WE 		= 6'b010x00;			// PC
+										REG_RSEL	= 4'b111x;				// tmp7
+									end
+								endcase
+							2'b01: begin			// DD - IX
+								ALU160_SEL = 1;			// PC
+								WE 		= 6'b010x00;	// PC
+								status[5:4] = 2'b01;
+							end
+							2'b10: begin			// ED prefix
+								ALU160_SEL = 1;			// PC
+								WE 		= 6'b010x00;	// PC
+								fetch98 = 2'b01;		
+							end
+							2'b11:	begin			// FD - IY
+								ALU160_SEL = 1;			// PC
+								WE 		= 6'b010x00;	// PC
+								status[5:4]	= 2'b11;	
+							end
+						endcase
+				endcase
+
+//	------------------------------------------- ED + opcode ----------------------------------------------------
+			4'b0100, 4'b0111: begin		// ED + 2'b00, ED + 2'b11 		= NOP
+				ALU160_SEL = 1;			// PC
+				WE 		= 6'b010x00;	// PC
+			end
+			4'b0101:
+				case(FETCH[2:0])
+//				-----------------------		in r (C)  --------------------
+					3'b000:
+						if(!STAGE[0]) begin
+							ALU160_SEL = 0;					// regs
+							DINW_SEL = 1;						// DI
+							WE 		= {4'b000x, !opd[3], opd[3]} ;	// hi/lo
+							next_stage = 1;
+							REG_WSEL	= {1'b0, opd[5:4], 1'bx};
+							REG_RSEL	= 4'b000x;				// BC
+							M1 		= 0;
+							MREQ		= 0;
+							IORQ 		= 1;
+						end else begin
+							ALU160_SEL = 1;					// pc
+							WE 		= 6'b110x00;			// flags, PC
+							ALU8OP	= 29;						// IN
+							REG_RSEL	= {1'b0, opd[5:3]};	// reg
+						end
+//				-----------------------		out (C) r  --------------------
+					3'b001:
+						if(!STAGE[0]) begin
+							DO_SEL	= 2'b00;					// ALU80
+							ALU160_SEL = 0;					// regs
+							WE 		= 6'b000x00;			// nothing
+							next_stage = 1;
+							REG_WSEL	= &opd[5:3] ? 4'b110x : {1'b0, opd[5:3]}; // zero/reg
+							REG_RSEL	= 4'b000x;				// BC
+							M1 		= 0;
+							MREQ		= 0;
+							WR			= 1;
+							IORQ 		= 1;
+						end else begin
+							ALU160_SEL = 1;					// pc
+							WE 		= 6'b010x00;			// PC
+						end
+//				-----------------------		SBC16, ADC16  --------------------
+					3'b010:
+						if(!STAGE[0]) begin			// stage1
+							DINW_SEL = 0;						// ALU8OUT
+							WE 		= 6'b100x01;			// flags, lo
+							ALU8OP	= {3'b000, !FETCH[3], 1'b1};	// SBC/ADC
+							next_stage = 1;
+							REG_WSEL	= 4'b0101;				// L			
+							REG_RSEL	= {op16, 1'b1};
+							M1 		= 0;
+							MREQ		= 0;
+						end else begin
+							ALU160_SEL = 1;					// pc
+							DINW_SEL = 0;						// ALU8OUT
+							WE 		= 6'b110x10;			// flags, PC, hi
+							ALU8OP	= {3'b000, !FETCH[3], 1'b1};
+							REG_WSEL	= 4'b0100;				// H
+							REG_RSEL	= {op16, 1'b0};
+						end
+//				-----------------------		LD (nn) r16, ld r16 (nn)  --------------------
+					3'b011:
+						case(STAGE[2:1])
+							2'b00:	begin // stage 1,2 - read address
+								ALU160_SEL = 1;				// pc
+								DINW_SEL = 1;					// DI
+								WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};	// PC, hi/lo
+								next_stage = 1;
+								REG_WSEL	= 4'b111x;			// tmp16
+								M1 		= 0;
+							end
+							2'b01: begin
+								ALU160_SEL = 0;			// regs
+								next_stage = 1;
+								ALU16OP	= {2'b00, STAGE[0]};				
+								REG_RSEL	= 4'b111x;		// tmp16
+								REG_WSEL	= {op16, !STAGE[0]};
+								M1 		= 0;
+								if(FETCH[3]) begin	// LD rr, (nn) - stage3,4
+									DINW_SEL = 1;				// DI
+									WE 		= {4'b000x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};	// lo
+								end else begin			// LD (nn), rr - stage3,4
+									DO_SEL	= op16[2] ? {1'b1, !STAGE[0]} : 2'b00;				// ALU80/sp
+									WE 		= 6'b000x00;		// nothing
+									WR			= 1;
+								end
+							end
+							2'b10:		// stage5 
+								if(FETCH[3] & op16[2] & !STAGE[0]) begin	// LD sp, (nn) - stage5
+									ALU160_SEL = 0;					// regs
+									WE 		= 6'b001x00;			// SP
+									ALU16OP	= 4;						// NOP
+									next_stage = 1;
+									REG_RSEL	= 4'b101x;				// tmp SP
+									M1 		= 0;
+									MREQ		= 0;
+								end else begin
+									ALU160_SEL = 1;					// pc
+									WE 		= 6'b010x00;			// PC
+								end
+							endcase
+//				-----------------------		NEG  --------------------
+					3'b100: begin
+						ALU160_SEL = 1;					// pc
+						DINW_SEL = 0;						// ALU8OUT
+						WE 		= 6'b110x10;			// flags, PC, hi
+						ALU8OP	= 5'b11111;				// NEG
+						REG_WSEL	= 4'b011x;				// A
+						REG_RSEL	= 4'b0110;				// A
+					end
+//				-----------------------		RETN, RETI  --------------------
+					3'b101:
+						case(STAGE[1:0])
+							2'b00, 2'b01:	begin		// stage1, stage2 - pop addr
+								ALU160_SEL = 0;				// regs
+								DINW_SEL = 1;					// DI
+								WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};		// SP, lo/hi
+								next_stage = 1;
+								REG_WSEL	= 4'b111x;			// tmp16
+								REG_RSEL	= 4'b101x;			// SP
+								M1 		= 0;
+							end		
+							2'b10: begin			// stage3 - jump
+								ALU160_SEL = 0;					// regs
+								WE 		= 6'b010x00;			// PC
+								REG_RSEL	= 4'b111x;				// tmp16
+								status[11] = 1'b1;
+								status[7:6] = {CPUStatus[7], CPUStatus[7]};
+							end
+						endcase
+//				-----------------------		IM  --------------------
+					3'b110: begin
+						ALU160_SEL = 1;					// PC
+						WE 		= 6'b010x00;			// PC
+						status[10:8] = {1'b1, FETCH[4:3]};
+					end
+//				-----------------------		LD I A, LD R A, LD A I, LD A R, RRD, RLD  --------------------
+					3'b111:
+						case(FETCH[5:4])
+							2'b00: begin	// LD I/R A
+								ALU160_SEL = 1;					// pc
+								DINW_SEL = 1'b0;					// ALU8OUT
+								WE 		= {4'b010x, !FETCH[3], FETCH[3]};	// PC, hi/lo
+								ALU8OP	= 29;						// pass D1
+								REG_WSEL	= 4'b1001;				// IR, write r
+								REG_RSEL	= 4'b0110;				// A
+							end
+							2'b01: begin	// LD A I/R
+								ALU160_SEL = 1;					// pc
+								DINW_SEL = 1'b0;					// ALU8OUT
+								WE 		= 6'b110x1x;			// flags, PC, hi
+								ALU8OP	= 29;						// PASS D1
+								REG_WSEL	= 4'b011x;				// A
+								REG_RSEL	= {3'b100, FETCH[3]};// I/R
+							end
+							2'b10: 			// RRD, RLD
+								case(STAGE[1:0])
+									2'b00:begin		// stage1, read data
+										ALU160_SEL = 0;					// regs
+										DINW_SEL = 1;						// DI
+										WE 		= 6'b000x01;			// lo
+										next_stage = 1;
+										REG_WSEL	= 4'b011x;				// tmpLO
+										REG_RSEL	= 4'b010x;				// HL
+										M1 		= 0;
+									end
+									2'b01: begin	// stage2, shift data
+										DINW_SEL = 0;						// ALU8OUT
+										WE 		= 6'b100x11;			// flags, hi, lo
+										ALU8OP	= FETCH[3] ? 5'b01100 : 5'b01011;	// RRD/RLD
+										next_stage = 1;
+										REG_WSEL	= 4'b0110;				// A
+										REG_RSEL	= 4'b0111;				// tmpLO
+										M1 		= 0;
+										MREQ		= 0;
+									end
+									2'b10: begin // stage3 - write
+										DO_SEL	= 2'b00;					// ALU80
+										ALU160_SEL = 0;					// regs
+										WE 		= 6'b000x0x;			// nothing
+										next_stage = 1;
+										REG_WSEL	= 4'b0111;				// tmpLO
+										REG_RSEL	= 4'b010x;				// HL
+										M1 		= 0;
+										WR			= 1;
+									end
+									2'b11: begin
+										ALU160_SEL = 1;					// PC
+										WE 		= 6'b010x00;			// PC
+									end
+								endcase
+							2'b11: begin	// NOP
+								ALU160_SEL = 1;					// PC
+								WE 		= 6'b010x00;			// PC
+							end
+						endcase
+				endcase
+//				-----------------------		block instructions  --------------------
+			4'b0110:
+				if({FETCH[5], FETCH[2]} == 4'b10)
+					case(FETCH[1:0])
+						2'b00:	// LDI, LDD, LDIR, LDDR
+							case(STAGE[1:0])
+								2'b00:	begin			// stage1, read data, inc/dec HL
+									ALU160_SEL = 0;					// regs
+									DINW_SEL = 0;						// ALU8OUT
+									WE 		= 6'b100111;			// flags, tmpHI, hi, lo
+									ALU8OP	= {4'b0111, FETCH[3]};	// INC/DEC16
+									next_stage = 1;
+									REG_WSEL	= 4'b0100;				// H
+									REG_RSEL	= 4'b0101;				// L
+									M1 		= 0;
+								end
+								2'b01:	begin			// stage2, dec BC
+									DINW_SEL = 0;						// ALU8OUT
+									WE 		= 6'b100011;			// flags, hi, lo (affects PF only)
+									ALU8OP	= 5'b01111;				// DEC
+									next_stage = 1;
+									REG_WSEL	= 4'b0000;				// B
+									REG_RSEL	= 4'b0001;				// C
+									M1 		= 0;
+									MREQ		= 0;
+								end
+								2'b10:	begin			// stage2, write data, inc/dec DE
+									DO_SEL	= 2'b01;					// th
+									ALU160_SEL = 0;					// regs
+									DINW_SEL = 0;						// ALU8OUT
+									WE 		= 6'b000x11;			// hi, lo
+									ALU8OP	= {4'b0111, FETCH[3]};	// INC / DEC
+									next_stage = FETCH[4] ? !FLAGS[2] : 1'b1;
+									REG_WSEL	= 4'b0010;				// D
+									REG_RSEL	= 4'b0011;				// E
+									M1 		= 0;
+									WR			= 1;
+								end
+								2'b11: begin
+									ALU160_SEL = 1;					// PC
+									WE 		= 6'b010x00;			// PC
+								end
+							endcase
+						2'b01:	// CPI, CPD, CPIR, CPDR
+							case(STAGE[1:0])
+								2'b00: begin			// stage1, load data
+									ALU160_SEL = 0;					// regs
+									DINW_SEL = 1;						// DI
+									WE 		= 6'b000x01;			// lo
+									next_stage = 1;
+									REG_WSEL	= 4'b011x;				// tmpLO
+									REG_RSEL	= 4'b010x;				// HL
+									M1 		= 0;
+								end
+								2'b01: begin			// stage2, CP
+									WE 		= 6'b100x0x;			// flags
+									ALU8OP	= 7;						// CP
+									next_stage = 1;
+									REG_WSEL	= 4'b0110;				// A
+									REG_RSEL	= 4'b0111;				// tmpLO
+									M1 		= 0;
+									MREQ		= 0;
+								end
+								2'b10: begin			// stage3, dec BC
+									DINW_SEL = 0;						// ALU8OUT
+									WE 		= 6'b100x11;			// flags, hi, lo
+									ALU8OP	= 5'b01111;				// DEC16
+									next_stage = 1;
+									REG_WSEL	= 4'b0000;				// B
+									REG_RSEL	= 4'b0001;				// C
+									M1 		= 0;
+									MREQ		= 0;
+								end
+								2'b11: begin			// stage4, inc/dec HL
+									ALU160_SEL = 1;					// pc
+									DINW_SEL = 0;						// ALU8OUT
+									M1 		= FETCH[4] ? (!FLAGS[2] || FLAGS[6]) : 1'b1;
+									WE 		= {1'b0, M1, 4'b0x11};	// PC, hi, lo
+									ALU8OP	= {4'b0111, FETCH[3]};	// INC / DEC
+									REG_WSEL	= 4'b0100;				// H
+									REG_RSEL	= 4'b0101;				// L
+									MREQ		= M1;
+								end
+							endcase
+						2'b10:	// INI, IND, INIR, INDR
+							case(STAGE[1:0])
+								2'b00: 	begin			// stage1, in data, dec B
+									ALU160_SEL = 0;					// regs
+									DINW_SEL = 0;						// ALU8OUT
+									WE 		= 6'b100110;			// flags, tmpHI, hi
+									ALU8OP	= 10;						// DEC
+									next_stage = 1;
+									REG_WSEL	= 4'b0000;				// B
+									REG_RSEL	= 4'b000x;				// BC
+									M1 		= 0;
+									MREQ		= 0;
+									IORQ		= 1;
+								end
+								2'b01:	begin			// stage2, write data, inc/dec HL
+									DO_SEL	= 2'b01;					// th
+									ALU160_SEL = 0;					// regs
+									DINW_SEL = 0;						// ALU8OUT
+									WE 		= 6'b000x11;			// hi, lo
+									ALU8OP	= {4'b0111, FETCH[3]};	// INC / DEC
+									next_stage = FETCH[4] ? FLAGS[6] : 1'b1;
+									REG_WSEL	= 4'b0100;				// H
+									REG_RSEL	= 4'b0101;				// L
+									M1 		= 0;
+									WR			= 1;
+								end
+								2'b10:	begin			// stage3
+									ALU160_SEL = 1;					// pc
+									WE 		= 6'b010x00;			// PC
+								end
+							endcase
+						2'b11:	// OUTI/OUTD/OTIR/OTDR
+							case(STAGE[1:0])
+								2'b00:	begin			// stage1, load data, inc/dec HL
+									ALU160_SEL = 0;					// regs
+									DINW_SEL = 0;						// ALU8OUT
+									WE 		= 6'b000111;			// tmpHI, hi, lo
+									ALU8OP	= {4'b0111, FETCH[3]};	// INC / DEC
+									next_stage = 1;
+									REG_WSEL	= 4'b0100;				// H
+									REG_RSEL	= 4'b0101;				// L
+									M1 		= 0;
+								end
+								2'b01: 	begin			// stage2, out data, dec B
+									DO_SEL	= 2'b01;					// th
+									ALU160_SEL = 0;					// regs
+									DINW_SEL = 0;						// ALU8OUT
+									WE 		= 6'b100x10;			// flags, hi
+									ALU8OP	= 10;						// DEC
+									next_stage = FETCH[4] ? (ALU80 == 8'b00000001) : 1'b1;
+									REG_WSEL	= 4'b0000;				// B
+									REG_RSEL	= 4'b000x;				// BC
+									M1 		= 0;
+									MREQ		= 0;
+									IORQ		= 1;
+									WR			= 1;
+								end
+								2'b10:	begin			// stage3
+									ALU160_SEL = 1;					// pc
+									WE 		= 6'b010x00;			// PC
+								end
+							endcase
+					endcase
+				else begin			// NOP
+					ALU160_SEL = 1;					// PC
+					WE 		= 6'b010x00;			// PC
+				end
+//------------------------------------------- CB + opcode ----------------------------------------------------
+			4'b1000, 4'b1001, 4'b1010, 4'b1011:										// CB class (rot/shift, bit/res/set)
+				case({STAGE[1:0], CPUStatus[4], op0mem})				
+					4'b00_0_0: begin						// execute reg-reg
+						DINW_SEL = 0;						// ALU8OUT
+						ALU160_SEL = 1;					// pc
+						WE 		= {!FETCH[7], 3'b10x, FETCH[7:6] == 2'b01 ? 2'b00 : {!opd[0], opd[0]}};	// flags, hi/lo
+						ALU8OP	= 28;					// BIT
+						REG_WSEL	= {1'b0, opd[2:0]};
+					end
+					4'b00_0_1, 4'b00_1_0, 4'b00_1_1: begin				// stage1, (HL-X) - read data
+						ALU160_SEL = 0;				// regs
+						DINW_SEL = 1;					// DI
+						WE 		= opd[0] ? 6'b000001 : 6'b000010;	// lo/hi
+						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;					// ADD - NOP
+						next_stage = 1;
+						REG_WSEL = FETCH[7:6] == 2'b01 ? 4'b111x : {1'b0, opd[2:0]};	// dest, tmp16 for BIT
+						REG_RSEL	= 4'b010x;			// HL
+						M1 		= 0;
+					end
+					4'b01_0_1, 4'b01_1_0, 4'b01_1_1:		// stage2 (HL-X) - execute, write
+						case(FETCH[7:6])
+							2'b00, 2'b10, 2'b11: begin		// exec + write
+								DINW_SEL = 0;					// ALU8OUT
+								DO_SEL	= 2'b11;				// ALU8OUT[7:0]
+								ALU160_SEL = 0;				// regs
+								WE 		= {!FETCH[7], 3'b00x, !opd[0], opd[0]};	// flags, hi/lo
+								ALU8OP	= 28;
+								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
+								next_stage = 1;
+								REG_WSEL	= {1'b0, opd[2:0]};
+								REG_RSEL	= 4'b010x;				// HL
+								M1 		= 0;
+								WR			= 1;
+							end
+							2'b01: begin							// BIT, no write
+								ALU160_SEL = 1;					// pc
+								WE 		= 6'b110xxx;			// flags, PC
+								ALU8OP	= 28;						// BIT
+								REG_WSEL	= {3'b111, opd[0]};	// tmp
+							end 
+						endcase
+					4'b10_0_1, 4'b10_1_0, 4'b10_1_1: begin	// (HL-X) - load next op
+						ALU160_SEL = 1;							// pc
+						WE 		= 6'b010x00;					// PC
+					end
+				endcase
+//------------------------------------------- // RST, NMI, INT ----------------------------------------------------
+			4'b1110: begin 			// RESET: IR <- 0, IM <- 0, IFF1,IFF2 <- 0, pC <- 0
+					ALU160_SEL = 0;					// regs
+					DINW_SEL = 0;						// ALU8OUT
+					WE 		= 6'bx1xx11;			// PC, hi, lo
+					ALU8OP	= 29;						// pass D1
+					ALU16OP	= 4;						// NOP
+					REG_WSEL	= 4'b1001;				// IR, write r
+					REG_RSEL	= 4'b110x;				// const
+					M1 		= 0;
+					MREQ		= 0;
+					status[11:6] = 6'b110000;		// IM0, DI
+				end 
+			4'b1101:						// NMI
+				case(STAGE[1:0])
+					2'b00: begin		
+						ALU160_SEL = 1;				// pc
+						WE 		= 6'b010x00;		// PC
+						ALU16OP	= intop;				// DEC/DEC2 (if block instruction interrupted)
+						next_stage = 1;
+						M1 		= 0;
+						MREQ		= 0;
+					end
+					2'b01, 2'b10: begin
+						DO_SEL	= {1'b0, !STAGE[0]};	// pc hi/lo
+						ALU160_SEL = 0;					// regs
+						WE 		= 6'b001x00;			// SP
+						ALU16OP	= 5;						// DEC
+						next_stage = 1;
+						REG_WSEL	= 4'b1xxx;				// pc
+						REG_RSEL	= 4'b101x;				// sp
+						M1 		= 0;
+						WR			= 1;
+						status[11]	= 1'b1;
+						status[7:6] = {CPUStatus[7], 1'b0};	// reset IFF1
+					end
+					2'b11: begin
+						ALU160_SEL = 0;					// regs
+						WE 		= 6'b010x00;			// PC
+						REG_RSEL	= 4'b110x;				// const
+					end
+				endcase
+			4'b1100:				// INT
+				case(CPUStatus[9:8])
+					2'b00, 2'b01, 2'b10: begin		// IM0, IM1	
+						ALU160_SEL = 1;					// pc
+						WE 		= 6'b010x00;			// PC
+						ALU16OP	= intop;					// DEC/DEC2 (if block instruction interrupted)
+						MREQ		= 0;
+						IORQ		= 1;
+						status[11]	= 1'b1;
+						status[7:6] = 2'b0;				// reset IFF1, IFF2
+					end
+					2'b11: 								// IM2
+						case(STAGE[2:0])
+							3'b000: begin
+								ALU160_SEL = 1;				// pc
+								DINW_SEL = 1;					// DI
+								WE 		= 6'b010x01;		// PC, lo
+								ALU16OP	= intop;				// DEC/DEC2 (if block instruction interrupted)
+								next_stage = 1;
+								REG_WSEL	= 4'b1000;			// Itmp, no write r
+								MREQ		= 0;
+								IORQ		= 1;
+								status[11]	= 1'b1;
+								status[7:6] = 2'b0;			// reset IFF1, IFF2
+							end
+							3'b001, 3'b010: begin			// push pc
+								DO_SEL	= {1'b0, !STAGE[0]};	// pc hi/lo
+								ALU160_SEL = 0;					// regs
+								WE 		= 6'b001x00;			// SP
+								ALU16OP	= 5;						// DEC
+								next_stage = 1;
+								REG_WSEL	= 4'b1xxx;				// pc
+								REG_RSEL	= 4'b101x;				// sp
+								M1 		= 0;
+								WR			= 1;
+							end
+							3'b011, 3'b100:	begin			// read address
+								ALU160_SEL = 0;					// regs
+								DINW_SEL = 1;						// DI
+								WE 		= {4'b0x0x, STAGE[0] ? 1'bx : 1'b1, STAGE[0]};				// hi/lo
+								ALU16OP	= {2'b00, !STAGE[0]};// NOP/INC
+								next_stage = 1;
+								REG_WSEL	= 4'b111x;				// tmp16
+								REG_RSEL	= 4'b1000;				// I-Itmp
+								M1 		= 0;
+							end
+							3'b101: begin						// jump
+								ALU160_SEL = 0;					// regs
+								WE 		= 6'b010x00;			// PC
+								REG_RSEL	= 4'b111x;				// tmp16
+							end
+						endcase
+				endcase
+		endcase	
+	end
+
+endmodule
diff --git a/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80Reg.v b/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80Reg.v
new file mode 100644
index 00000000..65d99661
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80Reg.v
@@ -0,0 +1,199 @@
+//////////////////////////////////////////////////////////////////////////////////
+//
+// This file is part of the NextZ80 project
+// http://www.opencores.org/cores/nextz80/
+//
+// Filename: NextZ80Regs.v
+// Description: Implementation of Z80 compatible CPU - registers
+// Version 1.0
+// Creation date: 28Jan2011 - 18Mar2011
+//
+// Author: Nicolae Dumitrache 
+// e-mail: ndumitrache@opencores.org
+//
+/////////////////////////////////////////////////////////////////////////////////
+// 
+// Copyright (C) 2011 Nicolae Dumitrache
+// 
+// This source file may be used and distributed without 
+// restriction provided that this copyright statement is not 
+// removed from the file and that any derivative work contains 
+// the original copyright notice and the associated disclaimer.
+// 
+// This source file is free software; you can redistribute it 
+// and/or modify it under the terms of the GNU Lesser General 
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any 
+// later version. 
+// 
+// This source is distributed in the hope that it will be 
+// useful, but WITHOUT ANY WARRANTY; without even the implied 
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
+// PURPOSE. See the GNU Lesser General Public License for more 
+// details. 
+// 
+// You should have received a copy of the GNU Lesser General 
+// Public License along with this source; if not, download it 
+// from http://www.opencores.org/lgpl.shtml 
+// 
+///////////////////////////////////////////////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module Z80Reg(
+	input wire [7:0]rstatus,	// 0=af-af', 1=exx, 2=hl-de, 3=hl'-de',4=hl-ixy, 5=ix-iy, 6=IFF1, 7=IFF2
+	input wire M1,
+	input wire [5:0]WE,			// 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo
+	input wire CLK,
+	input wire [15:0]ALU8OUT,	// CPU data out bus (output of alu8)
+	input wire [7:0]DI,			// CPU data in bus
+	output reg [7:0]DO,			// CPU data out bus
+	input wire [15:0]ADDR,		// CPU addr bus
+	input wire [7:0]CONST,
+	output reg [7:0]ALU80,
+	output reg [7:0]ALU81,
+	output reg [15:0]ALU160,
+	output wire[7:0]ALU161,
+	input wire [7:0]ALU8FLAGS,			
+	output wire [7:0]FLAGS,
+	
+	input wire [1:0]DO_SEL,		// select DO betwen ALU8OUT lo and th register
+	input wire ALU160_sel,		// 0=REG_RSEL, 1=PC
+	input wire [3:0]REG_WSEL,	// rdow:    	[3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-x  ----- [0] = 0HI,1LO
+	input wire [3:0]REG_RSEL,	// mux_rdor:   [3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-R, 5=SP, 7=tmpSP   ----- [0] = 0HI, 1LO
+	input wire DINW_SEL,			// select RAM write data between (0)ALU8OUT, and 1(DI)
+	input wire XMASK,				// 0 if REG_WSEL should not use IX, IY, even if rstatus[4] == 1
+	input wire [2:0]ALU16OP,	// ALU16OP
+	input wire WAIT				// wait
+	);
+	
+// latch registers
+	reg [15:0]pc=0;				// program counter
+	reg [15:0]sp;					// stack pointer
+	reg [7:0]r;						// refresh
+	reg [15:0]flg = 0;
+	reg [7:0]th;					// temp high
+
+// internal wires	
+	wire [15:0]rdor;		// R out from RAM
+	wire [15:0]rdow;		// W out from RAM
+	wire [3:0]SELW;		// RAM W port sel
+	wire [3:0]SELR;		// RAM R port sel
+	reg  [15:0]DIN;		// RAM W in data
+	reg [15:0]mux_rdor;	// (3)A reversed mixed with TL, (4)I mixed with R (5)SP
+	
+//------------------------------------ RAM block registers ----------------------------------
+// 0:BC, 1:DE, 2:HL, 3:A-x, 4:I-x, 5:IX, 6:IY, 7:x-x, 8:BC', 9:DE', 10:HL', 11:A'-x, 12: tmpSP, 13:zero
+   RAM16X8D_regs regs_lo (
+      .DPO(rdor[7:0]),   // Read-only data output
+      .SPO(rdow[7:0]),   // R/W data output
+      .A(SELW),       	 // R/W address
+      .D(DIN[7:0]),      // Write data input
+      .DPRA(SELR), 		 // Read-only address
+      .WCLK(CLK),   		 // Write clock input
+      .WE(WE[0] & !WAIT) // Write enable input
+   );
+
+   RAM16X8D_regs regs_hi (
+      .DPO(rdor[15:8]),  // Read-only data output
+      .SPO(rdow[15:8]),  // R/W data output
+      .A(SELW),       	 // R/W address
+      .D(DIN[15:8]),     // Write data input
+      .DPRA(SELR), 		 // Read-only address
+      .WCLK(CLK),   		 // Write clock input
+      .WE(WE[1] & !WAIT) // Write enable input
+   );
+
+	wire [15:0]ADDR1 = ADDR + !ALU16OP[2]; // address post increment
+	wire [7:0]flgmux = {ALU8FLAGS[7:3], SELR[3:0] == 4'b0100 ? rstatus[7] : ALU8FLAGS[2], ALU8FLAGS[1:0]}; // LD A, I/R IFF2 flag on parity
+	always @(posedge CLK)
+		if(!WAIT) begin
+			if(WE[2]) th <= DI;
+			if(WE[3]) sp <= ADDR1;
+			if(WE[4]) pc <= ADDR1;
+			if({REG_WSEL, WE[0]} == 5'b10011) r <= ALU8OUT[7:0]; 
+			else if(M1) r[6:0] <= r[6:0] + 1;
+			if(WE[5])
+				if(rstatus[0]) flg[15:8] <= flgmux;
+				else flg[7:0] <= flgmux;
+		end
+	
+	assign ALU161 = th;
+	assign FLAGS = rstatus[0] ? flg[15:8] : flg[7:0];
+	
+	always @* begin
+		DIN = DINW_SEL ? {DI, DI} : ALU8OUT;
+		ALU80 = REG_WSEL[0] ? rdow[7:0] : rdow[15:8];
+		ALU81 = REG_RSEL[0] ? mux_rdor[7:0] : mux_rdor[15:8];
+		ALU160 = ALU160_sel ? pc : mux_rdor;
+	
+		case({REG_WSEL[3], DO_SEL})
+			0:	DO = ALU80;
+			1:	DO = th;
+			2: DO = FLAGS;
+			3: DO = ALU8OUT[7:0];
+			4: DO = pc[15:8];
+			5: DO = pc[7:0];
+			6:	DO = sp[15:8];
+			7: DO = sp[7:0];
+		endcase
+		case({ALU16OP == 4, REG_RSEL[3:0]})
+			5'b01001, 5'b11001:								mux_rdor = {rdor[15:8], r};
+			5'b01010, 5'b01011: 								mux_rdor = sp;
+			5'b01100, 5'b01101, 5'b11100, 5'b11101:	mux_rdor = {8'b0, CONST};
+			default:		mux_rdor = rdor;
+		endcase 
+	end
+	
+	RegSelect WSelectW(.SEL(REG_WSEL[3:1]), .RAMSEL(SELW), .rstatus({rstatus[5], rstatus[4] & XMASK, rstatus[3:0]}));
+	RegSelect WSelectR(.SEL(REG_RSEL[3:1]), .RAMSEL(SELR), .rstatus(rstatus[5:0]));
+
+endmodule
+
+
+module RegSelect(
+	input [2:0]SEL,
+	output reg [3:0]RAMSEL,
+	input [5:0]rstatus			// 0=af-af', 1=exx, 2=hl-de, 3=hl'-de',4=hl-ixy, 5=ix-iy
+	);
+	
+	always @* begin
+		RAMSEL = 4'bxxxx;
+		case(SEL)
+			0: RAMSEL = {rstatus[1], 3'b000};	// BC
+			1:  //DE
+				if(rstatus[{1'b1, rstatus[1]}]) RAMSEL = {rstatus[1], 3'b010};		//	HL
+				else RAMSEL = {rstatus[1], 3'b001};				// DE
+			2:	// HL
+				case({rstatus[5:4], rstatus[{1'b1, rstatus[1]}]})
+					0,4: 	RAMSEL = {rstatus[1], 3'b010}; 		// HL
+					1,5: 	RAMSEL = {rstatus[1], 3'b001};		// DE
+					2,3:	RAMSEL = 4'b0101;  	//	IX
+					6,7:	RAMSEL = 4'b0110;		// IY
+				endcase
+			3: RAMSEL = {rstatus[0], 3'b011}; // A-TL
+			4:	RAMSEL = 4; // I-R
+			5: RAMSEL = 12;	// tmp SP
+			6: RAMSEL = 13;	// zero
+			7: RAMSEL = 7;	// temp reg for BIT/SET/RES
+		endcase
+	end
+endmodule	
+
+module RAM16X8D_regs(
+      output [7:0]DPO,     // Read-only data output
+      output [7:0]SPO,     // R/W data output
+      input [3:0]A,       	// R/W address 
+      input [7:0]D,        // Write data input
+      input [3:0]DPRA, 		// Read-only address
+      input WCLK,   			// Write clock
+      input WE        		// Write enable
+   );
+	
+	reg [7:0]data[15:0];
+	assign DPO = data[DPRA];
+	assign SPO = data[A];
+	
+	always @(posedge WCLK)
+		if(WE) data[A] <= D;		
+
+endmodule
diff --git a/Computer_MiST/Laser310_MiST/rtl/PIXEL_DISPLAY.v b/Computer_MiST/Laser310_MiST/rtl/PIXEL_DISPLAY.v
new file mode 100644
index 00000000..585fea04
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/PIXEL_DISPLAY.v
@@ -0,0 +1,296 @@
+module PIXEL_DISPLAY (
+	pixel_clock,
+	reset,
+
+	show_border,
+
+	// mode
+	ag,
+	gm,
+	css,
+
+	// text
+	char_column,
+	char_line,
+	subchar_line,
+	subchar_pixel,
+
+	// graph
+	graph_pixel,
+	graph_line_2x,
+	graph_line_3x,
+
+	// vram
+	vram_rd_enable,
+	vram_addr,
+	vram_data,
+
+	// vga
+	vga_red,
+	vga_green,
+	vga_blue
+);
+
+input					pixel_clock;
+input					reset;
+
+input					show_border;
+
+// mode
+input					ag;
+input			[2:0]	gm;
+input					css;
+
+// text
+input			[6:0]	char_column;		// character number on the current line
+input			[6:0]	char_line;			// line number on the screen
+input			[4:0]	subchar_line;		// the line number within a character block 0-8
+input			[3:0]	subchar_pixel;		// the pixel number within a character block 0-8
+
+// graph
+input			[8:0]	graph_pixel;		// pixel number on the current line
+input			[9:0]	graph_line_2x;		// line number on the screen
+input			[9:0]	graph_line_3x;		// line number on the screen
+
+output					vram_rd_enable;
+output	reg		[12:0]	vram_addr;
+input			[7:0] 	vram_data;
+
+output			[7:0]	vga_red;
+output			[7:0]	vga_green;
+output			[7:0]	vga_blue;
+
+
+//// Label Definitions ////
+
+// Note: all labels must match their defined length--shorter labels will be padded with solid blocks,
+// and longer labels will be truncated
+
+// 48 character label for the example text
+
+wire				pixel_on;					// high => output foreground color, low => output background color
+
+
+// 8p   代表每个点占用VGA水平 8 pixel
+// 2bit 代表每个点取2位值
+
+wire	[1:0]		pixel_8p_2bit;				// high => output foreground color, low => output background color
+wire	[1:0]		pixel_4p_2bit;				// high => output foreground color, low => output background color
+wire				pixel_4p_1bit;				// high => output foreground color, low => output background color
+wire				pixel_2p_1bit;				// high => output foreground color, low => output background color
+
+reg		[7:0] 		latched_vram_data;			// the data that will be written to character memory at the clock rise
+
+// 锁存数据用于选择调色板
+reg		[7:0] 		latched_palette_data;
+
+assign vram_rd_enable = pixel_clock;
+
+reg		[23:0] latched_vga_rgb;
+wire	[23:0] vga_rgb;
+
+// write the appropriate character data to memory
+
+always @ (posedge pixel_clock) begin
+	if(ag==1'b0)
+	begin
+			if(subchar_pixel==4'b0001)
+				vram_addr <= {4'b0,char_line[3:0], char_column[4:0]};
+			// 对于同步sram需要等待 1 个时钟周期
+			if(subchar_pixel==4'b0011)
+				latched_vram_data <= vram_data;
+			if(graph_pixel[3:0]==4'b0110)
+				latched_palette_data <= latched_vram_data;
+	end
+	else
+	begin
+		case(gm)
+		3'b000:
+		begin
+			// 64 x 64 x 4	gm: 000
+			if(graph_pixel[4:0]==5'b00001)
+				vram_addr <= {3'b0, graph_line_3x[9:4], graph_pixel[8:5]};
+			// 对于同步sram需要等待 1 个时钟周期
+			if(graph_pixel[4:0]==5'b00011)
+				latched_vram_data <= vram_data;
+		end
+		3'b001:
+		begin
+			// 128 x 64 x 2	gm: 001
+			if(graph_pixel[4:0]==5'b00001)
+				vram_addr <= {3'b0, graph_line_3x[9:4], graph_pixel[8:5]};
+			// 对于同步sram需要等待 1 个时钟周期
+			if(graph_pixel[4:0]==5'b00011)
+				latched_vram_data <= vram_data;
+		end
+		3'b011:
+		begin
+			// 128 x 96 x 2	gm: 011
+			if(graph_pixel[4:0]==5'b00001)
+				vram_addr <= {2'b0, graph_line_2x[9:3], graph_pixel[8:5]};
+			// 对于同步sram需要等待 1 个时钟周期
+			if(graph_pixel[4:0]==5'b00011)
+				latched_vram_data <= vram_data;
+		end
+		3'b100:
+		begin
+			// 128 x 96 x 4	gm: 100
+			if(graph_pixel[3:0]==4'b0001)
+				vram_addr <= {1'b0, graph_line_2x[8:1], graph_pixel[8:4]};
+			// 对于同步sram需要等待 1 个时钟周期
+			if(graph_pixel[3:0]==4'b0011)
+				latched_vram_data <= vram_data;
+		end
+		3'b101:
+		begin
+			// 128 x 192 x 2	gm: 101
+			if(graph_pixel[4:0]==5'b00001)
+				vram_addr <= {1'b0, graph_line_2x[9:1], graph_pixel[8:5]};
+			// 对于同步sram需要等待 1 个时钟周期
+			if(graph_pixel[4:0]==5'b00011)
+				latched_vram_data <= vram_data;
+		end
+		3'b110:
+		begin
+			// 128 x 192 x 4	gm: 110
+			if(graph_pixel[3:0]==4'b0001)
+				vram_addr <= {graph_line_2x[9:1], graph_pixel[8:4]};
+			// 对于同步sram需要等待 1 个时钟周期
+			if(graph_pixel[3:0]==4'b0011)
+				latched_vram_data <= vram_data;
+		end
+		3'b111:
+		begin
+			// 256 x 192 x 2	gm: 111
+			if(graph_pixel[3:0]==4'b0001)
+				vram_addr <= {graph_line_2x[9:1], graph_pixel[8:4]};
+			// 对于同步sram需要等待 1 个时钟周期
+			if(graph_pixel[3:0]==4'b0011)
+				latched_vram_data <= vram_data;
+		end
+		default:
+		begin
+			// 128 x 64 x 4 	gm: 010
+			if(graph_pixel[3:0]==4'b0001)
+				vram_addr <= {2'b0,graph_line_3x[9:3], graph_pixel[8:4]};
+				//vram_addr <= {2'b0,graph_line_3x[8:3], graph_pixel[6:2]};
+			// 对于同步sram需要等待 1 个时钟周期
+			if(graph_pixel[3:0]==4'b0011)
+				latched_vram_data <= vram_data;
+		end
+		endcase
+	end
+	latched_vga_rgb <= vga_rgb;
+end
+
+// palette
+/*
+位\色  绿   黄   蓝   红   浅黄  浅蓝  紫   橙
+D6     0    0    0    0    1     1     1    1
+D5     0    0    1    1    0     0     1    1
+D4     0    1    0    1    0     1     0    1
+
+0x07 0xff 0x00 // GREEN
+0xff 0xff 0x00 // YELLOW
+0x3b 0x08 0xff // BLUE
+0xcc 0x00 0x3b // RED
+0xff 0xff 0xff // BUFF
+0x07 0xe3 0x99 // CYAN
+0xff 0x1c 0xff // MAGENTA
+0xff 0x81 0x00 // ORANGE
+
+0x00 0x00 0x00 // BLACK
+0x07 0xff 0x00 // GREEN
+0x3b 0x08 0xff // BLUE
+0xff 0xff 0xff // BUFF
+
+*/
+
+wire [2:0]	palette_bit_graph;
+
+wire [23:0]	palette_rgb_border =	(~ag)?24'h000000:				// 字符模式背景
+									(css)?24'hffffff:24'h07ff00;	// 图形模式背景
+
+wire [23:0] palette_rgb_pixel = 24'h000000;
+wire [23:0] palette_rgb_background = 24'h07ff00;
+
+// 64 x 64 x 4		gm: 000
+// 128 x 64 x 2		gm: 001
+// 128 x 64 x 4 	gm: 010
+// 128 x 96 x 2		gm: 011
+// 128 x 96 x 4		gm: 100
+// 128 x 192 x 2	gm: 101
+// 128 x 192 x 4	gm: 110
+// 256 x 192 x 2	gm: 111
+
+//assign palette_bit_graph = (ag)? {css, pixel_4p_2bit} : latched_palette_data[6:4];
+
+assign palette_bit_graph		=	(~ag)			?	latched_palette_data[6:4]				:
+									(gm==3'b000)	?	{css, pixel_8p_2bit					}	:
+									(gm==3'b001)	?	{css, pixel_4p_1bit, pixel_4p_1bit	}	:
+									(gm==3'b010)	?	{css, pixel_4p_2bit					}	:
+									(gm==3'b011)	?	{css, pixel_4p_1bit, pixel_4p_1bit	}	:
+									(gm==3'b100)	?	{css, pixel_4p_2bit					}	:
+									(gm==3'b101)	?	{css, pixel_4p_1bit, pixel_4p_1bit	}	:
+									(gm==3'b110)	?	{css, pixel_4p_2bit					}	:
+														{css, pixel_2p_1bit, pixel_2p_1bit	}	;
+
+wire [23:0] palette_rgb_graph =	(palette_bit_graph==3'b000) ?	24'h07ff00 : // GREEN
+								(palette_bit_graph==3'b001) ?	24'hffff00 : // YELLOW
+								(palette_bit_graph==3'b010) ?	24'h3b08ff : // BLUE
+								(palette_bit_graph==3'b011) ?	24'hcc003b : // RED
+								(palette_bit_graph==3'b100) ?	24'hffffff : // BUFF
+								(palette_bit_graph==3'b101) ?	24'h07e399 : // CYAN
+								(palette_bit_graph==3'b110) ?	24'hff1cff : // MAGENTA
+																24'hff8100 ; // ORANGE
+
+/*
+	24'h000000 // BLACK
+	24'h07ff00 // GREEN
+	24'h3b08ff // BLUE
+	24'hffffff // BUFF
+*/
+
+
+// use the result of the character generator module to choose between the foreground and background color
+
+assign vga_rgb =	(show_border)	? palette_rgb_border :
+					(ag)			? palette_rgb_graph :
+					(~pixel_on)		? palette_rgb_pixel :
+					(latched_palette_data[7])	? palette_rgb_graph : palette_rgb_background;
+
+assign vga_red = latched_vga_rgb[23:16];
+assign vga_green = latched_vga_rgb[15:8];
+assign vga_blue = latched_vga_rgb[7:0];
+
+
+// the character generator block includes the character RAM
+// and the character generator ROM
+CHAR_GEN CHAR_GEN
+(
+	.reset(reset),					// reset signal
+
+	.char_code(latched_vram_data),
+	.subchar_line(subchar_line),	// current line of pixels within current character
+	.subchar_pixel(subchar_pixel),	// current column of pixels withing current character
+
+	.pixel_clock(pixel_clock),		// read clock
+	.pixel_on(pixel_on)				// read data
+);
+
+PIXEL_GEN PIXEL_GEN
+(
+	.reset(reset),					// reset signal
+
+	.pixel_code(latched_vram_data),
+	.graph_pixel(graph_pixel),		// current column of pixels withing current character
+
+	.pixel_clock(pixel_clock),		// read clock
+
+	.pixel_8p_2bit(pixel_8p_2bit),	//	64x64x4
+	.pixel_4p_2bit(pixel_4p_2bit),	//	128x64x4 128x96x4 128x192x4
+	.pixel_4p_1bit(pixel_4p_1bit),	//	128x64x2 128x96x2 128x192x2
+	.pixel_2p_1bit(pixel_2p_1bit)	//	256x192x2
+);
+
+endmodule //CHAR_DISPLAY
diff --git a/Computer_MiST/Laser310_MiST/rtl/PIXEL_GEN.v b/Computer_MiST/Laser310_MiST/rtl/PIXEL_GEN.v
new file mode 100644
index 00000000..cc2f61f3
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/PIXEL_GEN.v
@@ -0,0 +1,129 @@
+module PIXEL_GEN(
+	// control
+	reset,
+
+	pixel_code,
+	graph_pixel,
+
+	pixel_clock,
+
+	pixel_8p_2bit,	//	64x64x4
+	pixel_4p_2bit,	//	128x64x4 128x96x4 128x192x4
+	pixel_4p_1bit,	//	128x64x2 128x96x2 128x192x2
+	pixel_2p_1bit	//	256x192x2
+);
+
+
+input				reset;
+
+input	[7:0]		pixel_code;
+input	[8:0]		graph_pixel;		// pixel number on the current line
+
+input				pixel_clock;
+
+output	reg	[1:0]	pixel_8p_2bit;
+output	reg	[1:0]	pixel_4p_2bit;
+output	reg			pixel_4p_1bit;
+output	reg			pixel_2p_1bit;
+
+reg		[7:0]		latched_8p_2bit_data;
+reg		[7:0]		latched_4p_2bit_data;
+reg		[7:0]		latched_4p_1bit_data;
+reg		[7:0]		latched_2p_1bit_data;
+
+
+// 移位寄存器有四种模式
+// 每2个点 移 1 位
+// 每4个点 移 2 位
+// 每4个点 移 1 位
+// 每8个点 移 2 位
+
+
+// serialize the GRAPH MODE data
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+ 		begin
+			pixel_8p_2bit			<=	2'b00;
+			latched_8p_2bit_data	<=	8'h00;
+		end
+	else begin
+		case(graph_pixel[4:0])
+			5'b00101:
+				latched_8p_2bit_data[7:0]	<=	pixel_code;
+			default:
+				if(graph_pixel[3:0]==3'b110)
+					{pixel_8p_2bit,latched_8p_2bit_data[7:2]}	<=	latched_8p_2bit_data[7:0];
+		endcase
+		end
+
+	end
+
+
+// 延时：图形模式 128x64 4色
+// 1、(001)锁存 vram 地址，2、(010)读取 vram  3、(011)锁存 vram 数据 4、(100)空 5、(101)数据锁存至移位寄存器
+// 6、(110)移位得到点阵 7、(111)建立调色板，锁存色彩
+
+// serialize the GRAPH MODE data
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+ 		begin
+			pixel_4p_2bit			<=	2'b00;
+			latched_4p_2bit_data	<=	8'h00;
+		end
+	else begin
+		case(graph_pixel[3:0])
+			4'b0101:
+				latched_4p_2bit_data[7:0]	<=	pixel_code;
+			default:
+				if(graph_pixel[1:0]==2'b10)
+					{pixel_4p_2bit,latched_4p_2bit_data[7:2]}	<=	latched_4p_2bit_data[7:0];
+		endcase
+		end
+
+	end
+
+
+// serialize the GRAPH MODE data
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+ 		begin
+			pixel_4p_1bit			<=	2'b00;
+			latched_4p_1bit_data	<=	8'h00;
+		end
+	else begin
+		case(graph_pixel[4:0])
+			5'b00101:
+				latched_4p_1bit_data[7:0]	<=	pixel_code;
+			default:
+				if(graph_pixel[1:0]==2'b10)
+					{pixel_4p_1bit,latched_4p_1bit_data[7:1]}	<=	latched_4p_1bit_data[7:0];
+		endcase
+		end
+
+	end
+
+
+// 延时：图形模式 256x192 2色
+// 1、(001)锁存 vram 地址，2、(010)读取 vram  3、(011)锁存 vram 数据 4、(100)空 5、(101)数据锁存至移位寄存器
+// 6、(110)移位得到点阵 7、(111)建立调色板，锁存色彩
+
+// serialize the GRAPH MODE data
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+		begin
+			pixel_2p_1bit			<=	1'b0;
+			latched_2p_1bit_data	<=	8'h00;
+		end
+	else begin
+		case(graph_pixel[3:0])
+			4'b0101:
+				latched_2p_1bit_data[7:0]	<=	pixel_code;
+			default:
+				if(graph_pixel[0]==1'b0)
+					{pixel_2p_1bit,latched_2p_1bit_data[7:1]}	<=	latched_2p_1bit_data[7:0];
+		endcase
+		end
+
+	end
+
+endmodule //PIXEL_GEN
diff --git a/Computer_MiST/Laser310_MiST/rtl/SVGA_DEFINES.v b/Computer_MiST/Laser310_MiST/rtl/SVGA_DEFINES.v
new file mode 100644
index 00000000..599e568a
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/SVGA_DEFINES.v
@@ -0,0 +1,246 @@
+/*
+---------------------------------------------------------------------------------
+To select a resolution and refresh rate, remove the comments around the desired
+block in this file. The pixel clock output by the DCM module should approximately
+equal the rate specified above the timing block that is uncommented.
+---------------------------------------------------------------------------------
+*/
+
+// DEFINE THE VARIOUS PIPELINE DELAYS
+
+`define CHARACTER_DECODE_DELAY  4
+
+
+//  640 X 480 @ 60Hz with a 25.175MHz pixel clock
+`define H_ACTIVE			640		// pixels
+`define H_FRONT_PORCH		16		// pixels
+`define H_SYNCH				96		// pixels
+`define H_BACK_PORCH		48		// pixels
+`define H_TOTAL				800		// pixels
+
+`define V_ACTIVE			480		// lines
+`define V_FRONT_PORCH		11		// lines
+`define V_SYNCH				2		// lines
+`define V_BACK_PORCH		31		// lines
+`define V_TOTAL				524		// lines
+
+`define CLK_MULTIPLY		2		// 50 * 2/4 = 25.000 MHz
+`define CLK_DIVIDE			4
+
+
+/*
+//  640 X 480 @ 72Hz with a 31.500MHz pixel clock
+`define H_ACTIVE			640	// pixels
+`define H_FRONT_PORCH	24		// pixels
+`define H_SYNCH			40		// pixels
+`define H_BACK_PORCH		128	// pixels
+`define H_TOTAL			832	// pixels
+
+`define V_ACTIVE			480	// lines
+`define V_FRONT_PORCH	9		// lines
+`define V_SYNCH			3		// lines
+`define V_BACK_PORCH		28		// lines
+`define V_TOTAL			520	// lines
+
+`define CLK_MULTIPLY		5		// 50 * 5/8 = 31.250 MHz
+`define CLK_DIVIDE		8
+*/
+
+/*
+//  640 X 480 @ 75Hz with a 31.500MHz pixel clock
+`define H_ACTIVE			640	// pixels
+`define H_FRONT_PORCH	16		// pixels
+`define H_SYNCH			96		// pixels
+`define H_BACK_PORCH		48		// pixels
+`define H_TOTAL			800	// pixels
+
+`define V_ACTIVE			480	// lines
+`define V_FRONT_PORCH	11		// lines
+`define V_SYNCH			2		// lines
+`define V_BACK_PORCH		32		// lines
+`define V_TOTAL			525	// lines
+
+`define CLK_MULTIPLY		5		// 50 * 5/8 = 31.250 MHz
+`define CLK_DIVIDE		8
+*/
+
+/*
+// 640 X 480 @ 85Hz with a 36.000MHz pixel clock
+`define H_ACTIVE			640	// pixels
+`define H_FRONT_PORCH	32		// pixels
+`define H_SYNCH			48		// pixels
+`define H_BACK_PORCH		112	// pixels
+`define H_TOTAL			832	// pixels
+
+`define V_ACTIVE			480	// lines
+`define V_FRONT_PORCH	1		// lines
+`define V_SYNCH			3		// lines
+`define V_BACK_PORCH		25		// lines
+`define V_TOTAL			509	// lines
+
+`define CLK_MULTIPLY		18		// 50 * 18/25 = 36.000 MHz
+`define CLK_DIVIDE		25
+*/
+
+/*
+// 800 X 600 @ 56Hz with a 38.100MHz pixel clock
+`define H_ACTIVE			800	// pixels
+`define H_FRONT_PORCH	32		// pixels
+`define H_SYNCH			128	// pixels
+`define H_BACK_PORCH		128	// pixels
+`define H_TOTAL			1088	// pixels
+
+`define V_ACTIVE			600	// lines
+`define V_FRONT_PORCH	1		// lines
+`define V_SYNCH			4		// lines
+`define V_BACK_PORCH		14		// lines
+`define V_TOTAL			619	// lines
+
+`define CLK_MULTIPLY		16		// 50 * 16/21 = 38.095 MHz
+`define CLK_DIVIDE		21
+*/
+
+/*
+// 800 X 600 @ 60Hz with a 40.000MHz pixel clock
+`define H_ACTIVE			800	// pixels
+`define H_FRONT_PORCH	40		// pixels
+`define H_SYNCH			128	// pixels
+`define H_BACK_PORCH		88		// pixels
+`define H_TOTAL			1056	// pixels
+
+`define V_ACTIVE			600	// lines
+`define V_FRONT_PORCH	1		// lines
+`define V_SYNCH			4		// lines
+`define V_BACK_PORCH		23		// lines
+`define V_TOTAL			628	// lines
+
+`define CLK_MULTIPLY		4		// 50 * 4/5 = 40.000 MHz
+`define CLK_DIVIDE		5
+*/
+
+/*
+// 800 X 600 @ 72Hz with a 50.000MHz pixel clock
+`define H_ACTIVE			800	// pixels
+`define H_FRONT_PORCH	56		// pixels
+`define H_SYNCH			120	// pixels
+`define H_BACK_PORCH		64		// pixels
+`define H_TOTAL			1040	// pixels
+
+`define V_ACTIVE			600	// lines
+`define V_FRONT_PORCH	37		// lines
+`define V_SYNCH			6		// lines
+`define V_BACK_PORCH		23		// lines
+`define V_TOTAL			666	// lines
+
+`define CLK_MULTIPLY		2		// 50 * 2/2 = 50.000 MHz
+`define CLK_DIVIDE		2
+*/
+
+/*
+// 800 X 600 @ 75Hz with a 49.500MHz pixel clock
+`define H_ACTIVE			800	// pixels
+`define H_FRONT_PORCH	16		// pixels
+`define H_SYNCH			80		// pixels
+`define H_BACK_PORCH		160	// pixels
+`define H_TOTAL			1056	// pixels
+
+`define V_ACTIVE			600	// lines
+`define V_FRONT_PORCH	1		// lines
+`define V_SYNCH			2		// lines
+`define V_BACK_PORCH		21		// lines
+`define V_TOTAL			624	// lines
+
+`define CLK_MULTIPLY		2		// 50 * 2/2 = 50.000 MHz
+`define CLK_DIVIDE		2
+*/
+
+/*
+// 800 X 600 @ 85Hz with a 56.250MHz pixel clock
+`define H_ACTIVE			800	// pixels
+`define H_FRONT_PORCH	32		// pixels
+`define H_SYNCH			64		// pixels
+`define H_BACK_PORCH		152	// pixels
+`define H_TOTAL			1048	// pixels
+
+`define V_ACTIVE			600	// lines
+`define V_FRONT_PORCH	1		// lines
+`define V_SYNCH			3		// lines
+`define V_BACK_PORCH		27		// lines
+`define V_TOTAL			631	// lines
+
+`define CLK_MULTIPLY		9		// 50 * 9/8 = 56.250 MHz
+`define CLK_DIVIDE		8
+*/
+
+/*
+// 1024 X 768 @ 60Hz with a 65.000MHz pixel clock
+`define H_ACTIVE			1024	// pixels
+`define H_FRONT_PORCH	24		// pixels
+`define H_SYNCH			136	// pixels
+`define H_BACK_PORCH		160	// pixels
+`define H_TOTAL			1344	// pixels
+
+`define V_ACTIVE			768	// lines
+`define V_FRONT_PORCH	3		// lines
+`define V_SYNCH			6		// lines
+`define V_BACK_PORCH		29		// lines
+`define V_TOTAL			806	// lines
+
+`define CLK_MULTIPLY		13		// 50 * 13/10 = 65.000 MHz
+`define CLK_DIVIDE		10
+/*
+
+/*
+// 1024 X 768 @ 70Hz with a 75.000MHz pixel clock
+`define H_ACTIVE			1024	// pixels
+`define H_FRONT_PORCH	24		// pixels
+`define H_SYNCH			136	// pixels
+`define H_BACK_PORCH		144	// pixels
+`define H_TOTAL			1328	// pixels
+
+`define V_ACTIVE			768	// lines
+`define V_FRONT_PORCH	3		// lines
+`define V_SYNCH			6		// lines
+`define V_BACK_PORCH		29		// lines
+`define V_TOTAL			806	// lines
+
+`define CLK_MULTIPLY		3		// 50 * 3/2 = 75.000 MHz
+`define CLK_DIVIDE		2
+*/
+
+/*
+// 1024 X 768 @ 75Hz with a 78.750MHz pixel clock
+`define H_ACTIVE			1024	// pixels
+`define H_FRONT_PORCH	16		// pixels
+`define H_SYNCH			96		// pixels
+`define H_BACK_PORCH		176	// pixels
+`define H_TOTAL			1312	// pixels
+
+`define V_ACTIVE			768	// lines
+`define V_FRONT_PORCH	1		// lines
+`define V_SYNCH			3		// lines
+`define V_BACK_PORCH		28		// lines
+`define V_TOTAL			800	// lines
+
+`define CLK_MULTIPLY		11		// 50 * 11/7 = 78.571 MHz
+`define CLK_DIVIDE		7
+*/
+
+/*
+// 1024 X 768 @ 85Hz with a 94.500MHz pixel clock
+`define H_ACTIVE			1024	// pixels
+`define H_FRONT_PORCH	48		// pixels
+`define H_SYNCH			96		// pixels
+`define H_BACK_PORCH		208	// pixels
+`define H_TOTAL			1376	// pixels
+
+`define V_ACTIVE			768	// lines
+`define V_FRONT_PORCH	1		// lines
+`define V_SYNCH			3		// lines
+`define V_BACK_PORCH		36		// lines
+`define V_TOTAL			808	// lines
+
+`define CLK_MULTIPLY		17		// 50 * 17/9 = 94.444 MHz
+`define CLK_DIVIDE		9
+*/
+
diff --git a/Computer_MiST/Laser310_MiST/rtl/SVGA_TIMING_GENERATION.v b/Computer_MiST/Laser310_MiST/rtl/SVGA_TIMING_GENERATION.v
new file mode 100644
index 00000000..42a99da6
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/SVGA_TIMING_GENERATION.v
@@ -0,0 +1,353 @@
+`include "SVGA_DEFINES.v"
+
+
+`define SVGA_DECODE_DELAY  7
+// 延时：字符模式
+// 1、(001)锁存 vram 地址，2、(010)读取 vram  3、(011)锁存 vram 数据 4、(100)字库地址 5、(101)锁存字库 
+// 6、(110)移位得到点阵，同时锁存vram数据用于调色板 7、(111)建立调色板，锁存色彩
+
+// Delay: Character mode
+// 1 (001) latch vram address, 2, (010) read vram 3, (011) latch vram data 4, (100) font address 5, (101) latch font
+// 6, (110) shift to get a lattice, while latching vram data for the palette 7, (111) to create a palette, latch color
+
+// 延时：图形模式 128x64 4色
+// 1、(001)锁存 vram 地址，2、(010)读取 vram  3、(011)锁存 vram 数据 4、(100)空 5、(101)数据锁存至移位寄存器
+// 6、(110)移位得到点阵 7、(111)建立调色板，锁存色彩
+
+// Delay: graphics mode 128x64 4 colors
+// 1, (001) latch vram address, 2, (010) read vram 3, (011) latch vram data 4, (100) empty 5, (101) data latched to the shift register
+// 6, (110) shift to get the dot matrix 7, (111) to create a palette, latch color
+
+module SVGA_TIMING_GENERATION
+(
+	pixel_clock,
+	reset,
+	h_synch,
+	v_synch,
+	blank,
+	pixel_count,
+	line_count,
+
+	show_border,
+
+	// text
+	subchar_pixel,
+	subchar_line,
+	char_column,
+	char_line,
+
+	// graph
+	graph_pixel,
+	graph_line_2x,
+	graph_line_3x
+);
+
+input 				pixel_clock;		// pixel clock
+input 				reset;				// reset
+(*keep*)output	reg			h_synch;			// horizontal synch for VGA connector
+(*keep*)output	reg			v_synch;			// vertical synch for VGA connector
+output	reg			blank;				// composite blanking
+output	reg	[10:0]	pixel_count;		// counts the pixels in a line
+output	reg	[9:0]	line_count;			// counts the display lines
+
+(*keep*)output	reg			show_border;
+
+// 字符控制
+(*keep*)output	reg	[3:0]	subchar_pixel;		// pixel position within the character
+(*keep*)output	reg	[4:0]	subchar_line;		// identifies the line number within a character block
+(*keep*)output	reg	[6:0]	char_column;		// character number on the current line
+(*keep*)output	reg	[6:0]	char_line;			// line number on the screen
+
+// 图形控制 128*64
+(*keep*)output	reg		[8:0]	graph_pixel;
+(*keep*)output	reg		[9:0]	graph_line_3x;
+
+// 图形控制 256*192
+(*keep*)output	reg		[9:0]	graph_line_2x;
+
+(*keep*)reg			h_blank;
+reg			v_blank;
+
+reg			show_pixel;
+reg			show_line;
+
+// CREATE THE HORIZONTAL LINE PIXEL COUNTER
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+		// on reset set pixel counter to 0
+		pixel_count <= 11'd0;
+
+	else if (pixel_count == (`H_TOTAL - 1))
+		// last pixel in the line, so reset pixel counter
+		pixel_count <= 11'd0;
+
+	else
+		pixel_count <= pixel_count + 1;
+end
+
+// CREATE THE HORIZONTAL SYNCH PULSE
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+		// on reset remove h_synch
+		h_synch <= 1'b0;
+
+	else if (pixel_count == (`H_ACTIVE + `H_FRONT_PORCH - 1))
+		// start of h_synch
+		h_synch <= 1'b1;
+
+	else if (pixel_count == (`H_TOTAL - `H_BACK_PORCH - 1))
+		// end of h_synch
+		h_synch <= 1'b0;
+end
+
+// CREATE THE VERTICAL FRAME LINE COUNTER
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+		// on reset set line counter to 0
+		line_count <= 10'd0;
+
+	else if ((line_count == (`V_TOTAL - 1)) & (pixel_count == (`H_TOTAL - 1)))
+		// last pixel in last line of frame, so reset line counter
+		line_count <= 10'd0;
+
+	else if ((pixel_count == (`H_TOTAL - 1)))
+		// last pixel but not last line, so increment line counter
+		line_count <= line_count + 1;
+end
+
+// CREATE THE VERTICAL SYNCH PULSE
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+		// on reset remove v_synch
+		v_synch <= 1'b0;
+
+	else if ((line_count == (`V_ACTIVE + `V_FRONT_PORCH - 1) &
+		   (pixel_count == `H_TOTAL - 1)))
+		// start of v_synch
+		v_synch <= 1'b1;
+
+	else if ((line_count == (`V_TOTAL - `V_BACK_PORCH - 1)) &
+		   (pixel_count == (`H_TOTAL - 1)))
+		// end of v_synch
+		v_synch <= 1'b0;
+end
+
+
+// CREATE THE HORIZONTAL BLANKING SIGNAL
+// the "-2" is used instead of "-1" because of the extra register delay
+// for the composite blanking signal
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+		// on reset remove the h_blank
+		h_blank <= 1'b0;
+
+	else if (pixel_count == (`H_ACTIVE -2))
+		// start of HBI
+		h_blank <= 1'b1;
+
+	else if (pixel_count == (`H_TOTAL -2))
+		// end of HBI
+		h_blank <= 1'b0;
+end
+
+
+// CREATE THE VERTICAL BLANKING SIGNAL
+// the "-2" is used instead of "-1"  in the horizontal factor because of the extra
+// register delay for the composite blanking signal
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+		// on reset remove v_blank
+		v_blank <= 1'b0;
+
+	else if ((line_count == (`V_ACTIVE - 1) &
+		   (pixel_count == `H_TOTAL - 2)))
+		// start of VBI
+		v_blank <= 1'b1;
+
+	else if ((line_count == (`V_TOTAL - 1)) &
+		   (pixel_count == (`H_TOTAL - 2)))
+		// end of VBI
+		v_blank <= 1'b0;
+end
+
+
+// CREATE THE COMPOSITE BANKING SIGNAL
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+		// on reset remove blank
+		blank <= 1'b0;
+
+	// blank during HBI or VBI
+	else if (h_blank || v_blank)
+		blank <= 1'b1;
+
+	else
+		// active video do not blank
+		blank <= 1'b0;
+end
+
+
+////////////////////////////////////////////////////
+// 以上部分内容相对固定，是VGA的控制信号和计数器  //
+////////////////////////////////////////////////////
+
+
+/*
+   CREATE THE CHARACTER COUNTER.
+   CHARACTERS ARE DEFINED WITHIN AN 8 x 8 PIXEL BLOCK.
+
+	A 640  x 480 video mode will display 80  characters on 60 lines.
+	A 800  x 600 video mode will display 100 characters on 75 lines.
+	A 1024 x 768 video mode will display 128 characters on 96 lines.
+
+	"subchar_line" identifies the row in the 8 x 8 block.
+	"subchar_pixel" identifies the column in the 8 x 8 block.
+*/
+
+// 8x12点阵 32x16个字符 256x192
+// 640x480 倍线 512x384 左右各空64个点，上下空 48 个点。
+// 需要生成四个数据：
+// 字符点阵 subchar_line subchar_pixel
+// 字符寻址 char_column char_line
+
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+		show_pixel <= 1'b0;
+	else if (pixel_count == (-1) + 64 - `SVGA_DECODE_DELAY)
+		show_pixel <= 1'b1;
+	else if (pixel_count == (`H_ACTIVE - 1) - 64 - `SVGA_DECODE_DELAY)
+		show_pixel <= 1'b0;
+end
+
+always @ (posedge h_synch or posedge reset) begin
+	if (reset)
+		show_line <= 1'b0;
+	else if (line_count == (-1) + 48)
+		show_line <= 1'b1;
+	else if (line_count == (`V_ACTIVE - 1) - 48)
+		show_line <= 1'b0;
+end
+
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+		show_border <= 1'b1;
+	else if (pixel_count == (-1) + 64)
+		show_border <= ~show_line;
+	else if (pixel_count == (`H_ACTIVE - 1) - 64)
+		show_border <= 1'b1;
+end
+
+
+// text 32x16
+
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+	begin
+		// reset to 5 so that the first character data can be latched
+		subchar_pixel <= 4'b0000;
+		char_column <= 7'd0;
+	end
+	else if (h_synch)
+	begin
+		// reset to 5 so that the first character data can be latched
+		subchar_pixel <= 4'b0000;
+		char_column <= 7'd0;
+	end
+	else if(show_pixel)
+	begin
+		subchar_pixel <= subchar_pixel + 1;
+		if(subchar_pixel == 4'b1111)			// 8*2-1
+			char_column <= char_column + 1;
+	end
+end
+
+
+always @ (posedge h_synch or posedge reset) begin
+	if (reset)
+	begin
+		// on reset set line counter to 0
+		subchar_line <= 5'b00000;
+		char_line <= 7'd0;
+	end
+	else if(v_synch)
+	begin
+		// reset line counter
+		subchar_line <= 5'b00000;
+		char_line <= 7'd0;
+	end
+	else if(show_line)
+		if(subchar_line == 5'd23)		// 12*2-1
+		begin
+			subchar_line <= 5'b00000;
+			char_line <= char_line + 1;
+		end
+		else
+			// increment line counter
+			subchar_line <= subchar_line + 1;
+end
+
+
+// 为所有图形模式提供水平计数
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset)
+	begin
+		// reset to 5 so that the first character data can be latched
+		graph_pixel <= 9'd0;
+	end
+	else if (h_synch)
+	begin
+		// reset to 5 so that the first character data can be latched
+		graph_pixel <= 9'd0;
+	end
+	else if(show_pixel)
+	begin
+		graph_pixel <= graph_pixel + 1;
+	end
+end
+
+// 为图形模式提供垂直计数
+// 64x64  4色
+// 128x64  2色
+// 128x64  4色
+always @ (posedge h_synch or posedge reset) begin
+	if (reset)
+	begin
+		// on reset set line counter to 0
+		graph_line_3x <= 10'd0;
+	end
+	else if(v_synch)
+	begin
+		// reset line counter
+		graph_line_3x <= 10'd0;
+	end
+	else if(show_line)
+		if(graph_line_3x[1:0] == 2'b10)		// 3行为单位计数
+			graph_line_3x <= graph_line_3x + 2;
+		else
+			// increment line counter
+			graph_line_3x <= graph_line_3x + 1;
+end
+
+// 为图形模式提供垂直计数
+// 128x96  2色
+// 128x96  4色
+// 128x192 2色
+// 128x192 4色
+// 256x192 2色
+always @ (posedge h_synch or posedge reset) begin
+	if (reset)
+	begin
+		// on reset set line counter to 0
+		graph_line_2x <= 10'd0;
+	end
+	else if(v_synch)
+	begin
+		// reset line counter
+		graph_line_2x <= 10'd0;
+	end
+	else if(show_line)
+		// increment line counter
+		graph_line_2x <= graph_line_2x + 1;
+end
+
+endmodule //SVGA_TIMING_GENERATION
diff --git a/Computer_MiST/Laser310_MiST/rtl/T80/T80.vhd b/Computer_MiST/Laser310_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/T80/T80.vhd
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Computer_MiST/Laser310_MiST/rtl/T80/T80_ALU.vhd b/Computer_MiST/Laser310_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..95c98dab
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/T80/T80_ALU.vhd
@@ -0,0 +1,371 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+
+	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
+	process (Carry_v, Carry7_v, Q_v)
+	begin
+		if(Mode=2) then
+			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
+					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
+			OverFlow_v <= Carry_v xor Carry7_v;
+		end if;
+	end process;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Computer_MiST/Laser310_MiST/rtl/T80/T80_MCode.vhd b/Computer_MiST/Laser310_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/T80/T80_MCode.vhd
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Computer_MiST/Laser310_MiST/rtl/T80/T80_Pack.vhd b/Computer_MiST/Laser310_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/T80/T80_Pack.vhd
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Computer_MiST/Laser310_MiST/rtl/T80/T80_Reg.vhd b/Computer_MiST/Laser310_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..828485fb
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/T80/T80_Reg.vhd
@@ -0,0 +1,105 @@
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--	0242 : Initial release
+--
+--	0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk			: in std_logic;
+		CEN			: in std_logic;
+		WEH			: in std_logic;
+		WEL			: in std_logic;
+		AddrA		: in std_logic_vector(2 downto 0);
+		AddrB		: in std_logic_vector(2 downto 0);
+		AddrC		: in std_logic_vector(2 downto 0);
+		DIH			: in std_logic_vector(7 downto 0);
+		DIL			: in std_logic_vector(7 downto 0);
+		DOAH		: out std_logic_vector(7 downto 0);
+		DOAL		: out std_logic_vector(7 downto 0);
+		DOBH		: out std_logic_vector(7 downto 0);
+		DOBL		: out std_logic_vector(7 downto 0);
+		DOCH		: out std_logic_vector(7 downto 0);
+		DOCL		: out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal	RegsH	: Register_Image(0 to 7);
+	signal	RegsL	: Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Computer_MiST/Laser310_MiST/rtl/T80/T80sed.vhd b/Computer_MiST/Laser310_MiST/rtl/T80/T80sed.vhd
new file mode 100644
index 00000000..0c28ec21
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/T80/T80sed.vhd
@@ -0,0 +1,179 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
+--
+-- Z80 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original z80
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0238
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0235 : First release
+--
+--      0236 : Added T2Write generic
+--
+--      0237 : Fixed T2Write with wait state
+--
+--      0238 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80sed is
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CLKEN           : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		MREQ_n          : out std_logic;
+		IORQ_n          : out std_logic;
+		RD_n            : out std_logic;
+		WR_n            : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0)
+	);
+end T80sed;
+
+architecture rtl of T80sed is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead       : std_logic;
+	signal Write        : std_logic;
+	signal IORQ         : std_logic;
+	signal DI_Reg       : std_logic_vector(7 downto 0);
+	signal MCycle       : std_logic_vector(2 downto 0);
+	signal TState       : std_logic_vector(2 downto 0);
+
+begin
+
+	u0 : T80
+		generic map(
+			Mode      => 0,
+			IOWait    => 1)
+		port map(
+			CEN        => CLKEN,
+			M1_n       => M1_n,
+			IORQ       => IORQ,
+			NoRead     => NoRead,
+			Write      => Write,
+			RFSH_n     => RFSH_n,
+			HALT_n     => HALT_n,
+			WAIT_n     => Wait_n,
+			INT_n      => INT_n,
+			NMI_n      => NMI_n,
+			RESET_n    => RESET_n,
+			BUSRQ_n    => BUSRQ_n,
+			BUSAK_n    => BUSAK_n,
+			CLK_n      => CLK_n,
+			A          => A,
+			DInst      => DI,
+			DI         => DI_Reg,
+			DO         => DO,
+			MC         => MCycle,
+			TS         => TState,
+			IntCycle_n => IntCycle_n);
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			RD_n <= '1';
+			WR_n <= '1';
+			IORQ_n <= '1';
+			MREQ_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK_n'event and CLK_n = '1' then
+			if CLKEN = '1' then
+				RD_n <= '1';
+				WR_n <= '1';
+				IORQ_n <= '1';
+				MREQ_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and Wait_n = '0') then
+						RD_n <= not IntCycle_n;
+						MREQ_n <= not IntCycle_n;
+						IORQ_n <= IntCycle_n;
+					end if;
+					if TState = "011" then
+						MREQ_n <= '0';
+					end if;
+				else
+					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
+						RD_n <= '0';
+						IORQ_n <= not IORQ;
+						MREQ_n <= IORQ;
+					end if;
+						if ((TState = "001") or (TState = "010")) and Write = '1' then
+							WR_n <= '0';
+							IORQ_n <= not IORQ;
+							MREQ_n <= IORQ;
+						end if;
+				end if;
+				if TState = "010" and Wait_n = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Computer_MiST/Laser310_MiST/rtl/Text1.txt b/Computer_MiST/Laser310_MiST/rtl/Text1.txt
new file mode 100644
index 00000000..b8bd2837
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/Text1.txt
@@ -0,0 +1,483 @@
+
+
+
+
+// keyboard
+
+/*****************************************************************************
+* Convert PS/2 keyboard to ASCII keyboard
+******************************************************************************/
+
+/*
+   KD5 KD4 KD3 KD2 KD1 KD0 扫描用地址
+A0  R   Q   E       W   T  68FEH       0
+A1  F   A   D  CTRL S   G  68FDH       8
+A2  V   Z   C  SHFT X   B  68FBH      16
+A3  4   1   3       2   5  68F7H      24
+A4  M  空格 ，      .   N  68EFH      32
+A5  7   0   8   -   9   6  68DFH      40
+A6  U   P   I  RETN O   Y  68BFH      48
+A7  J   ；  K   :   L   H  687FH      56
+*/
+
+//  7: 0
+// 15: 8
+// 23:16
+// 31:24
+// 39:32
+// 47:40
+// 55:48
+// 63:56
+
+
+
+// 键盘检测的方法，就是循环地问每一行线发送低电平信号，也就是用该地址线为“0”的地址去读取数据。
+// 例如，检测第一行时，使A0为0，其余为1；加上选通IC4的高五位地址01101，成为01101***11111110B（A8~A10不起作用，
+// 可为任意值，故68FEH，69FEH，6AFEH，6BFEH，6CFEH，6DFEH，6EFEH，6FFEH均可）。
+// 读 6800H 判断是否有按键按下。
+
+// The method of keyboard detection is to cyclically ask each line to send a low level signal, 
+// that is, to read the data with the address line "0".
+// For example, when detecting the first line, make A0 0 and the rest 1; plus the high five-bit address 01101 of the strobe IC4, 
+// become 01101***11111110B (A8~A10 does not work,
+// It can be any value, so 68FEH, 69FEH, 6AFEH, 6BFEH, 6CFEH, 6DFEH, 6EFEH, 6FFEH can be).
+// Read 6800H to determine if there is a button press.
+
+// 键盘选通，整个竖列有一个选通的位置被按下，对应值为0。
+// The keyboard is strobed, and a strobe position is pressed in the entire vertical column, and the corresponding value is 0.
+
+// 键盘扩展
+// 加入方向键盘
+// Keyboard extension
+
+// left:  ctrl M      37 KEY_EX[5]
+// right: ctrl ,      35 KEY_EX[6]
+// up:    ctrl .      33 KEY_EX[4]
+// down:  ctrl space  36 KEY_EX[7]
+// esc:   ctrl -      42 KEY_EX[3]
+// backspace:  ctrl M      37 KEY_EX[8]
+
+// R-Shift
+
+
+wire	[63:0]	KEY_C		=	EMU_KEY_EN?EMU_KEY:KEY;
+wire	[9:0]	KEY_EX_C	=	EMU_KEY_EN?EMU_KEY_EX:KEY_EX;
+
+//wire KEY_CTRL_ULRD = (KEY_EX[7:4]==4'b1111);
+wire KEY_CTRL_ULRD_BRK = (KEY_EX[8:3]==6'b111111);
+
+wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY_C[61], KEY_C[53], KEY_C[45],           KEY_C[37]&KEY_EX_C[5]&KEY_EX_C[8], KEY_C[29], KEY_C[21],           KEY_C[13],                   KEY_C[ 5]})==8'hff;
+wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY_C[60], KEY_C[52], KEY_C[44],           KEY_C[36]&KEY_EX_C[7], KEY_C[28], KEY_C[20],           KEY_C[12],                   KEY_C[ 4]})==8'hff;
+wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY_C[59], KEY_C[51], KEY_C[43],           KEY_C[35]&KEY_EX_C[6], KEY_C[27], KEY_C[19],           KEY_C[11],                   KEY_C[ 3]})==8'hff;
+wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY_C[58], KEY_C[50], KEY_C[42]&KEY_EX_C[3], KEY_C[34],           KEY_C[26], KEY_C[18]&KEY_EX_C[0], KEY_C[10]&KEY_CTRL_ULRD_BRK, KEY_C[ 2]})==8'hff;
+wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY_C[57], KEY_C[49], KEY_C[41],           KEY_C[33]&KEY_EX_C[4], KEY_C[25], KEY_C[17],           KEY_C[ 9],                   KEY_C[ 1]})==8'hff;
+wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY_C[56], KEY_C[48], KEY_C[40],           KEY_C[32],             KEY_C[24], KEY_C[16],           KEY_C[ 8],                   KEY_C[ 0]})==8'hff;
+
+/*
+wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY[61], KEY[53], KEY[45], KEY[37], KEY[29], KEY[21], KEY[13], KEY[ 5]})==8'hff;
+wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY[60], KEY[52], KEY[44], KEY[36], KEY[28], KEY[20], KEY[12], KEY[ 4]})==8'hff;
+wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY[59], KEY[51], KEY[43], KEY[35], KEY[27], KEY[19], KEY[11], KEY[ 3]})==8'hff;
+wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY[58], KEY[50], KEY[42], KEY[34], KEY[26], KEY[18], KEY[10], KEY[ 2]})==8'hff;
+wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY[57], KEY[49], KEY[41], KEY[33], KEY[25], KEY[17], KEY[ 9], KEY[ 1]})==8'hff;
+wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY[56], KEY[48], KEY[40], KEY[32], KEY[24], KEY[16], KEY[ 8], KEY[ 0]})==8'hff;
+*/
+
+wire KEY_DATA_BIT7 = 1'b1;	// 没有空置，具体用途没有理解
+//wire KEY_DATA_BIT6 = CASS_IN;
+wire KEY_DATA_BIT6 = ~CASS_IN;
+
+assign KEY_DATA = { KEY_DATA_BIT7, KEY_DATA_BIT6, KEY_DATA_BIT5, KEY_DATA_BIT4, KEY_DATA_BIT3, KEY_DATA_BIT2, KEY_DATA_BIT1, KEY_DATA_BIT0 };
+
+/*
+assign KEY_DATA = 	(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
+					(CPU_A[1]==1'b0) ? KEY[15: 8] :
+					(CPU_A[2]==1'b0) ? KEY[23:16] :
+					(CPU_A[3]==1'b0) ? KEY[31:24] :
+					(CPU_A[4]==1'b0) ? KEY[39:32] :
+					(CPU_A[5]==1'b0) ? KEY[47:40] :
+					(CPU_A[6]==1'b0) ? KEY[55:48] :
+					(CPU_A[7]==1'b0) ? KEY[63:56] :
+					8'hff;
+
+assign KEY_DATA =
+					(CPU_A[7]==1'b0) ? KEY[63:56] :
+					(CPU_A[6]==1'b0) ? KEY[55:48] :
+					(CPU_A[5]==1'b0) ? KEY[47:40] :
+					(CPU_A[4]==1'b0) ? KEY[39:32] :
+					(CPU_A[3]==1'b0) ? KEY[31:24] :
+					(CPU_A[2]==1'b0) ? KEY[23:16] :
+					(CPU_A[1]==1'b0) ? KEY[15: 8] :
+					(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
+					8'hff;
+*/
+
+
+assign A_KEY_PRESSED = (KEY[63:0] == 64'hFFFFFFFFFFFFFFFF) ? 1'b0:1'b1;
+
+always @(posedge KB_CLK[3] or negedge SYS_RESET_N)
+begin
+	if(~SYS_RESET_N)
+	begin
+		KEY					<=	64'hFFFFFFFFFFFFFFFF;
+		KEY_EX				<=	10'h3FF;
+		KEY_Fxx				<=	12'h000;
+//		CAPS_CLK			<=	1'b0;
+		RESET_KEY_COUNT		<=	17'h1FFFF;
+
+		BOOTROM_BANK		<=	0;
+		BOOTROM_EN			<=	1'b0;
+
+		AUTOSTARTROM_BANK	<=	0;
+		AUTOSTARTROM_EN		<=	1'b0;
+	end
+	else
+	begin
+		//KEY[?] <= CAPS;
+		if(RESET_KEY_COUNT[16]==1'b0)
+			RESET_KEY_COUNT <= RESET_KEY_COUNT+1;
+
+		case(SCAN)
+		8'h07:
+		begin
+				KEY_Fxx[11]	<= PRESS;	// F12 RESET
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b0;
+					BOOTROM_BANK		<=	0;
+					AUTOSTARTROM_EN		<=	1'b0;
+					AUTOSTARTROM_BANK	<=	0;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h78:	KEY_Fxx[10] <= PRESS;	// F11
+		8'h09:	KEY_Fxx[ 9] <= PRESS;	// F10 CASS STOP
+		8'h01:	KEY_Fxx[ 8] <= PRESS;	// F9  CASS PLAY
+		8'h0A:
+		begin
+				KEY_Fxx[ 7] <= PRESS;	// F8  Ctrl or L-Shift BOOT 8
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	39;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	23;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h83:
+		begin
+				KEY_Fxx[ 6] <= PRESS;	// F7  Ctrl or L-Shift BOOT 7
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	38;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	22;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h0B:
+		begin
+				KEY_Fxx[ 5] <= PRESS;	// F6  Ctrl or L-Shift BOOT 6
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	37;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	21;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h03:
+		begin
+				KEY_Fxx[ 4] <= PRESS;	// F5  Ctrl or L-Shift BOOT 5
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	36;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	20;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h0C:
+		begin
+				KEY_Fxx[ 3] <= PRESS;	// F4  Ctrl or L-Shift BOOT 4
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	35;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	19;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h04:
+		begin
+				KEY_Fxx[ 2] <= PRESS;	// F3  Ctrl or L-Shift BOOT 3
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	34;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	18;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h06:
+		begin
+				KEY_Fxx[ 1] <= PRESS;	// F2  Ctrl or L-Shift BOOT 2
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	33;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	17;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+		8'h05:
+		begin
+				KEY_Fxx[ 0] <= PRESS;	// F1  Ctrl or L-Shift BOOT 1
+				if(PRESS && (KEY[18]==PRESS_N))
+				begin
+					BOOTROM_EN			<=	1'b1;
+					BOOTROM_BANK		<=	32;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+				else
+				if(PRESS && (KEY[10]==PRESS_N))
+				begin
+					AUTOSTARTROM_EN		<=	1'b1;
+					AUTOSTARTROM_BANK	<=	16;
+					RESET_KEY_COUNT		<=	17'h0;
+				end
+		end
+
+		8'h16:	KEY[28] <= PRESS_N;	// 1 !
+		8'h1E:	KEY[25] <= PRESS_N;	// 2 @
+		8'h26:	KEY[27] <= PRESS_N;	// 3 #
+		8'h25:	KEY[29] <= PRESS_N;	// 4 $
+		8'h2E:	KEY[24] <= PRESS_N;	// 5 %
+		8'h36:	KEY[40] <= PRESS_N;	// 6 ^
+		8'h3D:	KEY[45] <= PRESS_N;	// 7 &
+//		8'h0D:	KEY[?] <= PRESS_N;	// TAB
+		8'h3E:	KEY[43] <= PRESS_N;	// 8 *
+		8'h46:	KEY[41] <= PRESS_N;	// 9 (
+		8'h45:	KEY[44] <= PRESS_N;	// 0 )
+		8'h4E:	KEY[42] <= PRESS_N;	// - _
+//		8'h55:	KEY[?] <= PRESS_N;	// = +
+		8'h66:	KEY_EX[8] <= PRESS_N;	// backspace
+//		8'h0E:	KEY[?] <= PRESS_N;	// ` ~
+//		8'h5D:	KEY[?] <= PRESS_N;	// \ |
+		8'h49:	KEY[33] <= PRESS_N;	// . >
+		8'h4b:	KEY[57] <= PRESS_N;	// L
+		8'h44:	KEY[49] <= PRESS_N;	// O
+//		8'h11	KEY[?] <= PRESS_N; // line feed (really right ALT (Extended) see below
+		8'h5A:	KEY[50] <= PRESS_N;	// CR
+//		8'h54:	KEY[?] <= PRESS_N;	// [ {
+//		8'h5B:	KEY[?] <= PRESS_N;	// ] }
+		8'h52:	KEY[58] <= PRESS_N;	// ' "
+		8'h1D:	KEY[ 1] <= PRESS_N;	// W
+		8'h24:	KEY[ 3] <= PRESS_N;	// E
+		8'h2D:	KEY[ 5] <= PRESS_N;	// R
+		8'h2C:	KEY[ 0] <= PRESS_N;	// T
+		8'h35:	KEY[48] <= PRESS_N;	// Y
+		8'h3C:	KEY[53] <= PRESS_N;	// U
+		8'h43:	KEY[51] <= PRESS_N;	// I
+		8'h1B:	KEY[ 9] <= PRESS_N;	// S
+		8'h23:	KEY[11] <= PRESS_N;	// D
+		8'h2B:	KEY[13] <= PRESS_N;	// F
+		8'h34:	KEY[ 8] <= PRESS_N;	// G
+		8'h33:	KEY[56] <= PRESS_N;	// H
+		8'h3B:	KEY[61] <= PRESS_N;	// J
+		8'h42:	KEY[59] <= PRESS_N;	// K
+		8'h22:	KEY[17] <= PRESS_N;	// X
+		8'h21:	KEY[19] <= PRESS_N;	// C
+		8'h2a:	KEY[21] <= PRESS_N;	// V
+		8'h32:	KEY[16] <= PRESS_N;	// B
+		8'h31:	KEY[32] <= PRESS_N;	// N
+		8'h3a:	KEY[37] <= PRESS_N;	// M
+		8'h41:	KEY[35] <= PRESS_N;	// , <
+		8'h15:	KEY[ 4] <= PRESS_N;	// Q
+		8'h1C:	KEY[12] <= PRESS_N;	// A
+		8'h1A:	KEY[20] <= PRESS_N;	// Z
+		8'h29:	KEY[36] <= PRESS_N;	// Space
+//		8'h4A:	KEY[?] <= PRESS_N;	// / ?
+		8'h4C:	KEY[60] <= PRESS_N;	// ; :
+		8'h4D:	KEY[52] <= PRESS_N;	// P
+		8'h14:	KEY[10] <= PRESS_N;	// Ctrl either left or right
+		8'h12:	KEY[18] <= PRESS_N;	// L-Shift
+		8'h59:	KEY_EX[0] <= PRESS_N;	// R-Shift
+		8'h11:
+		begin
+			if(~EXTENDED)
+					KEY_EX[1] <= PRESS_N;	// Repeat really left ALT
+			else
+					KEY_EX[2] <= PRESS_N;	// LF really right ALT
+		end
+		8'h76:	KEY_EX[3] <= PRESS_N;	// Esc
+		8'h75:	KEY_EX[4] <= PRESS_N;	// up
+		8'h6B:	KEY_EX[5] <= PRESS_N;	// left
+		8'h74:	KEY_EX[6] <= PRESS_N;	// right
+		8'h72:	KEY_EX[7] <= PRESS_N;	// down
+		endcase
+	end
+end
+
+
+
+
+always @ (posedge CLK50MHZ)				// 50MHz
+	KB_CLK <= KB_CLK + 1'b1;			// 50/32 = 1.5625 MHz
+
+ps2_keyboard KEYBOARD(
+		.RESET_N(RESET_N),
+		.CLK(KB_CLK[4]),
+		.PS2_CLK(PS2_KBCLK),
+		.PS2_DATA(PS2_KBDAT),
+		.RX_SCAN(SCAN),
+		.RX_PRESSED(PRESS),
+		.RX_EXTENDED(EXTENDED)
+);
+
+assign PRESS_N = ~PRESS;
+
+
+`ifdef CASS_EMU
+
+wire			CASS_BUF_RD;
+wire	[15:0]	CASS_BUF_A;
+wire			CASS_BUF_WR;
+wire	[7:0]	CASS_BUF_DAT;
+wire	[7:0]	CASS_BUF_Q;
+
+// F9    CASS PLAY
+// F10   CASS STOP
+
+EMU_CASS_KEY	EMU_CASS_KEY(
+	KEY_Fxx[8],
+	KEY_Fxx[9],
+	// cass emu
+	CASS_BUF_RD,
+	//
+	CASS_BUF_A,
+	CASS_BUF_WR,
+	CASS_BUF_DAT,
+	CASS_BUF_Q,
+	//	Control Signals
+	EMU_CASS_EN,
+	EMU_CASS_DAT,
+
+	// key emu
+	EMU_KEY,
+	EMU_KEY_EX,
+	EMU_KEY_EN,
+    /*
+     * UART: 115200 bps, 8N1
+     */
+    UART_RXD,
+    UART_TXD,
+
+	// System
+	TURBO_SPEED,
+	// Clock: 10MHz
+	CLK10MHZ,
+	RESET_N
+);
+
+
+`ifdef CASS_EMU_16K
+
+cass_ram_16k_altera cass_buf(
+	.address(CASS_BUF_A[13:0]),
+	.clock(CLK10MHZ),
+	.data(CASS_BUF_DI),
+	.wren(CASS_BUF_WR),
+	.q(CASS_BUF_Q)
+);
+
+`endif
+
+
+`ifdef CASS_EMU_8K
+
+cass_ram_8k_altera cass_buf(
+	.address(CASS_BUF_A[12:0]),
+	.clock(CLK10MHZ),
+	.data(CASS_BUF_DI),
+	.wren(CASS_BUF_WR),
+	.q(CASS_BUF_Q)
+);
+
+`endif
+
+
+`ifdef CASS_EMU_4K
+
+cass_ram_4k_altera cass_buf(
+	.address(CASS_BUF_A[11:0]),
+	.clock(CLK10MHZ),
+	.data(CASS_BUF_DAT),
+	.wren(CASS_BUF_WR),
+	.q(CASS_BUF_Q)
+);
+
+`endif
+
+
+`ifdef CASS_EMU_2K
+
+cass_ram_2k_altera cass_buf(
+	.address(CASS_BUF_A[10:0]),
+	.clock(CLK10MHZ),
+	.data(CASS_BUF_DAT),
+	.wren(CASS_BUF_WR),
+	.q(CASS_BUF_Q)
+);
+
+`endif
+
+`endif
+
+
+
+assign	CASS_OUT = EMU_CASS_EN ? EMU_CASS_DAT : {LATCHED_IO_DATA_WR[2], 1'b0};
+
+(*keep*)wire trap = (CPU_RD|CPU_WR) && (CPU_A[15:12] == 4'h0);
+
diff --git a/Computer_MiST/Laser310_MiST/rtl/VIDEO_OUT.v b/Computer_MiST/Laser310_MiST/rtl/VIDEO_OUT.v
new file mode 100644
index 00000000..2c8f8a25
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/VIDEO_OUT.v
@@ -0,0 +1,70 @@
+module VIDEO_OUT
+(
+	pixel_clock,
+	reset,
+	vga_red_data,
+	vga_green_data,
+	vga_blue_data,
+	h_synch,
+	v_synch,
+	blank,
+
+	VGA_OUT_HSYNC,
+	VGA_OUT_VSYNC,
+	VGA_OUT_RED,
+	VGA_OUT_GREEN,
+	VGA_OUT_BLUE
+);
+
+input			pixel_clock;
+input			reset;
+input	[7:0]	vga_red_data;
+input	[7:0]	vga_green_data;
+input	[7:0]	vga_blue_data;
+input			h_synch;
+input			v_synch;
+input			blank;
+
+output			VGA_OUT_HSYNC;
+output			VGA_OUT_VSYNC;
+output	[7:0]	VGA_OUT_RED;
+output	[7:0]	VGA_OUT_GREEN;
+output	[7:0]	VGA_OUT_BLUE;
+
+reg				VGA_OUT_HSYNC;
+reg				VGA_OUT_VSYNC;
+reg		[7:0]	VGA_OUT_RED;
+reg		[7:0]	VGA_OUT_GREEN;
+reg		[7:0]	VGA_OUT_BLUE;
+
+// make the external video connections
+always @ (posedge pixel_clock or posedge reset) begin
+	if (reset) begin
+		// shut down the video output during reset
+		VGA_OUT_HSYNC 			<= 1'b1;
+		VGA_OUT_VSYNC 			<= 1'b1;
+		VGA_OUT_RED				<= 8'b0;
+		VGA_OUT_GREEN			<= 8'b0;
+		VGA_OUT_BLUE			<= 8'b0;
+	end
+	
+	else if (blank) begin
+		// output black during the blank signal
+		VGA_OUT_HSYNC	 		<= h_synch;
+		VGA_OUT_VSYNC 	 		<= v_synch;
+		VGA_OUT_RED				<= 8'b0;
+		VGA_OUT_GREEN			<= 8'b0;
+		VGA_OUT_BLUE			<= 8'b0;
+	end
+	
+	else begin
+		// output color data otherwise
+		VGA_OUT_HSYNC	 		<= h_synch;
+		VGA_OUT_VSYNC 	 		<= v_synch;
+		VGA_OUT_RED				<= vga_red_data;
+		VGA_OUT_GREEN			<= vga_green_data;
+		VGA_OUT_BLUE			<= vga_blue_data;
+	end
+end
+
+endmodule // VIDEO_OUT
diff --git a/Computer_MiST/Laser310_MiST/rtl/build_id.tcl b/Computer_MiST/Laser310_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/build_id.tcl
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Computer_MiST/Laser310_MiST/rtl/dac.vhd b/Computer_MiST/Laser310_MiST/rtl/dac.vhd
new file mode 100644
index 00000000..9685a6cc
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/dac.vhd
@@ -0,0 +1,48 @@
+-------------------------------------------------------------------------------
+--
+-- Delta-Sigma DAC
+--
+-- Refer to Xilinx Application Note XAPP154.
+--
+-- This DAC requires an external RC low-pass filter:
+--
+--   dac_o 0---XXXXX---+---0 analog audio
+--              3k3    |
+--                    === 4n7
+--                     |
+--                    GND
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.numeric_std.all;
+
+entity dac is
+	generic (
+		C_bits  : integer := 12
+	);
+	port (
+		clk_i   : in  std_logic;
+		res_n_i : in  std_logic;
+		dac_i   : in  std_logic_vector(C_bits-1 downto 0);
+		dac_o   : out std_logic
+	);
+end dac;
+
+architecture rtl of dac is
+	signal sig_in: unsigned(C_bits downto 0);
+begin
+	seq: process(clk_i, res_n_i)
+	begin
+		if res_n_i = '0' then
+			sig_in <= to_unsigned(2**C_bits, sig_in'length);
+			dac_o  <= '0';
+		elsif rising_edge(clk_i) then
+		        -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
+			--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
+			sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
+			dac_o  <= sig_in(C_bits);
+		end if;
+	end process seq;
+end rtl;
diff --git a/Computer_MiST/Laser310_MiST/rtl/dpram.vhd b/Computer_MiST/Laser310_MiST/rtl/dpram.vhd
new file mode 100644
index 00000000..78823ec4
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/dpram.vhd
@@ -0,0 +1,58 @@
+-------------------------------------------------------------------------------
+-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dpram is
+
+generic (
+	 addr_width_g : integer := 8;
+	 data_width_g : integer := 8
+);
+port (
+	clk_a_i  : in  std_logic;
+	en_a_i   : in  std_logic;
+	we_i     : in  std_logic;
+	addr_a_i : in  std_logic_vector(addr_width_g-1 downto 0);
+	data_a_i : in  std_logic_vector(data_width_g-1 downto 0);
+	data_a_o : out std_logic_vector(data_width_g-1 downto 0);
+	clk_b_i  : in  std_logic;
+	addr_b_i : in  std_logic_vector(addr_width_g-1 downto 0);
+	data_b_o : out std_logic_vector(data_width_g-1 downto 0)
+);
+
+end dpram;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of dpram is
+
+  type   ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0);
+  signal ram_q : ram_t;
+
+begin
+
+  mem_a: process (clk_a_i)
+  begin
+    if rising_edge(clk_a_i) then
+      if we_i = '1' and en_a_i = '1' then
+        ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i;
+		  data_a_o <= data_a_i;
+		else
+		  data_a_o <= ram_q(to_integer(unsigned(addr_a_i)));
+      end if;
+    end if;
+  end process mem_a;
+
+  mem_b: process (clk_b_i)
+  begin
+    if rising_edge(clk_b_i) then
+		data_b_o <= ram_q(to_integer(unsigned(addr_b_i)));
+    end if;
+  end process mem_b;
+
+end rtl;
diff --git a/Computer_MiST/Laser310_MiST/rtl/mc6847_vga.v b/Computer_MiST/Laser310_MiST/rtl/mc6847_vga.v
new file mode 100644
index 00000000..9b638ead
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/mc6847_vga.v
@@ -0,0 +1,199 @@
+// LASER310 VZ200
+// mc6847
+
+module MC6847_VGA(
+PIX_CLK,
+RESET_N,
+
+RD,
+DD,
+DA,
+
+AG,
+AS,
+EXT,
+INV,
+GM,
+CSS,
+
+// vga
+blank,
+VGA_OUT_HSYNC,
+VGA_OUT_VSYNC,
+VGA_OUT_RED,
+VGA_OUT_GREEN,
+VGA_OUT_BLUE
+);
+
+input			PIX_CLK;
+input			RESET_N;
+
+output	wire			RD;
+output	wire	[12:0]	DA;		// 8KB
+input			[7:0]	DD;
+input					AG;
+input					AS;
+input					EXT;
+input					INV;
+input					CSS;
+input			[2:0]	GM;
+output	wire			blank;
+output	wire			VGA_OUT_HSYNC;
+output	wire			VGA_OUT_VSYNC;
+output	wire	[7:0]	VGA_OUT_RED;
+output	wire	[7:0]	VGA_OUT_GREEN;
+output	wire	[7:0]	VGA_OUT_BLUE;
+
+
+reg				LATCHED_AG;
+reg				LATCHED_AS;
+reg				LATCHED_EXT;
+reg				LATCHED_INV;
+reg		[2:0]	LATCHED_GM;
+reg				LATCHED_CSS;
+
+wire			pixel_clock;				// generated from SYSTEM CLOCK
+wire			reset;						// reset asserted when DCMs are NOT LOCKED
+
+wire	[7:0]	vga_red;				// red video data
+wire	[7:0]	vga_green;				// green video data
+wire	[7:0]	vga_blue;				// blue video data
+
+// internal video timing signals
+wire 			h_synch;					// horizontal synch for VGA connector
+wire 			v_synch;					// vertical synch for VGA connector
+//wire 			blank;						// composite blanking
+wire	[10:0]	pixel_count;				// bit mapped pixel position within the line
+wire	[9:0]	line_count;					// bit mapped line number in a frame lines within the frame
+
+wire			show_border;
+
+// text
+wire	[3:0]	subchar_pixel;				// pixel position within the character
+wire	[4:0]	subchar_line;				// identifies the line number within a character block
+wire	[6:0]	char_column;				// character number on the current line
+wire	[6:0]	char_line;					// line number on the screen
+
+// graph
+wire	[8:0]	graph_pixel;				// pixel number on the current line
+wire	[9:0]	graph_line_2x;				// line number on the screen
+wire	[9:0]	graph_line_3x;				// line number on the screen
+
+/*
+wire	[11:0]	ROM_ADDRESS;
+wire	[7:0]	ROM_DATA;
+*/
+
+assign	reset = ~RESET_N;
+assign	pixel_clock = PIX_CLK;
+
+//assign	vga_red = 8'hff;
+//assign	vga_green = 8'h7f;
+//assign	vga_blue = 8'h7f;
+
+// Character generator
+/*
+char_rom_4k_altera char_rom(
+	.address(ROM_ADDRESS),
+	.clock(pixel_clock),
+	.q(ROM_DATA)
+);
+*/
+
+// 为了防止闪屏，再垂直回扫信号产生时，锁存模式信号。
+
+always @ (posedge v_synch or negedge RESET_N)
+begin
+	if(!RESET_N)
+	begin
+		LATCHED_AG		<=	1'b0;
+		LATCHED_AS		<=	1'b0;
+		LATCHED_EXT		<=	1'b0;
+		LATCHED_INV		<=	1'b0;
+		LATCHED_GM		<=	3'b0;
+		LATCHED_CSS		<=	1'b0;
+	end
+	else
+	begin
+		LATCHED_AG <= AG;
+		LATCHED_AS <= AS;
+		LATCHED_EXT <= EXT;
+		LATCHED_INV <= INV;
+		LATCHED_GM <= GM;
+		LATCHED_CSS <= CSS;
+	end
+end
+
+// instantiate the character generator
+PIXEL_DISPLAY PIXEL_DISPLAY(
+	.pixel_clock(pixel_clock),
+	.reset(reset),
+	.show_border(show_border),
+	// mode
+	.ag(LATCHED_AG),
+	.gm(LATCHED_GM),
+	.css(LATCHED_CSS),
+	// text
+	.char_column(char_column),
+	.char_line(char_line),
+	.subchar_line(subchar_line),
+	.subchar_pixel(subchar_pixel),
+	// graph
+	.graph_pixel(graph_pixel),
+	.graph_line_2x(graph_line_2x),
+	.graph_line_3x(graph_line_3x),
+	// vram
+	.vram_rd_enable(RD),
+	.vram_addr(DA),
+	.vram_data(DD),
+	// vga
+	.vga_red(vga_red),
+	.vga_green(vga_green),
+	.vga_blue(vga_blue)
+);
+
+// instantiate the video timing generator
+SVGA_TIMING_GENERATION SVGA_TIMING_GENERATION
+(
+	pixel_clock,
+	reset,
+	h_synch,
+	v_synch,
+	blank,
+	pixel_count,
+	line_count,
+
+	show_border,
+
+	// text
+	subchar_pixel,
+	subchar_line,
+	char_column,
+	char_line,
+
+	// graph
+	graph_pixel,
+	graph_line_2x,
+	graph_line_3x
+);
+
+// instantiate the video output mux
+VIDEO_OUT VIDEO_OUT
+(
+	pixel_clock,
+	reset,
+	vga_red,
+	vga_green,
+	vga_blue,
+	h_synch,
+	v_synch,
+	blank,
+
+	VGA_OUT_HSYNC,
+	VGA_OUT_VSYNC,
+	VGA_OUT_RED,
+	VGA_OUT_GREEN,
+	VGA_OUT_BLUE
+);
+
+endmodule
diff --git a/Computer_MiST/Laser310_MiST/rtl/pll.qip b/Computer_MiST/Laser310_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/pll.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Computer_MiST/Laser310_MiST/rtl/pll.vhd b/Computer_MiST/Laser310_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..7194c647
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/pll.vhd
@@ -0,0 +1,451 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire2    <= sub_wire0(3);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c3    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 50,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 25,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 27,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 10,
+		clk2_phase_shift => "0",
+		clk3_divide_by => 108,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 25,
+		clk3_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire6,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "108"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "10.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.250000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "25"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.25000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "108"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Computer_MiST/Laser310_MiST/rtl/ps2_keyboard_glb.v b/Computer_MiST/Laser310_MiST/rtl/ps2_keyboard_glb.v
new file mode 100644
index 00000000..fdfa25d9
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/ps2_keyboard_glb.v
@@ -0,0 +1,227 @@
+/*****************************************************************************
+* gbfpgaapple APPLE ][e core.
+*
+*
+* Ver 1.0
+* July 2006
+* Latest version from gbfpgaapple.tripod.com
+*
+******************************************************************************
+*
+* CPU section copyrighted by Daniel Wallner
+*
+******************************************************************************
+*
+* Apple ][e compatible system on a chip
+*
+* Version : 1.0
+*
+* Copyright (c) 2006 Gary Becker (gary_l_becker@yahoo.com)
+*
+* All rights reserved
+*
+* Redistribution and use in source and synthezised forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* Redistributions in synthesized form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* Neither the name of the author nor the names of other contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+* Please report bugs to the author, but before you do so, please
+* make sure that this is not a derivative work and that
+* you have the latest version of this file.
+*
+* The latest version of this file can be found at:
+*      http://gbfpgaapple.tripod.com
+*******************************************************************************/
+
+`timescale 1 ns / 1 ns
+
+module ps2_keyboard (
+CLK,
+RESET_N,
+PS2_CLK,
+PS2_DATA,
+RX_PRESSED,
+RX_EXTENDED,
+RX_SCAN
+);
+
+input					CLK;
+input					RESET_N;
+input					PS2_CLK;
+input					PS2_DATA;
+output				RX_PRESSED;
+reg					RX_PRESSED;
+output				RX_EXTENDED;
+reg					RX_EXTENDED;
+output	[7:0]		RX_SCAN;
+reg		[7:0]		RX_SCAN;
+
+reg					KB_CLK;
+reg					KB_DATA;
+reg					KB_CLK_B;
+reg					KB_DATA_B;
+reg					PRESSED_N;
+reg					EXTENDED;
+reg		[2:0]		BIT;
+reg		[7:0]		STATE;
+reg		[7:0]		SCAN;
+wire					PARITY;
+reg		[10:0]	TIMER;
+reg					KILLER;
+wire					RESET_X;
+
+// Double buffer
+always @ (posedge CLK)
+begin
+	KB_CLK_B		<=	PS2_CLK;
+	KB_DATA_B	<= PS2_DATA;
+	KB_CLK		<= KB_CLK_B;
+	KB_DATA		<= KB_DATA_B;
+end
+assign PARITY =	~(((SCAN[0]^SCAN[1])
+						  ^(SCAN[2]^SCAN[3]))
+						 ^((SCAN[4]^SCAN[5])
+						  ^(SCAN[6]^SCAN[7])));
+
+assign RESET_X = RESET_N & KILLER;
+always @ (negedge CLK or negedge RESET_N)
+	if(!RESET_N)
+	begin
+		KILLER <= 1'b1;
+		TIMER <= 11'h000;
+	end
+	else
+		case(TIMER)
+		11'h000:
+		begin
+			KILLER <= 1'b1;
+			if(STATE != 8'h00)
+				TIMER <= 11'h001;
+		end
+		11'h7FD:
+		begin
+			KILLER <= 1'b0;
+			TIMER <= 11'h7FE;
+		end
+		default:
+			if(STATE == 8'h00)
+				TIMER <= 11'h000;
+			else
+				TIMER <= TIMER + 1'b1;
+		endcase
+
+always @ (posedge CLK or negedge RESET_X)
+begin
+	if(!RESET_X)
+	begin
+		STATE				<= 8'h00;
+		SCAN				<= 8'h00;
+		BIT				<= 3'b000;
+		RX_SCAN			<= 8'h00;
+		RX_PRESSED		<= 1'b0;
+		PRESSED_N		<= 1'b0;
+		EXTENDED			<= 1'b0;
+	end
+	else
+	begin
+		
+		case (STATE)
+		8'h00:						// Hunt for start bit
+		begin
+			SCAN				<= 8'h00;
+			BIT				<= 3'b000;
+			RX_SCAN			<= 8'h00;
+			RX_PRESSED		<= 1'b0;
+			if(~KB_DATA & ~KB_CLK)
+					STATE			<= 8'h01;
+		end
+		8'h01:						// Started
+		begin
+			if(KB_CLK)
+				STATE				<= 8'h02;
+		end
+		8'h02:						// Hunt for Bit
+		begin
+			if(~KB_CLK)
+				STATE	<= 8'h03;
+		end
+		8'h03:
+		begin
+			if(KB_CLK)
+			begin
+				SCAN[BIT]		<= KB_DATA;
+				BIT				<= BIT + 1'b1;
+				if(BIT == 3'b111)
+					STATE				<= 8'h04;
+				else
+					STATE				<= 8'h02;
+			end
+		end
+		8'h04:						// Hunt for Bit
+		begin
+			if(~KB_CLK)
+				STATE	<= 8'h05;
+		end
+		8'h05:						// Test parity
+		begin
+			if(KB_CLK)
+			begin
+				if(KB_DATA == PARITY)
+					STATE				<= 8'h06;
+				else
+				begin
+					STATE				<= 8'h00;
+				end
+			end
+		end
+		8'h06:
+		begin
+			if(SCAN == 8'hE0)
+			begin
+				EXTENDED <= 1'b1;
+				STATE		<= 8'h00;
+			end
+			else
+				if(SCAN == 8'hF0)
+				begin
+					PRESSED_N	<= 1'b1;
+					STATE			<= 8'h00;
+				end
+				else
+				begin
+					RX_SCAN		<= SCAN;
+					RX_PRESSED	<= ~PRESSED_N;
+					RX_EXTENDED	<= EXTENDED;
+					PRESSED_N	<= 1'b0;
+					EXTENDED		<= 1'b0;
+					STATE			<= 8'h07;
+				end
+			end
+		8'h07:
+			STATE				<= 8'h00;
+		endcase
+	end
+end
+
+endmodule
diff --git a/Computer_MiST/Laser310_MiST/rtl/reset_de.v b/Computer_MiST/Laser310_MiST/rtl/reset_de.v
new file mode 100644
index 00000000..fd26e271
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/reset_de.v
@@ -0,0 +1,59 @@
+module RESET_DE(
+	CLK,			// 50MHz
+	SYS_RESET_N,
+	RESET_N,		// 50MHz/32/65536
+	RESET_AHEAD_N	// 提前恢复，可以接 FLASH_RESET_N
+);
+
+
+input				CLK;
+input				SYS_RESET_N;
+output				RESET_N;
+output				RESET_AHEAD_N;
+
+
+wire	RESET_N;
+wire	RESET_AHEAD_N;
+
+reg		[5:0]		CLK_CNT;
+reg		[16:0]		RESET_COUNT;
+
+wire	RESET_COUNT_CLK;
+wire	RESET_DE_N;
+wire	RESET_AHEAD_DE_N;
+
+assign RESET_COUNT_CLK = CLK_CNT[5];
+
+assign RESET_DE_N = RESET_COUNT[16]!=1'b0;
+assign RESET_N = SYS_RESET_N && RESET_DE_N;
+
+assign RESET_AHEAD_DE_N = RESET_COUNT[16:15]!=2'b00;
+assign RESET_AHEAD_N = SYS_RESET_N && RESET_AHEAD_DE_N;
+
+`ifdef SIMULATE
+initial
+	begin
+		CLK_CNT = 6'b0;
+	end
+`endif
+
+// 50MHz/32 = 1.5625MHz
+always @ (posedge CLK)
+	CLK_CNT <= CLK_CNT+1;
+
+// 50MHz/32/65536 = 23.84HZ
+always @ (posedge RESET_COUNT_CLK or negedge SYS_RESET_N)
+begin
+	if(~SYS_RESET_N)
+	begin
+		RESET_COUNT <= 17'h00000;
+	end
+	else
+	begin
+		if(RESET_COUNT!=17'h10000)
+			RESET_COUNT <= RESET_COUNT+1;
+
+	end
+end
+
+endmodule
diff --git a/Computer_MiST/Laser310_MiST/rtl/roms/boot_rom_6000.mif b/Computer_MiST/Laser310_MiST/rtl/roms/boot_rom_6000.mif
new file mode 100644
index 00000000..a60543fb
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/roms/boot_rom_6000.mif
@@ -0,0 +1,122 @@
+DEPTH = 115;
+WIDTH = 8;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+0000:AA;
+0001:55;
+0002:E7;
+0003:18;
+0004:AF;
+0005:2A;
+0006:00;
+0007:C0;
+0008:11;
+0009:00;
+000A:80;
+000B:ED;
+000C:52;
+000D:30;
+000E:63;
+000F:3A;
+0010:02;
+0011:C0;
+0012:FE;
+0013:56;
+0014:20;
+0015:18;
+0016:3A;
+0017:03;
+0018:C0;
+0019:FE;
+001A:5A;
+001B:20;
+001C:55;
+001D:3A;
+001E:04;
+001F:C0;
+0020:FE;
+0021:46;
+0022:20;
+0023:4E;
+0024:3A;
+0025:05;
+0026:C0;
+0027:FE;
+0028:20;
+0029:20;
+002A:47;
+002B:C3;
+002C:B7;
+002D:17;
+002E:FE;
+002F:20;
+0030:20;
+0031:40;
+0032:3A;
+0033:03;
+0034:C0;
+0035:FE;
+0036:20;
+0037:20;
+0038:39;
+0039:3A;
+003A:04;
+003B:C0;
+003C:FE;
+003D:00;
+003E:20;
+003F:32;
+0040:3A;
+0041:05;
+0042:C0;
+0043:FE;
+0044:00;
+0045:20;
+0046:2B;
+0047:3A;
+0048:17;
+0049:C0;
+004A:FE;
+004B:F0;
+004C:28;
+004D:07;
+004E:3A;
+004F:17;
+0050:C0;
+0051:FE;
+0052:F1;
+0053:20;
+0054:1D;
+0055:AF;
+0056:2A;
+0057:00;
+0058:C0;
+0059:11;
+005A:18;
+005B:00;
+005C:ED;
+005D:52;
+005E:44;
+005F:4D;
+0060:21;
+0061:1A;
+0062:C0;
+0063:ED;
+0064:5B;
+0065:18;
+0066:C0;
+0067:ED;
+0068:B0;
+0069:AF;
+006A:3E;
+006B:00;
+006C:D3;
+006D:70;
+006E:2A;
+006F:18;
+0070:C0;
+0071:E9;
+0072:76;
+END;
diff --git a/Computer_MiST/Laser310_MiST/rtl/roms/cass_ram.mif b/Computer_MiST/Laser310_MiST/rtl/roms/cass_ram.mif
new file mode 100644
index 00000000..1a8f22b4
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/roms/cass_ram.mif
@@ -0,0 +1,1313 @@
+DEPTH = 1306;
+WIDTH = 8;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+0000:17;
+0001:05;
+0002:8F;
+0003:80;
+0004:80;
+0005:80;
+0006:80;
+0007:80;
+0008:80;
+0009:80;
+000A:80;
+000B:80;
+000C:80;
+000D:80;
+000E:80;
+000F:80;
+0010:80;
+0011:80;
+0012:80;
+0013:80;
+0014:80;
+0015:80;
+0016:80;
+0017:80;
+0018:80;
+0019:80;
+001A:80;
+001B:80;
+001C:80;
+001D:80;
+001E:80;
+001F:80;
+0020:80;
+0021:80;
+0022:80;
+0023:80;
+0024:80;
+0025:80;
+0026:80;
+0027:80;
+0028:80;
+0029:80;
+002A:80;
+002B:80;
+002C:80;
+002D:80;
+002E:80;
+002F:80;
+0030:80;
+0031:80;
+0032:80;
+0033:80;
+0034:80;
+0035:80;
+0036:80;
+0037:80;
+0038:80;
+0039:80;
+003A:80;
+003B:80;
+003C:80;
+003D:80;
+003E:80;
+003F:80;
+0040:80;
+0041:80;
+0042:80;
+0043:80;
+0044:80;
+0045:80;
+0046:80;
+0047:80;
+0048:80;
+0049:80;
+004A:80;
+004B:80;
+004C:80;
+004D:80;
+004E:80;
+004F:80;
+0050:80;
+0051:80;
+0052:80;
+0053:80;
+0054:80;
+0055:80;
+0056:80;
+0057:80;
+0058:80;
+0059:80;
+005A:80;
+005B:80;
+005C:80;
+005D:80;
+005E:80;
+005F:80;
+0060:80;
+0061:80;
+0062:80;
+0063:80;
+0064:80;
+0065:80;
+0066:80;
+0067:80;
+0068:80;
+0069:80;
+006A:80;
+006B:80;
+006C:80;
+006D:80;
+006E:80;
+006F:80;
+0070:80;
+0071:80;
+0072:80;
+0073:80;
+0074:80;
+0075:80;
+0076:80;
+0077:80;
+0078:80;
+0079:80;
+007A:80;
+007B:80;
+007C:80;
+007D:80;
+007E:80;
+007F:80;
+0080:80;
+0081:80;
+0082:80;
+0083:FE;
+0084:FE;
+0085:FE;
+0086:FE;
+0087:FE;
+0088:F1;
+0089:50;
+008A:31;
+008B:2E;
+008C:35;
+008D:43;
+008E:00;
+008F:04;
+0090:7B;
+0091:75;
+0092:7F;
+0093:21;
+0094:74;
+0095:7F;
+0096:11;
+0097:A6;
+0098:79;
+0099:01;
+009A:55;
+009B:00;
+009C:ED;
+009D:B8;
+009E:11;
+009F:7D;
+00A0:78;
+00A1:01;
+00A2:21;
+00A3:00;
+00A4:ED;
+00A5:B8;
+00A6:11;
+00A7:9C;
+00A8:7A;
+00A9:01;
+00AA:64;
+00AB:00;
+00AC:ED;
+00AD:B8;
+00AE:ED;
+00AF:5B;
+00B0:B1;
+00B1:78;
+00B2:01;
+00B3:35;
+00B4:01;
+00B5:ED;
+00B6:B8;
+00B7:ED;
+00B8:53;
+00B9:9E;
+00BA:79;
+00BB:01;
+00BC:58;
+00BD:00;
+00BE:ED;
+00BF:B8;
+00C0:ED;
+00C1:53;
+00C2:86;
+00C3:79;
+00C4:01;
+00C5:7D;
+00C6:00;
+00C7:ED;
+00C8:B8;
+00C9:ED;
+00CA:53;
+00CB:A7;
+00CC:79;
+00CD:01;
+00CE:DC;
+00CF:00;
+00D0:ED;
+00D1:B8;
+00D2:00;
+00D3:ED;
+00D4:53;
+00D5:B1;
+00D6:78;
+00D7:13;
+00D8:ED;
+00D9:53;
+00DA:5E;
+00DB:78;
+00DC:21;
+00DD:CE;
+00DE:FF;
+00DF:19;
+00E0:22;
+00E1:A0;
+00E2:78;
+00E3:2B;
+00E4:F9;
+00E5:21;
+00E6:54;
+00E7:7A;
+00E8:22;
+00E9:D1;
+00EA:79;
+00EB:21;
+00EC:6B;
+00ED:79;
+00EE:22;
+00EF:BC;
+00F0:79;
+00F1:3E;
+00F2:C3;
+00F3:32;
+00F4:BB;
+00F5:79;
+00F6:21;
+00F7:E9;
+00F8:7A;
+00F9:22;
+00FA:A4;
+00FB:78;
+00FC:CD;
+00FD:4A;
+00FE:1B;
+00FF:21;
+0100:86;
+0101:7B;
+0102:CD;
+0103:A7;
+0104:28;
+0105:CD;
+0106:F9;
+0107:20;
+0108:21;
+0109:94;
+010A:7B;
+010B:CD;
+010C:A7;
+010D:28;
+010E:CD;
+010F:F9;
+0110:20;
+0111:C3;
+0112:19;
+0113:1A;
+0114:00;
+0115:4C;
+0116:41;
+0117:53;
+0118:45;
+0119:52;
+011A:20;
+011B:32;
+011C:30;
+011D:30;
+011E:2D;
+011F:33;
+0120:31;
+0121:30;
+0122:00;
+0123:42;
+0124:41;
+0125:53;
+0126:49;
+0127:43;
+0128:20;
+0129:20;
+012A:50;
+012B:31;
+012C:2E;
+012D:35;
+012E:43;
+012F:20;
+0130:20;
+0131:20;
+0132:20;
+0133:20;
+0134:20;
+0135:20;
+0136:20;
+0137:20;
+0138:20;
+0139:20;
+013A:20;
+013B:20;
+013C:20;
+013D:20;
+013E:20;
+013F:20;
+0140:20;
+0141:20;
+0142:20;
+0143:00;
+0144:20;
+0145:55;
+0146:BD;
+0147:07;
+0148:B7;
+0149:33;
+014A:52;
+014B:4F;
+014C:4E;
+014D:07;
+014E:A7;
+014F:33;
+0150:52;
+0151:4F;
+0152:46;
+0153:46;
+0154:07;
+0155:A8;
+0156:23;
+0157:45;
+0158:4C;
+0159:07;
+015A:B6;
+015B:21;
+015C:59;
+015D:45;
+015E:07;
+015F:AE;
+0160:32;
+0161:50;
+0162:45;
+0163:45;
+0164:44;
+0165:07;
+0166:14;
+0167:31;
+0168:45;
+0169:4E;
+016A:55;
+016B:4D;
+016C:07;
+016D:15;
+016E:2F;
+016F:53;
+0170:54;
+0171:07;
+0172:C5;
+0173:2C;
+0174:45;
+0175:52;
+0176:47;
+0177:45;
+0178:07;
+0179:17;
+017A:2B;
+017B:4F;
+017C:4D;
+017D:45;
+017E:4D;
+017F:07;
+0180:1C;
+0181:22;
+0182:41;
+0183:4C;
+0184:4C;
+0185:07;
+0186:18;
+0187:32;
+0188:41;
+0189:56;
+018A:45;
+018B:07;
+018C:1D;
+018D:31;
+018E:53;
+018F:54;
+0190:07;
+0191:19;
+0192:2F;
+0193:4F;
+0194:50;
+0195:07;
+0196:1A;
+0197:31;
+0198:45;
+0199:53;
+019A:55;
+019B:4D;
+019C:45;
+019D:07;
+019E:1B;
+019F:2F;
+01A0:4C;
+01A1:4F;
+01A2:41;
+01A3:44;
+01A4:07;
+01A5:16;
+01A6:2E;
+01A7:4E;
+01A8:45;
+01A9:52;
+01AA:52;
+01AB:07;
+01AC:85;
+01AD:23;
+01AE:45;
+01AF:46;
+01B0:44;
+01B1:42;
+01B2:4C;
+01B3:07;
+01B4:9B;
+01B5:23;
+01B6:45;
+01B7:46;
+01B8:D8;
+01B9:07;
+01BA:99;
+01BB:23;
+01BC:45;
+01BD:46;
+01BE:53;
+01BF:54;
+01C0:52;
+01C1:07;
+01C2:AA;
+01C3:23;
+01C4:45;
+01C5:46;
+01C6:53;
+01C7:4E;
+01C8:47;
+01C9:07;
+01CA:9A;
+01CB:2E;
+01CC:4E;
+01CD:07;
+01CE:A1;
+01CF:24;
+01D0:52;
+01D1:52;
+01D2:D3;
+01D3:07;
+01D4:A9;
+01D5:31;
+01D6:D2;
+01D7:4F;
+01D8:4D;
+01D9:07;
+01DA:86;
+01DB:2C;
+01DC:45;
+01DD:4D;
+01DE:07;
+01DF:C8;
+01E0:25;
+01E1:52;
+01E2:45;
+01E3:07;
+01E4:DA;
+01E5:2B;
+01E6:41;
+01E7:44;
+01E8:07;
+01E9:BE;
+01EA:35;
+01EB:41;
+01EC:52;
+01ED:50;
+01EE:54;
+01EF:52;
+01F0:07;
+01F1:C0;
+01F2:32;
+01F3:54;
+01F4:52;
+01F5:49;
+01F6:4E;
+01F7:47;
+01F8:24;
+01F9:07;
+01FA:C4;
+01FB:2F;
+01FC:4F;
+01FD:53;
+01FE:07;
+01FF:DC;
+0200:24;
+0201:52;
+0202:52;
+0203:07;
+0204:C3;
+0205:24;
+0206:52;
+0207:4C;
+0208:07;
+0209:C2;
+020A:25;
+020B:49;
+020C:58;
+020D:07;
+020E:F2;
+020F:22;
+0210:44;
+0211:42;
+0212:4C;
+0213:07;
+0214:F1;
+0215:22;
+0216:D8;
+0217:07;
+0218:EF;
+0219:22;
+021A:53;
+021B:4E;
+021C:47;
+021D:07;
+021E:F0;
+021F:3D;
+0220:32;
+0221:F2;
+0222:78;
+0223:3E;
+0224:22;
+0225:93;
+0226:20;
+0227:06;
+0228:CD;
+0229:6B;
+022A:79;
+022B:CA;
+022C:19;
+022D:1A;
+022E:D5;
+022F:E5;
+0230:2A;
+0231:EE;
+0232:78;
+0233:7E;
+0234:B7;
+0235:20;
+0236:04;
+0237:01;
+0238:04;
+0239:00;
+023A:09;
+023B:CD;
+023C:5D;
+023D:78;
+023E:20;
+023F:2D;
+0240:FE;
+0241:7F;
+0242:2A;
+0243:AA;
+0244:79;
+0245:45;
+0246:21;
+0247:9A;
+0248:78;
+0249:70;
+024A:2A;
+024B:6F;
+024C:79;
+024D:22;
+024E:EA;
+024F:78;
+0250:EB;
+0251:22;
+0252:E6;
+0253:78;
+0254:C1;
+0255:C1;
+0256:C1;
+0257:D2;
+0258:5B;
+0259:1D;
+025A:11;
+025B:1E;
+025C:1D;
+025D:D5;
+025E:EB;
+025F:2A;
+0260:86;
+0261:79;
+0262:D6;
+0263:14;
+0264:4F;
+0265:06;
+0266:00;
+0267:09;
+0268:4E;
+0269:09;
+026A:E5;
+026B:C3;
+026C:77;
+026D:1D;
+026E:2A;
+026F:9A;
+0270:78;
+0271:22;
+0272:AA;
+0273:79;
+0274:2A;
+0275:EA;
+0276:78;
+0277:22;
+0278:6F;
+0279:79;
+027A:2A;
+027B:EE;
+027C:78;
+027D:22;
+027E:71;
+027F:79;
+0280:2A;
+0281:F0;
+0282:78;
+0283:7C;
+0284:B5;
+0285:EB;
+0286:21;
+0287:2F;
+0288:79;
+0289:28;
+028A:0C;
+028B:A6;
+028C:20;
+028D:09;
+028E:35;
+028F:EB;
+0290:2B;
+0291:C1;
+0292:C1;
+0293:C1;
+0294:C3;
+0295:1E;
+0296:1D;
+0297:AF;
+0298:77;
+0299:E1;
+029A:D1;
+029B:C9;
+029C:0A;
+029D:21;
+029E:81;
+029F:89;
+02A0:B3;
+02A1:BC;
+02A2:C9;
+02A3:E0;
+02A4:ED;
+02A5:EE;
+02A6:CD;
+02A7:5A;
+02A8:1E;
+02A9:E5;
+02AA:21;
+02AB:D0;
+02AC:79;
+02AD:7B;
+02AE:B2;
+02AF:20;
+02B0:05;
+02B1:3E;
+02B2:C9;
+02B3:77;
+02B4:E1;
+02B5:C9;
+02B6:7B;
+02B7:32;
+02B8:56;
+02B9:7A;
+02BA:36;
+02BB:C3;
+02BC:E1;
+02BD:C9;
+02BE:11;
+02BF:0A;
+02C0:00;
+02C1:D5;
+02C2:28;
+02C3:12;
+02C4:FE;
+02C5:2C;
+02C6:28;
+02C7:08;
+02C8:CD;
+02C9:5A;
+02CA:1E;
+02CB:EB;
+02CC:E3;
+02CD:EB;
+02CE:28;
+02CF:06;
+02D0:D7;
+02D1:28;
+02D2:03;
+02D3:CD;
+02D4:5A;
+02D5:1E;
+02D6:E1;
+02D7:D5;
+02D8:EB;
+02D9:2A;
+02DA:A4;
+02DB:78;
+02DC:44;
+02DD:4D;
+02DE:7E;
+02DF:23;
+02E0:B6;
+02E1:CA;
+02E2:19;
+02E3:1A;
+02E4:23;
+02E5:73;
+02E6:23;
+02E7:72;
+02E8:E1;
+02E9:E5;
+02EA:19;
+02EB:EB;
+02EC:60;
+02ED:69;
+02EE:7E;
+02EF:23;
+02F0:66;
+02F1:6F;
+02F2:18;
+02F3:E8;
+02F4:2A;
+02F5:FD;
+02F6:78;
+02F7:E5;
+02F8:23;
+02F9:23;
+02FA:CD;
+02FB:07;
+02FC:1F;
+02FD:23;
+02FE:5E;
+02FF:23;
+0300:56;
+0301:DF;
+0302:30;
+0303:07;
+0304:24;
+0305:DF;
+0306:38;
+0307:05;
+0308:EB;
+0309:18;
+030A:F3;
+030B:7A;
+030C:B3;
+030D:C2;
+030E:4A;
+030F:1E;
+0310:23;
+0311:22;
+0312:F9;
+0313:78;
+0314:E1;
+0315:2B;
+0316:2B;
+0317:74;
+0318:22;
+0319:A4;
+031A:78;
+031B:E5;
+031C:C3;
+031D:E8;
+031E:1A;
+031F:CD;
+0320:77;
+0321:7A;
+0322:CD;
+0323:7D;
+0324:7A;
+0325:C3;
+0326:56;
+0327:36;
+0328:28;
+0329:07;
+032A:CF;
+032B:30;
+032C:2A;
+032D:A4;
+032E:78;
+032F:18;
+0330:05;
+0331:2A;
+0332:F9;
+0333:78;
+0334:2B;
+0335:2B;
+0336:E5;
+0337:ED;
+0338:5B;
+0339:53;
+033A:79;
+033B:7A;
+033C:B7;
+033D:CA;
+033E:97;
+033F:19;
+0340:AF;
+0341:32;
+0342:54;
+0343:79;
+0344:DF;
+0345:D2;
+0346:7A;
+0347:19;
+0348:D5;
+0349:E5;
+034A:2A;
+034B:A1;
+034C:79;
+034D:22;
+034E:F9;
+034F:78;
+0350:C3;
+0351:D9;
+0352:2B;
+0353:CD;
+0354:5A;
+0355:1E;
+0356:E5;
+0357:21;
+0358:90;
+0359:08;
+035A:E5;
+035B:EB;
+035C:E9;
+035D:CD;
+035E:02;
+035F:2B;
+0360:E5;
+0361:CD;
+0362:2C;
+0363:1B;
+0364:0B;
+0365:ED;
+0366:43;
+0367:FF;
+0368:78;
+0369:E1;
+036A:C9;
+036B:D9;
+036C:16;
+036D:FF;
+036E:CD;
+036F:36;
+0370:19;
+0371:F9;
+0372:22;
+0373:E8;
+0374:78;
+0375:FE;
+0376:91;
+0377:C2;
+0378:EA;
+0379:1E;
+037A:C1;
+037B:21;
+037C:1E;
+037D:1D;
+037E:E3;
+037F:D9;
+0380:C3;
+0381:C2;
+0382:1E;
+0383:E5;
+0384:2A;
+0385:71;
+0386:79;
+0387:22;
+0388:EE;
+0389:78;
+038A:E1;
+038B:11;
+038C:2F;
+038D:79;
+038E:C3;
+038F:B2;
+0390:1F;
+0391:18;
+0392:47;
+0393:F3;
+0394:23;
+0395:EB;
+0396:2A;
+0397:F9;
+0398:78;
+0399:E5;
+039A:2A;
+039B:A4;
+039C:78;
+039D:E5;
+039E:01;
+039F:04;
+03A0:7B;
+03A1:ED;
+03A2:42;
+03A3:38;
+03A4:06;
+03A5:FE;
+03A6:42;
+03A7:28;
+03A8:21;
+03A9:FE;
+03AA:41;
+03AB:C2;
+03AC:97;
+03AD:19;
+03AE:E1;
+03AF:E5;
+03B0:22;
+03B1:FC;
+03B2:7A;
+03B3:21;
+03B4:E9;
+03B5:7A;
+03B6:22;
+03B7:A4;
+03B8:78;
+03B9:0E;
+03BA:0E;
+03BB:EB;
+03BC:CD;
+03BD:AC;
+03BE:34;
+03BF:EB;
+03C0:E1;
+03C1:22;
+03C2:A4;
+03C3:78;
+03C4:E1;
+03C5:22;
+03C6:F9;
+03C7:78;
+03C8:EB;
+03C9:C9;
+03CA:E1;
+03CB:E5;
+03CC:2B;
+03CD:22;
+03CE:F9;
+03CF:78;
+03D0:21;
+03D1:04;
+03D2:7B;
+03D3:22;
+03D4:A4;
+03D5:78;
+03D6:0E;
+03D7:F1;
+03D8:18;
+03D9:E1;
+03DA:CA;
+03DB:A0;
+03DC:24;
+03DD:CD;
+03DE:77;
+03DF:7A;
+03E0:CD;
+03E1:5A;
+03E2:1E;
+03E3:21;
+03E4:E9;
+03E5:7A;
+03E6:7A;
+03E7:B3;
+03E8:20;
+03E9:10;
+03EA:ED;
+03EB:5B;
+03EC:A4;
+03ED:78;
+03EE:E5;
+03EF:D5;
+03F0:2B;
+03F1:77;
+03F2:23;
+03F3:22;
+03F4:A4;
+03F5:78;
+03F6:E5;
+03F7:C3;
+03F8:D9;
+03F9:2B;
+03FA:21;
+03FB:03;
+03FC:7B;
+03FD:DF;
+03FE:D2;
+03FF:4A;
+0400:1E;
+0401:21;
+0402:CE;
+0403:FF;
+0404:39;
+0405:DF;
+0406:DA;
+0407:4A;
+0408:1E;
+0409:D5;
+040A:CD;
+040B:7D;
+040C:7A;
+040D:E1;
+040E:DF;
+040F:D2;
+0410:7A;
+0411:19;
+0412:E5;
+0413:D5;
+0414:E5;
+0415:21;
+0416:39;
+0417:7A;
+0418:11;
+0419:E9;
+041A:7A;
+041B:01;
+041C:1B;
+041D:00;
+041E:ED;
+041F:B0;
+0420:2A;
+0421:A1;
+0422:79;
+0423:22;
+0424:F9;
+0425:78;
+0426:E1;
+0427:AF;
+0428:18;
+0429:C6;
+042A:F6;
+042B:7A;
+042C:FF;
+042D:FF;
+042E:43;
+042F:41;
+0430:4C;
+0431:4C;
+0432:33;
+0433:31;
+0434:34;
+0435:38;
+0436:33;
+0437:3A;
+0438:8E;
+0439:00;
+043A:00;
+043B:00;
+043C:21;
+043D:E9;
+043E:7A;
+043F:22;
+0440:A4;
+0441:78;
+0442:C9;
+0443:00;
+0444:00;
+0445:D9;
+0446:06;
+0447:01;
+0448:11;
+0449:00;
+044A:06;
+044B:C5;
+044C:D5;
+044D:CD;
+044E:F4;
+044F:2E;
+0450:FE;
+0451:2E;
+0452:28;
+0453:0B;
+0454:D1;
+0455:1B;
+0456:7A;
+0457:B3;
+0458:20;
+0459:F2;
+045A:C1;
+045B:10;
+045C:EB;
+045D:D9;
+045E:C9;
+045F:00;
+0460:00;
+0461:00;
+0462:C9;
+0463:32;
+0464:D0;
+0465:79;
+0466:D9;
+0467:C9;
+0468:11;
+0469:32;
+046A:00;
+046B:C3;
+046C:83;
+046D:1E;
+046E:E5;
+046F:2A;
+0470:F9;
+0471:78;
+0472:E5;
+0473:ED;
+0474:5B;
+0475:A4;
+0476:78;
+0477:ED;
+0478:52;
+0479:23;
+047A:44;
+047B:4D;
+047C:21;
+047D:CD;
+047E:FF;
+047F:39;
+0480:22;
+0481:A1;
+0482:79;
+0483:D1;
+0484:EB;
+0485:ED;
+0486:B8;
+0487:13;
+0488:ED;
+0489:53;
+048A:53;
+048B:79;
+048C:E1;
+048D:C9;
+048E:11;
+048F:00;
+0490:00;
+0491:01;
+0492:DB;
+0493:00;
+0494:D7;
+0495:EB;
+0496:D6;
+0497:21;
+0498:ED;
+0499:B1;
+049A:C0;
+049B:D5;
+049C:13;
+049D:1A;
+049E:BE;
+049F:28;
+04A0:04;
+04A1:D1;
+04A2:1A;
+04A3:18;
+04A4:F1;
+04A5:23;
+04A6:7E;
+04A7:FE;
+04A8:07;
+04A9:20;
+04AA:F1;
+04AB:23;
+04AC:7E;
+04AD:C1;
+04AE:C9;
+04AF:C9;
+04B0:00;
+04B1:00;
+04B2:D7;
+04B3:CF;
+04B4:28;
+04B5:CD;
+04B6:02;
+04B7:2B;
+04B8:E5;
+04B9:CD;
+04BA:2C;
+04BB:1B;
+04BC:D2;
+04BD:D9;
+04BE:1E;
+04BF:60;
+04C0:69;
+04C1:CD;
+04C2:9A;
+04C3:0A;
+04C4:E1;
+04C5:C3;
+04C6:2F;
+04C7:25;
+04C8:32;
+04C9:2F;
+04CA:79;
+04CB:C9;
+04CC:00;
+04CD:00;
+04CE:00;
+04CF:00;
+04D0:E5;
+04D1:D7;
+04D2:21;
+04D3:FF;
+04D4:00;
+04D5:FE;
+04D6:30;
+04D7:20;
+04D8:03;
+04D9:2A;
+04DA:2F;
+04DB:79;
+04DC:22;
+04DD:F2;
+04DE:78;
+04DF:E1;
+04E0:C3;
+04E1:71;
+04E2:1F;
+04E3:00;
+04E4:00;
+04E5:C3;
+04E6:F7;
+04E7:1D;
+04E8:C3;
+04E9:F9;
+04EA:1D;
+04EB:C3;
+04EC:F4;
+04ED:1F;
+04EE:C3;
+04EF:00;
+04F0:1E;
+04F1:CD;
+04F2:5D;
+04F3:78;
+04F4:C2;
+04F5:97;
+04F6:19;
+04F7:EB;
+04F8:18;
+04F9:06;
+04FA:C3;
+04FB:7D;
+04FC:B4;
+04FD:C9;
+04FE:00;
+04FF:00;
+0500:C3;
+0501:CB;
+0502:24;
+0503:C3;
+0504:57;
+0505:DE;
+0506:00;
+0507:00;
+0508:00;
+0509:00;
+050A:00;
+050B:00;
+050C:00;
+050D:00;
+050E:00;
+050F:00;
+0510:00;
+0511:00;
+0512:00;
+0513:00;
+0514:00;
+0515:00;
+0516:00;
+0517:00;
+0518:00;
+0519:00;
+END;
diff --git a/Computer_MiST/Laser310_MiST/rtl/roms/charrom.mif b/Computer_MiST/Laser310_MiST/rtl/roms/charrom.mif
new file mode 100644
index 00000000..e5c8c283
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/roms/charrom.mif
@@ -0,0 +1,3079 @@
+DEPTH = 3072;
+WIDTH = 8;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+0000:00;
+0001:1C;
+0002:22;
+0003:20;
+0004:2C;
+0005:32;
+0006:32;
+0007:1C;
+0008:00;
+0009:00;
+000A:00;
+000B:00;
+000C:00;
+000D:08;
+000E:14;
+000F:22;
+0010:22;
+0011:3E;
+0012:22;
+0013:22;
+0014:00;
+0015:00;
+0016:00;
+0017:00;
+0018:00;
+0019:1E;
+001A:24;
+001B:24;
+001C:1C;
+001D:24;
+001E:24;
+001F:1E;
+0020:00;
+0021:00;
+0022:00;
+0023:00;
+0024:00;
+0025:1C;
+0026:22;
+0027:02;
+0028:02;
+0029:02;
+002A:22;
+002B:1C;
+002C:00;
+002D:00;
+002E:00;
+002F:00;
+0030:00;
+0031:1E;
+0032:24;
+0033:24;
+0034:24;
+0035:24;
+0036:24;
+0037:1E;
+0038:00;
+0039:00;
+003A:00;
+003B:00;
+003C:00;
+003D:3E;
+003E:02;
+003F:02;
+0040:0E;
+0041:02;
+0042:02;
+0043:3E;
+0044:00;
+0045:00;
+0046:00;
+0047:00;
+0048:00;
+0049:3E;
+004A:02;
+004B:02;
+004C:1E;
+004D:02;
+004E:02;
+004F:02;
+0050:00;
+0051:00;
+0052:00;
+0053:00;
+0054:00;
+0055:3C;
+0056:02;
+0057:02;
+0058:32;
+0059:22;
+005A:22;
+005B:3C;
+005C:00;
+005D:00;
+005E:00;
+005F:00;
+0060:00;
+0061:22;
+0062:22;
+0063:22;
+0064:3E;
+0065:22;
+0066:22;
+0067:22;
+0068:00;
+0069:00;
+006A:00;
+006B:00;
+006C:00;
+006D:1C;
+006E:08;
+006F:08;
+0070:08;
+0071:08;
+0072:08;
+0073:1C;
+0074:00;
+0075:00;
+0076:00;
+0077:00;
+0078:00;
+0079:20;
+007A:20;
+007B:20;
+007C:20;
+007D:22;
+007E:22;
+007F:1C;
+0080:00;
+0081:00;
+0082:00;
+0083:00;
+0084:00;
+0085:22;
+0086:12;
+0087:0A;
+0088:06;
+0089:0A;
+008A:12;
+008B:22;
+008C:00;
+008D:00;
+008E:00;
+008F:00;
+0090:00;
+0091:02;
+0092:02;
+0093:02;
+0094:02;
+0095:02;
+0096:02;
+0097:3E;
+0098:00;
+0099:00;
+009A:00;
+009B:00;
+009C:00;
+009D:22;
+009E:36;
+009F:3E;
+00A0:2A;
+00A1:22;
+00A2:22;
+00A3:22;
+00A4:00;
+00A5:00;
+00A6:00;
+00A7:00;
+00A8:00;
+00A9:22;
+00AA:22;
+00AB:26;
+00AC:2A;
+00AD:32;
+00AE:22;
+00AF:22;
+00B0:00;
+00B1:00;
+00B2:00;
+00B3:00;
+00B4:00;
+00B5:3E;
+00B6:22;
+00B7:22;
+00B8:22;
+00B9:22;
+00BA:22;
+00BB:3E;
+00BC:00;
+00BD:00;
+00BE:00;
+00BF:00;
+00C0:00;
+00C1:1E;
+00C2:22;
+00C3:22;
+00C4:1E;
+00C5:02;
+00C6:02;
+00C7:02;
+00C8:00;
+00C9:00;
+00CA:00;
+00CB:00;
+00CC:00;
+00CD:1C;
+00CE:22;
+00CF:22;
+00D0:22;
+00D1:2A;
+00D2:12;
+00D3:2C;
+00D4:00;
+00D5:00;
+00D6:00;
+00D7:00;
+00D8:00;
+00D9:1E;
+00DA:22;
+00DB:22;
+00DC:1E;
+00DD:0A;
+00DE:12;
+00DF:22;
+00E0:00;
+00E1:00;
+00E2:00;
+00E3:00;
+00E4:00;
+00E5:1C;
+00E6:22;
+00E7:04;
+00E8:08;
+00E9:10;
+00EA:22;
+00EB:1C;
+00EC:00;
+00ED:00;
+00EE:00;
+00EF:00;
+00F0:00;
+00F1:3E;
+00F2:08;
+00F3:08;
+00F4:08;
+00F5:08;
+00F6:08;
+00F7:08;
+00F8:00;
+00F9:00;
+00FA:00;
+00FB:00;
+00FC:00;
+00FD:22;
+00FE:22;
+00FF:22;
+0100:22;
+0101:22;
+0102:22;
+0103:1C;
+0104:00;
+0105:00;
+0106:00;
+0107:00;
+0108:00;
+0109:22;
+010A:22;
+010B:22;
+010C:14;
+010D:14;
+010E:08;
+010F:08;
+0110:00;
+0111:00;
+0112:00;
+0113:00;
+0114:00;
+0115:22;
+0116:22;
+0117:22;
+0118:2A;
+0119:3E;
+011A:36;
+011B:22;
+011C:00;
+011D:00;
+011E:00;
+011F:00;
+0120:00;
+0121:22;
+0122:22;
+0123:14;
+0124:08;
+0125:14;
+0126:22;
+0127:22;
+0128:00;
+0129:00;
+012A:00;
+012B:00;
+012C:00;
+012D:22;
+012E:22;
+012F:14;
+0130:08;
+0131:08;
+0132:08;
+0133:08;
+0134:00;
+0135:00;
+0136:00;
+0137:00;
+0138:00;
+0139:3E;
+013A:20;
+013B:10;
+013C:08;
+013D:04;
+013E:02;
+013F:3E;
+0140:00;
+0141:00;
+0142:00;
+0143:00;
+0144:00;
+0145:1C;
+0146:04;
+0147:04;
+0148:04;
+0149:04;
+014A:04;
+014B:1C;
+014C:00;
+014D:00;
+014E:00;
+014F:00;
+0150:00;
+0151:00;
+0152:02;
+0153:04;
+0154:08;
+0155:10;
+0156:20;
+0157:00;
+0158:00;
+0159:00;
+015A:00;
+015B:00;
+015C:00;
+015D:1C;
+015E:10;
+015F:10;
+0160:10;
+0161:10;
+0162:10;
+0163:1C;
+0164:00;
+0165:00;
+0166:00;
+0167:00;
+0168:00;
+0169:08;
+016A:1C;
+016B:2A;
+016C:08;
+016D:08;
+016E:08;
+016F:08;
+0170:00;
+0171:00;
+0172:00;
+0173:00;
+0174:00;
+0175:00;
+0176:08;
+0177:04;
+0178:3E;
+0179:04;
+017A:08;
+017B:00;
+017C:00;
+017D:00;
+017E:00;
+017F:00;
+0180:00;
+0181:00;
+0182:00;
+0183:00;
+0184:00;
+0185:00;
+0186:00;
+0187:00;
+0188:00;
+0189:00;
+018A:00;
+018B:00;
+018C:00;
+018D:08;
+018E:08;
+018F:08;
+0190:08;
+0191:08;
+0192:00;
+0193:08;
+0194:00;
+0195:00;
+0196:00;
+0197:00;
+0198:00;
+0199:14;
+019A:14;
+019B:00;
+019C:00;
+019D:00;
+019E:00;
+019F:00;
+01A0:00;
+01A1:00;
+01A2:00;
+01A3:00;
+01A4:00;
+01A5:14;
+01A6:14;
+01A7:3E;
+01A8:14;
+01A9:3E;
+01AA:14;
+01AB:14;
+01AC:00;
+01AD:00;
+01AE:00;
+01AF:00;
+01B0:00;
+01B1:08;
+01B2:3C;
+01B3:02;
+01B4:1C;
+01B5:20;
+01B6:1E;
+01B7:08;
+01B8:00;
+01B9:00;
+01BA:00;
+01BB:00;
+01BC:00;
+01BD:26;
+01BE:26;
+01BF:10;
+01C0:08;
+01C1:04;
+01C2:32;
+01C3:32;
+01C4:00;
+01C5:00;
+01C6:00;
+01C7:00;
+01C8:00;
+01C9:04;
+01CA:0A;
+01CB:0A;
+01CC:04;
+01CD:2A;
+01CE:12;
+01CF:2C;
+01D0:00;
+01D1:00;
+01D2:00;
+01D3:00;
+01D4:00;
+01D5:08;
+01D6:08;
+01D7:00;
+01D8:00;
+01D9:00;
+01DA:00;
+01DB:00;
+01DC:00;
+01DD:00;
+01DE:00;
+01DF:00;
+01E0:00;
+01E1:10;
+01E2:08;
+01E3:04;
+01E4:04;
+01E5:04;
+01E6:08;
+01E7:10;
+01E8:00;
+01E9:00;
+01EA:00;
+01EB:00;
+01EC:00;
+01ED:04;
+01EE:08;
+01EF:10;
+01F0:10;
+01F1:10;
+01F2:08;
+01F3:04;
+01F4:00;
+01F5:00;
+01F6:00;
+01F7:00;
+01F8:00;
+01F9:00;
+01FA:08;
+01FB:1C;
+01FC:3E;
+01FD:1C;
+01FE:08;
+01FF:00;
+0200:00;
+0201:00;
+0202:00;
+0203:00;
+0204:00;
+0205:00;
+0206:08;
+0207:08;
+0208:3E;
+0209:08;
+020A:08;
+020B:00;
+020C:00;
+020D:00;
+020E:00;
+020F:00;
+0210:00;
+0211:00;
+0212:00;
+0213:00;
+0214:00;
+0215:0C;
+0216:0C;
+0217:08;
+0218:04;
+0219:00;
+021A:00;
+021B:00;
+021C:00;
+021D:00;
+021E:00;
+021F:00;
+0220:3E;
+0221:00;
+0222:00;
+0223:00;
+0224:00;
+0225:00;
+0226:00;
+0227:00;
+0228:00;
+0229:00;
+022A:00;
+022B:00;
+022C:00;
+022D:00;
+022E:0C;
+022F:0C;
+0230:00;
+0231:00;
+0232:00;
+0233:00;
+0234:00;
+0235:00;
+0236:20;
+0237:10;
+0238:08;
+0239:04;
+023A:02;
+023B:00;
+023C:00;
+023D:00;
+023E:00;
+023F:00;
+0240:00;
+0241:0C;
+0242:12;
+0243:12;
+0244:12;
+0245:12;
+0246:12;
+0247:0C;
+0248:00;
+0249:00;
+024A:00;
+024B:00;
+024C:00;
+024D:08;
+024E:0C;
+024F:08;
+0250:08;
+0251:08;
+0252:08;
+0253:1C;
+0254:00;
+0255:00;
+0256:00;
+0257:00;
+0258:00;
+0259:1C;
+025A:22;
+025B:20;
+025C:1C;
+025D:02;
+025E:02;
+025F:3E;
+0260:00;
+0261:00;
+0262:00;
+0263:00;
+0264:00;
+0265:1C;
+0266:22;
+0267:20;
+0268:1C;
+0269:20;
+026A:22;
+026B:1C;
+026C:00;
+026D:00;
+026E:00;
+026F:00;
+0270:00;
+0271:10;
+0272:18;
+0273:14;
+0274:3E;
+0275:10;
+0276:10;
+0277:10;
+0278:00;
+0279:00;
+027A:00;
+027B:00;
+027C:00;
+027D:3E;
+027E:02;
+027F:1E;
+0280:20;
+0281:20;
+0282:22;
+0283:1C;
+0284:00;
+0285:00;
+0286:00;
+0287:00;
+0288:00;
+0289:1C;
+028A:02;
+028B:02;
+028C:1E;
+028D:22;
+028E:22;
+028F:1C;
+0290:00;
+0291:00;
+0292:00;
+0293:00;
+0294:00;
+0295:3E;
+0296:20;
+0297:10;
+0298:08;
+0299:04;
+029A:02;
+029B:02;
+029C:00;
+029D:00;
+029E:00;
+029F:00;
+02A0:00;
+02A1:1C;
+02A2:22;
+02A3:22;
+02A4:1C;
+02A5:22;
+02A6:22;
+02A7:1C;
+02A8:00;
+02A9:00;
+02AA:00;
+02AB:00;
+02AC:00;
+02AD:1C;
+02AE:22;
+02AF:22;
+02B0:3C;
+02B1:20;
+02B2:20;
+02B3:1C;
+02B4:00;
+02B5:00;
+02B6:00;
+02B7:00;
+02B8:00;
+02B9:00;
+02BA:0C;
+02BB:0C;
+02BC:00;
+02BD:0C;
+02BE:0C;
+02BF:00;
+02C0:00;
+02C1:00;
+02C2:00;
+02C3:00;
+02C4:00;
+02C5:00;
+02C6:0C;
+02C7:0C;
+02C8:00;
+02C9:0C;
+02CA:0C;
+02CB:08;
+02CC:04;
+02CD:00;
+02CE:00;
+02CF:00;
+02D0:00;
+02D1:20;
+02D2:10;
+02D3:08;
+02D4:04;
+02D5:08;
+02D6:10;
+02D7:20;
+02D8:00;
+02D9:00;
+02DA:00;
+02DB:00;
+02DC:00;
+02DD:00;
+02DE:00;
+02DF:3E;
+02E0:00;
+02E1:3E;
+02E2:00;
+02E3:00;
+02E4:00;
+02E5:00;
+02E6:00;
+02E7:00;
+02E8:00;
+02E9:04;
+02EA:08;
+02EB:10;
+02EC:20;
+02ED:10;
+02EE:08;
+02EF:04;
+02F0:00;
+02F1:00;
+02F2:00;
+02F3:00;
+02F4:00;
+02F5:1C;
+02F6:22;
+02F7:20;
+02F8:10;
+02F9:08;
+02FA:00;
+02FB:08;
+02FC:00;
+02FD:00;
+02FE:00;
+02FF:00;
+0300:FF;
+0301:E3;
+0302:DD;
+0303:DF;
+0304:D3;
+0305:CD;
+0306:CD;
+0307:E3;
+0308:FF;
+0309:FF;
+030A:FF;
+030B:FF;
+030C:FF;
+030D:F7;
+030E:EB;
+030F:DD;
+0310:DD;
+0311:C1;
+0312:DD;
+0313:DD;
+0314:FF;
+0315:FF;
+0316:FF;
+0317:FF;
+0318:FF;
+0319:E1;
+031A:DB;
+031B:DB;
+031C:E3;
+031D:DB;
+031E:DB;
+031F:E1;
+0320:FF;
+0321:FF;
+0322:FF;
+0323:FF;
+0324:FF;
+0325:E3;
+0326:DD;
+0327:FD;
+0328:FD;
+0329:FD;
+032A:DD;
+032B:E3;
+032C:FF;
+032D:FF;
+032E:FF;
+032F:FF;
+0330:FF;
+0331:E1;
+0332:DB;
+0333:DB;
+0334:DB;
+0335:DB;
+0336:DB;
+0337:E1;
+0338:FF;
+0339:FF;
+033A:FF;
+033B:FF;
+033C:FF;
+033D:C1;
+033E:FD;
+033F:FD;
+0340:F1;
+0341:FD;
+0342:FD;
+0343:C1;
+0344:FF;
+0345:FF;
+0346:FF;
+0347:FF;
+0348:FF;
+0349:C1;
+034A:FD;
+034B:FD;
+034C:E1;
+034D:FD;
+034E:FD;
+034F:FD;
+0350:FF;
+0351:FF;
+0352:FF;
+0353:FF;
+0354:FF;
+0355:C3;
+0356:FD;
+0357:FD;
+0358:CD;
+0359:DD;
+035A:DD;
+035B:C3;
+035C:FF;
+035D:FF;
+035E:FF;
+035F:FF;
+0360:FF;
+0361:DD;
+0362:DD;
+0363:DD;
+0364:C1;
+0365:DD;
+0366:DD;
+0367:DD;
+0368:FF;
+0369:FF;
+036A:FF;
+036B:FF;
+036C:FF;
+036D:E3;
+036E:F7;
+036F:F7;
+0370:F7;
+0371:F7;
+0372:F7;
+0373:E3;
+0374:FF;
+0375:FF;
+0376:FF;
+0377:FF;
+0378:FF;
+0379:DF;
+037A:DF;
+037B:DF;
+037C:DF;
+037D:DD;
+037E:DD;
+037F:E3;
+0380:FF;
+0381:FF;
+0382:FF;
+0383:FF;
+0384:FF;
+0385:DD;
+0386:ED;
+0387:F5;
+0388:F9;
+0389:F5;
+038A:ED;
+038B:DD;
+038C:FF;
+038D:FF;
+038E:FF;
+038F:FF;
+0390:FF;
+0391:FD;
+0392:FD;
+0393:FD;
+0394:FD;
+0395:FD;
+0396:FD;
+0397:C1;
+0398:FF;
+0399:FF;
+039A:FF;
+039B:FF;
+039C:FF;
+039D:DD;
+039E:C9;
+039F:C1;
+03A0:D5;
+03A1:DD;
+03A2:DD;
+03A3:DD;
+03A4:FF;
+03A5:FF;
+03A6:FF;
+03A7:FF;
+03A8:FF;
+03A9:DD;
+03AA:DD;
+03AB:D9;
+03AC:D5;
+03AD:CD;
+03AE:DD;
+03AF:DD;
+03B0:FF;
+03B1:FF;
+03B2:FF;
+03B3:FF;
+03B4:FF;
+03B5:C1;
+03B6:DD;
+03B7:DD;
+03B8:DD;
+03B9:DD;
+03BA:DD;
+03BB:C1;
+03BC:FF;
+03BD:FF;
+03BE:FF;
+03BF:FF;
+03C0:FF;
+03C1:E1;
+03C2:DD;
+03C3:DD;
+03C4:E1;
+03C5:FD;
+03C6:FD;
+03C7:FD;
+03C8:FF;
+03C9:FF;
+03CA:FF;
+03CB:FF;
+03CC:FF;
+03CD:E3;
+03CE:DD;
+03CF:DD;
+03D0:DD;
+03D1:D5;
+03D2:ED;
+03D3:D3;
+03D4:FF;
+03D5:FF;
+03D6:FF;
+03D7:FF;
+03D8:FF;
+03D9:E1;
+03DA:DD;
+03DB:DD;
+03DC:E1;
+03DD:F5;
+03DE:ED;
+03DF:DD;
+03E0:FF;
+03E1:FF;
+03E2:FF;
+03E3:FF;
+03E4:FF;
+03E5:E3;
+03E6:DD;
+03E7:FB;
+03E8:F7;
+03E9:EF;
+03EA:DD;
+03EB:E3;
+03EC:FF;
+03ED:FF;
+03EE:FF;
+03EF:FF;
+03F0:FF;
+03F1:C1;
+03F2:F7;
+03F3:F7;
+03F4:F7;
+03F5:F7;
+03F6:F7;
+03F7:F7;
+03F8:FF;
+03F9:FF;
+03FA:FF;
+03FB:FF;
+03FC:FF;
+03FD:DD;
+03FE:DD;
+03FF:DD;
+0400:DD;
+0401:DD;
+0402:DD;
+0403:E3;
+0404:FF;
+0405:FF;
+0406:FF;
+0407:FF;
+0408:FF;
+0409:DD;
+040A:DD;
+040B:DD;
+040C:EB;
+040D:EB;
+040E:F7;
+040F:F7;
+0410:FF;
+0411:FF;
+0412:FF;
+0413:FF;
+0414:FF;
+0415:DD;
+0416:DD;
+0417:DD;
+0418:D5;
+0419:C1;
+041A:C9;
+041B:DD;
+041C:FF;
+041D:FF;
+041E:FF;
+041F:FF;
+0420:FF;
+0421:DD;
+0422:DD;
+0423:EB;
+0424:F7;
+0425:EB;
+0426:DD;
+0427:DD;
+0428:FF;
+0429:FF;
+042A:FF;
+042B:FF;
+042C:FF;
+042D:DD;
+042E:DD;
+042F:EB;
+0430:F7;
+0431:F7;
+0432:F7;
+0433:F7;
+0434:FF;
+0435:FF;
+0436:FF;
+0437:FF;
+0438:FF;
+0439:C1;
+043A:DF;
+043B:EF;
+043C:F7;
+043D:FB;
+043E:FD;
+043F:C1;
+0440:FF;
+0441:FF;
+0442:FF;
+0443:FF;
+0444:FF;
+0445:E3;
+0446:FB;
+0447:FB;
+0448:FB;
+0449:FB;
+044A:FB;
+044B:E3;
+044C:FF;
+044D:FF;
+044E:FF;
+044F:FF;
+0450:FF;
+0451:FF;
+0452:FD;
+0453:FB;
+0454:F7;
+0455:EF;
+0456:DF;
+0457:FF;
+0458:FF;
+0459:FF;
+045A:FF;
+045B:FF;
+045C:FF;
+045D:E3;
+045E:EF;
+045F:EF;
+0460:EF;
+0461:EF;
+0462:EF;
+0463:E3;
+0464:FF;
+0465:FF;
+0466:FF;
+0467:FF;
+0468:FF;
+0469:F7;
+046A:E3;
+046B:D5;
+046C:F7;
+046D:F7;
+046E:F7;
+046F:F7;
+0470:FF;
+0471:FF;
+0472:FF;
+0473:FF;
+0474:FF;
+0475:FF;
+0476:F7;
+0477:FB;
+0478:C1;
+0479:FB;
+047A:F7;
+047B:FF;
+047C:FF;
+047D:FF;
+047E:FF;
+047F:FF;
+0480:FF;
+0481:FF;
+0482:FF;
+0483:FF;
+0484:FF;
+0485:FF;
+0486:FF;
+0487:FF;
+0488:FF;
+0489:FF;
+048A:FF;
+048B:FF;
+048C:FF;
+048D:F7;
+048E:F7;
+048F:F7;
+0490:F7;
+0491:F7;
+0492:FF;
+0493:F7;
+0494:FF;
+0495:FF;
+0496:FF;
+0497:FF;
+0498:FF;
+0499:EB;
+049A:EB;
+049B:FF;
+049C:FF;
+049D:FF;
+049E:FF;
+049F:FF;
+04A0:FF;
+04A1:FF;
+04A2:FF;
+04A3:FF;
+04A4:FF;
+04A5:EB;
+04A6:EB;
+04A7:C1;
+04A8:EB;
+04A9:C1;
+04AA:EB;
+04AB:EB;
+04AC:FF;
+04AD:FF;
+04AE:FF;
+04AF:FF;
+04B0:FF;
+04B1:F7;
+04B2:C3;
+04B3:FD;
+04B4:E3;
+04B5:DF;
+04B6:E1;
+04B7:F7;
+04B8:FF;
+04B9:FF;
+04BA:FF;
+04BB:FF;
+04BC:FF;
+04BD:D9;
+04BE:D9;
+04BF:EF;
+04C0:F7;
+04C1:FB;
+04C2:CD;
+04C3:CD;
+04C4:FF;
+04C5:FF;
+04C6:FF;
+04C7:FF;
+04C8:FF;
+04C9:FB;
+04CA:F5;
+04CB:F5;
+04CC:FB;
+04CD:D5;
+04CE:ED;
+04CF:D3;
+04D0:FF;
+04D1:FF;
+04D2:FF;
+04D3:FF;
+04D4:FF;
+04D5:F7;
+04D6:F7;
+04D7:FF;
+04D8:FF;
+04D9:FF;
+04DA:FF;
+04DB:FF;
+04DC:FF;
+04DD:FF;
+04DE:FF;
+04DF:FF;
+04E0:FF;
+04E1:EF;
+04E2:F7;
+04E3:FB;
+04E4:FB;
+04E5:FB;
+04E6:F7;
+04E7:EF;
+04E8:FF;
+04E9:FF;
+04EA:FF;
+04EB:FF;
+04EC:FF;
+04ED:FB;
+04EE:F7;
+04EF:EF;
+04F0:EF;
+04F1:EF;
+04F2:F7;
+04F3:FB;
+04F4:FF;
+04F5:FF;
+04F6:FF;
+04F7:FF;
+04F8:FF;
+04F9:FF;
+04FA:F7;
+04FB:E3;
+04FC:C1;
+04FD:E3;
+04FE:F7;
+04FF:FF;
+0500:FF;
+0501:FF;
+0502:FF;
+0503:FF;
+0504:FF;
+0505:FF;
+0506:F7;
+0507:F7;
+0508:C1;
+0509:F7;
+050A:F7;
+050B:FF;
+050C:FF;
+050D:FF;
+050E:FF;
+050F:FF;
+0510:FF;
+0511:FF;
+0512:FF;
+0513:FF;
+0514:FF;
+0515:F3;
+0516:F3;
+0517:F7;
+0518:FB;
+0519:FF;
+051A:FF;
+051B:FF;
+051C:FF;
+051D:FF;
+051E:FF;
+051F:FF;
+0520:C1;
+0521:FF;
+0522:FF;
+0523:FF;
+0524:FF;
+0525:FF;
+0526:FF;
+0527:FF;
+0528:FF;
+0529:FF;
+052A:FF;
+052B:FF;
+052C:FF;
+052D:FF;
+052E:F3;
+052F:F3;
+0530:FF;
+0531:FF;
+0532:FF;
+0533:FF;
+0534:FF;
+0535:FF;
+0536:DF;
+0537:EF;
+0538:F7;
+0539:FB;
+053A:FD;
+053B:FF;
+053C:FF;
+053D:FF;
+053E:FF;
+053F:FF;
+0540:FF;
+0541:F3;
+0542:ED;
+0543:ED;
+0544:ED;
+0545:ED;
+0546:ED;
+0547:F3;
+0548:FF;
+0549:FF;
+054A:FF;
+054B:FF;
+054C:FF;
+054D:F7;
+054E:F3;
+054F:F7;
+0550:F7;
+0551:F7;
+0552:F7;
+0553:E3;
+0554:FF;
+0555:FF;
+0556:FF;
+0557:FF;
+0558:FF;
+0559:E3;
+055A:DD;
+055B:DF;
+055C:E3;
+055D:FD;
+055E:FD;
+055F:C1;
+0560:FF;
+0561:FF;
+0562:FF;
+0563:FF;
+0564:FF;
+0565:E3;
+0566:DD;
+0567:DF;
+0568:E3;
+0569:DF;
+056A:DD;
+056B:E3;
+056C:FF;
+056D:FF;
+056E:FF;
+056F:FF;
+0570:FF;
+0571:EF;
+0572:E7;
+0573:EB;
+0574:C1;
+0575:EF;
+0576:EF;
+0577:EF;
+0578:FF;
+0579:FF;
+057A:FF;
+057B:FF;
+057C:FF;
+057D:C1;
+057E:FD;
+057F:E1;
+0580:DF;
+0581:DF;
+0582:DD;
+0583:E3;
+0584:FF;
+0585:FF;
+0586:FF;
+0587:FF;
+0588:FF;
+0589:E3;
+058A:FD;
+058B:FD;
+058C:E1;
+058D:DD;
+058E:DD;
+058F:E3;
+0590:FF;
+0591:FF;
+0592:FF;
+0593:FF;
+0594:FF;
+0595:C1;
+0596:DF;
+0597:EF;
+0598:F7;
+0599:FB;
+059A:FD;
+059B:FD;
+059C:FF;
+059D:FF;
+059E:FF;
+059F:FF;
+05A0:FF;
+05A1:E3;
+05A2:DD;
+05A3:DD;
+05A4:E3;
+05A5:DD;
+05A6:DD;
+05A7:E3;
+05A8:FF;
+05A9:FF;
+05AA:FF;
+05AB:FF;
+05AC:FF;
+05AD:E3;
+05AE:DD;
+05AF:DD;
+05B0:C3;
+05B1:DF;
+05B2:DF;
+05B3:E3;
+05B4:FF;
+05B5:FF;
+05B6:FF;
+05B7:FF;
+05B8:FF;
+05B9:FF;
+05BA:F3;
+05BB:F3;
+05BC:FF;
+05BD:F3;
+05BE:F3;
+05BF:FF;
+05C0:FF;
+05C1:FF;
+05C2:FF;
+05C3:FF;
+05C4:FF;
+05C5:FF;
+05C6:F3;
+05C7:F3;
+05C8:FF;
+05C9:F3;
+05CA:F3;
+05CB:F7;
+05CC:FB;
+05CD:FF;
+05CE:FF;
+05CF:FF;
+05D0:FF;
+05D1:DF;
+05D2:EF;
+05D3:F7;
+05D4:FB;
+05D5:F7;
+05D6:EF;
+05D7:DF;
+05D8:FF;
+05D9:FF;
+05DA:FF;
+05DB:FF;
+05DC:FF;
+05DD:FF;
+05DE:FF;
+05DF:C1;
+05E0:FF;
+05E1:C1;
+05E2:FF;
+05E3:FF;
+05E4:FF;
+05E5:FF;
+05E6:FF;
+05E7:FF;
+05E8:FF;
+05E9:FB;
+05EA:F7;
+05EB:EF;
+05EC:DF;
+05ED:EF;
+05EE:F7;
+05EF:FB;
+05F0:FF;
+05F1:FF;
+05F2:FF;
+05F3:FF;
+05F4:FF;
+05F5:E3;
+05F6:DD;
+05F7:DF;
+05F8:EF;
+05F9:F7;
+05FA:FF;
+05FB:F7;
+05FC:FF;
+05FD:FF;
+05FE:FF;
+05FF:FF;
+0600:00;
+0601:00;
+0602:00;
+0603:00;
+0604:00;
+0605:00;
+0606:00;
+0607:00;
+0608:00;
+0609:00;
+060A:00;
+060B:00;
+060C:00;
+060D:00;
+060E:00;
+060F:00;
+0610:00;
+0611:00;
+0612:F0;
+0613:F0;
+0614:F0;
+0615:F0;
+0616:F0;
+0617:F0;
+0618:00;
+0619:00;
+061A:00;
+061B:00;
+061C:00;
+061D:00;
+061E:0F;
+061F:0F;
+0620:0F;
+0621:0F;
+0622:0F;
+0623:0F;
+0624:00;
+0625:00;
+0626:00;
+0627:00;
+0628:00;
+0629:00;
+062A:FF;
+062B:FF;
+062C:FF;
+062D:FF;
+062E:FF;
+062F:FF;
+0630:F0;
+0631:F0;
+0632:F0;
+0633:F0;
+0634:F0;
+0635:F0;
+0636:00;
+0637:00;
+0638:00;
+0639:00;
+063A:00;
+063B:00;
+063C:F0;
+063D:F0;
+063E:F0;
+063F:F0;
+0640:F0;
+0641:F0;
+0642:F0;
+0643:F0;
+0644:F0;
+0645:F0;
+0646:F0;
+0647:F0;
+0648:F0;
+0649:F0;
+064A:F0;
+064B:F0;
+064C:F0;
+064D:F0;
+064E:0F;
+064F:0F;
+0650:0F;
+0651:0F;
+0652:0F;
+0653:0F;
+0654:F0;
+0655:F0;
+0656:F0;
+0657:F0;
+0658:F0;
+0659:F0;
+065A:FF;
+065B:FF;
+065C:FF;
+065D:FF;
+065E:FF;
+065F:FF;
+0660:0F;
+0661:0F;
+0662:0F;
+0663:0F;
+0664:0F;
+0665:0F;
+0666:00;
+0667:00;
+0668:00;
+0669:00;
+066A:00;
+066B:00;
+066C:0F;
+066D:0F;
+066E:0F;
+066F:0F;
+0670:0F;
+0671:0F;
+0672:F0;
+0673:F0;
+0674:F0;
+0675:F0;
+0676:F0;
+0677:F0;
+0678:0F;
+0679:0F;
+067A:0F;
+067B:0F;
+067C:0F;
+067D:0F;
+067E:0F;
+067F:0F;
+0680:0F;
+0681:0F;
+0682:0F;
+0683:0F;
+0684:0F;
+0685:0F;
+0686:0F;
+0687:0F;
+0688:0F;
+0689:0F;
+068A:FF;
+068B:FF;
+068C:FF;
+068D:FF;
+068E:FF;
+068F:FF;
+0690:FF;
+0691:FF;
+0692:FF;
+0693:FF;
+0694:FF;
+0695:FF;
+0696:00;
+0697:00;
+0698:00;
+0699:00;
+069A:00;
+069B:00;
+069C:FF;
+069D:FF;
+069E:FF;
+069F:FF;
+06A0:FF;
+06A1:FF;
+06A2:F0;
+06A3:F0;
+06A4:F0;
+06A5:F0;
+06A6:F0;
+06A7:F0;
+06A8:FF;
+06A9:FF;
+06AA:FF;
+06AB:FF;
+06AC:FF;
+06AD:FF;
+06AE:0F;
+06AF:0F;
+06B0:0F;
+06B1:0F;
+06B2:0F;
+06B3:0F;
+06B4:FF;
+06B5:FF;
+06B6:FF;
+06B7:FF;
+06B8:FF;
+06B9:FF;
+06BA:FF;
+06BB:FF;
+06BC:FF;
+06BD:FF;
+06BE:FF;
+06BF:FF;
+06C0:00;
+06C1:00;
+06C2:00;
+06C3:00;
+06C4:00;
+06C5:00;
+06C6:00;
+06C7:00;
+06C8:00;
+06C9:00;
+06CA:00;
+06CB:00;
+06CC:00;
+06CD:00;
+06CE:00;
+06CF:00;
+06D0:00;
+06D1:00;
+06D2:F0;
+06D3:F0;
+06D4:F0;
+06D5:F0;
+06D6:F0;
+06D7:F0;
+06D8:00;
+06D9:00;
+06DA:00;
+06DB:00;
+06DC:00;
+06DD:00;
+06DE:0F;
+06DF:0F;
+06E0:0F;
+06E1:0F;
+06E2:0F;
+06E3:0F;
+06E4:00;
+06E5:00;
+06E6:00;
+06E7:00;
+06E8:00;
+06E9:00;
+06EA:FF;
+06EB:FF;
+06EC:FF;
+06ED:FF;
+06EE:FF;
+06EF:FF;
+06F0:F0;
+06F1:F0;
+06F2:F0;
+06F3:F0;
+06F4:F0;
+06F5:F0;
+06F6:00;
+06F7:00;
+06F8:00;
+06F9:00;
+06FA:00;
+06FB:00;
+06FC:F0;
+06FD:F0;
+06FE:F0;
+06FF:F0;
+0700:F0;
+0701:F0;
+0702:F0;
+0703:F0;
+0704:F0;
+0705:F0;
+0706:F0;
+0707:F0;
+0708:F0;
+0709:F0;
+070A:F0;
+070B:F0;
+070C:F0;
+070D:F0;
+070E:0F;
+070F:0F;
+0710:0F;
+0711:0F;
+0712:0F;
+0713:0F;
+0714:F0;
+0715:F0;
+0716:F0;
+0717:F0;
+0718:F0;
+0719:F0;
+071A:FF;
+071B:FF;
+071C:FF;
+071D:FF;
+071E:FF;
+071F:FF;
+0720:0F;
+0721:0F;
+0722:0F;
+0723:0F;
+0724:0F;
+0725:0F;
+0726:00;
+0727:00;
+0728:00;
+0729:00;
+072A:00;
+072B:00;
+072C:0F;
+072D:0F;
+072E:0F;
+072F:0F;
+0730:0F;
+0731:0F;
+0732:F0;
+0733:F0;
+0734:F0;
+0735:F0;
+0736:F0;
+0737:F0;
+0738:0F;
+0739:0F;
+073A:0F;
+073B:0F;
+073C:0F;
+073D:0F;
+073E:0F;
+073F:0F;
+0740:0F;
+0741:0F;
+0742:0F;
+0743:0F;
+0744:0F;
+0745:0F;
+0746:0F;
+0747:0F;
+0748:0F;
+0749:0F;
+074A:FF;
+074B:FF;
+074C:FF;
+074D:FF;
+074E:FF;
+074F:FF;
+0750:FF;
+0751:FF;
+0752:FF;
+0753:FF;
+0754:FF;
+0755:FF;
+0756:00;
+0757:00;
+0758:00;
+0759:00;
+075A:00;
+075B:00;
+075C:FF;
+075D:FF;
+075E:FF;
+075F:FF;
+0760:FF;
+0761:FF;
+0762:F0;
+0763:F0;
+0764:F0;
+0765:F0;
+0766:F0;
+0767:F0;
+0768:FF;
+0769:FF;
+076A:FF;
+076B:FF;
+076C:FF;
+076D:FF;
+076E:0F;
+076F:0F;
+0770:0F;
+0771:0F;
+0772:0F;
+0773:0F;
+0774:FF;
+0775:FF;
+0776:FF;
+0777:FF;
+0778:FF;
+0779:FF;
+077A:FF;
+077B:FF;
+077C:FF;
+077D:FF;
+077E:FF;
+077F:FF;
+0780:00;
+0781:00;
+0782:00;
+0783:00;
+0784:00;
+0785:00;
+0786:00;
+0787:00;
+0788:00;
+0789:00;
+078A:00;
+078B:00;
+078C:00;
+078D:00;
+078E:00;
+078F:00;
+0790:00;
+0791:00;
+0792:F0;
+0793:F0;
+0794:F0;
+0795:F0;
+0796:F0;
+0797:F0;
+0798:00;
+0799:00;
+079A:00;
+079B:00;
+079C:00;
+079D:00;
+079E:0F;
+079F:0F;
+07A0:0F;
+07A1:0F;
+07A2:0F;
+07A3:0F;
+07A4:00;
+07A5:00;
+07A6:00;
+07A7:00;
+07A8:00;
+07A9:00;
+07AA:FF;
+07AB:FF;
+07AC:FF;
+07AD:FF;
+07AE:FF;
+07AF:FF;
+07B0:F0;
+07B1:F0;
+07B2:F0;
+07B3:F0;
+07B4:F0;
+07B5:F0;
+07B6:00;
+07B7:00;
+07B8:00;
+07B9:00;
+07BA:00;
+07BB:00;
+07BC:F0;
+07BD:F0;
+07BE:F0;
+07BF:F0;
+07C0:F0;
+07C1:F0;
+07C2:F0;
+07C3:F0;
+07C4:F0;
+07C5:F0;
+07C6:F0;
+07C7:F0;
+07C8:F0;
+07C9:F0;
+07CA:F0;
+07CB:F0;
+07CC:F0;
+07CD:F0;
+07CE:0F;
+07CF:0F;
+07D0:0F;
+07D1:0F;
+07D2:0F;
+07D3:0F;
+07D4:F0;
+07D5:F0;
+07D6:F0;
+07D7:F0;
+07D8:F0;
+07D9:F0;
+07DA:FF;
+07DB:FF;
+07DC:FF;
+07DD:FF;
+07DE:FF;
+07DF:FF;
+07E0:0F;
+07E1:0F;
+07E2:0F;
+07E3:0F;
+07E4:0F;
+07E5:0F;
+07E6:00;
+07E7:00;
+07E8:00;
+07E9:00;
+07EA:00;
+07EB:00;
+07EC:0F;
+07ED:0F;
+07EE:0F;
+07EF:0F;
+07F0:0F;
+07F1:0F;
+07F2:F0;
+07F3:F0;
+07F4:F0;
+07F5:F0;
+07F6:F0;
+07F7:F0;
+07F8:0F;
+07F9:0F;
+07FA:0F;
+07FB:0F;
+07FC:0F;
+07FD:0F;
+07FE:0F;
+07FF:0F;
+0800:0F;
+0801:0F;
+0802:0F;
+0803:0F;
+0804:0F;
+0805:0F;
+0806:0F;
+0807:0F;
+0808:0F;
+0809:0F;
+080A:FF;
+080B:FF;
+080C:FF;
+080D:FF;
+080E:FF;
+080F:FF;
+0810:FF;
+0811:FF;
+0812:FF;
+0813:FF;
+0814:FF;
+0815:FF;
+0816:00;
+0817:00;
+0818:00;
+0819:00;
+081A:00;
+081B:00;
+081C:FF;
+081D:FF;
+081E:FF;
+081F:FF;
+0820:FF;
+0821:FF;
+0822:F0;
+0823:F0;
+0824:F0;
+0825:F0;
+0826:F0;
+0827:F0;
+0828:FF;
+0829:FF;
+082A:FF;
+082B:FF;
+082C:FF;
+082D:FF;
+082E:0F;
+082F:0F;
+0830:0F;
+0831:0F;
+0832:0F;
+0833:0F;
+0834:FF;
+0835:FF;
+0836:FF;
+0837:FF;
+0838:FF;
+0839:FF;
+083A:FF;
+083B:FF;
+083C:FF;
+083D:FF;
+083E:FF;
+083F:FF;
+0840:00;
+0841:00;
+0842:00;
+0843:00;
+0844:00;
+0845:00;
+0846:00;
+0847:00;
+0848:00;
+0849:00;
+084A:00;
+084B:00;
+084C:00;
+084D:00;
+084E:00;
+084F:00;
+0850:00;
+0851:00;
+0852:F0;
+0853:F0;
+0854:F0;
+0855:F0;
+0856:F0;
+0857:F0;
+0858:00;
+0859:00;
+085A:00;
+085B:00;
+085C:00;
+085D:00;
+085E:0F;
+085F:0F;
+0860:0F;
+0861:0F;
+0862:0F;
+0863:0F;
+0864:00;
+0865:00;
+0866:00;
+0867:00;
+0868:00;
+0869:00;
+086A:FF;
+086B:FF;
+086C:FF;
+086D:FF;
+086E:FF;
+086F:FF;
+0870:F0;
+0871:F0;
+0872:F0;
+0873:F0;
+0874:F0;
+0875:F0;
+0876:00;
+0877:00;
+0878:00;
+0879:00;
+087A:00;
+087B:00;
+087C:F0;
+087D:F0;
+087E:F0;
+087F:F0;
+0880:F0;
+0881:F0;
+0882:F0;
+0883:F0;
+0884:F0;
+0885:F0;
+0886:F0;
+0887:F0;
+0888:F0;
+0889:F0;
+088A:F0;
+088B:F0;
+088C:F0;
+088D:F0;
+088E:0F;
+088F:0F;
+0890:0F;
+0891:0F;
+0892:0F;
+0893:0F;
+0894:F0;
+0895:F0;
+0896:F0;
+0897:F0;
+0898:F0;
+0899:F0;
+089A:FF;
+089B:FF;
+089C:FF;
+089D:FF;
+089E:FF;
+089F:FF;
+08A0:0F;
+08A1:0F;
+08A2:0F;
+08A3:0F;
+08A4:0F;
+08A5:0F;
+08A6:00;
+08A7:00;
+08A8:00;
+08A9:00;
+08AA:00;
+08AB:00;
+08AC:0F;
+08AD:0F;
+08AE:0F;
+08AF:0F;
+08B0:0F;
+08B1:0F;
+08B2:F0;
+08B3:F0;
+08B4:F0;
+08B5:F0;
+08B6:F0;
+08B7:F0;
+08B8:0F;
+08B9:0F;
+08BA:0F;
+08BB:0F;
+08BC:0F;
+08BD:0F;
+08BE:0F;
+08BF:0F;
+08C0:0F;
+08C1:0F;
+08C2:0F;
+08C3:0F;
+08C4:0F;
+08C5:0F;
+08C6:0F;
+08C7:0F;
+08C8:0F;
+08C9:0F;
+08CA:FF;
+08CB:FF;
+08CC:FF;
+08CD:FF;
+08CE:FF;
+08CF:FF;
+08D0:FF;
+08D1:FF;
+08D2:FF;
+08D3:FF;
+08D4:FF;
+08D5:FF;
+08D6:00;
+08D7:00;
+08D8:00;
+08D9:00;
+08DA:00;
+08DB:00;
+08DC:FF;
+08DD:FF;
+08DE:FF;
+08DF:FF;
+08E0:FF;
+08E1:FF;
+08E2:F0;
+08E3:F0;
+08E4:F0;
+08E5:F0;
+08E6:F0;
+08E7:F0;
+08E8:FF;
+08E9:FF;
+08EA:FF;
+08EB:FF;
+08EC:FF;
+08ED:FF;
+08EE:0F;
+08EF:0F;
+08F0:0F;
+08F1:0F;
+08F2:0F;
+08F3:0F;
+08F4:FF;
+08F5:FF;
+08F6:FF;
+08F7:FF;
+08F8:FF;
+08F9:FF;
+08FA:FF;
+08FB:FF;
+08FC:FF;
+08FD:FF;
+08FE:FF;
+08FF:FF;
+0900:00;
+0901:00;
+0902:00;
+0903:00;
+0904:00;
+0905:00;
+0906:00;
+0907:00;
+0908:00;
+0909:00;
+090A:00;
+090B:00;
+090C:00;
+090D:00;
+090E:00;
+090F:00;
+0910:00;
+0911:00;
+0912:F0;
+0913:F0;
+0914:F0;
+0915:F0;
+0916:F0;
+0917:F0;
+0918:00;
+0919:00;
+091A:00;
+091B:00;
+091C:00;
+091D:00;
+091E:0F;
+091F:0F;
+0920:0F;
+0921:0F;
+0922:0F;
+0923:0F;
+0924:00;
+0925:00;
+0926:00;
+0927:00;
+0928:00;
+0929:00;
+092A:FF;
+092B:FF;
+092C:FF;
+092D:FF;
+092E:FF;
+092F:FF;
+0930:F0;
+0931:F0;
+0932:F0;
+0933:F0;
+0934:F0;
+0935:F0;
+0936:00;
+0937:00;
+0938:00;
+0939:00;
+093A:00;
+093B:00;
+093C:F0;
+093D:F0;
+093E:F0;
+093F:F0;
+0940:F0;
+0941:F0;
+0942:F0;
+0943:F0;
+0944:F0;
+0945:F0;
+0946:F0;
+0947:F0;
+0948:F0;
+0949:F0;
+094A:F0;
+094B:F0;
+094C:F0;
+094D:F0;
+094E:0F;
+094F:0F;
+0950:0F;
+0951:0F;
+0952:0F;
+0953:0F;
+0954:F0;
+0955:F0;
+0956:F0;
+0957:F0;
+0958:F0;
+0959:F0;
+095A:FF;
+095B:FF;
+095C:FF;
+095D:FF;
+095E:FF;
+095F:FF;
+0960:0F;
+0961:0F;
+0962:0F;
+0963:0F;
+0964:0F;
+0965:0F;
+0966:00;
+0967:00;
+0968:00;
+0969:00;
+096A:00;
+096B:00;
+096C:0F;
+096D:0F;
+096E:0F;
+096F:0F;
+0970:0F;
+0971:0F;
+0972:F0;
+0973:F0;
+0974:F0;
+0975:F0;
+0976:F0;
+0977:F0;
+0978:0F;
+0979:0F;
+097A:0F;
+097B:0F;
+097C:0F;
+097D:0F;
+097E:0F;
+097F:0F;
+0980:0F;
+0981:0F;
+0982:0F;
+0983:0F;
+0984:0F;
+0985:0F;
+0986:0F;
+0987:0F;
+0988:0F;
+0989:0F;
+098A:FF;
+098B:FF;
+098C:FF;
+098D:FF;
+098E:FF;
+098F:FF;
+0990:FF;
+0991:FF;
+0992:FF;
+0993:FF;
+0994:FF;
+0995:FF;
+0996:00;
+0997:00;
+0998:00;
+0999:00;
+099A:00;
+099B:00;
+099C:FF;
+099D:FF;
+099E:FF;
+099F:FF;
+09A0:FF;
+09A1:FF;
+09A2:F0;
+09A3:F0;
+09A4:F0;
+09A5:F0;
+09A6:F0;
+09A7:F0;
+09A8:FF;
+09A9:FF;
+09AA:FF;
+09AB:FF;
+09AC:FF;
+09AD:FF;
+09AE:0F;
+09AF:0F;
+09B0:0F;
+09B1:0F;
+09B2:0F;
+09B3:0F;
+09B4:FF;
+09B5:FF;
+09B6:FF;
+09B7:FF;
+09B8:FF;
+09B9:FF;
+09BA:FF;
+09BB:FF;
+09BC:FF;
+09BD:FF;
+09BE:FF;
+09BF:FF;
+09C0:00;
+09C1:00;
+09C2:00;
+09C3:00;
+09C4:00;
+09C5:00;
+09C6:00;
+09C7:00;
+09C8:00;
+09C9:00;
+09CA:00;
+09CB:00;
+09CC:00;
+09CD:00;
+09CE:00;
+09CF:00;
+09D0:00;
+09D1:00;
+09D2:F0;
+09D3:F0;
+09D4:F0;
+09D5:F0;
+09D6:F0;
+09D7:F0;
+09D8:00;
+09D9:00;
+09DA:00;
+09DB:00;
+09DC:00;
+09DD:00;
+09DE:0F;
+09DF:0F;
+09E0:0F;
+09E1:0F;
+09E2:0F;
+09E3:0F;
+09E4:00;
+09E5:00;
+09E6:00;
+09E7:00;
+09E8:00;
+09E9:00;
+09EA:FF;
+09EB:FF;
+09EC:FF;
+09ED:FF;
+09EE:FF;
+09EF:FF;
+09F0:F0;
+09F1:F0;
+09F2:F0;
+09F3:F0;
+09F4:F0;
+09F5:F0;
+09F6:00;
+09F7:00;
+09F8:00;
+09F9:00;
+09FA:00;
+09FB:00;
+09FC:F0;
+09FD:F0;
+09FE:F0;
+09FF:F0;
+0A00:F0;
+0A01:F0;
+0A02:F0;
+0A03:F0;
+0A04:F0;
+0A05:F0;
+0A06:F0;
+0A07:F0;
+0A08:F0;
+0A09:F0;
+0A0A:F0;
+0A0B:F0;
+0A0C:F0;
+0A0D:F0;
+0A0E:0F;
+0A0F:0F;
+0A10:0F;
+0A11:0F;
+0A12:0F;
+0A13:0F;
+0A14:F0;
+0A15:F0;
+0A16:F0;
+0A17:F0;
+0A18:F0;
+0A19:F0;
+0A1A:FF;
+0A1B:FF;
+0A1C:FF;
+0A1D:FF;
+0A1E:FF;
+0A1F:FF;
+0A20:0F;
+0A21:0F;
+0A22:0F;
+0A23:0F;
+0A24:0F;
+0A25:0F;
+0A26:00;
+0A27:00;
+0A28:00;
+0A29:00;
+0A2A:00;
+0A2B:00;
+0A2C:0F;
+0A2D:0F;
+0A2E:0F;
+0A2F:0F;
+0A30:0F;
+0A31:0F;
+0A32:F0;
+0A33:F0;
+0A34:F0;
+0A35:F0;
+0A36:F0;
+0A37:F0;
+0A38:0F;
+0A39:0F;
+0A3A:0F;
+0A3B:0F;
+0A3C:0F;
+0A3D:0F;
+0A3E:0F;
+0A3F:0F;
+0A40:0F;
+0A41:0F;
+0A42:0F;
+0A43:0F;
+0A44:0F;
+0A45:0F;
+0A46:0F;
+0A47:0F;
+0A48:0F;
+0A49:0F;
+0A4A:FF;
+0A4B:FF;
+0A4C:FF;
+0A4D:FF;
+0A4E:FF;
+0A4F:FF;
+0A50:FF;
+0A51:FF;
+0A52:FF;
+0A53:FF;
+0A54:FF;
+0A55:FF;
+0A56:00;
+0A57:00;
+0A58:00;
+0A59:00;
+0A5A:00;
+0A5B:00;
+0A5C:FF;
+0A5D:FF;
+0A5E:FF;
+0A5F:FF;
+0A60:FF;
+0A61:FF;
+0A62:F0;
+0A63:F0;
+0A64:F0;
+0A65:F0;
+0A66:F0;
+0A67:F0;
+0A68:FF;
+0A69:FF;
+0A6A:FF;
+0A6B:FF;
+0A6C:FF;
+0A6D:FF;
+0A6E:0F;
+0A6F:0F;
+0A70:0F;
+0A71:0F;
+0A72:0F;
+0A73:0F;
+0A74:FF;
+0A75:FF;
+0A76:FF;
+0A77:FF;
+0A78:FF;
+0A79:FF;
+0A7A:FF;
+0A7B:FF;
+0A7C:FF;
+0A7D:FF;
+0A7E:FF;
+0A7F:FF;
+0A80:00;
+0A81:00;
+0A82:00;
+0A83:00;
+0A84:00;
+0A85:00;
+0A86:00;
+0A87:00;
+0A88:00;
+0A89:00;
+0A8A:00;
+0A8B:00;
+0A8C:00;
+0A8D:00;
+0A8E:00;
+0A8F:00;
+0A90:00;
+0A91:00;
+0A92:F0;
+0A93:F0;
+0A94:F0;
+0A95:F0;
+0A96:F0;
+0A97:F0;
+0A98:00;
+0A99:00;
+0A9A:00;
+0A9B:00;
+0A9C:00;
+0A9D:00;
+0A9E:0F;
+0A9F:0F;
+0AA0:0F;
+0AA1:0F;
+0AA2:0F;
+0AA3:0F;
+0AA4:00;
+0AA5:00;
+0AA6:00;
+0AA7:00;
+0AA8:00;
+0AA9:00;
+0AAA:FF;
+0AAB:FF;
+0AAC:FF;
+0AAD:FF;
+0AAE:FF;
+0AAF:FF;
+0AB0:F0;
+0AB1:F0;
+0AB2:F0;
+0AB3:F0;
+0AB4:F0;
+0AB5:F0;
+0AB6:00;
+0AB7:00;
+0AB8:00;
+0AB9:00;
+0ABA:00;
+0ABB:00;
+0ABC:F0;
+0ABD:F0;
+0ABE:F0;
+0ABF:F0;
+0AC0:F0;
+0AC1:F0;
+0AC2:F0;
+0AC3:F0;
+0AC4:F0;
+0AC5:F0;
+0AC6:F0;
+0AC7:F0;
+0AC8:F0;
+0AC9:F0;
+0ACA:F0;
+0ACB:F0;
+0ACC:F0;
+0ACD:F0;
+0ACE:0F;
+0ACF:0F;
+0AD0:0F;
+0AD1:0F;
+0AD2:0F;
+0AD3:0F;
+0AD4:F0;
+0AD5:F0;
+0AD6:F0;
+0AD7:F0;
+0AD8:F0;
+0AD9:F0;
+0ADA:FF;
+0ADB:FF;
+0ADC:FF;
+0ADD:FF;
+0ADE:FF;
+0ADF:FF;
+0AE0:0F;
+0AE1:0F;
+0AE2:0F;
+0AE3:0F;
+0AE4:0F;
+0AE5:0F;
+0AE6:00;
+0AE7:00;
+0AE8:00;
+0AE9:00;
+0AEA:00;
+0AEB:00;
+0AEC:0F;
+0AED:0F;
+0AEE:0F;
+0AEF:0F;
+0AF0:0F;
+0AF1:0F;
+0AF2:F0;
+0AF3:F0;
+0AF4:F0;
+0AF5:F0;
+0AF6:F0;
+0AF7:F0;
+0AF8:0F;
+0AF9:0F;
+0AFA:0F;
+0AFB:0F;
+0AFC:0F;
+0AFD:0F;
+0AFE:0F;
+0AFF:0F;
+0B00:0F;
+0B01:0F;
+0B02:0F;
+0B03:0F;
+0B04:0F;
+0B05:0F;
+0B06:0F;
+0B07:0F;
+0B08:0F;
+0B09:0F;
+0B0A:FF;
+0B0B:FF;
+0B0C:FF;
+0B0D:FF;
+0B0E:FF;
+0B0F:FF;
+0B10:FF;
+0B11:FF;
+0B12:FF;
+0B13:FF;
+0B14:FF;
+0B15:FF;
+0B16:00;
+0B17:00;
+0B18:00;
+0B19:00;
+0B1A:00;
+0B1B:00;
+0B1C:FF;
+0B1D:FF;
+0B1E:FF;
+0B1F:FF;
+0B20:FF;
+0B21:FF;
+0B22:F0;
+0B23:F0;
+0B24:F0;
+0B25:F0;
+0B26:F0;
+0B27:F0;
+0B28:FF;
+0B29:FF;
+0B2A:FF;
+0B2B:FF;
+0B2C:FF;
+0B2D:FF;
+0B2E:0F;
+0B2F:0F;
+0B30:0F;
+0B31:0F;
+0B32:0F;
+0B33:0F;
+0B34:FF;
+0B35:FF;
+0B36:FF;
+0B37:FF;
+0B38:FF;
+0B39:FF;
+0B3A:FF;
+0B3B:FF;
+0B3C:FF;
+0B3D:FF;
+0B3E:FF;
+0B3F:FF;
+0B40:00;
+0B41:00;
+0B42:00;
+0B43:00;
+0B44:00;
+0B45:00;
+0B46:00;
+0B47:00;
+0B48:00;
+0B49:00;
+0B4A:00;
+0B4B:00;
+0B4C:00;
+0B4D:00;
+0B4E:00;
+0B4F:00;
+0B50:00;
+0B51:00;
+0B52:F0;
+0B53:F0;
+0B54:F0;
+0B55:F0;
+0B56:F0;
+0B57:F0;
+0B58:00;
+0B59:00;
+0B5A:00;
+0B5B:00;
+0B5C:00;
+0B5D:00;
+0B5E:0F;
+0B5F:0F;
+0B60:0F;
+0B61:0F;
+0B62:0F;
+0B63:0F;
+0B64:00;
+0B65:00;
+0B66:00;
+0B67:00;
+0B68:00;
+0B69:00;
+0B6A:FF;
+0B6B:FF;
+0B6C:FF;
+0B6D:FF;
+0B6E:FF;
+0B6F:FF;
+0B70:F0;
+0B71:F0;
+0B72:F0;
+0B73:F0;
+0B74:F0;
+0B75:F0;
+0B76:00;
+0B77:00;
+0B78:00;
+0B79:00;
+0B7A:00;
+0B7B:00;
+0B7C:F0;
+0B7D:F0;
+0B7E:F0;
+0B7F:F0;
+0B80:F0;
+0B81:F0;
+0B82:F0;
+0B83:F0;
+0B84:F0;
+0B85:F0;
+0B86:F0;
+0B87:F0;
+0B88:F0;
+0B89:F0;
+0B8A:F0;
+0B8B:F0;
+0B8C:F0;
+0B8D:F0;
+0B8E:0F;
+0B8F:0F;
+0B90:0F;
+0B91:0F;
+0B92:0F;
+0B93:0F;
+0B94:F0;
+0B95:F0;
+0B96:F0;
+0B97:F0;
+0B98:F0;
+0B99:F0;
+0B9A:FF;
+0B9B:FF;
+0B9C:FF;
+0B9D:FF;
+0B9E:FF;
+0B9F:FF;
+0BA0:0F;
+0BA1:0F;
+0BA2:0F;
+0BA3:0F;
+0BA4:0F;
+0BA5:0F;
+0BA6:00;
+0BA7:00;
+0BA8:00;
+0BA9:00;
+0BAA:00;
+0BAB:00;
+0BAC:0F;
+0BAD:0F;
+0BAE:0F;
+0BAF:0F;
+0BB0:0F;
+0BB1:0F;
+0BB2:F0;
+0BB3:F0;
+0BB4:F0;
+0BB5:F0;
+0BB6:F0;
+0BB7:F0;
+0BB8:0F;
+0BB9:0F;
+0BBA:0F;
+0BBB:0F;
+0BBC:0F;
+0BBD:0F;
+0BBE:0F;
+0BBF:0F;
+0BC0:0F;
+0BC1:0F;
+0BC2:0F;
+0BC3:0F;
+0BC4:0F;
+0BC5:0F;
+0BC6:0F;
+0BC7:0F;
+0BC8:0F;
+0BC9:0F;
+0BCA:FF;
+0BCB:FF;
+0BCC:FF;
+0BCD:FF;
+0BCE:FF;
+0BCF:FF;
+0BD0:FF;
+0BD1:FF;
+0BD2:FF;
+0BD3:FF;
+0BD4:FF;
+0BD5:FF;
+0BD6:00;
+0BD7:00;
+0BD8:00;
+0BD9:00;
+0BDA:00;
+0BDB:00;
+0BDC:FF;
+0BDD:FF;
+0BDE:FF;
+0BDF:FF;
+0BE0:FF;
+0BE1:FF;
+0BE2:F0;
+0BE3:F0;
+0BE4:F0;
+0BE5:F0;
+0BE6:F0;
+0BE7:F0;
+0BE8:FF;
+0BE9:FF;
+0BEA:FF;
+0BEB:FF;
+0BEC:FF;
+0BED:FF;
+0BEE:0F;
+0BEF:0F;
+0BF0:0F;
+0BF1:0F;
+0BF2:0F;
+0BF3:0F;
+0BF4:FF;
+0BF5:FF;
+0BF6:FF;
+0BF7:FF;
+0BF8:FF;
+0BF9:FF;
+0BFA:FF;
+0BFB:FF;
+0BFC:FF;
+0BFD:FF;
+0BFE:FF;
+0BFF:FF;
+END;
diff --git a/Computer_MiST/Laser310_MiST/rtl/roms/charrom_4k.mif b/Computer_MiST/Laser310_MiST/rtl/roms/charrom_4k.mif
new file mode 100644
index 00000000..35435b03
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/roms/charrom_4k.mif
@@ -0,0 +1,4103 @@
+DEPTH = 4096;
+WIDTH = 8;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+0000:00;
+0001:1C;
+0002:22;
+0003:20;
+0004:2C;
+0005:32;
+0006:32;
+0007:1C;
+0008:00;
+0009:00;
+000A:00;
+000B:00;
+000C:00;
+000D:00;
+000E:00;
+000F:00;
+0010:00;
+0011:08;
+0012:14;
+0013:22;
+0014:22;
+0015:3E;
+0016:22;
+0017:22;
+0018:00;
+0019:00;
+001A:00;
+001B:00;
+001C:00;
+001D:00;
+001E:00;
+001F:00;
+0020:00;
+0021:1E;
+0022:24;
+0023:24;
+0024:1C;
+0025:24;
+0026:24;
+0027:1E;
+0028:00;
+0029:00;
+002A:00;
+002B:00;
+002C:00;
+002D:00;
+002E:00;
+002F:00;
+0030:00;
+0031:1C;
+0032:22;
+0033:02;
+0034:02;
+0035:02;
+0036:22;
+0037:1C;
+0038:00;
+0039:00;
+003A:00;
+003B:00;
+003C:00;
+003D:00;
+003E:00;
+003F:00;
+0040:00;
+0041:1E;
+0042:24;
+0043:24;
+0044:24;
+0045:24;
+0046:24;
+0047:1E;
+0048:00;
+0049:00;
+004A:00;
+004B:00;
+004C:00;
+004D:00;
+004E:00;
+004F:00;
+0050:00;
+0051:3E;
+0052:02;
+0053:02;
+0054:0E;
+0055:02;
+0056:02;
+0057:3E;
+0058:00;
+0059:00;
+005A:00;
+005B:00;
+005C:00;
+005D:00;
+005E:00;
+005F:00;
+0060:00;
+0061:3E;
+0062:02;
+0063:02;
+0064:1E;
+0065:02;
+0066:02;
+0067:02;
+0068:00;
+0069:00;
+006A:00;
+006B:00;
+006C:00;
+006D:00;
+006E:00;
+006F:00;
+0070:00;
+0071:3C;
+0072:02;
+0073:02;
+0074:32;
+0075:22;
+0076:22;
+0077:3C;
+0078:00;
+0079:00;
+007A:00;
+007B:00;
+007C:00;
+007D:00;
+007E:00;
+007F:00;
+0080:00;
+0081:22;
+0082:22;
+0083:22;
+0084:3E;
+0085:22;
+0086:22;
+0087:22;
+0088:00;
+0089:00;
+008A:00;
+008B:00;
+008C:00;
+008D:00;
+008E:00;
+008F:00;
+0090:00;
+0091:1C;
+0092:08;
+0093:08;
+0094:08;
+0095:08;
+0096:08;
+0097:1C;
+0098:00;
+0099:00;
+009A:00;
+009B:00;
+009C:00;
+009D:00;
+009E:00;
+009F:00;
+00A0:00;
+00A1:20;
+00A2:20;
+00A3:20;
+00A4:20;
+00A5:22;
+00A6:22;
+00A7:1C;
+00A8:00;
+00A9:00;
+00AA:00;
+00AB:00;
+00AC:00;
+00AD:00;
+00AE:00;
+00AF:00;
+00B0:00;
+00B1:22;
+00B2:12;
+00B3:0A;
+00B4:06;
+00B5:0A;
+00B6:12;
+00B7:22;
+00B8:00;
+00B9:00;
+00BA:00;
+00BB:00;
+00BC:00;
+00BD:00;
+00BE:00;
+00BF:00;
+00C0:00;
+00C1:02;
+00C2:02;
+00C3:02;
+00C4:02;
+00C5:02;
+00C6:02;
+00C7:3E;
+00C8:00;
+00C9:00;
+00CA:00;
+00CB:00;
+00CC:00;
+00CD:00;
+00CE:00;
+00CF:00;
+00D0:00;
+00D1:22;
+00D2:36;
+00D3:3E;
+00D4:2A;
+00D5:22;
+00D6:22;
+00D7:22;
+00D8:00;
+00D9:00;
+00DA:00;
+00DB:00;
+00DC:00;
+00DD:00;
+00DE:00;
+00DF:00;
+00E0:00;
+00E1:22;
+00E2:22;
+00E3:26;
+00E4:2A;
+00E5:32;
+00E6:22;
+00E7:22;
+00E8:00;
+00E9:00;
+00EA:00;
+00EB:00;
+00EC:00;
+00ED:00;
+00EE:00;
+00EF:00;
+00F0:00;
+00F1:3E;
+00F2:22;
+00F3:22;
+00F4:22;
+00F5:22;
+00F6:22;
+00F7:3E;
+00F8:00;
+00F9:00;
+00FA:00;
+00FB:00;
+00FC:00;
+00FD:00;
+00FE:00;
+00FF:00;
+0100:00;
+0101:1E;
+0102:22;
+0103:22;
+0104:1E;
+0105:02;
+0106:02;
+0107:02;
+0108:00;
+0109:00;
+010A:00;
+010B:00;
+010C:00;
+010D:00;
+010E:00;
+010F:00;
+0110:00;
+0111:1C;
+0112:22;
+0113:22;
+0114:22;
+0115:2A;
+0116:12;
+0117:2C;
+0118:00;
+0119:00;
+011A:00;
+011B:00;
+011C:00;
+011D:00;
+011E:00;
+011F:00;
+0120:00;
+0121:1E;
+0122:22;
+0123:22;
+0124:1E;
+0125:0A;
+0126:12;
+0127:22;
+0128:00;
+0129:00;
+012A:00;
+012B:00;
+012C:00;
+012D:00;
+012E:00;
+012F:00;
+0130:00;
+0131:1C;
+0132:22;
+0133:04;
+0134:08;
+0135:10;
+0136:22;
+0137:1C;
+0138:00;
+0139:00;
+013A:00;
+013B:00;
+013C:00;
+013D:00;
+013E:00;
+013F:00;
+0140:00;
+0141:3E;
+0142:08;
+0143:08;
+0144:08;
+0145:08;
+0146:08;
+0147:08;
+0148:00;
+0149:00;
+014A:00;
+014B:00;
+014C:00;
+014D:00;
+014E:00;
+014F:00;
+0150:00;
+0151:22;
+0152:22;
+0153:22;
+0154:22;
+0155:22;
+0156:22;
+0157:1C;
+0158:00;
+0159:00;
+015A:00;
+015B:00;
+015C:00;
+015D:00;
+015E:00;
+015F:00;
+0160:00;
+0161:22;
+0162:22;
+0163:22;
+0164:14;
+0165:14;
+0166:08;
+0167:08;
+0168:00;
+0169:00;
+016A:00;
+016B:00;
+016C:00;
+016D:00;
+016E:00;
+016F:00;
+0170:00;
+0171:22;
+0172:22;
+0173:22;
+0174:2A;
+0175:3E;
+0176:36;
+0177:22;
+0178:00;
+0179:00;
+017A:00;
+017B:00;
+017C:00;
+017D:00;
+017E:00;
+017F:00;
+0180:00;
+0181:22;
+0182:22;
+0183:14;
+0184:08;
+0185:14;
+0186:22;
+0187:22;
+0188:00;
+0189:00;
+018A:00;
+018B:00;
+018C:00;
+018D:00;
+018E:00;
+018F:00;
+0190:00;
+0191:22;
+0192:22;
+0193:14;
+0194:08;
+0195:08;
+0196:08;
+0197:08;
+0198:00;
+0199:00;
+019A:00;
+019B:00;
+019C:00;
+019D:00;
+019E:00;
+019F:00;
+01A0:00;
+01A1:3E;
+01A2:20;
+01A3:10;
+01A4:08;
+01A5:04;
+01A6:02;
+01A7:3E;
+01A8:00;
+01A9:00;
+01AA:00;
+01AB:00;
+01AC:00;
+01AD:00;
+01AE:00;
+01AF:00;
+01B0:00;
+01B1:1C;
+01B2:04;
+01B3:04;
+01B4:04;
+01B5:04;
+01B6:04;
+01B7:1C;
+01B8:00;
+01B9:00;
+01BA:00;
+01BB:00;
+01BC:00;
+01BD:00;
+01BE:00;
+01BF:00;
+01C0:00;
+01C1:00;
+01C2:02;
+01C3:04;
+01C4:08;
+01C5:10;
+01C6:20;
+01C7:00;
+01C8:00;
+01C9:00;
+01CA:00;
+01CB:00;
+01CC:00;
+01CD:00;
+01CE:00;
+01CF:00;
+01D0:00;
+01D1:1C;
+01D2:10;
+01D3:10;
+01D4:10;
+01D5:10;
+01D6:10;
+01D7:1C;
+01D8:00;
+01D9:00;
+01DA:00;
+01DB:00;
+01DC:00;
+01DD:00;
+01DE:00;
+01DF:00;
+01E0:00;
+01E1:08;
+01E2:1C;
+01E3:2A;
+01E4:08;
+01E5:08;
+01E6:08;
+01E7:08;
+01E8:00;
+01E9:00;
+01EA:00;
+01EB:00;
+01EC:00;
+01ED:00;
+01EE:00;
+01EF:00;
+01F0:00;
+01F1:00;
+01F2:08;
+01F3:04;
+01F4:3E;
+01F5:04;
+01F6:08;
+01F7:00;
+01F8:00;
+01F9:00;
+01FA:00;
+01FB:00;
+01FC:00;
+01FD:00;
+01FE:00;
+01FF:00;
+0200:00;
+0201:00;
+0202:00;
+0203:00;
+0204:00;
+0205:00;
+0206:00;
+0207:00;
+0208:00;
+0209:00;
+020A:00;
+020B:00;
+020C:00;
+020D:00;
+020E:00;
+020F:00;
+0210:00;
+0211:08;
+0212:08;
+0213:08;
+0214:08;
+0215:08;
+0216:00;
+0217:08;
+0218:00;
+0219:00;
+021A:00;
+021B:00;
+021C:00;
+021D:00;
+021E:00;
+021F:00;
+0220:00;
+0221:14;
+0222:14;
+0223:00;
+0224:00;
+0225:00;
+0226:00;
+0227:00;
+0228:00;
+0229:00;
+022A:00;
+022B:00;
+022C:00;
+022D:00;
+022E:00;
+022F:00;
+0230:00;
+0231:14;
+0232:14;
+0233:3E;
+0234:14;
+0235:3E;
+0236:14;
+0237:14;
+0238:00;
+0239:00;
+023A:00;
+023B:00;
+023C:00;
+023D:00;
+023E:00;
+023F:00;
+0240:00;
+0241:08;
+0242:3C;
+0243:02;
+0244:1C;
+0245:20;
+0246:1E;
+0247:08;
+0248:00;
+0249:00;
+024A:00;
+024B:00;
+024C:00;
+024D:00;
+024E:00;
+024F:00;
+0250:00;
+0251:26;
+0252:26;
+0253:10;
+0254:08;
+0255:04;
+0256:32;
+0257:32;
+0258:00;
+0259:00;
+025A:00;
+025B:00;
+025C:00;
+025D:00;
+025E:00;
+025F:00;
+0260:00;
+0261:04;
+0262:0A;
+0263:0A;
+0264:04;
+0265:2A;
+0266:12;
+0267:2C;
+0268:00;
+0269:00;
+026A:00;
+026B:00;
+026C:00;
+026D:00;
+026E:00;
+026F:00;
+0270:00;
+0271:08;
+0272:08;
+0273:00;
+0274:00;
+0275:00;
+0276:00;
+0277:00;
+0278:00;
+0279:00;
+027A:00;
+027B:00;
+027C:00;
+027D:00;
+027E:00;
+027F:00;
+0280:00;
+0281:10;
+0282:08;
+0283:04;
+0284:04;
+0285:04;
+0286:08;
+0287:10;
+0288:00;
+0289:00;
+028A:00;
+028B:00;
+028C:00;
+028D:00;
+028E:00;
+028F:00;
+0290:00;
+0291:04;
+0292:08;
+0293:10;
+0294:10;
+0295:10;
+0296:08;
+0297:04;
+0298:00;
+0299:00;
+029A:00;
+029B:00;
+029C:00;
+029D:00;
+029E:00;
+029F:00;
+02A0:00;
+02A1:00;
+02A2:08;
+02A3:1C;
+02A4:3E;
+02A5:1C;
+02A6:08;
+02A7:00;
+02A8:00;
+02A9:00;
+02AA:00;
+02AB:00;
+02AC:00;
+02AD:00;
+02AE:00;
+02AF:00;
+02B0:00;
+02B1:00;
+02B2:08;
+02B3:08;
+02B4:3E;
+02B5:08;
+02B6:08;
+02B7:00;
+02B8:00;
+02B9:00;
+02BA:00;
+02BB:00;
+02BC:00;
+02BD:00;
+02BE:00;
+02BF:00;
+02C0:00;
+02C1:00;
+02C2:00;
+02C3:00;
+02C4:00;
+02C5:0C;
+02C6:0C;
+02C7:08;
+02C8:04;
+02C9:00;
+02CA:00;
+02CB:00;
+02CC:00;
+02CD:00;
+02CE:00;
+02CF:00;
+02D0:00;
+02D1:00;
+02D2:00;
+02D3:00;
+02D4:3E;
+02D5:00;
+02D6:00;
+02D7:00;
+02D8:00;
+02D9:00;
+02DA:00;
+02DB:00;
+02DC:00;
+02DD:00;
+02DE:00;
+02DF:00;
+02E0:00;
+02E1:00;
+02E2:00;
+02E3:00;
+02E4:00;
+02E5:00;
+02E6:0C;
+02E7:0C;
+02E8:00;
+02E9:00;
+02EA:00;
+02EB:00;
+02EC:00;
+02ED:00;
+02EE:00;
+02EF:00;
+02F0:00;
+02F1:00;
+02F2:20;
+02F3:10;
+02F4:08;
+02F5:04;
+02F6:02;
+02F7:00;
+02F8:00;
+02F9:00;
+02FA:00;
+02FB:00;
+02FC:00;
+02FD:00;
+02FE:00;
+02FF:00;
+0300:00;
+0301:0C;
+0302:12;
+0303:12;
+0304:12;
+0305:12;
+0306:12;
+0307:0C;
+0308:00;
+0309:00;
+030A:00;
+030B:00;
+030C:00;
+030D:00;
+030E:00;
+030F:00;
+0310:00;
+0311:08;
+0312:0C;
+0313:08;
+0314:08;
+0315:08;
+0316:08;
+0317:1C;
+0318:00;
+0319:00;
+031A:00;
+031B:00;
+031C:00;
+031D:00;
+031E:00;
+031F:00;
+0320:00;
+0321:1C;
+0322:22;
+0323:20;
+0324:1C;
+0325:02;
+0326:02;
+0327:3E;
+0328:00;
+0329:00;
+032A:00;
+032B:00;
+032C:00;
+032D:00;
+032E:00;
+032F:00;
+0330:00;
+0331:1C;
+0332:22;
+0333:20;
+0334:1C;
+0335:20;
+0336:22;
+0337:1C;
+0338:00;
+0339:00;
+033A:00;
+033B:00;
+033C:00;
+033D:00;
+033E:00;
+033F:00;
+0340:00;
+0341:10;
+0342:18;
+0343:14;
+0344:3E;
+0345:10;
+0346:10;
+0347:10;
+0348:00;
+0349:00;
+034A:00;
+034B:00;
+034C:00;
+034D:00;
+034E:00;
+034F:00;
+0350:00;
+0351:3E;
+0352:02;
+0353:1E;
+0354:20;
+0355:20;
+0356:22;
+0357:1C;
+0358:00;
+0359:00;
+035A:00;
+035B:00;
+035C:00;
+035D:00;
+035E:00;
+035F:00;
+0360:00;
+0361:1C;
+0362:02;
+0363:02;
+0364:1E;
+0365:22;
+0366:22;
+0367:1C;
+0368:00;
+0369:00;
+036A:00;
+036B:00;
+036C:00;
+036D:00;
+036E:00;
+036F:00;
+0370:00;
+0371:3E;
+0372:20;
+0373:10;
+0374:08;
+0375:04;
+0376:02;
+0377:02;
+0378:00;
+0379:00;
+037A:00;
+037B:00;
+037C:00;
+037D:00;
+037E:00;
+037F:00;
+0380:00;
+0381:1C;
+0382:22;
+0383:22;
+0384:1C;
+0385:22;
+0386:22;
+0387:1C;
+0388:00;
+0389:00;
+038A:00;
+038B:00;
+038C:00;
+038D:00;
+038E:00;
+038F:00;
+0390:00;
+0391:1C;
+0392:22;
+0393:22;
+0394:3C;
+0395:20;
+0396:20;
+0397:1C;
+0398:00;
+0399:00;
+039A:00;
+039B:00;
+039C:00;
+039D:00;
+039E:00;
+039F:00;
+03A0:00;
+03A1:00;
+03A2:0C;
+03A3:0C;
+03A4:00;
+03A5:0C;
+03A6:0C;
+03A7:00;
+03A8:00;
+03A9:00;
+03AA:00;
+03AB:00;
+03AC:00;
+03AD:00;
+03AE:00;
+03AF:00;
+03B0:00;
+03B1:00;
+03B2:0C;
+03B3:0C;
+03B4:00;
+03B5:0C;
+03B6:0C;
+03B7:08;
+03B8:04;
+03B9:00;
+03BA:00;
+03BB:00;
+03BC:00;
+03BD:00;
+03BE:00;
+03BF:00;
+03C0:00;
+03C1:20;
+03C2:10;
+03C3:08;
+03C4:04;
+03C5:08;
+03C6:10;
+03C7:20;
+03C8:00;
+03C9:00;
+03CA:00;
+03CB:00;
+03CC:00;
+03CD:00;
+03CE:00;
+03CF:00;
+03D0:00;
+03D1:00;
+03D2:00;
+03D3:3E;
+03D4:00;
+03D5:3E;
+03D6:00;
+03D7:00;
+03D8:00;
+03D9:00;
+03DA:00;
+03DB:00;
+03DC:00;
+03DD:00;
+03DE:00;
+03DF:00;
+03E0:00;
+03E1:04;
+03E2:08;
+03E3:10;
+03E4:20;
+03E5:10;
+03E6:08;
+03E7:04;
+03E8:00;
+03E9:00;
+03EA:00;
+03EB:00;
+03EC:00;
+03ED:00;
+03EE:00;
+03EF:00;
+03F0:00;
+03F1:1C;
+03F2:22;
+03F3:20;
+03F4:10;
+03F5:08;
+03F6:00;
+03F7:08;
+03F8:00;
+03F9:00;
+03FA:00;
+03FB:00;
+03FC:00;
+03FD:00;
+03FE:00;
+03FF:00;
+0400:FF;
+0401:E3;
+0402:DD;
+0403:DF;
+0404:D3;
+0405:CD;
+0406:CD;
+0407:E3;
+0408:FF;
+0409:FF;
+040A:FF;
+040B:FF;
+040C:00;
+040D:00;
+040E:00;
+040F:00;
+0410:FF;
+0411:F7;
+0412:EB;
+0413:DD;
+0414:DD;
+0415:C1;
+0416:DD;
+0417:DD;
+0418:FF;
+0419:FF;
+041A:FF;
+041B:FF;
+041C:00;
+041D:00;
+041E:00;
+041F:00;
+0420:FF;
+0421:E1;
+0422:DB;
+0423:DB;
+0424:E3;
+0425:DB;
+0426:DB;
+0427:E1;
+0428:FF;
+0429:FF;
+042A:FF;
+042B:FF;
+042C:00;
+042D:00;
+042E:00;
+042F:00;
+0430:FF;
+0431:E3;
+0432:DD;
+0433:FD;
+0434:FD;
+0435:FD;
+0436:DD;
+0437:E3;
+0438:FF;
+0439:FF;
+043A:FF;
+043B:FF;
+043C:00;
+043D:00;
+043E:00;
+043F:00;
+0440:FF;
+0441:E1;
+0442:DB;
+0443:DB;
+0444:DB;
+0445:DB;
+0446:DB;
+0447:E1;
+0448:FF;
+0449:FF;
+044A:FF;
+044B:FF;
+044C:00;
+044D:00;
+044E:00;
+044F:00;
+0450:FF;
+0451:C1;
+0452:FD;
+0453:FD;
+0454:F1;
+0455:FD;
+0456:FD;
+0457:C1;
+0458:FF;
+0459:FF;
+045A:FF;
+045B:FF;
+045C:00;
+045D:00;
+045E:00;
+045F:00;
+0460:FF;
+0461:C1;
+0462:FD;
+0463:FD;
+0464:E1;
+0465:FD;
+0466:FD;
+0467:FD;
+0468:FF;
+0469:FF;
+046A:FF;
+046B:FF;
+046C:00;
+046D:00;
+046E:00;
+046F:00;
+0470:FF;
+0471:C3;
+0472:FD;
+0473:FD;
+0474:CD;
+0475:DD;
+0476:DD;
+0477:C3;
+0478:FF;
+0479:FF;
+047A:FF;
+047B:FF;
+047C:00;
+047D:00;
+047E:00;
+047F:00;
+0480:FF;
+0481:DD;
+0482:DD;
+0483:DD;
+0484:C1;
+0485:DD;
+0486:DD;
+0487:DD;
+0488:FF;
+0489:FF;
+048A:FF;
+048B:FF;
+048C:00;
+048D:00;
+048E:00;
+048F:00;
+0490:FF;
+0491:E3;
+0492:F7;
+0493:F7;
+0494:F7;
+0495:F7;
+0496:F7;
+0497:E3;
+0498:FF;
+0499:FF;
+049A:FF;
+049B:FF;
+049C:00;
+049D:00;
+049E:00;
+049F:00;
+04A0:FF;
+04A1:DF;
+04A2:DF;
+04A3:DF;
+04A4:DF;
+04A5:DD;
+04A6:DD;
+04A7:E3;
+04A8:FF;
+04A9:FF;
+04AA:FF;
+04AB:FF;
+04AC:00;
+04AD:00;
+04AE:00;
+04AF:00;
+04B0:FF;
+04B1:DD;
+04B2:ED;
+04B3:F5;
+04B4:F9;
+04B5:F5;
+04B6:ED;
+04B7:DD;
+04B8:FF;
+04B9:FF;
+04BA:FF;
+04BB:FF;
+04BC:00;
+04BD:00;
+04BE:00;
+04BF:00;
+04C0:FF;
+04C1:FD;
+04C2:FD;
+04C3:FD;
+04C4:FD;
+04C5:FD;
+04C6:FD;
+04C7:C1;
+04C8:FF;
+04C9:FF;
+04CA:FF;
+04CB:FF;
+04CC:00;
+04CD:00;
+04CE:00;
+04CF:00;
+04D0:FF;
+04D1:DD;
+04D2:C9;
+04D3:C1;
+04D4:D5;
+04D5:DD;
+04D6:DD;
+04D7:DD;
+04D8:FF;
+04D9:FF;
+04DA:FF;
+04DB:FF;
+04DC:00;
+04DD:00;
+04DE:00;
+04DF:00;
+04E0:FF;
+04E1:DD;
+04E2:DD;
+04E3:D9;
+04E4:D5;
+04E5:CD;
+04E6:DD;
+04E7:DD;
+04E8:FF;
+04E9:FF;
+04EA:FF;
+04EB:FF;
+04EC:00;
+04ED:00;
+04EE:00;
+04EF:00;
+04F0:FF;
+04F1:C1;
+04F2:DD;
+04F3:DD;
+04F4:DD;
+04F5:DD;
+04F6:DD;
+04F7:C1;
+04F8:FF;
+04F9:FF;
+04FA:FF;
+04FB:FF;
+04FC:00;
+04FD:00;
+04FE:00;
+04FF:00;
+0500:FF;
+0501:E1;
+0502:DD;
+0503:DD;
+0504:E1;
+0505:FD;
+0506:FD;
+0507:FD;
+0508:FF;
+0509:FF;
+050A:FF;
+050B:FF;
+050C:00;
+050D:00;
+050E:00;
+050F:00;
+0510:FF;
+0511:E3;
+0512:DD;
+0513:DD;
+0514:DD;
+0515:D5;
+0516:ED;
+0517:D3;
+0518:FF;
+0519:FF;
+051A:FF;
+051B:FF;
+051C:00;
+051D:00;
+051E:00;
+051F:00;
+0520:FF;
+0521:E1;
+0522:DD;
+0523:DD;
+0524:E1;
+0525:F5;
+0526:ED;
+0527:DD;
+0528:FF;
+0529:FF;
+052A:FF;
+052B:FF;
+052C:00;
+052D:00;
+052E:00;
+052F:00;
+0530:FF;
+0531:E3;
+0532:DD;
+0533:FB;
+0534:F7;
+0535:EF;
+0536:DD;
+0537:E3;
+0538:FF;
+0539:FF;
+053A:FF;
+053B:FF;
+053C:00;
+053D:00;
+053E:00;
+053F:00;
+0540:FF;
+0541:C1;
+0542:F7;
+0543:F7;
+0544:F7;
+0545:F7;
+0546:F7;
+0547:F7;
+0548:FF;
+0549:FF;
+054A:FF;
+054B:FF;
+054C:00;
+054D:00;
+054E:00;
+054F:00;
+0550:FF;
+0551:DD;
+0552:DD;
+0553:DD;
+0554:DD;
+0555:DD;
+0556:DD;
+0557:E3;
+0558:FF;
+0559:FF;
+055A:FF;
+055B:FF;
+055C:00;
+055D:00;
+055E:00;
+055F:00;
+0560:FF;
+0561:DD;
+0562:DD;
+0563:DD;
+0564:EB;
+0565:EB;
+0566:F7;
+0567:F7;
+0568:FF;
+0569:FF;
+056A:FF;
+056B:FF;
+056C:00;
+056D:00;
+056E:00;
+056F:00;
+0570:FF;
+0571:DD;
+0572:DD;
+0573:DD;
+0574:D5;
+0575:C1;
+0576:C9;
+0577:DD;
+0578:FF;
+0579:FF;
+057A:FF;
+057B:FF;
+057C:00;
+057D:00;
+057E:00;
+057F:00;
+0580:FF;
+0581:DD;
+0582:DD;
+0583:EB;
+0584:F7;
+0585:EB;
+0586:DD;
+0587:DD;
+0588:FF;
+0589:FF;
+058A:FF;
+058B:FF;
+058C:00;
+058D:00;
+058E:00;
+058F:00;
+0590:FF;
+0591:DD;
+0592:DD;
+0593:EB;
+0594:F7;
+0595:F7;
+0596:F7;
+0597:F7;
+0598:FF;
+0599:FF;
+059A:FF;
+059B:FF;
+059C:00;
+059D:00;
+059E:00;
+059F:00;
+05A0:FF;
+05A1:C1;
+05A2:DF;
+05A3:EF;
+05A4:F7;
+05A5:FB;
+05A6:FD;
+05A7:C1;
+05A8:FF;
+05A9:FF;
+05AA:FF;
+05AB:FF;
+05AC:00;
+05AD:00;
+05AE:00;
+05AF:00;
+05B0:FF;
+05B1:E3;
+05B2:FB;
+05B3:FB;
+05B4:FB;
+05B5:FB;
+05B6:FB;
+05B7:E3;
+05B8:FF;
+05B9:FF;
+05BA:FF;
+05BB:FF;
+05BC:00;
+05BD:00;
+05BE:00;
+05BF:00;
+05C0:FF;
+05C1:FF;
+05C2:FD;
+05C3:FB;
+05C4:F7;
+05C5:EF;
+05C6:DF;
+05C7:FF;
+05C8:FF;
+05C9:FF;
+05CA:FF;
+05CB:FF;
+05CC:00;
+05CD:00;
+05CE:00;
+05CF:00;
+05D0:FF;
+05D1:E3;
+05D2:EF;
+05D3:EF;
+05D4:EF;
+05D5:EF;
+05D6:EF;
+05D7:E3;
+05D8:FF;
+05D9:FF;
+05DA:FF;
+05DB:FF;
+05DC:00;
+05DD:00;
+05DE:00;
+05DF:00;
+05E0:FF;
+05E1:F7;
+05E2:E3;
+05E3:D5;
+05E4:F7;
+05E5:F7;
+05E6:F7;
+05E7:F7;
+05E8:FF;
+05E9:FF;
+05EA:FF;
+05EB:FF;
+05EC:00;
+05ED:00;
+05EE:00;
+05EF:00;
+05F0:FF;
+05F1:FF;
+05F2:F7;
+05F3:FB;
+05F4:C1;
+05F5:FB;
+05F6:F7;
+05F7:FF;
+05F8:FF;
+05F9:FF;
+05FA:FF;
+05FB:FF;
+05FC:00;
+05FD:00;
+05FE:00;
+05FF:00;
+0600:FF;
+0601:FF;
+0602:FF;
+0603:FF;
+0604:FF;
+0605:FF;
+0606:FF;
+0607:FF;
+0608:FF;
+0609:FF;
+060A:FF;
+060B:FF;
+060C:00;
+060D:00;
+060E:00;
+060F:00;
+0610:FF;
+0611:F7;
+0612:F7;
+0613:F7;
+0614:F7;
+0615:F7;
+0616:FF;
+0617:F7;
+0618:FF;
+0619:FF;
+061A:FF;
+061B:FF;
+061C:00;
+061D:00;
+061E:00;
+061F:00;
+0620:FF;
+0621:EB;
+0622:EB;
+0623:FF;
+0624:FF;
+0625:FF;
+0626:FF;
+0627:FF;
+0628:FF;
+0629:FF;
+062A:FF;
+062B:FF;
+062C:00;
+062D:00;
+062E:00;
+062F:00;
+0630:FF;
+0631:EB;
+0632:EB;
+0633:C1;
+0634:EB;
+0635:C1;
+0636:EB;
+0637:EB;
+0638:FF;
+0639:FF;
+063A:FF;
+063B:FF;
+063C:00;
+063D:00;
+063E:00;
+063F:00;
+0640:FF;
+0641:F7;
+0642:C3;
+0643:FD;
+0644:E3;
+0645:DF;
+0646:E1;
+0647:F7;
+0648:FF;
+0649:FF;
+064A:FF;
+064B:FF;
+064C:00;
+064D:00;
+064E:00;
+064F:00;
+0650:FF;
+0651:D9;
+0652:D9;
+0653:EF;
+0654:F7;
+0655:FB;
+0656:CD;
+0657:CD;
+0658:FF;
+0659:FF;
+065A:FF;
+065B:FF;
+065C:00;
+065D:00;
+065E:00;
+065F:00;
+0660:FF;
+0661:FB;
+0662:F5;
+0663:F5;
+0664:FB;
+0665:D5;
+0666:ED;
+0667:D3;
+0668:FF;
+0669:FF;
+066A:FF;
+066B:FF;
+066C:00;
+066D:00;
+066E:00;
+066F:00;
+0670:FF;
+0671:F7;
+0672:F7;
+0673:FF;
+0674:FF;
+0675:FF;
+0676:FF;
+0677:FF;
+0678:FF;
+0679:FF;
+067A:FF;
+067B:FF;
+067C:00;
+067D:00;
+067E:00;
+067F:00;
+0680:FF;
+0681:EF;
+0682:F7;
+0683:FB;
+0684:FB;
+0685:FB;
+0686:F7;
+0687:EF;
+0688:FF;
+0689:FF;
+068A:FF;
+068B:FF;
+068C:00;
+068D:00;
+068E:00;
+068F:00;
+0690:FF;
+0691:FB;
+0692:F7;
+0693:EF;
+0694:EF;
+0695:EF;
+0696:F7;
+0697:FB;
+0698:FF;
+0699:FF;
+069A:FF;
+069B:FF;
+069C:00;
+069D:00;
+069E:00;
+069F:00;
+06A0:FF;
+06A1:FF;
+06A2:F7;
+06A3:E3;
+06A4:C1;
+06A5:E3;
+06A6:F7;
+06A7:FF;
+06A8:FF;
+06A9:FF;
+06AA:FF;
+06AB:FF;
+06AC:00;
+06AD:00;
+06AE:00;
+06AF:00;
+06B0:FF;
+06B1:FF;
+06B2:F7;
+06B3:F7;
+06B4:C1;
+06B5:F7;
+06B6:F7;
+06B7:FF;
+06B8:FF;
+06B9:FF;
+06BA:FF;
+06BB:FF;
+06BC:00;
+06BD:00;
+06BE:00;
+06BF:00;
+06C0:FF;
+06C1:FF;
+06C2:FF;
+06C3:FF;
+06C4:FF;
+06C5:F3;
+06C6:F3;
+06C7:F7;
+06C8:FB;
+06C9:FF;
+06CA:FF;
+06CB:FF;
+06CC:00;
+06CD:00;
+06CE:00;
+06CF:00;
+06D0:FF;
+06D1:FF;
+06D2:FF;
+06D3:FF;
+06D4:C1;
+06D5:FF;
+06D6:FF;
+06D7:FF;
+06D8:FF;
+06D9:FF;
+06DA:FF;
+06DB:FF;
+06DC:00;
+06DD:00;
+06DE:00;
+06DF:00;
+06E0:FF;
+06E1:FF;
+06E2:FF;
+06E3:FF;
+06E4:FF;
+06E5:FF;
+06E6:F3;
+06E7:F3;
+06E8:FF;
+06E9:FF;
+06EA:FF;
+06EB:FF;
+06EC:00;
+06ED:00;
+06EE:00;
+06EF:00;
+06F0:FF;
+06F1:FF;
+06F2:DF;
+06F3:EF;
+06F4:F7;
+06F5:FB;
+06F6:FD;
+06F7:FF;
+06F8:FF;
+06F9:FF;
+06FA:FF;
+06FB:FF;
+06FC:00;
+06FD:00;
+06FE:00;
+06FF:00;
+0700:FF;
+0701:F3;
+0702:ED;
+0703:ED;
+0704:ED;
+0705:ED;
+0706:ED;
+0707:F3;
+0708:FF;
+0709:FF;
+070A:FF;
+070B:FF;
+070C:00;
+070D:00;
+070E:00;
+070F:00;
+0710:FF;
+0711:F7;
+0712:F3;
+0713:F7;
+0714:F7;
+0715:F7;
+0716:F7;
+0717:E3;
+0718:FF;
+0719:FF;
+071A:FF;
+071B:FF;
+071C:00;
+071D:00;
+071E:00;
+071F:00;
+0720:FF;
+0721:E3;
+0722:DD;
+0723:DF;
+0724:E3;
+0725:FD;
+0726:FD;
+0727:C1;
+0728:FF;
+0729:FF;
+072A:FF;
+072B:FF;
+072C:00;
+072D:00;
+072E:00;
+072F:00;
+0730:FF;
+0731:E3;
+0732:DD;
+0733:DF;
+0734:E3;
+0735:DF;
+0736:DD;
+0737:E3;
+0738:FF;
+0739:FF;
+073A:FF;
+073B:FF;
+073C:00;
+073D:00;
+073E:00;
+073F:00;
+0740:FF;
+0741:EF;
+0742:E7;
+0743:EB;
+0744:C1;
+0745:EF;
+0746:EF;
+0747:EF;
+0748:FF;
+0749:FF;
+074A:FF;
+074B:FF;
+074C:00;
+074D:00;
+074E:00;
+074F:00;
+0750:FF;
+0751:C1;
+0752:FD;
+0753:E1;
+0754:DF;
+0755:DF;
+0756:DD;
+0757:E3;
+0758:FF;
+0759:FF;
+075A:FF;
+075B:FF;
+075C:00;
+075D:00;
+075E:00;
+075F:00;
+0760:FF;
+0761:E3;
+0762:FD;
+0763:FD;
+0764:E1;
+0765:DD;
+0766:DD;
+0767:E3;
+0768:FF;
+0769:FF;
+076A:FF;
+076B:FF;
+076C:00;
+076D:00;
+076E:00;
+076F:00;
+0770:FF;
+0771:C1;
+0772:DF;
+0773:EF;
+0774:F7;
+0775:FB;
+0776:FD;
+0777:FD;
+0778:FF;
+0779:FF;
+077A:FF;
+077B:FF;
+077C:00;
+077D:00;
+077E:00;
+077F:00;
+0780:FF;
+0781:E3;
+0782:DD;
+0783:DD;
+0784:E3;
+0785:DD;
+0786:DD;
+0787:E3;
+0788:FF;
+0789:FF;
+078A:FF;
+078B:FF;
+078C:00;
+078D:00;
+078E:00;
+078F:00;
+0790:FF;
+0791:E3;
+0792:DD;
+0793:DD;
+0794:C3;
+0795:DF;
+0796:DF;
+0797:E3;
+0798:FF;
+0799:FF;
+079A:FF;
+079B:FF;
+079C:00;
+079D:00;
+079E:00;
+079F:00;
+07A0:FF;
+07A1:FF;
+07A2:F3;
+07A3:F3;
+07A4:FF;
+07A5:F3;
+07A6:F3;
+07A7:FF;
+07A8:FF;
+07A9:FF;
+07AA:FF;
+07AB:FF;
+07AC:00;
+07AD:00;
+07AE:00;
+07AF:00;
+07B0:FF;
+07B1:FF;
+07B2:F3;
+07B3:F3;
+07B4:FF;
+07B5:F3;
+07B6:F3;
+07B7:F7;
+07B8:FB;
+07B9:FF;
+07BA:FF;
+07BB:FF;
+07BC:00;
+07BD:00;
+07BE:00;
+07BF:00;
+07C0:FF;
+07C1:DF;
+07C2:EF;
+07C3:F7;
+07C4:FB;
+07C5:F7;
+07C6:EF;
+07C7:DF;
+07C8:FF;
+07C9:FF;
+07CA:FF;
+07CB:FF;
+07CC:00;
+07CD:00;
+07CE:00;
+07CF:00;
+07D0:FF;
+07D1:FF;
+07D2:FF;
+07D3:C1;
+07D4:FF;
+07D5:C1;
+07D6:FF;
+07D7:FF;
+07D8:FF;
+07D9:FF;
+07DA:FF;
+07DB:FF;
+07DC:00;
+07DD:00;
+07DE:00;
+07DF:00;
+07E0:FF;
+07E1:FB;
+07E2:F7;
+07E3:EF;
+07E4:DF;
+07E5:EF;
+07E6:F7;
+07E7:FB;
+07E8:FF;
+07E9:FF;
+07EA:FF;
+07EB:FF;
+07EC:00;
+07ED:00;
+07EE:00;
+07EF:00;
+07F0:FF;
+07F1:E3;
+07F2:DD;
+07F3:DF;
+07F4:EF;
+07F5:F7;
+07F6:FF;
+07F7:F7;
+07F8:FF;
+07F9:FF;
+07FA:FF;
+07FB:FF;
+07FC:00;
+07FD:00;
+07FE:00;
+07FF:00;
+0800:00;
+0801:00;
+0802:00;
+0803:00;
+0804:00;
+0805:00;
+0806:00;
+0807:00;
+0808:00;
+0809:00;
+080A:00;
+080B:00;
+080C:00;
+080D:00;
+080E:00;
+080F:00;
+0810:00;
+0811:00;
+0812:00;
+0813:00;
+0814:00;
+0815:00;
+0816:F0;
+0817:F0;
+0818:F0;
+0819:F0;
+081A:F0;
+081B:F0;
+081C:00;
+081D:00;
+081E:00;
+081F:00;
+0820:00;
+0821:00;
+0822:00;
+0823:00;
+0824:00;
+0825:00;
+0826:0F;
+0827:0F;
+0828:0F;
+0829:0F;
+082A:0F;
+082B:0F;
+082C:00;
+082D:00;
+082E:00;
+082F:00;
+0830:00;
+0831:00;
+0832:00;
+0833:00;
+0834:00;
+0835:00;
+0836:FF;
+0837:FF;
+0838:FF;
+0839:FF;
+083A:FF;
+083B:FF;
+083C:00;
+083D:00;
+083E:00;
+083F:00;
+0840:F0;
+0841:F0;
+0842:F0;
+0843:F0;
+0844:F0;
+0845:F0;
+0846:00;
+0847:00;
+0848:00;
+0849:00;
+084A:00;
+084B:00;
+084C:00;
+084D:00;
+084E:00;
+084F:00;
+0850:F0;
+0851:F0;
+0852:F0;
+0853:F0;
+0854:F0;
+0855:F0;
+0856:F0;
+0857:F0;
+0858:F0;
+0859:F0;
+085A:F0;
+085B:F0;
+085C:00;
+085D:00;
+085E:00;
+085F:00;
+0860:F0;
+0861:F0;
+0862:F0;
+0863:F0;
+0864:F0;
+0865:F0;
+0866:0F;
+0867:0F;
+0868:0F;
+0869:0F;
+086A:0F;
+086B:0F;
+086C:00;
+086D:00;
+086E:00;
+086F:00;
+0870:F0;
+0871:F0;
+0872:F0;
+0873:F0;
+0874:F0;
+0875:F0;
+0876:FF;
+0877:FF;
+0878:FF;
+0879:FF;
+087A:FF;
+087B:FF;
+087C:00;
+087D:00;
+087E:00;
+087F:00;
+0880:0F;
+0881:0F;
+0882:0F;
+0883:0F;
+0884:0F;
+0885:0F;
+0886:00;
+0887:00;
+0888:00;
+0889:00;
+088A:00;
+088B:00;
+088C:00;
+088D:00;
+088E:00;
+088F:00;
+0890:0F;
+0891:0F;
+0892:0F;
+0893:0F;
+0894:0F;
+0895:0F;
+0896:F0;
+0897:F0;
+0898:F0;
+0899:F0;
+089A:F0;
+089B:F0;
+089C:00;
+089D:00;
+089E:00;
+089F:00;
+08A0:0F;
+08A1:0F;
+08A2:0F;
+08A3:0F;
+08A4:0F;
+08A5:0F;
+08A6:0F;
+08A7:0F;
+08A8:0F;
+08A9:0F;
+08AA:0F;
+08AB:0F;
+08AC:00;
+08AD:00;
+08AE:00;
+08AF:00;
+08B0:0F;
+08B1:0F;
+08B2:0F;
+08B3:0F;
+08B4:0F;
+08B5:0F;
+08B6:FF;
+08B7:FF;
+08B8:FF;
+08B9:FF;
+08BA:FF;
+08BB:FF;
+08BC:00;
+08BD:00;
+08BE:00;
+08BF:00;
+08C0:FF;
+08C1:FF;
+08C2:FF;
+08C3:FF;
+08C4:FF;
+08C5:FF;
+08C6:00;
+08C7:00;
+08C8:00;
+08C9:00;
+08CA:00;
+08CB:00;
+08CC:00;
+08CD:00;
+08CE:00;
+08CF:00;
+08D0:FF;
+08D1:FF;
+08D2:FF;
+08D3:FF;
+08D4:FF;
+08D5:FF;
+08D6:F0;
+08D7:F0;
+08D8:F0;
+08D9:F0;
+08DA:F0;
+08DB:F0;
+08DC:00;
+08DD:00;
+08DE:00;
+08DF:00;
+08E0:FF;
+08E1:FF;
+08E2:FF;
+08E3:FF;
+08E4:FF;
+08E5:FF;
+08E6:0F;
+08E7:0F;
+08E8:0F;
+08E9:0F;
+08EA:0F;
+08EB:0F;
+08EC:00;
+08ED:00;
+08EE:00;
+08EF:00;
+08F0:FF;
+08F1:FF;
+08F2:FF;
+08F3:FF;
+08F4:FF;
+08F5:FF;
+08F6:FF;
+08F7:FF;
+08F8:FF;
+08F9:FF;
+08FA:FF;
+08FB:FF;
+08FC:00;
+08FD:00;
+08FE:00;
+08FF:00;
+0900:00;
+0901:00;
+0902:00;
+0903:00;
+0904:00;
+0905:00;
+0906:00;
+0907:00;
+0908:00;
+0909:00;
+090A:00;
+090B:00;
+090C:00;
+090D:00;
+090E:00;
+090F:00;
+0910:00;
+0911:00;
+0912:00;
+0913:00;
+0914:00;
+0915:00;
+0916:F0;
+0917:F0;
+0918:F0;
+0919:F0;
+091A:F0;
+091B:F0;
+091C:00;
+091D:00;
+091E:00;
+091F:00;
+0920:00;
+0921:00;
+0922:00;
+0923:00;
+0924:00;
+0925:00;
+0926:0F;
+0927:0F;
+0928:0F;
+0929:0F;
+092A:0F;
+092B:0F;
+092C:00;
+092D:00;
+092E:00;
+092F:00;
+0930:00;
+0931:00;
+0932:00;
+0933:00;
+0934:00;
+0935:00;
+0936:FF;
+0937:FF;
+0938:FF;
+0939:FF;
+093A:FF;
+093B:FF;
+093C:00;
+093D:00;
+093E:00;
+093F:00;
+0940:F0;
+0941:F0;
+0942:F0;
+0943:F0;
+0944:F0;
+0945:F0;
+0946:00;
+0947:00;
+0948:00;
+0949:00;
+094A:00;
+094B:00;
+094C:00;
+094D:00;
+094E:00;
+094F:00;
+0950:F0;
+0951:F0;
+0952:F0;
+0953:F0;
+0954:F0;
+0955:F0;
+0956:F0;
+0957:F0;
+0958:F0;
+0959:F0;
+095A:F0;
+095B:F0;
+095C:00;
+095D:00;
+095E:00;
+095F:00;
+0960:F0;
+0961:F0;
+0962:F0;
+0963:F0;
+0964:F0;
+0965:F0;
+0966:0F;
+0967:0F;
+0968:0F;
+0969:0F;
+096A:0F;
+096B:0F;
+096C:00;
+096D:00;
+096E:00;
+096F:00;
+0970:F0;
+0971:F0;
+0972:F0;
+0973:F0;
+0974:F0;
+0975:F0;
+0976:FF;
+0977:FF;
+0978:FF;
+0979:FF;
+097A:FF;
+097B:FF;
+097C:00;
+097D:00;
+097E:00;
+097F:00;
+0980:0F;
+0981:0F;
+0982:0F;
+0983:0F;
+0984:0F;
+0985:0F;
+0986:00;
+0987:00;
+0988:00;
+0989:00;
+098A:00;
+098B:00;
+098C:00;
+098D:00;
+098E:00;
+098F:00;
+0990:0F;
+0991:0F;
+0992:0F;
+0993:0F;
+0994:0F;
+0995:0F;
+0996:F0;
+0997:F0;
+0998:F0;
+0999:F0;
+099A:F0;
+099B:F0;
+099C:00;
+099D:00;
+099E:00;
+099F:00;
+09A0:0F;
+09A1:0F;
+09A2:0F;
+09A3:0F;
+09A4:0F;
+09A5:0F;
+09A6:0F;
+09A7:0F;
+09A8:0F;
+09A9:0F;
+09AA:0F;
+09AB:0F;
+09AC:00;
+09AD:00;
+09AE:00;
+09AF:00;
+09B0:0F;
+09B1:0F;
+09B2:0F;
+09B3:0F;
+09B4:0F;
+09B5:0F;
+09B6:FF;
+09B7:FF;
+09B8:FF;
+09B9:FF;
+09BA:FF;
+09BB:FF;
+09BC:00;
+09BD:00;
+09BE:00;
+09BF:00;
+09C0:FF;
+09C1:FF;
+09C2:FF;
+09C3:FF;
+09C4:FF;
+09C5:FF;
+09C6:00;
+09C7:00;
+09C8:00;
+09C9:00;
+09CA:00;
+09CB:00;
+09CC:00;
+09CD:00;
+09CE:00;
+09CF:00;
+09D0:FF;
+09D1:FF;
+09D2:FF;
+09D3:FF;
+09D4:FF;
+09D5:FF;
+09D6:F0;
+09D7:F0;
+09D8:F0;
+09D9:F0;
+09DA:F0;
+09DB:F0;
+09DC:00;
+09DD:00;
+09DE:00;
+09DF:00;
+09E0:FF;
+09E1:FF;
+09E2:FF;
+09E3:FF;
+09E4:FF;
+09E5:FF;
+09E6:0F;
+09E7:0F;
+09E8:0F;
+09E9:0F;
+09EA:0F;
+09EB:0F;
+09EC:00;
+09ED:00;
+09EE:00;
+09EF:00;
+09F0:FF;
+09F1:FF;
+09F2:FF;
+09F3:FF;
+09F4:FF;
+09F5:FF;
+09F6:FF;
+09F7:FF;
+09F8:FF;
+09F9:FF;
+09FA:FF;
+09FB:FF;
+09FC:00;
+09FD:00;
+09FE:00;
+09FF:00;
+0A00:00;
+0A01:00;
+0A02:00;
+0A03:00;
+0A04:00;
+0A05:00;
+0A06:00;
+0A07:00;
+0A08:00;
+0A09:00;
+0A0A:00;
+0A0B:00;
+0A0C:00;
+0A0D:00;
+0A0E:00;
+0A0F:00;
+0A10:00;
+0A11:00;
+0A12:00;
+0A13:00;
+0A14:00;
+0A15:00;
+0A16:F0;
+0A17:F0;
+0A18:F0;
+0A19:F0;
+0A1A:F0;
+0A1B:F0;
+0A1C:00;
+0A1D:00;
+0A1E:00;
+0A1F:00;
+0A20:00;
+0A21:00;
+0A22:00;
+0A23:00;
+0A24:00;
+0A25:00;
+0A26:0F;
+0A27:0F;
+0A28:0F;
+0A29:0F;
+0A2A:0F;
+0A2B:0F;
+0A2C:00;
+0A2D:00;
+0A2E:00;
+0A2F:00;
+0A30:00;
+0A31:00;
+0A32:00;
+0A33:00;
+0A34:00;
+0A35:00;
+0A36:FF;
+0A37:FF;
+0A38:FF;
+0A39:FF;
+0A3A:FF;
+0A3B:FF;
+0A3C:00;
+0A3D:00;
+0A3E:00;
+0A3F:00;
+0A40:F0;
+0A41:F0;
+0A42:F0;
+0A43:F0;
+0A44:F0;
+0A45:F0;
+0A46:00;
+0A47:00;
+0A48:00;
+0A49:00;
+0A4A:00;
+0A4B:00;
+0A4C:00;
+0A4D:00;
+0A4E:00;
+0A4F:00;
+0A50:F0;
+0A51:F0;
+0A52:F0;
+0A53:F0;
+0A54:F0;
+0A55:F0;
+0A56:F0;
+0A57:F0;
+0A58:F0;
+0A59:F0;
+0A5A:F0;
+0A5B:F0;
+0A5C:00;
+0A5D:00;
+0A5E:00;
+0A5F:00;
+0A60:F0;
+0A61:F0;
+0A62:F0;
+0A63:F0;
+0A64:F0;
+0A65:F0;
+0A66:0F;
+0A67:0F;
+0A68:0F;
+0A69:0F;
+0A6A:0F;
+0A6B:0F;
+0A6C:00;
+0A6D:00;
+0A6E:00;
+0A6F:00;
+0A70:F0;
+0A71:F0;
+0A72:F0;
+0A73:F0;
+0A74:F0;
+0A75:F0;
+0A76:FF;
+0A77:FF;
+0A78:FF;
+0A79:FF;
+0A7A:FF;
+0A7B:FF;
+0A7C:00;
+0A7D:00;
+0A7E:00;
+0A7F:00;
+0A80:0F;
+0A81:0F;
+0A82:0F;
+0A83:0F;
+0A84:0F;
+0A85:0F;
+0A86:00;
+0A87:00;
+0A88:00;
+0A89:00;
+0A8A:00;
+0A8B:00;
+0A8C:00;
+0A8D:00;
+0A8E:00;
+0A8F:00;
+0A90:0F;
+0A91:0F;
+0A92:0F;
+0A93:0F;
+0A94:0F;
+0A95:0F;
+0A96:F0;
+0A97:F0;
+0A98:F0;
+0A99:F0;
+0A9A:F0;
+0A9B:F0;
+0A9C:00;
+0A9D:00;
+0A9E:00;
+0A9F:00;
+0AA0:0F;
+0AA1:0F;
+0AA2:0F;
+0AA3:0F;
+0AA4:0F;
+0AA5:0F;
+0AA6:0F;
+0AA7:0F;
+0AA8:0F;
+0AA9:0F;
+0AAA:0F;
+0AAB:0F;
+0AAC:00;
+0AAD:00;
+0AAE:00;
+0AAF:00;
+0AB0:0F;
+0AB1:0F;
+0AB2:0F;
+0AB3:0F;
+0AB4:0F;
+0AB5:0F;
+0AB6:FF;
+0AB7:FF;
+0AB8:FF;
+0AB9:FF;
+0ABA:FF;
+0ABB:FF;
+0ABC:00;
+0ABD:00;
+0ABE:00;
+0ABF:00;
+0AC0:FF;
+0AC1:FF;
+0AC2:FF;
+0AC3:FF;
+0AC4:FF;
+0AC5:FF;
+0AC6:00;
+0AC7:00;
+0AC8:00;
+0AC9:00;
+0ACA:00;
+0ACB:00;
+0ACC:00;
+0ACD:00;
+0ACE:00;
+0ACF:00;
+0AD0:FF;
+0AD1:FF;
+0AD2:FF;
+0AD3:FF;
+0AD4:FF;
+0AD5:FF;
+0AD6:F0;
+0AD7:F0;
+0AD8:F0;
+0AD9:F0;
+0ADA:F0;
+0ADB:F0;
+0ADC:00;
+0ADD:00;
+0ADE:00;
+0ADF:00;
+0AE0:FF;
+0AE1:FF;
+0AE2:FF;
+0AE3:FF;
+0AE4:FF;
+0AE5:FF;
+0AE6:0F;
+0AE7:0F;
+0AE8:0F;
+0AE9:0F;
+0AEA:0F;
+0AEB:0F;
+0AEC:00;
+0AED:00;
+0AEE:00;
+0AEF:00;
+0AF0:FF;
+0AF1:FF;
+0AF2:FF;
+0AF3:FF;
+0AF4:FF;
+0AF5:FF;
+0AF6:FF;
+0AF7:FF;
+0AF8:FF;
+0AF9:FF;
+0AFA:FF;
+0AFB:FF;
+0AFC:00;
+0AFD:00;
+0AFE:00;
+0AFF:00;
+0B00:00;
+0B01:00;
+0B02:00;
+0B03:00;
+0B04:00;
+0B05:00;
+0B06:00;
+0B07:00;
+0B08:00;
+0B09:00;
+0B0A:00;
+0B0B:00;
+0B0C:00;
+0B0D:00;
+0B0E:00;
+0B0F:00;
+0B10:00;
+0B11:00;
+0B12:00;
+0B13:00;
+0B14:00;
+0B15:00;
+0B16:F0;
+0B17:F0;
+0B18:F0;
+0B19:F0;
+0B1A:F0;
+0B1B:F0;
+0B1C:00;
+0B1D:00;
+0B1E:00;
+0B1F:00;
+0B20:00;
+0B21:00;
+0B22:00;
+0B23:00;
+0B24:00;
+0B25:00;
+0B26:0F;
+0B27:0F;
+0B28:0F;
+0B29:0F;
+0B2A:0F;
+0B2B:0F;
+0B2C:00;
+0B2D:00;
+0B2E:00;
+0B2F:00;
+0B30:00;
+0B31:00;
+0B32:00;
+0B33:00;
+0B34:00;
+0B35:00;
+0B36:FF;
+0B37:FF;
+0B38:FF;
+0B39:FF;
+0B3A:FF;
+0B3B:FF;
+0B3C:00;
+0B3D:00;
+0B3E:00;
+0B3F:00;
+0B40:F0;
+0B41:F0;
+0B42:F0;
+0B43:F0;
+0B44:F0;
+0B45:F0;
+0B46:00;
+0B47:00;
+0B48:00;
+0B49:00;
+0B4A:00;
+0B4B:00;
+0B4C:00;
+0B4D:00;
+0B4E:00;
+0B4F:00;
+0B50:F0;
+0B51:F0;
+0B52:F0;
+0B53:F0;
+0B54:F0;
+0B55:F0;
+0B56:F0;
+0B57:F0;
+0B58:F0;
+0B59:F0;
+0B5A:F0;
+0B5B:F0;
+0B5C:00;
+0B5D:00;
+0B5E:00;
+0B5F:00;
+0B60:F0;
+0B61:F0;
+0B62:F0;
+0B63:F0;
+0B64:F0;
+0B65:F0;
+0B66:0F;
+0B67:0F;
+0B68:0F;
+0B69:0F;
+0B6A:0F;
+0B6B:0F;
+0B6C:00;
+0B6D:00;
+0B6E:00;
+0B6F:00;
+0B70:F0;
+0B71:F0;
+0B72:F0;
+0B73:F0;
+0B74:F0;
+0B75:F0;
+0B76:FF;
+0B77:FF;
+0B78:FF;
+0B79:FF;
+0B7A:FF;
+0B7B:FF;
+0B7C:00;
+0B7D:00;
+0B7E:00;
+0B7F:00;
+0B80:0F;
+0B81:0F;
+0B82:0F;
+0B83:0F;
+0B84:0F;
+0B85:0F;
+0B86:00;
+0B87:00;
+0B88:00;
+0B89:00;
+0B8A:00;
+0B8B:00;
+0B8C:00;
+0B8D:00;
+0B8E:00;
+0B8F:00;
+0B90:0F;
+0B91:0F;
+0B92:0F;
+0B93:0F;
+0B94:0F;
+0B95:0F;
+0B96:F0;
+0B97:F0;
+0B98:F0;
+0B99:F0;
+0B9A:F0;
+0B9B:F0;
+0B9C:00;
+0B9D:00;
+0B9E:00;
+0B9F:00;
+0BA0:0F;
+0BA1:0F;
+0BA2:0F;
+0BA3:0F;
+0BA4:0F;
+0BA5:0F;
+0BA6:0F;
+0BA7:0F;
+0BA8:0F;
+0BA9:0F;
+0BAA:0F;
+0BAB:0F;
+0BAC:00;
+0BAD:00;
+0BAE:00;
+0BAF:00;
+0BB0:0F;
+0BB1:0F;
+0BB2:0F;
+0BB3:0F;
+0BB4:0F;
+0BB5:0F;
+0BB6:FF;
+0BB7:FF;
+0BB8:FF;
+0BB9:FF;
+0BBA:FF;
+0BBB:FF;
+0BBC:00;
+0BBD:00;
+0BBE:00;
+0BBF:00;
+0BC0:FF;
+0BC1:FF;
+0BC2:FF;
+0BC3:FF;
+0BC4:FF;
+0BC5:FF;
+0BC6:00;
+0BC7:00;
+0BC8:00;
+0BC9:00;
+0BCA:00;
+0BCB:00;
+0BCC:00;
+0BCD:00;
+0BCE:00;
+0BCF:00;
+0BD0:FF;
+0BD1:FF;
+0BD2:FF;
+0BD3:FF;
+0BD4:FF;
+0BD5:FF;
+0BD6:F0;
+0BD7:F0;
+0BD8:F0;
+0BD9:F0;
+0BDA:F0;
+0BDB:F0;
+0BDC:00;
+0BDD:00;
+0BDE:00;
+0BDF:00;
+0BE0:FF;
+0BE1:FF;
+0BE2:FF;
+0BE3:FF;
+0BE4:FF;
+0BE5:FF;
+0BE6:0F;
+0BE7:0F;
+0BE8:0F;
+0BE9:0F;
+0BEA:0F;
+0BEB:0F;
+0BEC:00;
+0BED:00;
+0BEE:00;
+0BEF:00;
+0BF0:FF;
+0BF1:FF;
+0BF2:FF;
+0BF3:FF;
+0BF4:FF;
+0BF5:FF;
+0BF6:FF;
+0BF7:FF;
+0BF8:FF;
+0BF9:FF;
+0BFA:FF;
+0BFB:FF;
+0BFC:00;
+0BFD:00;
+0BFE:00;
+0BFF:00;
+0C00:00;
+0C01:00;
+0C02:00;
+0C03:00;
+0C04:00;
+0C05:00;
+0C06:00;
+0C07:00;
+0C08:00;
+0C09:00;
+0C0A:00;
+0C0B:00;
+0C0C:00;
+0C0D:00;
+0C0E:00;
+0C0F:00;
+0C10:00;
+0C11:00;
+0C12:00;
+0C13:00;
+0C14:00;
+0C15:00;
+0C16:F0;
+0C17:F0;
+0C18:F0;
+0C19:F0;
+0C1A:F0;
+0C1B:F0;
+0C1C:00;
+0C1D:00;
+0C1E:00;
+0C1F:00;
+0C20:00;
+0C21:00;
+0C22:00;
+0C23:00;
+0C24:00;
+0C25:00;
+0C26:0F;
+0C27:0F;
+0C28:0F;
+0C29:0F;
+0C2A:0F;
+0C2B:0F;
+0C2C:00;
+0C2D:00;
+0C2E:00;
+0C2F:00;
+0C30:00;
+0C31:00;
+0C32:00;
+0C33:00;
+0C34:00;
+0C35:00;
+0C36:FF;
+0C37:FF;
+0C38:FF;
+0C39:FF;
+0C3A:FF;
+0C3B:FF;
+0C3C:00;
+0C3D:00;
+0C3E:00;
+0C3F:00;
+0C40:F0;
+0C41:F0;
+0C42:F0;
+0C43:F0;
+0C44:F0;
+0C45:F0;
+0C46:00;
+0C47:00;
+0C48:00;
+0C49:00;
+0C4A:00;
+0C4B:00;
+0C4C:00;
+0C4D:00;
+0C4E:00;
+0C4F:00;
+0C50:F0;
+0C51:F0;
+0C52:F0;
+0C53:F0;
+0C54:F0;
+0C55:F0;
+0C56:F0;
+0C57:F0;
+0C58:F0;
+0C59:F0;
+0C5A:F0;
+0C5B:F0;
+0C5C:00;
+0C5D:00;
+0C5E:00;
+0C5F:00;
+0C60:F0;
+0C61:F0;
+0C62:F0;
+0C63:F0;
+0C64:F0;
+0C65:F0;
+0C66:0F;
+0C67:0F;
+0C68:0F;
+0C69:0F;
+0C6A:0F;
+0C6B:0F;
+0C6C:00;
+0C6D:00;
+0C6E:00;
+0C6F:00;
+0C70:F0;
+0C71:F0;
+0C72:F0;
+0C73:F0;
+0C74:F0;
+0C75:F0;
+0C76:FF;
+0C77:FF;
+0C78:FF;
+0C79:FF;
+0C7A:FF;
+0C7B:FF;
+0C7C:00;
+0C7D:00;
+0C7E:00;
+0C7F:00;
+0C80:0F;
+0C81:0F;
+0C82:0F;
+0C83:0F;
+0C84:0F;
+0C85:0F;
+0C86:00;
+0C87:00;
+0C88:00;
+0C89:00;
+0C8A:00;
+0C8B:00;
+0C8C:00;
+0C8D:00;
+0C8E:00;
+0C8F:00;
+0C90:0F;
+0C91:0F;
+0C92:0F;
+0C93:0F;
+0C94:0F;
+0C95:0F;
+0C96:F0;
+0C97:F0;
+0C98:F0;
+0C99:F0;
+0C9A:F0;
+0C9B:F0;
+0C9C:00;
+0C9D:00;
+0C9E:00;
+0C9F:00;
+0CA0:0F;
+0CA1:0F;
+0CA2:0F;
+0CA3:0F;
+0CA4:0F;
+0CA5:0F;
+0CA6:0F;
+0CA7:0F;
+0CA8:0F;
+0CA9:0F;
+0CAA:0F;
+0CAB:0F;
+0CAC:00;
+0CAD:00;
+0CAE:00;
+0CAF:00;
+0CB0:0F;
+0CB1:0F;
+0CB2:0F;
+0CB3:0F;
+0CB4:0F;
+0CB5:0F;
+0CB6:FF;
+0CB7:FF;
+0CB8:FF;
+0CB9:FF;
+0CBA:FF;
+0CBB:FF;
+0CBC:00;
+0CBD:00;
+0CBE:00;
+0CBF:00;
+0CC0:FF;
+0CC1:FF;
+0CC2:FF;
+0CC3:FF;
+0CC4:FF;
+0CC5:FF;
+0CC6:00;
+0CC7:00;
+0CC8:00;
+0CC9:00;
+0CCA:00;
+0CCB:00;
+0CCC:00;
+0CCD:00;
+0CCE:00;
+0CCF:00;
+0CD0:FF;
+0CD1:FF;
+0CD2:FF;
+0CD3:FF;
+0CD4:FF;
+0CD5:FF;
+0CD6:F0;
+0CD7:F0;
+0CD8:F0;
+0CD9:F0;
+0CDA:F0;
+0CDB:F0;
+0CDC:00;
+0CDD:00;
+0CDE:00;
+0CDF:00;
+0CE0:FF;
+0CE1:FF;
+0CE2:FF;
+0CE3:FF;
+0CE4:FF;
+0CE5:FF;
+0CE6:0F;
+0CE7:0F;
+0CE8:0F;
+0CE9:0F;
+0CEA:0F;
+0CEB:0F;
+0CEC:00;
+0CED:00;
+0CEE:00;
+0CEF:00;
+0CF0:FF;
+0CF1:FF;
+0CF2:FF;
+0CF3:FF;
+0CF4:FF;
+0CF5:FF;
+0CF6:FF;
+0CF7:FF;
+0CF8:FF;
+0CF9:FF;
+0CFA:FF;
+0CFB:FF;
+0CFC:00;
+0CFD:00;
+0CFE:00;
+0CFF:00;
+0D00:00;
+0D01:00;
+0D02:00;
+0D03:00;
+0D04:00;
+0D05:00;
+0D06:00;
+0D07:00;
+0D08:00;
+0D09:00;
+0D0A:00;
+0D0B:00;
+0D0C:00;
+0D0D:00;
+0D0E:00;
+0D0F:00;
+0D10:00;
+0D11:00;
+0D12:00;
+0D13:00;
+0D14:00;
+0D15:00;
+0D16:F0;
+0D17:F0;
+0D18:F0;
+0D19:F0;
+0D1A:F0;
+0D1B:F0;
+0D1C:00;
+0D1D:00;
+0D1E:00;
+0D1F:00;
+0D20:00;
+0D21:00;
+0D22:00;
+0D23:00;
+0D24:00;
+0D25:00;
+0D26:0F;
+0D27:0F;
+0D28:0F;
+0D29:0F;
+0D2A:0F;
+0D2B:0F;
+0D2C:00;
+0D2D:00;
+0D2E:00;
+0D2F:00;
+0D30:00;
+0D31:00;
+0D32:00;
+0D33:00;
+0D34:00;
+0D35:00;
+0D36:FF;
+0D37:FF;
+0D38:FF;
+0D39:FF;
+0D3A:FF;
+0D3B:FF;
+0D3C:00;
+0D3D:00;
+0D3E:00;
+0D3F:00;
+0D40:F0;
+0D41:F0;
+0D42:F0;
+0D43:F0;
+0D44:F0;
+0D45:F0;
+0D46:00;
+0D47:00;
+0D48:00;
+0D49:00;
+0D4A:00;
+0D4B:00;
+0D4C:00;
+0D4D:00;
+0D4E:00;
+0D4F:00;
+0D50:F0;
+0D51:F0;
+0D52:F0;
+0D53:F0;
+0D54:F0;
+0D55:F0;
+0D56:F0;
+0D57:F0;
+0D58:F0;
+0D59:F0;
+0D5A:F0;
+0D5B:F0;
+0D5C:00;
+0D5D:00;
+0D5E:00;
+0D5F:00;
+0D60:F0;
+0D61:F0;
+0D62:F0;
+0D63:F0;
+0D64:F0;
+0D65:F0;
+0D66:0F;
+0D67:0F;
+0D68:0F;
+0D69:0F;
+0D6A:0F;
+0D6B:0F;
+0D6C:00;
+0D6D:00;
+0D6E:00;
+0D6F:00;
+0D70:F0;
+0D71:F0;
+0D72:F0;
+0D73:F0;
+0D74:F0;
+0D75:F0;
+0D76:FF;
+0D77:FF;
+0D78:FF;
+0D79:FF;
+0D7A:FF;
+0D7B:FF;
+0D7C:00;
+0D7D:00;
+0D7E:00;
+0D7F:00;
+0D80:0F;
+0D81:0F;
+0D82:0F;
+0D83:0F;
+0D84:0F;
+0D85:0F;
+0D86:00;
+0D87:00;
+0D88:00;
+0D89:00;
+0D8A:00;
+0D8B:00;
+0D8C:00;
+0D8D:00;
+0D8E:00;
+0D8F:00;
+0D90:0F;
+0D91:0F;
+0D92:0F;
+0D93:0F;
+0D94:0F;
+0D95:0F;
+0D96:F0;
+0D97:F0;
+0D98:F0;
+0D99:F0;
+0D9A:F0;
+0D9B:F0;
+0D9C:00;
+0D9D:00;
+0D9E:00;
+0D9F:00;
+0DA0:0F;
+0DA1:0F;
+0DA2:0F;
+0DA3:0F;
+0DA4:0F;
+0DA5:0F;
+0DA6:0F;
+0DA7:0F;
+0DA8:0F;
+0DA9:0F;
+0DAA:0F;
+0DAB:0F;
+0DAC:00;
+0DAD:00;
+0DAE:00;
+0DAF:00;
+0DB0:0F;
+0DB1:0F;
+0DB2:0F;
+0DB3:0F;
+0DB4:0F;
+0DB5:0F;
+0DB6:FF;
+0DB7:FF;
+0DB8:FF;
+0DB9:FF;
+0DBA:FF;
+0DBB:FF;
+0DBC:00;
+0DBD:00;
+0DBE:00;
+0DBF:00;
+0DC0:FF;
+0DC1:FF;
+0DC2:FF;
+0DC3:FF;
+0DC4:FF;
+0DC5:FF;
+0DC6:00;
+0DC7:00;
+0DC8:00;
+0DC9:00;
+0DCA:00;
+0DCB:00;
+0DCC:00;
+0DCD:00;
+0DCE:00;
+0DCF:00;
+0DD0:FF;
+0DD1:FF;
+0DD2:FF;
+0DD3:FF;
+0DD4:FF;
+0DD5:FF;
+0DD6:F0;
+0DD7:F0;
+0DD8:F0;
+0DD9:F0;
+0DDA:F0;
+0DDB:F0;
+0DDC:00;
+0DDD:00;
+0DDE:00;
+0DDF:00;
+0DE0:FF;
+0DE1:FF;
+0DE2:FF;
+0DE3:FF;
+0DE4:FF;
+0DE5:FF;
+0DE6:0F;
+0DE7:0F;
+0DE8:0F;
+0DE9:0F;
+0DEA:0F;
+0DEB:0F;
+0DEC:00;
+0DED:00;
+0DEE:00;
+0DEF:00;
+0DF0:FF;
+0DF1:FF;
+0DF2:FF;
+0DF3:FF;
+0DF4:FF;
+0DF5:FF;
+0DF6:FF;
+0DF7:FF;
+0DF8:FF;
+0DF9:FF;
+0DFA:FF;
+0DFB:FF;
+0DFC:00;
+0DFD:00;
+0DFE:00;
+0DFF:00;
+0E00:00;
+0E01:00;
+0E02:00;
+0E03:00;
+0E04:00;
+0E05:00;
+0E06:00;
+0E07:00;
+0E08:00;
+0E09:00;
+0E0A:00;
+0E0B:00;
+0E0C:00;
+0E0D:00;
+0E0E:00;
+0E0F:00;
+0E10:00;
+0E11:00;
+0E12:00;
+0E13:00;
+0E14:00;
+0E15:00;
+0E16:F0;
+0E17:F0;
+0E18:F0;
+0E19:F0;
+0E1A:F0;
+0E1B:F0;
+0E1C:00;
+0E1D:00;
+0E1E:00;
+0E1F:00;
+0E20:00;
+0E21:00;
+0E22:00;
+0E23:00;
+0E24:00;
+0E25:00;
+0E26:0F;
+0E27:0F;
+0E28:0F;
+0E29:0F;
+0E2A:0F;
+0E2B:0F;
+0E2C:00;
+0E2D:00;
+0E2E:00;
+0E2F:00;
+0E30:00;
+0E31:00;
+0E32:00;
+0E33:00;
+0E34:00;
+0E35:00;
+0E36:FF;
+0E37:FF;
+0E38:FF;
+0E39:FF;
+0E3A:FF;
+0E3B:FF;
+0E3C:00;
+0E3D:00;
+0E3E:00;
+0E3F:00;
+0E40:F0;
+0E41:F0;
+0E42:F0;
+0E43:F0;
+0E44:F0;
+0E45:F0;
+0E46:00;
+0E47:00;
+0E48:00;
+0E49:00;
+0E4A:00;
+0E4B:00;
+0E4C:00;
+0E4D:00;
+0E4E:00;
+0E4F:00;
+0E50:F0;
+0E51:F0;
+0E52:F0;
+0E53:F0;
+0E54:F0;
+0E55:F0;
+0E56:F0;
+0E57:F0;
+0E58:F0;
+0E59:F0;
+0E5A:F0;
+0E5B:F0;
+0E5C:00;
+0E5D:00;
+0E5E:00;
+0E5F:00;
+0E60:F0;
+0E61:F0;
+0E62:F0;
+0E63:F0;
+0E64:F0;
+0E65:F0;
+0E66:0F;
+0E67:0F;
+0E68:0F;
+0E69:0F;
+0E6A:0F;
+0E6B:0F;
+0E6C:00;
+0E6D:00;
+0E6E:00;
+0E6F:00;
+0E70:F0;
+0E71:F0;
+0E72:F0;
+0E73:F0;
+0E74:F0;
+0E75:F0;
+0E76:FF;
+0E77:FF;
+0E78:FF;
+0E79:FF;
+0E7A:FF;
+0E7B:FF;
+0E7C:00;
+0E7D:00;
+0E7E:00;
+0E7F:00;
+0E80:0F;
+0E81:0F;
+0E82:0F;
+0E83:0F;
+0E84:0F;
+0E85:0F;
+0E86:00;
+0E87:00;
+0E88:00;
+0E89:00;
+0E8A:00;
+0E8B:00;
+0E8C:00;
+0E8D:00;
+0E8E:00;
+0E8F:00;
+0E90:0F;
+0E91:0F;
+0E92:0F;
+0E93:0F;
+0E94:0F;
+0E95:0F;
+0E96:F0;
+0E97:F0;
+0E98:F0;
+0E99:F0;
+0E9A:F0;
+0E9B:F0;
+0E9C:00;
+0E9D:00;
+0E9E:00;
+0E9F:00;
+0EA0:0F;
+0EA1:0F;
+0EA2:0F;
+0EA3:0F;
+0EA4:0F;
+0EA5:0F;
+0EA6:0F;
+0EA7:0F;
+0EA8:0F;
+0EA9:0F;
+0EAA:0F;
+0EAB:0F;
+0EAC:00;
+0EAD:00;
+0EAE:00;
+0EAF:00;
+0EB0:0F;
+0EB1:0F;
+0EB2:0F;
+0EB3:0F;
+0EB4:0F;
+0EB5:0F;
+0EB6:FF;
+0EB7:FF;
+0EB8:FF;
+0EB9:FF;
+0EBA:FF;
+0EBB:FF;
+0EBC:00;
+0EBD:00;
+0EBE:00;
+0EBF:00;
+0EC0:FF;
+0EC1:FF;
+0EC2:FF;
+0EC3:FF;
+0EC4:FF;
+0EC5:FF;
+0EC6:00;
+0EC7:00;
+0EC8:00;
+0EC9:00;
+0ECA:00;
+0ECB:00;
+0ECC:00;
+0ECD:00;
+0ECE:00;
+0ECF:00;
+0ED0:FF;
+0ED1:FF;
+0ED2:FF;
+0ED3:FF;
+0ED4:FF;
+0ED5:FF;
+0ED6:F0;
+0ED7:F0;
+0ED8:F0;
+0ED9:F0;
+0EDA:F0;
+0EDB:F0;
+0EDC:00;
+0EDD:00;
+0EDE:00;
+0EDF:00;
+0EE0:FF;
+0EE1:FF;
+0EE2:FF;
+0EE3:FF;
+0EE4:FF;
+0EE5:FF;
+0EE6:0F;
+0EE7:0F;
+0EE8:0F;
+0EE9:0F;
+0EEA:0F;
+0EEB:0F;
+0EEC:00;
+0EED:00;
+0EEE:00;
+0EEF:00;
+0EF0:FF;
+0EF1:FF;
+0EF2:FF;
+0EF3:FF;
+0EF4:FF;
+0EF5:FF;
+0EF6:FF;
+0EF7:FF;
+0EF8:FF;
+0EF9:FF;
+0EFA:FF;
+0EFB:FF;
+0EFC:00;
+0EFD:00;
+0EFE:00;
+0EFF:00;
+0F00:00;
+0F01:00;
+0F02:00;
+0F03:00;
+0F04:00;
+0F05:00;
+0F06:00;
+0F07:00;
+0F08:00;
+0F09:00;
+0F0A:00;
+0F0B:00;
+0F0C:00;
+0F0D:00;
+0F0E:00;
+0F0F:00;
+0F10:00;
+0F11:00;
+0F12:00;
+0F13:00;
+0F14:00;
+0F15:00;
+0F16:F0;
+0F17:F0;
+0F18:F0;
+0F19:F0;
+0F1A:F0;
+0F1B:F0;
+0F1C:00;
+0F1D:00;
+0F1E:00;
+0F1F:00;
+0F20:00;
+0F21:00;
+0F22:00;
+0F23:00;
+0F24:00;
+0F25:00;
+0F26:0F;
+0F27:0F;
+0F28:0F;
+0F29:0F;
+0F2A:0F;
+0F2B:0F;
+0F2C:00;
+0F2D:00;
+0F2E:00;
+0F2F:00;
+0F30:00;
+0F31:00;
+0F32:00;
+0F33:00;
+0F34:00;
+0F35:00;
+0F36:FF;
+0F37:FF;
+0F38:FF;
+0F39:FF;
+0F3A:FF;
+0F3B:FF;
+0F3C:00;
+0F3D:00;
+0F3E:00;
+0F3F:00;
+0F40:F0;
+0F41:F0;
+0F42:F0;
+0F43:F0;
+0F44:F0;
+0F45:F0;
+0F46:00;
+0F47:00;
+0F48:00;
+0F49:00;
+0F4A:00;
+0F4B:00;
+0F4C:00;
+0F4D:00;
+0F4E:00;
+0F4F:00;
+0F50:F0;
+0F51:F0;
+0F52:F0;
+0F53:F0;
+0F54:F0;
+0F55:F0;
+0F56:F0;
+0F57:F0;
+0F58:F0;
+0F59:F0;
+0F5A:F0;
+0F5B:F0;
+0F5C:00;
+0F5D:00;
+0F5E:00;
+0F5F:00;
+0F60:F0;
+0F61:F0;
+0F62:F0;
+0F63:F0;
+0F64:F0;
+0F65:F0;
+0F66:0F;
+0F67:0F;
+0F68:0F;
+0F69:0F;
+0F6A:0F;
+0F6B:0F;
+0F6C:00;
+0F6D:00;
+0F6E:00;
+0F6F:00;
+0F70:F0;
+0F71:F0;
+0F72:F0;
+0F73:F0;
+0F74:F0;
+0F75:F0;
+0F76:FF;
+0F77:FF;
+0F78:FF;
+0F79:FF;
+0F7A:FF;
+0F7B:FF;
+0F7C:00;
+0F7D:00;
+0F7E:00;
+0F7F:00;
+0F80:0F;
+0F81:0F;
+0F82:0F;
+0F83:0F;
+0F84:0F;
+0F85:0F;
+0F86:00;
+0F87:00;
+0F88:00;
+0F89:00;
+0F8A:00;
+0F8B:00;
+0F8C:00;
+0F8D:00;
+0F8E:00;
+0F8F:00;
+0F90:0F;
+0F91:0F;
+0F92:0F;
+0F93:0F;
+0F94:0F;
+0F95:0F;
+0F96:F0;
+0F97:F0;
+0F98:F0;
+0F99:F0;
+0F9A:F0;
+0F9B:F0;
+0F9C:00;
+0F9D:00;
+0F9E:00;
+0F9F:00;
+0FA0:0F;
+0FA1:0F;
+0FA2:0F;
+0FA3:0F;
+0FA4:0F;
+0FA5:0F;
+0FA6:0F;
+0FA7:0F;
+0FA8:0F;
+0FA9:0F;
+0FAA:0F;
+0FAB:0F;
+0FAC:00;
+0FAD:00;
+0FAE:00;
+0FAF:00;
+0FB0:0F;
+0FB1:0F;
+0FB2:0F;
+0FB3:0F;
+0FB4:0F;
+0FB5:0F;
+0FB6:FF;
+0FB7:FF;
+0FB8:FF;
+0FB9:FF;
+0FBA:FF;
+0FBB:FF;
+0FBC:00;
+0FBD:00;
+0FBE:00;
+0FBF:00;
+0FC0:FF;
+0FC1:FF;
+0FC2:FF;
+0FC3:FF;
+0FC4:FF;
+0FC5:FF;
+0FC6:00;
+0FC7:00;
+0FC8:00;
+0FC9:00;
+0FCA:00;
+0FCB:00;
+0FCC:00;
+0FCD:00;
+0FCE:00;
+0FCF:00;
+0FD0:FF;
+0FD1:FF;
+0FD2:FF;
+0FD3:FF;
+0FD4:FF;
+0FD5:FF;
+0FD6:F0;
+0FD7:F0;
+0FD8:F0;
+0FD9:F0;
+0FDA:F0;
+0FDB:F0;
+0FDC:00;
+0FDD:00;
+0FDE:00;
+0FDF:00;
+0FE0:FF;
+0FE1:FF;
+0FE2:FF;
+0FE3:FF;
+0FE4:FF;
+0FE5:FF;
+0FE6:0F;
+0FE7:0F;
+0FE8:0F;
+0FE9:0F;
+0FEA:0F;
+0FEB:0F;
+0FEC:00;
+0FED:00;
+0FEE:00;
+0FEF:00;
+0FF0:FF;
+0FF1:FF;
+0FF2:FF;
+0FF3:FF;
+0FF4:FF;
+0FF5:FF;
+0FF6:FF;
+0FF7:FF;
+0FF8:FF;
+0FF9:FF;
+0FFA:FF;
+0FFB:FF;
+0FFC:00;
+0FFD:00;
+0FFE:00;
+0FFF:00;
+END;
diff --git a/Computer_MiST/Laser310_MiST/rtl/roms/dosrom.mif b/Computer_MiST/Laser310_MiST/rtl/roms/dosrom.mif
new file mode 100644
index 00000000..dc81212c
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/roms/dosrom.mif
@@ -0,0 +1,8199 @@
+DEPTH = 8192;
+WIDTH = 8;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+0000:AA;
+0001:55;
+0002:E7;
+0003:18;
+0004:F3;
+0005:C3;
+0006:47;
+0007:40;
+0008:C3;
+0009:41;
+000A:5F;
+000B:C3;
+000C:52;
+000D:5F;
+000E:C3;
+000F:41;
+0010:42;
+0011:C3;
+0012:17;
+0013:47;
+0014:C3;
+0015:49;
+0016:47;
+0017:C3;
+0018:54;
+0019:47;
+001A:C3;
+001B:08;
+001C:4B;
+001D:C3;
+001E:67;
+001F:53;
+0020:C3;
+0021:B9;
+0022:53;
+0023:C3;
+0024:EA;
+0025:53;
+0026:C3;
+0027:7B;
+0028:58;
+0029:C3;
+002A:BF;
+002B:58;
+002C:C3;
+002D:13;
+002E:59;
+002F:C3;
+0030:68;
+0031:59;
+0032:C3;
+0033:A1;
+0034:59;
+0035:C3;
+0036:27;
+0037:5B;
+0038:C3;
+0039:BE;
+003A:5E;
+003B:C3;
+003C:CE;
+003D:5E;
+003E:C3;
+003F:01;
+0040:5F;
+0041:C3;
+0042:B1;
+0043:43;
+0044:C3;
+0045:6E;
+0046:44;
+0047:3E;
+0048:61;
+0049:D3;
+004A:10;
+004B:2A;
+004C:B1;
+004D:78;
+004E:E5;
+004F:11;
+0050:CA;
+0051:FE;
+0052:19;
+0053:E5;
+0054:FD;
+0055:E1;
+0056:E1;
+0057:11;
+0058:00;
+0059:80;
+005A:B7;
+005B:ED;
+005C:52;
+005D:D2;
+005E:6A;
+005F:40;
+0060:21;
+0061:44;
+0062:41;
+0063:FB;
+0064:CD;
+0065:A7;
+0066:28;
+0067:C3;
+0068:19;
+0069:1A;
+006A:19;
+006B:11;
+006C:37;
+006D:01;
+006E:ED;
+006F:52;
+0070:22;
+0071:B1;
+0072:78;
+0073:22;
+0074:D6;
+0075:78;
+0076:11;
+0077:32;
+0078:00;
+0079:B7;
+007A:ED;
+007B:52;
+007C:22;
+007D:A0;
+007E:78;
+007F:2B;
+0080:2B;
+0081:22;
+0082:E8;
+0083:78;
+0084:23;
+0085:23;
+0086:F9;
+0087:FD;
+0088:36;
+0089:14;
+008A:00;
+008B:FD;
+008C:36;
+008D:12;
+008E:00;
+008F:FD;
+0090:36;
+0091:11;
+0092:00;
+0093:FD;
+0094:36;
+0095:13;
+0096:0A;
+0097:FD;
+0098:36;
+0099:16;
+009A:00;
+009B:FD;
+009C:36;
+009D:15;
+009E:00;
+009F:FD;
+00A0:36;
+00A1:17;
+00A2:00;
+00A3:FD;
+00A4:36;
+00A5:24;
+00A6:00;
+00A7:FD;
+00A8:36;
+00A9:39;
+00AA:00;
+00AB:FD;
+00AC:36;
+00AD:0B;
+00AE:10;
+00AF:FD;
+00B0:36;
+00B1:33;
+00B2:61;
+00B3:FD;
+00B4:36;
+00B5:38;
+00B6:11;
+00B7:FD;
+00B8:E5;
+00B9:E1;
+00BA:11;
+00BB:4D;
+00BC:00;
+00BD:19;
+00BE:FD;
+00BF:75;
+00C0:31;
+00C1:FD;
+00C2:74;
+00C3:32;
+00C4:11;
+00C5:F6;
+00C6:FF;
+00C7:19;
+00C8:EB;
+00C9:21;
+00CA:5D;
+00CB:4D;
+00CC:01;
+00CD:0A;
+00CE:00;
+00CF:ED;
+00D0:B0;
+00D1:FD;
+00D2:E5;
+00D3:E1;
+00D4:11;
+00D5:E7;
+00D6:00;
+00D7:19;
+00D8:FD;
+00D9:75;
+00DA:34;
+00DB:FD;
+00DC:74;
+00DD:35;
+00DE:CD;
+00DF:41;
+00E0:5F;
+00E1:06;
+00E2:28;
+00E3:CD;
+00E4:01;
+00E5:5F;
+00E6:CD;
+00E7:52;
+00E8:5F;
+00E9:21;
+00EA:93;
+00EB:42;
+00EC:22;
+00ED:04;
+00EE:78;
+00EF:21;
+00F0:13;
+00F1:41;
+00F2:FB;
+00F3:CD;
+00F4:A7;
+00F5:28;
+00F6:21;
+00F7:00;
+00F8:60;
+00F9:3E;
+00FA:AA;
+00FB:BE;
+00FC:23;
+00FD:20;
+00FE:10;
+00FF:3E;
+0100:55;
+0101:BE;
+0102:23;
+0103:20;
+0104:0A;
+0105:3E;
+0106:E7;
+0107:BE;
+0108:23;
+0109:20;
+010A:04;
+010B:3E;
+010C:18;
+010D:BE;
+010E:23;
+010F:C2;
+0110:19;
+0111:1A;
+0112:E9;
+0113:1B;
+0114:1B;
+0115:44;
+0116:4F;
+0117:53;
+0118:20;
+0119:42;
+011A:41;
+011B:53;
+011C:49;
+011D:43;
+011E:20;
+011F:56;
+0120:31;
+0121:2E;
+0122:32;
+0123:0D;
+0124:0D;
+0125:00;
+0126:62;
+0127:41;
+0128:77;
+0129:41;
+012A:87;
+012B:41;
+012C:9D;
+012D:41;
+012E:AC;
+012F:41;
+0130:BC;
+0131:41;
+0132:C7;
+0133:41;
+0134:AC;
+0135:41;
+0136:AC;
+0137:41;
+0138:DA;
+0139:41;
+013A:EE;
+013B:41;
+013C:02;
+013D:42;
+013E:12;
+013F:42;
+0140:24;
+0141:42;
+0142:32;
+0143:42;
+0144:3F;
+0145:49;
+0146:4E;
+0147:53;
+0148:55;
+0149:46;
+014A:46;
+014B:49;
+014C:43;
+014D:49;
+014E:45;
+014F:4E;
+0150:54;
+0151:20;
+0152:4D;
+0153:45;
+0154:4D;
+0155:4F;
+0156:52;
+0157:59;
+0158:20;
+0159:46;
+015A:4F;
+015B:52;
+015C:20;
+015D:44;
+015E:4F;
+015F:53;
+0160:0D;
+0161:00;
+0162:3F;
+0163:46;
+0164:49;
+0165:4C;
+0166:45;
+0167:20;
+0168:41;
+0169:4C;
+016A:52;
+016B:45;
+016C:41;
+016D:44;
+016E:59;
+016F:20;
+0170:45;
+0171:58;
+0172:49;
+0173:53;
+0174:54;
+0175:53;
+0176:00;
+0177:3F;
+0178:44;
+0179:49;
+017A:52;
+017B:45;
+017C:43;
+017D:54;
+017E:4F;
+017F:52;
+0180:59;
+0181:20;
+0182:46;
+0183:55;
+0184:4C;
+0185:4C;
+0186:00;
+0187:3F;
+0188:44;
+0189:49;
+018A:53;
+018B:4B;
+018C:20;
+018D:57;
+018E:52;
+018F:49;
+0190:54;
+0191:45;
+0192:20;
+0193:50;
+0194:52;
+0195:4F;
+0196:54;
+0197:45;
+0198:43;
+0199:54;
+019A:45;
+019B:44;
+019C:00;
+019D:3F;
+019E:46;
+019F:49;
+01A0:4C;
+01A1:45;
+01A2:20;
+01A3:4E;
+01A4:4F;
+01A5:54;
+01A6:20;
+01A7:4F;
+01A8:50;
+01A9:45;
+01AA:4E;
+01AB:00;
+01AC:3F;
+01AD:44;
+01AE:49;
+01AF:53;
+01B0:4B;
+01B1:20;
+01B2:49;
+01B3:2F;
+01B4:4F;
+01B5:20;
+01B6:45;
+01B7:52;
+01B8:52;
+01B9:4F;
+01BA:52;
+01BB:00;
+01BC:3F;
+01BD:44;
+01BE:49;
+01BF:53;
+01C0:4B;
+01C1:20;
+01C2:46;
+01C3:55;
+01C4:4C;
+01C5:4C;
+01C6:00;
+01C7:3F;
+01C8:46;
+01C9:49;
+01CA:4C;
+01CB:45;
+01CC:20;
+01CD:41;
+01CE:4C;
+01CF:52;
+01D0:45;
+01D1:41;
+01D2:44;
+01D3:59;
+01D4:20;
+01D5:4F;
+01D6:50;
+01D7:45;
+01D8:4E;
+01D9:00;
+01DA:3F;
+01DB:55;
+01DC:4E;
+01DD:53;
+01DE:55;
+01DF:50;
+01E0:50;
+01E1:4F;
+01E2:52;
+01E3:54;
+01E4:45;
+01E5:44;
+01E6:20;
+01E7:44;
+01E8:45;
+01E9:56;
+01EA:49;
+01EB:43;
+01EC:45;
+01ED:00;
+01EE:3F;
+01EF:46;
+01F0:49;
+01F1:4C;
+01F2:45;
+01F3:20;
+01F4:54;
+01F5:59;
+01F6:50;
+01F7:45;
+01F8:20;
+01F9:4D;
+01FA:49;
+01FB:53;
+01FC:4D;
+01FD:41;
+01FE:54;
+01FF:43;
+0200:48;
+0201:00;
+0202:3F;
+0203:46;
+0204:49;
+0205:4C;
+0206:45;
+0207:20;
+0208:4E;
+0209:4F;
+020A:54;
+020B:20;
+020C:46;
+020D:4F;
+020E:55;
+020F:4E;
+0210:44;
+0211:00;
+0212:3F;
+0213:44;
+0214:49;
+0215:53;
+0216:4B;
+0217:20;
+0218:42;
+0219:55;
+021A:46;
+021B:46;
+021C:45;
+021D:52;
+021E:20;
+021F:46;
+0220:55;
+0221:4C;
+0222:4C;
+0223:00;
+0224:3F;
+0225:49;
+0226:4C;
+0227:4C;
+0228:45;
+0229:47;
+022A:41;
+022B:4C;
+022C:20;
+022D:52;
+022E:45;
+022F:41;
+0230:44;
+0231:00;
+0232:3F;
+0233:49;
+0234:4C;
+0235:4C;
+0236:45;
+0237:47;
+0238:41;
+0239:4C;
+023A:20;
+023B:57;
+023C:52;
+023D:49;
+023E:54;
+023F:45;
+0240:00;
+0241:F5;
+0242:FD;
+0243:7E;
+0244:39;
+0245:B7;
+0246:C4;
+0247:44;
+0248:51;
+0249:F1;
+024A:B7;
+024B:28;
+024C:34;
+024D:FE;
+024E:01;
+024F:CA;
+0250:97;
+0251:19;
+0252:FE;
+0253:11;
+0254:CA;
+0255:8A;
+0256:42;
+0257:F5;
+0258:CD;
+0259:F9;
+025A:20;
+025B:F1;
+025C:21;
+025D:22;
+025E:41;
+025F:CB;
+0260:27;
+0261:85;
+0262:6F;
+0263:3E;
+0264:00;
+0265:8C;
+0266:67;
+0267:5E;
+0268:23;
+0269:56;
+026A:EB;
+026B:CD;
+026C:52;
+026D:5F;
+026E:CD;
+026F:A7;
+0270:28;
+0271:2A;
+0272:A2;
+0273:78;
+0274:22;
+0275:EA;
+0276:78;
+0277:22;
+0278:EC;
+0279:78;
+027A:23;
+027B:7D;
+027C:B4;
+027D:2B;
+027E:C4;
+027F:A7;
+0280:0F;
+0281:01;
+0282:19;
+0283:1A;
+0284:2A;
+0285:E8;
+0286:78;
+0287:C3;
+0288:9A;
+0289:1B;
+028A:CD;
+028B:52;
+028C:5F;
+028D:3E;
+028E:01;
+028F:FB;
+0290:C3;
+0291:A0;
+0292:1D;
+0293:D9;
+0294:21;
+0295:5B;
+0296:1D;
+0297:D1;
+0298:B7;
+0299:ED;
+029A:52;
+029B:D5;
+029C:D9;
+029D:C2;
+029E:78;
+029F:1D;
+02A0:E5;
+02A1:CD;
+02A2:78;
+02A3:1D;
+02A4:20;
+02A5:02;
+02A6:D1;
+02A7:C9;
+02A8:B7;
+02A9:F2;
+02AA:EF;
+02AB:42;
+02AC:FE;
+02AD:8E;
+02AE:20;
+02AF:F6;
+02B0:23;
+02B1:7E;
+02B2:B7;
+02B3:28;
+02B4:10;
+02B5:FE;
+02B6:20;
+02B7:28;
+02B8:F7;
+02B9:FE;
+02BA:22;
+02BB:20;
+02BC:08;
+02BD:D1;
+02BE:01;
+02BF:DB;
+02C0:45;
+02C1:2B;
+02C2:EB;
+02C3:18;
+02C4:61;
+02C5:E1;
+02C6:C3;
+02C7:78;
+02C8:1D;
+02C9:E1;
+02CA:E5;
+02CB:23;
+02CC:7E;
+02CD:FE;
+02CE:42;
+02CF:20;
+02D0:0B;
+02D1:23;
+02D2:7E;
+02D3:FE;
+02D4:8E;
+02D5:20;
+02D6:14;
+02D7:06;
+02D8:06;
+02D9:C5;
+02DA:18;
+02DB:39;
+02DC:FE;
+02DD:44;
+02DE:20;
+02DF:0B;
+02E0:23;
+02E1:7E;
+02E2:FE;
+02E3:96;
+02E4:20;
+02E5:05;
+02E6:06;
+02E7:0E;
+02E8:C5;
+02E9:18;
+02EA:2A;
+02EB:E1;
+02EC:C3;
+02ED:78;
+02EE:1D;
+02EF:11;
+02F0:2D;
+02F1:43;
+02F2:06;
+02F3:FF;
+02F4:4E;
+02F5:EB;
+02F6:23;
+02F7:B6;
+02F8:F2;
+02F9:F6;
+02FA:42;
+02FB:04;
+02FC:7E;
+02FD:E6;
+02FE:7F;
+02FF:28;
+0300:C8;
+0301:B9;
+0302:20;
+0303:F2;
+0304:EB;
+0305:E5;
+0306:13;
+0307:1A;
+0308:B7;
+0309:FA;
+030A:15;
+030B:43;
+030C:4F;
+030D:23;
+030E:7E;
+030F:B9;
+0310:28;
+0311:F4;
+0312:E1;
+0313:18;
+0314:DF;
+0315:78;
+0316:C1;
+0317:C1;
+0318:C1;
+0319:CB;
+031A:27;
+031B:4F;
+031C:06;
+031D:00;
+031E:EB;
+031F:21;
+0320:71;
+0321:43;
+0322:09;
+0323:4E;
+0324:23;
+0325:46;
+0326:21;
+0327:1E;
+0328:1D;
+0329:E5;
+032A:EB;
+032B:23;
+032C:C5;
+032D:C9;
+032E:CC;
+032F:4F;
+0330:41;
+0331:44;
+0332:D3;
+0333:41;
+0334:56;
+0335:45;
+0336:CF;
+0337:50;
+0338:45;
+0339:4E;
+033A:C3;
+033B:4C;
+033C:4F;
+033D:53;
+033E:45;
+033F:C2;
+0340:53;
+0341:41;
+0342:56;
+0343:45;
+0344:C2;
+0345:4C;
+0346:4F;
+0347:41;
+0348:44;
+0349:C2;
+034A:52;
+034B:55;
+034C:4E;
+034D:C4;
+034E:49;
+034F:52;
+0350:C5;
+0351:52;
+0352:41;
+0353:D2;
+0354:45;
+0355:4E;
+0356:C9;
+0357:4E;
+0358:49;
+0359:54;
+035A:C4;
+035B:52;
+035C:49;
+035D:56;
+035E:45;
+035F:C9;
+0360:4E;
+0361:23;
+0362:D0;
+0363:52;
+0364:23;
+0365:C4;
+0366:43;
+0367:4F;
+0368:50;
+0369:59;
+036A:D3;
+036B:54;
+036C:41;
+036D:54;
+036E:55;
+036F:53;
+0370:80;
+0371:91;
+0372:43;
+0373:4E;
+0374:44;
+0375:F5;
+0376:45;
+0377:DD;
+0378:47;
+0379:39;
+037A:48;
+037B:C4;
+037C:48;
+037D:EF;
+037E:48;
+037F:06;
+0380:49;
+0381:94;
+0382:49;
+0383:80;
+0384:4A;
+0385:08;
+0386:4B;
+0387:78;
+0388:4D;
+0389:92;
+038A:4D;
+038B:64;
+038C:4E;
+038D:FB;
+038E:4F;
+038F:D5;
+0390:52;
+0391:CD;
+0392:67;
+0393:53;
+0394:E5;
+0395:B7;
+0396:C2;
+0397:41;
+0398:42;
+0399:FD;
+039A:36;
+039B:09;
+039C:54;
+039D:CD;
+039E:B1;
+039F:43;
+03A0:B7;
+03A1:C2;
+03A2:41;
+03A3:42;
+03A4:21;
+03A5:29;
+03A6:19;
+03A7:CD;
+03A8:A7;
+03A9:28;
+03AA:2A;
+03AB:A4;
+03AC:78;
+03AD:E5;
+03AE:C3;
+03AF:E8;
+03B0:1A;
+03B1:F3;
+03B2:CD;
+03B3:41;
+03B4:5F;
+03B5:C5;
+03B6:01;
+03B7:32;
+03B8:00;
+03B9:CD;
+03BA:BE;
+03BB:5E;
+03BC:C1;
+03BD:CD;
+03BE:13;
+03BF:59;
+03C0:FE;
+03C1:02;
+03C2:CA;
+03C3:CA;
+03C4:43;
+03C5:B7;
+03C6:C0;
+03C7:3E;
+03C8:0D;
+03C9:C9;
+03CA:FD;
+03CB:7E;
+03CC:09;
+03CD:FD;
+03CE:BE;
+03CF:0A;
+03D0:3E;
+03D1:0C;
+03D2:C0;
+03D3:1A;
+03D4:13;
+03D5:FD;
+03D6:77;
+03D7:12;
+03D8:1A;
+03D9:13;
+03DA:FD;
+03DB:77;
+03DC:11;
+03DD:EB;
+03DE:5E;
+03DF:23;
+03E0:56;
+03E1:23;
+03E2:ED;
+03E3:53;
+03E4:A4;
+03E5:78;
+03E6:FD;
+03E7:73;
+03E8:0E;
+03E9:FD;
+03EA:72;
+03EB:0F;
+03EC:5E;
+03ED:23;
+03EE:56;
+03EF:ED;
+03F0:53;
+03F1:F9;
+03F2:78;
+03F3:CD;
+03F4:27;
+03F5:5B;
+03F6:B7;
+03F7:C2;
+03F8:41;
+03F9:44;
+03FA:FD;
+03FB:6E;
+03FC:31;
+03FD:FD;
+03FE:66;
+03FF:32;
+0400:E5;
+0401:11;
+0402:7E;
+0403:00;
+0404:19;
+0405:7E;
+0406:23;
+0407:FD;
+0408:77;
+0409:12;
+040A:7E;
+040B:FD;
+040C:77;
+040D:11;
+040E:E1;
+040F:FD;
+0410:5E;
+0411:0E;
+0412:FD;
+0413:56;
+0414:0F;
+0415:01;
+0416:7E;
+0417:00;
+0418:FD;
+0419:7E;
+041A:12;
+041B:FD;
+041C:B6;
+041D:11;
+041E:28;
+041F:10;
+0420:ED;
+0421:B0;
+0422:FD;
+0423:73;
+0424:0E;
+0425:FD;
+0426:72;
+0427:0F;
+0428:FD;
+0429:7E;
+042A:12;
+042B:FD;
+042C:B6;
+042D:11;
+042E:18;
+042F:C3;
+0430:E5;
+0431:2A;
+0432:F9;
+0433:78;
+0434:B7;
+0435:ED;
+0436:52;
+0437:4D;
+0438:44;
+0439:E1;
+043A:ED;
+043B:B0;
+043C:CD;
+043D:52;
+043E:5F;
+043F:AF;
+0440:C9;
+0441:2A;
+0442:A4;
+0443:78;
+0444:36;
+0445:00;
+0446:23;
+0447:36;
+0448:00;
+0449:23;
+044A:22;
+044B:F9;
+044C:78;
+044D:C9;
+044E:CD;
+044F:67;
+0450:53;
+0451:E5;
+0452:B7;
+0453:C2;
+0454:41;
+0455:42;
+0456:CD;
+0457:41;
+0458:5F;
+0459:C5;
+045A:01;
+045B:02;
+045C:00;
+045D:CD;
+045E:BE;
+045F:5E;
+0460:C1;
+0461:DB;
+0462:13;
+0463:B7;
+0464:3E;
+0465:04;
+0466:FA;
+0467:41;
+0468:42;
+0469:FD;
+046A:36;
+046B:09;
+046C:54;
+046D:E1;
+046E:ED;
+046F:5B;
+0470:F9;
+0471:78;
+0472:D5;
+0473:ED;
+0474:5B;
+0475:A4;
+0476:78;
+0477:D5;
+0478:E5;
+0479:F3;
+047A:C5;
+047B:01;
+047C:32;
+047D:00;
+047E:CD;
+047F:BE;
+0480:5E;
+0481:C1;
+0482:ED;
+0483:5B;
+0484:A4;
+0485:78;
+0486:FD;
+0487:73;
+0488:0E;
+0489:FD;
+048A:72;
+048B:0F;
+048C:FD;
+048D:36;
+048E:12;
+048F:00;
+0490:FD;
+0491:36;
+0492:11;
+0493:0F;
+0494:CD;
+0495:27;
+0496:5B;
+0497:B7;
+0498:C2;
+0499:9A;
+049A:48;
+049B:FD;
+049C:5E;
+049D:34;
+049E:FD;
+049F:56;
+04A0:35;
+04A1:FD;
+04A2:6E;
+04A3:31;
+04A4:FD;
+04A5:66;
+04A6:32;
+04A7:01;
+04A8:50;
+04A9:00;
+04AA:ED;
+04AB:B0;
+04AC:CD;
+04AD:7B;
+04AE:58;
+04AF:B7;
+04B0:C2;
+04B1:9A;
+04B2:48;
+04B3:FD;
+04B4:7E;
+04B5:16;
+04B6:FD;
+04B7:B6;
+04B8:15;
+04B9:CA;
+04BA:7C;
+04BB:45;
+04BC:FD;
+04BD:56;
+04BE:16;
+04BF:FD;
+04C0:5E;
+04C1:15;
+04C2:CD;
+04C3:BF;
+04C4:58;
+04C5:FE;
+04C6:07;
+04C7:20;
+04C8:19;
+04C9:CD;
+04CA:13;
+04CB:59;
+04CC:FE;
+04CD:02;
+04CE:3E;
+04CF:06;
+04D0:C2;
+04D1:9A;
+04D2:48;
+04D3:EB;
+04D4:11;
+04D5:F6;
+04D6:FF;
+04D7:19;
+04D8:36;
+04D9:01;
+04DA:CD;
+04DB:A1;
+04DC:59;
+04DD:3E;
+04DE:07;
+04DF:C3;
+04E0:9A;
+04E1:48;
+04E2:B7;
+04E3:C2;
+04E4:9A;
+04E5:48;
+04E6:FD;
+04E7:72;
+04E8:12;
+04E9:FD;
+04EA:73;
+04EB:11;
+04EC:FD;
+04ED:6E;
+04EE:31;
+04EF:FD;
+04F0:66;
+04F1:32;
+04F2:E5;
+04F3:5D;
+04F4:54;
+04F5:13;
+04F6:36;
+04F7:00;
+04F8:01;
+04F9:80;
+04FA:00;
+04FB:ED;
+04FC:B0;
+04FD:FD;
+04FE:6E;
+04FF:0E;
+0500:FD;
+0501:66;
+0502:0F;
+0503:E5;
+0504:ED;
+0505:5B;
+0506:F9;
+0507:78;
+0508:B7;
+0509:ED;
+050A:52;
+050B:D2;
+050C:3A;
+050D:45;
+050E:11;
+050F:7E;
+0510:00;
+0511:19;
+0512:DA;
+0513:76;
+0514:45;
+0515:ED;
+0516:5B;
+0517:F9;
+0518:78;
+0519:19;
+051A:FD;
+051B:75;
+051C:0E;
+051D:FD;
+051E:74;
+051F:0F;
+0520:E1;
+0521:D1;
+0522:01;
+0523:7E;
+0524:00;
+0525:ED;
+0526:B0;
+0527:FD;
+0528:7E;
+0529:16;
+052A:12;
+052B:13;
+052C:FD;
+052D:7E;
+052E:15;
+052F:12;
+0530:CD;
+0531:A1;
+0532:59;
+0533:B7;
+0534:C2;
+0535:9A;
+0536:48;
+0537:C3;
+0538:B3;
+0539:44;
+053A:E5;
+053B:FD;
+053C:6E;
+053D:34;
+053E:FD;
+053F:66;
+0540:35;
+0541:FD;
+0542:7E;
+0543:16;
+0544:3D;
+0545:CB;
+0546:27;
+0547:5F;
+0548:16;
+0549:00;
+054A:FD;
+054B:7E;
+054C:15;
+054D:FE;
+054E:08;
+054F:3F;
+0550:ED;
+0551:5A;
+0552:E6;
+0553:07;
+0554:3C;
+0555:47;
+0556:4E;
+0557:CB;
+0558:01;
+0559:CB;
+055A:09;
+055B:10;
+055C:FC;
+055D:CB;
+055E:81;
+055F:47;
+0560:CB;
+0561:09;
+0562:CB;
+0563:01;
+0564:10;
+0565:FC;
+0566:71;
+0567:C1;
+0568:E1;
+0569:D1;
+056A:ED;
+056B:B0;
+056C:FD;
+056D:36;
+056E:16;
+056F:00;
+0570:FD;
+0571:36;
+0572:15;
+0573:00;
+0574:18;
+0575:BA;
+0576:EB;
+0577:B7;
+0578:ED;
+0579:52;
+057A:18;
+057B:BE;
+057C:CD;
+057D:13;
+057E:59;
+057F:FE;
+0580:02;
+0581:C2;
+0582:9A;
+0583:48;
+0584:13;
+0585:13;
+0586:2A;
+0587:A4;
+0588:78;
+0589:EB;
+058A:73;
+058B:23;
+058C:72;
+058D:23;
+058E:EB;
+058F:2A;
+0590:F9;
+0591:78;
+0592:EB;
+0593:73;
+0594:23;
+0595:72;
+0596:CD;
+0597:A1;
+0598:59;
+0599:B7;
+059A:C2;
+059B:9A;
+059C:48;
+059D:FD;
+059E:6E;
+059F:31;
+05A0:FD;
+05A1:66;
+05A2:32;
+05A3:E5;
+05A4:5D;
+05A5:54;
+05A6:13;
+05A7:36;
+05A8:00;
+05A9:01;
+05AA:80;
+05AB:00;
+05AC:ED;
+05AD:B0;
+05AE:E1;
+05AF:FD;
+05B0:5E;
+05B1:34;
+05B2:FD;
+05B3:56;
+05B4:35;
+05B5:EB;
+05B6:01;
+05B7:50;
+05B8:00;
+05B9:ED;
+05BA:B0;
+05BB:FD;
+05BC:36;
+05BD:12;
+05BE:00;
+05BF:FD;
+05C0:36;
+05C1:11;
+05C2:0F;
+05C3:CD;
+05C4:A1;
+05C5:59;
+05C6:F5;
+05C7:CD;
+05C8:52;
+05C9:5F;
+05CA:F1;
+05CB:E1;
+05CC:D1;
+05CD:ED;
+05CE:53;
+05CF:A4;
+05D0:78;
+05D1:D1;
+05D2:ED;
+05D3:53;
+05D4:F9;
+05D5:78;
+05D6:B7;
+05D7:C2;
+05D8:41;
+05D9:42;
+05DA:C9;
+05DB:CD;
+05DC:67;
+05DD:53;
+05DE:E5;
+05DF:B7;
+05E0:C2;
+05E1:41;
+05E2:42;
+05E3:FD;
+05E4:36;
+05E5:09;
+05E6:54;
+05E7:CD;
+05E8:B1;
+05E9:43;
+05EA:B7;
+05EB:C2;
+05EC:41;
+05ED:42;
+05EE:ED;
+05EF:5B;
+05F0:A4;
+05F1:78;
+05F2:C3;
+05F3:E9;
+05F4:36;
+05F5:CD;
+05F6:28;
+05F7:28;
+05F8:CD;
+05F9:78;
+05FA:53;
+05FB:E5;
+05FC:B7;
+05FD:C2;
+05FE:41;
+05FF:42;
+0600:F1;
+0601:CF;
+0602:2C;
+0603:CD;
+0604:1C;
+0605:2B;
+0606:B7;
+0607:28;
+0608:05;
+0609:FE;
+060A:02;
+060B:D2;
+060C:4A;
+060D:1E;
+060E:FD;
+060F:77;
+0610:0C;
+0611:E5;
+0612:CD;
+0613:78;
+0614:47;
+0615:FE;
+0616:05;
+0617:C2;
+0618:41;
+0619:42;
+061A:E5;
+061B:CD;
+061C:A5;
+061D:4F;
+061E:E1;
+061F:36;
+0620:01;
+0621:23;
+0622:FD;
+0623:7E;
+0624:0C;
+0625:77;
+0626:23;
+0627:FD;
+0628:E5;
+0629:D1;
+062A:13;
+062B:EB;
+062C:01;
+062D:08;
+062E:00;
+062F:ED;
+0630:B0;
+0631:D5;
+0632:F3;
+0633:CD;
+0634:41;
+0635:5F;
+0636:C5;
+0637:01;
+0638:32;
+0639:00;
+063A:CD;
+063B:BE;
+063C:5E;
+063D:C1;
+063E:CD;
+063F:13;
+0640:59;
+0641:FE;
+0642:02;
+0643:C2;
+0644:6B;
+0645:46;
+0646:FD;
+0647:7E;
+0648:0A;
+0649:FE;
+064A:44;
+064B:3E;
+064C:0C;
+064D:C2;
+064E:41;
+064F:42;
+0650:E1;
+0651:1A;
+0652:77;
+0653:FD;
+0654:77;
+0655:12;
+0656:13;
+0657:23;
+0658:1A;
+0659:77;
+065A:FD;
+065B:77;
+065C:11;
+065D:AF;
+065E:23;
+065F:77;
+0660:FD;
+0661:7E;
+0662:0C;
+0663:B7;
+0664:20;
+0665:53;
+0666:CD;
+0667:52;
+0668:5F;
+0669:E1;
+066A:C9;
+066B:4F;
+066C:FD;
+066D:7E;
+066E:0C;
+066F:B7;
+0670:79;
+0671:CA;
+0672:A8;
+0673:46;
+0674:DB;
+0675:13;
+0676:B7;
+0677:0E;
+0678:04;
+0679:FA;
+067A:A8;
+067B:46;
+067C:CD;
+067D:17;
+067E:47;
+067F:FD;
+0680:36;
+0681:09;
+0682:44;
+0683:CD;
+0684:7B;
+0685:58;
+0686:B7;
+0687:C2;
+0688:41;
+0689:42;
+068A:E1;
+068B:FD;
+068C:7E;
+068D:16;
+068E:FD;
+068F:77;
+0690:12;
+0691:77;
+0692:23;
+0693:FD;
+0694:7E;
+0695:15;
+0696:FD;
+0697:77;
+0698:11;
+0699:77;
+069A:23;
+069B:36;
+069C:00;
+069D:CD;
+069E:49;
+069F:47;
+06A0:CD;
+06A1:54;
+06A2:47;
+06A3:CD;
+06A4:52;
+06A5:5F;
+06A6:E1;
+06A7:C9;
+06A8:E1;
+06A9:11;
+06AA:F6;
+06AB:FF;
+06AC:19;
+06AD:36;
+06AE:00;
+06AF:79;
+06B0:B7;
+06B1:C2;
+06B2:41;
+06B3:42;
+06B4:3E;
+06B5:0D;
+06B6:C3;
+06B7:41;
+06B8:42;
+06B9:E5;
+06BA:CD;
+06BB:27;
+06BC:5B;
+06BD:B7;
+06BE:C2;
+06BF:41;
+06C0:42;
+06C1:FD;
+06C2:6E;
+06C3:31;
+06C4:FD;
+06C5:66;
+06C6:32;
+06C7:11;
+06C8:7E;
+06C9:00;
+06CA:19;
+06CB:7E;
+06CC:B7;
+06CD:28;
+06CE:0A;
+06CF:23;
+06D0:FD;
+06D1:77;
+06D2:12;
+06D3:7E;
+06D4:FD;
+06D5:77;
+06D6:11;
+06D7:18;
+06D8:E1;
+06D9:06;
+06DA:7E;
+06DB:FD;
+06DC:6E;
+06DD:31;
+06DE:FD;
+06DF:66;
+06E0:32;
+06E1:7E;
+06E2:23;
+06E3:B7;
+06E4:28;
+06E5:1D;
+06E6:10;
+06E7:F9;
+06E8:CD;
+06E9:17;
+06EA:47;
+06EB:CD;
+06EC:BF;
+06ED:58;
+06EE:B7;
+06EF:C2;
+06F0:41;
+06F1:42;
+06F2:FD;
+06F3:7E;
+06F4:16;
+06F5:FD;
+06F6:77;
+06F7:12;
+06F8:FD;
+06F9:7E;
+06FA:15;
+06FB:FD;
+06FC:77;
+06FD:11;
+06FE:CD;
+06FF:49;
+0700:47;
+0701:06;
+0702:7E;
+0703:3E;
+0704:7E;
+0705:90;
+0706:E1;
+0707:77;
+0708:2B;
+0709:FD;
+070A:7E;
+070B:11;
+070C:77;
+070D:2B;
+070E:FD;
+070F:7E;
+0710:12;
+0711:77;
+0712:CD;
+0713:52;
+0714:5F;
+0715:E1;
+0716:C9;
+0717:FD;
+0718:36;
+0719:12;
+071A:00;
+071B:FD;
+071C:36;
+071D:11;
+071E:0F;
+071F:CD;
+0720:27;
+0721:5B;
+0722:B7;
+0723:C2;
+0724:41;
+0725:42;
+0726:FD;
+0727:5E;
+0728:34;
+0729:FD;
+072A:56;
+072B:35;
+072C:FD;
+072D:6E;
+072E:31;
+072F:FD;
+0730:66;
+0731:32;
+0732:01;
+0733:50;
+0734:00;
+0735:ED;
+0736:B0;
+0737:C9;
+0738:FD;
+0739:6E;
+073A:31;
+073B:FD;
+073C:66;
+073D:32;
+073E:36;
+073F:00;
+0740:5D;
+0741:54;
+0742:13;
+0743:01;
+0744:80;
+0745:00;
+0746:ED;
+0747:B0;
+0748:C9;
+0749:CD;
+074A:38;
+074B:47;
+074C:CD;
+074D:A1;
+074E:59;
+074F:B7;
+0750:C2;
+0751:41;
+0752:42;
+0753:C9;
+0754:CD;
+0755:38;
+0756:47;
+0757:FD;
+0758:36;
+0759:12;
+075A:00;
+075B:FD;
+075C:36;
+075D:11;
+075E:0F;
+075F:FD;
+0760:5E;
+0761:31;
+0762:FD;
+0763:56;
+0764:32;
+0765:FD;
+0766:6E;
+0767:34;
+0768:FD;
+0769:66;
+076A:35;
+076B:01;
+076C:50;
+076D:00;
+076E:ED;
+076F:B0;
+0770:CD;
+0771:A1;
+0772:59;
+0773:B7;
+0774:C2;
+0775:41;
+0776:42;
+0777:C9;
+0778:FD;
+0779:E5;
+077A:E1;
+077B:FD;
+077C:36;
+077D:00;
+077E:00;
+077F:11;
+0780:17;
+0781:00;
+0782:19;
+0783:7E;
+0784:B7;
+0785:28;
+0786:09;
+0787:CD;
+0788:BF;
+0789:47;
+078A:FE;
+078B:08;
+078C:C8;
+078D:FD;
+078E:34;
+078F:00;
+0790:11;
+0791:0D;
+0792:00;
+0793:19;
+0794:7E;
+0795:B7;
+0796:20;
+0797:14;
+0798:FD;
+0799:E5;
+079A:E1;
+079B:11;
+079C:17;
+079D:00;
+079E:19;
+079F:FD;
+07A0:7E;
+07A1:00;
+07A2:B7;
+07A3:28;
+07A4:04;
+07A5:11;
+07A6:0D;
+07A7:00;
+07A8:19;
+07A9:3E;
+07AA:05;
+07AB:C9;
+07AC:CD;
+07AD:BF;
+07AE:47;
+07AF:FE;
+07B0:08;
+07B1:C8;
+07B2:B7;
+07B3:ED;
+07B4:52;
+07B5:FD;
+07B6:7E;
+07B7:17;
+07B8:B7;
+07B9:3E;
+07BA:0E;
+07BB:C0;
+07BC:3E;
+07BD:05;
+07BE:C9;
+07BF:FD;
+07C0:E5;
+07C1:E5;
+07C2:06;
+07C3:08;
+07C4:23;
+07C5:23;
+07C6:FD;
+07C7:7E;
+07C8:01;
+07C9:BE;
+07CA:23;
+07CB:FD;
+07CC:23;
+07CD:20;
+07CE:08;
+07CF:10;
+07D0:F5;
+07D1:3E;
+07D2:08;
+07D3:D1;
+07D4:FD;
+07D5:E1;
+07D6:C9;
+07D7:E1;
+07D8:FD;
+07D9:E1;
+07DA:3E;
+07DB:05;
+07DC:C9;
+07DD:CD;
+07DE:67;
+07DF:53;
+07E0:B7;
+07E1:C2;
+07E2:41;
+07E3:42;
+07E4:E5;
+07E5:2A;
+07E6:A2;
+07E7:78;
+07E8:23;
+07E9:7C;
+07EA:B5;
+07EB:20;
+07EC:0A;
+07ED:CD;
+07EE:78;
+07EF:47;
+07F0:E1;
+07F1:FE;
+07F2:08;
+07F3:C0;
+07F4:AF;
+07F5:12;
+07F6:C9;
+07F7:CD;
+07F8:78;
+07F9:47;
+07FA:E1;
+07FB:FE;
+07FC:08;
+07FD:C0;
+07FE:1A;
+07FF:FE;
+0800:02;
+0801:3E;
+0802:00;
+0803:12;
+0804:C0;
+0805:13;
+0806:1A;
+0807:B7;
+0808:C8;
+0809:E5;
+080A:EB;
+080B:11;
+080C:09;
+080D:00;
+080E:19;
+080F:7E;
+0810:23;
+0811:FD;
+0812:77;
+0813:12;
+0814:7E;
+0815:FD;
+0816:77;
+0817:11;
+0818:F3;
+0819:CD;
+081A:41;
+081B:5F;
+081C:C5;
+081D:01;
+081E:32;
+081F:00;
+0820:CD;
+0821:BE;
+0822:5E;
+0823:C1;
+0824:DB;
+0825:13;
+0826:B7;
+0827:3E;
+0828:04;
+0829:FA;
+082A:41;
+082B:42;
+082C:CD;
+082D:A1;
+082E:59;
+082F:B7;
+0830:C2;
+0831:41;
+0832:42;
+0833:FB;
+0834:CD;
+0835:52;
+0836:5F;
+0837:E1;
+0838:C9;
+0839:CD;
+083A:78;
+083B:53;
+083C:E5;
+083D:B7;
+083E:C2;
+083F:41;
+0840:42;
+0841:E1;
+0842:CF;
+0843:2C;
+0844:ED;
+0845:5B;
+0846:F9;
+0847:78;
+0848:D5;
+0849:ED;
+084A:5B;
+084B:A4;
+084C:78;
+084D:D5;
+084E:CD;
+084F:B9;
+0850:53;
+0851:3E;
+0852:01;
+0853:DA;
+0854:B7;
+0855:48;
+0856:ED;
+0857:53;
+0858:A4;
+0859:78;
+085A:CF;
+085B:2C;
+085C:CD;
+085D:B9;
+085E:53;
+085F:3E;
+0860:01;
+0861:DA;
+0862:B7;
+0863:48;
+0864:13;
+0865:ED;
+0866:53;
+0867:F9;
+0868:78;
+0869:7E;
+086A:B7;
+086B:28;
+086C:07;
+086D:FE;
+086E:3A;
+086F:3E;
+0870:01;
+0871:C2;
+0872:B7;
+0873:48;
+0874:FD;
+0875:36;
+0876:09;
+0877:42;
+0878:E5;
+0879:2A;
+087A:A4;
+087B:78;
+087C:B7;
+087D:ED;
+087E:52;
+087F:3E;
+0880:01;
+0881:D2;
+0882:9A;
+0883:48;
+0884:CD;
+0885:41;
+0886:5F;
+0887:C5;
+0888:01;
+0889:02;
+088A:00;
+088B:CD;
+088C:BE;
+088D:5E;
+088E:C1;
+088F:DB;
+0890:13;
+0891:B7;
+0892:3E;
+0893:04;
+0894:FA;
+0895:9A;
+0896:48;
+0897:C3;
+0898:79;
+0899:44;
+089A:FE;
+089B:11;
+089C:20;
+089D:18;
+089E:CD;
+089F:13;
+08A0:59;
+08A1:FE;
+08A2:02;
+08A3:3E;
+08A4:11;
+08A5:20;
+08A6:0F;
+08A7:EB;
+08A8:11;
+08A9:F6;
+08AA:FF;
+08AB:19;
+08AC:36;
+08AD:01;
+08AE:CD;
+08AF:A1;
+08B0:59;
+08B1:B7;
+08B2:20;
+08B3:02;
+08B4:3E;
+08B5:11;
+08B6:E1;
+08B7:D1;
+08B8:ED;
+08B9:53;
+08BA:A4;
+08BB:78;
+08BC:D1;
+08BD:ED;
+08BE:53;
+08BF:F9;
+08C0:78;
+08C1:C3;
+08C2:41;
+08C3:42;
+08C4:CD;
+08C5:67;
+08C6:53;
+08C7:E5;
+08C8:B7;
+08C9:C2;
+08CA:41;
+08CB:42;
+08CC:FD;
+08CD:36;
+08CE:09;
+08CF:42;
+08D0:E1;
+08D1:ED;
+08D2:5B;
+08D3:F9;
+08D4:78;
+08D5:D5;
+08D6:ED;
+08D7:5B;
+08D8:A4;
+08D9:78;
+08DA:D5;
+08DB:E5;
+08DC:CD;
+08DD:B1;
+08DE:43;
+08DF:E1;
+08E0:D1;
+08E1:ED;
+08E2:53;
+08E3:A4;
+08E4:78;
+08E5:D1;
+08E6:ED;
+08E7:53;
+08E8:F9;
+08E9:78;
+08EA:B7;
+08EB:C2;
+08EC:41;
+08ED:42;
+08EE:C9;
+08EF:CD;
+08F0:67;
+08F1:53;
+08F2:E5;
+08F3:B7;
+08F4:C2;
+08F5:41;
+08F6:42;
+08F7:FD;
+08F8:36;
+08F9:09;
+08FA:42;
+08FB:CD;
+08FC:B1;
+08FD:43;
+08FE:B7;
+08FF:C2;
+0900:41;
+0901:42;
+0902:2A;
+0903:A4;
+0904:78;
+0905:E9;
+0906:E5;
+0907:F3;
+0908:CD;
+0909:41;
+090A:5F;
+090B:C5;
+090C:01;
+090D:32;
+090E:00;
+090F:CD;
+0910:BE;
+0911:5E;
+0912:C1;
+0913:FD;
+0914:36;
+0915:12;
+0916:00;
+0917:FD;
+0918:36;
+0919:11;
+091A:00;
+091B:F3;
+091C:CD;
+091D:27;
+091E:5B;
+091F:B7;
+0920:C2;
+0921:41;
+0922:42;
+0923:FD;
+0924:6E;
+0925:31;
+0926:FD;
+0927:66;
+0928:32;
+0929:11;
+092A:06;
+092B:00;
+092C:0E;
+092D:08;
+092E:7E;
+092F:B7;
+0930:28;
+0931:5D;
+0932:FE;
+0933:01;
+0934:20;
+0935:08;
+0936:C5;
+0937:01;
+0938:0A;
+0939:00;
+093A:09;
+093B:C1;
+093C:18;
+093D:0E;
+093E:06;
+093F:0A;
+0940:7E;
+0941:CD;
+0942:2A;
+0943:03;
+0944:23;
+0945:10;
+0946:F9;
+0947:3E;
+0948:0D;
+0949:CD;
+094A:2A;
+094B:03;
+094C:F3;
+094D:3A;
+094E:EF;
+094F:68;
+0950:CB;
+0951:67;
+0952:20;
+0953:2D;
+0954:C5;
+0955:01;
+0956:14;
+0957:00;
+0958:CD;
+0959:BE;
+095A:5E;
+095B:C1;
+095C:3A;
+095D:EF;
+095E:68;
+095F:CB;
+0960:67;
+0961:28;
+0962:F9;
+0963:C5;
+0964:01;
+0965:14;
+0966:00;
+0967:CD;
+0968:BE;
+0969:5E;
+096A:C1;
+096B:3A;
+096C:EF;
+096D:68;
+096E:CB;
+096F:67;
+0970:20;
+0971:F9;
+0972:C5;
+0973:01;
+0974:14;
+0975:00;
+0976:CD;
+0977:BE;
+0978:5E;
+0979:C1;
+097A:3A;
+097B:EF;
+097C:68;
+097D:CB;
+097E:67;
+097F:28;
+0980:F9;
+0981:19;
+0982:0D;
+0983:20;
+0984:A9;
+0985:FD;
+0986:34;
+0987:11;
+0988:FD;
+0989:7E;
+098A:11;
+098B:FE;
+098C:0F;
+098D:20;
+098E:8C;
+098F:CD;
+0990:52;
+0991:5F;
+0992:E1;
+0993:C9;
+0994:CD;
+0995:67;
+0996:53;
+0997:E5;
+0998:B7;
+0999:C2;
+099A:41;
+099B:42;
+099C:F3;
+099D:CD;
+099E:41;
+099F:5F;
+09A0:C5;
+09A1:01;
+09A2:32;
+09A3:00;
+09A4:CD;
+09A5:BE;
+09A6:5E;
+09A7:C1;
+09A8:DB;
+09A9:13;
+09AA:B7;
+09AB:3E;
+09AC:04;
+09AD:FA;
+09AE:41;
+09AF:42;
+09B0:CD;
+09B1:13;
+09B2:59;
+09B3:FE;
+09B4:02;
+09B5:28;
+09B6:09;
+09B7:B7;
+09B8:C2;
+09B9:41;
+09BA:42;
+09BB:3E;
+09BC:0D;
+09BD:C3;
+09BE:41;
+09BF:42;
+09C0:1A;
+09C1:13;
+09C2:FD;
+09C3:77;
+09C4:16;
+09C5:1A;
+09C6:FD;
+09C7:77;
+09C8:15;
+09C9:EB;
+09CA:11;
+09CB:F5;
+09CC:FF;
+09CD:19;
+09CE:36;
+09CF:01;
+09D0:CD;
+09D1:A1;
+09D2:59;
+09D3:B7;
+09D4:C2;
+09D5:41;
+09D6:42;
+09D7:FD;
+09D8:36;
+09D9:12;
+09DA:00;
+09DB:FD;
+09DC:36;
+09DD:11;
+09DE:0F;
+09DF:CD;
+09E0:27;
+09E1:5B;
+09E2:B7;
+09E3:C2;
+09E4:41;
+09E5:42;
+09E6:FD;
+09E7:5E;
+09E8:34;
+09E9:FD;
+09EA:56;
+09EB:35;
+09EC:FD;
+09ED:6E;
+09EE:31;
+09EF:FD;
+09F0:66;
+09F1:32;
+09F2:01;
+09F3:50;
+09F4:00;
+09F5:ED;
+09F6:B0;
+09F7:FD;
+09F8:7E;
+09F9:16;
+09FA:B7;
+09FB:CA;
+09FC:4F;
+09FD:4A;
+09FE:FD;
+09FF:77;
+0A00:12;
+0A01:FD;
+0A02:7E;
+0A03:15;
+0A04:FD;
+0A05:77;
+0A06:11;
+0A07:CD;
+0A08:27;
+0A09:5B;
+0A0A:B7;
+0A0B:C2;
+0A0C:41;
+0A0D:42;
+0A0E:FD;
+0A0F:6E;
+0A10:31;
+0A11:FD;
+0A12:66;
+0A13:32;
+0A14:11;
+0A15:7E;
+0A16:00;
+0A17:19;
+0A18:7E;
+0A19:FD;
+0A1A:77;
+0A1B:16;
+0A1C:23;
+0A1D:7E;
+0A1E:FD;
+0A1F:77;
+0A20:15;
+0A21:FD;
+0A22:6E;
+0A23:34;
+0A24:FD;
+0A25:66;
+0A26:35;
+0A27:FD;
+0A28:7E;
+0A29:12;
+0A2A:3D;
+0A2B:CB;
+0A2C:27;
+0A2D:5F;
+0A2E:16;
+0A2F:00;
+0A30:FD;
+0A31:7E;
+0A32:11;
+0A33:FE;
+0A34:08;
+0A35:3F;
+0A36:ED;
+0A37:5A;
+0A38:E6;
+0A39:07;
+0A3A:3C;
+0A3B:47;
+0A3C:4E;
+0A3D:CB;
+0A3E:01;
+0A3F:CB;
+0A40:09;
+0A41:10;
+0A42:FC;
+0A43:CB;
+0A44:81;
+0A45:47;
+0A46:CB;
+0A47:09;
+0A48:CB;
+0A49:01;
+0A4A:10;
+0A4B:FC;
+0A4C:71;
+0A4D:18;
+0A4E:A8;
+0A4F:FD;
+0A50:6E;
+0A51:31;
+0A52:FD;
+0A53:66;
+0A54:32;
+0A55:E5;
+0A56:36;
+0A57:00;
+0A58:5D;
+0A59:54;
+0A5A:13;
+0A5B:01;
+0A5C:7F;
+0A5D:00;
+0A5E:ED;
+0A5F:B0;
+0A60:D1;
+0A61:FD;
+0A62:6E;
+0A63:34;
+0A64:FD;
+0A65:66;
+0A66:35;
+0A67:01;
+0A68:50;
+0A69:00;
+0A6A:ED;
+0A6B:B0;
+0A6C:FD;
+0A6D:36;
+0A6E:12;
+0A6F:00;
+0A70:FD;
+0A71:36;
+0A72:11;
+0A73:0F;
+0A74:CD;
+0A75:A1;
+0A76:59;
+0A77:B7;
+0A78:C2;
+0A79:41;
+0A7A:42;
+0A7B:CD;
+0A7C:52;
+0A7D:5F;
+0A7E:E1;
+0A7F:C9;
+0A80:E5;
+0A81:CD;
+0A82:78;
+0A83:53;
+0A84:B7;
+0A85:C2;
+0A86:41;
+0A87:42;
+0A88:CF;
+0A89:2C;
+0A8A:CD;
+0A8B:67;
+0A8C:53;
+0A8D:B7;
+0A8E:C2;
+0A8F:41;
+0A90:42;
+0A91:E1;
+0A92:E5;
+0A93:CD;
+0A94:78;
+0A95:53;
+0A96:23;
+0A97:E5;
+0A98:F3;
+0A99:CD;
+0A9A:41;
+0A9B:5F;
+0A9C:C5;
+0A9D:01;
+0A9E:32;
+0A9F:00;
+0AA0:CD;
+0AA1:BE;
+0AA2:5E;
+0AA3:C1;
+0AA4:DB;
+0AA5:13;
+0AA6:B7;
+0AA7:3E;
+0AA8:04;
+0AA9:FA;
+0AAA:41;
+0AAB:42;
+0AAC:CD;
+0AAD:13;
+0AAE:59;
+0AAF:FE;
+0AB0:02;
+0AB1:CA;
+0AB2:BD;
+0AB3:4A;
+0AB4:B7;
+0AB5:C2;
+0AB6:41;
+0AB7:42;
+0AB8:3E;
+0AB9:0D;
+0ABA:C3;
+0ABB:41;
+0ABC:42;
+0ABD:E1;
+0ABE:CD;
+0ABF:67;
+0AC0:53;
+0AC1:E3;
+0AC2:E5;
+0AC3:CD;
+0AC4:13;
+0AC5:59;
+0AC6:FE;
+0AC7:0D;
+0AC8:28;
+0AC9:04;
+0ACA:B7;
+0ACB:C2;
+0ACC:41;
+0ACD:42;
+0ACE:E1;
+0ACF:CD;
+0AD0:78;
+0AD1:53;
+0AD2:23;
+0AD3:E5;
+0AD4:CD;
+0AD5:13;
+0AD6:59;
+0AD7:FE;
+0AD8:02;
+0AD9:C2;
+0ADA:41;
+0ADB:42;
+0ADC:C1;
+0ADD:E5;
+0ADE:D5;
+0ADF:69;
+0AE0:60;
+0AE1:CD;
+0AE2:67;
+0AE3:53;
+0AE4:D1;
+0AE5:E1;
+0AE6:01;
+0AE7:F8;
+0AE8:FF;
+0AE9:09;
+0AEA:EB;
+0AEB:09;
+0AEC:2B;
+0AED:2B;
+0AEE:FD;
+0AEF:7E;
+0AF0:0A;
+0AF1:77;
+0AF2:23;
+0AF3:36;
+0AF4:3A;
+0AF5:23;
+0AF6:EB;
+0AF7:01;
+0AF8:08;
+0AF9:00;
+0AFA:ED;
+0AFB:B0;
+0AFC:CD;
+0AFD:A1;
+0AFE:59;
+0AFF:B7;
+0B00:C2;
+0B01:41;
+0B02:42;
+0B03:CD;
+0B04:52;
+0B05:5F;
+0B06:E1;
+0B07:C9;
+0B08:F3;
+0B09:CD;
+0B0A:41;
+0B0B:5F;
+0B0C:C5;
+0B0D:01;
+0B0E:E8;
+0B0F:03;
+0B10:CD;
+0B11:BE;
+0B12:5E;
+0B13:C1;
+0B14:DB;
+0B15:13;
+0B16:B7;
+0B17:3E;
+0B18:04;
+0B19:FA;
+0B1A:41;
+0B1B:42;
+0B1C:E5;
+0B1D:FD;
+0B1E:E5;
+0B1F:E1;
+0B20:11;
+0B21:4D;
+0B22:00;
+0B23:19;
+0B24:FD;
+0B25:36;
+0B26:12;
+0B27:00;
+0B28:FD;
+0B29:36;
+0B2A:11;
+0B2B:00;
+0B2C:FD;
+0B2D:75;
+0B2E:0E;
+0B2F:FD;
+0B30:74;
+0B31:0F;
+0B32:EB;
+0B33:21;
+0B34:4F;
+0B35:4D;
+0B36:01;
+0B37:18;
+0B38:00;
+0B39:ED;
+0B3A:B0;
+0B3B:62;
+0B3C:6B;
+0B3D:36;
+0B3E:00;
+0B3F:13;
+0B40:01;
+0B41:82;
+0B42:00;
+0B43:ED;
+0B44:B0;
+0B45:FD;
+0B46:36;
+0B47:38;
+0B48:11;
+0B49:06;
+0B4A:28;
+0B4B:CD;
+0B4C:01;
+0B4D:5F;
+0B4E:C5;
+0B4F:01;
+0B50:90;
+0B51:01;
+0B52:CD;
+0B53:BE;
+0B54:5E;
+0B55:C1;
+0B56:FD;
+0B57:6E;
+0B58:0E;
+0B59:FD;
+0B5A:66;
+0B5B:0F;
+0B5C:11;
+0B5D:0B;
+0B5E:00;
+0B5F:19;
+0B60:54;
+0B61:5D;
+0B62:13;
+0B63:42;
+0B64:4B;
+0B65:03;
+0B66:D9;
+0B67:C5;
+0B68:01;
+0B69:64;
+0B6A:00;
+0B6B:CD;
+0B6C:BE;
+0B6D:5E;
+0B6E:C1;
+0B6F:FD;
+0B70:7E;
+0B71:33;
+0B72:CB;
+0B73:B7;
+0B74:FD;
+0B75:77;
+0B76:33;
+0B77:D3;
+0B78:10;
+0B79:C5;
+0B7A:01;
+0B7B:64;
+0B7C:00;
+0B7D:CD;
+0B7E:BE;
+0B7F:5E;
+0B80:C1;
+0B81:DD;
+0B82:21;
+0B83:67;
+0B84:4D;
+0B85:FD;
+0B86:6E;
+0B87:0E;
+0B88:FD;
+0B89:66;
+0B8A:0F;
+0B8B:FD;
+0B8C:56;
+0B8D:33;
+0B8E:06;
+0B8F:9A;
+0B90:4E;
+0B91:3E;
+0B92:20;
+0B93:AA;
+0B94:CB;
+0B95:11;
+0B96:D2;
+0B97:A4;
+0B98:4B;
+0B99:D3;
+0B9A:10;
+0B9B:EE;
+0B9C:20;
+0B9D:57;
+0B9E:2B;
+0B9F:D3;
+0BA0:10;
+0BA1:C3;
+0BA2:AF;
+0BA3:4B;
+0BA4:D3;
+0BA5:10;
+0BA6:EE;
+0BA7:00;
+0BA8:57;
+0BA9:2B;
+0BAA:D3;
+0BAB:10;
+0BAC:C3;
+0BAD:AF;
+0BAE:4B;
+0BAF:23;
+0BB0:C3;
+0BB1:B3;
+0BB2:4B;
+0BB3:C3;
+0BB4:B6;
+0BB5:4B;
+0BB6:DB;
+0BB7:12;
+0BB8:3E;
+0BB9:20;
+0BBA:AA;
+0BBB:CB;
+0BBC:11;
+0BBD:D2;
+0BBE:CB;
+0BBF:4B;
+0BC0:D3;
+0BC1:10;
+0BC2:EE;
+0BC3:20;
+0BC4:57;
+0BC5:2B;
+0BC6:D3;
+0BC7:10;
+0BC8:C3;
+0BC9:D6;
+0BCA:4B;
+0BCB:D3;
+0BCC:10;
+0BCD:EE;
+0BCE:00;
+0BCF:57;
+0BD0:2B;
+0BD1:D3;
+0BD2:10;
+0BD3:C3;
+0BD4:D6;
+0BD5:4B;
+0BD6:23;
+0BD7:C3;
+0BD8:DA;
+0BD9:4B;
+0BDA:C3;
+0BDB:DD;
+0BDC:4B;
+0BDD:DB;
+0BDE:12;
+0BDF:3E;
+0BE0:20;
+0BE1:AA;
+0BE2:CB;
+0BE3:11;
+0BE4:D2;
+0BE5:F2;
+0BE6:4B;
+0BE7:D3;
+0BE8:10;
+0BE9:EE;
+0BEA:20;
+0BEB:57;
+0BEC:2B;
+0BED:D3;
+0BEE:10;
+0BEF:C3;
+0BF0:FD;
+0BF1:4B;
+0BF2:D3;
+0BF3:10;
+0BF4:EE;
+0BF5:00;
+0BF6:57;
+0BF7:2B;
+0BF8:D3;
+0BF9:10;
+0BFA:C3;
+0BFB:FD;
+0BFC:4B;
+0BFD:23;
+0BFE:C3;
+0BFF:01;
+0C00:4C;
+0C01:C3;
+0C02:04;
+0C03:4C;
+0C04:DB;
+0C05:12;
+0C06:3E;
+0C07:20;
+0C08:AA;
+0C09:CB;
+0C0A:11;
+0C0B:D2;
+0C0C:19;
+0C0D:4C;
+0C0E:D3;
+0C0F:10;
+0C10:EE;
+0C11:20;
+0C12:57;
+0C13:2B;
+0C14:D3;
+0C15:10;
+0C16:C3;
+0C17:24;
+0C18:4C;
+0C19:D3;
+0C1A:10;
+0C1B:EE;
+0C1C:00;
+0C1D:57;
+0C1E:2B;
+0C1F:D3;
+0C20:10;
+0C21:C3;
+0C22:24;
+0C23:4C;
+0C24:23;
+0C25:C3;
+0C26:28;
+0C27:4C;
+0C28:C3;
+0C29:2B;
+0C2A:4C;
+0C2B:DB;
+0C2C:12;
+0C2D:3E;
+0C2E:20;
+0C2F:AA;
+0C30:CB;
+0C31:11;
+0C32:D2;
+0C33:40;
+0C34:4C;
+0C35:D3;
+0C36:10;
+0C37:EE;
+0C38:20;
+0C39:57;
+0C3A:2B;
+0C3B:D3;
+0C3C:10;
+0C3D:C3;
+0C3E:4B;
+0C3F:4C;
+0C40:D3;
+0C41:10;
+0C42:EE;
+0C43:00;
+0C44:57;
+0C45:2B;
+0C46:D3;
+0C47:10;
+0C48:C3;
+0C49:4B;
+0C4A:4C;
+0C4B:23;
+0C4C:C3;
+0C4D:4F;
+0C4E:4C;
+0C4F:C3;
+0C50:52;
+0C51:4C;
+0C52:DB;
+0C53:12;
+0C54:3E;
+0C55:20;
+0C56:AA;
+0C57:CB;
+0C58:11;
+0C59:D2;
+0C5A:67;
+0C5B:4C;
+0C5C:D3;
+0C5D:10;
+0C5E:EE;
+0C5F:20;
+0C60:57;
+0C61:2B;
+0C62:D3;
+0C63:10;
+0C64:C3;
+0C65:72;
+0C66:4C;
+0C67:D3;
+0C68:10;
+0C69:EE;
+0C6A:00;
+0C6B:57;
+0C6C:2B;
+0C6D:D3;
+0C6E:10;
+0C6F:C3;
+0C70:72;
+0C71:4C;
+0C72:23;
+0C73:C3;
+0C74:76;
+0C75:4C;
+0C76:C3;
+0C77:79;
+0C78:4C;
+0C79:DB;
+0C7A:12;
+0C7B:3E;
+0C7C:20;
+0C7D:AA;
+0C7E:CB;
+0C7F:11;
+0C80:D2;
+0C81:8E;
+0C82:4C;
+0C83:D3;
+0C84:10;
+0C85:EE;
+0C86:20;
+0C87:57;
+0C88:2B;
+0C89:D3;
+0C8A:10;
+0C8B:C3;
+0C8C:99;
+0C8D:4C;
+0C8E:D3;
+0C8F:10;
+0C90:EE;
+0C91:00;
+0C92:57;
+0C93:2B;
+0C94:D3;
+0C95:10;
+0C96:C3;
+0C97:99;
+0C98:4C;
+0C99:23;
+0C9A:C3;
+0C9B:9D;
+0C9C:4C;
+0C9D:C3;
+0C9E:A0;
+0C9F:4C;
+0CA0:DB;
+0CA1:12;
+0CA2:3E;
+0CA3:20;
+0CA4:AA;
+0CA5:CB;
+0CA6:11;
+0CA7:D2;
+0CA8:B5;
+0CA9:4C;
+0CAA:D3;
+0CAB:10;
+0CAC:EE;
+0CAD:20;
+0CAE:57;
+0CAF:2B;
+0CB0:D3;
+0CB1:10;
+0CB2:C3;
+0CB3:C0;
+0CB4:4C;
+0CB5:D3;
+0CB6:10;
+0CB7:EE;
+0CB8:00;
+0CB9:57;
+0CBA:2B;
+0CBB:D3;
+0CBC:10;
+0CBD:C3;
+0CBE:C0;
+0CBF:4C;
+0CC0:23;
+0CC1:23;
+0CC2:00;
+0CC3:05;
+0CC4:C2;
+0CC5:90;
+0CC6:4B;
+0CC7:FD;
+0CC8:72;
+0CC9:33;
+0CCA:D9;
+0CCB:DD;
+0CCC:7E;
+0CCD:01;
+0CCE:DD;
+0CCF:23;
+0CD0:12;
+0CD1:86;
+0CD2:02;
+0CD3:1A;
+0CD4:D9;
+0CD5:FE;
+0CD6:FF;
+0CD7:C2;
+0CD8:85;
+0CD9:4B;
+0CDA:D9;
+0CDB:AF;
+0CDC:12;
+0CDD:7E;
+0CDE:3C;
+0CDF:77;
+0CE0:02;
+0CE1:D9;
+0CE2:FE;
+0CE3:28;
+0CE4:CA;
+0CE5:F9;
+0CE6:4C;
+0CE7:FD;
+0CE8:7E;
+0CE9:33;
+0CEA:F6;
+0CEB:40;
+0CEC:FD;
+0CED:77;
+0CEE:33;
+0CEF:D3;
+0CF0:10;
+0CF1:06;
+0CF2:01;
+0CF3:CD;
+0CF4:CE;
+0CF5:5E;
+0CF6:C3;
+0CF7:67;
+0CF8:4B;
+0CF9:FD;
+0CFA:7E;
+0CFB:33;
+0CFC:F6;
+0CFD:40;
+0CFE:FD;
+0CFF:77;
+0D00:33;
+0D01:D3;
+0D02:10;
+0D03:06;
+0D04:27;
+0D05:CD;
+0D06:01;
+0D07:5F;
+0D08:FD;
+0D09:36;
+0D0A:12;
+0D0B:00;
+0D0C:FD;
+0D0D:36;
+0D0E:11;
+0D0F:00;
+0D10:DD;
+0D11:21;
+0D12:67;
+0D13:4D;
+0D14:CD;
+0D15:EA;
+0D16:53;
+0D17:20;
+0D18:2C;
+0D19:DD;
+0D1A:7E;
+0D1B:01;
+0D1C:DD;
+0D1D:23;
+0D1E:FD;
+0D1F:77;
+0D20:11;
+0D21:FE;
+0D22:FF;
+0D23:20;
+0D24:EF;
+0D25:AF;
+0D26:FD;
+0D27:77;
+0D28:11;
+0D29:FD;
+0D2A:7E;
+0D2B:12;
+0D2C:3C;
+0D2D:FD;
+0D2E:77;
+0D2F:12;
+0D30:FE;
+0D31:28;
+0D32:28;
+0D33:07;
+0D34:06;
+0D35:01;
+0D36:CD;
+0D37:CE;
+0D38:5E;
+0D39:18;
+0D3A:D5;
+0D3B:06;
+0D3C:27;
+0D3D:CD;
+0D3E:01;
+0D3F:5F;
+0D40:CD;
+0D41:52;
+0D42:5F;
+0D43:E1;
+0D44:C9;
+0D45:FE;
+0D46:11;
+0D47:CA;
+0D48:41;
+0D49:42;
+0D4A:3E;
+0D4B:06;
+0D4C:C3;
+0D4D:41;
+0D4E:42;
+0D4F:80;
+0D50:80;
+0D51:80;
+0D52:80;
+0D53:80;
+0D54:80;
+0D55:00;
+0D56:FE;
+0D57:E7;
+0D58:18;
+0D59:C3;
+0D5A:00;
+0D5B:00;
+0D5C:00;
+0D5D:80;
+0D5E:80;
+0D5F:80;
+0D60:80;
+0D61:80;
+0D62:00;
+0D63:C3;
+0D64:18;
+0D65:E7;
+0D66:FE;
+0D67:00;
+0D68:0B;
+0D69:06;
+0D6A:01;
+0D6B:0C;
+0D6C:07;
+0D6D:02;
+0D6E:0D;
+0D6F:08;
+0D70:03;
+0D71:0E;
+0D72:09;
+0D73:04;
+0D74:0F;
+0D75:0A;
+0D76:05;
+0D77:FF;
+0D78:CD;
+0D79:1C;
+0D7A:2B;
+0D7B:B7;
+0D7C:CA;
+0D7D:4A;
+0D7E:1E;
+0D7F:FE;
+0D80:03;
+0D81:D2;
+0D82:4A;
+0D83:1E;
+0D84:FE;
+0D85:01;
+0D86:20;
+0D87:05;
+0D88:FD;
+0D89:36;
+0D8A:0B;
+0D8B:10;
+0D8C:C9;
+0D8D:FD;
+0D8E:36;
+0D8F:0B;
+0D90:80;
+0D91:C9;
+0D92:CD;
+0D93:28;
+0D94:28;
+0D95:CD;
+0D96:78;
+0D97:53;
+0D98:B7;
+0D99:C2;
+0D9A:41;
+0D9B:42;
+0D9C:CF;
+0D9D:2C;
+0D9E:E5;
+0D9F:CD;
+0DA0:78;
+0DA1:47;
+0DA2:FE;
+0DA3:08;
+0DA4:3E;
+0DA5:05;
+0DA6:C2;
+0DA7:41;
+0DA8:42;
+0DA9:13;
+0DAA:1A;
+0DAB:B7;
+0DAC:3E;
+0DAD:0F;
+0DAE:C2;
+0DAF:41;
+0DB0:42;
+0DB1:1B;
+0DB2:1A;
+0DB3:FE;
+0DB4:02;
+0DB5:28;
+0DB6:2B;
+0DB7:CD;
+0DB8:A5;
+0DB9:4F;
+0DBA:3E;
+0DBB:02;
+0DBC:12;
+0DBD:EB;
+0DBE:11;
+0DBF:0A;
+0DC0:00;
+0DC1:19;
+0DC2:7E;
+0DC3:23;
+0DC4:FD;
+0DC5:77;
+0DC6:12;
+0DC7:7E;
+0DC8:FD;
+0DC9:77;
+0DCA:11;
+0DCB:F3;
+0DCC:CD;
+0DCD:41;
+0DCE:5F;
+0DCF:C5;
+0DD0:01;
+0DD1:32;
+0DD2:00;
+0DD3:CD;
+0DD4:BE;
+0DD5:5E;
+0DD6:C1;
+0DD7:CD;
+0DD8:27;
+0DD9:5B;
+0DDA:B7;
+0DDB:C2;
+0DDC:41;
+0DDD:42;
+0DDE:FB;
+0DDF:CD;
+0DE0:52;
+0DE1:5F;
+0DE2:06;
+0DE3:C7;
+0DE4:2A;
+0DE5:A7;
+0DE6:78;
+0DE7:CD;
+0DE8:F9;
+0DE9:4D;
+0DEA:77;
+0DEB:23;
+0DEC:FE;
+0DED:0D;
+0DEE:28;
+0DEF:02;
+0DF0:10;
+0DF1:F5;
+0DF2:AF;
+0DF3:32;
+0DF4:A9;
+0DF5:78;
+0DF6:C3;
+0DF7:BD;
+0DF8:21;
+0DF9:E5;
+0DFA:D5;
+0DFB:C5;
+0DFC:CD;
+0DFD:78;
+0DFE:47;
+0DFF:21;
+0E00:0C;
+0E01:00;
+0E02:EB;
+0E03:19;
+0E04:7E;
+0E05:EB;
+0E06:FD;
+0E07:6E;
+0E08:31;
+0E09:FD;
+0E0A:66;
+0E0B:32;
+0E0C:85;
+0E0D:6F;
+0E0E:3E;
+0E0F:00;
+0E10:8C;
+0E11:67;
+0E12:7E;
+0E13:B7;
+0E14:20;
+0E15:04;
+0E16:0E;
+0E17:0D;
+0E18:18;
+0E19:40;
+0E1A:4F;
+0E1B:1A;
+0E1C:3C;
+0E1D:12;
+0E1E:FE;
+0E1F:7E;
+0E20:20;
+0E21:38;
+0E22:AF;
+0E23:12;
+0E24:FD;
+0E25:6E;
+0E26:31;
+0E27:FD;
+0E28:66;
+0E29:32;
+0E2A:D5;
+0E2B:11;
+0E2C:7E;
+0E2D:00;
+0E2E:19;
+0E2F:D1;
+0E30:7E;
+0E31:B7;
+0E32:28;
+0E33:2B;
+0E34:FD;
+0E35:77;
+0E36:12;
+0E37:1B;
+0E38:1B;
+0E39:12;
+0E3A:23;
+0E3B:7E;
+0E3C:FD;
+0E3D:77;
+0E3E:11;
+0E3F:13;
+0E40:12;
+0E41:F3;
+0E42:CD;
+0E43:41;
+0E44:5F;
+0E45:C5;
+0E46:01;
+0E47:32;
+0E48:00;
+0E49:CD;
+0E4A:BE;
+0E4B:5E;
+0E4C:C1;
+0E4D:C5;
+0E4E:CD;
+0E4F:27;
+0E50:5B;
+0E51:C1;
+0E52:B7;
+0E53:C2;
+0E54:41;
+0E55:42;
+0E56:CD;
+0E57:52;
+0E58:5F;
+0E59:FB;
+0E5A:79;
+0E5B:C1;
+0E5C:D1;
+0E5D:E1;
+0E5E:C9;
+0E5F:3E;
+0E60:7F;
+0E61:12;
+0E62:18;
+0E63:F6;
+0E64:CD;
+0E65:28;
+0E66:28;
+0E67:CD;
+0E68:78;
+0E69:53;
+0E6A:B7;
+0E6B:C2;
+0E6C:41;
+0E6D:42;
+0E6E:E5;
+0E6F:CD;
+0E70:78;
+0E71:47;
+0E72:FE;
+0E73:08;
+0E74:3E;
+0E75:05;
+0E76:C2;
+0E77:41;
+0E78:42;
+0E79:E1;
+0E7A:CF;
+0E7B:2C;
+0E7C:2B;
+0E7D:D7;
+0E7E:CC;
+0E7F:AC;
+0E80:4E;
+0E81:C8;
+0E82:E5;
+0E83:FE;
+0E84:2C;
+0E85:CA;
+0E86:B3;
+0E87:4E;
+0E88:FE;
+0E89:3A;
+0E8A:28;
+0E8B:2B;
+0E8C:C1;
+0E8D:CD;
+0E8E:37;
+0E8F:23;
+0E90:E5;
+0E91:E7;
+0E92:28;
+0E93:12;
+0E94:CD;
+0E95:BD;
+0E96:0F;
+0E97:CD;
+0E98:65;
+0E99:28;
+0E9A:2A;
+0E9B:21;
+0E9C:79;
+0E9D:CD;
+0E9E:BA;
+0E9F:4E;
+0EA0:3E;
+0EA1:20;
+0EA2:CD;
+0EA3:CA;
+0EA4:4E;
+0EA5:B7;
+0EA6:CC;
+0EA7:BA;
+0EA8:4E;
+0EA9:E1;
+0EAA:18;
+0EAB:D0;
+0EAC:3E;
+0EAD:0D;
+0EAE:CD;
+0EAF:CA;
+0EB0:4E;
+0EB1:AF;
+0EB2:C9;
+0EB3:CD;
+0EB4:CA;
+0EB5:4E;
+0EB6:E1;
+0EB7:D7;
+0EB8:18;
+0EB9:C7;
+0EBA:CD;
+0EBB:DA;
+0EBC:29;
+0EBD:CD;
+0EBE:C4;
+0EBF:09;
+0EC0:14;
+0EC1:15;
+0EC2:C8;
+0EC3:0A;
+0EC4:CD;
+0EC5:CA;
+0EC6:4E;
+0EC7:03;
+0EC8:18;
+0EC9:F7;
+0ECA:E5;
+0ECB:D5;
+0ECC:C5;
+0ECD:F5;
+0ECE:CD;
+0ECF:78;
+0ED0:47;
+0ED1:EB;
+0ED2:23;
+0ED3:7E;
+0ED4:B7;
+0ED5:3E;
+0ED6:10;
+0ED7:CA;
+0ED8:41;
+0ED9:42;
+0EDA:2B;
+0EDB:7E;
+0EDC:FE;
+0EDD:02;
+0EDE:28;
+0EDF:2C;
+0EE0:CD;
+0EE1:A5;
+0EE2:4F;
+0EE3:11;
+0EE4:0A;
+0EE5:00;
+0EE6:19;
+0EE7:7E;
+0EE8:23;
+0EE9:FD;
+0EEA:77;
+0EEB:12;
+0EEC:7E;
+0EED:23;
+0EEE:FD;
+0EEF:77;
+0EF0:11;
+0EF1:F3;
+0EF2:CD;
+0EF3:41;
+0EF4:5F;
+0EF5:DB;
+0EF6:13;
+0EF7:B7;
+0EF8:3E;
+0EF9:04;
+0EFA:FA;
+0EFB:41;
+0EFC:42;
+0EFD:E5;
+0EFE:CD;
+0EFF:27;
+0F00:5B;
+0F01:B7;
+0F02:C2;
+0F03:41;
+0F04:42;
+0F05:E1;
+0F06:11;
+0F07:F4;
+0F08:FF;
+0F09:19;
+0F0A:36;
+0F0B:02;
+0F0C:11;
+0F0D:0C;
+0F0E:00;
+0F0F:19;
+0F10:5E;
+0F11:34;
+0F12:16;
+0F13:00;
+0F14:FD;
+0F15:6E;
+0F16:31;
+0F17:FD;
+0F18:66;
+0F19:32;
+0F1A:19;
+0F1B:F1;
+0F1C:F5;
+0F1D:77;
+0F1E:7B;
+0F1F:3C;
+0F20:FE;
+0F21:7E;
+0F22:20;
+0F23:78;
+0F24:F3;
+0F25:CD;
+0F26:41;
+0F27:5F;
+0F28:C5;
+0F29:01;
+0F2A:02;
+0F2B:00;
+0F2C:CD;
+0F2D:BE;
+0F2E:5E;
+0F2F:C1;
+0F30:DB;
+0F31:13;
+0F32:B7;
+0F33:3E;
+0F34:04;
+0F35:FA;
+0F36:41;
+0F37:42;
+0F38:FD;
+0F39:5E;
+0F3A:11;
+0F3B:FD;
+0F3C:56;
+0F3D:12;
+0F3E:D5;
+0F3F:CD;
+0F40:A1;
+0F41:59;
+0F42:B7;
+0F43:C2;
+0F44:41;
+0F45:42;
+0F46:CD;
+0F47:17;
+0F48:47;
+0F49:B7;
+0F4A:C2;
+0F4B:41;
+0F4C:42;
+0F4D:CD;
+0F4E:BF;
+0F4F:58;
+0F50:B7;
+0F51:C2;
+0F52:41;
+0F53:42;
+0F54:CD;
+0F55:54;
+0F56:47;
+0F57:D1;
+0F58:FD;
+0F59:73;
+0F5A:11;
+0F5B:FD;
+0F5C:72;
+0F5D:12;
+0F5E:CD;
+0F5F:27;
+0F60:5B;
+0F61:B7;
+0F62:C2;
+0F63:41;
+0F64:42;
+0F65:FD;
+0F66:6E;
+0F67:31;
+0F68:FD;
+0F69:66;
+0F6A:32;
+0F6B:11;
+0F6C:7E;
+0F6D:00;
+0F6E:19;
+0F6F:FD;
+0F70:7E;
+0F71:16;
+0F72:77;
+0F73:23;
+0F74:FD;
+0F75:7E;
+0F76:15;
+0F77:77;
+0F78:CD;
+0F79:A1;
+0F7A:59;
+0F7B:B7;
+0F7C:C2;
+0F7D:41;
+0F7E:42;
+0F7F:CD;
+0F80:78;
+0F81:47;
+0F82:EB;
+0F83:11;
+0F84:0A;
+0F85:00;
+0F86:19;
+0F87:FD;
+0F88:7E;
+0F89:16;
+0F8A:FD;
+0F8B:77;
+0F8C:12;
+0F8D:77;
+0F8E:23;
+0F8F:FD;
+0F90:7E;
+0F91:15;
+0F92:FD;
+0F93:77;
+0F94:11;
+0F95:77;
+0F96:23;
+0F97:AF;
+0F98:77;
+0F99:CD;
+0F9A:49;
+0F9B:47;
+0F9C:CD;
+0F9D:52;
+0F9E:5F;
+0F9F:FB;
+0FA0:F1;
+0FA1:C1;
+0FA2:D1;
+0FA3:E1;
+0FA4:C9;
+0FA5:E5;
+0FA6:D5;
+0FA7:FD;
+0FA8:E5;
+0FA9:E1;
+0FAA:11;
+0FAB:17;
+0FAC:00;
+0FAD:19;
+0FAE:CD;
+0FAF:BB;
+0FB0:4F;
+0FB1:11;
+0FB2:0D;
+0FB3:00;
+0FB4:19;
+0FB5:CD;
+0FB6:BB;
+0FB7:4F;
+0FB8:D1;
+0FB9:E1;
+0FBA:C9;
+0FBB:7E;
+0FBC:B7;
+0FBD:C8;
+0FBE:FE;
+0FBF:02;
+0FC0:C0;
+0FC1:36;
+0FC2:01;
+0FC3:23;
+0FC4:7E;
+0FC5:B7;
+0FC6:2B;
+0FC7:C8;
+0FC8:11;
+0FC9:0A;
+0FCA:00;
+0FCB:19;
+0FCC:7E;
+0FCD:FD;
+0FCE:77;
+0FCF:12;
+0FD0:23;
+0FD1:7E;
+0FD2:FD;
+0FD3:77;
+0FD4:11;
+0FD5:F3;
+0FD6:CD;
+0FD7:41;
+0FD8:5F;
+0FD9:C5;
+0FDA:01;
+0FDB:32;
+0FDC:00;
+0FDD:CD;
+0FDE:BE;
+0FDF:5E;
+0FE0:C1;
+0FE1:DB;
+0FE2:13;
+0FE3:B7;
+0FE4:3E;
+0FE5:04;
+0FE6:FA;
+0FE7:41;
+0FE8:42;
+0FE9:E5;
+0FEA:CD;
+0FEB:A1;
+0FEC:59;
+0FED:E1;
+0FEE:B7;
+0FEF:C2;
+0FF0:41;
+0FF1:42;
+0FF2:11;
+0FF3:F5;
+0FF4:FF;
+0FF5:19;
+0FF6:CD;
+0FF7:52;
+0FF8:5F;
+0FF9:FB;
+0FFA:C9;
+0FFB:ED;
+0FFC:5B;
+0FFD:A2;
+0FFE:78;
+0FFF:13;
+1000:7A;
+1001:B3;
+1002:1E;
+1003:16;
+1004:C2;
+1005:A2;
+1006:19;
+1007:FD;
+1008:36;
+1009:39;
+100A:01;
+100B:2B;
+100C:D7;
+100D:28;
+100E:4E;
+100F:CD;
+1010:67;
+1011:53;
+1012:B7;
+1013:C2;
+1014:41;
+1015:42;
+1016:E5;
+1017:CD;
+1018:68;
+1019:51;
+101A:CD;
+101B:19;
+101C:52;
+101D:F3;
+101E:CD;
+101F:41;
+1020:5F;
+1021:C5;
+1022:01;
+1023:32;
+1024:00;
+1025:CD;
+1026:BE;
+1027:5E;
+1028:C1;
+1029:CD;
+102A:13;
+102B:59;
+102C:FE;
+102D:02;
+102E:28;
+102F:09;
+1030:B7;
+1031:C2;
+1032:41;
+1033:42;
+1034:3E;
+1035:0D;
+1036:C3;
+1037:41;
+1038:42;
+1039:FD;
+103A:7E;
+103B:0A;
+103C:FD;
+103D:77;
+103E:09;
+103F:FE;
+1040:44;
+1041:3E;
+1042:0C;
+1043:CA;
+1044:41;
+1045:42;
+1046:CD;
+1047:D3;
+1048:43;
+1049:B7;
+104A:C2;
+104B:62;
+104C:51;
+104D:CD;
+104E:75;
+104F:52;
+1050:CD;
+1051:41;
+1052:5F;
+1053:CD;
+1054:6E;
+1055:44;
+1056:B7;
+1057:C2;
+1058:62;
+1059:51;
+105A:C3;
+105B:37;
+105C:51;
+105D:E5;
+105E:21;
+105F:C6;
+1060:FF;
+1061:39;
+1062:11;
+1063:E9;
+1064:7A;
+1065:B7;
+1066:ED;
+1067:52;
+1068:CB;
+1069:3C;
+106A:CB;
+106B:3C;
+106C:CB;
+106D:3C;
+106E:FD;
+106F:74;
+1070:36;
+1071:FD;
+1072:36;
+1073:37;
+1074:00;
+1075:FD;
+1076:36;
+1077:12;
+1078:00;
+1079:FD;
+107A:36;
+107B:11;
+107C:00;
+107D:CD;
+107E:A5;
+107F:4F;
+1080:CD;
+1081:68;
+1082:51;
+1083:11;
+1084:E9;
+1085:7A;
+1086:ED;
+1087:53;
+1088:A4;
+1089:78;
+108A:CD;
+108B:19;
+108C:52;
+108D:F3;
+108E:CD;
+108F:41;
+1090:5F;
+1091:CD;
+1092:27;
+1093:5B;
+1094:B7;
+1095:C2;
+1096:62;
+1097:51;
+1098:FD;
+1099:6E;
+109A:31;
+109B:FD;
+109C:66;
+109D:32;
+109E:ED;
+109F:5B;
+10A0:A4;
+10A1:78;
+10A2:01;
+10A3:80;
+10A4:00;
+10A5:ED;
+10A6:B0;
+10A7:ED;
+10A8:53;
+10A9:A4;
+10AA:78;
+10AB:FD;
+10AC:34;
+10AD:11;
+10AE:FD;
+10AF:7E;
+10B0:11;
+10B1:FE;
+10B2:10;
+10B3:20;
+10B4:DC;
+10B5:FD;
+10B6:36;
+10B7:11;
+10B8:00;
+10B9:FD;
+10BA:34;
+10BB:12;
+10BC:FD;
+10BD:7E;
+10BE:12;
+10BF:FE;
+10C0:28;
+10C1:28;
+10C2:08;
+10C3:FD;
+10C4:96;
+10C5:37;
+10C6:FD;
+10C7:96;
+10C8:36;
+10C9:20;
+10CA:C6;
+10CB:FD;
+10CC:7E;
+10CD:37;
+10CE:FD;
+10CF:77;
+10D0:12;
+10D1:CD;
+10D2:52;
+10D3:5F;
+10D4:CD;
+10D5:75;
+10D6:52;
+10D7:F3;
+10D8:CD;
+10D9:41;
+10DA:5F;
+10DB:C5;
+10DC:01;
+10DD:02;
+10DE:00;
+10DF:CD;
+10E0:BE;
+10E1:5E;
+10E2:C1;
+10E3:DB;
+10E4:13;
+10E5:B7;
+10E6:3E;
+10E7:04;
+10E8:FA;
+10E9:62;
+10EA:51;
+10EB:21;
+10EC:E9;
+10ED:7A;
+10EE:22;
+10EF:A4;
+10F0:78;
+10F1:2A;
+10F2:A4;
+10F3:78;
+10F4:FD;
+10F5:5E;
+10F6:31;
+10F7:FD;
+10F8:56;
+10F9:32;
+10FA:01;
+10FB:80;
+10FC:00;
+10FD:ED;
+10FE:B0;
+10FF:22;
+1100:A4;
+1101:78;
+1102:CD;
+1103:A1;
+1104:59;
+1105:B7;
+1106:20;
+1107:5A;
+1108:FD;
+1109:34;
+110A:11;
+110B:FD;
+110C:7E;
+110D:11;
+110E:FE;
+110F:10;
+1110:20;
+1111:DF;
+1112:FD;
+1113:36;
+1114:11;
+1115:00;
+1116:FD;
+1117:34;
+1118:12;
+1119:FD;
+111A:7E;
+111B:12;
+111C:FE;
+111D:28;
+111E:28;
+111F:17;
+1120:FD;
+1121:96;
+1122:37;
+1123:FD;
+1124:96;
+1125:36;
+1126:20;
+1127:C9;
+1128:FD;
+1129:7E;
+112A:36;
+112B:FD;
+112C:86;
+112D:37;
+112E:FD;
+112F:77;
+1130:37;
+1131:CD;
+1132:52;
+1133:5F;
+1134:C3;
+1135:83;
+1136:50;
+1137:CD;
+1138:52;
+1139:5F;
+113A:CD;
+113B:44;
+113C:51;
+113D:01;
+113E:19;
+113F:1A;
+1140:C5;
+1141:C3;
+1142:4D;
+1143:1B;
+1144:21;
+1145:E9;
+1146:7A;
+1147:22;
+1148:A4;
+1149:78;
+114A:36;
+114B:00;
+114C:23;
+114D:36;
+114E:00;
+114F:23;
+1150:22;
+1151:F9;
+1152:78;
+1153:22;
+1154:FB;
+1155:78;
+1156:22;
+1157:FD;
+1158:78;
+1159:FD;
+115A:36;
+115B:0B;
+115C:10;
+115D:FD;
+115E:36;
+115F:39;
+1160:00;
+1161:C9;
+1162:CD;
+1163:44;
+1164:51;
+1165:C3;
+1166:41;
+1167:42;
+1168:21;
+1169:EC;
+116A:51;
+116B:CD;
+116C:A7;
+116D:28;
+116E:CD;
+116F:92;
+1170:51;
+1171:79;
+1172:CD;
+1173:2A;
+1174:03;
+1175:E6;
+1176:03;
+1177:FD;
+1178:77;
+1179:0D;
+117A:21;
+117B:00;
+117C:52;
+117D:CD;
+117E:A7;
+117F:28;
+1180:CD;
+1181:92;
+1182:51;
+1183:79;
+1184:CD;
+1185:2A;
+1186:03;
+1187:E6;
+1188:03;
+1189:FD;
+118A:77;
+118B:10;
+118C:3E;
+118D:0D;
+118E:CD;
+118F:2A;
+1190:03;
+1191:C9;
+1192:3A;
+1193:AF;
+1194:7A;
+1195:B7;
+1196:20;
+1197:FA;
+1198:F3;
+1199:1E;
+119A:10;
+119B:53;
+119C:2A;
+119D:20;
+119E:78;
+119F:3A;
+11A0:00;
+11A1:68;
+11A2:B7;
+11A3:FA;
+11A4:9F;
+11A5:51;
+11A6:15;
+11A7:20;
+11A8:05;
+11A9:53;
+11AA:3E;
+11AB:40;
+11AC:AE;
+11AD:77;
+11AE:3A;
+11AF:00;
+11B0:68;
+11B1:B7;
+11B2:F2;
+11B3:AE;
+11B4:51;
+11B5:3A;
+11B6:DF;
+11B7:68;
+11B8:CB;
+11B9:57;
+11BA:20;
+11BB:0F;
+11BC:3A;
+11BD:FD;
+11BE:68;
+11BF:CB;
+11C0:57;
+11C1:20;
+11C2:08;
+11C3:CD;
+11C4:44;
+11C5:51;
+11C6:3E;
+11C7:11;
+11C8:C3;
+11C9:41;
+11CA:42;
+11CB:3A;
+11CC:F7;
+11CD:68;
+11CE:CB;
+11CF:67;
+11D0:0E;
+11D1:31;
+11D2:28;
+11D3:06;
+11D4:CB;
+11D5:4F;
+11D6:0E;
+11D7:32;
+11D8:20;
+11D9:C5;
+11DA:C5;
+11DB:01;
+11DC:64;
+11DD:00;
+11DE:CD;
+11DF:BE;
+11E0:5E;
+11E1:C1;
+11E2:3A;
+11E3:00;
+11E4:68;
+11E5:F6;
+11E6:80;
+11E7:3C;
+11E8:20;
+11E9:F8;
+11EA:FB;
+11EB:C9;
+11EC:0D;
+11ED:53;
+11EE:4F;
+11EF:55;
+11F0:52;
+11F1:43;
+11F2:45;
+11F3:20;
+11F4:44;
+11F5:49;
+11F6:53;
+11F7:4B;
+11F8:28;
+11F9:31;
+11FA:2F;
+11FB:32;
+11FC:29;
+11FD:3F;
+11FE:20;
+11FF:00;
+1200:0D;
+1201:44;
+1202:45;
+1203:53;
+1204:54;
+1205:49;
+1206:4E;
+1207:41;
+1208:54;
+1209:49;
+120A:4F;
+120B:4E;
+120C:20;
+120D:44;
+120E:49;
+120F:53;
+1210:4B;
+1211:28;
+1212:31;
+1213:2F;
+1214:32;
+1215:29;
+1216:3F;
+1217:20;
+1218:00;
+1219:FD;
+121A:7E;
+121B:0D;
+121C:CD;
+121D:84;
+121E:4D;
+121F:FD;
+1220:BE;
+1221:10;
+1222:C0;
+1223:21;
+1224:84;
+1225:52;
+1226:CD;
+1227:A7;
+1228:28;
+1229:21;
+122A:9D;
+122B:52;
+122C:CD;
+122D:A7;
+122E:28;
+122F:3A;
+1230:AF;
+1231:7A;
+1232:B7;
+1233:20;
+1234:FA;
+1235:F3;
+1236:1E;
+1237:10;
+1238:53;
+1239:2A;
+123A:20;
+123B:78;
+123C:3A;
+123D:00;
+123E:68;
+123F:B7;
+1240:FA;
+1241:3C;
+1242:52;
+1243:15;
+1244:20;
+1245:05;
+1246:53;
+1247:3E;
+1248:40;
+1249:AE;
+124A:77;
+124B:3A;
+124C:00;
+124D:68;
+124E:B7;
+124F:F2;
+1250:4B;
+1251:52;
+1252:3A;
+1253:DF;
+1254:68;
+1255:CB;
+1256:57;
+1257:20;
+1258:0F;
+1259:3A;
+125A:FD;
+125B:68;
+125C:CB;
+125D:57;
+125E:20;
+125F:08;
+1260:CD;
+1261:44;
+1262:51;
+1263:3E;
+1264:11;
+1265:C3;
+1266:41;
+1267:42;
+1268:3A;
+1269:EF;
+126A:68;
+126B:CB;
+126C:67;
+126D:20;
+126E:CD;
+126F:3A;
+1270:3C;
+1271:78;
+1272:77;
+1273:FB;
+1274:C9;
+1275:FD;
+1276:7E;
+1277:10;
+1278:CD;
+1279:84;
+127A:4D;
+127B:FD;
+127C:BE;
+127D:0D;
+127E:C0;
+127F:21;
+1280:B7;
+1281:52;
+1282:18;
+1283:A2;
+1284:0D;
+1285:49;
+1286:4E;
+1287:53;
+1288:45;
+1289:52;
+128A:54;
+128B:20;
+128C:53;
+128D:4F;
+128E:55;
+128F:52;
+1290:43;
+1291:45;
+1292:20;
+1293:44;
+1294:49;
+1295:53;
+1296:4B;
+1297:45;
+1298:54;
+1299:54;
+129A:45;
+129B:0D;
+129C:00;
+129D:28;
+129E:50;
+129F:52;
+12A0:45;
+12A1:53;
+12A2:53;
+12A3:20;
+12A4:53;
+12A5:50;
+12A6:41;
+12A7:43;
+12A8:45;
+12A9:20;
+12AA:57;
+12AB:48;
+12AC:45;
+12AD:4E;
+12AE:20;
+12AF:52;
+12B0:45;
+12B1:41;
+12B2:44;
+12B3:59;
+12B4:29;
+12B5:0D;
+12B6:00;
+12B7:0D;
+12B8:49;
+12B9:4E;
+12BA:53;
+12BB:45;
+12BC:52;
+12BD:54;
+12BE:20;
+12BF:44;
+12C0:45;
+12C1:53;
+12C2:54;
+12C3:49;
+12C4:4E;
+12C5:41;
+12C6:54;
+12C7:49;
+12C8:4F;
+12C9:4E;
+12CA:20;
+12CB:44;
+12CC:49;
+12CD:53;
+12CE:4B;
+12CF:45;
+12D0:54;
+12D1:54;
+12D2:45;
+12D3:0D;
+12D4:00;
+12D5:E5;
+12D6:F3;
+12D7:CD;
+12D8:41;
+12D9:5F;
+12DA:C5;
+12DB:01;
+12DC:32;
+12DD:00;
+12DE:CD;
+12DF:BE;
+12E0:5E;
+12E1:C1;
+12E2:FD;
+12E3:36;
+12E4:12;
+12E5:00;
+12E6:FD;
+12E7:36;
+12E8:11;
+12E9:0F;
+12EA:CD;
+12EB:27;
+12EC:5B;
+12ED:B7;
+12EE:C2;
+12EF:41;
+12F0:42;
+12F1:CD;
+12F2:52;
+12F3:5F;
+12F4:FD;
+12F5:6E;
+12F6:31;
+12F7:FD;
+12F8:66;
+12F9:32;
+12FA:1E;
+12FB:00;
+12FC:16;
+12FD:00;
+12FE:0E;
+12FF:4E;
+1300:06;
+1301:08;
+1302:7E;
+1303:CB;
+1304:0F;
+1305:38;
+1306:01;
+1307:13;
+1308:10;
+1309:F9;
+130A:23;
+130B:0D;
+130C:20;
+130D:F2;
+130E:6B;
+130F:62;
+1310:E5;
+1311:CD;
+1312:AF;
+1313:0F;
+1314:21;
+1315:4A;
+1316:53;
+1317:CD;
+1318:A7;
+1319:28;
+131A:E1;
+131B:E5;
+131C:CB;
+131D:3C;
+131E:CB;
+131F:1D;
+1320:CB;
+1321:3C;
+1322:CB;
+1323:1D;
+1324:CB;
+1325:3C;
+1326:CB;
+1327:1D;
+1328:CD;
+1329:AF;
+132A:0F;
+132B:3E;
+132C:2E;
+132D:CD;
+132E:2A;
+132F:03;
+1330:E1;
+1331:3E;
+1332:07;
+1333:A5;
+1334:3C;
+1335:47;
+1336:21;
+1337:83;
+1338:FF;
+1339:11;
+133A:7D;
+133B:00;
+133C:19;
+133D:10;
+133E:FD;
+133F:CD;
+1340:AF;
+1341:0F;
+1342:21;
+1343:59;
+1344:53;
+1345:CD;
+1346:A7;
+1347:28;
+1348:E1;
+1349:C9;
+134A:20;
+134B:52;
+134C:45;
+134D:43;
+134E:4F;
+134F:52;
+1350:44;
+1351:53;
+1352:20;
+1353:46;
+1354:52;
+1355:45;
+1356:45;
+1357:0D;
+1358:00;
+1359:4B;
+135A:20;
+135B:42;
+135C:59;
+135D:54;
+135E:45;
+135F:53;
+1360:20;
+1361:46;
+1362:52;
+1363:45;
+1364:45;
+1365:0D;
+1366:00;
+1367:CD;
+1368:78;
+1369:53;
+136A:B7;
+136B:C2;
+136C:41;
+136D:42;
+136E:7E;
+136F:B7;
+1370:C8;
+1371:FE;
+1372:3A;
+1373:C2;
+1374:97;
+1375:19;
+1376:AF;
+1377:C9;
+1378:FD;
+1379:E5;
+137A:06;
+137B:08;
+137C:FD;
+137D:36;
+137E:01;
+137F:20;
+1380:FD;
+1381:23;
+1382:10;
+1383:F8;
+1384:FD;
+1385:E1;
+1386:7E;
+1387:23;
+1388:FE;
+1389:20;
+138A:28;
+138B:FA;
+138C:2B;
+138D:CF;
+138E:22;
+138F:06;
+1390:08;
+1391:7E;
+1392:FE;
+1393:22;
+1394:20;
+1395:03;
+1396:3E;
+1397:01;
+1398:C9;
+1399:FD;
+139A:E5;
+139B:7E;
+139C:23;
+139D:FE;
+139E:22;
+139F:28;
+13A0:14;
+13A1:FD;
+13A2:77;
+13A3:01;
+13A4:FD;
+13A5:23;
+13A6:10;
+13A7:F3;
+13A8:FD;
+13A9:E1;
+13AA:7E;
+13AB:23;
+13AC:B7;
+13AD:28;
+13AE:E7;
+13AF:FE;
+13B0:22;
+13B1:28;
+13B2:04;
+13B3:18;
+13B4:F5;
+13B5:FD;
+13B6:E1;
+13B7:AF;
+13B8:C9;
+13B9:CD;
+13BA:C1;
+13BB:53;
+13BC:D8;
+13BD:53;
+13BE:C3;
+13BF:C1;
+13C0:53;
+13C1:7E;
+13C2:23;
+13C3:CD;
+13C4:D5;
+13C5:53;
+13C6:D8;
+13C7:17;
+13C8:17;
+13C9:17;
+13CA:17;
+13CB:5F;
+13CC:7E;
+13CD:23;
+13CE:CD;
+13CF:D5;
+13D0:53;
+13D1:D8;
+13D2:B3;
+13D3:5F;
+13D4:C9;
+13D5:FE;
+13D6:30;
+13D7:D8;
+13D8:FE;
+13D9:3A;
+13DA:30;
+13DB:03;
+13DC:E6;
+13DD:0F;
+13DE:C9;
+13DF:FE;
+13E0:41;
+13E1:D8;
+13E2:FE;
+13E3:47;
+13E4:30;
+13E5:02;
+13E6:C6;
+13E7:C9;
+13E8:3F;
+13E9:C9;
+13EA:26;
+13EB:A5;
+13EC:2E;
+13ED:0A;
+13EE:18;
+13EF:0B;
+13F0:2E;
+13F1:0A;
+13F2:FD;
+13F3:36;
+13F4:38;
+13F5:11;
+13F6:06;
+13F7:28;
+13F8:CD;
+13F9:01;
+13FA:5F;
+13FB:FD;
+13FC:7E;
+13FD:12;
+13FE:FD;
+13FF:96;
+1400:14;
+1401:28;
+1402:1A;
+1403:F2;
+1404:11;
+1405:54;
+1406:ED;
+1407:44;
+1408:47;
+1409:CD;
+140A:01;
+140B:5F;
+140C:18;
+140D:0F;
+140E:C3;
+140F:A4;
+1410:5E;
+1411:47;
+1412:CD;
+1413:CE;
+1414:5E;
+1415:C5;
+1416:01;
+1417:64;
+1418:00;
+1419:CD;
+141A:BE;
+141B:5E;
+141C:C1;
+141D:0E;
+141E:12;
+141F:FD;
+1420:7E;
+1421:12;
+1422:FD;
+1423:86;
+1424:11;
+1425:57;
+1426:DB;
+1427:11;
+1428:ED;
+1429:78;
+142A:F2;
+142B:28;
+142C:54;
+142D:00;
+142E:00;
+142F:00;
+1430:00;
+1431:3A;
+1432:DF;
+1433:68;
+1434:E6;
+1435:04;
+1436:28;
+1437:D6;
+1438:DB;
+1439:11;
+143A:47;
+143B:ED;
+143C:78;
+143D:F2;
+143E:3B;
+143F:54;
+1440:78;
+1441:FE;
+1442:80;
+1443:C2;
+1444:31;
+1445:54;
+1446:00;
+1447:00;
+1448:00;
+1449:3E;
+144A:00;
+144B:3E;
+144C:00;
+144D:DB;
+144E:11;
+144F:ED;
+1450:78;
+1451:F2;
+1452:4F;
+1453:54;
+1454:2B;
+1455:23;
+1456:2B;
+1457:23;
+1458:2B;
+1459:23;
+145A:00;
+145B:3E;
+145C:00;
+145D:DB;
+145E:11;
+145F:ED;
+1460:78;
+1461:F2;
+1462:5F;
+1463:54;
+1464:2B;
+1465:23;
+1466:2B;
+1467:23;
+1468:2B;
+1469:23;
+146A:00;
+146B:3E;
+146C:00;
+146D:DB;
+146E:11;
+146F:ED;
+1470:78;
+1471:F2;
+1472:6F;
+1473:54;
+1474:2B;
+1475:23;
+1476:2B;
+1477:23;
+1478:2B;
+1479:23;
+147A:00;
+147B:3E;
+147C:00;
+147D:DB;
+147E:11;
+147F:ED;
+1480:78;
+1481:F2;
+1482:7F;
+1483:54;
+1484:2B;
+1485:23;
+1486:2B;
+1487:23;
+1488:2B;
+1489:23;
+148A:00;
+148B:3E;
+148C:00;
+148D:DB;
+148E:11;
+148F:ED;
+1490:78;
+1491:F2;
+1492:8F;
+1493:54;
+1494:2B;
+1495:23;
+1496:2B;
+1497:23;
+1498:2B;
+1499:23;
+149A:00;
+149B:3E;
+149C:00;
+149D:DB;
+149E:11;
+149F:ED;
+14A0:78;
+14A1:F2;
+14A2:9F;
+14A3:54;
+14A4:2B;
+14A5:23;
+14A6:2B;
+14A7:23;
+14A8:2B;
+14A9:23;
+14AA:00;
+14AB:3E;
+14AC:00;
+14AD:DB;
+14AE:11;
+14AF:ED;
+14B0:78;
+14B1:F2;
+14B2:AF;
+14B3:54;
+14B4:2B;
+14B5:23;
+14B6:2B;
+14B7:23;
+14B8:2B;
+14B9:23;
+14BA:00;
+14BB:3E;
+14BC:00;
+14BD:DB;
+14BE:11;
+14BF:47;
+14C0:ED;
+14C1:78;
+14C2:F2;
+14C3:C0;
+14C4:54;
+14C5:78;
+14C6:FE;
+14C7:80;
+14C8:CA;
+14C9:46;
+14CA:54;
+14CB:00;
+14CC:00;
+14CD:00;
+14CE:3E;
+14CF:00;
+14D0:3E;
+14D1:00;
+14D2:DB;
+14D3:11;
+14D4:ED;
+14D5:78;
+14D6:F2;
+14D7:D4;
+14D8:54;
+14D9:2B;
+14DA:23;
+14DB:2B;
+14DC:23;
+14DD:2B;
+14DE:23;
+14DF:00;
+14E0:3E;
+14E1:00;
+14E2:DB;
+14E3:11;
+14E4:ED;
+14E5:78;
+14E6:F2;
+14E7:E4;
+14E8:54;
+14E9:2B;
+14EA:23;
+14EB:2B;
+14EC:23;
+14ED:2B;
+14EE:23;
+14EF:00;
+14F0:3E;
+14F1:00;
+14F2:DB;
+14F3:11;
+14F4:ED;
+14F5:78;
+14F6:F2;
+14F7:F4;
+14F8:54;
+14F9:2B;
+14FA:23;
+14FB:2B;
+14FC:23;
+14FD:2B;
+14FE:23;
+14FF:00;
+1500:3E;
+1501:00;
+1502:DB;
+1503:11;
+1504:ED;
+1505:78;
+1506:F2;
+1507:04;
+1508:55;
+1509:2B;
+150A:23;
+150B:2B;
+150C:23;
+150D:2B;
+150E:23;
+150F:00;
+1510:3E;
+1511:00;
+1512:DB;
+1513:11;
+1514:ED;
+1515:78;
+1516:F2;
+1517:14;
+1518:55;
+1519:2B;
+151A:23;
+151B:2B;
+151C:23;
+151D:2B;
+151E:23;
+151F:00;
+1520:3E;
+1521:00;
+1522:DB;
+1523:11;
+1524:ED;
+1525:78;
+1526:F2;
+1527:24;
+1528:55;
+1529:2B;
+152A:23;
+152B:2B;
+152C:23;
+152D:2B;
+152E:23;
+152F:00;
+1530:3E;
+1531:00;
+1532:DB;
+1533:11;
+1534:ED;
+1535:78;
+1536:F2;
+1537:34;
+1538:55;
+1539:2B;
+153A:23;
+153B:2B;
+153C:23;
+153D:2B;
+153E:23;
+153F:00;
+1540:3E;
+1541:00;
+1542:DB;
+1543:11;
+1544:47;
+1545:ED;
+1546:78;
+1547:F2;
+1548:45;
+1549:55;
+154A:78;
+154B:FE;
+154C:FE;
+154D:C2;
+154E:31;
+154F:54;
+1550:00;
+1551:00;
+1552:00;
+1553:3E;
+1554:00;
+1555:3E;
+1556:00;
+1557:DB;
+1558:11;
+1559:ED;
+155A:78;
+155B:F2;
+155C:59;
+155D:55;
+155E:2B;
+155F:23;
+1560:2B;
+1561:23;
+1562:2B;
+1563:23;
+1564:00;
+1565:3E;
+1566:00;
+1567:DB;
+1568:11;
+1569:ED;
+156A:78;
+156B:F2;
+156C:69;
+156D:55;
+156E:2B;
+156F:23;
+1570:2B;
+1571:23;
+1572:2B;
+1573:23;
+1574:00;
+1575:3E;
+1576:00;
+1577:DB;
+1578:11;
+1579:ED;
+157A:78;
+157B:F2;
+157C:79;
+157D:55;
+157E:2B;
+157F:23;
+1580:2B;
+1581:23;
+1582:2B;
+1583:23;
+1584:00;
+1585:3E;
+1586:00;
+1587:DB;
+1588:11;
+1589:ED;
+158A:78;
+158B:F2;
+158C:89;
+158D:55;
+158E:2B;
+158F:23;
+1590:2B;
+1591:23;
+1592:2B;
+1593:23;
+1594:00;
+1595:3E;
+1596:00;
+1597:DB;
+1598:11;
+1599:ED;
+159A:78;
+159B:F2;
+159C:99;
+159D:55;
+159E:2B;
+159F:23;
+15A0:2B;
+15A1:23;
+15A2:2B;
+15A3:23;
+15A4:00;
+15A5:3E;
+15A6:00;
+15A7:DB;
+15A8:11;
+15A9:ED;
+15AA:78;
+15AB:F2;
+15AC:A9;
+15AD:55;
+15AE:2B;
+15AF:23;
+15B0:2B;
+15B1:23;
+15B2:2B;
+15B3:23;
+15B4:00;
+15B5:3E;
+15B6:00;
+15B7:DB;
+15B8:11;
+15B9:ED;
+15BA:78;
+15BB:F2;
+15BC:B9;
+15BD:55;
+15BE:2B;
+15BF:23;
+15C0:2B;
+15C1:23;
+15C2:2B;
+15C3:23;
+15C4:00;
+15C5:3E;
+15C6:00;
+15C7:DB;
+15C8:11;
+15C9:47;
+15CA:ED;
+15CB:78;
+15CC:F2;
+15CD:CA;
+15CE:55;
+15CF:78;
+15D0:FE;
+15D1:E7;
+15D2:C2;
+15D3:31;
+15D4:54;
+15D5:00;
+15D6:00;
+15D7:00;
+15D8:3E;
+15D9:00;
+15DA:3E;
+15DB:00;
+15DC:DB;
+15DD:11;
+15DE:ED;
+15DF:78;
+15E0:F2;
+15E1:DE;
+15E2:55;
+15E3:2B;
+15E4:23;
+15E5:2B;
+15E6:23;
+15E7:2B;
+15E8:23;
+15E9:00;
+15EA:3E;
+15EB:00;
+15EC:DB;
+15ED:11;
+15EE:ED;
+15EF:78;
+15F0:F2;
+15F1:EE;
+15F2:55;
+15F3:2B;
+15F4:23;
+15F5:2B;
+15F6:23;
+15F7:2B;
+15F8:23;
+15F9:00;
+15FA:3E;
+15FB:00;
+15FC:DB;
+15FD:11;
+15FE:ED;
+15FF:78;
+1600:F2;
+1601:FE;
+1602:55;
+1603:2B;
+1604:23;
+1605:2B;
+1606:23;
+1607:2B;
+1608:23;
+1609:00;
+160A:3E;
+160B:00;
+160C:DB;
+160D:11;
+160E:ED;
+160F:78;
+1610:F2;
+1611:0E;
+1612:56;
+1613:2B;
+1614:23;
+1615:2B;
+1616:23;
+1617:2B;
+1618:23;
+1619:00;
+161A:3E;
+161B:00;
+161C:DB;
+161D:11;
+161E:ED;
+161F:78;
+1620:F2;
+1621:1E;
+1622:56;
+1623:2B;
+1624:23;
+1625:2B;
+1626:23;
+1627:2B;
+1628:23;
+1629:00;
+162A:3E;
+162B:00;
+162C:DB;
+162D:11;
+162E:ED;
+162F:78;
+1630:F2;
+1631:2E;
+1632:56;
+1633:2B;
+1634:23;
+1635:2B;
+1636:23;
+1637:2B;
+1638:23;
+1639:00;
+163A:3E;
+163B:00;
+163C:DB;
+163D:11;
+163E:ED;
+163F:78;
+1640:F2;
+1641:3E;
+1642:56;
+1643:2B;
+1644:23;
+1645:2B;
+1646:23;
+1647:2B;
+1648:23;
+1649:00;
+164A:3E;
+164B:00;
+164C:DB;
+164D:11;
+164E:47;
+164F:ED;
+1650:78;
+1651:F2;
+1652:4F;
+1653:56;
+1654:78;
+1655:FE;
+1656:18;
+1657:C2;
+1658:31;
+1659:54;
+165A:00;
+165B:00;
+165C:00;
+165D:3E;
+165E:00;
+165F:3E;
+1660:00;
+1661:DB;
+1662:11;
+1663:ED;
+1664:78;
+1665:F2;
+1666:63;
+1667:56;
+1668:2B;
+1669:23;
+166A:2B;
+166B:23;
+166C:2B;
+166D:23;
+166E:00;
+166F:3E;
+1670:00;
+1671:3E;
+1672:00;
+1673:DB;
+1674:11;
+1675:ED;
+1676:78;
+1677:F2;
+1678:73;
+1679:56;
+167A:2B;
+167B:23;
+167C:2B;
+167D:23;
+167E:2B;
+167F:23;
+1680:00;
+1681:3E;
+1682:00;
+1683:DB;
+1684:11;
+1685:ED;
+1686:78;
+1687:F2;
+1688:83;
+1689:56;
+168A:2B;
+168B:23;
+168C:2B;
+168D:23;
+168E:2B;
+168F:23;
+1690:00;
+1691:DB;
+1692:11;
+1693:ED;
+1694:78;
+1695:F2;
+1696:93;
+1697:56;
+1698:2B;
+1699:23;
+169A:2B;
+169B:23;
+169C:2B;
+169D:23;
+169E:00;
+169F:3E;
+16A0:00;
+16A1:DB;
+16A2:11;
+16A3:ED;
+16A4:78;
+16A5:F2;
+16A6:A3;
+16A7:56;
+16A8:2B;
+16A9:23;
+16AA:2B;
+16AB:23;
+16AC:2B;
+16AD:23;
+16AE:00;
+16AF:3E;
+16B0:00;
+16B1:DB;
+16B2:11;
+16B3:ED;
+16B4:78;
+16B5:F2;
+16B6:B3;
+16B7:56;
+16B8:2B;
+16B9:23;
+16BA:2B;
+16BB:23;
+16BC:2B;
+16BD:23;
+16BE:00;
+16BF:3E;
+16C0:00;
+16C1:DB;
+16C2:11;
+16C3:ED;
+16C4:78;
+16C5:F2;
+16C6:C3;
+16C7:56;
+16C8:2B;
+16C9:23;
+16CA:2B;
+16CB:23;
+16CC:2B;
+16CD:23;
+16CE:00;
+16CF:3E;
+16D0:00;
+16D1:DB;
+16D2:11;
+16D3:47;
+16D4:ED;
+16D5:78;
+16D6:F2;
+16D7:D4;
+16D8:56;
+16D9:78;
+16DA:FE;
+16DB:C3;
+16DC:C2;
+16DD:31;
+16DE:54;
+16DF:00;
+16E0:00;
+16E1:00;
+16E2:3E;
+16E3:00;
+16E4:3E;
+16E5:00;
+16E6:DB;
+16E7:11;
+16E8:ED;
+16E9:78;
+16EA:F2;
+16EB:E8;
+16EC:56;
+16ED:2B;
+16EE:23;
+16EF:2B;
+16F0:23;
+16F1:2B;
+16F2:23;
+16F3:00;
+16F4:3E;
+16F5:00;
+16F6:DB;
+16F7:11;
+16F8:ED;
+16F9:78;
+16FA:F2;
+16FB:F8;
+16FC:56;
+16FD:2B;
+16FE:23;
+16FF:2B;
+1700:23;
+1701:2B;
+1702:23;
+1703:00;
+1704:3E;
+1705:00;
+1706:DB;
+1707:11;
+1708:ED;
+1709:78;
+170A:F2;
+170B:08;
+170C:57;
+170D:2B;
+170E:23;
+170F:2B;
+1710:23;
+1711:2B;
+1712:23;
+1713:00;
+1714:3E;
+1715:00;
+1716:DB;
+1717:11;
+1718:ED;
+1719:78;
+171A:F2;
+171B:18;
+171C:57;
+171D:2B;
+171E:23;
+171F:2B;
+1720:23;
+1721:2B;
+1722:23;
+1723:00;
+1724:3E;
+1725:00;
+1726:DB;
+1727:11;
+1728:ED;
+1729:78;
+172A:F2;
+172B:28;
+172C:57;
+172D:2B;
+172E:23;
+172F:2B;
+1730:23;
+1731:2B;
+1732:23;
+1733:00;
+1734:3E;
+1735:00;
+1736:DB;
+1737:11;
+1738:ED;
+1739:78;
+173A:F2;
+173B:38;
+173C:57;
+173D:2B;
+173E:23;
+173F:2B;
+1740:23;
+1741:2B;
+1742:23;
+1743:00;
+1744:3E;
+1745:00;
+1746:DB;
+1747:11;
+1748:ED;
+1749:78;
+174A:F2;
+174B:48;
+174C:57;
+174D:FD;
+174E:7E;
+174F:12;
+1750:47;
+1751:00;
+1752:C3;
+1753:55;
+1754:57;
+1755:C3;
+1756:58;
+1757:57;
+1758:DB;
+1759:11;
+175A:08;
+175B:ED;
+175C:78;
+175D:F2;
+175E:5B;
+175F:57;
+1760:08;
+1761:B8;
+1762:CA;
+1763:6C;
+1764:57;
+1765:2D;
+1766:C2;
+1767:FB;
+1768:53;
+1769:C3;
+176A:F0;
+176B:53;
+176C:00;
+176D:00;
+176E:00;
+176F:C3;
+1770:72;
+1771:57;
+1772:3E;
+1773:00;
+1774:DB;
+1775:11;
+1776:ED;
+1777:78;
+1778:F2;
+1779:76;
+177A:57;
+177B:2B;
+177C:23;
+177D:2B;
+177E:23;
+177F:2B;
+1780:23;
+1781:00;
+1782:3E;
+1783:00;
+1784:DB;
+1785:11;
+1786:ED;
+1787:78;
+1788:F2;
+1789:86;
+178A:57;
+178B:2B;
+178C:23;
+178D:2B;
+178E:23;
+178F:2B;
+1790:23;
+1791:00;
+1792:3E;
+1793:00;
+1794:DB;
+1795:11;
+1796:ED;
+1797:78;
+1798:F2;
+1799:96;
+179A:57;
+179B:2B;
+179C:23;
+179D:2B;
+179E:23;
+179F:2B;
+17A0:23;
+17A1:00;
+17A2:3E;
+17A3:00;
+17A4:DB;
+17A5:11;
+17A6:ED;
+17A7:78;
+17A8:F2;
+17A9:A6;
+17AA:57;
+17AB:2B;
+17AC:23;
+17AD:2B;
+17AE:23;
+17AF:2B;
+17B0:23;
+17B1:00;
+17B2:3E;
+17B3:00;
+17B4:DB;
+17B5:11;
+17B6:ED;
+17B7:78;
+17B8:F2;
+17B9:B6;
+17BA:57;
+17BB:2B;
+17BC:23;
+17BD:2B;
+17BE:23;
+17BF:2B;
+17C0:23;
+17C1:00;
+17C2:3E;
+17C3:00;
+17C4:DB;
+17C5:11;
+17C6:ED;
+17C7:78;
+17C8:F2;
+17C9:C6;
+17CA:57;
+17CB:2B;
+17CC:23;
+17CD:2B;
+17CE:23;
+17CF:2B;
+17D0:23;
+17D1:00;
+17D2:3E;
+17D3:00;
+17D4:DB;
+17D5:11;
+17D6:ED;
+17D7:78;
+17D8:F2;
+17D9:D6;
+17DA:57;
+17DB:FD;
+17DC:7E;
+17DD:11;
+17DE:47;
+17DF:00;
+17E0:C3;
+17E1:E3;
+17E2:57;
+17E3:C3;
+17E4:E6;
+17E5:57;
+17E6:DB;
+17E7:11;
+17E8:08;
+17E9:ED;
+17EA:78;
+17EB:F2;
+17EC:E9;
+17ED:57;
+17EE:08;
+17EF:B8;
+17F0:CA;
+17F1:FB;
+17F2:57;
+17F3:25;
+17F4:C2;
+17F5:31;
+17F6:54;
+17F7:3E;
+17F8:09;
+17F9:B7;
+17FA:C9;
+17FB:00;
+17FC:00;
+17FD:00;
+17FE:C3;
+17FF:01;
+1800:58;
+1801:3E;
+1802:00;
+1803:DB;
+1804:11;
+1805:ED;
+1806:78;
+1807:F2;
+1808:05;
+1809:58;
+180A:2B;
+180B:23;
+180C:2B;
+180D:23;
+180E:2B;
+180F:23;
+1810:00;
+1811:3E;
+1812:00;
+1813:DB;
+1814:11;
+1815:ED;
+1816:78;
+1817:F2;
+1818:15;
+1819:58;
+181A:2B;
+181B:23;
+181C:2B;
+181D:23;
+181E:2B;
+181F:23;
+1820:00;
+1821:3E;
+1822:00;
+1823:DB;
+1824:11;
+1825:ED;
+1826:78;
+1827:F2;
+1828:25;
+1829:58;
+182A:2B;
+182B:23;
+182C:2B;
+182D:23;
+182E:2B;
+182F:23;
+1830:00;
+1831:3E;
+1832:00;
+1833:DB;
+1834:11;
+1835:ED;
+1836:78;
+1837:F2;
+1838:35;
+1839:58;
+183A:2B;
+183B:23;
+183C:2B;
+183D:23;
+183E:2B;
+183F:23;
+1840:00;
+1841:3E;
+1842:00;
+1843:DB;
+1844:11;
+1845:ED;
+1846:78;
+1847:F2;
+1848:45;
+1849:58;
+184A:2B;
+184B:23;
+184C:2B;
+184D:23;
+184E:2B;
+184F:23;
+1850:00;
+1851:3E;
+1852:00;
+1853:DB;
+1854:11;
+1855:ED;
+1856:78;
+1857:F2;
+1858:55;
+1859:58;
+185A:2B;
+185B:23;
+185C:2B;
+185D:23;
+185E:2B;
+185F:23;
+1860:00;
+1861:3E;
+1862:00;
+1863:DB;
+1864:11;
+1865:ED;
+1866:78;
+1867:F2;
+1868:65;
+1869:58;
+186A:2B;
+186B:23;
+186C:2B;
+186D:23;
+186E:2B;
+186F:23;
+1870:00;
+1871:3E;
+1872:00;
+1873:DB;
+1874:11;
+1875:BA;
+1876:C2;
+1877:31;
+1878:54;
+1879:AF;
+187A:C9;
+187B:CD;
+187C:13;
+187D:59;
+187E:FE;
+187F:0D;
+1880:28;
+1881:02;
+1882:B7;
+1883:C0;
+1884:CD;
+1885:68;
+1886:59;
+1887:B7;
+1888:C0;
+1889:FD;
+188A:56;
+188B:11;
+188C:D5;
+188D:E5;
+188E:CD;
+188F:BF;
+1890:58;
+1891:E1;
+1892:D1;
+1893:B7;
+1894:C0;
+1895:FD;
+1896:72;
+1897:11;
+1898:E5;
+1899:CD;
+189A:27;
+189B:5B;
+189C:E1;
+189D:B7;
+189E:C0;
+189F:EB;
+18A0:FD;
+18A1:7E;
+18A2:09;
+18A3:12;
+18A4:13;
+18A5:3E;
+18A6:3A;
+18A7:12;
+18A8:13;
+18A9:FD;
+18AA:E5;
+18AB:E1;
+18AC:23;
+18AD:01;
+18AE:08;
+18AF:00;
+18B0:ED;
+18B1:B0;
+18B2:FD;
+18B3:7E;
+18B4:16;
+18B5:12;
+18B6:13;
+18B7:FD;
+18B8:7E;
+18B9:15;
+18BA:12;
+18BB:CD;
+18BC:A1;
+18BD:59;
+18BE:C9;
+18BF:FD;
+18C0:36;
+18C1:16;
+18C2:01;
+18C3:FD;
+18C4:36;
+18C5:15;
+18C6:00;
+18C7:FD;
+18C8:6E;
+18C9:34;
+18CA:FD;
+18CB:66;
+18CC:35;
+18CD:2B;
+18CE:23;
+18CF:4E;
+18D0:CB;
+18D1:09;
+18D2:30;
+18D3:2B;
+18D4:FD;
+18D5:34;
+18D6:15;
+18D7:FD;
+18D8:7E;
+18D9:15;
+18DA:FE;
+18DB:08;
+18DC:20;
+18DD:F2;
+18DE:23;
+18DF:4E;
+18E0:CB;
+18E1:09;
+18E2:30;
+18E3:1B;
+18E4:FD;
+18E5:34;
+18E6:15;
+18E7:FD;
+18E8:7E;
+18E9:15;
+18EA:FE;
+18EB:10;
+18EC:20;
+18ED:F2;
+18EE:FD;
+18EF:36;
+18F0:15;
+18F1:00;
+18F2:FD;
+18F3:34;
+18F4:16;
+18F5:FD;
+18F6:7E;
+18F7:16;
+18F8:FE;
+18F9:28;
+18FA:20;
+18FB:D2;
+18FC:3E;
+18FD:07;
+18FE:C9;
+18FF:CB;
+1900:01;
+1901:CB;
+1902:C1;
+1903:FD;
+1904:7E;
+1905:15;
+1906:E6;
+1907:07;
+1908:3C;
+1909:47;
+190A:CB;
+190B:09;
+190C:CB;
+190D:01;
+190E:10;
+190F:FC;
+1910:71;
+1911:AF;
+1912:C9;
+1913:FD;
+1914:6E;
+1915:31;
+1916:FD;
+1917:66;
+1918:32;
+1919:FD;
+191A:36;
+191B:12;
+191C:00;
+191D:FD;
+191E:36;
+191F:11;
+1920:00;
+1921:CD;
+1922:27;
+1923:5B;
+1924:B7;
+1925:C2;
+1926:41;
+1927:42;
+1928:06;
+1929:08;
+192A:FD;
+192B:6E;
+192C:31;
+192D:FD;
+192E:66;
+192F:32;
+1930:FD;
+1931:E5;
+1932:D1;
+1933:13;
+1934:7E;
+1935:B7;
+1936:C8;
+1937:D5;
+1938:E5;
+1939:FE;
+193A:01;
+193B:28;
+193C:16;
+193D:FD;
+193E:77;
+193F:0A;
+1940:23;
+1941:23;
+1942:0E;
+1943:08;
+1944:EB;
+1945:1A;
+1946:BE;
+1947:20;
+1948:0A;
+1949:23;
+194A:13;
+194B:0D;
+194C:20;
+194D:F7;
+194E:F1;
+194F:F1;
+1950:3E;
+1951:02;
+1952:C9;
+1953:E1;
+1954:11;
+1955:10;
+1956:00;
+1957:19;
+1958:D1;
+1959:10;
+195A:D9;
+195B:FD;
+195C:34;
+195D:11;
+195E:FD;
+195F:7E;
+1960:11;
+1961:FE;
+1962:0F;
+1963:20;
+1964:BC;
+1965:3E;
+1966:0D;
+1967:C9;
+1968:FD;
+1969:6E;
+196A:31;
+196B:FD;
+196C:66;
+196D:32;
+196E:FD;
+196F:36;
+1970:12;
+1971:00;
+1972:FD;
+1973:36;
+1974:11;
+1975:00;
+1976:CD;
+1977:27;
+1978:5B;
+1979:B7;
+197A:C2;
+197B:41;
+197C:42;
+197D:06;
+197E:08;
+197F:FD;
+1980:6E;
+1981:31;
+1982:FD;
+1983:66;
+1984:32;
+1985:7E;
+1986:B7;
+1987:C8;
+1988:FE;
+1989:01;
+198A:20;
+198B:02;
+198C:AF;
+198D:C9;
+198E:11;
+198F:10;
+1990:00;
+1991:19;
+1992:10;
+1993:F1;
+1994:FD;
+1995:34;
+1996:11;
+1997:FD;
+1998:7E;
+1999:11;
+199A:FE;
+199B:0F;
+199C:20;
+199D:D8;
+199E:3E;
+199F:03;
+19A0:C9;
+19A1:CD;
+19A2:10;
+19A3:5B;
+19A4:D5;
+19A5:FD;
+19A6:E5;
+19A7:E1;
+19A8:11;
+19A9:CD;
+19AA:00;
+19AB:19;
+19AC:D1;
+19AD:73;
+19AE:23;
+19AF:72;
+19B0:FD;
+19B1:E5;
+19B2:E1;
+19B3:11;
+19B4:43;
+19B5:00;
+19B6:19;
+19B7:06;
+19B8:8C;
+19B9:D9;
+19BA:CD;
+19BB:EA;
+19BC:53;
+19BD:CA;
+19BE:C6;
+19BF:59;
+19C0:FE;
+19C1:11;
+19C2:C8;
+19C3:3E;
+19C4:09;
+19C5:C9;
+19C6:D9;
+19C7:FD;
+19C8:56;
+19C9:33;
+19CA:CB;
+19CB:B2;
+19CC:7A;
+19CD:D3;
+19CE:10;
+19CF:4E;
+19D0:3E;
+19D1:20;
+19D2:AA;
+19D3:CB;
+19D4:11;
+19D5:D2;
+19D6:E3;
+19D7:59;
+19D8:D3;
+19D9:10;
+19DA:EE;
+19DB:20;
+19DC:57;
+19DD:2B;
+19DE:D3;
+19DF:10;
+19E0:C3;
+19E1:EE;
+19E2:59;
+19E3:D3;
+19E4:10;
+19E5:EE;
+19E6:00;
+19E7:57;
+19E8:2B;
+19E9:D3;
+19EA:10;
+19EB:C3;
+19EC:EE;
+19ED:59;
+19EE:23;
+19EF:C3;
+19F0:F2;
+19F1:59;
+19F2:C3;
+19F3:F5;
+19F4:59;
+19F5:DB;
+19F6:12;
+19F7:3E;
+19F8:20;
+19F9:AA;
+19FA:CB;
+19FB:11;
+19FC:D2;
+19FD:0A;
+19FE:5A;
+19FF:D3;
+1A00:10;
+1A01:EE;
+1A02:20;
+1A03:57;
+1A04:2B;
+1A05:D3;
+1A06:10;
+1A07:C3;
+1A08:15;
+1A09:5A;
+1A0A:D3;
+1A0B:10;
+1A0C:EE;
+1A0D:00;
+1A0E:57;
+1A0F:2B;
+1A10:D3;
+1A11:10;
+1A12:C3;
+1A13:15;
+1A14:5A;
+1A15:23;
+1A16:C3;
+1A17:19;
+1A18:5A;
+1A19:C3;
+1A1A:1C;
+1A1B:5A;
+1A1C:DB;
+1A1D:12;
+1A1E:3E;
+1A1F:20;
+1A20:AA;
+1A21:CB;
+1A22:11;
+1A23:D2;
+1A24:31;
+1A25:5A;
+1A26:D3;
+1A27:10;
+1A28:EE;
+1A29:20;
+1A2A:57;
+1A2B:2B;
+1A2C:D3;
+1A2D:10;
+1A2E:C3;
+1A2F:3C;
+1A30:5A;
+1A31:D3;
+1A32:10;
+1A33:EE;
+1A34:00;
+1A35:57;
+1A36:2B;
+1A37:D3;
+1A38:10;
+1A39:C3;
+1A3A:3C;
+1A3B:5A;
+1A3C:23;
+1A3D:C3;
+1A3E:40;
+1A3F:5A;
+1A40:C3;
+1A41:43;
+1A42:5A;
+1A43:DB;
+1A44:12;
+1A45:3E;
+1A46:20;
+1A47:AA;
+1A48:CB;
+1A49:11;
+1A4A:D2;
+1A4B:58;
+1A4C:5A;
+1A4D:D3;
+1A4E:10;
+1A4F:EE;
+1A50:20;
+1A51:57;
+1A52:2B;
+1A53:D3;
+1A54:10;
+1A55:C3;
+1A56:63;
+1A57:5A;
+1A58:D3;
+1A59:10;
+1A5A:EE;
+1A5B:00;
+1A5C:57;
+1A5D:2B;
+1A5E:D3;
+1A5F:10;
+1A60:C3;
+1A61:63;
+1A62:5A;
+1A63:23;
+1A64:C3;
+1A65:67;
+1A66:5A;
+1A67:C3;
+1A68:6A;
+1A69:5A;
+1A6A:DB;
+1A6B:12;
+1A6C:3E;
+1A6D:20;
+1A6E:AA;
+1A6F:CB;
+1A70:11;
+1A71:D2;
+1A72:7F;
+1A73:5A;
+1A74:D3;
+1A75:10;
+1A76:EE;
+1A77:20;
+1A78:57;
+1A79:2B;
+1A7A:D3;
+1A7B:10;
+1A7C:C3;
+1A7D:8A;
+1A7E:5A;
+1A7F:D3;
+1A80:10;
+1A81:EE;
+1A82:00;
+1A83:57;
+1A84:2B;
+1A85:D3;
+1A86:10;
+1A87:C3;
+1A88:8A;
+1A89:5A;
+1A8A:23;
+1A8B:C3;
+1A8C:8E;
+1A8D:5A;
+1A8E:C3;
+1A8F:91;
+1A90:5A;
+1A91:DB;
+1A92:12;
+1A93:3E;
+1A94:20;
+1A95:AA;
+1A96:CB;
+1A97:11;
+1A98:D2;
+1A99:A6;
+1A9A:5A;
+1A9B:D3;
+1A9C:10;
+1A9D:EE;
+1A9E:20;
+1A9F:57;
+1AA0:2B;
+1AA1:D3;
+1AA2:10;
+1AA3:C3;
+1AA4:B1;
+1AA5:5A;
+1AA6:D3;
+1AA7:10;
+1AA8:EE;
+1AA9:00;
+1AAA:57;
+1AAB:2B;
+1AAC:D3;
+1AAD:10;
+1AAE:C3;
+1AAF:B1;
+1AB0:5A;
+1AB1:23;
+1AB2:C3;
+1AB3:B5;
+1AB4:5A;
+1AB5:C3;
+1AB6:B8;
+1AB7:5A;
+1AB8:DB;
+1AB9:12;
+1ABA:3E;
+1ABB:20;
+1ABC:AA;
+1ABD:CB;
+1ABE:11;
+1ABF:D2;
+1AC0:CD;
+1AC1:5A;
+1AC2:D3;
+1AC3:10;
+1AC4:EE;
+1AC5:20;
+1AC6:57;
+1AC7:2B;
+1AC8:D3;
+1AC9:10;
+1ACA:C3;
+1ACB:D8;
+1ACC:5A;
+1ACD:D3;
+1ACE:10;
+1ACF:EE;
+1AD0:00;
+1AD1:57;
+1AD2:2B;
+1AD3:D3;
+1AD4:10;
+1AD5:C3;
+1AD6:D8;
+1AD7:5A;
+1AD8:23;
+1AD9:C3;
+1ADA:DC;
+1ADB:5A;
+1ADC:C3;
+1ADD:DF;
+1ADE:5A;
+1ADF:DB;
+1AE0:12;
+1AE1:3E;
+1AE2:20;
+1AE3:AA;
+1AE4:CB;
+1AE5:11;
+1AE6:D2;
+1AE7:F4;
+1AE8:5A;
+1AE9:D3;
+1AEA:10;
+1AEB:EE;
+1AEC:20;
+1AED:57;
+1AEE:2B;
+1AEF:D3;
+1AF0:10;
+1AF1:C3;
+1AF2:FF;
+1AF3:5A;
+1AF4:D3;
+1AF5:10;
+1AF6:EE;
+1AF7:00;
+1AF8:57;
+1AF9:2B;
+1AFA:D3;
+1AFB:10;
+1AFC:C3;
+1AFD:FF;
+1AFE:5A;
+1AFF:23;
+1B00:23;
+1B01:00;
+1B02:05;
+1B03:C2;
+1B04:CF;
+1B05:59;
+1B06:CB;
+1B07:F2;
+1B08:7A;
+1B09:D3;
+1B0A:10;
+1B0B:FD;
+1B0C:77;
+1B0D:33;
+1B0E:AF;
+1B0F:C9;
+1B10:FD;
+1B11:E5;
+1B12:E1;
+1B13:11;
+1B14:4D;
+1B15:00;
+1B16:19;
+1B17:5E;
+1B18:16;
+1B19:00;
+1B1A:06;
+1B1B:7F;
+1B1C:23;
+1B1D:7B;
+1B1E:86;
+1B1F:5F;
+1B20:3E;
+1B21:00;
+1B22:8A;
+1B23:57;
+1B24:10;
+1B25:F6;
+1B26:C9;
+1B27:FD;
+1B28:36;
+1B29:13;
+1B2A:0A;
+1B2B:CD;
+1B2C:EA;
+1B2D:53;
+1B2E:CA;
+1B2F:37;
+1B30:5B;
+1B31:FE;
+1B32:11;
+1B33:C8;
+1B34:3E;
+1B35:09;
+1B36:C9;
+1B37:FD;
+1B38:E5;
+1B39:E1;
+1B3A:11;
+1B3B:4C;
+1B3C:00;
+1B3D:19;
+1B3E:1E;
+1B3F:83;
+1B40:18;
+1B41:03;
+1B42:C3;
+1B43:A4;
+1B44:5E;
+1B45:DB;
+1B46:11;
+1B47:ED;
+1B48:78;
+1B49:F2;
+1B4A:47;
+1B4B:5B;
+1B4C:00;
+1B4D:00;
+1B4E:00;
+1B4F:00;
+1B50:3A;
+1B51:DF;
+1B52:68;
+1B53:E6;
+1B54:04;
+1B55:28;
+1B56:EB;
+1B57:DB;
+1B58:11;
+1B59:47;
+1B5A:ED;
+1B5B:78;
+1B5C:F2;
+1B5D:5A;
+1B5E:5B;
+1B5F:78;
+1B60:FE;
+1B61:80;
+1B62:C2;
+1B63:50;
+1B64:5B;
+1B65:00;
+1B66:00;
+1B67:00;
+1B68:3E;
+1B69:00;
+1B6A:3E;
+1B6B:00;
+1B6C:DB;
+1B6D:11;
+1B6E:ED;
+1B6F:78;
+1B70:F2;
+1B71:6E;
+1B72:5B;
+1B73:2B;
+1B74:23;
+1B75:2B;
+1B76:23;
+1B77:2B;
+1B78:23;
+1B79:00;
+1B7A:3E;
+1B7B:00;
+1B7C:DB;
+1B7D:11;
+1B7E:ED;
+1B7F:78;
+1B80:F2;
+1B81:7E;
+1B82:5B;
+1B83:2B;
+1B84:23;
+1B85:2B;
+1B86:23;
+1B87:2B;
+1B88:23;
+1B89:00;
+1B8A:3E;
+1B8B:00;
+1B8C:DB;
+1B8D:11;
+1B8E:ED;
+1B8F:78;
+1B90:F2;
+1B91:8E;
+1B92:5B;
+1B93:2B;
+1B94:23;
+1B95:2B;
+1B96:23;
+1B97:2B;
+1B98:23;
+1B99:00;
+1B9A:3E;
+1B9B:00;
+1B9C:DB;
+1B9D:11;
+1B9E:ED;
+1B9F:78;
+1BA0:F2;
+1BA1:9E;
+1BA2:5B;
+1BA3:2B;
+1BA4:23;
+1BA5:2B;
+1BA6:23;
+1BA7:2B;
+1BA8:23;
+1BA9:00;
+1BAA:3E;
+1BAB:00;
+1BAC:DB;
+1BAD:11;
+1BAE:ED;
+1BAF:78;
+1BB0:F2;
+1BB1:AE;
+1BB2:5B;
+1BB3:2B;
+1BB4:23;
+1BB5:2B;
+1BB6:23;
+1BB7:2B;
+1BB8:23;
+1BB9:00;
+1BBA:3E;
+1BBB:00;
+1BBC:DB;
+1BBD:11;
+1BBE:ED;
+1BBF:78;
+1BC0:F2;
+1BC1:BE;
+1BC2:5B;
+1BC3:2B;
+1BC4:23;
+1BC5:2B;
+1BC6:23;
+1BC7:2B;
+1BC8:23;
+1BC9:00;
+1BCA:3E;
+1BCB:00;
+1BCC:DB;
+1BCD:11;
+1BCE:ED;
+1BCF:78;
+1BD0:F2;
+1BD1:CE;
+1BD2:5B;
+1BD3:2B;
+1BD4:23;
+1BD5:2B;
+1BD6:23;
+1BD7:2B;
+1BD8:23;
+1BD9:00;
+1BDA:3E;
+1BDB:00;
+1BDC:DB;
+1BDD:11;
+1BDE:47;
+1BDF:ED;
+1BE0:78;
+1BE1:F2;
+1BE2:DF;
+1BE3:5B;
+1BE4:78;
+1BE5:FE;
+1BE6:80;
+1BE7:CA;
+1BE8:65;
+1BE9:5B;
+1BEA:00;
+1BEB:00;
+1BEC:00;
+1BED:3E;
+1BEE:00;
+1BEF:3E;
+1BF0:00;
+1BF1:DB;
+1BF2:11;
+1BF3:ED;
+1BF4:78;
+1BF5:F2;
+1BF6:F3;
+1BF7:5B;
+1BF8:2B;
+1BF9:23;
+1BFA:2B;
+1BFB:23;
+1BFC:2B;
+1BFD:23;
+1BFE:00;
+1BFF:3E;
+1C00:00;
+1C01:DB;
+1C02:11;
+1C03:ED;
+1C04:78;
+1C05:F2;
+1C06:03;
+1C07:5C;
+1C08:2B;
+1C09:23;
+1C0A:2B;
+1C0B:23;
+1C0C:2B;
+1C0D:23;
+1C0E:00;
+1C0F:3E;
+1C10:00;
+1C11:DB;
+1C12:11;
+1C13:ED;
+1C14:78;
+1C15:F2;
+1C16:13;
+1C17:5C;
+1C18:2B;
+1C19:23;
+1C1A:2B;
+1C1B:23;
+1C1C:2B;
+1C1D:23;
+1C1E:00;
+1C1F:3E;
+1C20:00;
+1C21:DB;
+1C22:11;
+1C23:ED;
+1C24:78;
+1C25:F2;
+1C26:23;
+1C27:5C;
+1C28:2B;
+1C29:23;
+1C2A:2B;
+1C2B:23;
+1C2C:2B;
+1C2D:23;
+1C2E:00;
+1C2F:3E;
+1C30:00;
+1C31:DB;
+1C32:11;
+1C33:ED;
+1C34:78;
+1C35:F2;
+1C36:33;
+1C37:5C;
+1C38:2B;
+1C39:23;
+1C3A:2B;
+1C3B:23;
+1C3C:2B;
+1C3D:23;
+1C3E:00;
+1C3F:3E;
+1C40:00;
+1C41:DB;
+1C42:11;
+1C43:ED;
+1C44:78;
+1C45:F2;
+1C46:43;
+1C47:5C;
+1C48:2B;
+1C49:23;
+1C4A:2B;
+1C4B:23;
+1C4C:2B;
+1C4D:23;
+1C4E:00;
+1C4F:3E;
+1C50:00;
+1C51:DB;
+1C52:11;
+1C53:ED;
+1C54:78;
+1C55:F2;
+1C56:53;
+1C57:5C;
+1C58:2B;
+1C59:23;
+1C5A:2B;
+1C5B:23;
+1C5C:2B;
+1C5D:23;
+1C5E:00;
+1C5F:3E;
+1C60:00;
+1C61:DB;
+1C62:11;
+1C63:47;
+1C64:ED;
+1C65:78;
+1C66:F2;
+1C67:64;
+1C68:5C;
+1C69:78;
+1C6A:FE;
+1C6B:C3;
+1C6C:C2;
+1C6D:50;
+1C6E:5B;
+1C6F:00;
+1C70:00;
+1C71:00;
+1C72:3E;
+1C73:00;
+1C74:3E;
+1C75:00;
+1C76:DB;
+1C77:11;
+1C78:ED;
+1C79:78;
+1C7A:F2;
+1C7B:78;
+1C7C:5C;
+1C7D:2B;
+1C7E:23;
+1C7F:2B;
+1C80:23;
+1C81:2B;
+1C82:23;
+1C83:00;
+1C84:3E;
+1C85:00;
+1C86:DB;
+1C87:11;
+1C88:ED;
+1C89:78;
+1C8A:F2;
+1C8B:88;
+1C8C:5C;
+1C8D:2B;
+1C8E:23;
+1C8F:2B;
+1C90:23;
+1C91:2B;
+1C92:23;
+1C93:00;
+1C94:3E;
+1C95:00;
+1C96:DB;
+1C97:11;
+1C98:ED;
+1C99:78;
+1C9A:F2;
+1C9B:98;
+1C9C:5C;
+1C9D:2B;
+1C9E:23;
+1C9F:2B;
+1CA0:23;
+1CA1:2B;
+1CA2:23;
+1CA3:00;
+1CA4:3E;
+1CA5:00;
+1CA6:DB;
+1CA7:11;
+1CA8:ED;
+1CA9:78;
+1CAA:F2;
+1CAB:A8;
+1CAC:5C;
+1CAD:2B;
+1CAE:23;
+1CAF:2B;
+1CB0:23;
+1CB1:2B;
+1CB2:23;
+1CB3:00;
+1CB4:3E;
+1CB5:00;
+1CB6:DB;
+1CB7:11;
+1CB8:ED;
+1CB9:78;
+1CBA:F2;
+1CBB:B8;
+1CBC:5C;
+1CBD:2B;
+1CBE:23;
+1CBF:2B;
+1CC0:23;
+1CC1:2B;
+1CC2:23;
+1CC3:00;
+1CC4:3E;
+1CC5:00;
+1CC6:DB;
+1CC7:11;
+1CC8:ED;
+1CC9:78;
+1CCA:F2;
+1CCB:C8;
+1CCC:5C;
+1CCD:2B;
+1CCE:23;
+1CCF:2B;
+1CD0:23;
+1CD1:2B;
+1CD2:23;
+1CD3:00;
+1CD4:3E;
+1CD5:00;
+1CD6:DB;
+1CD7:11;
+1CD8:ED;
+1CD9:78;
+1CDA:F2;
+1CDB:D8;
+1CDC:5C;
+1CDD:2B;
+1CDE:23;
+1CDF:2B;
+1CE0:23;
+1CE1:2B;
+1CE2:23;
+1CE3:00;
+1CE4:3E;
+1CE5:00;
+1CE6:DB;
+1CE7:11;
+1CE8:47;
+1CE9:ED;
+1CEA:78;
+1CEB:F2;
+1CEC:E9;
+1CED:5C;
+1CEE:78;
+1CEF:FE;
+1CF0:18;
+1CF1:C2;
+1CF2:27;
+1CF3:5B;
+1CF4:00;
+1CF5:00;
+1CF6:00;
+1CF7:3E;
+1CF8:00;
+1CF9:3E;
+1CFA:00;
+1CFB:DB;
+1CFC:11;
+1CFD:ED;
+1CFE:78;
+1CFF:F2;
+1D00:FD;
+1D01:5C;
+1D02:2B;
+1D03:23;
+1D04:2B;
+1D05:23;
+1D06:2B;
+1D07:23;
+1D08:00;
+1D09:3E;
+1D0A:00;
+1D0B:DB;
+1D0C:11;
+1D0D:ED;
+1D0E:78;
+1D0F:F2;
+1D10:0D;
+1D11:5D;
+1D12:2B;
+1D13:23;
+1D14:2B;
+1D15:23;
+1D16:2B;
+1D17:23;
+1D18:00;
+1D19:3E;
+1D1A:00;
+1D1B:DB;
+1D1C:11;
+1D1D:ED;
+1D1E:78;
+1D1F:F2;
+1D20:1D;
+1D21:5D;
+1D22:2B;
+1D23:23;
+1D24:2B;
+1D25:23;
+1D26:2B;
+1D27:23;
+1D28:00;
+1D29:3E;
+1D2A:00;
+1D2B:DB;
+1D2C:11;
+1D2D:ED;
+1D2E:78;
+1D2F:F2;
+1D30:2D;
+1D31:5D;
+1D32:2B;
+1D33:23;
+1D34:2B;
+1D35:23;
+1D36:2B;
+1D37:23;
+1D38:00;
+1D39:3E;
+1D3A:00;
+1D3B:DB;
+1D3C:11;
+1D3D:ED;
+1D3E:78;
+1D3F:F2;
+1D40:3D;
+1D41:5D;
+1D42:2B;
+1D43:23;
+1D44:2B;
+1D45:23;
+1D46:2B;
+1D47:23;
+1D48:00;
+1D49:3E;
+1D4A:00;
+1D4B:DB;
+1D4C:11;
+1D4D:ED;
+1D4E:78;
+1D4F:F2;
+1D50:4D;
+1D51:5D;
+1D52:2B;
+1D53:23;
+1D54:2B;
+1D55:23;
+1D56:2B;
+1D57:23;
+1D58:00;
+1D59:3E;
+1D5A:00;
+1D5B:DB;
+1D5C:11;
+1D5D:ED;
+1D5E:78;
+1D5F:F2;
+1D60:5D;
+1D61:5D;
+1D62:2B;
+1D63:23;
+1D64:2B;
+1D65:23;
+1D66:2B;
+1D67:23;
+1D68:00;
+1D69:3E;
+1D6A:00;
+1D6B:DB;
+1D6C:11;
+1D6D:47;
+1D6E:ED;
+1D6F:78;
+1D70:F2;
+1D71:6E;
+1D72:5D;
+1D73:78;
+1D74:FE;
+1D75:E7;
+1D76:C2;
+1D77:27;
+1D78:5B;
+1D79:00;
+1D7A:00;
+1D7B:00;
+1D7C:3E;
+1D7D:00;
+1D7E:3E;
+1D7F:00;
+1D80:DB;
+1D81:11;
+1D82:ED;
+1D83:78;
+1D84:F2;
+1D85:82;
+1D86:5D;
+1D87:2B;
+1D88:23;
+1D89:2B;
+1D8A:23;
+1D8B:2B;
+1D8C:23;
+1D8D:00;
+1D8E:3E;
+1D8F:00;
+1D90:DB;
+1D91:11;
+1D92:ED;
+1D93:78;
+1D94:F2;
+1D95:92;
+1D96:5D;
+1D97:2B;
+1D98:23;
+1D99:2B;
+1D9A:23;
+1D9B:2B;
+1D9C:23;
+1D9D:00;
+1D9E:3E;
+1D9F:00;
+1DA0:DB;
+1DA1:11;
+1DA2:ED;
+1DA3:78;
+1DA4:F2;
+1DA5:A2;
+1DA6:5D;
+1DA7:2B;
+1DA8:23;
+1DA9:2B;
+1DAA:23;
+1DAB:2B;
+1DAC:23;
+1DAD:00;
+1DAE:3E;
+1DAF:00;
+1DB0:DB;
+1DB1:11;
+1DB2:ED;
+1DB3:78;
+1DB4:F2;
+1DB5:B2;
+1DB6:5D;
+1DB7:2B;
+1DB8:23;
+1DB9:2B;
+1DBA:23;
+1DBB:2B;
+1DBC:23;
+1DBD:00;
+1DBE:3E;
+1DBF:00;
+1DC0:DB;
+1DC1:11;
+1DC2:ED;
+1DC3:78;
+1DC4:F2;
+1DC5:C2;
+1DC6:5D;
+1DC7:2B;
+1DC8:23;
+1DC9:2B;
+1DCA:23;
+1DCB:2B;
+1DCC:23;
+1DCD:00;
+1DCE:3E;
+1DCF:00;
+1DD0:DB;
+1DD1:11;
+1DD2:ED;
+1DD3:78;
+1DD4:F2;
+1DD5:D2;
+1DD6:5D;
+1DD7:2B;
+1DD8:23;
+1DD9:2B;
+1DDA:23;
+1DDB:2B;
+1DDC:23;
+1DDD:00;
+1DDE:3E;
+1DDF:00;
+1DE0:DB;
+1DE1:11;
+1DE2:ED;
+1DE3:78;
+1DE4:F2;
+1DE5:E2;
+1DE6:5D;
+1DE7:2B;
+1DE8:23;
+1DE9:2B;
+1DEA:23;
+1DEB:2B;
+1DEC:23;
+1DED:00;
+1DEE:3E;
+1DEF:00;
+1DF0:DB;
+1DF1:11;
+1DF2:47;
+1DF3:ED;
+1DF4:78;
+1DF5:F2;
+1DF6:F3;
+1DF7:5D;
+1DF8:78;
+1DF9:FE;
+1DFA:FE;
+1DFB:C2;
+1DFC:27;
+1DFD:5B;
+1DFE:00;
+1DFF:00;
+1E00:00;
+1E01:3E;
+1E02:00;
+1E03:3E;
+1E04:00;
+1E05:DB;
+1E06:11;
+1E07:ED;
+1E08:78;
+1E09:F2;
+1E0A:07;
+1E0B:5E;
+1E0C:2B;
+1E0D:23;
+1E0E:2B;
+1E0F:23;
+1E10:2B;
+1E11:23;
+1E12:00;
+1E13:3E;
+1E14:00;
+1E15:DB;
+1E16:11;
+1E17:ED;
+1E18:78;
+1E19:F2;
+1E1A:17;
+1E1B:5E;
+1E1C:2B;
+1E1D:23;
+1E1E:2B;
+1E1F:23;
+1E20:2B;
+1E21:23;
+1E22:00;
+1E23:3E;
+1E24:00;
+1E25:DB;
+1E26:11;
+1E27:ED;
+1E28:78;
+1E29:F2;
+1E2A:27;
+1E2B:5E;
+1E2C:2B;
+1E2D:23;
+1E2E:2B;
+1E2F:23;
+1E30:2B;
+1E31:23;
+1E32:00;
+1E33:3E;
+1E34:00;
+1E35:DB;
+1E36:11;
+1E37:ED;
+1E38:78;
+1E39:F2;
+1E3A:37;
+1E3B:5E;
+1E3C:2B;
+1E3D:23;
+1E3E:2B;
+1E3F:23;
+1E40:2B;
+1E41:23;
+1E42:00;
+1E43:3E;
+1E44:00;
+1E45:DB;
+1E46:11;
+1E47:ED;
+1E48:78;
+1E49:F2;
+1E4A:47;
+1E4B:5E;
+1E4C:2B;
+1E4D:23;
+1E4E:2B;
+1E4F:23;
+1E50:2B;
+1E51:23;
+1E52:00;
+1E53:3E;
+1E54:00;
+1E55:DB;
+1E56:11;
+1E57:ED;
+1E58:78;
+1E59:F2;
+1E5A:57;
+1E5B:5E;
+1E5C:2B;
+1E5D:23;
+1E5E:2B;
+1E5F:23;
+1E60:2B;
+1E61:23;
+1E62:00;
+1E63:3E;
+1E64:00;
+1E65:DB;
+1E66:11;
+1E67:ED;
+1E68:78;
+1E69:F2;
+1E6A:67;
+1E6B:5E;
+1E6C:2B;
+1E6D:23;
+1E6E:2B;
+1E6F:23;
+1E70:2B;
+1E71:23;
+1E72:00;
+1E73:3E;
+1E74:00;
+1E75:DB;
+1E76:11;
+1E77:08;
+1E78:ED;
+1E79:78;
+1E7A:F2;
+1E7B:78;
+1E7C:5E;
+1E7D:23;
+1E7E:1D;
+1E7F:28;
+1E80:07;
+1E81:08;
+1E82:77;
+1E83:ED;
+1E84:5F;
+1E85:C3;
+1E86:05;
+1E87:5E;
+1E88:CD;
+1E89:10;
+1E8A:5B;
+1E8B:23;
+1E8C:7E;
+1E8D:BB;
+1E8E:20;
+1E8F:05;
+1E90:23;
+1E91:7E;
+1E92:BA;
+1E93:28;
+1E94:0D;
+1E95:FD;
+1E96:7E;
+1E97:13;
+1E98:3D;
+1E99:FD;
+1E9A:77;
+1E9B:13;
+1E9C:C2;
+1E9D:2B;
+1E9E:5B;
+1E9F:3E;
+1EA0:0A;
+1EA1:C9;
+1EA2:AF;
+1EA3:C9;
+1EA4:3A;
+1EA5:DF;
+1EA6:68;
+1EA7:E6;
+1EA8:04;
+1EA9:28;
+1EAA:F9;
+1EAB:C5;
+1EAC:01;
+1EAD:14;
+1EAE:00;
+1EAF:CD;
+1EB0:BE;
+1EB1:5E;
+1EB2:C1;
+1EB3:3A;
+1EB4:DF;
+1EB5:68;
+1EB6:E6;
+1EB7:04;
+1EB8:28;
+1EB9:EA;
+1EBA:3E;
+1EBB:11;
+1EBC:B7;
+1EBD:C9;
+1EBE:C5;
+1EBF:01;
+1EC0:89;
+1EC1:00;
+1EC2:0B;
+1EC3:78;
+1EC4:B1;
+1EC5:20;
+1EC6:FB;
+1EC7:C1;
+1EC8:0B;
+1EC9:78;
+1ECA:B1;
+1ECB:20;
+1ECC:F1;
+1ECD:C9;
+1ECE:FD;
+1ECF:7E;
+1ED0:14;
+1ED1:80;
+1ED2:FE;
+1ED3:28;
+1ED4:38;
+1ED5:02;
+1ED6:3E;
+1ED7:27;
+1ED8:FD;
+1ED9:77;
+1EDA:14;
+1EDB:CB;
+1EDC:20;
+1EDD:FD;
+1EDE:7E;
+1EDF:38;
+1EE0:4F;
+1EE1:07;
+1EE2:F5;
+1EE3:FD;
+1EE4:77;
+1EE5:38;
+1EE6:B1;
+1EE7:CD;
+1EE8:32;
+1EE9:5F;
+1EEA:C5;
+1EEB:01;
+1EEC:02;
+1EED:00;
+1EEE:CD;
+1EEF:BE;
+1EF0:5E;
+1EF1:C1;
+1EF2:F1;
+1EF3:CD;
+1EF4:32;
+1EF5:5F;
+1EF6:C5;
+1EF7:01;
+1EF8:0E;
+1EF9:00;
+1EFA:CD;
+1EFB:BE;
+1EFC:5E;
+1EFD:C1;
+1EFE:10;
+1EFF:DD;
+1F00:C9;
+1F01:FD;
+1F02:7E;
+1F03:14;
+1F04:90;
+1F05:F2;
+1F06:09;
+1F07:5F;
+1F08:AF;
+1F09:FD;
+1F0A:77;
+1F0B:14;
+1F0C:CB;
+1F0D:20;
+1F0E:FD;
+1F0F:7E;
+1F10:38;
+1F11:4F;
+1F12:0F;
+1F13:F5;
+1F14:FD;
+1F15:77;
+1F16:38;
+1F17:B1;
+1F18:CD;
+1F19:32;
+1F1A:5F;
+1F1B:C5;
+1F1C:01;
+1F1D:02;
+1F1E:00;
+1F1F:CD;
+1F20:BE;
+1F21:5E;
+1F22:C1;
+1F23:F1;
+1F24:CD;
+1F25:32;
+1F26:5F;
+1F27:C5;
+1F28:01;
+1F29:0E;
+1F2A:00;
+1F2B:CD;
+1F2C:BE;
+1F2D:5E;
+1F2E:C1;
+1F2F:10;
+1F30:DD;
+1F31:C9;
+1F32:E6;
+1F33:0F;
+1F34:4F;
+1F35:3E;
+1F36:F0;
+1F37:FD;
+1F38:A6;
+1F39:33;
+1F3A:B1;
+1F3B:FD;
+1F3C:77;
+1F3D:33;
+1F3E:D3;
+1F3F:10;
+1F40:C9;
+1F41:FD;
+1F42:7E;
+1F43:38;
+1F44:E6;
+1F45:0F;
+1F46:FD;
+1F47:B6;
+1F48:33;
+1F49:FD;
+1F4A:B6;
+1F4B:0B;
+1F4C:FD;
+1F4D:77;
+1F4E:33;
+1F4F:D3;
+1F50:10;
+1F51:C9;
+1F52:FD;
+1F53:7E;
+1F54:33;
+1F55:F6;
+1F56:40;
+1F57:E6;
+1F58:60;
+1F59:FD;
+1F5A:77;
+1F5B:33;
+1F5C:D3;
+1F5D:10;
+1F5E:C9;
+1F5F:00;
+1F60:00;
+1F61:00;
+1F62:00;
+1F63:00;
+1F64:00;
+1F65:00;
+1F66:00;
+1F67:00;
+1F68:00;
+1F69:00;
+1F6A:00;
+1F6B:00;
+1F6C:00;
+1F6D:00;
+1F6E:00;
+1F6F:00;
+1F70:00;
+1F71:00;
+1F72:00;
+1F73:00;
+1F74:00;
+1F75:00;
+1F76:00;
+1F77:00;
+1F78:00;
+1F79:00;
+1F7A:00;
+1F7B:00;
+1F7C:00;
+1F7D:FF;
+1F7E:FF;
+1F7F:FF;
+1F80:FF;
+1F81:FF;
+1F82:FF;
+1F83:FF;
+1F84:FF;
+1F85:FF;
+1F86:FF;
+1F87:FF;
+1F88:FF;
+1F89:FF;
+1F8A:FF;
+1F8B:FF;
+1F8C:FF;
+1F8D:FF;
+1F8E:FF;
+1F8F:FF;
+1F90:FF;
+1F91:FF;
+1F92:FF;
+1F93:FF;
+1F94:FF;
+1F95:FF;
+1F96:FF;
+1F97:FF;
+1F98:FF;
+1F99:FF;
+1F9A:FF;
+1F9B:FF;
+1F9C:FF;
+1F9D:FF;
+1F9E:FF;
+1F9F:FF;
+1FA0:FF;
+1FA1:FF;
+1FA2:FF;
+1FA3:FF;
+1FA4:FF;
+1FA5:FF;
+1FA6:FF;
+1FA7:FF;
+1FA8:FF;
+1FA9:FF;
+1FAA:FF;
+1FAB:FF;
+1FAC:FF;
+1FAD:FF;
+1FAE:FF;
+1FAF:FF;
+1FB0:FF;
+1FB1:FF;
+1FB2:FF;
+1FB3:FF;
+1FB4:FF;
+1FB5:FF;
+1FB6:FF;
+1FB7:FF;
+1FB8:FF;
+1FB9:FF;
+1FBA:FF;
+1FBB:FF;
+1FBC:FF;
+1FBD:FF;
+1FBE:FF;
+1FBF:FF;
+1FC0:FF;
+1FC1:FF;
+1FC2:FF;
+1FC3:FF;
+1FC4:FF;
+1FC5:FF;
+1FC6:FF;
+1FC7:FF;
+1FC8:FF;
+1FC9:FF;
+1FCA:FF;
+1FCB:FF;
+1FCC:FF;
+1FCD:FF;
+1FCE:FF;
+1FCF:FF;
+1FD0:FF;
+1FD1:FF;
+1FD2:FF;
+1FD3:FF;
+1FD4:FF;
+1FD5:FF;
+1FD6:FF;
+1FD7:FF;
+1FD8:FF;
+1FD9:FF;
+1FDA:FF;
+1FDB:FF;
+1FDC:FF;
+1FDD:FF;
+1FDE:FF;
+1FDF:FF;
+1FE0:FF;
+1FE1:FF;
+1FE2:FF;
+1FE3:FF;
+1FE4:FF;
+1FE5:FF;
+1FE6:FF;
+1FE7:FF;
+1FE8:FF;
+1FE9:FF;
+1FEA:FF;
+1FEB:FF;
+1FEC:FF;
+1FED:FF;
+1FEE:FF;
+1FEF:FF;
+1FF0:FF;
+1FF1:FF;
+1FF2:FF;
+1FF3:FF;
+1FF4:FF;
+1FF5:FF;
+1FF6:FF;
+1FF7:FF;
+1FF8:FF;
+1FF9:FF;
+1FFA:FF;
+1FFB:FF;
+1FFC:FF;
+1FFD:FF;
+1FFE:FF;
+1FFF:FF;
+END;
diff --git a/Computer_MiST/Laser310_MiST/rtl/roms/sysrom.mif b/Computer_MiST/Laser310_MiST/rtl/roms/sysrom.mif
new file mode 100644
index 00000000..e125b8a7
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/roms/sysrom.mif
@@ -0,0 +1,16391 @@
+DEPTH = 16384;
+WIDTH = 8;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+0000:F3;
+0001:AF;
+0002:32;
+0003:00;
+0004:68;
+0005:C3;
+0006:74;
+0007:06;
+0008:C3;
+0009:00;
+000A:78;
+000B:E1;
+000C:E9;
+000D:00;
+000E:00;
+000F:00;
+0010:C3;
+0011:03;
+0012:78;
+0013:C5;
+0014:06;
+0015:01;
+0016:18;
+0017:2E;
+0018:C3;
+0019:06;
+001A:78;
+001B:C5;
+001C:06;
+001D:02;
+001E:18;
+001F:26;
+0020:C3;
+0021:09;
+0022:78;
+0023:C5;
+0024:06;
+0025:04;
+0026:18;
+0027:1E;
+0028:C3;
+0029:0C;
+002A:78;
+002B:11;
+002C:15;
+002D:78;
+002E:18;
+002F:E3;
+0030:C3;
+0031:0F;
+0032:78;
+0033:11;
+0034:1D;
+0035:78;
+0036:18;
+0037:E3;
+0038:C3;
+0039:B8;
+003A:2E;
+003B:11;
+003C:25;
+003D:78;
+003E:18;
+003F:DB;
+0040:C3;
+0041:FD;
+0042:2E;
+0043:C9;
+0044:00;
+0045:00;
+0046:C3;
+0047:C2;
+0048:03;
+0049:CD;
+004A:2B;
+004B:00;
+004C:B7;
+004D:C0;
+004E:18;
+004F:F9;
+0050:2A;
+0051:20;
+0052:78;
+0053:7E;
+0054:32;
+0055:3C;
+0056:78;
+0057:C9;
+0058:4C;
+0059:FE;
+005A:54;
+005B:20;
+005C:D6;
+005D:FD;
+005E:21;
+005F:F1;
+0060:0B;
+0061:78;
+0062:B1;
+0063:20;
+0064:FB;
+0065:C9;
+0066:31;
+0067:00;
+0068:06;
+0069:3A;
+006A:EC;
+006B:68;
+006C:3C;
+006D:FE;
+006E:02;
+006F:D2;
+0070:00;
+0071:00;
+0072:C3;
+0073:CC;
+0074:06;
+0075:11;
+0076:80;
+0077:78;
+0078:21;
+0079:F7;
+007A:18;
+007B:01;
+007C:27;
+007D:00;
+007E:ED;
+007F:B0;
+0080:21;
+0081:E5;
+0082:79;
+0083:36;
+0084:3A;
+0085:23;
+0086:70;
+0087:23;
+0088:36;
+0089:2C;
+008A:23;
+008B:22;
+008C:A7;
+008D:78;
+008E:11;
+008F:2D;
+0090:01;
+0091:06;
+0092:1C;
+0093:21;
+0094:52;
+0095:79;
+0096:36;
+0097:C3;
+0098:23;
+0099:73;
+009A:23;
+009B:72;
+009C:23;
+009D:10;
+009E:F7;
+009F:06;
+00A0:15;
+00A1:36;
+00A2:C9;
+00A3:23;
+00A4:23;
+00A5:23;
+00A6:10;
+00A7:F9;
+00A8:21;
+00A9:E8;
+00AA:7A;
+00AB:70;
+00AC:31;
+00AD:F8;
+00AE:79;
+00AF:CD;
+00B0:8F;
+00B1:1B;
+00B2:CD;
+00B3:C9;
+00B4:01;
+00B5:00;
+00B6:00;
+00B7:00;
+00B8:00;
+00B9:00;
+00BA:00;
+00BB:00;
+00BC:00;
+00BD:00;
+00BE:18;
+00BF:04;
+00C0:D7;
+00C1:B7;
+00C2:20;
+00C3:12;
+00C4:21;
+00C5:4C;
+00C6:7B;
+00C7:23;
+00C8:7C;
+00C9:B5;
+00CA:28;
+00CB:1B;
+00CC:7E;
+00CD:47;
+00CE:2F;
+00CF:77;
+00D0:BE;
+00D1:70;
+00D2:28;
+00D3:F3;
+00D4:18;
+00D5:11;
+00D6:CD;
+00D7:5A;
+00D8:1E;
+00D9:B7;
+00DA:C2;
+00DB:97;
+00DC:19;
+00DD:EB;
+00DE:2B;
+00DF:3E;
+00E0:8F;
+00E1:46;
+00E2:77;
+00E3:BE;
+00E4:70;
+00E5:20;
+00E6:CE;
+00E7:2B;
+00E8:11;
+00E9:14;
+00EA:7C;
+00EB:DF;
+00EC:DA;
+00ED:7A;
+00EE:19;
+00EF:11;
+00F0:CE;
+00F1:FF;
+00F2:22;
+00F3:B1;
+00F4:78;
+00F5:19;
+00F6:22;
+00F7:A0;
+00F8:78;
+00F9:CD;
+00FA:4D;
+00FB:1B;
+00FC:CD;
+00FD:84;
+00FE:34;
+00FF:21;
+0100:0F;
+0101:01;
+0102:CD;
+0103:A7;
+0104:28;
+0105:ED;
+0106:56;
+0107:C3;
+0108:8E;
+0109:06;
+010A:00;
+010B:7E;
+010C:23;
+010D:FE;
+010E:0D;
+010F:56;
+0110:49;
+0111:44;
+0112:45;
+0113:4F;
+0114:20;
+0115:54;
+0116:45;
+0117:43;
+0118:48;
+0119:4E;
+011A:4F;
+011B:4C;
+011C:4F;
+011D:47;
+011E:59;
+011F:0D;
+0120:42;
+0121:41;
+0122:53;
+0123:49;
+0124:43;
+0125:20;
+0126:56;
+0127:32;
+0128:2E;
+0129:30;
+012A:0D;
+012B:0D;
+012C:00;
+012D:1E;
+012E:2C;
+012F:C3;
+0130:A2;
+0131:19;
+0132:D7;
+0133:AF;
+0134:01;
+0135:3E;
+0136:80;
+0137:01;
+0138:3E;
+0139:01;
+013A:F5;
+013B:CF;
+013C:28;
+013D:CD;
+013E:1C;
+013F:2B;
+0140:FE;
+0141:80;
+0142:D2;
+0143:4A;
+0144:1E;
+0145:F5;
+0146:CF;
+0147:2C;
+0148:CD;
+0149:1C;
+014A:2B;
+014B:FE;
+014C:40;
+014D:D2;
+014E:4A;
+014F:1E;
+0150:5F;
+0151:AF;
+0152:57;
+0153:EB;
+0154:29;
+0155:29;
+0156:29;
+0157:29;
+0158:29;
+0159:EB;
+015A:F1;
+015B:F5;
+015C:CB;
+015D:3F;
+015E:CB;
+015F:3F;
+0160:83;
+0161:5F;
+0162:7A;
+0163:F6;
+0164:70;
+0165:57;
+0166:F1;
+0167:E6;
+0168:03;
+0169:87;
+016A:47;
+016B:F1;
+016C:B7;
+016D:CA;
+016E:E7;
+016F:38;
+0170:F5;
+0171:0E;
+0172:3F;
+0173:3A;
+0174:46;
+0175:78;
+0176:CB;
+0177:27;
+0178:CB;
+0179:27;
+017A:CB;
+017B:0F;
+017C:CB;
+017D:09;
+017E:10;
+017F:FA;
+0180:C3;
+0181:03;
+0182:39;
+0183:21;
+0184:39;
+0185:78;
+0186:CB;
+0187:9E;
+0188:21;
+0189:84;
+018A:03;
+018B:CD;
+018C:A7;
+018D:28;
+018E:C3;
+018F:CF;
+0190:36;
+0191:F1;
+0192:FE;
+0193:20;
+0194:20;
+0195:14;
+0196:1A;
+0197:13;
+0198:FE;
+0199:20;
+019A:28;
+019B:FA;
+019C:FE;
+019D:D7;
+019E:E5;
+019F:3A;
+01A0:99;
+01A1:78;
+01A2:B7;
+01A3:20;
+01A4:06;
+01A5:CD;
+01A6:58;
+01A7:03;
+01A8:B7;
+01A9:28;
+01AA:11;
+01AB:F5;
+01AC:AF;
+01AD:32;
+01AE:99;
+01AF:78;
+01B0:3C;
+01B1:CD;
+01B2:57;
+01B3:28;
+01B4:F1;
+01B5:2A;
+01B6:D4;
+01B7:78;
+01B8:77;
+01B9:C3;
+01BA:84;
+01BB:28;
+01BC:21;
+01BD:28;
+01BE:19;
+01BF:22;
+01C0:21;
+01C1:79;
+01C2:3E;
+01C3:03;
+01C4:32;
+01C5:AF;
+01C6:78;
+01C7:E1;
+01C8:C9;
+01C9:3E;
+01CA:1C;
+01CB:CD;
+01CC:3A;
+01CD:03;
+01CE:3E;
+01CF:1F;
+01D0:C3;
+01D1:3A;
+01D2:03;
+01D3:ED;
+01D4:5F;
+01D5:32;
+01D6:AB;
+01D7:78;
+01D8:C9;
+01D9:54;
+01DA:47;
+01DB:42;
+01DC:35;
+01DD:4E;
+01DE:36;
+01DF:59;
+01E0:48;
+01E1:57;
+01E2:53;
+01E3:58;
+01E4:32;
+01E5:2E;
+01E6:39;
+01E7:4F;
+01E8:4C;
+01E9:00;
+01EA:00;
+01EB:00;
+01EC:00;
+01ED:00;
+01EE:2D;
+01EF:0D;
+01F0:3A;
+01F1:45;
+01F2:44;
+01F3:43;
+01F4:33;
+01F5:2C;
+01F6:38;
+01F7:49;
+01F8:4B;
+01F9:51;
+01FA:41;
+01FB:5A;
+01FC:31;
+01FD:20;
+01FE:30;
+01FF:50;
+0200:3B;
+0201:52;
+0202:46;
+0203:56;
+0204:34;
+0205:4D;
+0206:37;
+0207:55;
+0208:4A;
+0209:8C;
+020A:89;
+020B:00;
+020C:25;
+020D:5E;
+020E:26;
+020F:83;
+0210:86;
+0211:8D;
+0212:82;
+0213:00;
+0214:22;
+0215:3E;
+0216:29;
+0217:5B;
+0218:3F;
+0219:00;
+021A:00;
+021B:00;
+021C:00;
+021D:00;
+021E:3D;
+021F:0D;
+0220:2A;
+0221:8B;
+0222:84;
+0223:00;
+0224:23;
+0225:3C;
+0226:28;
+0227:85;
+0228:2F;
+0229:8E;
+022A:81;
+022B:80;
+022C:21;
+022D:20;
+022E:40;
+022F:5D;
+0230:2B;
+0231:87;
+0232:88;
+0233:00;
+0234:24;
+0235:5C;
+0236:27;
+0237:8A;
+0238:8F;
+0239:CA;
+023A:8D;
+023B:B5;
+023C:B4;
+023D:97;
+023E:8E;
+023F:95;
+0240:84;
+0241:BD;
+0242:CC;
+0243:B1;
+0244:B9;
+0245:1B;
+0246:8B;
+0247:8C;
+0248:15;
+0249:00;
+024A:00;
+024B:00;
+024C:00;
+024D:00;
+024E:01;
+024F:00;
+0250:00;
+0251:87;
+0252:8A;
+0253:B3;
+0254:9C;
+0255:09;
+0256:BB;
+0257:89;
+0258:BC;
+0259:81;
+025A:9D;
+025B:E5;
+025C:BA;
+025D:0A;
+025E:88;
+025F:B2;
+0260:7F;
+0261:92;
+0262:91;
+0263:AF;
+0264:98;
+0265:08;
+0266:80;
+0267:8F;
+0268:93;
+0269:FA;
+026A:94;
+026B:9E;
+026C:DF;
+026D:BF;
+026E:E0;
+026F:F9;
+0270:83;
+0271:F5;
+0272:F4;
+0273:A0;
+0274:E1;
+0275:00;
+0276:D9;
+0277:D3;
+0278:00;
+0279:00;
+027A:00;
+027B:00;
+027C:00;
+027D:00;
+027E:01;
+027F:00;
+0280:00;
+0281:F3;
+0282:90;
+0283:96;
+0284:E3;
+0285:00;
+0286:DD;
+0287:D2;
+0288:C6;
+0289:F7;
+028A:F6;
+028B:DB;
+028C:E2;
+028D:00;
+028E:D8;
+028F:CB;
+0290:00;
+0291:F8;
+0292:DE;
+0293:C1;
+0294:E4;
+0295:00;
+0296:D7;
+0297:C9;
+0298:82;
+0299:E2;
+029A:E1;
+029B:E3;
+029C:E4;
+029D:DF;
+029E:E0;
+029F:D7;
+02A0:DD;
+02A1:D9;
+02A2:D8;
+02A3:F7;
+02A4:F5;
+02A5:F3;
+02A6:F8;
+02A7:F7;
+02A8:F9;
+02A9:9D;
+02AA:F6;
+02AB:F4;
+02AC:DE;
+02AD:E5;
+02AE:FA;
+02AF:80;
+02B0:80;
+02B1:80;
+02B2:B8;
+02B3:B8;
+02B4:80;
+02B5:B8;
+02B6:B8;
+02B7:80;
+02B8:87;
+02B9:80;
+02BA:BF;
+02BB:B8;
+02BC:87;
+02BD:B8;
+02BE:BF;
+02BF:87;
+02C0:80;
+02C1:87;
+02C2:B8;
+02C3:BF;
+02C4:80;
+02C5:BF;
+02C6:B8;
+02C7:87;
+02C8:87;
+02C9:87;
+02CA:BF;
+02CB:BF;
+02CC:87;
+02CD:BF;
+02CE:BF;
+02CF:72;
+02D0:02;
+02D1:4F;
+02D2:02;
+02D3:2E;
+02D4:02;
+02D5:0E;
+02D6:02;
+02D7:F1;
+02D8:01;
+02D9:D5;
+02DA:01;
+02DB:B7;
+02DC:01;
+02DD:9E;
+02DE:01;
+02DF:86;
+02E0:01;
+02E1:70;
+02E2:01;
+02E3:5B;
+02E4:01;
+02E5:48;
+02E6:01;
+02E7:35;
+02E8:01;
+02E9:23;
+02EA:01;
+02EB:13;
+02EC:01;
+02ED:03;
+02EE:01;
+02EF:F4;
+02F0:00;
+02F1:E6;
+02F2:00;
+02F3:D9;
+02F4:00;
+02F5:CD;
+02F6:00;
+02F7:C1;
+02F8:00;
+02F9:B6;
+02FA:00;
+02FB:AB;
+02FC:00;
+02FD:A1;
+02FE:00;
+02FF:98;
+0300:00;
+0301:8F;
+0302:00;
+0303:87;
+0304:00;
+0305:7F;
+0306:00;
+0307:78;
+0308:00;
+0309:70;
+030A:00;
+030B:6A;
+030C:00;
+030D:47;
+030E:3A;
+030F:3C;
+0310:78;
+0311:2A;
+0312:20;
+0313:78;
+0314:77;
+0315:78;
+0316:C9;
+0317:01;
+0318:20;
+0319:00;
+031A:B7;
+031B:ED;
+031C:42;
+031D:22;
+031E:20;
+031F:78;
+0320:C9;
+0321:01;
+0322:02;
+0323:03;
+0324:04;
+0325:06;
+0326:08;
+0327:0C;
+0328:10;
+0329:18;
+032A:C5;
+032B:4F;
+032C:CD;
+032D:C1;
+032E:79;
+032F:3A;
+0330:9C;
+0331:78;
+0332:B7;
+0333:79;
+0334:C1;
+0335:FA;
+0336:54;
+0337:3B;
+0338:20;
+0339:62;
+033A:D5;
+033B:F5;
+033C:C5;
+033D:E5;
+033E:CD;
+033F:8B;
+0340:30;
+0341:E1;
+0342:C1;
+0343:00;
+0344:00;
+0345:F1;
+0346:D1;
+0347:C9;
+0348:3A;
+0349:3D;
+034A:78;
+034B:E6;
+034C:08;
+034D:3A;
+034E:20;
+034F:78;
+0350:28;
+0351:03;
+0352:0F;
+0353:E6;
+0354:1F;
+0355:E6;
+0356:1F;
+0357:C9;
+0358:CD;
+0359:C4;
+035A:79;
+035B:D5;
+035C:CD;
+035D:2B;
+035E:00;
+035F:D1;
+0360:C9;
+0361:0A;
+0362:0B;
+0363:0C;
+0364:0C;
+0365:0D;
+0366:0E;
+0367:0F;
+0368:0F;
+0369:10;
+036A:11;
+036B:12;
+036C:13;
+036D:15;
+036E:16;
+036F:17;
+0370:19;
+0371:1A;
+0372:1C;
+0373:1D;
+0374:1F;
+0375:21;
+0376:23;
+0377:25;
+0378:27;
+0379:29;
+037A:2C;
+037B:2E;
+037C:31;
+037D:34;
+037E:35;
+037F:3A;
+0380:4F;
+0381:4B;
+0382:0D;
+0383:00;
+0384:45;
+0385:52;
+0386:52;
+0387:4F;
+0388:52;
+0389:0D;
+038A:00;
+038B:AF;
+038C:32;
+038D:9C;
+038E:78;
+038F:3A;
+0390:9B;
+0391:78;
+0392:B7;
+0393:C8;
+0394:3E;
+0395:0D;
+0396:D5;
+0397:CD;
+0398:9C;
+0399:03;
+039A:D1;
+039B:C9;
+039C:F5;
+039D:D5;
+039E:C5;
+039F:4F;
+03A0:1E;
+03A1:00;
+03A2:FE;
+03A3:0C;
+03A4:28;
+03A5:10;
+03A6:FE;
+03A7:0A;
+03A8:20;
+03A9:03;
+03AA:3E;
+03AB:0D;
+03AC:4F;
+03AD:FE;
+03AE:0D;
+03AF:28;
+03B0:05;
+03B1:3A;
+03B2:9B;
+03B3:78;
+03B4:3C;
+03B5:5F;
+03B6:7B;
+03B7:32;
+03B8:9B;
+03B9:78;
+03BA:79;
+03BB:CD;
+03BC:3B;
+03BD:00;
+03BE:C1;
+03BF:D1;
+03C0:F1;
+03C1:C9;
+03C2:E5;
+03C3:DD;
+03C4:E5;
+03C5:D5;
+03C6:DD;
+03C7:E1;
+03C8:D5;
+03C9:21;
+03CA:DD;
+03CB:03;
+03CC:E5;
+03CD:4F;
+03CE:1A;
+03CF:A0;
+03D0:B8;
+03D1:C2;
+03D2:33;
+03D3:78;
+03D4:FE;
+03D5:02;
+03D6:DD;
+03D7:6E;
+03D8:01;
+03D9:DD;
+03DA:66;
+03DB:02;
+03DC:E9;
+03DD:D1;
+03DE:DD;
+03DF:E1;
+03E0:E1;
+03E1:C1;
+03E2:C9;
+03E3:21;
+03E4:39;
+03E5:78;
+03E6:CB;
+03E7:EE;
+03E8:2A;
+03E9:20;
+03EA:78;
+03EB:CD;
+03EC:53;
+03ED:00;
+03EE:7C;
+03EF:FE;
+03F0:71;
+03F1:20;
+03F2:10;
+03F3:7D;
+03F4:FE;
+03F5:E0;
+03F6:20;
+03F7:0B;
+03F8:3A;
+03F9:D7;
+03FA:7A;
+03FB:B7;
+03FC:20;
+03FD:05;
+03FE:3E;
+03FF:0D;
+0400:CD;
+0401:8B;
+0402:30;
+0403:41;
+0404:C5;
+0405:21;
+0406:39;
+0407:78;
+0408:CB;
+0409:86;
+040A:CB;
+040B:96;
+040C:CB;
+040D:46;
+040E:28;
+040F:FC;
+0410:3A;
+0411:A6;
+0412:78;
+0413:4F;
+0414:AF;
+0415:32;
+0416:A6;
+0417:78;
+0418:47;
+0419:2A;
+041A:20;
+041B:78;
+041C:ED;
+041D:42;
+041E:22;
+041F:20;
+0420:78;
+0421:11;
+0422:E8;
+0423:79;
+0424:C1;
+0425:21;
+0426:39;
+0427:78;
+0428:CB;
+0429:66;
+042A:2A;
+042B:20;
+042C:78;
+042D:28;
+042E:42;
+042F:C5;
+0430:E5;
+0431:CD;
+0432:A8;
+0433:33;
+0434:E1;
+0435:C1;
+0436:B7;
+0437:20;
+0438:08;
+0439:7D;
+043A:D6;
+043B:20;
+043C:6F;
+043D:7C;
+043E:DE;
+043F:00;
+0440:67;
+0441:48;
+0442:1A;
+0443:BE;
+0444:20;
+0445:07;
+0446:23;
+0447:13;
+0448:10;
+0449:F8;
+044A:C5;
+044B:18;
+044C:04;
+044D:01;
+044E:00;
+044F:00;
+0450:C5;
+0451:E5;
+0452:CD;
+0453:A8;
+0454:33;
+0455:E1;
+0456:C1;
+0457:C5;
+0458:FE;
+0459:80;
+045A:28;
+045B:0A;
+045C:3E;
+045D:40;
+045E:91;
+045F:47;
+0460:D1;
+0461:1E;
+0462:00;
+0463:D5;
+0464:18;
+0465:05;
+0466:06;
+0467:20;
+0468:2A;
+0469:20;
+046A:78;
+046B:11;
+046C:E8;
+046D:79;
+046E:C3;
+046F:A8;
+0470:3E;
+0471:01;
+0472:00;
+0473:00;
+0474:C5;
+0475:E5;
+0476:CD;
+0477:A8;
+0478:33;
+0479:E1;
+047A:FE;
+047B:80;
+047C:28;
+047D:0E;
+047E:FE;
+047F:81;
+0480:28;
+0481:06;
+0482:01;
+0483:20;
+0484:00;
+0485:B7;
+0486:ED;
+0487:42;
+0488:06;
+0489:40;
+048A:18;
+048B:02;
+048C:06;
+048D:20;
+048E:3A;
+048F:18;
+0490:78;
+0491:B7;
+0492:CA;
+0493:40;
+0494:3E;
+0495:7E;
+0496:FE;
+0497:40;
+0498:DA;
+0499:AE;
+049A:04;
+049B:C1;
+049C:11;
+049D:A4;
+049E:04;
+049F:D5;
+04A0:C5;
+04A1:C3;
+04A2:02;
+04A3:05;
+04A4:D8;
+04A5:21;
+04A6:1A;
+04A7:3E;
+04A8:CD;
+04A9:A7;
+04AA:28;
+04AB:C3;
+04AC:E3;
+04AD:03;
+04AE:FE;
+04AF:22;
+04B0:20;
+04B1:31;
+04B2:12;
+04B3:23;
+04B4:13;
+04B5:05;
+04B6:28;
+04B7:36;
+04B8:7E;
+04B9:FE;
+04BA:40;
+04BB:DA;
+04BC:C9;
+04BD:04;
+04BE:FE;
+04BF:80;
+04C0:DA;
+04C1:C5;
+04C2:04;
+04C3:E6;
+04C4:8F;
+04C5:F6;
+04C6:80;
+04C7:18;
+04C8:13;
+04C9:FE;
+04CA:22;
+04CB:20;
+04CC:09;
+04CD:E5;
+04CE:21;
+04CF:39;
+04D0:78;
+04D1:CB;
+04D2:66;
+04D3:E1;
+04D4:28;
+04D5:0D;
+04D6:CB;
+04D7:6F;
+04D8:20;
+04D9:02;
+04DA:F6;
+04DB:40;
+04DC:12;
+04DD:23;
+04DE:13;
+04DF:10;
+04E0:D7;
+04E1:18;
+04E2:0B;
+04E3:CB;
+04E4:6F;
+04E5:20;
+04E6:02;
+04E7:F6;
+04E8:40;
+04E9:12;
+04EA:23;
+04EB:13;
+04EC:10;
+04ED:A7;
+04EE:1B;
+04EF:7A;
+04F0:FE;
+04F1:79;
+04F2:20;
+04F3:06;
+04F4:7B;
+04F5:FE;
+04F6:E8;
+04F7:DA;
+04F8:FF;
+04F9:04;
+04FA:1A;
+04FB:FE;
+04FC:20;
+04FD:28;
+04FE:EF;
+04FF:13;
+0500:AF;
+0501:12;
+0502:CD;
+0503:A8;
+0504:33;
+0505:2A;
+0506:20;
+0507:78;
+0508:FE;
+0509:81;
+050A:CD;
+050B:53;
+050C:00;
+050D:20;
+050E:04;
+050F:AF;
+0510:CD;
+0511:8B;
+0512:30;
+0513:AF;
+0514:CD;
+0515:8B;
+0516:30;
+0517:3A;
+0518:38;
+0519:78;
+051A:E6;
+051B:FD;
+051C:32;
+051D:38;
+051E:78;
+051F:21;
+0520:39;
+0521:78;
+0522:CB;
+0523:56;
+0524:28;
+0525:05;
+0526:3E;
+0527:01;
+0528:37;
+0529:18;
+052A:01;
+052B:AF;
+052C:21;
+052D:39;
+052E:78;
+052F:CB;
+0530:A6;
+0531:21;
+0532:E8;
+0533:79;
+0534:C1;
+0535:F5;
+0536:09;
+0537:C3;
+0538:29;
+0539:3E;
+053A:3A;
+053B:AF;
+053C:7A;
+053D:B7;
+053E:20;
+053F:FA;
+0540:06;
+0541:40;
+0542:21;
+0543:E8;
+0544:79;
+0545:3E;
+0546:20;
+0547:77;
+0548:23;
+0549:10;
+054A:FC;
+054B:AF;
+054C:77;
+054D:CD;
+054E:A8;
+054F:33;
+0550:B7;
+0551:3A;
+0552:A6;
+0553:78;
+0554:20;
+0555:02;
+0556:C6;
+0557:20;
+0558:4F;
+0559:AF;
+055A:47;
+055B:2A;
+055C:20;
+055D:78;
+055E:ED;
+055F:42;
+0560:11;
+0561:E8;
+0562:79;
+0563:C5;
+0564:ED;
+0565:B0;
+0566:C1;
+0567:21;
+0568:39;
+0569:78;
+056A:CB;
+056B:E6;
+056C:CD;
+056D:E3;
+056E:03;
+056F:C9;
+0570:52;
+0571:55;
+0572:4E;
+0573:00;
+0574:C4;
+0575:33;
+0576:32;
+0577:CD;
+0578:A3;
+0579:1A;
+057A:CD;
+057B:D8;
+057C:17;
+057D:CD;
+057E:0D;
+057F:19;
+0580:CA;
+0581:5A;
+0582:12;
+0583:CD;
+0584:49;
+0585:1F;
+0586:38;
+0587:18;
+0588:EF;
+0589:3A;
+058A:38;
+058B:04;
+058C:DD;
+058D:79;
+058E:B7;
+058F:28;
+0590:33;
+0591:FE;
+0592:0B;
+0593:28;
+0594:0A;
+0595:FE;
+0596:0C;
+0597:20;
+0598:14;
+0599:AF;
+059A:DD;
+059B:B6;
+059C:03;
+059D:28;
+059E:0E;
+059F:DD;
+05A0:7E;
+05A1:03;
+05A2:DD;
+05A3:96;
+05A4:04;
+05A5:47;
+05A6:CD;
+05A7:E2;
+05A8:3A;
+05A9:10;
+05AA:FB;
+05AB:18;
+05AC:12;
+05AD:CD;
+05AE:B6;
+05AF:3A;
+05B0:79;
+05B1:FE;
+05B2:0D;
+05B3:C0;
+05B4:DD;
+05B5:34;
+05B6:04;
+05B7:DD;
+05B8:7E;
+05B9:04;
+05BA:DD;
+05BB:BE;
+05BC:03;
+05BD:79;
+05BE:C0;
+05BF:DD;
+05C0:36;
+05C1:04;
+05C2:00;
+05C3:C9;
+05C4:DB;
+05C5:00;
+05C6:E6;
+05C7:01;
+05C8:C9;
+05C9:C5;
+05CA:E5;
+05CB:06;
+05CC:04;
+05CD:21;
+05CE:D2;
+05CF:7A;
+05D0:77;
+05D1:23;
+05D2:10;
+05D3:FC;
+05D4:E1;
+05D5:C1;
+05D6:C9;
+05D7:21;
+05D8:38;
+05D9:78;
+05DA:CB;
+05DB:56;
+05DC:28;
+05DD:15;
+05DE:57;
+05DF:3A;
+05E0:3A;
+05E1:78;
+05E2:B7;
+05E3:28;
+05E4:0F;
+05E5:3C;
+05E6:32;
+05E7:3A;
+05E8:78;
+05E9:FE;
+05EA:2A;
+05EB:28;
+05EC:02;
+05ED:AF;
+05EE:C9;
+05EF:CB;
+05F0:96;
+05F1:AF;
+05F2:C9;
+05F3:57;
+05F4:21;
+05F5:38;
+05F6:78;
+05F7:7E;
+05F8:E6;
+05F9:18;
+05FA:20;
+05FB:0B;
+05FC:CB;
+05FD:DE;
+05FE:AF;
+05FF:32;
+0600:37;
+0601:78;
+0602:7A;
+0603:32;
+0604:36;
+0605:78;
+0606:C9;
+0607:CB;
+0608:66;
+0609:20;
+060A:2A;
+060B:3A;
+060C:36;
+060D:78;
+060E:BA;
+060F:20;
+0610:21;
+0611:ED;
+0612:4B;
+0613:42;
+0614:78;
+0615:2A;
+0616:44;
+0617:78;
+0618:7B;
+0619:CD;
+061A:35;
+061B:2F;
+061C:BA;
+061D:CA;
+061E:D7;
+061F:2F;
+0620:FE;
+0621:00;
+0622:CA;
+0623:D7;
+0624:2F;
+0625:21;
+0626:38;
+0627:78;
+0628:CB;
+0629:DE;
+062A:CB;
+062B:E6;
+062C:CB;
+062D:96;
+062E:32;
+062F:37;
+0630:78;
+0631:C9;
+0632:7A;
+0633:18;
+0634:F0;
+0635:3A;
+0636:36;
+0637:78;
+0638:BA;
+0639:28;
+063A:08;
+063B:3A;
+063C:37;
+063D:78;
+063E:BA;
+063F:28;
+0640:02;
+0641:AF;
+0642:C9;
+0643:ED;
+0644:4B;
+0645:42;
+0646:78;
+0647:2A;
+0648:44;
+0649:78;
+064A:7B;
+064B:CD;
+064C:35;
+064D:2F;
+064E:BA;
+064F:28;
+0650:05;
+0651:FE;
+0652:00;
+0653:C2;
+0654:D7;
+0655:2F;
+0656:21;
+0657:38;
+0658:78;
+0659:CB;
+065A:DE;
+065B:CB;
+065C:A6;
+065D:3A;
+065E:36;
+065F:78;
+0660:BA;
+0661:20;
+0662:05;
+0663:AF;
+0664:32;
+0665:37;
+0666:78;
+0667:C9;
+0668:3A;
+0669:37;
+066A:78;
+066B:32;
+066C:36;
+066D:78;
+066E:18;
+066F:F3;
+0670:DD;
+0671:CB;
+0672:09;
+0673:D6;
+0674:00;
+0675:00;
+0676:21;
+0677:D2;
+0678:06;
+0679:11;
+067A:00;
+067B:78;
+067C:01;
+067D:36;
+067E:00;
+067F:ED;
+0680:B0;
+0681:3D;
+0682:3D;
+0683:20;
+0684:F1;
+0685:06;
+0686:27;
+0687:12;
+0688:13;
+0689:10;
+068A:FC;
+068B:C3;
+068C:75;
+068D:00;
+068E:21;
+068F:00;
+0690:40;
+0691:CD;
+0692:A4;
+0693:06;
+0694:21;
+0695:00;
+0696:60;
+0697:CD;
+0698:A4;
+0699:06;
+069A:21;
+069B:00;
+069C:80;
+069D:CD;
+069E:A4;
+069F:06;
+06A0:FB;
+06A1:C3;
+06A2:19;
+06A3:1A;
+06A4:3E;
+06A5:AA;
+06A6:BE;
+06A7:23;
+06A8:C0;
+06A9:2F;
+06AA:BE;
+06AB:23;
+06AC:C0;
+06AD:3E;
+06AE:E7;
+06AF:BE;
+06B0:23;
+06B1:C0;
+06B2:2F;
+06B3:BE;
+06B4:23;
+06B5:C0;
+06B6:FB;
+06B7:E9;
+06B8:0E;
+06B9:02;
+06BA:CD;
+06BB:59;
+06BC:1A;
+06BD:CD;
+06BE:B8;
+06BF:34;
+06C0:CD;
+06C1:E3;
+06C2:18;
+06C3:28;
+06C4:C0;
+06C5:EF;
+06C6:2C;
+06C7:28;
+06C8:14;
+06C9:CD;
+06CA:F1;
+06CB:34;
+06CC:01;
+06CD:18;
+06CE:1A;
+06CF:C3;
+06D0:AE;
+06D1:19;
+06D2:C3;
+06D3:96;
+06D4:1C;
+06D5:C3;
+06D6:78;
+06D7:1D;
+06D8:C3;
+06D9:90;
+06DA:1C;
+06DB:C3;
+06DC:D9;
+06DD:25;
+06DE:C9;
+06DF:00;
+06E0:00;
+06E1:C9;
+06E2:00;
+06E3:00;
+06E4:FB;
+06E5:C9;
+06E6:00;
+06E7:01;
+06E8:F4;
+06E9:2E;
+06EA:00;
+06EB:00;
+06EC:00;
+06ED:4B;
+06EE:49;
+06EF:00;
+06F0:00;
+06F1:00;
+06F2:00;
+06F3:70;
+06F4:00;
+06F5:00;
+06F6:00;
+06F7:06;
+06F8:8D;
+06F9:05;
+06FA:43;
+06FB:00;
+06FC:00;
+06FD:50;
+06FE:52;
+06FF:C3;
+0700:00;
+0701:50;
+0702:C7;
+0703:00;
+0704:00;
+0705:3E;
+0706:00;
+0707:C9;
+0708:21;
+0709:80;
+070A:13;
+070B:CD;
+070C:C2;
+070D:09;
+070E:18;
+070F:06;
+0710:CD;
+0711:C2;
+0712:09;
+0713:CD;
+0714:82;
+0715:09;
+0716:78;
+0717:B7;
+0718:C8;
+0719:3A;
+071A:24;
+071B:79;
+071C:B7;
+071D:CA;
+071E:B4;
+071F:09;
+0720:90;
+0721:30;
+0722:0C;
+0723:2F;
+0724:3C;
+0725:EB;
+0726:CD;
+0727:A4;
+0728:09;
+0729:EB;
+072A:CD;
+072B:B4;
+072C:09;
+072D:C1;
+072E:D1;
+072F:FE;
+0730:19;
+0731:D0;
+0732:F5;
+0733:CD;
+0734:DF;
+0735:09;
+0736:67;
+0737:F1;
+0738:CD;
+0739:D7;
+073A:07;
+073B:B4;
+073C:21;
+073D:21;
+073E:79;
+073F:F2;
+0740:54;
+0741:07;
+0742:CD;
+0743:B7;
+0744:07;
+0745:D2;
+0746:96;
+0747:07;
+0748:23;
+0749:34;
+074A:CA;
+074B:B2;
+074C:07;
+074D:2E;
+074E:01;
+074F:CD;
+0750:EB;
+0751:07;
+0752:18;
+0753:42;
+0754:AF;
+0755:90;
+0756:47;
+0757:7E;
+0758:9B;
+0759:5F;
+075A:23;
+075B:7E;
+075C:9A;
+075D:57;
+075E:23;
+075F:7E;
+0760:99;
+0761:4F;
+0762:DC;
+0763:C3;
+0764:07;
+0765:68;
+0766:63;
+0767:AF;
+0768:47;
+0769:79;
+076A:B7;
+076B:20;
+076C:18;
+076D:4A;
+076E:54;
+076F:65;
+0770:6F;
+0771:78;
+0772:D6;
+0773:08;
+0774:FE;
+0775:E0;
+0776:20;
+0777:F0;
+0778:AF;
+0779:32;
+077A:24;
+077B:79;
+077C:C9;
+077D:05;
+077E:29;
+077F:7A;
+0780:17;
+0781:57;
+0782:79;
+0783:8F;
+0784:4F;
+0785:F2;
+0786:7D;
+0787:07;
+0788:78;
+0789:5C;
+078A:45;
+078B:B7;
+078C:28;
+078D:08;
+078E:21;
+078F:24;
+0790:79;
+0791:86;
+0792:77;
+0793:30;
+0794:E3;
+0795:C8;
+0796:78;
+0797:21;
+0798:24;
+0799:79;
+079A:B7;
+079B:FC;
+079C:A8;
+079D:07;
+079E:46;
+079F:23;
+07A0:7E;
+07A1:E6;
+07A2:80;
+07A3:A9;
+07A4:4F;
+07A5:C3;
+07A6:B4;
+07A7:09;
+07A8:1C;
+07A9:C0;
+07AA:14;
+07AB:C0;
+07AC:0C;
+07AD:C0;
+07AE:0E;
+07AF:80;
+07B0:34;
+07B1:C0;
+07B2:1E;
+07B3:0A;
+07B4:C3;
+07B5:A2;
+07B6:19;
+07B7:7E;
+07B8:83;
+07B9:5F;
+07BA:23;
+07BB:7E;
+07BC:8A;
+07BD:57;
+07BE:23;
+07BF:7E;
+07C0:89;
+07C1:4F;
+07C2:C9;
+07C3:21;
+07C4:25;
+07C5:79;
+07C6:7E;
+07C7:2F;
+07C8:77;
+07C9:AF;
+07CA:6F;
+07CB:90;
+07CC:47;
+07CD:7D;
+07CE:9B;
+07CF:5F;
+07D0:7D;
+07D1:9A;
+07D2:57;
+07D3:7D;
+07D4:99;
+07D5:4F;
+07D6:C9;
+07D7:06;
+07D8:00;
+07D9:D6;
+07DA:08;
+07DB:38;
+07DC:07;
+07DD:43;
+07DE:5A;
+07DF:51;
+07E0:0E;
+07E1:00;
+07E2:18;
+07E3:F5;
+07E4:C6;
+07E5:09;
+07E6:6F;
+07E7:AF;
+07E8:2D;
+07E9:C8;
+07EA:79;
+07EB:1F;
+07EC:4F;
+07ED:7A;
+07EE:1F;
+07EF:57;
+07F0:7B;
+07F1:1F;
+07F2:5F;
+07F3:78;
+07F4:1F;
+07F5:47;
+07F6:18;
+07F7:EF;
+07F8:00;
+07F9:00;
+07FA:00;
+07FB:81;
+07FC:03;
+07FD:AA;
+07FE:56;
+07FF:19;
+0800:80;
+0801:F1;
+0802:22;
+0803:76;
+0804:80;
+0805:45;
+0806:AA;
+0807:38;
+0808:82;
+0809:CD;
+080A:55;
+080B:09;
+080C:B7;
+080D:EA;
+080E:4A;
+080F:1E;
+0810:21;
+0811:24;
+0812:79;
+0813:7E;
+0814:01;
+0815:35;
+0816:80;
+0817:11;
+0818:F3;
+0819:04;
+081A:90;
+081B:F5;
+081C:70;
+081D:D5;
+081E:C5;
+081F:CD;
+0820:16;
+0821:07;
+0822:C1;
+0823:D1;
+0824:04;
+0825:CD;
+0826:A2;
+0827:08;
+0828:21;
+0829:F8;
+082A:07;
+082B:CD;
+082C:10;
+082D:07;
+082E:21;
+082F:FC;
+0830:07;
+0831:CD;
+0832:9A;
+0833:14;
+0834:01;
+0835:80;
+0836:80;
+0837:11;
+0838:00;
+0839:00;
+083A:CD;
+083B:16;
+083C:07;
+083D:F1;
+083E:CD;
+083F:89;
+0840:0F;
+0841:01;
+0842:31;
+0843:80;
+0844:11;
+0845:18;
+0846:72;
+0847:CD;
+0848:55;
+0849:09;
+084A:C8;
+084B:2E;
+084C:00;
+084D:CD;
+084E:14;
+084F:09;
+0850:79;
+0851:32;
+0852:4F;
+0853:79;
+0854:EB;
+0855:22;
+0856:50;
+0857:79;
+0858:01;
+0859:00;
+085A:00;
+085B:50;
+085C:58;
+085D:21;
+085E:65;
+085F:07;
+0860:E5;
+0861:21;
+0862:69;
+0863:08;
+0864:E5;
+0865:E5;
+0866:21;
+0867:21;
+0868:79;
+0869:7E;
+086A:23;
+086B:B7;
+086C:28;
+086D:24;
+086E:E5;
+086F:2E;
+0870:08;
+0871:1F;
+0872:67;
+0873:79;
+0874:30;
+0875:0B;
+0876:E5;
+0877:2A;
+0878:50;
+0879:79;
+087A:19;
+087B:EB;
+087C:E1;
+087D:3A;
+087E:4F;
+087F:79;
+0880:89;
+0881:1F;
+0882:4F;
+0883:7A;
+0884:1F;
+0885:57;
+0886:7B;
+0887:1F;
+0888:5F;
+0889:78;
+088A:1F;
+088B:47;
+088C:2D;
+088D:7C;
+088E:20;
+088F:E1;
+0890:E1;
+0891:C9;
+0892:43;
+0893:5A;
+0894:51;
+0895:4F;
+0896:C9;
+0897:CD;
+0898:A4;
+0899:09;
+089A:21;
+089B:D8;
+089C:0D;
+089D:CD;
+089E:B1;
+089F:09;
+08A0:C1;
+08A1:D1;
+08A2:CD;
+08A3:55;
+08A4:09;
+08A5:CA;
+08A6:9A;
+08A7:19;
+08A8:2E;
+08A9:FF;
+08AA:CD;
+08AB:14;
+08AC:09;
+08AD:34;
+08AE:34;
+08AF:2B;
+08B0:7E;
+08B1:32;
+08B2:89;
+08B3:78;
+08B4:2B;
+08B5:7E;
+08B6:32;
+08B7:85;
+08B8:78;
+08B9:2B;
+08BA:7E;
+08BB:32;
+08BC:81;
+08BD:78;
+08BE:41;
+08BF:EB;
+08C0:AF;
+08C1:4F;
+08C2:57;
+08C3:5F;
+08C4:32;
+08C5:8C;
+08C6:78;
+08C7:E5;
+08C8:C5;
+08C9:7D;
+08CA:CD;
+08CB:80;
+08CC:78;
+08CD:DE;
+08CE:00;
+08CF:3F;
+08D0:30;
+08D1:07;
+08D2:32;
+08D3:8C;
+08D4:78;
+08D5:F1;
+08D6:F1;
+08D7:37;
+08D8:D2;
+08D9:C1;
+08DA:E1;
+08DB:79;
+08DC:3C;
+08DD:3D;
+08DE:1F;
+08DF:FA;
+08E0:97;
+08E1:07;
+08E2:17;
+08E3:7B;
+08E4:17;
+08E5:5F;
+08E6:7A;
+08E7:17;
+08E8:57;
+08E9:79;
+08EA:17;
+08EB:4F;
+08EC:29;
+08ED:78;
+08EE:17;
+08EF:47;
+08F0:3A;
+08F1:8C;
+08F2:78;
+08F3:17;
+08F4:32;
+08F5:8C;
+08F6:78;
+08F7:79;
+08F8:B2;
+08F9:B3;
+08FA:20;
+08FB:CB;
+08FC:E5;
+08FD:21;
+08FE:24;
+08FF:79;
+0900:35;
+0901:E1;
+0902:20;
+0903:C3;
+0904:C3;
+0905:B2;
+0906:07;
+0907:3E;
+0908:FF;
+0909:2E;
+090A:AF;
+090B:21;
+090C:2D;
+090D:79;
+090E:4E;
+090F:23;
+0910:AE;
+0911:47;
+0912:2E;
+0913:00;
+0914:78;
+0915:B7;
+0916:28;
+0917:1F;
+0918:7D;
+0919:21;
+091A:24;
+091B:79;
+091C:AE;
+091D:80;
+091E:47;
+091F:1F;
+0920:A8;
+0921:78;
+0922:F2;
+0923:36;
+0924:09;
+0925:C6;
+0926:80;
+0927:77;
+0928:CA;
+0929:90;
+092A:08;
+092B:CD;
+092C:DF;
+092D:09;
+092E:77;
+092F:2B;
+0930:C9;
+0931:CD;
+0932:55;
+0933:09;
+0934:2F;
+0935:E1;
+0936:B7;
+0937:E1;
+0938:F2;
+0939:78;
+093A:07;
+093B:C3;
+093C:B2;
+093D:07;
+093E:CD;
+093F:BF;
+0940:09;
+0941:78;
+0942:B7;
+0943:C8;
+0944:C6;
+0945:02;
+0946:DA;
+0947:B2;
+0948:07;
+0949:47;
+094A:CD;
+094B:16;
+094C:07;
+094D:21;
+094E:24;
+094F:79;
+0950:34;
+0951:C0;
+0952:C3;
+0953:B2;
+0954:07;
+0955:3A;
+0956:24;
+0957:79;
+0958:B7;
+0959:C8;
+095A:3A;
+095B:23;
+095C:79;
+095D:FE;
+095E:2F;
+095F:17;
+0960:9F;
+0961:C0;
+0962:3C;
+0963:C9;
+0964:06;
+0965:88;
+0966:11;
+0967:00;
+0968:00;
+0969:21;
+096A:24;
+096B:79;
+096C:4F;
+096D:70;
+096E:06;
+096F:00;
+0970:23;
+0971:36;
+0972:80;
+0973:17;
+0974:C3;
+0975:62;
+0976:07;
+0977:CD;
+0978:94;
+0979:09;
+097A:F0;
+097B:E7;
+097C:FA;
+097D:5B;
+097E:0C;
+097F:CA;
+0980:F6;
+0981:0A;
+0982:21;
+0983:23;
+0984:79;
+0985:7E;
+0986:EE;
+0987:80;
+0988:77;
+0989:C9;
+098A:CD;
+098B:94;
+098C:09;
+098D:6F;
+098E:17;
+098F:9F;
+0990:67;
+0991:C3;
+0992:9A;
+0993:0A;
+0994:E7;
+0995:CA;
+0996:F6;
+0997:0A;
+0998:F2;
+0999:55;
+099A:09;
+099B:2A;
+099C:21;
+099D:79;
+099E:7C;
+099F:B5;
+09A0:C8;
+09A1:7C;
+09A2:18;
+09A3:BB;
+09A4:EB;
+09A5:2A;
+09A6:21;
+09A7:79;
+09A8:E3;
+09A9:E5;
+09AA:2A;
+09AB:23;
+09AC:79;
+09AD:E3;
+09AE:E5;
+09AF:EB;
+09B0:C9;
+09B1:CD;
+09B2:C2;
+09B3:09;
+09B4:EB;
+09B5:22;
+09B6:21;
+09B7:79;
+09B8:60;
+09B9:69;
+09BA:22;
+09BB:23;
+09BC:79;
+09BD:EB;
+09BE:C9;
+09BF:21;
+09C0:21;
+09C1:79;
+09C2:5E;
+09C3:23;
+09C4:56;
+09C5:23;
+09C6:4E;
+09C7:23;
+09C8:46;
+09C9:23;
+09CA:C9;
+09CB:11;
+09CC:21;
+09CD:79;
+09CE:06;
+09CF:04;
+09D0:18;
+09D1:05;
+09D2:EB;
+09D3:3A;
+09D4:AF;
+09D5:78;
+09D6:47;
+09D7:1A;
+09D8:77;
+09D9:13;
+09DA:23;
+09DB:05;
+09DC:20;
+09DD:F9;
+09DE:C9;
+09DF:21;
+09E0:23;
+09E1:79;
+09E2:7E;
+09E3:07;
+09E4:37;
+09E5:1F;
+09E6:77;
+09E7:3F;
+09E8:1F;
+09E9:23;
+09EA:23;
+09EB:77;
+09EC:79;
+09ED:07;
+09EE:37;
+09EF:1F;
+09F0:4F;
+09F1:1F;
+09F2:AE;
+09F3:C9;
+09F4:21;
+09F5:27;
+09F6:79;
+09F7:11;
+09F8:D2;
+09F9:09;
+09FA:18;
+09FB:06;
+09FC:21;
+09FD:27;
+09FE:79;
+09FF:11;
+0A00:D3;
+0A01:09;
+0A02:D5;
+0A03:11;
+0A04:21;
+0A05:79;
+0A06:E7;
+0A07:D8;
+0A08:11;
+0A09:1D;
+0A0A:79;
+0A0B:C9;
+0A0C:78;
+0A0D:B7;
+0A0E:CA;
+0A0F:55;
+0A10:09;
+0A11:21;
+0A12:5E;
+0A13:09;
+0A14:E5;
+0A15:CD;
+0A16:55;
+0A17:09;
+0A18:79;
+0A19:C8;
+0A1A:21;
+0A1B:23;
+0A1C:79;
+0A1D:AE;
+0A1E:79;
+0A1F:F8;
+0A20:CD;
+0A21:26;
+0A22:0A;
+0A23:1F;
+0A24:A9;
+0A25:C9;
+0A26:23;
+0A27:78;
+0A28:BE;
+0A29:C0;
+0A2A:2B;
+0A2B:79;
+0A2C:BE;
+0A2D:C0;
+0A2E:2B;
+0A2F:7A;
+0A30:BE;
+0A31:C0;
+0A32:2B;
+0A33:7B;
+0A34:96;
+0A35:C0;
+0A36:E1;
+0A37:E1;
+0A38:C9;
+0A39:7A;
+0A3A:AC;
+0A3B:7C;
+0A3C:FA;
+0A3D:5F;
+0A3E:09;
+0A3F:BA;
+0A40:C2;
+0A41:60;
+0A42:09;
+0A43:7D;
+0A44:93;
+0A45:C2;
+0A46:60;
+0A47:09;
+0A48:C9;
+0A49:21;
+0A4A:27;
+0A4B:79;
+0A4C:CD;
+0A4D:D3;
+0A4E:09;
+0A4F:11;
+0A50:2E;
+0A51:79;
+0A52:1A;
+0A53:B7;
+0A54:CA;
+0A55:55;
+0A56:09;
+0A57:21;
+0A58:5E;
+0A59:09;
+0A5A:E5;
+0A5B:CD;
+0A5C:55;
+0A5D:09;
+0A5E:1B;
+0A5F:1A;
+0A60:4F;
+0A61:C8;
+0A62:21;
+0A63:23;
+0A64:79;
+0A65:AE;
+0A66:79;
+0A67:F8;
+0A68:13;
+0A69:23;
+0A6A:06;
+0A6B:08;
+0A6C:1A;
+0A6D:96;
+0A6E:C2;
+0A6F:23;
+0A70:0A;
+0A71:1B;
+0A72:2B;
+0A73:05;
+0A74:20;
+0A75:F6;
+0A76:C1;
+0A77:C9;
+0A78:CD;
+0A79:4F;
+0A7A:0A;
+0A7B:C2;
+0A7C:5E;
+0A7D:09;
+0A7E:C9;
+0A7F:E7;
+0A80:2A;
+0A81:21;
+0A82:79;
+0A83:F8;
+0A84:CA;
+0A85:F6;
+0A86:0A;
+0A87:D4;
+0A88:B9;
+0A89:0A;
+0A8A:21;
+0A8B:B2;
+0A8C:07;
+0A8D:E5;
+0A8E:3A;
+0A8F:24;
+0A90:79;
+0A91:FE;
+0A92:90;
+0A93:30;
+0A94:0E;
+0A95:CD;
+0A96:FB;
+0A97:0A;
+0A98:EB;
+0A99:D1;
+0A9A:22;
+0A9B:21;
+0A9C:79;
+0A9D:3E;
+0A9E:02;
+0A9F:32;
+0AA0:AF;
+0AA1:78;
+0AA2:C9;
+0AA3:01;
+0AA4:80;
+0AA5:90;
+0AA6:11;
+0AA7:00;
+0AA8:00;
+0AA9:CD;
+0AAA:0C;
+0AAB:0A;
+0AAC:C0;
+0AAD:61;
+0AAE:6A;
+0AAF:18;
+0AB0:E8;
+0AB1:E7;
+0AB2:E0;
+0AB3:FA;
+0AB4:CC;
+0AB5:0A;
+0AB6:CA;
+0AB7:F6;
+0AB8:0A;
+0AB9:CD;
+0ABA:BF;
+0ABB:09;
+0ABC:CD;
+0ABD:EF;
+0ABE:0A;
+0ABF:78;
+0AC0:B7;
+0AC1:C8;
+0AC2:CD;
+0AC3:DF;
+0AC4:09;
+0AC5:21;
+0AC6:20;
+0AC7:79;
+0AC8:46;
+0AC9:C3;
+0ACA:96;
+0ACB:07;
+0ACC:2A;
+0ACD:21;
+0ACE:79;
+0ACF:CD;
+0AD0:EF;
+0AD1:0A;
+0AD2:7C;
+0AD3:55;
+0AD4:1E;
+0AD5:00;
+0AD6:06;
+0AD7:90;
+0AD8:C3;
+0AD9:69;
+0ADA:09;
+0ADB:E7;
+0ADC:D0;
+0ADD:CA;
+0ADE:F6;
+0ADF:0A;
+0AE0:FC;
+0AE1:CC;
+0AE2:0A;
+0AE3:21;
+0AE4:00;
+0AE5:00;
+0AE6:22;
+0AE7:1D;
+0AE8:79;
+0AE9:22;
+0AEA:1F;
+0AEB:79;
+0AEC:3E;
+0AED:08;
+0AEE:01;
+0AEF:3E;
+0AF0:04;
+0AF1:C3;
+0AF2:9F;
+0AF3:0A;
+0AF4:E7;
+0AF5:C8;
+0AF6:1E;
+0AF7:18;
+0AF8:C3;
+0AF9:A2;
+0AFA:19;
+0AFB:47;
+0AFC:4F;
+0AFD:57;
+0AFE:5F;
+0AFF:B7;
+0B00:C8;
+0B01:E5;
+0B02:CD;
+0B03:BF;
+0B04:09;
+0B05:CD;
+0B06:DF;
+0B07:09;
+0B08:AE;
+0B09:67;
+0B0A:FC;
+0B0B:1F;
+0B0C:0B;
+0B0D:3E;
+0B0E:98;
+0B0F:90;
+0B10:CD;
+0B11:D7;
+0B12:07;
+0B13:7C;
+0B14:17;
+0B15:DC;
+0B16:A8;
+0B17:07;
+0B18:06;
+0B19:00;
+0B1A:DC;
+0B1B:C3;
+0B1C:07;
+0B1D:E1;
+0B1E:C9;
+0B1F:1B;
+0B20:7A;
+0B21:A3;
+0B22:3C;
+0B23:C0;
+0B24:0B;
+0B25:C9;
+0B26:E7;
+0B27:F8;
+0B28:CD;
+0B29:55;
+0B2A:09;
+0B2B:F2;
+0B2C:37;
+0B2D:0B;
+0B2E:CD;
+0B2F:82;
+0B30:09;
+0B31:CD;
+0B32:37;
+0B33:0B;
+0B34:C3;
+0B35:7B;
+0B36:09;
+0B37:E7;
+0B38:F8;
+0B39:30;
+0B3A:1E;
+0B3B:28;
+0B3C:B9;
+0B3D:CD;
+0B3E:8E;
+0B3F:0A;
+0B40:21;
+0B41:24;
+0B42:79;
+0B43:7E;
+0B44:FE;
+0B45:98;
+0B46:3A;
+0B47:21;
+0B48:79;
+0B49:D0;
+0B4A:7E;
+0B4B:CD;
+0B4C:FB;
+0B4D:0A;
+0B4E:36;
+0B4F:98;
+0B50:7B;
+0B51:F5;
+0B52:79;
+0B53:17;
+0B54:CD;
+0B55:62;
+0B56:07;
+0B57:F1;
+0B58:C9;
+0B59:21;
+0B5A:24;
+0B5B:79;
+0B5C:7E;
+0B5D:FE;
+0B5E:90;
+0B5F:DA;
+0B60:7F;
+0B61:0A;
+0B62:20;
+0B63:14;
+0B64:4F;
+0B65:2B;
+0B66:7E;
+0B67:EE;
+0B68:80;
+0B69:06;
+0B6A:06;
+0B6B:2B;
+0B6C:B6;
+0B6D:05;
+0B6E:20;
+0B6F:FB;
+0B70:B7;
+0B71:21;
+0B72:00;
+0B73:80;
+0B74:CA;
+0B75:9A;
+0B76:0A;
+0B77:79;
+0B78:FE;
+0B79:B8;
+0B7A:D0;
+0B7B:F5;
+0B7C:CD;
+0B7D:BF;
+0B7E:09;
+0B7F:CD;
+0B80:DF;
+0B81:09;
+0B82:AE;
+0B83:2B;
+0B84:36;
+0B85:B8;
+0B86:F5;
+0B87:FC;
+0B88:A0;
+0B89:0B;
+0B8A:21;
+0B8B:23;
+0B8C:79;
+0B8D:3E;
+0B8E:B8;
+0B8F:90;
+0B90:CD;
+0B91:69;
+0B92:0D;
+0B93:F1;
+0B94:FC;
+0B95:20;
+0B96:0D;
+0B97:AF;
+0B98:32;
+0B99:1C;
+0B9A:79;
+0B9B:F1;
+0B9C:D0;
+0B9D:C3;
+0B9E:D8;
+0B9F:0C;
+0BA0:21;
+0BA1:1D;
+0BA2:79;
+0BA3:7E;
+0BA4:35;
+0BA5:B7;
+0BA6:23;
+0BA7:28;
+0BA8:FA;
+0BA9:C9;
+0BAA:E5;
+0BAB:21;
+0BAC:00;
+0BAD:00;
+0BAE:78;
+0BAF:B1;
+0BB0:28;
+0BB1:12;
+0BB2:3E;
+0BB3:10;
+0BB4:29;
+0BB5:DA;
+0BB6:3D;
+0BB7:27;
+0BB8:EB;
+0BB9:29;
+0BBA:EB;
+0BBB:30;
+0BBC:04;
+0BBD:09;
+0BBE:DA;
+0BBF:3D;
+0BC0:27;
+0BC1:3D;
+0BC2:20;
+0BC3:F0;
+0BC4:EB;
+0BC5:E1;
+0BC6:C9;
+0BC7:7C;
+0BC8:17;
+0BC9:9F;
+0BCA:47;
+0BCB:CD;
+0BCC:51;
+0BCD:0C;
+0BCE:79;
+0BCF:98;
+0BD0:18;
+0BD1:03;
+0BD2:7C;
+0BD3:17;
+0BD4:9F;
+0BD5:47;
+0BD6:E5;
+0BD7:7A;
+0BD8:17;
+0BD9:9F;
+0BDA:19;
+0BDB:88;
+0BDC:0F;
+0BDD:AC;
+0BDE:F2;
+0BDF:99;
+0BE0:0A;
+0BE1:C5;
+0BE2:EB;
+0BE3:CD;
+0BE4:CF;
+0BE5:0A;
+0BE6:F1;
+0BE7:E1;
+0BE8:CD;
+0BE9:A4;
+0BEA:09;
+0BEB:EB;
+0BEC:CD;
+0BED:6B;
+0BEE:0C;
+0BEF:C3;
+0BF0:8F;
+0BF1:0F;
+0BF2:7C;
+0BF3:B5;
+0BF4:CA;
+0BF5:9A;
+0BF6:0A;
+0BF7:E5;
+0BF8:D5;
+0BF9:CD;
+0BFA:45;
+0BFB:0C;
+0BFC:C5;
+0BFD:44;
+0BFE:4D;
+0BFF:21;
+0C00:00;
+0C01:00;
+0C02:3E;
+0C03:10;
+0C04:29;
+0C05:38;
+0C06:1F;
+0C07:EB;
+0C08:29;
+0C09:EB;
+0C0A:30;
+0C0B:04;
+0C0C:09;
+0C0D:DA;
+0C0E:26;
+0C0F:0C;
+0C10:3D;
+0C11:20;
+0C12:F1;
+0C13:C1;
+0C14:D1;
+0C15:7C;
+0C16:B7;
+0C17:FA;
+0C18:1F;
+0C19:0C;
+0C1A:D1;
+0C1B:78;
+0C1C:C3;
+0C1D:4D;
+0C1E:0C;
+0C1F:EE;
+0C20:80;
+0C21:B5;
+0C22:28;
+0C23:13;
+0C24:EB;
+0C25:01;
+0C26:C1;
+0C27:E1;
+0C28:CD;
+0C29:CF;
+0C2A:0A;
+0C2B:E1;
+0C2C:CD;
+0C2D:A4;
+0C2E:09;
+0C2F:CD;
+0C30:CF;
+0C31:0A;
+0C32:C1;
+0C33:D1;
+0C34:C3;
+0C35:47;
+0C36:08;
+0C37:78;
+0C38:B7;
+0C39:C1;
+0C3A:FA;
+0C3B:9A;
+0C3C:0A;
+0C3D:D5;
+0C3E:CD;
+0C3F:CF;
+0C40:0A;
+0C41:D1;
+0C42:C3;
+0C43:82;
+0C44:09;
+0C45:7C;
+0C46:AA;
+0C47:47;
+0C48:CD;
+0C49:4C;
+0C4A:0C;
+0C4B:EB;
+0C4C:7C;
+0C4D:B7;
+0C4E:F2;
+0C4F:9A;
+0C50:0A;
+0C51:AF;
+0C52:4F;
+0C53:95;
+0C54:6F;
+0C55:79;
+0C56:9C;
+0C57:67;
+0C58:C3;
+0C59:9A;
+0C5A:0A;
+0C5B:2A;
+0C5C:21;
+0C5D:79;
+0C5E:CD;
+0C5F:51;
+0C60:0C;
+0C61:7C;
+0C62:EE;
+0C63:80;
+0C64:B5;
+0C65:C0;
+0C66:EB;
+0C67:CD;
+0C68:EF;
+0C69:0A;
+0C6A:AF;
+0C6B:06;
+0C6C:98;
+0C6D:C3;
+0C6E:69;
+0C6F:09;
+0C70:21;
+0C71:2D;
+0C72:79;
+0C73:7E;
+0C74:EE;
+0C75:80;
+0C76:77;
+0C77:21;
+0C78:2E;
+0C79:79;
+0C7A:7E;
+0C7B:B7;
+0C7C:C8;
+0C7D:47;
+0C7E:2B;
+0C7F:4E;
+0C80:11;
+0C81:24;
+0C82:79;
+0C83:1A;
+0C84:B7;
+0C85:CA;
+0C86:F4;
+0C87:09;
+0C88:90;
+0C89:30;
+0C8A:16;
+0C8B:2F;
+0C8C:3C;
+0C8D:F5;
+0C8E:0E;
+0C8F:08;
+0C90:23;
+0C91:E5;
+0C92:1A;
+0C93:46;
+0C94:77;
+0C95:78;
+0C96:12;
+0C97:1B;
+0C98:2B;
+0C99:0D;
+0C9A:20;
+0C9B:F6;
+0C9C:E1;
+0C9D:46;
+0C9E:2B;
+0C9F:4E;
+0CA0:F1;
+0CA1:FE;
+0CA2:39;
+0CA3:D0;
+0CA4:F5;
+0CA5:CD;
+0CA6:DF;
+0CA7:09;
+0CA8:23;
+0CA9:36;
+0CAA:00;
+0CAB:47;
+0CAC:F1;
+0CAD:21;
+0CAE:2D;
+0CAF:79;
+0CB0:CD;
+0CB1:69;
+0CB2:0D;
+0CB3:3A;
+0CB4:26;
+0CB5:79;
+0CB6:32;
+0CB7:1C;
+0CB8:79;
+0CB9:78;
+0CBA:B7;
+0CBB:F2;
+0CBC:CF;
+0CBD:0C;
+0CBE:CD;
+0CBF:33;
+0CC0:0D;
+0CC1:D2;
+0CC2:0E;
+0CC3:0D;
+0CC4:EB;
+0CC5:34;
+0CC6:CA;
+0CC7:B2;
+0CC8:07;
+0CC9:CD;
+0CCA:90;
+0CCB:0D;
+0CCC:C3;
+0CCD:0E;
+0CCE:0D;
+0CCF:CD;
+0CD0:45;
+0CD1:0D;
+0CD2:21;
+0CD3:25;
+0CD4:79;
+0CD5:DC;
+0CD6:57;
+0CD7:0D;
+0CD8:AF;
+0CD9:47;
+0CDA:3A;
+0CDB:23;
+0CDC:79;
+0CDD:B7;
+0CDE:20;
+0CDF:1E;
+0CE0:21;
+0CE1:1C;
+0CE2:79;
+0CE3:0E;
+0CE4:08;
+0CE5:56;
+0CE6:77;
+0CE7:7A;
+0CE8:23;
+0CE9:0D;
+0CEA:20;
+0CEB:F9;
+0CEC:78;
+0CED:D6;
+0CEE:08;
+0CEF:FE;
+0CF0:C0;
+0CF1:20;
+0CF2:E6;
+0CF3:C3;
+0CF4:78;
+0CF5:07;
+0CF6:05;
+0CF7:21;
+0CF8:1C;
+0CF9:79;
+0CFA:CD;
+0CFB:97;
+0CFC:0D;
+0CFD:B7;
+0CFE:F2;
+0CFF:F6;
+0D00:0C;
+0D01:78;
+0D02:B7;
+0D03:28;
+0D04:09;
+0D05:21;
+0D06:24;
+0D07:79;
+0D08:86;
+0D09:77;
+0D0A:D2;
+0D0B:78;
+0D0C:07;
+0D0D:C8;
+0D0E:3A;
+0D0F:1C;
+0D10:79;
+0D11:B7;
+0D12:FC;
+0D13:20;
+0D14:0D;
+0D15:21;
+0D16:25;
+0D17:79;
+0D18:7E;
+0D19:E6;
+0D1A:80;
+0D1B:2B;
+0D1C:2B;
+0D1D:AE;
+0D1E:77;
+0D1F:C9;
+0D20:21;
+0D21:1D;
+0D22:79;
+0D23:06;
+0D24:07;
+0D25:34;
+0D26:C0;
+0D27:23;
+0D28:05;
+0D29:20;
+0D2A:FA;
+0D2B:34;
+0D2C:CA;
+0D2D:B2;
+0D2E:07;
+0D2F:2B;
+0D30:36;
+0D31:80;
+0D32:C9;
+0D33:21;
+0D34:27;
+0D35:79;
+0D36:11;
+0D37:1D;
+0D38:79;
+0D39:0E;
+0D3A:07;
+0D3B:AF;
+0D3C:1A;
+0D3D:8E;
+0D3E:12;
+0D3F:13;
+0D40:23;
+0D41:0D;
+0D42:20;
+0D43:F8;
+0D44:C9;
+0D45:21;
+0D46:27;
+0D47:79;
+0D48:11;
+0D49:1D;
+0D4A:79;
+0D4B:0E;
+0D4C:07;
+0D4D:AF;
+0D4E:1A;
+0D4F:9E;
+0D50:12;
+0D51:13;
+0D52:23;
+0D53:0D;
+0D54:20;
+0D55:F8;
+0D56:C9;
+0D57:7E;
+0D58:2F;
+0D59:77;
+0D5A:21;
+0D5B:1C;
+0D5C:79;
+0D5D:06;
+0D5E:08;
+0D5F:AF;
+0D60:4F;
+0D61:79;
+0D62:9E;
+0D63:77;
+0D64:23;
+0D65:05;
+0D66:20;
+0D67:F9;
+0D68:C9;
+0D69:71;
+0D6A:E5;
+0D6B:D6;
+0D6C:08;
+0D6D:38;
+0D6E:0E;
+0D6F:E1;
+0D70:E5;
+0D71:11;
+0D72:00;
+0D73:08;
+0D74:4E;
+0D75:73;
+0D76:59;
+0D77:2B;
+0D78:15;
+0D79:20;
+0D7A:F9;
+0D7B:18;
+0D7C:EE;
+0D7D:C6;
+0D7E:09;
+0D7F:57;
+0D80:AF;
+0D81:E1;
+0D82:15;
+0D83:C8;
+0D84:E5;
+0D85:1E;
+0D86:08;
+0D87:7E;
+0D88:1F;
+0D89:77;
+0D8A:2B;
+0D8B:1D;
+0D8C:20;
+0D8D:F9;
+0D8E:18;
+0D8F:F0;
+0D90:21;
+0D91:23;
+0D92:79;
+0D93:16;
+0D94:01;
+0D95:18;
+0D96:ED;
+0D97:0E;
+0D98:08;
+0D99:7E;
+0D9A:17;
+0D9B:77;
+0D9C:23;
+0D9D:0D;
+0D9E:20;
+0D9F:F9;
+0DA0:C9;
+0DA1:CD;
+0DA2:55;
+0DA3:09;
+0DA4:C8;
+0DA5:CD;
+0DA6:0A;
+0DA7:09;
+0DA8:CD;
+0DA9:39;
+0DAA:0E;
+0DAB:71;
+0DAC:13;
+0DAD:06;
+0DAE:07;
+0DAF:1A;
+0DB0:13;
+0DB1:B7;
+0DB2:D5;
+0DB3:28;
+0DB4:17;
+0DB5:0E;
+0DB6:08;
+0DB7:C5;
+0DB8:1F;
+0DB9:47;
+0DBA:DC;
+0DBB:33;
+0DBC:0D;
+0DBD:CD;
+0DBE:90;
+0DBF:0D;
+0DC0:78;
+0DC1:C1;
+0DC2:0D;
+0DC3:20;
+0DC4:F2;
+0DC5:D1;
+0DC6:05;
+0DC7:20;
+0DC8:E6;
+0DC9:C3;
+0DCA:D8;
+0DCB:0C;
+0DCC:21;
+0DCD:23;
+0DCE:79;
+0DCF:CD;
+0DD0:70;
+0DD1:0D;
+0DD2:18;
+0DD3:F1;
+0DD4:00;
+0DD5:00;
+0DD6:00;
+0DD7:00;
+0DD8:00;
+0DD9:00;
+0DDA:20;
+0DDB:84;
+0DDC:11;
+0DDD:D4;
+0DDE:0D;
+0DDF:21;
+0DE0:27;
+0DE1:79;
+0DE2:CD;
+0DE3:D3;
+0DE4:09;
+0DE5:3A;
+0DE6:2E;
+0DE7:79;
+0DE8:B7;
+0DE9:CA;
+0DEA:9A;
+0DEB:19;
+0DEC:CD;
+0DED:07;
+0DEE:09;
+0DEF:34;
+0DF0:34;
+0DF1:CD;
+0DF2:39;
+0DF3:0E;
+0DF4:21;
+0DF5:51;
+0DF6:79;
+0DF7:71;
+0DF8:41;
+0DF9:11;
+0DFA:4A;
+0DFB:79;
+0DFC:21;
+0DFD:27;
+0DFE:79;
+0DFF:CD;
+0E00:4B;
+0E01:0D;
+0E02:1A;
+0E03:99;
+0E04:3F;
+0E05:38;
+0E06:0B;
+0E07:11;
+0E08:4A;
+0E09:79;
+0E0A:21;
+0E0B:27;
+0E0C:79;
+0E0D:CD;
+0E0E:39;
+0E0F:0D;
+0E10:AF;
+0E11:DA;
+0E12:12;
+0E13:04;
+0E14:3A;
+0E15:23;
+0E16:79;
+0E17:3C;
+0E18:3D;
+0E19:1F;
+0E1A:FA;
+0E1B:11;
+0E1C:0D;
+0E1D:17;
+0E1E:21;
+0E1F:1D;
+0E20:79;
+0E21:0E;
+0E22:07;
+0E23:CD;
+0E24:99;
+0E25:0D;
+0E26:21;
+0E27:4A;
+0E28:79;
+0E29:CD;
+0E2A:97;
+0E2B:0D;
+0E2C:78;
+0E2D:B7;
+0E2E:20;
+0E2F:C9;
+0E30:21;
+0E31:24;
+0E32:79;
+0E33:35;
+0E34:20;
+0E35:C3;
+0E36:C3;
+0E37:B2;
+0E38:07;
+0E39:79;
+0E3A:32;
+0E3B:2D;
+0E3C:79;
+0E3D:2B;
+0E3E:11;
+0E3F:50;
+0E40:79;
+0E41:01;
+0E42:00;
+0E43:07;
+0E44:7E;
+0E45:12;
+0E46:71;
+0E47:1B;
+0E48:2B;
+0E49:05;
+0E4A:20;
+0E4B:F8;
+0E4C:C9;
+0E4D:CD;
+0E4E:FC;
+0E4F:09;
+0E50:EB;
+0E51:2B;
+0E52:7E;
+0E53:B7;
+0E54:C8;
+0E55:C6;
+0E56:02;
+0E57:DA;
+0E58:B2;
+0E59:07;
+0E5A:77;
+0E5B:E5;
+0E5C:CD;
+0E5D:77;
+0E5E:0C;
+0E5F:E1;
+0E60:34;
+0E61:C0;
+0E62:C3;
+0E63:B2;
+0E64:07;
+0E65:CD;
+0E66:78;
+0E67:07;
+0E68:CD;
+0E69:EC;
+0E6A:0A;
+0E6B:F6;
+0E6C:AF;
+0E6D:EB;
+0E6E:01;
+0E6F:FF;
+0E70:00;
+0E71:60;
+0E72:68;
+0E73:CC;
+0E74:9A;
+0E75:0A;
+0E76:EB;
+0E77:7E;
+0E78:FE;
+0E79:2D;
+0E7A:F5;
+0E7B:CA;
+0E7C:83;
+0E7D:0E;
+0E7E:FE;
+0E7F:2B;
+0E80:28;
+0E81:01;
+0E82:2B;
+0E83:D7;
+0E84:DA;
+0E85:29;
+0E86:0F;
+0E87:FE;
+0E88:2E;
+0E89:CA;
+0E8A:E4;
+0E8B:0E;
+0E8C:FE;
+0E8D:45;
+0E8E:28;
+0E8F:14;
+0E90:FE;
+0E91:25;
+0E92:CA;
+0E93:EE;
+0E94:0E;
+0E95:FE;
+0E96:23;
+0E97:CA;
+0E98:F5;
+0E99:0E;
+0E9A:FE;
+0E9B:21;
+0E9C:CA;
+0E9D:F6;
+0E9E:0E;
+0E9F:FE;
+0EA0:44;
+0EA1:20;
+0EA2:24;
+0EA3:B7;
+0EA4:CD;
+0EA5:FB;
+0EA6:0E;
+0EA7:E5;
+0EA8:21;
+0EA9:BD;
+0EAA:0E;
+0EAB:E3;
+0EAC:D7;
+0EAD:15;
+0EAE:FE;
+0EAF:CE;
+0EB0:C8;
+0EB1:FE;
+0EB2:2D;
+0EB3:C8;
+0EB4:14;
+0EB5:FE;
+0EB6:CD;
+0EB7:C8;
+0EB8:FE;
+0EB9:2B;
+0EBA:C8;
+0EBB:2B;
+0EBC:F1;
+0EBD:D7;
+0EBE:DA;
+0EBF:94;
+0EC0:0F;
+0EC1:14;
+0EC2:20;
+0EC3:03;
+0EC4:AF;
+0EC5:93;
+0EC6:5F;
+0EC7:E5;
+0EC8:7B;
+0EC9:90;
+0ECA:F4;
+0ECB:0A;
+0ECC:0F;
+0ECD:FC;
+0ECE:18;
+0ECF:0F;
+0ED0:20;
+0ED1:F8;
+0ED2:E1;
+0ED3:F1;
+0ED4:E5;
+0ED5:CC;
+0ED6:7B;
+0ED7:09;
+0ED8:E1;
+0ED9:E7;
+0EDA:E8;
+0EDB:E5;
+0EDC:21;
+0EDD:90;
+0EDE:08;
+0EDF:E5;
+0EE0:CD;
+0EE1:A3;
+0EE2:0A;
+0EE3:C9;
+0EE4:E7;
+0EE5:0C;
+0EE6:20;
+0EE7:DF;
+0EE8:DC;
+0EE9:FB;
+0EEA:0E;
+0EEB:C3;
+0EEC:83;
+0EED:0E;
+0EEE:E7;
+0EEF:F2;
+0EF0:97;
+0EF1:19;
+0EF2:23;
+0EF3:18;
+0EF4:D2;
+0EF5:B7;
+0EF6:CD;
+0EF7:FB;
+0EF8:0E;
+0EF9:18;
+0EFA:F7;
+0EFB:E5;
+0EFC:D5;
+0EFD:C5;
+0EFE:F5;
+0EFF:CC;
+0F00:B1;
+0F01:0A;
+0F02:F1;
+0F03:C4;
+0F04:DB;
+0F05:0A;
+0F06:C1;
+0F07:D1;
+0F08:E1;
+0F09:C9;
+0F0A:C8;
+0F0B:F5;
+0F0C:E7;
+0F0D:F5;
+0F0E:E4;
+0F0F:3E;
+0F10:09;
+0F11:F1;
+0F12:EC;
+0F13:4D;
+0F14:0E;
+0F15:F1;
+0F16:3D;
+0F17:C9;
+0F18:D5;
+0F19:E5;
+0F1A:F5;
+0F1B:E7;
+0F1C:F5;
+0F1D:E4;
+0F1E:97;
+0F1F:08;
+0F20:F1;
+0F21:EC;
+0F22:DC;
+0F23:0D;
+0F24:F1;
+0F25:E1;
+0F26:D1;
+0F27:3C;
+0F28:C9;
+0F29:D5;
+0F2A:78;
+0F2B:89;
+0F2C:47;
+0F2D:C5;
+0F2E:E5;
+0F2F:7E;
+0F30:D6;
+0F31:30;
+0F32:F5;
+0F33:E7;
+0F34:F2;
+0F35:5D;
+0F36:0F;
+0F37:2A;
+0F38:21;
+0F39:79;
+0F3A:11;
+0F3B:CD;
+0F3C:0C;
+0F3D:DF;
+0F3E:30;
+0F3F:19;
+0F40:54;
+0F41:5D;
+0F42:29;
+0F43:29;
+0F44:19;
+0F45:29;
+0F46:F1;
+0F47:4F;
+0F48:09;
+0F49:7C;
+0F4A:B7;
+0F4B:FA;
+0F4C:57;
+0F4D:0F;
+0F4E:22;
+0F4F:21;
+0F50:79;
+0F51:E1;
+0F52:C1;
+0F53:D1;
+0F54:C3;
+0F55:83;
+0F56:0E;
+0F57:79;
+0F58:F5;
+0F59:CD;
+0F5A:CC;
+0F5B:0A;
+0F5C:37;
+0F5D:30;
+0F5E:18;
+0F5F:01;
+0F60:74;
+0F61:94;
+0F62:11;
+0F63:00;
+0F64:24;
+0F65:CD;
+0F66:0C;
+0F67:0A;
+0F68:F2;
+0F69:74;
+0F6A:0F;
+0F6B:CD;
+0F6C:3E;
+0F6D:09;
+0F6E:F1;
+0F6F:CD;
+0F70:89;
+0F71:0F;
+0F72:18;
+0F73:DD;
+0F74:CD;
+0F75:E3;
+0F76:0A;
+0F77:CD;
+0F78:4D;
+0F79:0E;
+0F7A:CD;
+0F7B:FC;
+0F7C:09;
+0F7D:F1;
+0F7E:CD;
+0F7F:64;
+0F80:09;
+0F81:CD;
+0F82:E3;
+0F83:0A;
+0F84:CD;
+0F85:77;
+0F86:0C;
+0F87:18;
+0F88:C8;
+0F89:CD;
+0F8A:A4;
+0F8B:09;
+0F8C:CD;
+0F8D:64;
+0F8E:09;
+0F8F:C1;
+0F90:D1;
+0F91:C3;
+0F92:16;
+0F93:07;
+0F94:7B;
+0F95:FE;
+0F96:0A;
+0F97:30;
+0F98:09;
+0F99:07;
+0F9A:07;
+0F9B:83;
+0F9C:07;
+0F9D:86;
+0F9E:D6;
+0F9F:30;
+0FA0:5F;
+0FA1:FA;
+0FA2:1E;
+0FA3:32;
+0FA4:C3;
+0FA5:BD;
+0FA6:0E;
+0FA7:E5;
+0FA8:21;
+0FA9:24;
+0FAA:19;
+0FAB:CD;
+0FAC:A7;
+0FAD:28;
+0FAE:E1;
+0FAF:CD;
+0FB0:9A;
+0FB1:0A;
+0FB2:AF;
+0FB3:CD;
+0FB4:34;
+0FB5:10;
+0FB6:B6;
+0FB7:CD;
+0FB8:D9;
+0FB9:0F;
+0FBA:C3;
+0FBB:A6;
+0FBC:28;
+0FBD:AF;
+0FBE:CD;
+0FBF:34;
+0FC0:10;
+0FC1:E6;
+0FC2:08;
+0FC3:28;
+0FC4:02;
+0FC5:36;
+0FC6:2B;
+0FC7:EB;
+0FC8:CD;
+0FC9:94;
+0FCA:09;
+0FCB:EB;
+0FCC:F2;
+0FCD:D9;
+0FCE:0F;
+0FCF:36;
+0FD0:2D;
+0FD1:C5;
+0FD2:E5;
+0FD3:CD;
+0FD4:7B;
+0FD5:09;
+0FD6:E1;
+0FD7:C1;
+0FD8:B4;
+0FD9:23;
+0FDA:36;
+0FDB:30;
+0FDC:3A;
+0FDD:D8;
+0FDE:78;
+0FDF:57;
+0FE0:17;
+0FE1:3A;
+0FE2:AF;
+0FE3:78;
+0FE4:DA;
+0FE5:9A;
+0FE6:10;
+0FE7:CA;
+0FE8:92;
+0FE9:10;
+0FEA:FE;
+0FEB:04;
+0FEC:D2;
+0FED:3D;
+0FEE:10;
+0FEF:01;
+0FF0:00;
+0FF1:00;
+0FF2:CD;
+0FF3:2F;
+0FF4:13;
+0FF5:21;
+0FF6:30;
+0FF7:79;
+0FF8:46;
+0FF9:0E;
+0FFA:20;
+0FFB:3A;
+0FFC:D8;
+0FFD:78;
+0FFE:5F;
+0FFF:E6;
+1000:20;
+1001:28;
+1002:07;
+1003:78;
+1004:B9;
+1005:0E;
+1006:2A;
+1007:20;
+1008:01;
+1009:41;
+100A:71;
+100B:D7;
+100C:28;
+100D:14;
+100E:FE;
+100F:45;
+1010:28;
+1011:10;
+1012:FE;
+1013:44;
+1014:28;
+1015:0C;
+1016:FE;
+1017:30;
+1018:28;
+1019:F0;
+101A:FE;
+101B:2C;
+101C:28;
+101D:EC;
+101E:FE;
+101F:2E;
+1020:20;
+1021:03;
+1022:2B;
+1023:36;
+1024:30;
+1025:7B;
+1026:E6;
+1027:10;
+1028:28;
+1029:03;
+102A:2B;
+102B:36;
+102C:24;
+102D:7B;
+102E:E6;
+102F:04;
+1030:C0;
+1031:2B;
+1032:70;
+1033:C9;
+1034:32;
+1035:D8;
+1036:78;
+1037:21;
+1038:30;
+1039:79;
+103A:36;
+103B:20;
+103C:C9;
+103D:FE;
+103E:05;
+103F:E5;
+1040:DE;
+1041:00;
+1042:17;
+1043:57;
+1044:14;
+1045:CD;
+1046:01;
+1047:12;
+1048:01;
+1049:00;
+104A:03;
+104B:82;
+104C:FA;
+104D:57;
+104E:10;
+104F:14;
+1050:BA;
+1051:30;
+1052:04;
+1053:3C;
+1054:47;
+1055:3E;
+1056:02;
+1057:D6;
+1058:02;
+1059:E1;
+105A:F5;
+105B:CD;
+105C:91;
+105D:12;
+105E:36;
+105F:30;
+1060:CC;
+1061:C9;
+1062:09;
+1063:CD;
+1064:A4;
+1065:12;
+1066:2B;
+1067:7E;
+1068:FE;
+1069:30;
+106A:28;
+106B:FA;
+106C:FE;
+106D:2E;
+106E:C4;
+106F:C9;
+1070:09;
+1071:F1;
+1072:28;
+1073:1F;
+1074:F5;
+1075:E7;
+1076:3E;
+1077:22;
+1078:8F;
+1079:77;
+107A:23;
+107B:F1;
+107C:36;
+107D:2B;
+107E:F2;
+107F:85;
+1080:10;
+1081:36;
+1082:2D;
+1083:2F;
+1084:3C;
+1085:06;
+1086:2F;
+1087:04;
+1088:D6;
+1089:0A;
+108A:30;
+108B:FB;
+108C:C6;
+108D:3A;
+108E:23;
+108F:70;
+1090:23;
+1091:77;
+1092:23;
+1093:36;
+1094:00;
+1095:EB;
+1096:21;
+1097:30;
+1098:79;
+1099:C9;
+109A:23;
+109B:C5;
+109C:FE;
+109D:04;
+109E:7A;
+109F:D2;
+10A0:09;
+10A1:11;
+10A2:1F;
+10A3:DA;
+10A4:A3;
+10A5:11;
+10A6:01;
+10A7:03;
+10A8:06;
+10A9:CD;
+10AA:89;
+10AB:12;
+10AC:D1;
+10AD:7A;
+10AE:D6;
+10AF:05;
+10B0:F4;
+10B1:69;
+10B2:12;
+10B3:CD;
+10B4:2F;
+10B5:13;
+10B6:7B;
+10B7:B7;
+10B8:CC;
+10B9:2F;
+10BA:09;
+10BB:3D;
+10BC:F4;
+10BD:69;
+10BE:12;
+10BF:E5;
+10C0:CD;
+10C1:F5;
+10C2:0F;
+10C3:E1;
+10C4:28;
+10C5:02;
+10C6:70;
+10C7:23;
+10C8:36;
+10C9:00;
+10CA:21;
+10CB:2F;
+10CC:79;
+10CD:23;
+10CE:3A;
+10CF:F3;
+10D0:78;
+10D1:95;
+10D2:92;
+10D3:C8;
+10D4:7E;
+10D5:FE;
+10D6:20;
+10D7:28;
+10D8:F4;
+10D9:FE;
+10DA:2A;
+10DB:28;
+10DC:F0;
+10DD:2B;
+10DE:E5;
+10DF:F5;
+10E0:01;
+10E1:DF;
+10E2:10;
+10E3:C5;
+10E4:D7;
+10E5:FE;
+10E6:2D;
+10E7:C8;
+10E8:FE;
+10E9:2B;
+10EA:C8;
+10EB:FE;
+10EC:24;
+10ED:C8;
+10EE:C1;
+10EF:FE;
+10F0:30;
+10F1:20;
+10F2:0F;
+10F3:23;
+10F4:D7;
+10F5:30;
+10F6:0B;
+10F7:2B;
+10F8:01;
+10F9:2B;
+10FA:77;
+10FB:F1;
+10FC:28;
+10FD:FB;
+10FE:C1;
+10FF:C3;
+1100:CE;
+1101:10;
+1102:F1;
+1103:28;
+1104:FD;
+1105:E1;
+1106:36;
+1107:25;
+1108:C9;
+1109:E5;
+110A:1F;
+110B:DA;
+110C:AA;
+110D:11;
+110E:28;
+110F:14;
+1110:11;
+1111:84;
+1112:13;
+1113:CD;
+1114:49;
+1115:0A;
+1116:16;
+1117:10;
+1118:FA;
+1119:32;
+111A:11;
+111B:E1;
+111C:C1;
+111D:CD;
+111E:BD;
+111F:0F;
+1120:2B;
+1121:36;
+1122:25;
+1123:C9;
+1124:01;
+1125:0E;
+1126:B6;
+1127:11;
+1128:CA;
+1129:1B;
+112A:CD;
+112B:0C;
+112C:0A;
+112D:F2;
+112E:1B;
+112F:11;
+1130:16;
+1131:06;
+1132:CD;
+1133:55;
+1134:09;
+1135:C4;
+1136:01;
+1137:12;
+1138:E1;
+1139:C1;
+113A:FA;
+113B:57;
+113C:11;
+113D:C5;
+113E:5F;
+113F:78;
+1140:92;
+1141:93;
+1142:F4;
+1143:69;
+1144:12;
+1145:CD;
+1146:7D;
+1147:12;
+1148:CD;
+1149:A4;
+114A:12;
+114B:B3;
+114C:C4;
+114D:77;
+114E:12;
+114F:B3;
+1150:C4;
+1151:91;
+1152:12;
+1153:D1;
+1154:C3;
+1155:B6;
+1156:10;
+1157:5F;
+1158:79;
+1159:B7;
+115A:C4;
+115B:16;
+115C:0F;
+115D:83;
+115E:FA;
+115F:62;
+1160:11;
+1161:AF;
+1162:C5;
+1163:F5;
+1164:FC;
+1165:18;
+1166:0F;
+1167:FA;
+1168:64;
+1169:11;
+116A:C1;
+116B:7B;
+116C:90;
+116D:C1;
+116E:5F;
+116F:82;
+1170:78;
+1171:FA;
+1172:7F;
+1173:11;
+1174:92;
+1175:93;
+1176:F4;
+1177:69;
+1178:12;
+1179:C5;
+117A:CD;
+117B:7D;
+117C:12;
+117D:18;
+117E:11;
+117F:CD;
+1180:69;
+1181:12;
+1182:79;
+1183:CD;
+1184:94;
+1185:12;
+1186:4F;
+1187:AF;
+1188:92;
+1189:93;
+118A:CD;
+118B:69;
+118C:12;
+118D:C5;
+118E:47;
+118F:4F;
+1190:CD;
+1191:A4;
+1192:12;
+1193:C1;
+1194:B1;
+1195:20;
+1196:03;
+1197:2A;
+1198:F3;
+1199:78;
+119A:83;
+119B:3D;
+119C:F4;
+119D:69;
+119E:12;
+119F:50;
+11A0:C3;
+11A1:BF;
+11A2:10;
+11A3:E5;
+11A4:D5;
+11A5:CD;
+11A6:CC;
+11A7:0A;
+11A8:D1;
+11A9:AF;
+11AA:CA;
+11AB:B0;
+11AC:11;
+11AD:1E;
+11AE:10;
+11AF:01;
+11B0:1E;
+11B1:06;
+11B2:CD;
+11B3:55;
+11B4:09;
+11B5:37;
+11B6:C4;
+11B7:01;
+11B8:12;
+11B9:E1;
+11BA:C1;
+11BB:F5;
+11BC:79;
+11BD:B7;
+11BE:F5;
+11BF:C4;
+11C0:16;
+11C1:0F;
+11C2:80;
+11C3:4F;
+11C4:7A;
+11C5:E6;
+11C6:04;
+11C7:FE;
+11C8:01;
+11C9:9F;
+11CA:57;
+11CB:81;
+11CC:4F;
+11CD:93;
+11CE:F5;
+11CF:C5;
+11D0:FC;
+11D1:18;
+11D2:0F;
+11D3:FA;
+11D4:D0;
+11D5:11;
+11D6:C1;
+11D7:F1;
+11D8:C5;
+11D9:F5;
+11DA:FA;
+11DB:DE;
+11DC:11;
+11DD:AF;
+11DE:2F;
+11DF:3C;
+11E0:80;
+11E1:3C;
+11E2:82;
+11E3:47;
+11E4:0E;
+11E5:00;
+11E6:CD;
+11E7:A4;
+11E8:12;
+11E9:F1;
+11EA:F4;
+11EB:71;
+11EC:12;
+11ED:C1;
+11EE:F1;
+11EF:CC;
+11F0:2F;
+11F1:09;
+11F2:F1;
+11F3:38;
+11F4:03;
+11F5:83;
+11F6:90;
+11F7:92;
+11F8:C5;
+11F9:CD;
+11FA:74;
+11FB:10;
+11FC:EB;
+11FD:D1;
+11FE:C3;
+11FF:BF;
+1200:10;
+1201:D5;
+1202:AF;
+1203:F5;
+1204:E7;
+1205:E2;
+1206:22;
+1207:12;
+1208:3A;
+1209:24;
+120A:79;
+120B:FE;
+120C:91;
+120D:D2;
+120E:22;
+120F:12;
+1210:11;
+1211:64;
+1212:13;
+1213:21;
+1214:27;
+1215:79;
+1216:CD;
+1217:D3;
+1218:09;
+1219:CD;
+121A:A1;
+121B:0D;
+121C:F1;
+121D:D6;
+121E:0A;
+121F:F5;
+1220:18;
+1221:E6;
+1222:CD;
+1223:4F;
+1224:12;
+1225:E7;
+1226:EA;
+1227:34;
+1228:12;
+1229:01;
+122A:43;
+122B:91;
+122C:11;
+122D:F9;
+122E:4F;
+122F:CD;
+1230:0C;
+1231:0A;
+1232:18;
+1233:06;
+1234:11;
+1235:6C;
+1236:13;
+1237:CD;
+1238:49;
+1239:0A;
+123A:F2;
+123B:4C;
+123C:12;
+123D:F1;
+123E:CD;
+123F:0B;
+1240:0F;
+1241:F5;
+1242:18;
+1243:E1;
+1244:F1;
+1245:CD;
+1246:18;
+1247:0F;
+1248:F5;
+1249:CD;
+124A:4F;
+124B:12;
+124C:F1;
+124D:D1;
+124E:C9;
+124F:E7;
+1250:EA;
+1251:5E;
+1252:12;
+1253:01;
+1254:74;
+1255:94;
+1256:11;
+1257:F8;
+1258:23;
+1259:CD;
+125A:0C;
+125B:0A;
+125C:18;
+125D:06;
+125E:11;
+125F:74;
+1260:13;
+1261:CD;
+1262:49;
+1263:0A;
+1264:E1;
+1265:F2;
+1266:44;
+1267:12;
+1268:E9;
+1269:B7;
+126A:C8;
+126B:3D;
+126C:36;
+126D:30;
+126E:23;
+126F:18;
+1270:F9;
+1271:20;
+1272:04;
+1273:C8;
+1274:CD;
+1275:91;
+1276:12;
+1277:36;
+1278:30;
+1279:23;
+127A:3D;
+127B:18;
+127C:F6;
+127D:7B;
+127E:82;
+127F:3C;
+1280:47;
+1281:3C;
+1282:D6;
+1283:03;
+1284:30;
+1285:FC;
+1286:C6;
+1287:05;
+1288:4F;
+1289:3A;
+128A:D8;
+128B:78;
+128C:E6;
+128D:40;
+128E:C0;
+128F:4F;
+1290:C9;
+1291:05;
+1292:20;
+1293:08;
+1294:36;
+1295:2E;
+1296:22;
+1297:F3;
+1298:78;
+1299:23;
+129A:48;
+129B:C9;
+129C:0D;
+129D:C0;
+129E:36;
+129F:2C;
+12A0:23;
+12A1:0E;
+12A2:03;
+12A3:C9;
+12A4:D5;
+12A5:E7;
+12A6:E2;
+12A7:EA;
+12A8:12;
+12A9:C5;
+12AA:E5;
+12AB:CD;
+12AC:FC;
+12AD:09;
+12AE:21;
+12AF:7C;
+12B0:13;
+12B1:CD;
+12B2:F7;
+12B3:09;
+12B4:CD;
+12B5:77;
+12B6:0C;
+12B7:AF;
+12B8:CD;
+12B9:7B;
+12BA:0B;
+12BB:E1;
+12BC:C1;
+12BD:11;
+12BE:8C;
+12BF:13;
+12C0:3E;
+12C1:0A;
+12C2:CD;
+12C3:91;
+12C4:12;
+12C5:C5;
+12C6:F5;
+12C7:E5;
+12C8:D5;
+12C9:06;
+12CA:2F;
+12CB:04;
+12CC:E1;
+12CD:E5;
+12CE:CD;
+12CF:48;
+12D0:0D;
+12D1:30;
+12D2:F8;
+12D3:E1;
+12D4:CD;
+12D5:36;
+12D6:0D;
+12D7:EB;
+12D8:E1;
+12D9:70;
+12DA:23;
+12DB:F1;
+12DC:C1;
+12DD:3D;
+12DE:20;
+12DF:E2;
+12E0:C5;
+12E1:E5;
+12E2:21;
+12E3:1D;
+12E4:79;
+12E5:CD;
+12E6:B1;
+12E7:09;
+12E8:18;
+12E9:0C;
+12EA:C5;
+12EB:E5;
+12EC:CD;
+12ED:08;
+12EE:07;
+12EF:3C;
+12F0:CD;
+12F1:FB;
+12F2:0A;
+12F3:CD;
+12F4:B4;
+12F5:09;
+12F6:E1;
+12F7:C1;
+12F8:AF;
+12F9:11;
+12FA:D2;
+12FB:13;
+12FC:3F;
+12FD:CD;
+12FE:91;
+12FF:12;
+1300:C5;
+1301:F5;
+1302:E5;
+1303:D5;
+1304:CD;
+1305:BF;
+1306:09;
+1307:E1;
+1308:06;
+1309:2F;
+130A:04;
+130B:7B;
+130C:96;
+130D:5F;
+130E:23;
+130F:7A;
+1310:9E;
+1311:57;
+1312:23;
+1313:79;
+1314:9E;
+1315:4F;
+1316:2B;
+1317:2B;
+1318:30;
+1319:F0;
+131A:CD;
+131B:B7;
+131C:07;
+131D:23;
+131E:CD;
+131F:B4;
+1320:09;
+1321:EB;
+1322:E1;
+1323:70;
+1324:23;
+1325:F1;
+1326:C1;
+1327:38;
+1328:D3;
+1329:13;
+132A:13;
+132B:3E;
+132C:04;
+132D:18;
+132E:06;
+132F:D5;
+1330:11;
+1331:D8;
+1332:13;
+1333:3E;
+1334:05;
+1335:CD;
+1336:91;
+1337:12;
+1338:C5;
+1339:F5;
+133A:E5;
+133B:EB;
+133C:4E;
+133D:23;
+133E:46;
+133F:C5;
+1340:23;
+1341:E3;
+1342:EB;
+1343:2A;
+1344:21;
+1345:79;
+1346:06;
+1347:2F;
+1348:04;
+1349:7D;
+134A:93;
+134B:6F;
+134C:7C;
+134D:9A;
+134E:67;
+134F:30;
+1350:F7;
+1351:19;
+1352:22;
+1353:21;
+1354:79;
+1355:D1;
+1356:E1;
+1357:70;
+1358:23;
+1359:F1;
+135A:C1;
+135B:3D;
+135C:20;
+135D:D7;
+135E:CD;
+135F:91;
+1360:12;
+1361:77;
+1362:D1;
+1363:C9;
+1364:00;
+1365:00;
+1366:00;
+1367:00;
+1368:F9;
+1369:02;
+136A:15;
+136B:A2;
+136C:FD;
+136D:FF;
+136E:9F;
+136F:31;
+1370:A9;
+1371:5F;
+1372:63;
+1373:B2;
+1374:FE;
+1375:FF;
+1376:03;
+1377:BF;
+1378:C9;
+1379:1B;
+137A:0E;
+137B:B6;
+137C:00;
+137D:00;
+137E:00;
+137F:00;
+1380:00;
+1381:00;
+1382:00;
+1383:80;
+1384:00;
+1385:00;
+1386:04;
+1387:BF;
+1388:C9;
+1389:1B;
+138A:0E;
+138B:B6;
+138C:00;
+138D:80;
+138E:C6;
+138F:A4;
+1390:7E;
+1391:8D;
+1392:03;
+1393:00;
+1394:40;
+1395:7A;
+1396:10;
+1397:F3;
+1398:5A;
+1399:00;
+139A:00;
+139B:A0;
+139C:72;
+139D:4E;
+139E:18;
+139F:09;
+13A0:00;
+13A1:00;
+13A2:10;
+13A3:A5;
+13A4:D4;
+13A5:E8;
+13A6:00;
+13A7:00;
+13A8:00;
+13A9:E8;
+13AA:76;
+13AB:48;
+13AC:17;
+13AD:00;
+13AE:00;
+13AF:00;
+13B0:E4;
+13B1:0B;
+13B2:54;
+13B3:02;
+13B4:00;
+13B5:00;
+13B6:00;
+13B7:CA;
+13B8:9A;
+13B9:3B;
+13BA:00;
+13BB:00;
+13BC:00;
+13BD:00;
+13BE:E1;
+13BF:F5;
+13C0:05;
+13C1:00;
+13C2:00;
+13C3:00;
+13C4:80;
+13C5:96;
+13C6:98;
+13C7:00;
+13C8:00;
+13C9:00;
+13CA:00;
+13CB:40;
+13CC:42;
+13CD:0F;
+13CE:00;
+13CF:00;
+13D0:00;
+13D1:00;
+13D2:A0;
+13D3:86;
+13D4:01;
+13D5:10;
+13D6:27;
+13D7:00;
+13D8:10;
+13D9:27;
+13DA:E8;
+13DB:03;
+13DC:64;
+13DD:00;
+13DE:0A;
+13DF:00;
+13E0:01;
+13E1:00;
+13E2:21;
+13E3:82;
+13E4:09;
+13E5:E3;
+13E6:E9;
+13E7:CD;
+13E8:A4;
+13E9:09;
+13EA:21;
+13EB:80;
+13EC:13;
+13ED:CD;
+13EE:B1;
+13EF:09;
+13F0:18;
+13F1:03;
+13F2:CD;
+13F3:B1;
+13F4:0A;
+13F5:C1;
+13F6:D1;
+13F7:CD;
+13F8:55;
+13F9:09;
+13FA:78;
+13FB:28;
+13FC:3C;
+13FD:F2;
+13FE:04;
+13FF:14;
+1400:B7;
+1401:CA;
+1402:9A;
+1403:19;
+1404:B7;
+1405:CA;
+1406:79;
+1407:07;
+1408:D5;
+1409:C5;
+140A:79;
+140B:F6;
+140C:7F;
+140D:CD;
+140E:BF;
+140F:09;
+1410:F2;
+1411:21;
+1412:14;
+1413:D5;
+1414:C5;
+1415:CD;
+1416:40;
+1417:0B;
+1418:C1;
+1419:D1;
+141A:F5;
+141B:CD;
+141C:0C;
+141D:0A;
+141E:E1;
+141F:7C;
+1420:1F;
+1421:E1;
+1422:22;
+1423:23;
+1424:79;
+1425:E1;
+1426:22;
+1427:21;
+1428:79;
+1429:DC;
+142A:E2;
+142B:13;
+142C:CC;
+142D:82;
+142E:09;
+142F:D5;
+1430:C5;
+1431:CD;
+1432:09;
+1433:08;
+1434:C1;
+1435:D1;
+1436:CD;
+1437:47;
+1438:08;
+1439:CD;
+143A:A4;
+143B:09;
+143C:01;
+143D:38;
+143E:81;
+143F:11;
+1440:3B;
+1441:AA;
+1442:CD;
+1443:47;
+1444:08;
+1445:3A;
+1446:24;
+1447:79;
+1448:FE;
+1449:88;
+144A:D2;
+144B:31;
+144C:09;
+144D:CD;
+144E:40;
+144F:0B;
+1450:C6;
+1451:80;
+1452:C6;
+1453:02;
+1454:DA;
+1455:31;
+1456:09;
+1457:F5;
+1458:21;
+1459:F8;
+145A:07;
+145B:CD;
+145C:0B;
+145D:07;
+145E:CD;
+145F:41;
+1460:08;
+1461:F1;
+1462:C1;
+1463:D1;
+1464:F5;
+1465:CD;
+1466:13;
+1467:07;
+1468:CD;
+1469:82;
+146A:09;
+146B:21;
+146C:79;
+146D:14;
+146E:CD;
+146F:A9;
+1470:14;
+1471:11;
+1472:00;
+1473:00;
+1474:C1;
+1475:4A;
+1476:C3;
+1477:47;
+1478:08;
+1479:08;
+147A:40;
+147B:2E;
+147C:94;
+147D:74;
+147E:70;
+147F:4F;
+1480:2E;
+1481:77;
+1482:6E;
+1483:02;
+1484:88;
+1485:7A;
+1486:E6;
+1487:A0;
+1488:2A;
+1489:7C;
+148A:50;
+148B:AA;
+148C:AA;
+148D:7E;
+148E:FF;
+148F:FF;
+1490:7F;
+1491:7F;
+1492:00;
+1493:00;
+1494:80;
+1495:81;
+1496:00;
+1497:00;
+1498:00;
+1499:81;
+149A:CD;
+149B:A4;
+149C:09;
+149D:11;
+149E:32;
+149F:0C;
+14A0:D5;
+14A1:E5;
+14A2:CD;
+14A3:BF;
+14A4:09;
+14A5:CD;
+14A6:47;
+14A7:08;
+14A8:E1;
+14A9:CD;
+14AA:A4;
+14AB:09;
+14AC:7E;
+14AD:23;
+14AE:CD;
+14AF:B1;
+14B0:09;
+14B1:06;
+14B2:F1;
+14B3:C1;
+14B4:D1;
+14B5:3D;
+14B6:C8;
+14B7:D5;
+14B8:C5;
+14B9:F5;
+14BA:E5;
+14BB:CD;
+14BC:47;
+14BD:08;
+14BE:E1;
+14BF:CD;
+14C0:C2;
+14C1:09;
+14C2:E5;
+14C3:CD;
+14C4:16;
+14C5:07;
+14C6:E1;
+14C7:18;
+14C8:E9;
+14C9:CD;
+14CA:7F;
+14CB:0A;
+14CC:7C;
+14CD:B7;
+14CE:FA;
+14CF:4A;
+14D0:1E;
+14D1:B5;
+14D2:CA;
+14D3:F0;
+14D4:14;
+14D5:E5;
+14D6:CD;
+14D7:F0;
+14D8:14;
+14D9:CD;
+14DA:BF;
+14DB:09;
+14DC:EB;
+14DD:E3;
+14DE:C5;
+14DF:CD;
+14E0:CF;
+14E1:0A;
+14E2:C1;
+14E3:D1;
+14E4:CD;
+14E5:47;
+14E6:08;
+14E7:21;
+14E8:F8;
+14E9:07;
+14EA:CD;
+14EB:0B;
+14EC:07;
+14ED:C3;
+14EE:40;
+14EF:0B;
+14F0:21;
+14F1:90;
+14F2:78;
+14F3:E5;
+14F4:11;
+14F5:00;
+14F6:00;
+14F7:4B;
+14F8:26;
+14F9:03;
+14FA:2E;
+14FB:08;
+14FC:EB;
+14FD:29;
+14FE:EB;
+14FF:79;
+1500:17;
+1501:4F;
+1502:E3;
+1503:7E;
+1504:07;
+1505:77;
+1506:E3;
+1507:D2;
+1508:16;
+1509:15;
+150A:E5;
+150B:2A;
+150C:AA;
+150D:78;
+150E:19;
+150F:EB;
+1510:3A;
+1511:AC;
+1512:78;
+1513:89;
+1514:4F;
+1515:E1;
+1516:2D;
+1517:C2;
+1518:FC;
+1519:14;
+151A:E3;
+151B:23;
+151C:E3;
+151D:25;
+151E:C2;
+151F:FA;
+1520:14;
+1521:E1;
+1522:21;
+1523:65;
+1524:B0;
+1525:19;
+1526:22;
+1527:AA;
+1528:78;
+1529:CD;
+152A:EF;
+152B:0A;
+152C:3E;
+152D:05;
+152E:89;
+152F:32;
+1530:AC;
+1531:78;
+1532:EB;
+1533:06;
+1534:80;
+1535:21;
+1536:25;
+1537:79;
+1538:70;
+1539:2B;
+153A:70;
+153B:4F;
+153C:06;
+153D:00;
+153E:C3;
+153F:65;
+1540:07;
+1541:21;
+1542:8B;
+1543:15;
+1544:CD;
+1545:0B;
+1546:07;
+1547:CD;
+1548:A4;
+1549:09;
+154A:01;
+154B:49;
+154C:83;
+154D:11;
+154E:DB;
+154F:0F;
+1550:CD;
+1551:B4;
+1552:09;
+1553:C1;
+1554:D1;
+1555:CD;
+1556:A2;
+1557:08;
+1558:CD;
+1559:A4;
+155A:09;
+155B:CD;
+155C:40;
+155D:0B;
+155E:C1;
+155F:D1;
+1560:CD;
+1561:13;
+1562:07;
+1563:21;
+1564:8F;
+1565:15;
+1566:CD;
+1567:10;
+1568:07;
+1569:CD;
+156A:55;
+156B:09;
+156C:37;
+156D:F2;
+156E:77;
+156F:15;
+1570:CD;
+1571:08;
+1572:07;
+1573:CD;
+1574:55;
+1575:09;
+1576:B7;
+1577:F5;
+1578:F4;
+1579:82;
+157A:09;
+157B:21;
+157C:8F;
+157D:15;
+157E:CD;
+157F:0B;
+1580:07;
+1581:F1;
+1582:D4;
+1583:82;
+1584:09;
+1585:21;
+1586:93;
+1587:15;
+1588:C3;
+1589:9A;
+158A:14;
+158B:DB;
+158C:0F;
+158D:49;
+158E:81;
+158F:00;
+1590:00;
+1591:00;
+1592:7F;
+1593:05;
+1594:BA;
+1595:D7;
+1596:1E;
+1597:86;
+1598:64;
+1599:26;
+159A:99;
+159B:87;
+159C:58;
+159D:34;
+159E:23;
+159F:87;
+15A0:E0;
+15A1:5D;
+15A2:A5;
+15A3:86;
+15A4:DA;
+15A5:0F;
+15A6:49;
+15A7:83;
+15A8:CD;
+15A9:A4;
+15AA:09;
+15AB:CD;
+15AC:47;
+15AD:15;
+15AE:C1;
+15AF:E1;
+15B0:CD;
+15B1:A4;
+15B2:09;
+15B3:EB;
+15B4:CD;
+15B5:B4;
+15B6:09;
+15B7:CD;
+15B8:41;
+15B9:15;
+15BA:C3;
+15BB:A0;
+15BC:08;
+15BD:CD;
+15BE:55;
+15BF:09;
+15C0:FC;
+15C1:E2;
+15C2:13;
+15C3:FC;
+15C4:82;
+15C5:09;
+15C6:3A;
+15C7:24;
+15C8:79;
+15C9:FE;
+15CA:81;
+15CB:38;
+15CC:0C;
+15CD:01;
+15CE:00;
+15CF:81;
+15D0:51;
+15D1:59;
+15D2:CD;
+15D3:A2;
+15D4:08;
+15D5:21;
+15D6:10;
+15D7:07;
+15D8:E5;
+15D9:21;
+15DA:E3;
+15DB:15;
+15DC:CD;
+15DD:9A;
+15DE:14;
+15DF:21;
+15E0:8B;
+15E1:15;
+15E2:C9;
+15E3:09;
+15E4:4A;
+15E5:D7;
+15E6:3B;
+15E7:78;
+15E8:02;
+15E9:6E;
+15EA:84;
+15EB:7B;
+15EC:FE;
+15ED:C1;
+15EE:2F;
+15EF:7C;
+15F0:74;
+15F1:31;
+15F2:9A;
+15F3:7D;
+15F4:84;
+15F5:3D;
+15F6:5A;
+15F7:7D;
+15F8:C8;
+15F9:7F;
+15FA:91;
+15FB:7E;
+15FC:E4;
+15FD:BB;
+15FE:4C;
+15FF:7E;
+1600:6C;
+1601:AA;
+1602:AA;
+1603:7F;
+1604:00;
+1605:00;
+1606:00;
+1607:81;
+1608:8A;
+1609:09;
+160A:37;
+160B:0B;
+160C:77;
+160D:09;
+160E:D4;
+160F:27;
+1610:EF;
+1611:2A;
+1612:F5;
+1613:27;
+1614:E7;
+1615:13;
+1616:C9;
+1617:14;
+1618:09;
+1619:08;
+161A:39;
+161B:14;
+161C:41;
+161D:15;
+161E:47;
+161F:15;
+1620:A8;
+1621:15;
+1622:BD;
+1623:15;
+1624:AA;
+1625:2C;
+1626:52;
+1627:79;
+1628:58;
+1629:79;
+162A:5E;
+162B:79;
+162C:61;
+162D:79;
+162E:64;
+162F:79;
+1630:67;
+1631:79;
+1632:6A;
+1633:79;
+1634:6D;
+1635:79;
+1636:70;
+1637:79;
+1638:7F;
+1639:0A;
+163A:B1;
+163B:0A;
+163C:DB;
+163D:0A;
+163E:26;
+163F:0B;
+1640:03;
+1641:2A;
+1642:36;
+1643:28;
+1644:C5;
+1645:2A;
+1646:0F;
+1647:2A;
+1648:1F;
+1649:2A;
+164A:61;
+164B:2A;
+164C:91;
+164D:2A;
+164E:9A;
+164F:2A;
+1650:C5;
+1651:4E;
+1652:44;
+1653:C6;
+1654:4F;
+1655:52;
+1656:D2;
+1657:45;
+1658:53;
+1659:45;
+165A:54;
+165B:D3;
+165C:45;
+165D:54;
+165E:C3;
+165F:4C;
+1660:53;
+1661:81;
+1662:00;
+1663:00;
+1664:81;
+1665:00;
+1666:00;
+1667:00;
+1668:00;
+1669:00;
+166A:CE;
+166B:45;
+166C:58;
+166D:54;
+166E:C4;
+166F:41;
+1670:54;
+1671:41;
+1672:C9;
+1673:4E;
+1674:50;
+1675:55;
+1676:54;
+1677:C4;
+1678:49;
+1679:4D;
+167A:D2;
+167B:45;
+167C:41;
+167D:44;
+167E:CC;
+167F:45;
+1680:54;
+1681:C7;
+1682:4F;
+1683:54;
+1684:4F;
+1685:D2;
+1686:55;
+1687:4E;
+1688:C9;
+1689:46;
+168A:D2;
+168B:45;
+168C:53;
+168D:54;
+168E:4F;
+168F:52;
+1690:45;
+1691:C7;
+1692:4F;
+1693:53;
+1694:55;
+1695:42;
+1696:D2;
+1697:45;
+1698:54;
+1699:55;
+169A:52;
+169B:4E;
+169C:D2;
+169D:45;
+169E:4D;
+169F:D3;
+16A0:54;
+16A1:4F;
+16A2:50;
+16A3:C5;
+16A4:4C;
+16A5:53;
+16A6:45;
+16A7:C3;
+16A8:4F;
+16A9:50;
+16AA:59;
+16AB:C3;
+16AC:4F;
+16AD:4C;
+16AE:4F;
+16AF:52;
+16B0:D6;
+16B1:45;
+16B2:52;
+16B3:49;
+16B4:46;
+16B5:59;
+16B6:81;
+16B7:00;
+16B8:00;
+16B9:00;
+16BA:00;
+16BB:00;
+16BC:81;
+16BD:00;
+16BE:00;
+16BF:00;
+16C0:00;
+16C1:00;
+16C2:81;
+16C3:00;
+16C4:00;
+16C5:00;
+16C6:00;
+16C7:00;
+16C8:C3;
+16C9:52;
+16CA:55;
+16CB:4E;
+16CC:CD;
+16CD:4F;
+16CE:44;
+16CF:45;
+16D0:D3;
+16D1:4F;
+16D2:55;
+16D3:4E;
+16D4:44;
+16D5:81;
+16D6:00;
+16D7:00;
+16D8:00;
+16D9:00;
+16DA:00;
+16DB:CF;
+16DC:55;
+16DD:54;
+16DE:81;
+16DF:00;
+16E0:81;
+16E1:00;
+16E2:00;
+16E3:00;
+16E4:81;
+16E5:00;
+16E6:00;
+16E7:00;
+16E8:00;
+16E9:81;
+16EA:00;
+16EB:00;
+16EC:81;
+16ED:00;
+16EE:00;
+16EF:81;
+16F0:00;
+16F1:00;
+16F2:00;
+16F3:00;
+16F4:81;
+16F5:00;
+16F6:00;
+16F7:00;
+16F8:81;
+16F9:00;
+16FA:00;
+16FB:00;
+16FC:00;
+16FD:81;
+16FE:00;
+16FF:00;
+1700:00;
+1701:81;
+1702:00;
+1703:00;
+1704:00;
+1705:81;
+1706:00;
+1707:00;
+1708:00;
+1709:81;
+170A:00;
+170B:00;
+170C:00;
+170D:81;
+170E:00;
+170F:00;
+1710:00;
+1711:81;
+1712:00;
+1713:00;
+1714:00;
+1715:00;
+1716:00;
+1717:CC;
+1718:50;
+1719:52;
+171A:49;
+171B:4E;
+171C:54;
+171D:81;
+171E:00;
+171F:00;
+1720:D0;
+1721:4F;
+1722:4B;
+1723:45;
+1724:D0;
+1725:52;
+1726:49;
+1727:4E;
+1728:54;
+1729:C3;
+172A:4F;
+172B:4E;
+172C:54;
+172D:CC;
+172E:49;
+172F:53;
+1730:54;
+1731:CC;
+1732:4C;
+1733:49;
+1734:53;
+1735:54;
+1736:81;
+1737:00;
+1738:00;
+1739:00;
+173A:00;
+173B:00;
+173C:81;
+173D:00;
+173E:00;
+173F:00;
+1740:C3;
+1741:4C;
+1742:45;
+1743:41;
+1744:52;
+1745:C3;
+1746:4C;
+1747:4F;
+1748:41;
+1749:44;
+174A:C3;
+174B:53;
+174C:41;
+174D:56;
+174E:45;
+174F:CE;
+1750:45;
+1751:57;
+1752:D4;
+1753:41;
+1754:42;
+1755:28;
+1756:D4;
+1757:4F;
+1758:81;
+1759:00;
+175A:D5;
+175B:53;
+175C:49;
+175D:4E;
+175E:47;
+175F:81;
+1760:00;
+1761:00;
+1762:00;
+1763:00;
+1764:00;
+1765:D5;
+1766:53;
+1767:52;
+1768:81;
+1769:00;
+176A:00;
+176B:81;
+176C:00;
+176D:00;
+176E:81;
+176F:00;
+1770:00;
+1771:00;
+1772:00;
+1773:00;
+1774:00;
+1775:81;
+1776:00;
+1777:00;
+1778:00;
+1779:00;
+177A:D0;
+177B:4F;
+177C:49;
+177D:4E;
+177E:54;
+177F:81;
+1780:00;
+1781:00;
+1782:00;
+1783:00;
+1784:81;
+1785:00;
+1786:00;
+1787:C9;
+1788:4E;
+1789:4B;
+178A:45;
+178B:59;
+178C:24;
+178D:D4;
+178E:48;
+178F:45;
+1790:4E;
+1791:CE;
+1792:4F;
+1793:54;
+1794:D3;
+1795:54;
+1796:45;
+1797:50;
+1798:AB;
+1799:AD;
+179A:AA;
+179B:AF;
+179C:DE;
+179D:C1;
+179E:4E;
+179F:44;
+17A0:CF;
+17A1:52;
+17A2:BE;
+17A3:BD;
+17A4:BC;
+17A5:D3;
+17A6:47;
+17A7:4E;
+17A8:C9;
+17A9:4E;
+17AA:54;
+17AB:C1;
+17AC:42;
+17AD:53;
+17AE:81;
+17AF:00;
+17B0:00;
+17B1:C9;
+17B2:4E;
+17B3:50;
+17B4:81;
+17B5:00;
+17B6:00;
+17B7:D3;
+17B8:51;
+17B9:52;
+17BA:D2;
+17BB:4E;
+17BC:44;
+17BD:CC;
+17BE:4F;
+17BF:47;
+17C0:C5;
+17C1:58;
+17C2:50;
+17C3:C3;
+17C4:4F;
+17C5:53;
+17C6:D3;
+17C7:49;
+17C8:4E;
+17C9:D4;
+17CA:41;
+17CB:4E;
+17CC:C1;
+17CD:54;
+17CE:4E;
+17CF:D0;
+17D0:45;
+17D1:45;
+17D2:4B;
+17D3:81;
+17D4:00;
+17D5:00;
+17D6:81;
+17D7:00;
+17D8:00;
+17D9:81;
+17DA:00;
+17DB:00;
+17DC:81;
+17DD:00;
+17DE:00;
+17DF:81;
+17E0:00;
+17E1:00;
+17E2:81;
+17E3:00;
+17E4:00;
+17E5:81;
+17E6:00;
+17E7:00;
+17E8:00;
+17E9:81;
+17EA:00;
+17EB:00;
+17EC:00;
+17ED:81;
+17EE:00;
+17EF:00;
+17F0:00;
+17F1:81;
+17F2:00;
+17F3:00;
+17F4:00;
+17F5:81;
+17F6:00;
+17F7:00;
+17F8:00;
+17F9:81;
+17FA:00;
+17FB:00;
+17FC:00;
+17FD:81;
+17FE:00;
+17FF:00;
+1800:CC;
+1801:45;
+1802:4E;
+1803:D3;
+1804:54;
+1805:52;
+1806:24;
+1807:D6;
+1808:41;
+1809:4C;
+180A:C1;
+180B:53;
+180C:43;
+180D:C3;
+180E:48;
+180F:52;
+1810:24;
+1811:CC;
+1812:45;
+1813:46;
+1814:54;
+1815:24;
+1816:D2;
+1817:49;
+1818:47;
+1819:48;
+181A:54;
+181B:24;
+181C:CD;
+181D:49;
+181E:44;
+181F:24;
+1820:A7;
+1821:80;
+1822:AE;
+1823:1D;
+1824:A1;
+1825:1C;
+1826:38;
+1827:01;
+1828:35;
+1829:01;
+182A:C9;
+182B:01;
+182C:73;
+182D:79;
+182E:D3;
+182F:01;
+1830:B6;
+1831:22;
+1832:05;
+1833:1F;
+1834:9A;
+1835:21;
+1836:08;
+1837:26;
+1838:EF;
+1839:21;
+183A:21;
+183B:1F;
+183C:C2;
+183D:1E;
+183E:A3;
+183F:1E;
+1840:39;
+1841:20;
+1842:91;
+1843:1D;
+1844:B1;
+1845:1E;
+1846:DE;
+1847:1E;
+1848:07;
+1849:1F;
+184A:A9;
+184B:1D;
+184C:07;
+184D:1F;
+184E:12;
+184F:39;
+1850:9D;
+1851:38;
+1852:38;
+1853:37;
+1854:03;
+1855:1E;
+1856:06;
+1857:1E;
+1858:09;
+1859:1E;
+185A:2E;
+185B:37;
+185C:63;
+185D:2E;
+185E:F5;
+185F:2B;
+1860:AF;
+1861:1F;
+1862:FB;
+1863:2A;
+1864:6C;
+1865:1F;
+1866:79;
+1867:79;
+1868:7C;
+1869:79;
+186A:7F;
+186B:79;
+186C:82;
+186D:79;
+186E:85;
+186F:79;
+1870:88;
+1871:79;
+1872:8B;
+1873:79;
+1874:8E;
+1875:79;
+1876:91;
+1877:79;
+1878:97;
+1879:79;
+187A:9A;
+187B:79;
+187C:A0;
+187D:79;
+187E:00;
+187F:00;
+1880:67;
+1881:20;
+1882:5B;
+1883:79;
+1884:B1;
+1885:2C;
+1886:6F;
+1887:20;
+1888:E4;
+1889:1D;
+188A:2E;
+188B:2B;
+188C:29;
+188D:2B;
+188E:C6;
+188F:2B;
+1890:08;
+1891:20;
+1892:7A;
+1893:1E;
+1894:56;
+1895:36;
+1896:A9;
+1897:34;
+1898:49;
+1899:1B;
+189A:79;
+189B:79;
+189C:7C;
+189D:7C;
+189E:7F;
+189F:50;
+18A0:46;
+18A1:DB;
+18A2:0A;
+18A3:00;
+18A4:00;
+18A5:7F;
+18A6:0A;
+18A7:F4;
+18A8:0A;
+18A9:B1;
+18AA:0A;
+18AB:77;
+18AC:0C;
+18AD:70;
+18AE:0C;
+18AF:A1;
+18B0:0D;
+18B1:E5;
+18B2:0D;
+18B3:78;
+18B4:0A;
+18B5:16;
+18B6:07;
+18B7:13;
+18B8:07;
+18B9:47;
+18BA:08;
+18BB:A2;
+18BC:08;
+18BD:0C;
+18BE:0A;
+18BF:D2;
+18C0:0B;
+18C1:C7;
+18C2:0B;
+18C3:F2;
+18C4:0B;
+18C5:90;
+18C6:24;
+18C7:39;
+18C8:0A;
+18C9:4E;
+18CA:46;
+18CB:53;
+18CC:4E;
+18CD:52;
+18CE:47;
+18CF:4F;
+18D0:44;
+18D1:46;
+18D2:43;
+18D3:4F;
+18D4:56;
+18D5:4F;
+18D6:4D;
+18D7:55;
+18D8:4C;
+18D9:42;
+18DA:53;
+18DB:44;
+18DC:44;
+18DD:2F;
+18DE:30;
+18DF:49;
+18E0:44;
+18E1:54;
+18E2:4D;
+18E3:4F;
+18E4:53;
+18E5:4C;
+18E6:53;
+18E7:53;
+18E8:54;
+18E9:43;
+18EA:4E;
+18EB:4E;
+18EC:52;
+18ED:52;
+18EE:57;
+18EF:55;
+18F0:45;
+18F1:4D;
+18F2:4F;
+18F3:46;
+18F4:44;
+18F5:4C;
+18F6:33;
+18F7:D6;
+18F8:00;
+18F9:6F;
+18FA:7C;
+18FB:DE;
+18FC:00;
+18FD:67;
+18FE:78;
+18FF:DE;
+1900:00;
+1901:47;
+1902:3E;
+1903:00;
+1904:C9;
+1905:4A;
+1906:1E;
+1907:40;
+1908:E6;
+1909:4D;
+190A:DB;
+190B:00;
+190C:C9;
+190D:D3;
+190E:00;
+190F:C9;
+1910:00;
+1911:00;
+1912:00;
+1913:00;
+1914:40;
+1915:30;
+1916:00;
+1917:4C;
+1918:7B;
+1919:FE;
+191A:FF;
+191B:E9;
+191C:7A;
+191D:20;
+191E:45;
+191F:52;
+1920:52;
+1921:4F;
+1922:52;
+1923:00;
+1924:20;
+1925:49;
+1926:4E;
+1927:20;
+1928:00;
+1929:52;
+192A:45;
+192B:41;
+192C:44;
+192D:59;
+192E:0D;
+192F:00;
+1930:42;
+1931:52;
+1932:45;
+1933:41;
+1934:4B;
+1935:00;
+1936:21;
+1937:04;
+1938:00;
+1939:39;
+193A:7E;
+193B:23;
+193C:FE;
+193D:81;
+193E:C0;
+193F:4E;
+1940:23;
+1941:46;
+1942:23;
+1943:E5;
+1944:69;
+1945:60;
+1946:7A;
+1947:B3;
+1948:EB;
+1949:28;
+194A:02;
+194B:EB;
+194C:DF;
+194D:01;
+194E:0E;
+194F:00;
+1950:E1;
+1951:C8;
+1952:09;
+1953:18;
+1954:E5;
+1955:CD;
+1956:6C;
+1957:19;
+1958:C5;
+1959:E3;
+195A:C1;
+195B:DF;
+195C:7E;
+195D:02;
+195E:C8;
+195F:0B;
+1960:2B;
+1961:18;
+1962:F8;
+1963:E5;
+1964:2A;
+1965:FD;
+1966:78;
+1967:06;
+1968:00;
+1969:09;
+196A:09;
+196B:3E;
+196C:E5;
+196D:3E;
+196E:C6;
+196F:95;
+1970:6F;
+1971:3E;
+1972:FF;
+1973:9C;
+1974:38;
+1975:04;
+1976:67;
+1977:39;
+1978:E1;
+1979:D8;
+197A:1E;
+197B:0C;
+197C:18;
+197D:24;
+197E:2A;
+197F:A2;
+1980:78;
+1981:7C;
+1982:A5;
+1983:3C;
+1984:28;
+1985:08;
+1986:3A;
+1987:F2;
+1988:78;
+1989:B7;
+198A:1E;
+198B:22;
+198C:20;
+198D:14;
+198E:C3;
+198F:C1;
+1990:1D;
+1991:2A;
+1992:DA;
+1993:78;
+1994:22;
+1995:A2;
+1996:78;
+1997:1E;
+1998:02;
+1999:01;
+199A:1E;
+199B:14;
+199C:01;
+199D:1E;
+199E:00;
+199F:01;
+19A0:1E;
+19A1:24;
+19A2:2A;
+19A3:A2;
+19A4:78;
+19A5:22;
+19A6:EA;
+19A7:78;
+19A8:22;
+19A9:EC;
+19AA:78;
+19AB:01;
+19AC:B4;
+19AD:19;
+19AE:2A;
+19AF:E8;
+19B0:78;
+19B1:C3;
+19B2:9A;
+19B3:1B;
+19B4:C1;
+19B5:7B;
+19B6:4B;
+19B7:32;
+19B8:9A;
+19B9:78;
+19BA:2A;
+19BB:E6;
+19BC:78;
+19BD:22;
+19BE:EE;
+19BF:78;
+19C0:EB;
+19C1:2A;
+19C2:EA;
+19C3:78;
+19C4:7C;
+19C5:A5;
+19C6:3C;
+19C7:28;
+19C8:07;
+19C9:22;
+19CA:F5;
+19CB:78;
+19CC:EB;
+19CD:22;
+19CE:F7;
+19CF:78;
+19D0:2A;
+19D1:F0;
+19D2:78;
+19D3:7C;
+19D4:B5;
+19D5:EB;
+19D6:21;
+19D7:F2;
+19D8:78;
+19D9:28;
+19DA:08;
+19DB:A6;
+19DC:20;
+19DD:05;
+19DE:35;
+19DF:EB;
+19E0:C3;
+19E1:36;
+19E2:1D;
+19E3:AF;
+19E4:77;
+19E5:59;
+19E6:CD;
+19E7:F9;
+19E8:20;
+19E9:21;
+19EA:EC;
+19EB:3C;
+19EC:CD;
+19ED:A6;
+19EE:79;
+19EF:57;
+19F0:3E;
+19F1:3F;
+19F2:CD;
+19F3:2A;
+19F4:03;
+19F5:CD;
+19F6:D4;
+19F7:3C;
+19F8:00;
+19F9:00;
+19FA:00;
+19FB:00;
+19FC:00;
+19FD:00;
+19FE:21;
+19FF:1D;
+1A00:19;
+1A01:E5;
+1A02:2A;
+1A03:EA;
+1A04:78;
+1A05:E3;
+1A06:CD;
+1A07:A7;
+1A08:28;
+1A09:E1;
+1A0A:11;
+1A0B:FE;
+1A0C:FF;
+1A0D:DF;
+1A0E:CA;
+1A0F:74;
+1A10:06;
+1A11:7C;
+1A12:A5;
+1A13:3C;
+1A14:C4;
+1A15:A7;
+1A16:0F;
+1A17:3E;
+1A18:C1;
+1A19:CD;
+1A1A:8B;
+1A1B:03;
+1A1C:CD;
+1A1D:AC;
+1A1E:79;
+1A1F:00;
+1A20:00;
+1A21:00;
+1A22:CD;
+1A23:F9;
+1A24:20;
+1A25:21;
+1A26:29;
+1A27:19;
+1A28:CD;
+1A29:A7;
+1A2A:28;
+1A2B:3A;
+1A2C:9A;
+1A2D:78;
+1A2E:D6;
+1A2F:02;
+1A30:00;
+1A31:00;
+1A32:00;
+1A33:21;
+1A34:FF;
+1A35:FF;
+1A36:22;
+1A37:A2;
+1A38:78;
+1A39:3A;
+1A3A:E1;
+1A3B:78;
+1A3C:B7;
+1A3D:28;
+1A3E:3A;
+1A3F:2A;
+1A40:E2;
+1A41:78;
+1A42:E5;
+1A43:CD;
+1A44:AF;
+1A45:0F;
+1A46:3E;
+1A47:20;
+1A48:CD;
+1A49:2A;
+1A4A:03;
+1A4B:D1;
+1A4C:D5;
+1A4D:CD;
+1A4E:2C;
+1A4F:1B;
+1A50:DC;
+1A51:53;
+1A52:2E;
+1A53:00;
+1A54:CD;
+1A55:E3;
+1A56:03;
+1A57:D1;
+1A58:30;
+1A59:06;
+1A5A:AF;
+1A5B:32;
+1A5C:E1;
+1A5D:78;
+1A5E:18;
+1A5F:B9;
+1A60:2A;
+1A61:E4;
+1A62:78;
+1A63:19;
+1A64:38;
+1A65:F4;
+1A66:D5;
+1A67:11;
+1A68:F9;
+1A69:FF;
+1A6A:DF;
+1A6B:D1;
+1A6C:30;
+1A6D:EC;
+1A6E:22;
+1A6F:E2;
+1A70:78;
+1A71:00;
+1A72:00;
+1A73:21;
+1A74:E7;
+1A75:79;
+1A76:C3;
+1A77:81;
+1A78:1A;
+1A79:00;
+1A7A:00;
+1A7B:CD;
+1A7C:E3;
+1A7D:03;
+1A7E:DA;
+1A7F:33;
+1A80:1A;
+1A81:D7;
+1A82:3C;
+1A83:3D;
+1A84:CA;
+1A85:33;
+1A86:1A;
+1A87:F5;
+1A88:CD;
+1A89:5A;
+1A8A:1E;
+1A8B:2B;
+1A8C:7E;
+1A8D:FE;
+1A8E:20;
+1A8F:28;
+1A90:FA;
+1A91:23;
+1A92:7E;
+1A93:FE;
+1A94:20;
+1A95:CC;
+1A96:C9;
+1A97:09;
+1A98:D5;
+1A99:CD;
+1A9A:C0;
+1A9B:1B;
+1A9C:D1;
+1A9D:F1;
+1A9E:22;
+1A9F:E6;
+1AA0:78;
+1AA1:CD;
+1AA2:B2;
+1AA3:79;
+1AA4:D2;
+1AA5:5A;
+1AA6:1D;
+1AA7:D5;
+1AA8:C5;
+1AA9:AF;
+1AAA:32;
+1AAB:DD;
+1AAC:78;
+1AAD:D7;
+1AAE:B7;
+1AAF:F5;
+1AB0:EB;
+1AB1:22;
+1AB2:EC;
+1AB3:78;
+1AB4:EB;
+1AB5:CD;
+1AB6:2C;
+1AB7:1B;
+1AB8:C5;
+1AB9:DC;
+1ABA:E4;
+1ABB:2B;
+1ABC:D1;
+1ABD:F1;
+1ABE:D5;
+1ABF:28;
+1AC0:27;
+1AC1:D1;
+1AC2:2A;
+1AC3:F9;
+1AC4:78;
+1AC5:E3;
+1AC6:C1;
+1AC7:09;
+1AC8:E5;
+1AC9:CD;
+1ACA:55;
+1ACB:19;
+1ACC:E1;
+1ACD:22;
+1ACE:F9;
+1ACF:78;
+1AD0:EB;
+1AD1:74;
+1AD2:D1;
+1AD3:E5;
+1AD4:23;
+1AD5:23;
+1AD6:73;
+1AD7:23;
+1AD8:72;
+1AD9:23;
+1ADA:EB;
+1ADB:2A;
+1ADC:A7;
+1ADD:78;
+1ADE:EB;
+1ADF:1B;
+1AE0:1B;
+1AE1:1A;
+1AE2:77;
+1AE3:23;
+1AE4:13;
+1AE5:B7;
+1AE6:20;
+1AE7:F9;
+1AE8:D1;
+1AE9:CD;
+1AEA:FC;
+1AEB:1A;
+1AEC:CD;
+1AED:B5;
+1AEE:79;
+1AEF:CD;
+1AF0:5D;
+1AF1:1B;
+1AF2:CD;
+1AF3:B8;
+1AF4:79;
+1AF5:C3;
+1AF6:33;
+1AF7:1A;
+1AF8:2A;
+1AF9:A4;
+1AFA:78;
+1AFB:EB;
+1AFC:62;
+1AFD:6B;
+1AFE:7E;
+1AFF:23;
+1B00:B6;
+1B01:C8;
+1B02:23;
+1B03:23;
+1B04:23;
+1B05:AF;
+1B06:BE;
+1B07:23;
+1B08:20;
+1B09:FC;
+1B0A:EB;
+1B0B:73;
+1B0C:23;
+1B0D:72;
+1B0E:18;
+1B0F:EC;
+1B10:11;
+1B11:00;
+1B12:00;
+1B13:D5;
+1B14:28;
+1B15:09;
+1B16:D1;
+1B17:CD;
+1B18:4F;
+1B19:1E;
+1B1A:D5;
+1B1B:28;
+1B1C:0B;
+1B1D:CF;
+1B1E:CE;
+1B1F:11;
+1B20:FA;
+1B21:FF;
+1B22:C4;
+1B23:4F;
+1B24:1E;
+1B25:C2;
+1B26:97;
+1B27:19;
+1B28:EB;
+1B29:D1;
+1B2A:E3;
+1B2B:E5;
+1B2C:2A;
+1B2D:A4;
+1B2E:78;
+1B2F:44;
+1B30:4D;
+1B31:7E;
+1B32:23;
+1B33:B6;
+1B34:2B;
+1B35:C8;
+1B36:23;
+1B37:23;
+1B38:7E;
+1B39:23;
+1B3A:66;
+1B3B:6F;
+1B3C:DF;
+1B3D:60;
+1B3E:69;
+1B3F:7E;
+1B40:23;
+1B41:66;
+1B42:6F;
+1B43:3F;
+1B44:C8;
+1B45:3F;
+1B46:D0;
+1B47:18;
+1B48:E6;
+1B49:C0;
+1B4A:CD;
+1B4B:C9;
+1B4C:01;
+1B4D:2A;
+1B4E:A4;
+1B4F:78;
+1B50:CD;
+1B51:F8;
+1B52:1D;
+1B53:32;
+1B54:E1;
+1B55:78;
+1B56:77;
+1B57:23;
+1B58:77;
+1B59:23;
+1B5A:22;
+1B5B:F9;
+1B5C:78;
+1B5D:2A;
+1B5E:A4;
+1B5F:78;
+1B60:2B;
+1B61:22;
+1B62:DF;
+1B63:78;
+1B64:06;
+1B65:1A;
+1B66:21;
+1B67:01;
+1B68:79;
+1B69:36;
+1B6A:04;
+1B6B:23;
+1B6C:10;
+1B6D:FB;
+1B6E:AF;
+1B6F:32;
+1B70:F2;
+1B71:78;
+1B72:6F;
+1B73:67;
+1B74:22;
+1B75:F0;
+1B76:78;
+1B77:22;
+1B78:F7;
+1B79:78;
+1B7A:2A;
+1B7B:B1;
+1B7C:78;
+1B7D:22;
+1B7E:D6;
+1B7F:78;
+1B80:CD;
+1B81:91;
+1B82:1D;
+1B83:2A;
+1B84:F9;
+1B85:78;
+1B86:22;
+1B87:FB;
+1B88:78;
+1B89:22;
+1B8A:FD;
+1B8B:78;
+1B8C:CD;
+1B8D:BB;
+1B8E:79;
+1B8F:C1;
+1B90:2A;
+1B91:A0;
+1B92:78;
+1B93:2B;
+1B94:2B;
+1B95:22;
+1B96:E8;
+1B97:78;
+1B98:23;
+1B99:23;
+1B9A:F9;
+1B9B:21;
+1B9C:B5;
+1B9D:78;
+1B9E:22;
+1B9F:B3;
+1BA0:78;
+1BA1:CD;
+1BA2:8B;
+1BA3:03;
+1BA4:CD;
+1BA5:69;
+1BA6:21;
+1BA7:AF;
+1BA8:67;
+1BA9:6F;
+1BAA:32;
+1BAB:DC;
+1BAC:78;
+1BAD:E5;
+1BAE:C5;
+1BAF:2A;
+1BB0:DF;
+1BB1:78;
+1BB2:C9;
+1BB3:3E;
+1BB4:3F;
+1BB5:CD;
+1BB6:2A;
+1BB7:03;
+1BB8:3E;
+1BB9:20;
+1BBA:CD;
+1BBB:2A;
+1BBC:03;
+1BBD:C3;
+1BBE:3A;
+1BBF:05;
+1BC0:AF;
+1BC1:32;
+1BC2:B0;
+1BC3:78;
+1BC4:4F;
+1BC5:EB;
+1BC6:2A;
+1BC7:A7;
+1BC8:78;
+1BC9:2B;
+1BCA:2B;
+1BCB:EB;
+1BCC:7E;
+1BCD:FE;
+1BCE:20;
+1BCF:CA;
+1BD0:5B;
+1BD1:1C;
+1BD2:47;
+1BD3:FE;
+1BD4:22;
+1BD5:CA;
+1BD6:77;
+1BD7:1C;
+1BD8:B7;
+1BD9:CA;
+1BDA:7D;
+1BDB:1C;
+1BDC:3A;
+1BDD:B0;
+1BDE:78;
+1BDF:B7;
+1BE0:7E;
+1BE1:C2;
+1BE2:5B;
+1BE3:1C;
+1BE4:FE;
+1BE5:3F;
+1BE6:3E;
+1BE7:B2;
+1BE8:CA;
+1BE9:5B;
+1BEA:1C;
+1BEB:7E;
+1BEC:FE;
+1BED:30;
+1BEE:38;
+1BEF:05;
+1BF0:FE;
+1BF1:3C;
+1BF2:DA;
+1BF3:5B;
+1BF4:1C;
+1BF5:D5;
+1BF6:11;
+1BF7:4F;
+1BF8:16;
+1BF9:C5;
+1BFA:01;
+1BFB:3D;
+1BFC:1C;
+1BFD:C5;
+1BFE:06;
+1BFF:7F;
+1C00:7E;
+1C01:FE;
+1C02:61;
+1C03:38;
+1C04:07;
+1C05:FE;
+1C06:7B;
+1C07:30;
+1C08:03;
+1C09:E6;
+1C0A:5F;
+1C0B:77;
+1C0C:4E;
+1C0D:EB;
+1C0E:23;
+1C0F:B6;
+1C10:F2;
+1C11:0E;
+1C12:1C;
+1C13:04;
+1C14:7E;
+1C15:E6;
+1C16:7F;
+1C17:C8;
+1C18:B9;
+1C19:20;
+1C1A:F3;
+1C1B:EB;
+1C1C:E5;
+1C1D:13;
+1C1E:1A;
+1C1F:B7;
+1C20:FA;
+1C21:39;
+1C22:1C;
+1C23:4F;
+1C24:78;
+1C25:FE;
+1C26:8D;
+1C27:20;
+1C28:02;
+1C29:D7;
+1C2A:2B;
+1C2B:23;
+1C2C:7E;
+1C2D:FE;
+1C2E:61;
+1C2F:38;
+1C30:02;
+1C31:E6;
+1C32:5F;
+1C33:B9;
+1C34:28;
+1C35:E7;
+1C36:E1;
+1C37:18;
+1C38:D3;
+1C39:48;
+1C3A:F1;
+1C3B:EB;
+1C3C:C9;
+1C3D:EB;
+1C3E:79;
+1C3F:C1;
+1C40:D1;
+1C41:EB;
+1C42:FE;
+1C43:95;
+1C44:36;
+1C45:3A;
+1C46:20;
+1C47:02;
+1C48:0C;
+1C49:23;
+1C4A:FE;
+1C4B:FB;
+1C4C:20;
+1C4D:0C;
+1C4E:36;
+1C4F:3A;
+1C50:23;
+1C51:06;
+1C52:93;
+1C53:70;
+1C54:23;
+1C55:EB;
+1C56:0C;
+1C57:0C;
+1C58:18;
+1C59:1D;
+1C5A:EB;
+1C5B:23;
+1C5C:12;
+1C5D:13;
+1C5E:0C;
+1C5F:D6;
+1C60:3A;
+1C61:28;
+1C62:04;
+1C63:FE;
+1C64:4E;
+1C65:20;
+1C66:03;
+1C67:32;
+1C68:B0;
+1C69:78;
+1C6A:D6;
+1C6B:59;
+1C6C:C2;
+1C6D:CC;
+1C6E:1B;
+1C6F:47;
+1C70:7E;
+1C71:B7;
+1C72:28;
+1C73:09;
+1C74:B8;
+1C75:28;
+1C76:E4;
+1C77:23;
+1C78:12;
+1C79:0C;
+1C7A:13;
+1C7B:18;
+1C7C:F3;
+1C7D:21;
+1C7E:05;
+1C7F:00;
+1C80:44;
+1C81:09;
+1C82:44;
+1C83:4D;
+1C84:2A;
+1C85:A7;
+1C86:78;
+1C87:2B;
+1C88:2B;
+1C89:2B;
+1C8A:12;
+1C8B:13;
+1C8C:12;
+1C8D:13;
+1C8E:12;
+1C8F:C9;
+1C90:7C;
+1C91:92;
+1C92:C0;
+1C93:7D;
+1C94:93;
+1C95:C9;
+1C96:7E;
+1C97:E3;
+1C98:BE;
+1C99:23;
+1C9A:E3;
+1C9B:CA;
+1C9C:78;
+1C9D:1D;
+1C9E:C3;
+1C9F:97;
+1CA0:19;
+1CA1:3E;
+1CA2:64;
+1CA3:32;
+1CA4:DC;
+1CA5:78;
+1CA6:CD;
+1CA7:21;
+1CA8:1F;
+1CA9:E3;
+1CAA:CD;
+1CAB:36;
+1CAC:19;
+1CAD:D1;
+1CAE:20;
+1CAF:05;
+1CB0:09;
+1CB1:F9;
+1CB2:22;
+1CB3:E8;
+1CB4:78;
+1CB5:EB;
+1CB6:0E;
+1CB7:08;
+1CB8:CD;
+1CB9:63;
+1CBA:19;
+1CBB:E5;
+1CBC:CD;
+1CBD:05;
+1CBE:1F;
+1CBF:E3;
+1CC0:E5;
+1CC1:2A;
+1CC2:A2;
+1CC3:78;
+1CC4:E3;
+1CC5:CF;
+1CC6:BD;
+1CC7:E7;
+1CC8:CA;
+1CC9:F6;
+1CCA:0A;
+1CCB:D2;
+1CCC:F6;
+1CCD:0A;
+1CCE:F5;
+1CCF:CD;
+1CD0:37;
+1CD1:23;
+1CD2:F1;
+1CD3:E5;
+1CD4:F2;
+1CD5:EC;
+1CD6:1C;
+1CD7:CD;
+1CD8:7F;
+1CD9:0A;
+1CDA:E3;
+1CDB:11;
+1CDC:01;
+1CDD:00;
+1CDE:7E;
+1CDF:FE;
+1CE0:CC;
+1CE1:CC;
+1CE2:01;
+1CE3:2B;
+1CE4:D5;
+1CE5:E5;
+1CE6:EB;
+1CE7:CD;
+1CE8:9E;
+1CE9:09;
+1CEA:18;
+1CEB:22;
+1CEC:CD;
+1CED:B1;
+1CEE:0A;
+1CEF:CD;
+1CF0:BF;
+1CF1:09;
+1CF2:E1;
+1CF3:C5;
+1CF4:D5;
+1CF5:01;
+1CF6:00;
+1CF7:81;
+1CF8:51;
+1CF9:5A;
+1CFA:7E;
+1CFB:FE;
+1CFC:CC;
+1CFD:3E;
+1CFE:01;
+1CFF:20;
+1D00:0E;
+1D01:CD;
+1D02:38;
+1D03:23;
+1D04:E5;
+1D05:CD;
+1D06:B1;
+1D07:0A;
+1D08:CD;
+1D09:BF;
+1D0A:09;
+1D0B:CD;
+1D0C:55;
+1D0D:09;
+1D0E:E1;
+1D0F:C5;
+1D10:D5;
+1D11:4F;
+1D12:E7;
+1D13:47;
+1D14:C5;
+1D15:E5;
+1D16:2A;
+1D17:DF;
+1D18:78;
+1D19:E3;
+1D1A:06;
+1D1B:81;
+1D1C:C5;
+1D1D:33;
+1D1E:CD;
+1D1F:58;
+1D20:03;
+1D21:B7;
+1D22:C4;
+1D23:A0;
+1D24:1D;
+1D25:22;
+1D26:E6;
+1D27:78;
+1D28:ED;
+1D29:73;
+1D2A:E8;
+1D2B:78;
+1D2C:7E;
+1D2D:FE;
+1D2E:3A;
+1D2F:28;
+1D30:29;
+1D31:B7;
+1D32:C2;
+1D33:97;
+1D34:19;
+1D35:23;
+1D36:7E;
+1D37:23;
+1D38:B6;
+1D39:CA;
+1D3A:7E;
+1D3B:19;
+1D3C:23;
+1D3D:5E;
+1D3E:23;
+1D3F:56;
+1D40:EB;
+1D41:22;
+1D42:A2;
+1D43:78;
+1D44:3A;
+1D45:1B;
+1D46:79;
+1D47:B7;
+1D48:28;
+1D49:0F;
+1D4A:D5;
+1D4B:3E;
+1D4C:3C;
+1D4D:CD;
+1D4E:2A;
+1D4F:03;
+1D50:CD;
+1D51:AF;
+1D52:0F;
+1D53:3E;
+1D54:3E;
+1D55:CD;
+1D56:2A;
+1D57:03;
+1D58:D1;
+1D59:EB;
+1D5A:D7;
+1D5B:11;
+1D5C:1E;
+1D5D:1D;
+1D5E:D5;
+1D5F:C8;
+1D60:D6;
+1D61:80;
+1D62:DA;
+1D63:21;
+1D64:1F;
+1D65:FE;
+1D66:3C;
+1D67:D2;
+1D68:E7;
+1D69:2A;
+1D6A:07;
+1D6B:4F;
+1D6C:06;
+1D6D:00;
+1D6E:EB;
+1D6F:21;
+1D70:22;
+1D71:18;
+1D72:09;
+1D73:4E;
+1D74:23;
+1D75:46;
+1D76:C5;
+1D77:EB;
+1D78:23;
+1D79:7E;
+1D7A:FE;
+1D7B:3A;
+1D7C:D0;
+1D7D:FE;
+1D7E:20;
+1D7F:CA;
+1D80:78;
+1D81:1D;
+1D82:FE;
+1D83:0B;
+1D84:30;
+1D85:05;
+1D86:FE;
+1D87:09;
+1D88:D2;
+1D89:78;
+1D8A:1D;
+1D8B:FE;
+1D8C:30;
+1D8D:3F;
+1D8E:3C;
+1D8F:3D;
+1D90:C9;
+1D91:EB;
+1D92:2A;
+1D93:A4;
+1D94:78;
+1D95:2B;
+1D96:22;
+1D97:FF;
+1D98:78;
+1D99:EB;
+1D9A:C9;
+1D9B:CD;
+1D9C:58;
+1D9D:03;
+1D9E:B7;
+1D9F:C8;
+1DA0:00;
+1DA1:00;
+1DA2:00;
+1DA3:00;
+1DA4:00;
+1DA5:32;
+1DA6:99;
+1DA7:78;
+1DA8:3D;
+1DA9:C0;
+1DAA:3C;
+1DAB:C3;
+1DAC:B4;
+1DAD:1D;
+1DAE:C0;
+1DAF:F5;
+1DB0:CC;
+1DB1:BB;
+1DB2:79;
+1DB3:F1;
+1DB4:22;
+1DB5:E6;
+1DB6:78;
+1DB7:21;
+1DB8:B5;
+1DB9:78;
+1DBA:22;
+1DBB:B3;
+1DBC:78;
+1DBD:21;
+1DBE:F6;
+1DBF:FF;
+1DC0:C1;
+1DC1:2A;
+1DC2:A2;
+1DC3:78;
+1DC4:E5;
+1DC5:F5;
+1DC6:7D;
+1DC7:A4;
+1DC8:3C;
+1DC9:28;
+1DCA:09;
+1DCB:22;
+1DCC:F5;
+1DCD:78;
+1DCE:2A;
+1DCF:E6;
+1DD0:78;
+1DD1:22;
+1DD2:F7;
+1DD3:78;
+1DD4:CD;
+1DD5:8B;
+1DD6:03;
+1DD7:CD;
+1DD8:F9;
+1DD9:20;
+1DDA:F1;
+1DDB:21;
+1DDC:30;
+1DDD:19;
+1DDE:C2;
+1DDF:06;
+1DE0:1A;
+1DE1:C3;
+1DE2:18;
+1DE3:1A;
+1DE4:2A;
+1DE5:F7;
+1DE6:78;
+1DE7:7C;
+1DE8:B5;
+1DE9:1E;
+1DEA:20;
+1DEB:CA;
+1DEC:A2;
+1DED:19;
+1DEE:EB;
+1DEF:2A;
+1DF0:F5;
+1DF1:78;
+1DF2:22;
+1DF3:A2;
+1DF4:78;
+1DF5:EB;
+1DF6:C9;
+1DF7:3E;
+1DF8:AF;
+1DF9:32;
+1DFA:1B;
+1DFB:79;
+1DFC:C9;
+1DFD:F1;
+1DFE:E1;
+1DFF:C9;
+1E00:1E;
+1E01:03;
+1E02:01;
+1E03:1E;
+1E04:02;
+1E05:01;
+1E06:1E;
+1E07:04;
+1E08:01;
+1E09:1E;
+1E0A:08;
+1E0B:CD;
+1E0C:3D;
+1E0D:1E;
+1E0E:01;
+1E0F:97;
+1E10:19;
+1E11:C5;
+1E12:D8;
+1E13:D6;
+1E14:41;
+1E15:4F;
+1E16:47;
+1E17:D7;
+1E18:FE;
+1E19:CE;
+1E1A:20;
+1E1B:09;
+1E1C:D7;
+1E1D:CD;
+1E1E:3D;
+1E1F:1E;
+1E20:D8;
+1E21:D6;
+1E22:41;
+1E23:47;
+1E24:D7;
+1E25:78;
+1E26:91;
+1E27:D8;
+1E28:3C;
+1E29:E3;
+1E2A:21;
+1E2B:01;
+1E2C:79;
+1E2D:06;
+1E2E:00;
+1E2F:09;
+1E30:73;
+1E31:23;
+1E32:3D;
+1E33:20;
+1E34:FB;
+1E35:E1;
+1E36:7E;
+1E37:FE;
+1E38:2C;
+1E39:C0;
+1E3A:D7;
+1E3B:18;
+1E3C:CE;
+1E3D:7E;
+1E3E:FE;
+1E3F:41;
+1E40:D8;
+1E41:FE;
+1E42:5B;
+1E43:3F;
+1E44:C9;
+1E45:D7;
+1E46:CD;
+1E47:02;
+1E48:2B;
+1E49:F0;
+1E4A:1E;
+1E4B:08;
+1E4C:C3;
+1E4D:A2;
+1E4E:19;
+1E4F:7E;
+1E50:FE;
+1E51:2E;
+1E52:EB;
+1E53:2A;
+1E54:EC;
+1E55:78;
+1E56:EB;
+1E57:CA;
+1E58:78;
+1E59:1D;
+1E5A:2B;
+1E5B:11;
+1E5C:00;
+1E5D:00;
+1E5E:D7;
+1E5F:D0;
+1E60:E5;
+1E61:F5;
+1E62:21;
+1E63:98;
+1E64:19;
+1E65:DF;
+1E66:DA;
+1E67:97;
+1E68:19;
+1E69:62;
+1E6A:6B;
+1E6B:19;
+1E6C:29;
+1E6D:19;
+1E6E:29;
+1E6F:F1;
+1E70:D6;
+1E71:30;
+1E72:5F;
+1E73:16;
+1E74:00;
+1E75:19;
+1E76:EB;
+1E77:E1;
+1E78:18;
+1E79:E4;
+1E7A:CA;
+1E7B:61;
+1E7C:1B;
+1E7D:CD;
+1E7E:46;
+1E7F:1E;
+1E80:2B;
+1E81:D7;
+1E82:C0;
+1E83:E5;
+1E84:2A;
+1E85:B1;
+1E86:78;
+1E87:7D;
+1E88:93;
+1E89:5F;
+1E8A:7C;
+1E8B:9A;
+1E8C:57;
+1E8D:DA;
+1E8E:7A;
+1E8F:19;
+1E90:2A;
+1E91:F9;
+1E92:78;
+1E93:01;
+1E94:28;
+1E95:00;
+1E96:09;
+1E97:DF;
+1E98:D2;
+1E99:7A;
+1E9A:19;
+1E9B:EB;
+1E9C:22;
+1E9D:A0;
+1E9E:78;
+1E9F:E1;
+1EA0:C3;
+1EA1:61;
+1EA2:1B;
+1EA3:CA;
+1EA4:5D;
+1EA5:1B;
+1EA6:CD;
+1EA7:C7;
+1EA8:79;
+1EA9:CD;
+1EAA:61;
+1EAB:1B;
+1EAC:01;
+1EAD:1E;
+1EAE:1D;
+1EAF:18;
+1EB0:10;
+1EB1:0E;
+1EB2:03;
+1EB3:CD;
+1EB4:63;
+1EB5:19;
+1EB6:C1;
+1EB7:E5;
+1EB8:E5;
+1EB9:2A;
+1EBA:A2;
+1EBB:78;
+1EBC:E3;
+1EBD:3E;
+1EBE:91;
+1EBF:F5;
+1EC0:33;
+1EC1:C5;
+1EC2:CD;
+1EC3:5A;
+1EC4:1E;
+1EC5:CD;
+1EC6:07;
+1EC7:1F;
+1EC8:E5;
+1EC9:2A;
+1ECA:A2;
+1ECB:78;
+1ECC:DF;
+1ECD:E1;
+1ECE:23;
+1ECF:DC;
+1ED0:2F;
+1ED1:1B;
+1ED2:D4;
+1ED3:2C;
+1ED4:1B;
+1ED5:60;
+1ED6:69;
+1ED7:2B;
+1ED8:D8;
+1ED9:1E;
+1EDA:0E;
+1EDB:C3;
+1EDC:A2;
+1EDD:19;
+1EDE:C0;
+1EDF:16;
+1EE0:FF;
+1EE1:CD;
+1EE2:36;
+1EE3:19;
+1EE4:F9;
+1EE5:22;
+1EE6:E8;
+1EE7:78;
+1EE8:FE;
+1EE9:91;
+1EEA:1E;
+1EEB:04;
+1EEC:C2;
+1EED:A2;
+1EEE:19;
+1EEF:E1;
+1EF0:22;
+1EF1:A2;
+1EF2:78;
+1EF3:23;
+1EF4:7C;
+1EF5:B5;
+1EF6:20;
+1EF7:07;
+1EF8:3A;
+1EF9:DD;
+1EFA:78;
+1EFB:B7;
+1EFC:C2;
+1EFD:18;
+1EFE:1A;
+1EFF:21;
+1F00:1E;
+1F01:1D;
+1F02:E3;
+1F03:3E;
+1F04:E1;
+1F05:01;
+1F06:3A;
+1F07:0E;
+1F08:00;
+1F09:06;
+1F0A:00;
+1F0B:79;
+1F0C:48;
+1F0D:47;
+1F0E:7E;
+1F0F:B7;
+1F10:C8;
+1F11:B8;
+1F12:C8;
+1F13:23;
+1F14:FE;
+1F15:22;
+1F16:28;
+1F17:F3;
+1F18:D6;
+1F19:8F;
+1F1A:20;
+1F1B:F2;
+1F1C:B8;
+1F1D:8A;
+1F1E:57;
+1F1F:18;
+1F20:ED;
+1F21:CD;
+1F22:0D;
+1F23:26;
+1F24:CF;
+1F25:D5;
+1F26:EB;
+1F27:22;
+1F28:DF;
+1F29:78;
+1F2A:EB;
+1F2B:D5;
+1F2C:E7;
+1F2D:F5;
+1F2E:CD;
+1F2F:37;
+1F30:23;
+1F31:F1;
+1F32:E3;
+1F33:C6;
+1F34:03;
+1F35:CD;
+1F36:19;
+1F37:28;
+1F38:CD;
+1F39:03;
+1F3A:0A;
+1F3B:E5;
+1F3C:20;
+1F3D:28;
+1F3E:2A;
+1F3F:21;
+1F40:79;
+1F41:E5;
+1F42:23;
+1F43:5E;
+1F44:23;
+1F45:56;
+1F46:2A;
+1F47:A4;
+1F48:78;
+1F49:DF;
+1F4A:30;
+1F4B:0E;
+1F4C:2A;
+1F4D:A0;
+1F4E:78;
+1F4F:DF;
+1F50:D1;
+1F51:30;
+1F52:0F;
+1F53:2A;
+1F54:F9;
+1F55:78;
+1F56:DF;
+1F57:30;
+1F58:09;
+1F59:3E;
+1F5A:D1;
+1F5B:CD;
+1F5C:F5;
+1F5D:29;
+1F5E:EB;
+1F5F:CD;
+1F60:43;
+1F61:28;
+1F62:CD;
+1F63:F5;
+1F64:29;
+1F65:E3;
+1F66:CD;
+1F67:D3;
+1F68:09;
+1F69:D1;
+1F6A:E1;
+1F6B:C9;
+1F6C:FE;
+1F6D:9E;
+1F6E:20;
+1F6F:25;
+1F70:D7;
+1F71:CF;
+1F72:8D;
+1F73:CD;
+1F74:5A;
+1F75:1E;
+1F76:7A;
+1F77:B3;
+1F78:28;
+1F79:09;
+1F7A:CD;
+1F7B:2A;
+1F7C:1B;
+1F7D:50;
+1F7E:59;
+1F7F:E1;
+1F80:D2;
+1F81:D9;
+1F82:1E;
+1F83:EB;
+1F84:22;
+1F85:F0;
+1F86:78;
+1F87:EB;
+1F88:D8;
+1F89:3A;
+1F8A:F2;
+1F8B:78;
+1F8C:B7;
+1F8D:C8;
+1F8E:3A;
+1F8F:9A;
+1F90:78;
+1F91:5F;
+1F92:C3;
+1F93:AB;
+1F94:19;
+1F95:CD;
+1F96:1C;
+1F97:2B;
+1F98:7E;
+1F99:47;
+1F9A:FE;
+1F9B:91;
+1F9C:28;
+1F9D:03;
+1F9E:CF;
+1F9F:8D;
+1FA0:2B;
+1FA1:4B;
+1FA2:0D;
+1FA3:78;
+1FA4:CA;
+1FA5:60;
+1FA6:1D;
+1FA7:CD;
+1FA8:5B;
+1FA9:1E;
+1FAA:FE;
+1FAB:2C;
+1FAC:C0;
+1FAD:18;
+1FAE:F3;
+1FAF:11;
+1FB0:F2;
+1FB1:78;
+1FB2:1A;
+1FB3:B7;
+1FB4:CA;
+1FB5:A0;
+1FB6:19;
+1FB7:3C;
+1FB8:32;
+1FB9:9A;
+1FBA:78;
+1FBB:12;
+1FBC:7E;
+1FBD:FE;
+1FBE:87;
+1FBF:28;
+1FC0:0C;
+1FC1:CD;
+1FC2:5A;
+1FC3:1E;
+1FC4:C0;
+1FC5:7A;
+1FC6:B3;
+1FC7:C2;
+1FC8:C5;
+1FC9:1E;
+1FCA:3C;
+1FCB:18;
+1FCC:02;
+1FCD:D7;
+1FCE:C0;
+1FCF:2A;
+1FD0:EE;
+1FD1:78;
+1FD2:EB;
+1FD3:2A;
+1FD4:EA;
+1FD5:78;
+1FD6:22;
+1FD7:A2;
+1FD8:78;
+1FD9:EB;
+1FDA:C0;
+1FDB:7E;
+1FDC:B7;
+1FDD:20;
+1FDE:04;
+1FDF:23;
+1FE0:23;
+1FE1:23;
+1FE2:23;
+1FE3:23;
+1FE4:7A;
+1FE5:A3;
+1FE6:3C;
+1FE7:C2;
+1FE8:05;
+1FE9:1F;
+1FEA:3A;
+1FEB:DD;
+1FEC:78;
+1FED:3D;
+1FEE:CA;
+1FEF:BE;
+1FF0:1D;
+1FF1:C3;
+1FF2:05;
+1FF3:1F;
+1FF4:CD;
+1FF5:1C;
+1FF6:2B;
+1FF7:C0;
+1FF8:B7;
+1FF9:CA;
+1FFA:4A;
+1FFB:1E;
+1FFC:3D;
+1FFD:87;
+1FFE:5F;
+1FFF:FE;
+2000:2D;
+2001:38;
+2002:02;
+2003:1E;
+2004:26;
+2005:C3;
+2006:A2;
+2007:19;
+2008:11;
+2009:0A;
+200A:00;
+200B:D5;
+200C:28;
+200D:17;
+200E:CD;
+200F:4F;
+2010:1E;
+2011:EB;
+2012:E3;
+2013:28;
+2014:11;
+2015:EB;
+2016:CF;
+2017:2C;
+2018:EB;
+2019:2A;
+201A:E4;
+201B:78;
+201C:EB;
+201D:28;
+201E:06;
+201F:CD;
+2020:5A;
+2021:1E;
+2022:C2;
+2023:97;
+2024:19;
+2025:EB;
+2026:7C;
+2027:B5;
+2028:CA;
+2029:4A;
+202A:1E;
+202B:22;
+202C:E4;
+202D:78;
+202E:32;
+202F:E1;
+2030:78;
+2031:E1;
+2032:22;
+2033:E2;
+2034:78;
+2035:C1;
+2036:C3;
+2037:33;
+2038:1A;
+2039:CD;
+203A:37;
+203B:23;
+203C:7E;
+203D:FE;
+203E:2C;
+203F:CC;
+2040:78;
+2041:1D;
+2042:FE;
+2043:CA;
+2044:CC;
+2045:78;
+2046:1D;
+2047:2B;
+2048:E5;
+2049:CD;
+204A:94;
+204B:09;
+204C:E1;
+204D:28;
+204E:07;
+204F:D7;
+2050:DA;
+2051:C2;
+2052:1E;
+2053:C3;
+2054:5F;
+2055:1D;
+2056:16;
+2057:01;
+2058:CD;
+2059:05;
+205A:1F;
+205B:B7;
+205C:C8;
+205D:D7;
+205E:FE;
+205F:95;
+2060:20;
+2061:F6;
+2062:15;
+2063:20;
+2064:F3;
+2065:18;
+2066:E8;
+2067:3E;
+2068:01;
+2069:32;
+206A:9C;
+206B:78;
+206C:C3;
+206D:9B;
+206E:20;
+206F:CD;
+2070:CA;
+2071:79;
+2072:FE;
+2073:40;
+2074:20;
+2075:19;
+2076:CD;
+2077:01;
+2078:2B;
+2079:FE;
+207A:02;
+207B:D2;
+207C:4A;
+207D:1E;
+207E:E5;
+207F:21;
+2080:00;
+2081:70;
+2082:19;
+2083:22;
+2084:20;
+2085:78;
+2086:7B;
+2087:E6;
+2088:1F;
+2089:32;
+208A:A6;
+208B:78;
+208C:E1;
+208D:CF;
+208E:2C;
+208F:FE;
+2090:23;
+2091:20;
+2092:08;
+2093:CD;
+2094:58;
+2095:3B;
+2096:3E;
+2097:80;
+2098:32;
+2099:9C;
+209A:78;
+209B:2B;
+209C:D7;
+209D:CC;
+209E:FE;
+209F:20;
+20A0:CA;
+20A1:69;
+20A2:21;
+20A3:FE;
+20A4:BF;
+20A5:CA;
+20A6:BD;
+20A7:2C;
+20A8:FE;
+20A9:BC;
+20AA:CA;
+20AB:37;
+20AC:21;
+20AD:E5;
+20AE:FE;
+20AF:2C;
+20B0:CA;
+20B1:08;
+20B2:21;
+20B3:FE;
+20B4:3B;
+20B5:CA;
+20B6:0C;
+20B7:3B;
+20B8:C1;
+20B9:CD;
+20BA:37;
+20BB:23;
+20BC:E5;
+20BD:E7;
+20BE:28;
+20BF:32;
+20C0:CD;
+20C1:BD;
+20C2:0F;
+20C3:CD;
+20C4:65;
+20C5:28;
+20C6:CD;
+20C7:CD;
+20C8:79;
+20C9:2A;
+20CA:21;
+20CB:79;
+20CC:3A;
+20CD:9C;
+20CE:78;
+20CF:B7;
+20D0:FA;
+20D1:E9;
+20D2:20;
+20D3:28;
+20D4:08;
+20D5:3A;
+20D6:9B;
+20D7:78;
+20D8:86;
+20D9:FE;
+20DA:84;
+20DB:18;
+20DC:09;
+20DD:3A;
+20DE:9D;
+20DF:78;
+20E0:47;
+20E1:3A;
+20E2:A6;
+20E3:78;
+20E4:86;
+20E5:B8;
+20E6:D4;
+20E7:FE;
+20E8:20;
+20E9:CD;
+20EA:AA;
+20EB:28;
+20EC:3E;
+20ED:20;
+20EE:CD;
+20EF:2A;
+20F0:03;
+20F1:B7;
+20F2:CC;
+20F3:AA;
+20F4:28;
+20F5:E1;
+20F6:C3;
+20F7:9B;
+20F8:20;
+20F9:CD;
+20FA:1C;
+20FB:3B;
+20FC:B7;
+20FD:C8;
+20FE:3E;
+20FF:0D;
+2100:CD;
+2101:2A;
+2102:03;
+2103:CD;
+2104:D0;
+2105:79;
+2106:AF;
+2107:C9;
+2108:CD;
+2109:D3;
+210A:79;
+210B:3A;
+210C:9C;
+210D:78;
+210E:B7;
+210F:F2;
+2110:19;
+2111:21;
+2112:3E;
+2113:2C;
+2114:CD;
+2115:2A;
+2116:03;
+2117:18;
+2118:4B;
+2119:28;
+211A:08;
+211B:3A;
+211C:9B;
+211D:78;
+211E:FE;
+211F:70;
+2120:C3;
+2121:2B;
+2122:21;
+2123:3A;
+2124:9E;
+2125:78;
+2126:47;
+2127:3A;
+2128:AE;
+2129:7A;
+212A:B8;
+212B:D4;
+212C:FE;
+212D:20;
+212E:30;
+212F:34;
+2130:D6;
+2131:10;
+2132:30;
+2133:FC;
+2134:2F;
+2135:18;
+2136:23;
+2137:CD;
+2138:1B;
+2139:2B;
+213A:E6;
+213B:3F;
+213C:5F;
+213D:CF;
+213E:29;
+213F:2B;
+2140:E5;
+2141:CD;
+2142:D3;
+2143:79;
+2144:3A;
+2145:9C;
+2146:78;
+2147:B7;
+2148:FA;
+2149:4A;
+214A:1E;
+214B:CA;
+214C:53;
+214D:21;
+214E:3A;
+214F:9B;
+2150:78;
+2151:18;
+2152:03;
+2153:3A;
+2154:A6;
+2155:78;
+2156:2F;
+2157:83;
+2158:30;
+2159:0A;
+215A:3C;
+215B:47;
+215C:3E;
+215D:20;
+215E:CD;
+215F:2A;
+2160:03;
+2161:05;
+2162:20;
+2163:FA;
+2164:E1;
+2165:D7;
+2166:C3;
+2167:A0;
+2168:20;
+2169:3A;
+216A:9C;
+216B:78;
+216C:00;
+216D:00;
+216E:00;
+216F:00;
+2170:AF;
+2171:32;
+2172:9C;
+2173:78;
+2174:CD;
+2175:BE;
+2176:79;
+2177:C9;
+2178:3F;
+2179:52;
+217A:45;
+217B:44;
+217C:4F;
+217D:0D;
+217E:00;
+217F:3A;
+2180:DE;
+2181:78;
+2182:B7;
+2183:C2;
+2184:91;
+2185:19;
+2186:3A;
+2187:A9;
+2188:78;
+2189:B7;
+218A:1E;
+218B:2A;
+218C:CA;
+218D:A2;
+218E:19;
+218F:C1;
+2190:21;
+2191:78;
+2192:21;
+2193:CD;
+2194:A7;
+2195:28;
+2196:2A;
+2197:E6;
+2198:78;
+2199:C9;
+219A:CD;
+219B:28;
+219C:28;
+219D:7E;
+219E:CD;
+219F:D6;
+21A0:79;
+21A1:D6;
+21A2:23;
+21A3:32;
+21A4:A9;
+21A5:78;
+21A6:7E;
+21A7:20;
+21A8:20;
+21A9:CD;
+21AA:68;
+21AB:3B;
+21AC:E5;
+21AD:06;
+21AE:FA;
+21AF:2A;
+21B0:A7;
+21B1:78;
+21B2:CD;
+21B3:88;
+21B4:3B;
+21B5:77;
+21B6:23;
+21B7:FE;
+21B8:0D;
+21B9:28;
+21BA:02;
+21BB:10;
+21BC:F5;
+21BD:2B;
+21BE:36;
+21BF:00;
+21C0:00;
+21C1:00;
+21C2:00;
+21C3:2A;
+21C4:A7;
+21C5:78;
+21C6:2B;
+21C7:18;
+21C8:22;
+21C9:01;
+21CA:DB;
+21CB:21;
+21CC:C5;
+21CD:FE;
+21CE:22;
+21CF:C0;
+21D0:CD;
+21D1:66;
+21D2:28;
+21D3:CF;
+21D4:3B;
+21D5:E5;
+21D6:CD;
+21D7:AA;
+21D8:28;
+21D9:E1;
+21DA:C9;
+21DB:E5;
+21DC:CD;
+21DD:B3;
+21DE:1B;
+21DF:C1;
+21E0:DA;
+21E1:BE;
+21E2:1D;
+21E3:23;
+21E4:7E;
+21E5:B7;
+21E6:2B;
+21E7:C5;
+21E8:CA;
+21E9:04;
+21EA:1F;
+21EB:36;
+21EC:2C;
+21ED:18;
+21EE:05;
+21EF:E5;
+21F0:2A;
+21F1:FF;
+21F2:78;
+21F3:F6;
+21F4:AF;
+21F5:32;
+21F6:DE;
+21F7:78;
+21F8:E3;
+21F9:18;
+21FA:02;
+21FB:CF;
+21FC:2C;
+21FD:CD;
+21FE:0D;
+21FF:26;
+2200:E3;
+2201:D5;
+2202:7E;
+2203:FE;
+2204:2C;
+2205:28;
+2206:26;
+2207:3A;
+2208:DE;
+2209:78;
+220A:B7;
+220B:C2;
+220C:96;
+220D:22;
+220E:3A;
+220F:A9;
+2210:78;
+2211:B7;
+2212:1E;
+2213:06;
+2214:CA;
+2215:A2;
+2216:19;
+2217:3E;
+2218:3F;
+2219:CD;
+221A:2A;
+221B:03;
+221C:CD;
+221D:B3;
+221E:1B;
+221F:D1;
+2220:C1;
+2221:DA;
+2222:BE;
+2223:1D;
+2224:23;
+2225:7E;
+2226:B7;
+2227:2B;
+2228:C5;
+2229:CA;
+222A:04;
+222B:1F;
+222C:D5;
+222D:CD;
+222E:DC;
+222F:79;
+2230:E7;
+2231:F5;
+2232:20;
+2233:19;
+2234:D7;
+2235:57;
+2236:47;
+2237:FE;
+2238:22;
+2239:28;
+223A:05;
+223B:16;
+223C:3A;
+223D:06;
+223E:2C;
+223F:2B;
+2240:CD;
+2241:69;
+2242:28;
+2243:F1;
+2244:EB;
+2245:21;
+2246:5A;
+2247:22;
+2248:E3;
+2249:D5;
+224A:C3;
+224B:33;
+224C:1F;
+224D:D7;
+224E:F1;
+224F:F5;
+2250:01;
+2251:43;
+2252:22;
+2253:C5;
+2254:DA;
+2255:6C;
+2256:0E;
+2257:D2;
+2258:65;
+2259:0E;
+225A:2B;
+225B:D7;
+225C:28;
+225D:05;
+225E:FE;
+225F:2C;
+2260:C2;
+2261:7F;
+2262:21;
+2263:E3;
+2264:2B;
+2265:D7;
+2266:C2;
+2267:FB;
+2268:21;
+2269:D1;
+226A:00;
+226B:00;
+226C:00;
+226D:00;
+226E:00;
+226F:3A;
+2270:DE;
+2271:78;
+2272:B7;
+2273:EB;
+2274:C2;
+2275:96;
+2276:1D;
+2277:D5;
+2278:CD;
+2279:DF;
+227A:79;
+227B:B6;
+227C:21;
+227D:86;
+227E:22;
+227F:C4;
+2280:A7;
+2281:28;
+2282:E1;
+2283:C3;
+2284:69;
+2285:21;
+2286:3F;
+2287:45;
+2288:58;
+2289:54;
+228A:52;
+228B:41;
+228C:20;
+228D:49;
+228E:47;
+228F:4E;
+2290:4F;
+2291:52;
+2292:45;
+2293:44;
+2294:0D;
+2295:00;
+2296:CD;
+2297:05;
+2298:1F;
+2299:B7;
+229A:20;
+229B:12;
+229C:23;
+229D:7E;
+229E:23;
+229F:B6;
+22A0:1E;
+22A1:06;
+22A2:CA;
+22A3:A2;
+22A4:19;
+22A5:23;
+22A6:5E;
+22A7:23;
+22A8:56;
+22A9:EB;
+22AA:22;
+22AB:DA;
+22AC:78;
+22AD:EB;
+22AE:D7;
+22AF:FE;
+22B0:88;
+22B1:20;
+22B2:E3;
+22B3:C3;
+22B4:2D;
+22B5:22;
+22B6:11;
+22B7:00;
+22B8:00;
+22B9:C4;
+22BA:0D;
+22BB:26;
+22BC:22;
+22BD:DF;
+22BE:78;
+22BF:CD;
+22C0:36;
+22C1:19;
+22C2:C2;
+22C3:9D;
+22C4:19;
+22C5:F9;
+22C6:22;
+22C7:E8;
+22C8:78;
+22C9:D5;
+22CA:7E;
+22CB:23;
+22CC:F5;
+22CD:D5;
+22CE:7E;
+22CF:23;
+22D0:B7;
+22D1:FA;
+22D2:EA;
+22D3:22;
+22D4:CD;
+22D5:B1;
+22D6:09;
+22D7:E3;
+22D8:E5;
+22D9:CD;
+22DA:0B;
+22DB:07;
+22DC:E1;
+22DD:CD;
+22DE:CB;
+22DF:09;
+22E0:E1;
+22E1:CD;
+22E2:C2;
+22E3:09;
+22E4:E5;
+22E5:CD;
+22E6:0C;
+22E7:0A;
+22E8:18;
+22E9:29;
+22EA:23;
+22EB:23;
+22EC:23;
+22ED:23;
+22EE:4E;
+22EF:23;
+22F0:46;
+22F1:23;
+22F2:E3;
+22F3:5E;
+22F4:23;
+22F5:56;
+22F6:E5;
+22F7:69;
+22F8:60;
+22F9:CD;
+22FA:D2;
+22FB:0B;
+22FC:3A;
+22FD:AF;
+22FE:78;
+22FF:FE;
+2300:04;
+2301:CA;
+2302:B2;
+2303:07;
+2304:EB;
+2305:E1;
+2306:72;
+2307:2B;
+2308:73;
+2309:E1;
+230A:D5;
+230B:5E;
+230C:23;
+230D:56;
+230E:23;
+230F:E3;
+2310:CD;
+2311:39;
+2312:0A;
+2313:E1;
+2314:C1;
+2315:90;
+2316:CD;
+2317:C2;
+2318:09;
+2319:28;
+231A:09;
+231B:EB;
+231C:22;
+231D:A2;
+231E:78;
+231F:69;
+2320:60;
+2321:C3;
+2322:1A;
+2323:1D;
+2324:F9;
+2325:22;
+2326:E8;
+2327:78;
+2328:2A;
+2329:DF;
+232A:78;
+232B:7E;
+232C:FE;
+232D:2C;
+232E:C2;
+232F:1E;
+2330:1D;
+2331:D7;
+2332:CD;
+2333:B9;
+2334:22;
+2335:CF;
+2336:28;
+2337:2B;
+2338:16;
+2339:00;
+233A:D5;
+233B:0E;
+233C:01;
+233D:CD;
+233E:63;
+233F:19;
+2340:CD;
+2341:9F;
+2342:24;
+2343:22;
+2344:F3;
+2345:78;
+2346:2A;
+2347:F3;
+2348:78;
+2349:C1;
+234A:7E;
+234B:16;
+234C:00;
+234D:D6;
+234E:D4;
+234F:38;
+2350:13;
+2351:FE;
+2352:03;
+2353:30;
+2354:0F;
+2355:FE;
+2356:01;
+2357:17;
+2358:AA;
+2359:BA;
+235A:57;
+235B:DA;
+235C:97;
+235D:19;
+235E:22;
+235F:D8;
+2360:78;
+2361:D7;
+2362:18;
+2363:E9;
+2364:7A;
+2365:B7;
+2366:C2;
+2367:EC;
+2368:23;
+2369:7E;
+236A:22;
+236B:D8;
+236C:78;
+236D:D6;
+236E:CD;
+236F:D8;
+2370:FE;
+2371:07;
+2372:D0;
+2373:5F;
+2374:3A;
+2375:AF;
+2376:78;
+2377:D6;
+2378:03;
+2379:B3;
+237A:CA;
+237B:8F;
+237C:29;
+237D:21;
+237E:9A;
+237F:18;
+2380:19;
+2381:78;
+2382:56;
+2383:BA;
+2384:D0;
+2385:C5;
+2386:01;
+2387:46;
+2388:23;
+2389:C5;
+238A:7A;
+238B:FE;
+238C:7F;
+238D:CA;
+238E:D4;
+238F:23;
+2390:FE;
+2391:51;
+2392:DA;
+2393:E1;
+2394:23;
+2395:21;
+2396:21;
+2397:79;
+2398:B7;
+2399:3A;
+239A:AF;
+239B:78;
+239C:3D;
+239D:3D;
+239E:3D;
+239F:CA;
+23A0:F6;
+23A1:0A;
+23A2:4E;
+23A3:23;
+23A4:46;
+23A5:C5;
+23A6:FA;
+23A7:C5;
+23A8:23;
+23A9:23;
+23AA:4E;
+23AB:23;
+23AC:46;
+23AD:C5;
+23AE:F5;
+23AF:B7;
+23B0:E2;
+23B1:C4;
+23B2:23;
+23B3:F1;
+23B4:23;
+23B5:38;
+23B6:03;
+23B7:21;
+23B8:1D;
+23B9:79;
+23BA:4E;
+23BB:23;
+23BC:46;
+23BD:23;
+23BE:C5;
+23BF:4E;
+23C0:23;
+23C1:46;
+23C2:C5;
+23C3:06;
+23C4:F1;
+23C5:C6;
+23C6:03;
+23C7:4B;
+23C8:47;
+23C9:C5;
+23CA:01;
+23CB:06;
+23CC:24;
+23CD:C5;
+23CE:2A;
+23CF:D8;
+23D0:78;
+23D1:C3;
+23D2:3A;
+23D3:23;
+23D4:CD;
+23D5:B1;
+23D6:0A;
+23D7:CD;
+23D8:A4;
+23D9:09;
+23DA:01;
+23DB:F2;
+23DC:13;
+23DD:16;
+23DE:7F;
+23DF:18;
+23E0:EC;
+23E1:D5;
+23E2:CD;
+23E3:7F;
+23E4:0A;
+23E5:D1;
+23E6:E5;
+23E7:01;
+23E8:E9;
+23E9:25;
+23EA:18;
+23EB:E1;
+23EC:78;
+23ED:FE;
+23EE:64;
+23EF:D0;
+23F0:C5;
+23F1:D5;
+23F2:11;
+23F3:04;
+23F4:64;
+23F5:21;
+23F6:B8;
+23F7:25;
+23F8:E5;
+23F9:E7;
+23FA:C2;
+23FB:95;
+23FC:23;
+23FD:2A;
+23FE:21;
+23FF:79;
+2400:E5;
+2401:01;
+2402:8C;
+2403:25;
+2404:18;
+2405:C7;
+2406:C1;
+2407:79;
+2408:32;
+2409:B0;
+240A:78;
+240B:78;
+240C:FE;
+240D:08;
+240E:28;
+240F:28;
+2410:3A;
+2411:AF;
+2412:78;
+2413:FE;
+2414:08;
+2415:CA;
+2416:60;
+2417:24;
+2418:57;
+2419:78;
+241A:FE;
+241B:04;
+241C:CA;
+241D:72;
+241E:24;
+241F:7A;
+2420:FE;
+2421:03;
+2422:CA;
+2423:F6;
+2424:0A;
+2425:D2;
+2426:7C;
+2427:24;
+2428:21;
+2429:BF;
+242A:18;
+242B:06;
+242C:00;
+242D:09;
+242E:09;
+242F:4E;
+2430:23;
+2431:46;
+2432:D1;
+2433:2A;
+2434:21;
+2435:79;
+2436:C5;
+2437:C9;
+2438:CD;
+2439:DB;
+243A:0A;
+243B:CD;
+243C:FC;
+243D:09;
+243E:E1;
+243F:22;
+2440:1F;
+2441:79;
+2442:E1;
+2443:22;
+2444:1D;
+2445:79;
+2446:C1;
+2447:D1;
+2448:CD;
+2449:B4;
+244A:09;
+244B:CD;
+244C:DB;
+244D:0A;
+244E:21;
+244F:AB;
+2450:18;
+2451:3A;
+2452:B0;
+2453:78;
+2454:07;
+2455:C5;
+2456:4F;
+2457:06;
+2458:00;
+2459:09;
+245A:C1;
+245B:7E;
+245C:23;
+245D:66;
+245E:6F;
+245F:E9;
+2460:C5;
+2461:CD;
+2462:FC;
+2463:09;
+2464:F1;
+2465:32;
+2466:AF;
+2467:78;
+2468:FE;
+2469:04;
+246A:28;
+246B:DA;
+246C:E1;
+246D:22;
+246E:21;
+246F:79;
+2470:18;
+2471:D9;
+2472:CD;
+2473:B1;
+2474:0A;
+2475:C1;
+2476:D1;
+2477:21;
+2478:B5;
+2479:18;
+247A:18;
+247B:D5;
+247C:E1;
+247D:CD;
+247E:A4;
+247F:09;
+2480:CD;
+2481:CF;
+2482:0A;
+2483:CD;
+2484:BF;
+2485:09;
+2486:E1;
+2487:22;
+2488:23;
+2489:79;
+248A:E1;
+248B:22;
+248C:21;
+248D:79;
+248E:18;
+248F:E7;
+2490:E5;
+2491:EB;
+2492:CD;
+2493:CF;
+2494:0A;
+2495:E1;
+2496:CD;
+2497:A4;
+2498:09;
+2499:CD;
+249A:CF;
+249B:0A;
+249C:C3;
+249D:A0;
+249E:08;
+249F:D7;
+24A0:1E;
+24A1:28;
+24A2:CA;
+24A3:A2;
+24A4:19;
+24A5:DA;
+24A6:6C;
+24A7:0E;
+24A8:CD;
+24A9:3D;
+24AA:1E;
+24AB:D2;
+24AC:40;
+24AD:25;
+24AE:FE;
+24AF:CD;
+24B0:28;
+24B1:ED;
+24B2:FE;
+24B3:2E;
+24B4:CA;
+24B5:6C;
+24B6:0E;
+24B7:FE;
+24B8:CE;
+24B9:CA;
+24BA:32;
+24BB:25;
+24BC:FE;
+24BD:22;
+24BE:CA;
+24BF:66;
+24C0:28;
+24C1:FE;
+24C2:CB;
+24C3:CA;
+24C4:C4;
+24C5:25;
+24C6:FE;
+24C7:26;
+24C8:CA;
+24C9:94;
+24CA:79;
+24CB:FE;
+24CC:C3;
+24CD:20;
+24CE:0A;
+24CF:D7;
+24D0:3A;
+24D1:9A;
+24D2:78;
+24D3:E5;
+24D4:CD;
+24D5:F8;
+24D6:27;
+24D7:E1;
+24D8:C9;
+24D9:FE;
+24DA:C2;
+24DB:20;
+24DC:0A;
+24DD:D7;
+24DE:E5;
+24DF:2A;
+24E0:EA;
+24E1:78;
+24E2:CD;
+24E3:66;
+24E4:0C;
+24E5:E1;
+24E6:C9;
+24E7:FE;
+24E8:C0;
+24E9:20;
+24EA:14;
+24EB:D7;
+24EC:CF;
+24ED:28;
+24EE:CD;
+24EF:0D;
+24F0:26;
+24F1:CF;
+24F2:29;
+24F3:E5;
+24F4:EB;
+24F5:7C;
+24F6:B5;
+24F7:CA;
+24F8:4A;
+24F9:1E;
+24FA:CD;
+24FB:9A;
+24FC:0A;
+24FD:E1;
+24FE:C9;
+24FF:FE;
+2500:C1;
+2501:CA;
+2502:FE;
+2503:27;
+2504:FE;
+2505:C5;
+2506:CA;
+2507:9D;
+2508:79;
+2509:FE;
+250A:C8;
+250B:CA;
+250C:C9;
+250D:27;
+250E:FE;
+250F:C7;
+2510:CA;
+2511:76;
+2512:79;
+2513:FE;
+2514:C6;
+2515:CA;
+2516:32;
+2517:01;
+2518:FE;
+2519:C9;
+251A:CA;
+251B:9D;
+251C:01;
+251D:FE;
+251E:C4;
+251F:CA;
+2520:2F;
+2521:2A;
+2522:FE;
+2523:BE;
+2524:CA;
+2525:55;
+2526:79;
+2527:D6;
+2528:D7;
+2529:D2;
+252A:4E;
+252B:25;
+252C:CD;
+252D:35;
+252E:23;
+252F:CF;
+2530:29;
+2531:C9;
+2532:16;
+2533:7D;
+2534:CD;
+2535:3A;
+2536:23;
+2537:2A;
+2538:F3;
+2539:78;
+253A:E5;
+253B:CD;
+253C:7B;
+253D:09;
+253E:E1;
+253F:C9;
+2540:CD;
+2541:0D;
+2542:26;
+2543:E5;
+2544:EB;
+2545:22;
+2546:21;
+2547:79;
+2548:E7;
+2549:C4;
+254A:F7;
+254B:09;
+254C:E1;
+254D:C9;
+254E:06;
+254F:00;
+2550:07;
+2551:4F;
+2552:C5;
+2553:D7;
+2554:79;
+2555:FE;
+2556:41;
+2557:38;
+2558:16;
+2559:CD;
+255A:35;
+255B:23;
+255C:CF;
+255D:2C;
+255E:CD;
+255F:F4;
+2560:0A;
+2561:EB;
+2562:2A;
+2563:21;
+2564:79;
+2565:E3;
+2566:E5;
+2567:EB;
+2568:CD;
+2569:1C;
+256A:2B;
+256B:EB;
+256C:E3;
+256D:18;
+256E:14;
+256F:CD;
+2570:2C;
+2571:25;
+2572:E3;
+2573:7D;
+2574:FE;
+2575:0C;
+2576:38;
+2577:07;
+2578:FE;
+2579:1B;
+257A:E5;
+257B:DC;
+257C:B1;
+257D:0A;
+257E:E1;
+257F:11;
+2580:3E;
+2581:25;
+2582:D5;
+2583:01;
+2584:08;
+2585:16;
+2586:09;
+2587:4E;
+2588:23;
+2589:66;
+258A:69;
+258B:E9;
+258C:CD;
+258D:D7;
+258E:29;
+258F:7E;
+2590:23;
+2591:4E;
+2592:23;
+2593:46;
+2594:D1;
+2595:C5;
+2596:F5;
+2597:CD;
+2598:DE;
+2599:29;
+259A:D1;
+259B:5E;
+259C:23;
+259D:4E;
+259E:23;
+259F:46;
+25A0:E1;
+25A1:7B;
+25A2:B2;
+25A3:C8;
+25A4:7A;
+25A5:D6;
+25A6:01;
+25A7:D8;
+25A8:AF;
+25A9:BB;
+25AA:3C;
+25AB:D0;
+25AC:15;
+25AD:1D;
+25AE:0A;
+25AF:BE;
+25B0:23;
+25B1:03;
+25B2:28;
+25B3:ED;
+25B4:3F;
+25B5:C3;
+25B6:60;
+25B7:09;
+25B8:3C;
+25B9:8F;
+25BA:C1;
+25BB:A0;
+25BC:C6;
+25BD:FF;
+25BE:9F;
+25BF:CD;
+25C0:8D;
+25C1:09;
+25C2:18;
+25C3:12;
+25C4:16;
+25C5:5A;
+25C6:CD;
+25C7:3A;
+25C8:23;
+25C9:CD;
+25CA:7F;
+25CB:0A;
+25CC:7D;
+25CD:2F;
+25CE:6F;
+25CF:7C;
+25D0:2F;
+25D1:67;
+25D2:22;
+25D3:21;
+25D4:79;
+25D5:C1;
+25D6:C3;
+25D7:46;
+25D8:23;
+25D9:3A;
+25DA:AF;
+25DB:78;
+25DC:FE;
+25DD:08;
+25DE:30;
+25DF:05;
+25E0:D6;
+25E1:03;
+25E2:B7;
+25E3:37;
+25E4:C9;
+25E5:D6;
+25E6:03;
+25E7:B7;
+25E8:C9;
+25E9:C5;
+25EA:CD;
+25EB:7F;
+25EC:0A;
+25ED:F1;
+25EE:D1;
+25EF:01;
+25F0:FA;
+25F1:27;
+25F2:C5;
+25F3:FE;
+25F4:46;
+25F5:20;
+25F6:06;
+25F7:7B;
+25F8:B5;
+25F9:6F;
+25FA:7C;
+25FB:B2;
+25FC:C9;
+25FD:7B;
+25FE:A5;
+25FF:6F;
+2600:7C;
+2601:A2;
+2602:C9;
+2603:2B;
+2604:D7;
+2605:C8;
+2606:CF;
+2607:2C;
+2608:01;
+2609:03;
+260A:26;
+260B:C5;
+260C:F6;
+260D:AF;
+260E:32;
+260F:AE;
+2610:78;
+2611:46;
+2612:CD;
+2613:3D;
+2614:1E;
+2615:DA;
+2616:97;
+2617:19;
+2618:AF;
+2619:4F;
+261A:D7;
+261B:38;
+261C:05;
+261D:CD;
+261E:3D;
+261F:1E;
+2620:38;
+2621:09;
+2622:4F;
+2623:D7;
+2624:38;
+2625:FD;
+2626:CD;
+2627:3D;
+2628:1E;
+2629:30;
+262A:F8;
+262B:11;
+262C:52;
+262D:26;
+262E:D5;
+262F:16;
+2630:02;
+2631:FE;
+2632:25;
+2633:C8;
+2634:14;
+2635:FE;
+2636:24;
+2637:C8;
+2638:00;
+2639:00;
+263A:00;
+263B:00;
+263C:00;
+263D:00;
+263E:00;
+263F:00;
+2640:00;
+2641:78;
+2642:D6;
+2643:41;
+2644:E6;
+2645:7F;
+2646:5F;
+2647:16;
+2648:00;
+2649:E5;
+264A:21;
+264B:01;
+264C:79;
+264D:19;
+264E:56;
+264F:E1;
+2650:2B;
+2651:C9;
+2652:7A;
+2653:32;
+2654:AF;
+2655:78;
+2656:D7;
+2657:3A;
+2658:DC;
+2659:78;
+265A:B7;
+265B:C2;
+265C:64;
+265D:26;
+265E:7E;
+265F:D6;
+2660:28;
+2661:CA;
+2662:E9;
+2663:26;
+2664:AF;
+2665:32;
+2666:DC;
+2667:78;
+2668:E5;
+2669:D5;
+266A:2A;
+266B:F9;
+266C:78;
+266D:EB;
+266E:2A;
+266F:FB;
+2670:78;
+2671:DF;
+2672:E1;
+2673:28;
+2674:19;
+2675:1A;
+2676:6F;
+2677:BC;
+2678:13;
+2679:20;
+267A:0B;
+267B:1A;
+267C:B9;
+267D:20;
+267E:07;
+267F:13;
+2680:1A;
+2681:B8;
+2682:CA;
+2683:CC;
+2684:26;
+2685:3E;
+2686:13;
+2687:13;
+2688:E5;
+2689:26;
+268A:00;
+268B:19;
+268C:18;
+268D:DF;
+268E:7C;
+268F:E1;
+2690:E3;
+2691:F5;
+2692:D5;
+2693:11;
+2694:F1;
+2695:24;
+2696:DF;
+2697:28;
+2698:36;
+2699:11;
+269A:43;
+269B:25;
+269C:DF;
+269D:D1;
+269E:28;
+269F:35;
+26A0:F1;
+26A1:E3;
+26A2:E5;
+26A3:C5;
+26A4:4F;
+26A5:06;
+26A6:00;
+26A7:C5;
+26A8:03;
+26A9:03;
+26AA:03;
+26AB:2A;
+26AC:FD;
+26AD:78;
+26AE:E5;
+26AF:09;
+26B0:C1;
+26B1:E5;
+26B2:CD;
+26B3:55;
+26B4:19;
+26B5:E1;
+26B6:22;
+26B7:FD;
+26B8:78;
+26B9:60;
+26BA:69;
+26BB:22;
+26BC:FB;
+26BD:78;
+26BE:2B;
+26BF:36;
+26C0:00;
+26C1:DF;
+26C2:20;
+26C3:FA;
+26C4:D1;
+26C5:73;
+26C6:23;
+26C7:D1;
+26C8:73;
+26C9:23;
+26CA:72;
+26CB:EB;
+26CC:13;
+26CD:E1;
+26CE:C9;
+26CF:57;
+26D0:5F;
+26D1:F1;
+26D2:F1;
+26D3:E3;
+26D4:C9;
+26D5:32;
+26D6:24;
+26D7:79;
+26D8:C1;
+26D9:67;
+26DA:6F;
+26DB:22;
+26DC:21;
+26DD:79;
+26DE:E7;
+26DF:20;
+26E0:06;
+26E1:21;
+26E2:28;
+26E3:19;
+26E4:22;
+26E5:21;
+26E6:79;
+26E7:E1;
+26E8:C9;
+26E9:E5;
+26EA:2A;
+26EB:AE;
+26EC:78;
+26ED:E3;
+26EE:57;
+26EF:D5;
+26F0:C5;
+26F1:CD;
+26F2:45;
+26F3:1E;
+26F4:C1;
+26F5:F1;
+26F6:EB;
+26F7:E3;
+26F8:E5;
+26F9:EB;
+26FA:3C;
+26FB:57;
+26FC:7E;
+26FD:FE;
+26FE:2C;
+26FF:28;
+2700:EE;
+2701:CF;
+2702:29;
+2703:22;
+2704:F3;
+2705:78;
+2706:E1;
+2707:22;
+2708:AE;
+2709:78;
+270A:D5;
+270B:2A;
+270C:FB;
+270D:78;
+270E:3E;
+270F:19;
+2710:EB;
+2711:2A;
+2712:FD;
+2713:78;
+2714:EB;
+2715:DF;
+2716:3A;
+2717:AF;
+2718:78;
+2719:28;
+271A:27;
+271B:BE;
+271C:23;
+271D:20;
+271E:08;
+271F:7E;
+2720:B9;
+2721:23;
+2722:20;
+2723:04;
+2724:7E;
+2725:B8;
+2726:3E;
+2727:23;
+2728:23;
+2729:5E;
+272A:23;
+272B:56;
+272C:23;
+272D:20;
+272E:E0;
+272F:3A;
+2730:AE;
+2731:78;
+2732:B7;
+2733:1E;
+2734:12;
+2735:C2;
+2736:A2;
+2737:19;
+2738:F1;
+2739:96;
+273A:CA;
+273B:95;
+273C:27;
+273D:1E;
+273E:10;
+273F:C3;
+2740:A2;
+2741:19;
+2742:77;
+2743:23;
+2744:5F;
+2745:16;
+2746:00;
+2747:F1;
+2748:71;
+2749:23;
+274A:70;
+274B:23;
+274C:4F;
+274D:CD;
+274E:63;
+274F:19;
+2750:23;
+2751:23;
+2752:22;
+2753:D8;
+2754:78;
+2755:71;
+2756:23;
+2757:3A;
+2758:AE;
+2759:78;
+275A:17;
+275B:79;
+275C:01;
+275D:0B;
+275E:00;
+275F:30;
+2760:02;
+2761:C1;
+2762:03;
+2763:71;
+2764:23;
+2765:70;
+2766:23;
+2767:F5;
+2768:CD;
+2769:AA;
+276A:0B;
+276B:F1;
+276C:3D;
+276D:20;
+276E:ED;
+276F:F5;
+2770:42;
+2771:4B;
+2772:EB;
+2773:19;
+2774:38;
+2775:C7;
+2776:CD;
+2777:6C;
+2778:19;
+2779:22;
+277A:FD;
+277B:78;
+277C:2B;
+277D:36;
+277E:00;
+277F:DF;
+2780:20;
+2781:FA;
+2782:03;
+2783:57;
+2784:2A;
+2785:D8;
+2786:78;
+2787:5E;
+2788:EB;
+2789:29;
+278A:09;
+278B:EB;
+278C:2B;
+278D:2B;
+278E:73;
+278F:23;
+2790:72;
+2791:23;
+2792:F1;
+2793:38;
+2794:30;
+2795:47;
+2796:4F;
+2797:7E;
+2798:23;
+2799:16;
+279A:E1;
+279B:5E;
+279C:23;
+279D:56;
+279E:23;
+279F:E3;
+27A0:F5;
+27A1:DF;
+27A2:D2;
+27A3:3D;
+27A4:27;
+27A5:CD;
+27A6:AA;
+27A7:0B;
+27A8:19;
+27A9:F1;
+27AA:3D;
+27AB:44;
+27AC:4D;
+27AD:20;
+27AE:EB;
+27AF:3A;
+27B0:AF;
+27B1:78;
+27B2:44;
+27B3:4D;
+27B4:29;
+27B5:D6;
+27B6:04;
+27B7:38;
+27B8:04;
+27B9:29;
+27BA:28;
+27BB:06;
+27BC:29;
+27BD:B7;
+27BE:E2;
+27BF:C2;
+27C0:27;
+27C1:09;
+27C2:C1;
+27C3:09;
+27C4:EB;
+27C5:2A;
+27C6:F3;
+27C7:78;
+27C8:C9;
+27C9:AF;
+27CA:E5;
+27CB:32;
+27CC:AF;
+27CD:78;
+27CE:CD;
+27CF:D4;
+27D0:27;
+27D1:E1;
+27D2:D7;
+27D3:C9;
+27D4:2A;
+27D5:FD;
+27D6:78;
+27D7:EB;
+27D8:21;
+27D9:00;
+27DA:00;
+27DB:39;
+27DC:E7;
+27DD:20;
+27DE:0D;
+27DF:CD;
+27E0:DA;
+27E1:29;
+27E2:CD;
+27E3:E6;
+27E4:28;
+27E5:2A;
+27E6:A0;
+27E7:78;
+27E8:EB;
+27E9:2A;
+27EA:D6;
+27EB:78;
+27EC:7D;
+27ED:93;
+27EE:6F;
+27EF:7C;
+27F0:9A;
+27F1:67;
+27F2:C3;
+27F3:66;
+27F4:0C;
+27F5:3A;
+27F6:A6;
+27F7:78;
+27F8:6F;
+27F9:AF;
+27FA:67;
+27FB:C3;
+27FC:9A;
+27FD:0A;
+27FE:CD;
+27FF:A9;
+2800:79;
+2801:D7;
+2802:CD;
+2803:2C;
+2804:25;
+2805:E5;
+2806:21;
+2807:90;
+2808:08;
+2809:E5;
+280A:3A;
+280B:AF;
+280C:78;
+280D:F5;
+280E:FE;
+280F:03;
+2810:CC;
+2811:DA;
+2812:29;
+2813:F1;
+2814:EB;
+2815:2A;
+2816:8E;
+2817:78;
+2818:E9;
+2819:E5;
+281A:E6;
+281B:07;
+281C:21;
+281D:A1;
+281E:18;
+281F:4F;
+2820:06;
+2821:00;
+2822:09;
+2823:CD;
+2824:86;
+2825:25;
+2826:E1;
+2827:C9;
+2828:E5;
+2829:2A;
+282A:A2;
+282B:78;
+282C:23;
+282D:7C;
+282E:B5;
+282F:E1;
+2830:C0;
+2831:1E;
+2832:16;
+2833:C3;
+2834:A2;
+2835:19;
+2836:CD;
+2837:BD;
+2838:0F;
+2839:CD;
+283A:65;
+283B:28;
+283C:CD;
+283D:DA;
+283E:29;
+283F:01;
+2840:2B;
+2841:2A;
+2842:C5;
+2843:7E;
+2844:23;
+2845:E5;
+2846:CD;
+2847:BF;
+2848:28;
+2849:E1;
+284A:4E;
+284B:23;
+284C:46;
+284D:CD;
+284E:5A;
+284F:28;
+2850:E5;
+2851:6F;
+2852:CD;
+2853:CE;
+2854:29;
+2855:D1;
+2856:C9;
+2857:CD;
+2858:BF;
+2859:28;
+285A:21;
+285B:D3;
+285C:78;
+285D:E5;
+285E:77;
+285F:23;
+2860:73;
+2861:23;
+2862:72;
+2863:E1;
+2864:C9;
+2865:2B;
+2866:06;
+2867:22;
+2868:50;
+2869:E5;
+286A:0E;
+286B:FF;
+286C:23;
+286D:7E;
+286E:0C;
+286F:B7;
+2870:28;
+2871:06;
+2872:BA;
+2873:28;
+2874:03;
+2875:B8;
+2876:20;
+2877:F4;
+2878:FE;
+2879:22;
+287A:CC;
+287B:78;
+287C:1D;
+287D:E3;
+287E:23;
+287F:EB;
+2880:79;
+2881:CD;
+2882:5A;
+2883:28;
+2884:11;
+2885:D3;
+2886:78;
+2887:3E;
+2888:D5;
+2889:2A;
+288A:B3;
+288B:78;
+288C:22;
+288D:21;
+288E:79;
+288F:3E;
+2890:03;
+2891:32;
+2892:AF;
+2893:78;
+2894:CD;
+2895:D3;
+2896:09;
+2897:11;
+2898:D6;
+2899:78;
+289A:DF;
+289B:22;
+289C:B3;
+289D:78;
+289E:E1;
+289F:7E;
+28A0:C0;
+28A1:1E;
+28A2:1E;
+28A3:C3;
+28A4:A2;
+28A5:19;
+28A6:23;
+28A7:CD;
+28A8:65;
+28A9:28;
+28AA:CD;
+28AB:DA;
+28AC:29;
+28AD:CD;
+28AE:C4;
+28AF:09;
+28B0:14;
+28B1:15;
+28B2:C8;
+28B3:0A;
+28B4:CD;
+28B5:2A;
+28B6:03;
+28B7:FE;
+28B8:0D;
+28B9:CC;
+28BA:03;
+28BB:21;
+28BC:03;
+28BD:18;
+28BE:F2;
+28BF:B7;
+28C0:0E;
+28C1:F1;
+28C2:F5;
+28C3:2A;
+28C4:A0;
+28C5:78;
+28C6:EB;
+28C7:2A;
+28C8:D6;
+28C9:78;
+28CA:2F;
+28CB:4F;
+28CC:06;
+28CD:FF;
+28CE:09;
+28CF:23;
+28D0:DF;
+28D1:38;
+28D2:07;
+28D3:22;
+28D4:D6;
+28D5:78;
+28D6:23;
+28D7:EB;
+28D8:F1;
+28D9:C9;
+28DA:F1;
+28DB:1E;
+28DC:1A;
+28DD:CA;
+28DE:A2;
+28DF:19;
+28E0:BF;
+28E1:F5;
+28E2:01;
+28E3:C1;
+28E4:28;
+28E5:C5;
+28E6:2A;
+28E7:B1;
+28E8:78;
+28E9:22;
+28EA:D6;
+28EB:78;
+28EC:21;
+28ED:00;
+28EE:00;
+28EF:E5;
+28F0:2A;
+28F1:A0;
+28F2:78;
+28F3:E5;
+28F4:21;
+28F5:B5;
+28F6:78;
+28F7:EB;
+28F8:2A;
+28F9:B3;
+28FA:78;
+28FB:EB;
+28FC:DF;
+28FD:01;
+28FE:F7;
+28FF:28;
+2900:C2;
+2901:4A;
+2902:29;
+2903:2A;
+2904:F9;
+2905:78;
+2906:EB;
+2907:2A;
+2908:FB;
+2909:78;
+290A:EB;
+290B:DF;
+290C:28;
+290D:13;
+290E:7E;
+290F:23;
+2910:23;
+2911:23;
+2912:FE;
+2913:03;
+2914:20;
+2915:04;
+2916:CD;
+2917:4B;
+2918:29;
+2919:AF;
+291A:5F;
+291B:16;
+291C:00;
+291D:19;
+291E:18;
+291F:E6;
+2920:C1;
+2921:EB;
+2922:2A;
+2923:FD;
+2924:78;
+2925:EB;
+2926:DF;
+2927:CA;
+2928:6B;
+2929:29;
+292A:7E;
+292B:23;
+292C:CD;
+292D:C2;
+292E:09;
+292F:E5;
+2930:09;
+2931:FE;
+2932:03;
+2933:20;
+2934:EB;
+2935:22;
+2936:D8;
+2937:78;
+2938:E1;
+2939:4E;
+293A:06;
+293B:00;
+293C:09;
+293D:09;
+293E:23;
+293F:EB;
+2940:2A;
+2941:D8;
+2942:78;
+2943:EB;
+2944:DF;
+2945:28;
+2946:DA;
+2947:01;
+2948:3F;
+2949:29;
+294A:C5;
+294B:AF;
+294C:B6;
+294D:23;
+294E:5E;
+294F:23;
+2950:56;
+2951:23;
+2952:C8;
+2953:44;
+2954:4D;
+2955:2A;
+2956:D6;
+2957:78;
+2958:DF;
+2959:60;
+295A:69;
+295B:D8;
+295C:E1;
+295D:E3;
+295E:DF;
+295F:E3;
+2960:E5;
+2961:60;
+2962:69;
+2963:D0;
+2964:C1;
+2965:F1;
+2966:F1;
+2967:E5;
+2968:D5;
+2969:C5;
+296A:C9;
+296B:D1;
+296C:E1;
+296D:7D;
+296E:B4;
+296F:C8;
+2970:2B;
+2971:46;
+2972:2B;
+2973:4E;
+2974:E5;
+2975:2B;
+2976:6E;
+2977:26;
+2978:00;
+2979:09;
+297A:50;
+297B:59;
+297C:2B;
+297D:44;
+297E:4D;
+297F:2A;
+2980:D6;
+2981:78;
+2982:CD;
+2983:58;
+2984:19;
+2985:E1;
+2986:71;
+2987:23;
+2988:70;
+2989:69;
+298A:60;
+298B:2B;
+298C:C3;
+298D:E9;
+298E:28;
+298F:C5;
+2990:E5;
+2991:2A;
+2992:21;
+2993:79;
+2994:E3;
+2995:CD;
+2996:9F;
+2997:24;
+2998:E3;
+2999:CD;
+299A:F4;
+299B:0A;
+299C:7E;
+299D:E5;
+299E:2A;
+299F:21;
+29A0:79;
+29A1:E5;
+29A2:86;
+29A3:1E;
+29A4:1C;
+29A5:DA;
+29A6:A2;
+29A7:19;
+29A8:CD;
+29A9:57;
+29AA:28;
+29AB:D1;
+29AC:CD;
+29AD:DE;
+29AE:29;
+29AF:E3;
+29B0:CD;
+29B1:DD;
+29B2:29;
+29B3:E5;
+29B4:2A;
+29B5:D4;
+29B6:78;
+29B7:EB;
+29B8:CD;
+29B9:C6;
+29BA:29;
+29BB:CD;
+29BC:C6;
+29BD:29;
+29BE:21;
+29BF:49;
+29C0:23;
+29C1:E3;
+29C2:E5;
+29C3:C3;
+29C4:84;
+29C5:28;
+29C6:E1;
+29C7:E3;
+29C8:7E;
+29C9:23;
+29CA:4E;
+29CB:23;
+29CC:46;
+29CD:6F;
+29CE:2C;
+29CF:2D;
+29D0:C8;
+29D1:0A;
+29D2:12;
+29D3:03;
+29D4:13;
+29D5:18;
+29D6:F8;
+29D7:CD;
+29D8:F4;
+29D9:0A;
+29DA:2A;
+29DB:21;
+29DC:79;
+29DD:EB;
+29DE:CD;
+29DF:F5;
+29E0:29;
+29E1:EB;
+29E2:C0;
+29E3:D5;
+29E4:50;
+29E5:59;
+29E6:1B;
+29E7:4E;
+29E8:2A;
+29E9:D6;
+29EA:78;
+29EB:DF;
+29EC:20;
+29ED:05;
+29EE:47;
+29EF:09;
+29F0:22;
+29F1:D6;
+29F2:78;
+29F3:E1;
+29F4:C9;
+29F5:2A;
+29F6:B3;
+29F7:78;
+29F8:2B;
+29F9:46;
+29FA:2B;
+29FB:4E;
+29FC:2B;
+29FD:DF;
+29FE:C0;
+29FF:22;
+2A00:B3;
+2A01:78;
+2A02:C9;
+2A03:01;
+2A04:F8;
+2A05:27;
+2A06:C5;
+2A07:CD;
+2A08:D7;
+2A09:29;
+2A0A:AF;
+2A0B:57;
+2A0C:7E;
+2A0D:B7;
+2A0E:C9;
+2A0F:01;
+2A10:F8;
+2A11:27;
+2A12:C5;
+2A13:CD;
+2A14:07;
+2A15:2A;
+2A16:CA;
+2A17:4A;
+2A18:1E;
+2A19:23;
+2A1A:5E;
+2A1B:23;
+2A1C:56;
+2A1D:1A;
+2A1E:C9;
+2A1F:3E;
+2A20:01;
+2A21:CD;
+2A22:57;
+2A23:28;
+2A24:CD;
+2A25:1F;
+2A26:2B;
+2A27:2A;
+2A28:D4;
+2A29:78;
+2A2A:73;
+2A2B:C1;
+2A2C:C3;
+2A2D:84;
+2A2E:28;
+2A2F:D7;
+2A30:CF;
+2A31:28;
+2A32:CD;
+2A33:1C;
+2A34:2B;
+2A35:D5;
+2A36:CF;
+2A37:2C;
+2A38:CD;
+2A39:37;
+2A3A:23;
+2A3B:CF;
+2A3C:29;
+2A3D:E3;
+2A3E:E5;
+2A3F:E7;
+2A40:28;
+2A41:05;
+2A42:CD;
+2A43:1F;
+2A44:2B;
+2A45:18;
+2A46:03;
+2A47:CD;
+2A48:13;
+2A49:2A;
+2A4A:D1;
+2A4B:F5;
+2A4C:F5;
+2A4D:7B;
+2A4E:CD;
+2A4F:57;
+2A50:28;
+2A51:5F;
+2A52:F1;
+2A53:1C;
+2A54:1D;
+2A55:28;
+2A56:D4;
+2A57:2A;
+2A58:D4;
+2A59:78;
+2A5A:77;
+2A5B:23;
+2A5C:1D;
+2A5D:20;
+2A5E:FB;
+2A5F:18;
+2A60:CA;
+2A61:CD;
+2A62:DF;
+2A63:2A;
+2A64:AF;
+2A65:E3;
+2A66:4F;
+2A67:3E;
+2A68:E5;
+2A69:E5;
+2A6A:7E;
+2A6B:B8;
+2A6C:38;
+2A6D:02;
+2A6E:78;
+2A6F:11;
+2A70:0E;
+2A71:00;
+2A72:C5;
+2A73:CD;
+2A74:BF;
+2A75:28;
+2A76:C1;
+2A77:E1;
+2A78:E5;
+2A79:23;
+2A7A:46;
+2A7B:23;
+2A7C:66;
+2A7D:68;
+2A7E:06;
+2A7F:00;
+2A80:09;
+2A81:44;
+2A82:4D;
+2A83:CD;
+2A84:5A;
+2A85:28;
+2A86:6F;
+2A87:CD;
+2A88:CE;
+2A89:29;
+2A8A:D1;
+2A8B:CD;
+2A8C:DE;
+2A8D:29;
+2A8E:C3;
+2A8F:84;
+2A90:28;
+2A91:CD;
+2A92:DF;
+2A93:2A;
+2A94:D1;
+2A95:D5;
+2A96:1A;
+2A97:90;
+2A98:18;
+2A99:CB;
+2A9A:EB;
+2A9B:7E;
+2A9C:CD;
+2A9D:E2;
+2A9E:2A;
+2A9F:04;
+2AA0:05;
+2AA1:CA;
+2AA2:4A;
+2AA3:1E;
+2AA4:C5;
+2AA5:1E;
+2AA6:FF;
+2AA7:FE;
+2AA8:29;
+2AA9:28;
+2AAA:05;
+2AAB:CF;
+2AAC:2C;
+2AAD:CD;
+2AAE:1C;
+2AAF:2B;
+2AB0:CF;
+2AB1:29;
+2AB2:F1;
+2AB3:E3;
+2AB4:01;
+2AB5:69;
+2AB6:2A;
+2AB7:C5;
+2AB8:3D;
+2AB9:BE;
+2ABA:06;
+2ABB:00;
+2ABC:D0;
+2ABD:4F;
+2ABE:7E;
+2ABF:91;
+2AC0:BB;
+2AC1:47;
+2AC2:D8;
+2AC3:43;
+2AC4:C9;
+2AC5:CD;
+2AC6:07;
+2AC7:2A;
+2AC8:CA;
+2AC9:F8;
+2ACA:27;
+2ACB:5F;
+2ACC:23;
+2ACD:7E;
+2ACE:23;
+2ACF:66;
+2AD0:6F;
+2AD1:E5;
+2AD2:19;
+2AD3:46;
+2AD4:72;
+2AD5:E3;
+2AD6:C5;
+2AD7:7E;
+2AD8:CD;
+2AD9:65;
+2ADA:0E;
+2ADB:C1;
+2ADC:E1;
+2ADD:70;
+2ADE:C9;
+2ADF:EB;
+2AE0:CF;
+2AE1:29;
+2AE2:C1;
+2AE3:D1;
+2AE4:C5;
+2AE5:43;
+2AE6:C9;
+2AE7:FE;
+2AE8:7A;
+2AE9:C2;
+2AEA:97;
+2AEB:19;
+2AEC:C3;
+2AED:D9;
+2AEE:79;
+2AEF:CD;
+2AF0:1F;
+2AF1:2B;
+2AF2:32;
+2AF3:94;
+2AF4:78;
+2AF5:CD;
+2AF6:93;
+2AF7:78;
+2AF8:C3;
+2AF9:F8;
+2AFA:27;
+2AFB:CD;
+2AFC:0E;
+2AFD:2B;
+2AFE:C3;
+2AFF:96;
+2B00:78;
+2B01:D7;
+2B02:CD;
+2B03:37;
+2B04:23;
+2B05:E5;
+2B06:CD;
+2B07:7F;
+2B08:0A;
+2B09:EB;
+2B0A:E1;
+2B0B:7A;
+2B0C:B7;
+2B0D:C9;
+2B0E:CD;
+2B0F:1C;
+2B10:2B;
+2B11:32;
+2B12:94;
+2B13:78;
+2B14:32;
+2B15:97;
+2B16:78;
+2B17:CF;
+2B18:2C;
+2B19:18;
+2B1A:01;
+2B1B:D7;
+2B1C:CD;
+2B1D:37;
+2B1E:23;
+2B1F:CD;
+2B20:05;
+2B21:2B;
+2B22:C2;
+2B23:4A;
+2B24:1E;
+2B25:2B;
+2B26:D7;
+2B27:7B;
+2B28:C9;
+2B29:3E;
+2B2A:01;
+2B2B:32;
+2B2C:9C;
+2B2D:78;
+2B2E:C1;
+2B2F:CD;
+2B30:10;
+2B31:1B;
+2B32:C5;
+2B33:CD;
+2B34:25;
+2B35:3B;
+2B36:22;
+2B37:A2;
+2B38:78;
+2B39:E1;
+2B3A:D1;
+2B3B:4E;
+2B3C:23;
+2B3D:46;
+2B3E:23;
+2B3F:78;
+2B40:B1;
+2B41:CA;
+2B42:19;
+2B43:1A;
+2B44:CD;
+2B45:DF;
+2B46:79;
+2B47:CD;
+2B48:9B;
+2B49:1D;
+2B4A:C5;
+2B4B:4E;
+2B4C:23;
+2B4D:46;
+2B4E:23;
+2B4F:C5;
+2B50:E3;
+2B51:EB;
+2B52:DF;
+2B53:C1;
+2B54:DA;
+2B55:18;
+2B56:1A;
+2B57:E3;
+2B58:E5;
+2B59:C5;
+2B5A:EB;
+2B5B:22;
+2B5C:EC;
+2B5D:78;
+2B5E:CD;
+2B5F:AF;
+2B60:0F;
+2B61:3E;
+2B62:20;
+2B63:E1;
+2B64:CD;
+2B65:2A;
+2B66:03;
+2B67:CD;
+2B68:7E;
+2B69:2B;
+2B6A:2A;
+2B6B:A7;
+2B6C:78;
+2B6D:CD;
+2B6E:75;
+2B6F:2B;
+2B70:CD;
+2B71:FE;
+2B72:20;
+2B73:18;
+2B74:BE;
+2B75:7E;
+2B76:B7;
+2B77:C8;
+2B78:CD;
+2B79:2A;
+2B7A:03;
+2B7B:23;
+2B7C:18;
+2B7D:F7;
+2B7E:E5;
+2B7F:2A;
+2B80:A7;
+2B81:78;
+2B82:44;
+2B83:4D;
+2B84:E1;
+2B85:16;
+2B86:FF;
+2B87:18;
+2B88:03;
+2B89:03;
+2B8A:15;
+2B8B:C8;
+2B8C:7E;
+2B8D:B7;
+2B8E:23;
+2B8F:02;
+2B90:C8;
+2B91:C3;
+2B92:9D;
+2B93:2E;
+2B94:FE;
+2B95:FB;
+2B96:20;
+2B97:08;
+2B98:0B;
+2B99:0B;
+2B9A:0B;
+2B9B:0B;
+2B9C:14;
+2B9D:14;
+2B9E:14;
+2B9F:14;
+2BA0:FE;
+2BA1:95;
+2BA2:CC;
+2BA3:24;
+2BA4:0B;
+2BA5:D6;
+2BA6:7F;
+2BA7:E5;
+2BA8:5F;
+2BA9:21;
+2BAA:50;
+2BAB:16;
+2BAC:7E;
+2BAD:B7;
+2BAE:23;
+2BAF:F2;
+2BB0:AC;
+2BB1:2B;
+2BB2:1D;
+2BB3:20;
+2BB4:F7;
+2BB5:E6;
+2BB6:7F;
+2BB7:02;
+2BB8:03;
+2BB9:15;
+2BBA:CA;
+2BBB:D8;
+2BBC:28;
+2BBD:7E;
+2BBE:23;
+2BBF:B7;
+2BC0:F2;
+2BC1:B7;
+2BC2:2B;
+2BC3:E1;
+2BC4:18;
+2BC5:C6;
+2BC6:CD;
+2BC7:10;
+2BC8:1B;
+2BC9:D1;
+2BCA:C5;
+2BCB:C5;
+2BCC:CD;
+2BCD:2C;
+2BCE:1B;
+2BCF:30;
+2BD0:05;
+2BD1:54;
+2BD2:5D;
+2BD3:E3;
+2BD4:E5;
+2BD5:DF;
+2BD6:D2;
+2BD7:4A;
+2BD8:1E;
+2BD9:21;
+2BDA:29;
+2BDB:19;
+2BDC:CD;
+2BDD:A7;
+2BDE:28;
+2BDF:C1;
+2BE0:21;
+2BE1:E8;
+2BE2:1A;
+2BE3:E3;
+2BE4:EB;
+2BE5:2A;
+2BE6:F9;
+2BE7:78;
+2BE8:1A;
+2BE9:02;
+2BEA:03;
+2BEB:13;
+2BEC:DF;
+2BED:20;
+2BEE:F9;
+2BEF:60;
+2BF0:69;
+2BF1:22;
+2BF2:F9;
+2BF3:78;
+2BF4:C9;
+2BF5:CD;
+2BF6:1C;
+2BF7:2B;
+2BF8:FE;
+2BF9:20;
+2BFA:D2;
+2BFB:4A;
+2BFC:1E;
+2BFD:32;
+2BFE:D2;
+2BFF:7A;
+2C00:CF;
+2C01:2C;
+2C02:CD;
+2C03:1C;
+2C04:2B;
+2C05:B7;
+2C06:CA;
+2C07:4A;
+2C08:1E;
+2C09:FE;
+2C0A:0A;
+2C0B:D2;
+2C0C:4A;
+2C0D:1E;
+2C0E:F3;
+2C0F:E5;
+2C10:3D;
+2C11:F5;
+2C12:3A;
+2C13:D2;
+2C14:7A;
+2C15:B7;
+2C16:28;
+2C17:40;
+2C18:3D;
+2C19:CB;
+2C1A:27;
+2C1B:4F;
+2C1C:AF;
+2C1D:47;
+2C1E:F1;
+2C1F:21;
+2C20:CF;
+2C21:02;
+2C22:09;
+2C23:5E;
+2C24:23;
+2C25:56;
+2C26:D5;
+2C27:21;
+2C28:61;
+2C29:03;
+2C2A:CB;
+2C2B:39;
+2C2C:09;
+2C2D:5E;
+2C2E:16;
+2C2F:00;
+2C30:21;
+2C31:21;
+2C32:03;
+2C33:4F;
+2C34:09;
+2C35:46;
+2C36:D5;
+2C37:E1;
+2C38:19;
+2C39:10;
+2C3A:FD;
+2C3B:E5;
+2C3C:C1;
+2C3D:E1;
+2C3E:CD;
+2C3F:F8;
+2C40:3A;
+2C41:3A;
+2C42:3B;
+2C43:78;
+2C44:57;
+2C45:CD;
+2C46:69;
+2C47:34;
+2C48:0B;
+2C49:79;
+2C4A:B0;
+2C4B:20;
+2C4C:F1;
+2C4D:E1;
+2C4E:FB;
+2C4F:7E;
+2C50:23;
+2C51:FE;
+2C52:3B;
+2C53:CA;
+2C54:F5;
+2C55:2B;
+2C56:2B;
+2C57:C9;
+2C58:F1;
+2C59:4F;
+2C5A:AF;
+2C5B:47;
+2C5C:21;
+2C5D:21;
+2C5E:03;
+2C5F:09;
+2C60:46;
+2C61:21;
+2C62:36;
+2C63:19;
+2C64:E5;
+2C65:D1;
+2C66:19;
+2C67:10;
+2C68:FD;
+2C69:CD;
+2C6A:F8;
+2C6B:3A;
+2C6C:2B;
+2C6D:7D;
+2C6E:B4;
+2C6F:20;
+2C70:F8;
+2C71:18;
+2C72:DA;
+2C73:C5;
+2C74:47;
+2C75:3E;
+2C76:08;
+2C77:CD;
+2C78:BA;
+2C79:3A;
+2C7A:78;
+2C7B:E6;
+2C7C:0F;
+2C7D:E5;
+2C7E:CB;
+2C7F:27;
+2C80:4F;
+2C81:AF;
+2C82:47;
+2C83:21;
+2C84:AF;
+2C85:02;
+2C86:09;
+2C87:7E;
+2C88:47;
+2C89:23;
+2C8A:7E;
+2C8B:4F;
+2C8C:78;
+2C8D:CD;
+2C8E:BA;
+2C8F:3A;
+2C90:CD;
+2C91:BA;
+2C92:3A;
+2C93:CD;
+2C94:BA;
+2C95:3A;
+2C96:79;
+2C97:CD;
+2C98:BA;
+2C99:3A;
+2C9A:CD;
+2C9B:BA;
+2C9C:3A;
+2C9D:CD;
+2C9E:BA;
+2C9F:3A;
+2CA0:E1;
+2CA1:C1;
+2CA2:3E;
+2CA3:0F;
+2CA4:CD;
+2CA5:BA;
+2CA6:3A;
+2CA7:C9;
+2CA8:30;
+2CA9:9D;
+2CAA:CD;
+2CAB:7F;
+2CAC:0A;
+2CAD:7E;
+2CAE:C3;
+2CAF:F8;
+2CB0:27;
+2CB1:CD;
+2CB2:02;
+2CB3:2B;
+2CB4:D5;
+2CB5:CF;
+2CB6:2C;
+2CB7:CD;
+2CB8:1C;
+2CB9:2B;
+2CBA:D1;
+2CBB:12;
+2CBC:C9;
+2CBD:CD;
+2CBE:38;
+2CBF:23;
+2CC0:CD;
+2CC1:F4;
+2CC2:0A;
+2CC3:CF;
+2CC4:3B;
+2CC5:EB;
+2CC6:2A;
+2CC7:21;
+2CC8:79;
+2CC9:18;
+2CCA:08;
+2CCB:3A;
+2CCC:DE;
+2CCD:78;
+2CCE:B7;
+2CCF:28;
+2CD0:0C;
+2CD1:D1;
+2CD2:EB;
+2CD3:E5;
+2CD4:AF;
+2CD5:32;
+2CD6:DE;
+2CD7:78;
+2CD8:BA;
+2CD9:F5;
+2CDA:D5;
+2CDB:46;
+2CDC:B0;
+2CDD:CA;
+2CDE:4A;
+2CDF:1E;
+2CE0:23;
+2CE1:4E;
+2CE2:23;
+2CE3:66;
+2CE4:69;
+2CE5:18;
+2CE6:1C;
+2CE7:58;
+2CE8:E5;
+2CE9:0E;
+2CEA:02;
+2CEB:7E;
+2CEC:23;
+2CED:FE;
+2CEE:25;
+2CEF:CA;
+2CF0:17;
+2CF1:2E;
+2CF2:FE;
+2CF3:20;
+2CF4:20;
+2CF5:03;
+2CF6:0C;
+2CF7:10;
+2CF8:F2;
+2CF9:E1;
+2CFA:43;
+2CFB:3E;
+2CFC:25;
+2CFD:CD;
+2CFE:49;
+2CFF:2E;
+2D00:CD;
+2D01:2A;
+2D02:03;
+2D03:AF;
+2D04:5F;
+2D05:57;
+2D06:CD;
+2D07:49;
+2D08:2E;
+2D09:57;
+2D0A:7E;
+2D0B:23;
+2D0C:FE;
+2D0D:21;
+2D0E:CA;
+2D0F:14;
+2D10:2E;
+2D11:FE;
+2D12:23;
+2D13:28;
+2D14:37;
+2D15:05;
+2D16:CA;
+2D17:FE;
+2D18:2D;
+2D19:FE;
+2D1A:2B;
+2D1B:3E;
+2D1C:08;
+2D1D:28;
+2D1E:E7;
+2D1F:2B;
+2D20:7E;
+2D21:23;
+2D22:FE;
+2D23:2E;
+2D24:28;
+2D25:40;
+2D26:FE;
+2D27:25;
+2D28:28;
+2D29:BD;
+2D2A:BE;
+2D2B:20;
+2D2C:D0;
+2D2D:FE;
+2D2E:24;
+2D2F:28;
+2D30:14;
+2D31:FE;
+2D32:2A;
+2D33:20;
+2D34:C8;
+2D35:78;
+2D36:FE;
+2D37:02;
+2D38:23;
+2D39:38;
+2D3A:03;
+2D3B:7E;
+2D3C:FE;
+2D3D:24;
+2D3E:3E;
+2D3F:20;
+2D40:20;
+2D41:07;
+2D42:05;
+2D43:1C;
+2D44:FE;
+2D45:AF;
+2D46:C6;
+2D47:10;
+2D48:23;
+2D49:1C;
+2D4A:82;
+2D4B:57;
+2D4C:1C;
+2D4D:0E;
+2D4E:00;
+2D4F:05;
+2D50:28;
+2D51:47;
+2D52:7E;
+2D53:23;
+2D54:FE;
+2D55:2E;
+2D56:28;
+2D57:18;
+2D58:FE;
+2D59:23;
+2D5A:28;
+2D5B:F0;
+2D5C:FE;
+2D5D:2C;
+2D5E:20;
+2D5F:1A;
+2D60:7A;
+2D61:F6;
+2D62:40;
+2D63:57;
+2D64:18;
+2D65:E6;
+2D66:7E;
+2D67:FE;
+2D68:23;
+2D69:3E;
+2D6A:2E;
+2D6B:20;
+2D6C:90;
+2D6D:0E;
+2D6E:01;
+2D6F:23;
+2D70:0C;
+2D71:05;
+2D72:28;
+2D73:25;
+2D74:7E;
+2D75:23;
+2D76:FE;
+2D77:23;
+2D78:28;
+2D79:F6;
+2D7A:D5;
+2D7B:11;
+2D7C:97;
+2D7D:2D;
+2D7E:D5;
+2D7F:54;
+2D80:5D;
+2D81:FE;
+2D82:5B;
+2D83:C0;
+2D84:BE;
+2D85:C0;
+2D86:23;
+2D87:BE;
+2D88:C0;
+2D89:23;
+2D8A:BE;
+2D8B:C0;
+2D8C:23;
+2D8D:78;
+2D8E:D6;
+2D8F:04;
+2D90:D8;
+2D91:D1;
+2D92:D1;
+2D93:47;
+2D94:14;
+2D95:23;
+2D96:CA;
+2D97:EB;
+2D98:D1;
+2D99:7A;
+2D9A:2B;
+2D9B:1C;
+2D9C:E6;
+2D9D:08;
+2D9E:20;
+2D9F:15;
+2DA0:1D;
+2DA1:78;
+2DA2:B7;
+2DA3:28;
+2DA4:10;
+2DA5:7E;
+2DA6:D6;
+2DA7:2D;
+2DA8:28;
+2DA9:06;
+2DAA:FE;
+2DAB:FE;
+2DAC:20;
+2DAD:07;
+2DAE:3E;
+2DAF:08;
+2DB0:C6;
+2DB1:04;
+2DB2:82;
+2DB3:57;
+2DB4:05;
+2DB5:E1;
+2DB6:F1;
+2DB7:28;
+2DB8:50;
+2DB9:C5;
+2DBA:D5;
+2DBB:CD;
+2DBC:37;
+2DBD:23;
+2DBE:D1;
+2DBF:C1;
+2DC0:C5;
+2DC1:E5;
+2DC2:43;
+2DC3:78;
+2DC4:81;
+2DC5:FE;
+2DC6:19;
+2DC7:D2;
+2DC8:4A;
+2DC9:1E;
+2DCA:7A;
+2DCB:F6;
+2DCC:80;
+2DCD:CD;
+2DCE:BE;
+2DCF:0F;
+2DD0:CD;
+2DD1:A7;
+2DD2:28;
+2DD3:E1;
+2DD4:2B;
+2DD5:D7;
+2DD6:37;
+2DD7:28;
+2DD8:0D;
+2DD9:32;
+2DDA:DE;
+2DDB:78;
+2DDC:FE;
+2DDD:3B;
+2DDE:28;
+2DDF:05;
+2DE0:FE;
+2DE1:2C;
+2DE2:C2;
+2DE3:97;
+2DE4:19;
+2DE5:D7;
+2DE6:C1;
+2DE7:EB;
+2DE8:E1;
+2DE9:E5;
+2DEA:F5;
+2DEB:D5;
+2DEC:7E;
+2DED:90;
+2DEE:23;
+2DEF:4E;
+2DF0:23;
+2DF1:66;
+2DF2:69;
+2DF3:16;
+2DF4:00;
+2DF5:5F;
+2DF6:19;
+2DF7:78;
+2DF8:B7;
+2DF9:C2;
+2DFA:03;
+2DFB:2D;
+2DFC:18;
+2DFD:06;
+2DFE:CD;
+2DFF:49;
+2E00:2E;
+2E01:CD;
+2E02:2A;
+2E03:03;
+2E04:E1;
+2E05:F1;
+2E06:C2;
+2E07:CB;
+2E08:2C;
+2E09:DC;
+2E0A:FE;
+2E0B:20;
+2E0C:E3;
+2E0D:CD;
+2E0E:DD;
+2E0F:29;
+2E10:E1;
+2E11:C3;
+2E12:69;
+2E13:21;
+2E14:0E;
+2E15:01;
+2E16:3E;
+2E17:F1;
+2E18:05;
+2E19:CD;
+2E1A:49;
+2E1B:2E;
+2E1C:E1;
+2E1D:F1;
+2E1E:28;
+2E1F:E9;
+2E20:C5;
+2E21:CD;
+2E22:37;
+2E23:23;
+2E24:CD;
+2E25:F4;
+2E26:0A;
+2E27:C1;
+2E28:C5;
+2E29:E5;
+2E2A:2A;
+2E2B:21;
+2E2C:79;
+2E2D:41;
+2E2E:0E;
+2E2F:00;
+2E30:C5;
+2E31:CD;
+2E32:68;
+2E33:2A;
+2E34:CD;
+2E35:AA;
+2E36:28;
+2E37:2A;
+2E38:21;
+2E39:79;
+2E3A:F1;
+2E3B:96;
+2E3C:47;
+2E3D:3E;
+2E3E:20;
+2E3F:04;
+2E40:05;
+2E41:CA;
+2E42:D3;
+2E43:2D;
+2E44:CD;
+2E45:2A;
+2E46:03;
+2E47:18;
+2E48:F7;
+2E49:F5;
+2E4A:7A;
+2E4B:B7;
+2E4C:3E;
+2E4D:2B;
+2E4E:C4;
+2E4F:2A;
+2E50:03;
+2E51:F1;
+2E52:C9;
+2E53:60;
+2E54:69;
+2E55:23;
+2E56:23;
+2E57:23;
+2E58:23;
+2E59:CD;
+2E5A:7E;
+2E5B:2B;
+2E5C:2A;
+2E5D:A7;
+2E5E:78;
+2E5F:CD;
+2E60:75;
+2E61:2B;
+2E62:C9;
+2E63:CF;
+2E64:28;
+2E65:CD;
+2E66:1C;
+2E67:2B;
+2E68:B7;
+2E69:28;
+2E6A:12;
+2E6B:3D;
+2E6C:28;
+2E6D:03;
+2E6E:C3;
+2E6F:4A;
+2E70:1E;
+2E71:16;
+2E72:00;
+2E73:3A;
+2E74:3B;
+2E75:78;
+2E76:F6;
+2E77:08;
+2E78:32;
+2E79:3B;
+2E7A:78;
+2E7B:18;
+2E7C:0A;
+2E7D:16;
+2E7E:20;
+2E7F:3A;
+2E80:3B;
+2E81:78;
+2E82:E6;
+2E83:F7;
+2E84:32;
+2E85:3B;
+2E86:78;
+2E87:32;
+2E88:00;
+2E89:68;
+2E8A:E5;
+2E8B:21;
+2E8C:00;
+2E8D:70;
+2E8E:01;
+2E8F:00;
+2E90:08;
+2E91:7A;
+2E92:77;
+2E93:23;
+2E94:0B;
+2E95:78;
+2E96:B1;
+2E97:20;
+2E98:F8;
+2E99:E1;
+2E9A:CF;
+2E9B:29;
+2E9C:C9;
+2E9D:FE;
+2E9E:22;
+2E9F:CA;
+2EA0:B3;
+2EA1:2E;
+2EA2:B7;
+2EA3:F2;
+2EA4:89;
+2EA5:2B;
+2EA6:C3;
+2EA7:94;
+2EA8:2B;
+2EA9:7E;
+2EAA:B7;
+2EAB:23;
+2EAC:02;
+2EAD:C8;
+2EAE:FE;
+2EAF:22;
+2EB0:CA;
+2EB1:89;
+2EB2:2B;
+2EB3:03;
+2EB4:15;
+2EB5:C8;
+2EB6:18;
+2EB7:F1;
+2EB8:F5;
+2EB9:C5;
+2EBA:D5;
+2EBB:E5;
+2EBC:CD;
+2EBD:7D;
+2EBE:78;
+2EBF:CD;
+2EC0:7B;
+2EC1:3F;
+2EC2:CD;
+2EC3:DC;
+2EC4:2E;
+2EC5:CD;
+2EC6:FD;
+2EC7:2E;
+2EC8:F5;
+2EC9:21;
+2ECA:39;
+2ECB:78;
+2ECC:CB;
+2ECD:46;
+2ECE:CC;
+2ECF:1B;
+2ED0:30;
+2ED1:F1;
+2ED2:CD;
+2ED3:30;
+2ED4:34;
+2ED5:E1;
+2ED6:D1;
+2ED7:C1;
+2ED8:F1;
+2ED9:FB;
+2EDA:ED;
+2EDB:4D;
+2EDC:3A;
+2EDD:39;
+2EDE:78;
+2EDF:CB;
+2EE0:47;
+2EE1:C0;
+2EE2:21;
+2EE3:41;
+2EE4:78;
+2EE5:35;
+2EE6:C0;
+2EE7:3E;
+2EE8:10;
+2EE9:32;
+2EEA:41;
+2EEB:78;
+2EEC:2A;
+2EED:20;
+2EEE:78;
+2EEF:3E;
+2EF0:40;
+2EF1:AE;
+2EF2:77;
+2EF3:C9;
+2EF4:CD;
+2EF5:FD;
+2EF6:2E;
+2EF7:F5;
+2EF8:CD;
+2EF9:0E;
+2EFA:2F;
+2EFB:F1;
+2EFC:C9;
+2EFD:3A;
+2EFE:00;
+2EFF:68;
+2F00:F6;
+2F01:C0;
+2F02:2F;
+2F03:FE;
+2F04:00;
+2F05:28;
+2F06:07;
+2F07:CD;
+2F08:28;
+2F09:2F;
+2F0A:B7;
+2F0B:C2;
+2F0C:D7;
+2F0D:05;
+2F0E:21;
+2F0F:38;
+2F10:78;
+2F11:CB;
+2F12:56;
+2F13:28;
+2F14:08;
+2F15:3A;
+2F16:3A;
+2F17:78;
+2F18:B7;
+2F19:28;
+2F1A:02;
+2F1B:CB;
+2F1C:96;
+2F1D:7E;
+2F1E:E6;
+2F1F:06;
+2F20:32;
+2F21:38;
+2F22:78;
+2F23:AF;
+2F24:32;
+2F25:36;
+2F26:78;
+2F27:C9;
+2F28:21;
+2F29:FE;
+2F2A:68;
+2F2B:0E;
+2F2C:08;
+2F2D:06;
+2F2E:06;
+2F2F:7E;
+2F30:F6;
+2F31:04;
+2F32:1F;
+2F33:30;
+2F34:2D;
+2F35:10;
+2F36:FB;
+2F37:CB;
+2F38:05;
+2F39:0D;
+2F3A:20;
+2F3B:F1;
+2F3C:06;
+2F3D:04;
+2F3E:21;
+2F3F:DF;
+2F40:68;
+2F41:7E;
+2F42:CB;
+2F43:57;
+2F44:28;
+2F45:10;
+2F46:CB;
+2F47:05;
+2F48:7E;
+2F49:CB;
+2F4A:57;
+2F4B:28;
+2F4C:0D;
+2F4D:CB;
+2F4E:05;
+2F4F:7E;
+2F50:CB;
+2F51:57;
+2F52:28;
+2F53:0A;
+2F54:AF;
+2F55:C9;
+2F56:0E;
+2F57:03;
+2F58:18;
+2F59:06;
+2F5A:0E;
+2F5B:02;
+2F5C:18;
+2F5D:02;
+2F5E:0E;
+2F5F:01;
+2F60:F6;
+2F61:04;
+2F62:5F;
+2F63:3E;
+2F64:06;
+2F65:90;
+2F66:CB;
+2F67:27;
+2F68:CB;
+2F69:27;
+2F6A:CB;
+2F6B:27;
+2F6C:C6;
+2F6D:08;
+2F6E:91;
+2F6F:ED;
+2F70:43;
+2F71:42;
+2F72:78;
+2F73:22;
+2F74:44;
+2F75:78;
+2F76:21;
+2F77:D9;
+2F78:01;
+2F79:4F;
+2F7A:06;
+2F7B:00;
+2F7C:3A;
+2F7D:FB;
+2F7E:68;
+2F7F:CB;
+2F80:57;
+2F81:20;
+2F82:0A;
+2F83:21;
+2F84:38;
+2F85:78;
+2F86:CB;
+2F87:C6;
+2F88:21;
+2F89:09;
+2F8A:02;
+2F8B:18;
+2F8C:3D;
+2F8D:3A;
+2F8E:FD;
+2F8F:68;
+2F90:CB;
+2F91:57;
+2F92:20;
+2F93:39;
+2F94:3A;
+2F95:7F;
+2F96:68;
+2F97:CB;
+2F98:57;
+2F99:20;
+2F9A:0E;
+2F9B:21;
+2F9C:38;
+2F9D:78;
+2F9E:CB;
+2F9F:6E;
+2FA0:20;
+2FA1:04;
+2FA2:7E;
+2FA3:EE;
+2FA4:22;
+2FA5:77;
+2FA6:AF;
+2FA7:C1;
+2FA8:C9;
+2FA9:21;
+2FAA:38;
+2FAB:78;
+2FAC:CB;
+2FAD:FE;
+2FAE:CB;
+2FAF:56;
+2FB0:28;
+2FB1:05;
+2FB2:21;
+2FB3:69;
+2FB4:02;
+2FB5:18;
+2FB6:13;
+2FB7:3A;
+2FB8:BF;
+2FB9:68;
+2FBA:CB;
+2FBB:57;
+2FBC:20;
+2FBD:07;
+2FBE:CB;
+2FBF:D6;
+2FC0:AF;
+2FC1:32;
+2FC2:3A;
+2FC3:78;
+2FC4:C9;
+2FC5:CB;
+2FC6:96;
+2FC7:21;
+2FC8:39;
+2FC9:02;
+2FCA:09;
+2FCB:7E;
+2FCC:C9;
+2FCD:3A;
+2FCE:38;
+2FCF:78;
+2FD0:E6;
+2FD1:81;
+2FD2:28;
+2FD3:F6;
+2FD4:AF;
+2FD5:E1;
+2FD6:C9;
+2FD7:21;
+2FD8:38;
+2FD9:78;
+2FDA:CB;
+2FDB:6E;
+2FDC:28;
+2FDD:25;
+2FDE:3A;
+2FDF:3A;
+2FE0:78;
+2FE1:3C;
+2FE2:32;
+2FE3:3A;
+2FE4:78;
+2FE5:FE;
+2FE6:2A;
+2FE7:28;
+2FE8:02;
+2FE9:AF;
+2FEA:C9;
+2FEB:7E;
+2FEC:E6;
+2FED:DF;
+2FEE:F6;
+2FEF:40;
+2FF0:32;
+2FF1:38;
+2FF2:78;
+2FF3:AF;
+2FF4:32;
+2FF5:3A;
+2FF6:78;
+2FF7:CB;
+2FF8:66;
+2FF9:20;
+2FFA:04;
+2FFB:3A;
+2FFC:36;
+2FFD:78;
+2FFE:C9;
+2FFF:3A;
+3000:37;
+3001:78;
+3002:C9;
+3003:CB;
+3004:76;
+3005:20;
+3006:07;
+3007:CB;
+3008:EE;
+3009:AF;
+300A:32;
+300B:3A;
+300C:78;
+300D:C9;
+300E:3A;
+300F:3A;
+3010:78;
+3011:3C;
+3012:32;
+3013:3A;
+3014:78;
+3015:FE;
+3016:06;
+3017:28;
+3018:DA;
+3019:AF;
+301A:C9;
+301B:B7;
+301C:C8;
+301D:F5;
+301E:CD;
+301F:39;
+3020:30;
+3021:F1;
+3022:FE;
+3023:0D;
+3024:C8;
+3025:FE;
+3026:01;
+3027:C8;
+3028:3A;
+3029:39;
+302A:78;
+302B:CB;
+302C:47;
+302D:C0;
+302E:3E;
+302F:20;
+3030:32;
+3031:41;
+3032:78;
+3033:2A;
+3034:20;
+3035:78;
+3036:C3;
+3037:B2;
+3038:3E;
+3039:21;
+303A:38;
+303B:78;
+303C:CB;
+303D:7E;
+303E:CA;
+303F:57;
+3040:31;
+3041:B7;
+3042:F2;
+3043:57;
+3044:31;
+3045:F5;
+3046:D6;
+3047:80;
+3048:3C;
+3049:47;
+304A:21;
+304B:4F;
+304C:16;
+304D:23;
+304E:CB;
+304F:7E;
+3050:28;
+3051:FB;
+3052:10;
+3053:F9;
+3054:7E;
+3055:CD;
+3056:82;
+3057:30;
+3058:7E;
+3059:CB;
+305A:7F;
+305B:28;
+305C:F8;
+305D:F1;
+305E:06;
+305F:16;
+3060:21;
+3061:99;
+3062:02;
+3063:BE;
+3064:28;
+3065:16;
+3066:23;
+3067:10;
+3068:FA;
+3069:FE;
+306A:B0;
+306B:C0;
+306C:3E;
+306D:20;
+306E:CD;
+306F:82;
+3070:30;
+3071:3E;
+3072:46;
+3073:CD;
+3074:82;
+3075:30;
+3076:3E;
+3077:4E;
+3078:CD;
+3079:82;
+307A:30;
+307B:C9;
+307C:3E;
+307D:28;
+307E:CD;
+307F:82;
+3080:30;
+3081:C9;
+3082:E6;
+3083:7F;
+3084:E5;
+3085:CD;
+3086:57;
+3087:31;
+3088:E1;
+3089:23;
+308A:C9;
+308B:F5;
+308C:3A;
+308D:3B;
+308E:78;
+308F:CB;
+3090:5F;
+3091:28;
+3092:17;
+3093:E6;
+3094:F7;
+3095:32;
+3096:3B;
+3097:78;
+3098:32;
+3099:00;
+309A:68;
+309B:01;
+309C:00;
+309D:02;
+309E:21;
+309F:00;
+30A0:70;
+30A1:CD;
+30A2:BE;
+30A3:3E;
+30A4:23;
+30A5:0B;
+30A6:79;
+30A7:B0;
+30A8:20;
+30A9:F7;
+30AA:F1;
+30AB:21;
+30AC:39;
+30AD:78;
+30AE:CB;
+30AF:6E;
+30B0:CA;
+30B1:06;
+30B2:31;
+30B3:FE;
+30B4:20;
+30B5:D2;
+30B6:C0;
+30B7:30;
+30B8:F5;
+30B9:3A;
+30BA:AF;
+30BB:7A;
+30BC:B7;
+30BD:20;
+30BE:FA;
+30BF:F1;
+30C0:F3;
+30C1:2A;
+30C2:B0;
+30C3:7A;
+30C4:77;
+30C5:23;
+30C6:22;
+30C7:B0;
+30C8:7A;
+30C9:21;
+30CA:AF;
+30CB:7A;
+30CC:34;
+30CD:F5;
+30CE:3A;
+30CF:A6;
+30D0:78;
+30D1:86;
+30D2:32;
+30D3:AE;
+30D4:7A;
+30D5:F1;
+30D6:FB;
+30D7:FE;
+30D8:20;
+30D9:DA;
+30DA:E3;
+30DB:30;
+30DC:3E;
+30DD:14;
+30DE:BE;
+30DF:DA;
+30E0:DE;
+30E1:30;
+30E2:C9;
+30E3:AF;
+30E4:BE;
+30E5:20;
+30E6:FD;
+30E7:C9;
+30E8:3A;
+30E9:AF;
+30EA:7A;
+30EB:B7;
+30EC:C8;
+30ED:47;
+30EE:21;
+30EF:B2;
+30F0:7A;
+30F1:E5;
+30F2:7E;
+30F3:23;
+30F4:E5;
+30F5:C5;
+30F6:CD;
+30F7:06;
+30F8:31;
+30F9:C1;
+30FA:E1;
+30FB:10;
+30FC:F5;
+30FD:E1;
+30FE:22;
+30FF:B0;
+3100:7A;
+3101:AF;
+3102:32;
+3103:AF;
+3104:7A;
+3105:C9;
+3106:CD;
+3107:0D;
+3108:03;
+3109:B7;
+310A:28;
+310B:04;
+310C:FE;
+310D:0D;
+310E:20;
+310F:4A;
+3110:F5;
+3111:2A;
+3112:20;
+3113:78;
+3114:3A;
+3115:A6;
+3116:78;
+3117:4F;
+3118:AF;
+3119:47;
+311A:32;
+311B:A6;
+311C:78;
+311D:ED;
+311E:42;
+311F:01;
+3120:20;
+3121:00;
+3122:09;
+3123:7C;
+3124:FE;
+3125:72;
+3126:F4;
+3127:F3;
+3128:33;
+3129:22;
+312A:20;
+312B:78;
+312C:CD;
+312D:53;
+312E:00;
+312F:F1;
+3130:B7;
+3131:C8;
+3132:CD;
+3133:A8;
+3134:33;
+3135:FE;
+3136:80;
+3137:C8;
+3138:FE;
+3139:81;
+313A:20;
+313B:05;
+313C:3D;
+313D:77;
+313E:23;
+313F:77;
+3140:C9;
+3141:3E;
+3142:80;
+3143:77;
+3144:C9;
+3145:CB;
+3146:77;
+3147:28;
+3148:04;
+3149:C3;
+314A:60;
+314B:3F;
+314C:00;
+314D:E6;
+314E:8F;
+314F:47;
+3150:3A;
+3151:46;
+3152:78;
+3153:B0;
+3154:47;
+3155:18;
+3156:5F;
+3157:CD;
+3158:0D;
+3159:03;
+315A:B7;
+315B:FA;
+315C:45;
+315D:31;
+315E:FE;
+315F:0D;
+3160:C8;
+3161:FE;
+3162:08;
+3163:CA;
+3164:27;
+3165:32;
+3166:FE;
+3167:1B;
+3168:CA;
+3169:53;
+316A:32;
+316B:FE;
+316C:0A;
+316D:CA;
+316E:6D;
+316F:32;
+3170:FE;
+3171:08;
+3172:CA;
+3173:27;
+3174:32;
+3175:FE;
+3176:09;
+3177:CA;
+3178:B8;
+3179:31;
+317A:FE;
+317B:01;
+317C:C8;
+317D:FE;
+317E:7F;
+317F:CA;
+3180:CB;
+3181:33;
+3182:FE;
+3183:15;
+3184:CA;
+3185:C6;
+3186:32;
+3187:FE;
+3188:18;
+3189:CA;
+318A:27;
+318B:32;
+318C:FE;
+318D:19;
+318E:CA;
+318F:B8;
+3190:31;
+3191:FE;
+3192:1B;
+3193:CA;
+3194:53;
+3195:32;
+3196:FE;
+3197:1C;
+3198:CA;
+3199:87;
+319A:32;
+319B:FE;
+319C:1D;
+319D:CA;
+319E:B4;
+319F:32;
+31A0:FE;
+31A1:1F;
+31A2:CA;
+31A3:92;
+31A4:32;
+31A5:FE;
+31A6:20;
+31A7:F8;
+31A8:C3;
+31A9:CA;
+31AA:3E;
+31AB:21;
+31AC:38;
+31AD:78;
+31AE:CB;
+31AF:4E;
+31B0:E1;
+31B1:28;
+31B2:02;
+31B3:F6;
+31B4:40;
+31B5:47;
+31B6:78;
+31B7:77;
+31B8:CD;
+31B9:BF;
+31BA:31;
+31BB:CD;
+31BC:50;
+31BD:00;
+31BE:C9;
+31BF:3A;
+31C0:A6;
+31C1:78;
+31C2:3C;
+31C3:FE;
+31C4:20;
+31C5:20;
+31C6:2B;
+31C7:CD;
+31C8:A8;
+31C9:33;
+31CA:FE;
+31CB:81;
+31CC:28;
+31CD:23;
+31CE:B7;
+31CF:20;
+31D0:35;
+31D1:47;
+31D2:3A;
+31D3:39;
+31D4:78;
+31D5:CB;
+31D6:47;
+31D7:78;
+31D8:C8;
+31D9:AF;
+31DA:23;
+31DB:77;
+31DC:23;
+31DD:E5;
+31DE:ED;
+31DF:4B;
+31E0:A4;
+31E1:78;
+31E2:0B;
+31E3:0B;
+31E4:B7;
+31E5:ED;
+31E6:42;
+31E7:E1;
+31E8:30;
+31E9:07;
+31EA:7E;
+31EB:B7;
+31EC:20;
+31ED:03;
+31EE:3E;
+31EF:80;
+31F0:77;
+31F1:AF;
+31F2:32;
+31F3:A6;
+31F4:78;
+31F5:2A;
+31F6:20;
+31F7:78;
+31F8:01;
+31F9:01;
+31FA:00;
+31FB:09;
+31FC:7C;
+31FD:FE;
+31FE:72;
+31FF:F4;
+3200:F3;
+3201:33;
+3202:22;
+3203:20;
+3204:78;
+3205:C9;
+3206:F5;
+3207:ED;
+3208:5B;
+3209:20;
+320A:78;
+320B:13;
+320C:7A;
+320D:FE;
+320E:72;
+320F:28;
+3210:10;
+3211:E5;
+3212:21;
+3213:39;
+3214:78;
+3215:CB;
+3216:46;
+3217:20;
+3218:07;
+3219:CB;
+321A:66;
+321B:20;
+321C:03;
+321D:CD;
+321E:2C;
+321F:33;
+3220:E1;
+3221:F1;
+3222:3C;
+3223:77;
+3224:C3;
+3225:D9;
+3226:31;
+3227:3A;
+3228:A6;
+3229:78;
+322A:3D;
+322B:F2;
+322C:35;
+322D:32;
+322E:CD;
+322F:A8;
+3230:33;
+3231:B7;
+3232:C0;
+3233:3E;
+3234:1F;
+3235:32;
+3236:A6;
+3237:78;
+3238:01;
+3239:01;
+323A:00;
+323B:2A;
+323C:20;
+323D:78;
+323E:AF;
+323F:ED;
+3240:42;
+3241:7C;
+3242:FE;
+3243:70;
+3244:DA;
+3245:4E;
+3246:32;
+3247:22;
+3248:20;
+3249:78;
+324A:CD;
+324B:53;
+324C:00;
+324D:C9;
+324E:AF;
+324F:32;
+3250:A6;
+3251:78;
+3252:C9;
+3253:21;
+3254:39;
+3255:78;
+3256:CB;
+3257:66;
+3258:C0;
+3259:01;
+325A:20;
+325B:00;
+325C:2A;
+325D:20;
+325E:78;
+325F:AF;
+3260:ED;
+3261:42;
+3262:7C;
+3263:FE;
+3264:70;
+3265:F8;
+3266:22;
+3267:20;
+3268:78;
+3269:CD;
+326A:53;
+326B:00;
+326C:C9;
+326D:21;
+326E:39;
+326F:78;
+3270:CB;
+3271:66;
+3272:C0;
+3273:01;
+3274:20;
+3275:00;
+3276:2A;
+3277:20;
+3278:78;
+3279:09;
+327A:7C;
+327B:FE;
+327C:72;
+327D:F4;
+327E:24;
+327F:34;
+3280:22;
+3281:20;
+3282:78;
+3283:CD;
+3284:53;
+3285:00;
+3286:C9;
+3287:21;
+3288:00;
+3289:70;
+328A:22;
+328B:20;
+328C:78;
+328D:AF;
+328E:32;
+328F:A6;
+3290:78;
+3291:C9;
+3292:21;
+3293:00;
+3294:70;
+3295:22;
+3296:20;
+3297:78;
+3298:01;
+3299:00;
+329A:02;
+329B:CD;
+329C:BE;
+329D:3E;
+329E:23;
+329F:0B;
+32A0:79;
+32A1:B0;
+32A2:20;
+32A3:F7;
+32A4:AF;
+32A5:32;
+32A6:A6;
+32A7:78;
+32A8:06;
+32A9:10;
+32AA:3E;
+32AB:80;
+32AC:21;
+32AD:D7;
+32AE:7A;
+32AF:77;
+32B0:23;
+32B1:10;
+32B2:FC;
+32B3:C9;
+32B4:2A;
+32B5:20;
+32B6:78;
+32B7:3A;
+32B8:A6;
+32B9:78;
+32BA:4F;
+32BB:AF;
+32BC:47;
+32BD:32;
+32BE:A6;
+32BF:78;
+32C0:ED;
+32C1:42;
+32C2:22;
+32C3:20;
+32C4:78;
+32C5:C9;
+32C6:CD;
+32C7:A8;
+32C8:33;
+32C9:FE;
+32CA:81;
+32CB:28;
+32CC:31;
+32CD:3A;
+32CE:A6;
+32CF:78;
+32D0:FE;
+32D1:1F;
+32D2:28;
+32D3:25;
+32D4:4F;
+32D5:AF;
+32D6:47;
+32D7:2A;
+32D8:20;
+32D9:78;
+32DA:ED;
+32DB:42;
+32DC:01;
+32DD:1F;
+32DE:00;
+32DF:09;
+32E0:CD;
+32E1:E9;
+32E2:3E;
+32E3:20;
+32E4:14;
+32E5:E5;
+32E6:D1;
+32E7:2B;
+32E8:3A;
+32E9:A6;
+32EA:78;
+32EB:4F;
+32EC:3E;
+32ED:1F;
+32EE:91;
+32EF:4F;
+32F0:ED;
+32F1:B8;
+32F2:CD;
+32F3:F6;
+32F4:3E;
+32F5:32;
+32F6:3C;
+32F7:78;
+32F8:C9;
+32F9:CD;
+32FA:A8;
+32FB:33;
+32FC:B7;
+32FD:C8;
+32FE:FE;
+32FF:80;
+3300:28;
+3301:1E;
+3302:3A;
+3303:A6;
+3304:78;
+3305:4F;
+3306:AF;
+3307:47;
+3308:2A;
+3309:20;
+330A:78;
+330B:ED;
+330C:42;
+330D:01;
+330E:3F;
+330F:00;
+3310:09;
+3311:CD;
+3312:E9;
+3313:3E;
+3314:C0;
+3315:E5;
+3316:D1;
+3317:2B;
+3318:3A;
+3319:A6;
+331A:78;
+331B:4F;
+331C:3E;
+331D:3F;
+331E:18;
+331F:CE;
+3320:E5;
+3321:CD;
+3322:2C;
+3323:33;
+3324:E1;
+3325:3E;
+3326:81;
+3327:77;
+3328:23;
+3329:AF;
+332A:77;
+332B:C9;
+332C:2A;
+332D:20;
+332E:78;
+332F:7C;
+3330:FE;
+3331:71;
+3332:20;
+3333:2B;
+3334:7D;
+3335:FE;
+3336:E0;
+3337:DA;
+3338:5F;
+3339:33;
+333A:3A;
+333B:A6;
+333C:78;
+333D:F5;
+333E:3A;
+333F:D7;
+3340:7A;
+3341:FE;
+3342:81;
+3343:20;
+3344:08;
+3345:E5;
+3346:CD;
+3347:F3;
+3348:33;
+3349:E1;
+334A:CD;
+334B:17;
+334C:03;
+334D:E5;
+334E:CD;
+334F:F3;
+3350:33;
+3351:E1;
+3352:CD;
+3353:17;
+3354:03;
+3355:F1;
+3356:32;
+3357:A6;
+3358:78;
+3359:D1;
+335A:E1;
+335B:2B;
+335C:E5;
+335D:D5;
+335E:C9;
+335F:3A;
+3360:A6;
+3361:78;
+3362:4F;
+3363:AF;
+3364:47;
+3365:ED;
+3366:42;
+3367:01;
+3368:40;
+3369:00;
+336A:09;
+336B:E5;
+336C:EB;
+336D:21;
+336E:00;
+336F:72;
+3370:ED;
+3371:52;
+3372:E5;
+3373:C1;
+3374:21;
+3375:DF;
+3376:71;
+3377:11;
+3378:FF;
+3379:71;
+337A:79;
+337B:B0;
+337C:28;
+337D:02;
+337E:ED;
+337F:B8;
+3380:E1;
+3381:CD;
+3382:02;
+3383:3F;
+3384:00;
+3385:12;
+3386:1B;
+3387:10;
+3388:FC;
+3389:CD;
+338A:A8;
+338B:33;
+338C:E5;
+338D:C1;
+338E:21;
+338F:E6;
+3390:7A;
+3391:E5;
+3392:B7;
+3393:ED;
+3394:42;
+3395:E5;
+3396:C1;
+3397:E1;
+3398:E5;
+3399:D1;
+339A:2B;
+339B:ED;
+339C:B8;
+339D:3A;
+339E:E6;
+339F:7A;
+33A0:FE;
+33A1:81;
+33A2:C0;
+33A3:2A;
+33A4:20;
+33A5:78;
+33A6:18;
+33A7:B7;
+33A8:3A;
+33A9:A6;
+33AA:78;
+33AB:4F;
+33AC:AF;
+33AD:47;
+33AE:2A;
+33AF:20;
+33B0:78;
+33B1:ED;
+33B2:42;
+33B3:E5;
+33B4:C1;
+33B5:78;
+33B6:E6;
+33B7:0F;
+33B8:CB;
+33B9:3F;
+33BA:47;
+33BB:CB;
+33BC:19;
+33BD:CB;
+33BE:39;
+33BF:CB;
+33C0:39;
+33C1:CB;
+33C2:39;
+33C3:CB;
+33C4:39;
+33C5:21;
+33C6:D7;
+33C7:7A;
+33C8:09;
+33C9:7E;
+33CA:C9;
+33CB:CD;
+33CC:A8;
+33CD:33;
+33CE:FE;
+33CF:81;
+33D0:2A;
+33D1:20;
+33D2:78;
+33D3:E5;
+33D4:D1;
+33D5:23;
+33D6:3A;
+33D7:A6;
+33D8:78;
+33D9:4F;
+33DA:28;
+33DB:13;
+33DC:FE;
+33DD:1F;
+33DE:28;
+33DF:08;
+33E0:3E;
+33E1:1F;
+33E2:91;
+33E3:4F;
+33E4:AF;
+33E5:47;
+33E6:ED;
+33E7:B0;
+33E8:CD;
+33E9:F6;
+33EA:3E;
+33EB:CD;
+33EC:50;
+33ED:00;
+33EE:C9;
+33EF:3E;
+33F0:3F;
+33F1:18;
+33F2:EF;
+33F3:11;
+33F4:00;
+33F5:70;
+33F6:21;
+33F7:20;
+33F8:70;
+33F9:01;
+33FA:E0;
+33FB:01;
+33FC:ED;
+33FD:B0;
+33FE:CD;
+33FF:02;
+3400:3F;
+3401:00;
+3402:12;
+3403:13;
+3404:10;
+3405:FC;
+3406:21;
+3407:D7;
+3408:7A;
+3409:E5;
+340A:D1;
+340B:23;
+340C:01;
+340D:0F;
+340E:00;
+340F:ED;
+3410:B0;
+3411:1A;
+3412:FE;
+3413:81;
+3414:20;
+3415:03;
+3416:AF;
+3417:18;
+3418:02;
+3419:3E;
+341A:80;
+341B:12;
+341C:AF;
+341D:32;
+341E:A6;
+341F:78;
+3420:21;
+3421:E0;
+3422:71;
+3423:C9;
+3424:3A;
+3425:D7;
+3426:7A;
+3427:FE;
+3428:81;
+3429:CC;
+342A:F3;
+342B:33;
+342C:CD;
+342D:F3;
+342E:33;
+342F:C9;
+3430:21;
+3431:39;
+3432:78;
+3433:B7;
+3434:20;
+3435:0B;
+3436:CB;
+3437:CE;
+3438:01;
+3439:FF;
+343A:03;
+343B:0B;
+343C:79;
+343D:B0;
+343E:20;
+343F:FB;
+3440:C9;
+3441:CB;
+3442:46;
+3443:C0;
+3444:FE;
+3445:0D;
+3446:28;
+3447:06;
+3448:FE;
+3449:01;
+344A:20;
+344B:04;
+344C:CB;
+344D:D6;
+344E:CB;
+344F:C6;
+3450:E5;
+3451:21;
+3452:A0;
+3453:00;
+3454:01;
+3455:06;
+3456:00;
+3457:CD;
+3458:5C;
+3459:34;
+345A:E1;
+345B:C9;
+345C:3A;
+345D:3B;
+345E:78;
+345F:57;
+3460:CD;
+3461:69;
+3462:34;
+3463:0B;
+3464:79;
+3465:B0;
+3466:20;
+3467:F8;
+3468:C9;
+3469:C5;
+346A:7A;
+346B:EE;
+346C:21;
+346D:32;
+346E:00;
+346F:68;
+3470:E5;
+3471:C1;
+3472:0B;
+3473:79;
+3474:B0;
+3475:20;
+3476:FB;
+3477:7A;
+3478:32;
+3479:00;
+347A:68;
+347B:E5;
+347C:C1;
+347D:0B;
+347E:79;
+347F:B0;
+3480:20;
+3481:FB;
+3482:C1;
+3483:C9;
+3484:CD;
+3485:A0;
+3486:3F;
+3487:3E;
+3488:20;
+3489:32;
+348A:3B;
+348B:78;
+348C:32;
+348D:00;
+348E:68;
+348F:3E;
+3490:3C;
+3491:32;
+3492:3A;
+3493:78;
+3494:3E;
+3495:10;
+3496:32;
+3497:41;
+3498:78;
+3499:AF;
+349A:32;
+349B:AF;
+349C:7A;
+349D:21;
+349E:B2;
+349F:7A;
+34A0:22;
+34A1:B0;
+34A2:7A;
+34A3:3E;
+34A4:C9;
+34A5:C3;
+34A6:37;
+34A7:3E;
+34A8:C9;
+34A9:F3;
+34AA:0E;
+34AB:F0;
+34AC:CD;
+34AD:58;
+34AE:35;
+34AF:DA;
+34B0:FE;
+34B1:3A;
+34B2:E5;
+34B3:01;
+34B4:9A;
+34B5:01;
+34B6:0B;
+34B7:79;
+34B8:B0;
+34B9:20;
+34BA:FB;
+34BB:CD;
+34BC:F8;
+34BD:3A;
+34BE:DD;
+34BF:21;
+34C0:23;
+34C1:78;
+34C2:2A;
+34C3:A4;
+34C4:78;
+34C5:7D;
+34C6:CD;
+34C7:11;
+34C8:35;
+34C9:DD;
+34CA:77;
+34CB:00;
+34CC:AF;
+34CD:DD;
+34CE:77;
+34CF:01;
+34D0:7C;
+34D1:CD;
+34D2:11;
+34D3:35;
+34D4:CD;
+34D5:8E;
+34D6:38;
+34D7:EB;
+34D8:2A;
+34D9:F9;
+34DA:78;
+34DB:7D;
+34DC:CD;
+34DD:11;
+34DE:35;
+34DF:CD;
+34E0:8E;
+34E1:38;
+34E2:7C;
+34E3:CD;
+34E4:11;
+34E5:35;
+34E6:CD;
+34E7:8E;
+34E8:38;
+34E9:CD;
+34EA:F8;
+34EB:3A;
+34EC:1A;
+34ED:13;
+34EE:CD;
+34EF:11;
+34F0:35;
+34F1:CD;
+34F2:8E;
+34F3:38;
+34F4:CD;
+34F5:F8;
+34F6:3A;
+34F7:DF;
+34F8:20;
+34F9:F2;
+34FA:DD;
+34FB:7E;
+34FC:00;
+34FD:CD;
+34FE:11;
+34FF:35;
+3500:DD;
+3501:7E;
+3502:01;
+3503:CD;
+3504:11;
+3505:35;
+3506:06;
+3507:14;
+3508:AF;
+3509:CD;
+350A:11;
+350B:35;
+350C:10;
+350D:FB;
+350E:E1;
+350F:FB;
+3510:C9;
+3511:F5;
+3512:C5;
+3513:E5;
+3514:2E;
+3515:08;
+3516:67;
+3517:CD;
+3518:42;
+3519:35;
+351A:CB;
+351B:04;
+351C:30;
+351D:0D;
+351E:CD;
+351F:42;
+3520:35;
+3521:CD;
+3522:42;
+3523:35;
+3524:2D;
+3525:20;
+3526:F0;
+3527:E1;
+3528:C1;
+3529:F1;
+352A:C9;
+352B:3A;
+352C:3B;
+352D:78;
+352E:F6;
+352F:06;
+3530:32;
+3531:00;
+3532:68;
+3533:06;
+3534:99;
+3535:10;
+3536:FE;
+3537:E6;
+3538:F9;
+3539:32;
+353A:00;
+353B:68;
+353C:06;
+353D:99;
+353E:10;
+353F:FE;
+3540:18;
+3541:E2;
+3542:3A;
+3543:3B;
+3544:78;
+3545:F6;
+3546:06;
+3547:32;
+3548:00;
+3549:68;
+354A:06;
+354B:4C;
+354C:10;
+354D:FE;
+354E:E6;
+354F:F9;
+3550:32;
+3551:00;
+3552:68;
+3553:06;
+3554:4C;
+3555:10;
+3556:FE;
+3557:C9;
+3558:CD;
+3559:8C;
+355A:35;
+355B:06;
+355C:FF;
+355D:3E;
+355E:80;
+355F:CD;
+3560:11;
+3561:35;
+3562:CD;
+3563:E8;
+3564:3A;
+3565:D8;
+3566:10;
+3567:F5;
+3568:06;
+3569:05;
+356A:3E;
+356B:FE;
+356C:CD;
+356D:11;
+356E:35;
+356F:CD;
+3570:E8;
+3571:3A;
+3572:D8;
+3573:10;
+3574:F5;
+3575:79;
+3576:CD;
+3577:11;
+3578:35;
+3579:CD;
+357A:E8;
+357B:3A;
+357C:D8;
+357D:3A;
+357E:D6;
+357F:7A;
+3580:47;
+3581:11;
+3582:9D;
+3583:7A;
+3584:1A;
+3585:13;
+3586:CD;
+3587:11;
+3588:35;
+3589:10;
+358A:F9;
+358B:C9;
+358C:06;
+358D:10;
+358E:11;
+358F:9D;
+3590:7A;
+3591:7E;
+3592:FE;
+3593:3A;
+3594:28;
+3595:12;
+3596:B7;
+3597:28;
+3598:0F;
+3599:CF;
+359A:22;
+359B:7E;
+359C:B7;
+359D:28;
+359E:09;
+359F:23;
+35A0:FE;
+35A1:22;
+35A2:28;
+35A3:04;
+35A4:12;
+35A5:13;
+35A6:10;
+35A7:F3;
+35A8:AF;
+35A9:12;
+35AA:3E;
+35AB:11;
+35AC:90;
+35AD:32;
+35AE:D6;
+35AF:7A;
+35B0:C9;
+35B1:3A;
+35B2:4C;
+35B3:78;
+35B4:B7;
+35B5:C0;
+35B6:3A;
+35B7:3B;
+35B8:78;
+35B9:CB;
+35BA:5F;
+35BB:28;
+35BC:0B;
+35BD:E6;
+35BE:F7;
+35BF:32;
+35C0:3B;
+35C1:78;
+35C2:32;
+35C3:00;
+35C4:68;
+35C5:CD;
+35C6:92;
+35C7:32;
+35C8:21;
+35C9:FF;
+35CA:71;
+35CB:22;
+35CC:20;
+35CD:78;
+35CE:3E;
+35CF:1F;
+35D0:32;
+35D1:A6;
+35D2:78;
+35D3:3A;
+35D4:E5;
+35D5:7A;
+35D6:FE;
+35D7:81;
+35D8:C0;
+35D9:3D;
+35DA:32;
+35DB:E5;
+35DC:7A;
+35DD:32;
+35DE:E6;
+35DF:7A;
+35E0:C9;
+35E1:21;
+35E2:42;
+35E3:38;
+35E4:CD;
+35E5:F4;
+35E6:37;
+35E7:CD;
+35E8:F8;
+35E9:3A;
+35EA:3A;
+35EB:00;
+35EC:68;
+35ED:CB;
+35EE:77;
+35EF:20;
+35F0:F6;
+35F1:CD;
+35F2:8F;
+35F3:37;
+35F4:38;
+35F5:F1;
+35F6:CB;
+35F7:47;
+35F8:28;
+35F9:F7;
+35FA:06;
+35FB:07;
+35FC:CD;
+35FD:8F;
+35FE:37;
+35FF:38;
+3600:E6;
+3601:10;
+3602:F9;
+3603:FE;
+3604:80;
+3605:20;
+3606:E0;
+3607:CD;
+3608:75;
+3609:37;
+360A:DA;
+360B:E7;
+360C:35;
+360D:FE;
+360E:80;
+360F:28;
+3610:F6;
+3611:06;
+3612:04;
+3613:FE;
+3614:FE;
+3615:C2;
+3616:E7;
+3617:35;
+3618:CD;
+3619:75;
+361A:37;
+361B:DA;
+361C:E7;
+361D:35;
+361E:10;
+361F:F3;
+3620:CD;
+3621:75;
+3622:37;
+3623:32;
+3624:D2;
+3625:7A;
+3626:21;
+3627:B2;
+3628:7A;
+3629:06;
+362A:12;
+362B:CD;
+362C:75;
+362D:37;
+362E:77;
+362F:B7;
+3630:28;
+3631:06;
+3632:23;
+3633:10;
+3634:F6;
+3635:C3;
+3636:E7;
+3637:35;
+3638:21;
+3639:5A;
+363A:38;
+363B:CD;
+363C:F4;
+363D:37;
+363E:21;
+363F:B2;
+3640:7A;
+3641:CD;
+3642:14;
+3643:38;
+3644:21;
+3645:B2;
+3646:7A;
+3647:11;
+3648:9D;
+3649:7A;
+364A:1A;
+364B:B7;
+364C:C8;
+364D:BE;
+364E:C2;
+364F:E7;
+3650:35;
+3651:23;
+3652:13;
+3653:18;
+3654:F5;
+3655:C9;
+3656:E5;
+3657:21;
+3658:39;
+3659:78;
+365A:CB;
+365B:B6;
+365C:CB;
+365D:9E;
+365E:E1;
+365F:F3;
+3660:CD;
+3661:8C;
+3662:35;
+3663:E5;
+3664:CD;
+3665:B1;
+3666:35;
+3667:21;
+3668:42;
+3669:38;
+366A:CD;
+366B:F4;
+366C:37;
+366D:CD;
+366E:E7;
+366F:35;
+3670:3A;
+3671:D2;
+3672:7A;
+3673:FE;
+3674:F2;
+3675:28;
+3676:F6;
+3677:21;
+3678:60;
+3679:38;
+367A:CD;
+367B:04;
+367C:38;
+367D:DD;
+367E:21;
+367F:23;
+3680:78;
+3681:CD;
+3682:68;
+3683:38;
+3684:DA;
+3685:11;
+3686:37;
+3687:E5;
+3688:ED;
+3689:52;
+368A:DA;
+368B:11;
+368C:37;
+368D:ED;
+368E:53;
+368F:1E;
+3690:78;
+3691:E5;
+3692:C1;
+3693:E1;
+3694:3A;
+3695:39;
+3696:78;
+3697:CB;
+3698:5F;
+3699:C2;
+369A:42;
+369B:37;
+369C:CD;
+369D:73;
+369E:3F;
+369F:12;
+36A0:CD;
+36A1:8E;
+36A2:38;
+36A3:13;
+36A4:0B;
+36A5:79;
+36A6:B0;
+36A7:20;
+36A8:F3;
+36A9:CD;
+36AA:75;
+36AB:37;
+36AC:DD;
+36AD:BE;
+36AE:00;
+36AF:C2;
+36B0:11;
+36B1:37;
+36B2:CD;
+36B3:75;
+36B4:37;
+36B5:DD;
+36B6:BE;
+36B7:01;
+36B8:C2;
+36B9:11;
+36BA:37;
+36BB:22;
+36BC:F9;
+36BD:78;
+36BE:FB;
+36BF:3E;
+36C0:0D;
+36C1:CD;
+36C2:8B;
+36C3:30;
+36C4:3A;
+36C5:D2;
+36C6:7A;
+36C7:FE;
+36C8:F1;
+36C9:20;
+36CA:04;
+36CB:2A;
+36CC:1E;
+36CD:78;
+36CE:E9;
+36CF:21;
+36D0:29;
+36D1:19;
+36D2:CD;
+36D3:A7;
+36D4:28;
+36D5:2A;
+36D6:A4;
+36D7:78;
+36D8:E5;
+36D9:21;
+36DA:39;
+36DB:78;
+36DC:CB;
+36DD:76;
+36DE:20;
+36DF:03;
+36E0:C3;
+36E1:E8;
+36E2:1A;
+36E3:21;
+36E4:39;
+36E5:78;
+36E6:CB;
+36E7:B6;
+36E8:D1;
+36E9:CD;
+36EA:FC;
+36EB:1A;
+36EC:CD;
+36ED:B5;
+36EE:79;
+36EF:CD;
+36F0:5D;
+36F1:1B;
+36F2:CD;
+36F3:B8;
+36F4:79;
+36F5:21;
+36F6:FF;
+36F7:FF;
+36F8:22;
+36F9:A2;
+36FA:78;
+36FB:21;
+36FC:E8;
+36FD:79;
+36FE:11;
+36FF:70;
+3700:05;
+3701:1A;
+3702:77;
+3703:B7;
+3704:28;
+3705:04;
+3706:23;
+3707:13;
+3708:18;
+3709:F7;
+370A:21;
+370B:E7;
+370C:79;
+370D:AF;
+370E:C3;
+370F:81;
+3710:1A;
+3711:21;
+3712:4A;
+3713:38;
+3714:FB;
+3715:CD;
+3716:A7;
+3717:28;
+3718:F3;
+3719:3A;
+371A:4C;
+371B:78;
+371C:B7;
+371D:C2;
+371E:67;
+371F:36;
+3720:21;
+3721:FF;
+3722:71;
+3723:22;
+3724:20;
+3725:78;
+3726:3E;
+3727:1F;
+3728:32;
+3729:A6;
+372A:78;
+372B:C3;
+372C:67;
+372D:36;
+372E:E5;
+372F:21;
+3730:39;
+3731:78;
+3732:CB;
+3733:F6;
+3734:E1;
+3735:C3;
+3736:5F;
+3737:36;
+3738:E5;
+3739:21;
+373A:39;
+373B:78;
+373C:CB;
+373D:DE;
+373E:E1;
+373F:C3;
+3740:5F;
+3741:36;
+3742:EB;
+3743:CD;
+3744:75;
+3745:37;
+3746:BE;
+3747:28;
+3748:09;
+3749:21;
+374A:6C;
+374B:37;
+374C:CD;
+374D:A7;
+374E:28;
+374F:C3;
+3750:83;
+3751:01;
+3752:23;
+3753:0B;
+3754:79;
+3755:B0;
+3756:20;
+3757:EB;
+3758:21;
+3759:39;
+375A:78;
+375B:CB;
+375C:9E;
+375D:21;
+375E:6C;
+375F:37;
+3760:CD;
+3761:A7;
+3762:28;
+3763:21;
+3764:80;
+3765:03;
+3766:CD;
+3767:A7;
+3768:28;
+3769:C3;
+376A:CF;
+376B:36;
+376C:0D;
+376D:56;
+376E:45;
+376F:52;
+3770:49;
+3771:46;
+3772:59;
+3773:20;
+3774:00;
+3775:C5;
+3776:D5;
+3777:06;
+3778:08;
+3779:CD;
+377A:8F;
+377B:37;
+377C:38;
+377D:0E;
+377E:10;
+377F:F9;
+3780:D1;
+3781:C1;
+3782:32;
+3783:D3;
+3784:7A;
+3785:CD;
+3786:F8;
+3787:3A;
+3788:3A;
+3789:D3;
+378A:7A;
+378B:C9;
+378C:D1;
+378D:C1;
+378E:C9;
+378F:C5;
+3790:01;
+3791:FF;
+3792:07;
+3793:3A;
+3794:00;
+3795:68;
+3796:CB;
+3797:77;
+3798:28;
+3799:08;
+379A:0B;
+379B:79;
+379C:B0;
+379D:20;
+379E:F4;
+379F:C1;
+37A0:37;
+37A1:C9;
+37A2:3A;
+37A3:00;
+37A4:68;
+37A5:CB;
+37A6:77;
+37A7:20;
+37A8:EA;
+37A9:3A;
+37AA:00;
+37AB:68;
+37AC:CB;
+37AD:77;
+37AE:20;
+37AF:E3;
+37B0:06;
+37B1:52;
+37B2:10;
+37B3:FE;
+37B4:3A;
+37B5:00;
+37B6:68;
+37B7:CB;
+37B8:77;
+37B9:20;
+37BA:09;
+37BB:3A;
+37BC:00;
+37BD:68;
+37BE:CB;
+37BF:77;
+37C0:28;
+37C1:F9;
+37C2:18;
+37C3:CC;
+37C4:06;
+37C5:5A;
+37C6:0E;
+37C7:00;
+37C8:3A;
+37C9:00;
+37CA:68;
+37CB:CB;
+37CC:77;
+37CD:28;
+37CE:0B;
+37CF:10;
+37D0:F7;
+37D1:79;
+37D2:3D;
+37D3:1F;
+37D4:CB;
+37D5:12;
+37D6:C1;
+37D7:7A;
+37D8:B7;
+37D9:C9;
+37DA:3A;
+37DB:00;
+37DC:68;
+37DD:CB;
+37DE:77;
+37DF:20;
+37E0:EE;
+37E1:3A;
+37E2:00;
+37E3:68;
+37E4:CB;
+37E5:77;
+37E6:20;
+37E7:E7;
+37E8:0C;
+37E9:3A;
+37EA:00;
+37EB:68;
+37EC:CB;
+37ED:77;
+37EE:20;
+37EF:DF;
+37F0:10;
+37F1:F7;
+37F2:18;
+37F3:DD;
+37F4:3A;
+37F5:4C;
+37F6:78;
+37F7:B7;
+37F8:C0;
+37F9:11;
+37FA:E0;
+37FB:71;
+37FC:06;
+37FD:20;
+37FE:CD;
+37FF:F6;
+3800:3E;
+3801:13;
+3802:10;
+3803:FA;
+3804:3A;
+3805:4C;
+3806:78;
+3807:B7;
+3808:C0;
+3809:CD;
+380A:0E;
+380B:3F;
+380C:7E;
+380D:B7;
+380E:C8;
+380F:12;
+3810:13;
+3811:23;
+3812:18;
+3813:F8;
+3814:3A;
+3815:4C;
+3816:78;
+3817:B7;
+3818:C0;
+3819:11;
+381A:E9;
+381B:71;
+381C:E5;
+381D:3A;
+381E:D2;
+381F:7A;
+3820:E6;
+3821:0F;
+3822:21;
+3823:3F;
+3824:38;
+3825:85;
+3826:6F;
+3827:3E;
+3828:00;
+3829:8C;
+382A:67;
+382B:CD;
+382C:21;
+382D:3F;
+382E:00;
+382F:00;
+3830:12;
+3831:13;
+3832:13;
+3833:E1;
+3834:7E;
+3835:B7;
+3836:C8;
+3837:CD;
+3838:33;
+3839:3F;
+383A:13;
+383B:23;
+383C:18;
+383D:F6;
+383E:C9;
+383F:14;
+3840:02;
+3841:04;
+3842:57;
+3843:41;
+3844:49;
+3845:54;
+3846:49;
+3847:4E;
+3848:47;
+3849:00;
+384A:0D;
+384B:4C;
+384C:4F;
+384D:41;
+384E:44;
+384F:49;
+3850:4E;
+3851:47;
+3852:20;
+3853:45;
+3854:52;
+3855:52;
+3856:4F;
+3857:52;
+3858:0D;
+3859:00;
+385A:46;
+385B:4F;
+385C:55;
+385D:4E;
+385E:44;
+385F:00;
+3860:4C;
+3861:4F;
+3862:41;
+3863:44;
+3864:49;
+3865:4E;
+3866:47;
+3867:00;
+3868:CD;
+3869:75;
+386A:37;
+386B:D8;
+386C:5F;
+386D:DD;
+386E:77;
+386F:00;
+3870:AF;
+3871:DD;
+3872:77;
+3873:01;
+3874:CD;
+3875:75;
+3876:37;
+3877:D8;
+3878:57;
+3879:CD;
+387A:8E;
+387B:38;
+387C:CD;
+387D:75;
+387E:37;
+387F:D8;
+3880:6F;
+3881:CD;
+3882:8E;
+3883:38;
+3884:CD;
+3885:75;
+3886:37;
+3887:D8;
+3888:67;
+3889:CD;
+388A:8E;
+388B:38;
+388C:B7;
+388D:C9;
+388E:DD;
+388F:86;
+3890:00;
+3891:DD;
+3892:77;
+3893:00;
+3894:3E;
+3895:00;
+3896:DD;
+3897:8E;
+3898:01;
+3899:DD;
+389A:77;
+389B:01;
+389C:C9;
+389D:7E;
+389E:FE;
+389F:2C;
+38A0:28;
+38A1:20;
+38A2:CD;
+38A3:1C;
+38A4:2B;
+38A5:B7;
+38A6:CA;
+38A7:4A;
+38A8:1E;
+38A9:FE;
+38AA:09;
+38AB:D2;
+38AC:4A;
+38AD:1E;
+38AE:3D;
+38AF:E6;
+38B0:07;
+38B1:CB;
+38B2:27;
+38B3:CB;
+38B4:27;
+38B5:CB;
+38B6:27;
+38B7:CB;
+38B8:27;
+38B9:32;
+38BA:46;
+38BB:78;
+38BC:7E;
+38BD:B7;
+38BE:C8;
+38BF:FE;
+38C0:3A;
+38C1:C8;
+38C2:CF;
+38C3:2C;
+38C4:CD;
+38C5:1C;
+38C6:2B;
+38C7:B7;
+38C8:20;
+38C9:0C;
+38CA:3A;
+38CB:3B;
+38CC:78;
+38CD:CB;
+38CE:A7;
+38CF:32;
+38D0:3B;
+38D1:78;
+38D2:32;
+38D3:00;
+38D4:68;
+38D5:C9;
+38D6:FE;
+38D7:01;
+38D8:C2;
+38D9:4A;
+38DA:1E;
+38DB:3A;
+38DC:3B;
+38DD:78;
+38DE:CB;
+38DF:E7;
+38E0:32;
+38E1:3B;
+38E2:78;
+38E3:32;
+38E4:00;
+38E5:68;
+38E6:C9;
+38E7:0E;
+38E8:C0;
+38E9:CB;
+38EA:09;
+38EB:10;
+38EC:FC;
+38ED:1A;
+38EE:A1;
+38EF:47;
+38F0:79;
+38F1:CB;
+38F2:08;
+38F3:CB;
+38F4:0F;
+38F5:FE;
+38F6:03;
+38F7:20;
+38F8:F8;
+38F9:78;
+38FA:3C;
+38FB:E5;
+38FC:CD;
+38FD:8D;
+38FE:09;
+38FF:E1;
+3900:C3;
+3901:0F;
+3902:39;
+3903:47;
+3904:1A;
+3905:A1;
+3906:12;
+3907:F1;
+3908:B7;
+3909:F2;
+390A:0F;
+390B:39;
+390C:1A;
+390D:B0;
+390E:12;
+390F:CF;
+3910:29;
+3911:C9;
+3912:F3;
+3913:E5;
+3914:3A;
+3915:3B;
+3916:78;
+3917:CB;
+3918:5F;
+3919:C2;
+391A:8E;
+391B:39;
+391C:21;
+391D:00;
+391E:70;
+391F:0E;
+3920:10;
+3921:06;
+3922:20;
+3923:7E;
+3924:B7;
+3925:F2;
+3926:2D;
+3927:39;
+3928:CD;
+3929:73;
+392A:2C;
+392B:18;
+392C:16;
+392D:C3;
+392E:44;
+392F:3F;
+3930:00;
+3931:E6;
+3932:3F;
+3933:CD;
+3934:56;
+3935:39;
+3936:18;
+3937:0B;
+3938:E6;
+3939:3F;
+393A:CB;
+393B:6F;
+393C:20;
+393D:02;
+393E:F6;
+393F:40;
+3940:CD;
+3941:BA;
+3942:3A;
+3943:23;
+3944:10;
+3945:DD;
+3946:3E;
+3947:0D;
+3948:CD;
+3949:BA;
+394A:3A;
+394B:CD;
+394C:F8;
+394D:3A;
+394E:0D;
+394F:79;
+3950:B7;
+3951:20;
+3952:CE;
+3953:E1;
+3954:FB;
+3955:C9;
+3956:F5;
+3957:C5;
+3958:D5;
+3959:E5;
+395A:6F;
+395B:26;
+395C:00;
+395D:3E;
+395E:08;
+395F:CD;
+3960:BA;
+3961:3A;
+3962:06;
+3963:04;
+3964:E5;
+3965:D1;
+3966:B7;
+3967:ED;
+3968:5A;
+3969:10;
+396A:FC;
+396B:E5;
+396C:C1;
+396D:21;
+396E:94;
+396F:3B;
+3970:09;
+3971:3E;
+3972:FF;
+3973:CD;
+3974:BA;
+3975:3A;
+3976:06;
+3977:05;
+3978:7E;
+3979:23;
+397A:CD;
+397B:BA;
+397C:3A;
+397D:10;
+397E:F9;
+397F:3E;
+3980:FF;
+3981:CD;
+3982:BA;
+3983:3A;
+3984:3E;
+3985:0F;
+3986:CD;
+3987:BA;
+3988:3A;
+3989:E1;
+398A:D1;
+398B:C1;
+398C:F1;
+398D:C9;
+398E:AF;
+398F:32;
+3990:D6;
+3991:7A;
+3992:32;
+3993:D6;
+3994:7A;
+3995:3E;
+3996:08;
+3997:CD;
+3998:BA;
+3999:3A;
+399A:DD;
+399B:21;
+399C:D2;
+399D:7A;
+399E:21;
+399F:00;
+39A0:70;
+39A1:11;
+39A2:00;
+39A3:00;
+39A4:0E;
+39A5:C0;
+39A6:CD;
+39A7:F8;
+39A8:3A;
+39A9:E5;
+39AA:CD;
+39AB:C9;
+39AC:05;
+39AD:06;
+39AE:03;
+39AF:7E;
+39B0:A1;
+39B1:C5;
+39B2:47;
+39B3:CB;
+39B4:08;
+39B5:CB;
+39B6:08;
+39B7:CB;
+39B8:09;
+39B9:CB;
+39BA:09;
+39BB:79;
+39BC:FE;
+39BD:03;
+39BE:C2;
+39BF:B3;
+39C0:39;
+39C1:78;
+39C2:C1;
+39C3:FE;
+39C4:03;
+39C5:28;
+39C6:0D;
+39C7:FE;
+39C8:02;
+39C9:28;
+39CA:0E;
+39CB:FE;
+39CC:01;
+39CD:28;
+39CE:10;
+39CF:11;
+39D0:00;
+39D1:00;
+39D2:18;
+39D3:0F;
+39D4:11;
+39D5:E0;
+39D6:E0;
+39D7:18;
+39D8:0A;
+39D9:16;
+39DA:40;
+39DB:1E;
+39DC:A0;
+39DD:18;
+39DE:04;
+39DF:16;
+39E0:A0;
+39E1:1E;
+39E2:40;
+39E3:DD;
+39E4:7E;
+39E5:00;
+39E6:CB;
+39E7:3F;
+39E8:CB;
+39E9:3F;
+39EA:CB;
+39EB:3F;
+39EC:E5;
+39ED:21;
+39EE:D3;
+39EF:7A;
+39F0:CD;
+39F1:6A;
+39F2:3A;
+39F3:E1;
+39F4:B2;
+39F5:DD;
+39F6:77;
+39F7:00;
+39F8:DD;
+39F9:7E;
+39FA:02;
+39FB:CB;
+39FC:3F;
+39FD:CB;
+39FE:3F;
+39FF:CB;
+3A00:3F;
+3A01:E5;
+3A02:21;
+3A03:D5;
+3A04:7A;
+3A05:CD;
+3A06:6A;
+3A07:3A;
+3A08:E1;
+3A09:B3;
+3A0A:DD;
+3A0B:77;
+3A0C:02;
+3A0D:3E;
+3A0E:20;
+3A0F:85;
+3A10:6F;
+3A11:3E;
+3A12:00;
+3A13:8C;
+3A14:67;
+3A15:10;
+3A16:50;
+3A17:CD;
+3A18:73;
+3A19:3A;
+3A1A:E1;
+3A1B:CB;
+3A1C:39;
+3A1D:CB;
+3A1E:39;
+3A1F:79;
+3A20:B7;
+3A21:20;
+3A22:83;
+3A23:23;
+3A24:7D;
+3A25:E6;
+3A26:1F;
+3A27:C2;
+3A28:A4;
+3A29:39;
+3A2A:CD;
+3A2B:E2;
+3A2C:3A;
+3A2D:3A;
+3A2E:D6;
+3A2F:7A;
+3A30:3C;
+3A31:FE;
+3A32:03;
+3A33:20;
+3A34:01;
+3A35:AF;
+3A36:32;
+3A37:D6;
+3A38:7A;
+3A39:20;
+3A3A:04;
+3A3B:3E;
+3A3C:40;
+3A3D:18;
+3A3E:02;
+3A3F:3E;
+3A40:20;
+3A41:85;
+3A42:6F;
+3A43:3E;
+3A44:00;
+3A45:8C;
+3A46:67;
+3A47:FE;
+3A48:78;
+3A49:D2;
+3A4A:5F;
+3A4B:3A;
+3A4C:FE;
+3A4D:77;
+3A4E:C2;
+3A4F:A4;
+3A50:39;
+3A51:7D;
+3A52:FE;
+3A53:E0;
+3A54:DA;
+3A55:A4;
+3A56:39;
+3A57:3E;
+3A58:FF;
+3A59:32;
+3A5A:D6;
+3A5B:7A;
+3A5C:C3;
+3A5D:A4;
+3A5E:39;
+3A5F:3E;
+3A60:0F;
+3A61:CD;
+3A62:BA;
+3A63:3A;
+3A64:E1;
+3A65:FB;
+3A66:C9;
+3A67:C3;
+3A68:AF;
+3A69:39;
+3A6A:D2;
+3A6B:70;
+3A6C:3A;
+3A6D:CB;
+3A6E:C6;
+3A6F:C9;
+3A70:CB;
+3A71:86;
+3A72:C9;
+3A73:CD;
+3A74:85;
+3A75:3A;
+3A76:DD;
+3A77:23;
+3A78:DD;
+3A79:23;
+3A7A:CD;
+3A7B:85;
+3A7C:3A;
+3A7D:DD;
+3A7E:2B;
+3A7F:DD;
+3A80:2B;
+3A81:CD;
+3A82:85;
+3A83:3A;
+3A84:C9;
+3A85:DD;
+3A86:7E;
+3A87:01;
+3A88:CB;
+3A89:0F;
+3A8A:DD;
+3A8B:7E;
+3A8C:00;
+3A8D:F5;
+3A8E:3A;
+3A8F:D6;
+3A90:7A;
+3A91:FE;
+3A92:02;
+3A93:28;
+3A94:1D;
+3A95:FE;
+3A96:01;
+3A97:28;
+3A98:16;
+3A99:F1;
+3A9A:17;
+3A9B:F5;
+3A9C:3A;
+3A9D:D6;
+3A9E:7A;
+3A9F:FE;
+3AA0:FF;
+3AA1:20;
+3AA2:05;
+3AA3:F1;
+3AA4:E6;
+3AA5:07;
+3AA6:18;
+3AA7:01;
+3AA8:F1;
+3AA9:F6;
+3AAA:80;
+3AAB:CD;
+3AAC:BA;
+3AAD:3A;
+3AAE:C9;
+3AAF:F1;
+3AB0:18;
+3AB1:E9;
+3AB2:F1;
+3AB3:1F;
+3AB4:18;
+3AB5:E5;
+3AB6:B7;
+3AB7:FA;
+3AB8:D8;
+3AB9:3A;
+3ABA:F5;
+3ABB:CD;
+3ABC:E8;
+3ABD:3A;
+3ABE:D2;
+3ABF:C4;
+3AC0:3A;
+3AC1:F1;
+3AC2:37;
+3AC3:C9;
+3AC4:DB;
+3AC5:00;
+3AC6:CB;
+3AC7:47;
+3AC8:20;
+3AC9:F1;
+3ACA:F1;
+3ACB:D3;
+3ACC:0E;
+3ACD:D3;
+3ACE:0D;
+3ACF:FE;
+3AD0:0D;
+3AD1:37;
+3AD2:3F;
+3AD3:C0;
+3AD4:3E;
+3AD5:0A;
+3AD6:18;
+3AD7:E2;
+3AD8:CB;
+3AD9:77;
+3ADA:CA;
+3ADB:73;
+3ADC:2C;
+3ADD:E6;
+3ADE:3F;
+3ADF:C3;
+3AE0:56;
+3AE1:39;
+3AE2:3E;
+3AE3:0D;
+3AE4:CD;
+3AE5:BA;
+3AE6:3A;
+3AE7:C9;
+3AE8:B7;
+3AE9:3A;
+3AEA:FD;
+3AEB:68;
+3AEC:CB;
+3AED:57;
+3AEE:C0;
+3AEF:3A;
+3AF0:DF;
+3AF1:68;
+3AF2:37;
+3AF3:CB;
+3AF4:57;
+3AF5:C8;
+3AF6:3F;
+3AF7:C9;
+3AF8:CD;
+3AF9:E8;
+3AFA:3A;
+3AFB:D0;
+3AFC:E1;
+3AFD:E1;
+3AFE:3A;
+3AFF:39;
+3B00:78;
+3B01:E6;
+3B02:B7;
+3B03:32;
+3B04:39;
+3B05:78;
+3B06:3E;
+3B07:01;
+3B08:FB;
+3B09:C3;
+3B0A:A0;
+3B0B:1D;
+3B0C:3A;
+3B0D:9C;
+3B0E:78;
+3B0F:B7;
+3B10:C2;
+3B11:64;
+3B12:21;
+3B13:3A;
+3B14:AF;
+3B15:7A;
+3B16:B7;
+3B17:20;
+3B18:FA;
+3B19:C3;
+3B1A:64;
+3B1B:21;
+3B1C:3A;
+3B1D:AF;
+3B1E:7A;
+3B1F:B7;
+3B20:C0;
+3B21:3A;
+3B22:A6;
+3B23:78;
+3B24:C9;
+3B25:21;
+3B26:EF;
+3B27:68;
+3B28:CB;
+3B29:66;
+3B2A:20;
+3B2B:18;
+3B2C:CD;
+3B2D:48;
+3B2E:3B;
+3B2F:CB;
+3B30:66;
+3B31:28;
+3B32:FC;
+3B33:CD;
+3B34:48;
+3B35:3B;
+3B36:CD;
+3B37:F8;
+3B38:3A;
+3B39:CB;
+3B3A:66;
+3B3B:20;
+3B3C:F9;
+3B3D:CD;
+3B3E:48;
+3B3F:3B;
+3B40:CB;
+3B41:66;
+3B42:28;
+3B43:FC;
+3B44:21;
+3B45:FF;
+3B46:FF;
+3B47:C9;
+3B48:21;
+3B49:FF;
+3B4A:07;
+3B4B:2B;
+3B4C:7D;
+3B4D:B4;
+3B4E:20;
+3B4F:FB;
+3B50:21;
+3B51:EF;
+3B52:68;
+3B53:C9;
+3B54:CD;
+3B55:11;
+3B56:35;
+3B57:C9;
+3B58:F3;
+3B59:23;
+3B5A:0E;
+3B5B:F2;
+3B5C:CD;
+3B5D:58;
+3B5E:35;
+3B5F:DA;
+3B60:FE;
+3B61:3A;
+3B62:2B;
+3B63:CF;
+3B64:22;
+3B65:CF;
+3B66:2C;
+3B67:C9;
+3B68:F3;
+3B69:23;
+3B6A:CD;
+3B6B:8C;
+3B6C:35;
+3B6D:2B;
+3B6E:CF;
+3B6F:22;
+3B70:CF;
+3B71:2C;
+3B72:E5;
+3B73:CD;
+3B74:B1;
+3B75:35;
+3B76:21;
+3B77:42;
+3B78:38;
+3B79:CD;
+3B7A:F4;
+3B7B:37;
+3B7C:CD;
+3B7D:E7;
+3B7E:35;
+3B7F:3A;
+3B80:D2;
+3B81:7A;
+3B82:FE;
+3B83:F2;
+3B84:20;
+3B85:F6;
+3B86:E1;
+3B87:C9;
+3B88:CD;
+3B89:75;
+3B8A:37;
+3B8B:FE;
+3B8C:0D;
+3B8D:C0;
+3B8E:F5;
+3B8F:CD;
+3B90:F9;
+3B91:20;
+3B92:F1;
+3B93:C9;
+3B94:C1;
+3B95:BE;
+3B96:A2;
+3B97:AE;
+3B98:B1;
+3B99:83;
+3B9A:ED;
+3B9B:EE;
+3B9C:ED;
+3B9D:83;
+3B9E:80;
+3B9F:B6;
+3BA0:B6;
+3BA1:B6;
+3BA2:C1;
+3BA3:C1;
+3BA4:BE;
+3BA5:BE;
+3BA6:BE;
+3BA7:DD;
+3BA8:80;
+3BA9:BE;
+3BAA:BE;
+3BAB:BE;
+3BAC:C1;
+3BAD:80;
+3BAE:B6;
+3BAF:B6;
+3BB0:B6;
+3BB1:BE;
+3BB2:80;
+3BB3:F6;
+3BB4:F6;
+3BB5:F6;
+3BB6:FE;
+3BB7:C1;
+3BB8:BE;
+3BB9:BE;
+3BBA:AE;
+3BBB:8C;
+3BBC:80;
+3BBD:F7;
+3BBE:F7;
+3BBF:F7;
+3BC0:80;
+3BC1:FF;
+3BC2:BE;
+3BC3:80;
+3BC4:BE;
+3BC5:FF;
+3BC6:DF;
+3BC7:BF;
+3BC8:BF;
+3BC9:C0;
+3BCA:FE;
+3BCB:80;
+3BCC:F7;
+3BCD:EB;
+3BCE:DD;
+3BCF:BE;
+3BD0:80;
+3BD1:BF;
+3BD2:BF;
+3BD3:BF;
+3BD4:BF;
+3BD5:80;
+3BD6:FD;
+3BD7:F3;
+3BD8:FD;
+3BD9:80;
+3BDA:80;
+3BDB:FD;
+3BDC:FB;
+3BDD:F7;
+3BDE:80;
+3BDF:C1;
+3BE0:BE;
+3BE1:BE;
+3BE2:BE;
+3BE3:C1;
+3BE4:80;
+3BE5:F6;
+3BE6:F6;
+3BE7:F6;
+3BE8:F9;
+3BE9:C1;
+3BEA:BE;
+3BEB:AE;
+3BEC:DE;
+3BED:A1;
+3BEE:80;
+3BEF:F6;
+3BF0:E6;
+3BF1:D6;
+3BF2:B9;
+3BF3:D9;
+3BF4:B6;
+3BF5:B6;
+3BF6:B6;
+3BF7:CD;
+3BF8:FE;
+3BF9:FE;
+3BFA:80;
+3BFB:FE;
+3BFC:FE;
+3BFD:C0;
+3BFE:BF;
+3BFF:BF;
+3C00:BF;
+3C01:C0;
+3C02:F8;
+3C03:E7;
+3C04:9F;
+3C05:E7;
+3C06:F8;
+3C07:80;
+3C08:DF;
+3C09:E7;
+3C0A:DF;
+3C0B:80;
+3C0C:9C;
+3C0D:ED;
+3C0E:F7;
+3C0F:EB;
+3C10:9C;
+3C11:FC;
+3C12:FB;
+3C13:87;
+3C14:FB;
+3C15:FC;
+3C16:9E;
+3C17:AE;
+3C18:B6;
+3C19:BA;
+3C1A:BC;
+3C1B:FF;
+3C1C:80;
+3C1D:BE;
+3C1E:BE;
+3C1F:FF;
+3C20:FD;
+3C21:FB;
+3C22:F7;
+3C23:EF;
+3C24:DF;
+3C25:FF;
+3C26:BE;
+3C27:BE;
+3C28:80;
+3C29:FF;
+3C2A:FB;
+3C2B:FD;
+3C2C:80;
+3C2D:FD;
+3C2E:FB;
+3C2F:F7;
+3C30:E3;
+3C31:D6;
+3C32:F7;
+3C33:F7;
+3C34:FF;
+3C35:FF;
+3C36:FF;
+3C37:FF;
+3C38:FF;
+3C39:FF;
+3C3A:FF;
+3C3B:A0;
+3C3C:FF;
+3C3D:FF;
+3C3E:FF;
+3C3F:F8;
+3C40:FF;
+3C41:F8;
+3C42:FF;
+3C43:EB;
+3C44:80;
+3C45:EB;
+3C46:80;
+3C47:ED;
+3C48:DB;
+3C49:D6;
+3C4A:80;
+3C4B:D6;
+3C4C:ED;
+3C4D:D9;
+3C4E:E9;
+3C4F:F7;
+3C50:CB;
+3C51:CD;
+3C52:C9;
+3C53:D6;
+3C54:A9;
+3C55:DF;
+3C56:AF;
+3C57:F7;
+3C58:F8;
+3C59:FC;
+3C5A:FF;
+3C5B:FF;
+3C5C:FF;
+3C5D:E3;
+3C5E:DD;
+3C5F:BE;
+3C60:FF;
+3C61:FF;
+3C62:BE;
+3C63:DD;
+3C64:E3;
+3C65:FF;
+3C66:D6;
+3C67:E3;
+3C68:80;
+3C69:E3;
+3C6A:D5;
+3C6B:F7;
+3C6C:F7;
+3C6D:C1;
+3C6E:F7;
+3C6F:F7;
+3C70:DF;
+3C71:C7;
+3C72:F7;
+3C73:FF;
+3C74:FF;
+3C75:F7;
+3C76:F7;
+3C77:F7;
+3C78:F7;
+3C79:F7;
+3C7A:FF;
+3C7B:9F;
+3C7C:9F;
+3C7D:FF;
+3C7E:FF;
+3C7F:DF;
+3C80:EF;
+3C81:F7;
+3C82:FB;
+3C83:FD;
+3C84:C1;
+3C85:AE;
+3C86:B6;
+3C87:BA;
+3C88:C1;
+3C89:FF;
+3C8A:BD;
+3C8B:80;
+3C8C:BF;
+3C8D:FF;
+3C8E:9D;
+3C8F:AE;
+3C90:B6;
+3C91:BA;
+3C92:BD;
+3C93:DD;
+3C94:BB;
+3C95:BB;
+3C96:BB;
+3C97:C9;
+3C98:E7;
+3C99:EB;
+3C9A:ED;
+3C9B:80;
+3C9C:EF;
+3C9D:D8;
+3C9E:BA;
+3C9F:DA;
+3CA0:DA;
+3CA1:C6;
+3CA2:C1;
+3CA3:B6;
+3CA4:B6;
+3CA5:B6;
+3CA6:CF;
+3CA7:FC;
+3CA8:FE;
+3CA9:86;
+3CAA:FA;
+3CAB:FC;
+3CAC:C9;
+3CAD:B6;
+3CAE:B6;
+3CAF:B6;
+3CB0:C9;
+3CB1:F9;
+3CB2:B6;
+3CB3:B6;
+3CB4:B6;
+3CB5:C1;
+3CB6:FF;
+3CB7:C9;
+3CB8:C9;
+3CB9:FF;
+3CBA:FF;
+3CBB:BF;
+3CBC:C4;
+3CBD:E4;
+3CBE:FF;
+3CBF:FF;
+3CC0:F7;
+3CC1:EB;
+3CC2:DD;
+3CC3:DE;
+3CC4:DE;
+3CC5:EB;
+3CC6:EB;
+3CC7:EB;
+3CC8:EB;
+3CC9:EB;
+3CCA:DE;
+3CCB:DE;
+3CCC:DD;
+3CCD:EB;
+3CCE:F7;
+3CCF:FD;
+3CD0:FE;
+3CD1:A6;
+3CD2:FA;
+3CD3:FD;
+3CD4:CB;
+3CD5:3B;
+3CD6:1C;
+3CD7:7E;
+3CD8:23;
+3CD9:B7;
+3CDA:F2;
+3CDB:D7;
+3CDC:3C;
+3CDD:1D;
+3CDE:20;
+3CDF:F7;
+3CE0:E6;
+3CE1:7F;
+3CE2:CD;
+3CE3:2A;
+3CE4:03;
+3CE5:7E;
+3CE6:23;
+3CE7:B7;
+3CE8:F2;
+3CE9:E2;
+3CEA:3C;
+3CEB:C9;
+3CEC:CE;
+3CED:45;
+3CEE:58;
+3CEF:54;
+3CF0:20;
+3CF1:57;
+3CF2:49;
+3CF3:54;
+3CF4:48;
+3CF5:4F;
+3CF6:55;
+3CF7:54;
+3CF8:20;
+3CF9:46;
+3CFA:4F;
+3CFB:52;
+3CFC:D3;
+3CFD:59;
+3CFE:4E;
+3CFF:54;
+3D00:41;
+3D01:58;
+3D02:D2;
+3D03:45;
+3D04:54;
+3D05:27;
+3D06:4E;
+3D07:20;
+3D08:57;
+3D09:49;
+3D0A:54;
+3D0B:48;
+3D0C:4F;
+3D0D:55;
+3D0E:54;
+3D0F:20;
+3D10:47;
+3D11:4F;
+3D12:53;
+3D13:55;
+3D14:42;
+3D15:CF;
+3D16:55;
+3D17:54;
+3D18:20;
+3D19:4F;
+3D1A:46;
+3D1B:20;
+3D1C:44;
+3D1D:41;
+3D1E:54;
+3D1F:41;
+3D20:C6;
+3D21:55;
+3D22:4E;
+3D23:43;
+3D24:54;
+3D25:49;
+3D26:4F;
+3D27:4E;
+3D28:20;
+3D29:43;
+3D2A:4F;
+3D2B:44;
+3D2C:45;
+3D2D:CF;
+3D2E:56;
+3D2F:45;
+3D30:52;
+3D31:46;
+3D32:4C;
+3D33:4F;
+3D34:57;
+3D35:CF;
+3D36:55;
+3D37:54;
+3D38:20;
+3D39:4F;
+3D3A:46;
+3D3B:20;
+3D3C:4D;
+3D3D:45;
+3D3E:4D;
+3D3F:4F;
+3D40:52;
+3D41:59;
+3D42:D5;
+3D43:4E;
+3D44:44;
+3D45:45;
+3D46:46;
+3D47:27;
+3D48:44;
+3D49:20;
+3D4A:53;
+3D4B:54;
+3D4C:41;
+3D4D:54;
+3D4E:45;
+3D4F:4D;
+3D50:45;
+3D51:4E;
+3D52:54;
+3D53:C2;
+3D54:41;
+3D55:44;
+3D56:20;
+3D57:53;
+3D58:55;
+3D59:42;
+3D5A:53;
+3D5B:43;
+3D5C:52;
+3D5D:49;
+3D5E:50;
+3D5F:54;
+3D60:D2;
+3D61:45;
+3D62:44;
+3D63:49;
+3D64:4D;
+3D65:27;
+3D66:44;
+3D67:20;
+3D68:41;
+3D69:52;
+3D6A:52;
+3D6B:41;
+3D6C:59;
+3D6D:C4;
+3D6E:49;
+3D6F:56;
+3D70:49;
+3D71:53;
+3D72:49;
+3D73:4F;
+3D74:4E;
+3D75:20;
+3D76:42;
+3D77:59;
+3D78:20;
+3D79:5A;
+3D7A:45;
+3D7B:52;
+3D7C:4F;
+3D7D:C9;
+3D7E:4C;
+3D7F:4C;
+3D80:45;
+3D81:47;
+3D82:41;
+3D83:4C;
+3D84:20;
+3D85:44;
+3D86:49;
+3D87:52;
+3D88:45;
+3D89:43;
+3D8A:54;
+3D8B:D4;
+3D8C:59;
+3D8D:50;
+3D8E:45;
+3D8F:20;
+3D90:4D;
+3D91:49;
+3D92:53;
+3D93:4D;
+3D94:41;
+3D95:54;
+3D96:43;
+3D97:48;
+3D98:CF;
+3D99:55;
+3D9A:54;
+3D9B:20;
+3D9C:4F;
+3D9D:46;
+3D9E:20;
+3D9F:53;
+3DA0:50;
+3DA1:41;
+3DA2:43;
+3DA3:45;
+3DA4:D3;
+3DA5:54;
+3DA6:52;
+3DA7:49;
+3DA8:4E;
+3DA9:47;
+3DAA:20;
+3DAB:54;
+3DAC:4F;
+3DAD:4F;
+3DAE:20;
+3DAF:4C;
+3DB0:4F;
+3DB1:4E;
+3DB2:47;
+3DB3:C6;
+3DB4:4F;
+3DB5:52;
+3DB6:4D;
+3DB7:55;
+3DB8:4C;
+3DB9:41;
+3DBA:20;
+3DBB:54;
+3DBC:4F;
+3DBD:4F;
+3DBE:20;
+3DBF:43;
+3DC0:4F;
+3DC1:4D;
+3DC2:50;
+3DC3:4C;
+3DC4:45;
+3DC5:58;
+3DC6:C3;
+3DC7:41;
+3DC8:4E;
+3DC9:27;
+3DCA:54;
+3DCB:20;
+3DCC:43;
+3DCD:4F;
+3DCE:4E;
+3DCF:54;
+3DD0:CE;
+3DD1:4F;
+3DD2:20;
+3DD3:52;
+3DD4:45;
+3DD5:53;
+3DD6:55;
+3DD7:4D;
+3DD8:45;
+3DD9:D2;
+3DDA:45;
+3DDB:53;
+3DDC:55;
+3DDD:4D;
+3DDE:45;
+3DDF:20;
+3DE0:57;
+3DE1:49;
+3DE2:54;
+3DE3:48;
+3DE4:4F;
+3DE5:55;
+3DE6:54;
+3DE7:D5;
+3DE8:4E;
+3DE9:50;
+3DEA:52;
+3DEB:49;
+3DEC:4E;
+3DED:54;
+3DEE:41;
+3DEF:42;
+3DF0:4C;
+3DF1:45;
+3DF2:CD;
+3DF3:49;
+3DF4:53;
+3DF5:53;
+3DF6:49;
+3DF7:4E;
+3DF8:47;
+3DF9:20;
+3DFA:4F;
+3DFB:50;
+3DFC:45;
+3DFD:52;
+3DFE:41;
+3DFF:4E;
+3E00:44;
+3E01:C2;
+3E02:41;
+3E03:44;
+3E04:20;
+3E05:46;
+3E06:49;
+3E07:4C;
+3E08:45;
+3E09:20;
+3E0A:44;
+3E0B:41;
+3E0C:54;
+3E0D:41;
+3E0E:C4;
+3E0F:49;
+3E10:53;
+3E11:4B;
+3E12:20;
+3E13:43;
+3E14:4F;
+3E15:4D;
+3E16:4D;
+3E17:41;
+3E18:4E;
+3E19:44;
+3E1A:3F;
+3E1B:53;
+3E1C:59;
+3E1D:4E;
+3E1E:54;
+3E1F:41;
+3E20:58;
+3E21:20;
+3E22:45;
+3E23:52;
+3E24:52;
+3E25:4F;
+3E26:52;
+3E27:0D;
+3E28:00;
+3E29:7E;
+3E2A:B7;
+3E2B:20;
+3E2C:07;
+3E2D:3E;
+3E2E:20;
+3E2F:77;
+3E30:23;
+3E31:AF;
+3E32:77;
+3E33:2B;
+3E34:2B;
+3E35:F1;
+3E36:C9;
+3E37:32;
+3E38:7D;
+3E39:78;
+3E3A:3E;
+3E3B:10;
+3E3C:32;
+3E3D:46;
+3E3E:78;
+3E3F:C9;
+3E40:7E;
+3E41:CB;
+3E42:77;
+3E43:28;
+3E44:05;
+3E45:FE;
+3E46:80;
+3E47:DA;
+3E48:5D;
+3E49:3E;
+3E4A:C1;
+3E4B:11;
+3E4C:53;
+3E4D:3E;
+3E4E:D5;
+3E4F:C5;
+3E50:C3;
+3E51:02;
+3E52:05;
+3E53:D8;
+3E54:21;
+3E55:1A;
+3E56:3E;
+3E57:CD;
+3E58:A7;
+3E59:28;
+3E5A:C3;
+3E5B:E3;
+3E5C:03;
+3E5D:FE;
+3E5E:62;
+3E5F:20;
+3E60:39;
+3E61:E6;
+3E62:BF;
+3E63:12;
+3E64:23;
+3E65:13;
+3E66:05;
+3E67:CA;
+3E68:EE;
+3E69:04;
+3E6A:7E;
+3E6B:CB;
+3E6C:7F;
+3E6D:20;
+3E6E:06;
+3E6F:CB;
+3E70:77;
+3E71:20;
+3E72:0C;
+3E73:18;
+3E74:06;
+3E75:E6;
+3E76:8F;
+3E77:F6;
+3E78:80;
+3E79:18;
+3E7A:17;
+3E7B:F6;
+3E7C:C0;
+3E7D:18;
+3E7E:13;
+3E7F:FE;
+3E80:62;
+3E81:20;
+3E82:09;
+3E83:E5;
+3E84:21;
+3E85:39;
+3E86:78;
+3E87:CB;
+3E88:66;
+3E89:E1;
+3E8A:28;
+3E8B:0E;
+3E8C:CB;
+3E8D:6F;
+3E8E:28;
+3E8F:02;
+3E90:E6;
+3E91:BF;
+3E92:12;
+3E93:23;
+3E94:13;
+3E95:10;
+3E96:D3;
+3E97:C3;
+3E98:EE;
+3E99:04;
+3E9A:CB;
+3E9B:6F;
+3E9C:28;
+3E9D:02;
+3E9E:E6;
+3E9F:BF;
+3EA0:12;
+3EA1:23;
+3EA2:13;
+3EA3:10;
+3EA4:9B;
+3EA5:C3;
+3EA6:EE;
+3EA7:04;
+3EA8:3A;
+3EA9:18;
+3EAA:78;
+3EAB:B7;
+3EAC:C2;
+3EAD:B8;
+3EAE:04;
+3EAF:C3;
+3EB0:6A;
+3EB1:3E;
+3EB2:3A;
+3EB3:18;
+3EB4:78;
+3EB5:B7;
+3EB6:20;
+3EB7:03;
+3EB8:CB;
+3EB9:B6;
+3EBA:C9;
+3EBB:CB;
+3EBC:F6;
+3EBD:C9;
+3EBE:3A;
+3EBF:18;
+3EC0:78;
+3EC1:B7;
+3EC2:3E;
+3EC3:20;
+3EC4:20;
+3EC5:02;
+3EC6:F6;
+3EC7:40;
+3EC8:77;
+3EC9:C9;
+3ECA:F5;
+3ECB:3A;
+3ECC:18;
+3ECD:78;
+3ECE:B7;
+3ECF:28;
+3ED0:07;
+3ED1:F1;
+3ED2:E6;
+3ED3:3F;
+3ED4:E5;
+3ED5:C3;
+3ED6:AB;
+3ED7:31;
+3ED8:F1;
+3ED9:F6;
+3EDA:40;
+3EDB:E5;
+3EDC:21;
+3EDD:38;
+3EDE:78;
+3EDF:CB;
+3EE0:4E;
+3EE1:E1;
+3EE2:28;
+3EE3:02;
+3EE4:E6;
+3EE5:BF;
+3EE6:C3;
+3EE7:B5;
+3EE8:31;
+3EE9:3A;
+3EEA:18;
+3EEB:78;
+3EEC:B7;
+3EED:7E;
+3EEE:20;
+3EEF:03;
+3EF0:FE;
+3EF1:60;
+3EF2:C9;
+3EF3:FE;
+3EF4:20;
+3EF5:C9;
+3EF6:3A;
+3EF7:18;
+3EF8:78;
+3EF9:B7;
+3EFA:3E;
+3EFB:20;
+3EFC:20;
+3EFD:02;
+3EFE:F6;
+3EFF:40;
+3F00:12;
+3F01:C9;
+3F02:06;
+3F03:20;
+3F04:3A;
+3F05:18;
+3F06:78;
+3F07:B7;
+3F08:3E;
+3F09:20;
+3F0A:C0;
+3F0B:F6;
+3F0C:40;
+3F0D:C9;
+3F0E:11;
+3F0F:E0;
+3F10:71;
+3F11:3A;
+3F12:18;
+3F13:78;
+3F14:B7;
+3F15:C0;
+3F16:F1;
+3F17:7E;
+3F18:B7;
+3F19:C8;
+3F1A:CB;
+3F1B:B7;
+3F1C:12;
+3F1D:13;
+3F1E:23;
+3F1F:18;
+3F20:F6;
+3F21:3A;
+3F22:18;
+3F23:78;
+3F24:B7;
+3F25:7E;
+3F26:20;
+3F27:07;
+3F28:CB;
+3F29:F7;
+3F2A:12;
+3F2B:13;
+3F2C:3E;
+3F2D:7A;
+3F2E:C9;
+3F2F:12;
+3F30:3E;
+3F31:3A;
+3F32:C9;
+3F33:F5;
+3F34:3A;
+3F35:18;
+3F36:78;
+3F37:B7;
+3F38:20;
+3F39:05;
+3F3A:F1;
+3F3B:F6;
+3F3C:40;
+3F3D:12;
+3F3E:C9;
+3F3F:F1;
+3F40:E6;
+3F41:3F;
+3F42:12;
+3F43:C9;
+3F44:F5;
+3F45:3A;
+3F46:18;
+3F47:78;
+3F48:B7;
+3F49:20;
+3F4A:09;
+3F4B:F1;
+3F4C:CB;
+3F4D:77;
+3F4E:C2;
+3F4F:38;
+3F50:39;
+3F51:C3;
+3F52:31;
+3F53:39;
+3F54:F1;
+3F55:CB;
+3F56:77;
+3F57:CA;
+3F58:38;
+3F59:39;
+3F5A:C3;
+3F5B:31;
+3F5C:39;
+3F5D:C3;
+3F5E:31;
+3F5F:39;
+3F60:F5;
+3F61:3A;
+3F62:18;
+3F63:78;
+3F64:B7;
+3F65:20;
+3F66:06;
+3F67:F1;
+3F68:E6;
+3F69:3F;
+3F6A:C3;
+3F6B:54;
+3F6C:31;
+3F6D:F1;
+3F6E:E6;
+3F6F:7F;
+3F70:C3;
+3F71:54;
+3F72:31;
+3F73:CD;
+3F74:75;
+3F75:37;
+3F76:D0;
+3F77:E1;
+3F78:C3;
+3F79:11;
+3F7A:37;
+3F7B:3A;
+3F7C:19;
+3F7D:78;
+3F7E:47;
+3F7F:3A;
+3F80:18;
+3F81:78;
+3F82:B8;
+3F83:CA;
+3F84:E8;
+3F85:30;
+3F86:32;
+3F87:19;
+3F88:78;
+3F89:21;
+3F8A:00;
+3F8B:70;
+3F8C:01;
+3F8D:00;
+3F8E:02;
+3F8F:7E;
+3F90:B7;
+3F91:FA;
+3F92:97;
+3F93:3F;
+3F94:EE;
+3F95:40;
+3F96:77;
+3F97:23;
+3F98:0B;
+3F99:78;
+3F9A:B1;
+3F9B:20;
+3F9C:F2;
+3F9D:C3;
+3F9E:E8;
+3F9F:30;
+3FA0:3A;
+3FA1:FD;
+3FA2:68;
+3FA3:CB;
+3FA4:57;
+3FA5:3E;
+3FA6:20;
+3FA7:20;
+3FA8:08;
+3FA9:F6;
+3FAA:40;
+3FAB:32;
+3FAC:18;
+3FAD:78;
+3FAE:32;
+3FAF:19;
+3FB0:78;
+3FB1:32;
+3FB2:3C;
+3FB3:78;
+3FB4:C3;
+3FB5:C9;
+3FB6:01;
+3FB7:00;
+3FB8:00;
+3FB9:00;
+3FBA:00;
+3FBB:00;
+3FBC:00;
+3FBD:00;
+3FBE:00;
+3FBF:00;
+3FC0:00;
+3FC1:00;
+3FC2:00;
+3FC3:00;
+3FC4:00;
+3FC5:00;
+3FC6:00;
+3FC7:00;
+3FC8:00;
+3FC9:00;
+3FCA:00;
+3FCB:00;
+3FCC:00;
+3FCD:00;
+3FCE:00;
+3FCF:00;
+3FD0:00;
+3FD1:00;
+3FD2:00;
+3FD3:00;
+3FD4:00;
+3FD5:00;
+3FD6:00;
+3FD7:00;
+3FD8:00;
+3FD9:00;
+3FDA:00;
+3FDB:00;
+3FDC:00;
+3FDD:00;
+3FDE:00;
+3FDF:00;
+3FE0:00;
+3FE1:00;
+3FE2:00;
+3FE3:00;
+3FE4:00;
+3FE5:00;
+3FE6:00;
+3FE7:00;
+3FE8:00;
+3FE9:00;
+3FEA:00;
+3FEB:00;
+3FEC:00;
+3FED:00;
+3FEE:00;
+3FEF:00;
+3FF0:FF;
+3FF1:FF;
+3FF2:FF;
+3FF3:FF;
+3FF4:FF;
+3FF5:FF;
+3FF6:FF;
+3FF7:FF;
+3FF8:FF;
+3FF9:FF;
+3FFA:FF;
+3FFB:FF;
+3FFC:FF;
+3FFD:FF;
+3FFE:FF;
+3FFF:FF;
+END;
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/COPYING b/Computer_MiST/Laser310_MiST/rtl/sn76489/COPYING
new file mode 100644
index 00000000..60549be5
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/sn76489/COPYING
@@ -0,0 +1,340 @@
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ Everyone is permitted to copy and distribute verbatim copies
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+
+			    Preamble
+
+  The licenses for most software are designed to take away your
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+
+		    GNU GENERAL PUBLIC LICENSE
+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
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+either of that version or of any later version published by the Free
+Software Foundation.  If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
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+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
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+		     END OF TERMS AND CONDITIONS
+
+	    How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
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+  To do so, attach the following notices to the program.  It is safest
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+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) 19yy  <name of author>
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+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
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+    GNU General Public License for more details.
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+
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+    Gnomovision version 69, Copyright (C) 19yy name of author
+    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary.  Here is a sample; alter the names:
+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  <signature of Ty Coon>, 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs.  If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library.  If this is what you want to do, use the GNU Library General
+Public License instead of this License.
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/README b/Computer_MiST/Laser310_MiST/rtl/sn76489/README
new file mode 100644
index 00000000..33630144
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/sn76489/README
@@ -0,0 +1,143 @@
+
+An SN76489AN Compatible Implementation in VHDL
+==============================================
+Version: $Date: 2006/06/18 19:28:40 $
+
+Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
+See the file COPYING.
+
+
+Integration
+-----------
+
+The sn76489 design exhibits all interface signals as the original chip. It
+only differs in the audio data output which is provided as an 8 bit signed
+vector instead of an analog output pin.
+
+  generic (
+    clock_div_16_g : integer := 1
+    -- Set to '1' when operating the design in SN76489 mode. The primary clock
+    -- input is divided by 16 in this variant. The data sheet mentions the
+    -- SN76494 which contains a divide-by-2 clock input stage. Set the generic
+    -- to '0' to enable this mode.
+  );
+  port (
+    clock_i    : in  std_logic;
+    -- Primary clock input
+    -- Drive with the target frequency or any integer multiple of it.
+
+    clock_en_i : in  std_logic;
+    -- Clock enable
+    -- A '1' on this input qualifies a valid rising edge on clock_i. A '0'
+    -- disables the next rising clock edge, effectivley halting the design
+    -- until the next enabled rising clock edge.
+    -- Can be used to run the core at lower frequencies than applied on
+    -- clock_i.
+
+    res_n_i    : in  std_logic;
+    -- Asynchronous low active reset input.
+    -- Sets all sequential elements to a known state.
+
+    ce_n_i     : in  std_logic;
+    -- Chip enable, low active.
+
+    we_n_i     : in  std_logic;
+    -- Write enable, low active.
+
+    ready_o    : out std_logic;
+    -- Ready indication to microprocessor.
+
+    d_i        : in  std_logic_vector(0 to 7);
+    -- Data input
+    -- MSB 0 ... 7 LSB
+
+    aout_o     : out signed(0 to 7)
+    -- Audio output, signed vector
+    -- MSB/SIGN 0 ... 7 LSB
+  );
+
+
+Both 8 bit vector ports are defined (0 to 7) which declares bit 0 to be the
+MSB and bit 7 to be the LSB. This has been implemented according to TI's data
+sheet, thus all register/data format figures apply 1:1 for this design.
+Many systems will flip the system data bus bit wise before it is connected to
+this PSG. This is simply achieved with the following VHDL construct:
+
+  signal data_s : std_logic_vector(7 downto 0);
+
+  ...
+  d_i => data_s,
+  ...
+
+d_i and data_s will be assigned from left to right, resulting in the expected
+bit assignment:
+
+  d_i    data_s
+   0       7
+   1       6
+      ...
+   6       1
+   7       0
+
+
+As this design is fully synchronous, care has to be taken when the design
+replaces an SN76489 in asynchronous mode. No problems are expected when
+interfacing the code to other synchronous components.
+
+
+Design Hierarchy
+----------------
+
+  sn76489_top
+    |
+    +-- sn76489_latch_ctrl
+    |
+    +-- sn76489_clock_div
+    |
+    +-- sn76489_tone
+    |     |
+    |     \-- sn76489_attentuator
+    |
+    +-- sn76489_tone
+    |     |
+    |     \-- sn76489_attentuator
+    |
+    +-- sn76489_tone
+    |     |
+    |     \-- sn76489_attentuator
+    |
+    \-- sn76489_noise
+          |
+          \-- sn76489_attentuator
+
+Resulting compilation sequence:
+
+  sn76489_comp_pack-p.vhd
+  sn76489_top.vhd
+  sn76489_latch_ctrl.vhd
+  sn76489_latch_ctrl-c.vhd
+  sn76489_clock_div.vhd
+  sn76489_clock_div-c.vhd
+  sn76489_attenuator.vhd
+  sn76489_attenuator-c.vhd
+  sn76489_tone.vhd
+  sn76489_tone-c.vhd
+  sn76489_noise.vhd
+  sn76489_noise-c.vhd
+  sn76489_top-c.vhd
+
+Skip the files containing VHDL configurations when analyzing the code for
+synthesis.
+
+
+References
+----------
+
+* TI Data sheet SN76489.pdf
+  ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
+
+* John Kortink's article on the SN76489:
+  http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
+
+* Maxim's "SN76489 notes" in
+  http://www.smspower.org/maxim/docs/SN76489.txt
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_attenuator.vhd b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_attenuator.vhd
new file mode 100644
index 00000000..444064e5
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_attenuator.vhd
@@ -0,0 +1,114 @@
+-------------------------------------------------------------------------------
+--
+-- Synthesizable model of TI's SN76489AN.
+--
+-- $Id: sn76489_attenuator.vhd,v 1.7 2006/02/27 20:30:10 arnim Exp $
+--
+-- Attenuator Module
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sn76489_attenuator is
+
+  port (
+    attenuation_i : in  std_logic_vector(0 to 3);
+    factor_i      : in  signed(0 to 1);
+    product_o     : out signed(0 to 7)
+  );
+
+end sn76489_attenuator;
+
+
+architecture rtl of sn76489_attenuator is
+
+begin
+
+  -----------------------------------------------------------------------------
+  -- Process attenuate
+  --
+  -- Purpose:
+  --   Determine the attenuation and generate the resulting product.
+  --
+  --   The maximum attenuation value is 31 which corresponds to volume off.
+  --   As described in the data sheet, the maximum "playing" attenuation is
+  --     28 = 16 + 8 + 4
+  --
+  --   The table for the volume constants is derived from the following
+  --   formula (each step is 2dB voltage):
+  --     v(0)   = 31
+  --     v(n+1) = v(n) * 0.79432823
+  --
+  attenuate: process (attenuation_i,
+                      factor_i)
+
+    type     volume_t is array (natural range 0 to 15) of natural;
+    constant volume_c : volume_t :=
+      (31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0);
+
+    variable attenuation_v  : unsigned(attenuation_i'range);
+    variable volume_v       : signed(product_o'range);
+
+  begin
+
+    attenuation_v := unsigned(attenuation_i);
+
+    -- volume look-up table
+    volume_v := to_signed(volume_c(to_integer(attenuation_v)),
+                          product_o'length);
+
+    -- this replaces a multiplier and consumes a bit fewer
+    -- resources
+    case to_integer(factor_i) is
+      when +1 =>
+        product_o <= volume_v;
+      when -1 =>
+        product_o <= -volume_v;
+      when others =>
+        product_o <= (others => '0');
+    end case;
+
+  end process attenuate;
+  --
+  -----------------------------------------------------------------------------
+
+end rtl;
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_clock_div.vhd b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_clock_div.vhd
new file mode 100644
index 00000000..eab86beb
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_clock_div.vhd
@@ -0,0 +1,134 @@
+-------------------------------------------------------------------------------
+--
+-- Synthesizable model of TI's SN76489AN.
+--
+-- $Id: sn76489_clock_div.vhd,v 1.4 2005/10/10 21:51:27 arnim Exp $
+--
+-- Clock Divider Circuit
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity sn76489_clock_div is
+
+  generic (
+    clock_div_16_g : integer := 1
+  );
+  port (
+    clock_i    : in  std_logic;
+    clock_en_i : in  std_logic;
+    res_n_i    : in  std_logic;
+    clk_en_o   : out boolean
+  );
+
+end sn76489_clock_div;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of sn76489_clock_div is
+
+  signal cnt_s,
+         cnt_q  : unsigned(3 downto 0);
+
+begin
+
+  -----------------------------------------------------------------------------
+  -- Process seq
+  --
+  -- Purpose:
+  --   Implements the sequential counter element.
+  --
+  seq: process (clock_i, res_n_i)
+  begin
+    if res_n_i = '0' then
+      cnt_q <= (others => '0');
+    elsif clock_i'event and clock_i = '1' then
+      cnt_q <= cnt_s;
+    end if;
+  end process seq;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process comb
+  --
+  -- Purpose:
+  --   Implements the combinational counter logic.
+  --
+  comb: process (clock_en_i,
+                 cnt_q)
+  begin
+    -- default assignments
+    cnt_s    <= cnt_q;
+    clk_en_o <= false;
+
+    if clock_en_i = '1' then
+
+      if cnt_q = 0 then
+        clk_en_o <= true;
+
+        if clock_div_16_g = 1 then
+          cnt_s  <= to_unsigned(15, cnt_q'length);
+        elsif clock_div_16_g = 0 then
+          cnt_s  <= to_unsigned( 1, cnt_q'length);
+        else
+          -- pragma translate_off
+          assert false
+            report "Generic clock_div_16_g must be either 0 or 1."
+            severity failure;
+          -- pragma translate_on
+        end if;
+
+      else
+        cnt_s    <= cnt_q - 1;
+
+      end if;
+
+    end if;
+
+  end process comb;
+  --
+  -----------------------------------------------------------------------------
+
+end rtl;
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd
new file mode 100644
index 00000000..789720c2
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd
@@ -0,0 +1,138 @@
+-------------------------------------------------------------------------------
+--
+-- Synthesizable model of TI's SN76489AN.
+--
+-- $Id: sn76489_latch_ctrl.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
+--
+-- Latch Control Unit
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity sn76489_latch_ctrl is
+
+  port (
+    clock_i    : in  std_logic;
+    clk_en_i   : in  boolean;
+    res_n_i    : in  std_logic;
+    ce_n_i     : in  std_logic;
+    we_n_i     : in  std_logic;
+    d_i        : in  std_logic_vector(0 to 7);
+    ready_o    : out std_logic;
+    tone1_we_o : out boolean;
+    tone2_we_o : out boolean;
+    tone3_we_o : out boolean;
+    noise_we_o : out boolean;
+    r2_o       : out std_logic
+  );
+
+end sn76489_latch_ctrl;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of sn76489_latch_ctrl is
+
+  signal reg_q   : std_logic_vector(0 to 2);
+  signal we_q    : boolean;
+  signal ready_q : std_logic;
+
+begin
+
+  -----------------------------------------------------------------------------
+  -- Process seq
+  --
+  -- Purpose:
+  --   Implements the sequential elements.
+  --
+  seq: process (clock_i, res_n_i)
+  begin
+    if res_n_i = '0' then
+      reg_q     <= (others => '0');
+      we_q      <= false;
+      ready_q   <= '0';
+
+    elsif clock_i'event and clock_i = '1' then
+      -- READY Flag Output ----------------------------------------------------
+      if ready_q = '0' and we_q then
+        if clk_en_i then
+          -- assert READY when write access happened
+          ready_q <= '1';
+        end if;
+      elsif ce_n_i = '1' then
+        -- deassert READY when access has finished
+        ready_q <= '0';
+      end if;
+
+      -- Register Selection ---------------------------------------------------
+      if ce_n_i = '0' and we_n_i = '0' then
+        if clk_en_i then
+          if d_i(0) = '1' then
+            reg_q <= d_i(1 to 3);
+          end if;
+          we_q  <= true;
+        end if;
+      else
+        we_q  <= false;
+      end if;
+
+    end if;
+  end process seq;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Output mapping
+  -----------------------------------------------------------------------------
+  tone1_we_o <= reg_q(0 to 1) = "00" and we_q;
+  tone2_we_o <= reg_q(0 to 1) = "01" and we_q;
+  tone3_we_o <= reg_q(0 to 1) = "10" and we_q;
+  noise_we_o <= reg_q(0 to 1) = "11" and we_q;
+
+  r2_o       <= reg_q(2);
+
+  ready_o    <=   ready_q
+                when ce_n_i = '0' else
+                  '1';
+
+end rtl;
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_noise.vhd b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_noise.vhd
new file mode 100644
index 00000000..688bdd56
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_noise.vhd
@@ -0,0 +1,278 @@
+-------------------------------------------------------------------------------
+--
+-- Synthesizable model of TI's SN76489AN.
+--
+-- $Id: sn76489_noise.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
+--
+-- Noise Generator
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sn76489_noise is
+
+  port (
+    clock_i    : in  std_logic;
+    clk_en_i   : in  boolean;
+    res_n_i    : in  std_logic;
+    we_i       : in  boolean;
+    d_i        : in  std_logic_vector(0 to 7);
+    r2_i       : in  std_logic;
+    tone3_ff_i : in  std_logic;
+    noise_o    : out signed(0 to 7)
+  );
+
+end sn76489_noise;
+
+architecture rtl of sn76489_noise is
+
+  signal nf_q       : std_logic_vector(0 to 1);
+  signal fb_q       : std_logic;
+  signal a_q        : std_logic_vector(0 to 3);
+  signal freq_cnt_q : unsigned(0 to 6);
+  signal freq_ff_q  : std_logic;
+
+  signal shift_source_s,
+         shift_source_q    : std_logic;
+  signal shift_rise_edge_s : boolean;
+
+  signal lfsr_q            : std_logic_vector(0 to 15);
+
+  signal freq_s      : signed(0 to 1);
+
+begin
+
+  -----------------------------------------------------------------------------
+  -- Process cpu_regs
+  --
+  -- Purpose:
+  --   Implements the registers writable by the CPU.
+  --
+  cpu_regs: process (clock_i, res_n_i)
+  begin
+    if res_n_i = '0' then
+      nf_q <= (others => '0');
+      fb_q <= '0';
+      a_q  <= (others => '1');
+
+    elsif clock_i'event and clock_i = '1' then
+      if clk_en_i and we_i then
+        if r2_i = '0' then
+          -- access to control register
+          -- both access types can write to the control register!
+          nf_q <= d_i(6 to 7);
+          fb_q <= d_i(5);
+
+        else
+          -- access to attenuator register
+          -- both access types can write to the attenuator register!
+          a_q <= d_i(4 to 7);
+
+        end if;
+      end if;
+    end if;
+  end process cpu_regs;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process freq_gen
+  --
+  -- Purpose:
+  --   Implements the frequency generation components.
+  --
+  freq_gen: process (clock_i, res_n_i)
+  begin
+    if res_n_i = '0' then
+      freq_cnt_q <= (others => '0');
+      freq_ff_q  <= '0';
+
+    elsif clock_i'event and clock_i = '1' then
+      if clk_en_i then
+        if freq_cnt_q = 0 then
+          -- reload frequency counter according to NF setting
+          case nf_q is
+            when "00" =>
+              freq_cnt_q <= to_unsigned(16 * 2 - 1, freq_cnt_q'length);
+            when "01" =>
+              freq_cnt_q <= to_unsigned(16 * 4 - 1, freq_cnt_q'length);
+            when "10" =>
+              freq_cnt_q <= to_unsigned(16 * 8 - 1, freq_cnt_q'length);
+            when others =>
+              null;
+          end case;
+
+          freq_ff_q <= not freq_ff_q;
+
+        else
+          -- decrement frequency counter
+          freq_cnt_q <= freq_cnt_q - 1;
+
+        end if;
+
+      end if;
+    end if;
+  end process freq_gen;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Multiplex the source of the LFSR's shift enable
+  -----------------------------------------------------------------------------
+  shift_source_s <=   tone3_ff_i
+                    when nf_q = "11" else
+                      freq_ff_q;
+
+  -----------------------------------------------------------------------------
+  -- Process rise_edge
+  --
+  -- Purpose:
+  --   Detect the rising edge of the selected LFSR shift source.
+  --
+  rise_edge: process (clock_i, res_n_i)
+  begin
+    if res_n_i = '0' then
+      shift_source_q <= '0';
+
+    elsif clock_i'event and clock_i = '1' then
+      if clk_en_i then
+        shift_source_q <= shift_source_s;
+      end if;
+    end if;
+  end process rise_edge;
+  --
+  -----------------------------------------------------------------------------
+
+  -- detect rising edge on shift source
+  shift_rise_edge_s <= shift_source_q = '0' and shift_source_s = '1';
+
+
+  -----------------------------------------------------------------------------
+  -- Process lfsr
+  --
+  -- Purpose:
+  --   Implements the LFSR that generates noise.
+  --   Note: This implementation shifts the register right, i.e. from index
+  --         15 towards 0 => bit 15 is the input, bit 0 is the output
+  --
+  --   Tapped bits according to MAME's sn76496.c, implemented in function
+  --   lfsr_tapped_f.
+  --
+  lfsr: process (clock_i, res_n_i)
+
+    function lfsr_tapped_f(lfsr : in std_logic_vector) return std_logic is
+      constant tapped_bits_c : std_logic_vector(0 to 15)
+        -- tapped bits are 0, 2, 15
+        := "1010000000000001";
+      variable parity_v : std_logic;
+    begin
+      parity_v := '0';
+
+      for idx in lfsr'low to lfsr'high loop
+        parity_v := parity_v xor (lfsr(idx) and tapped_bits_c(idx));
+      end loop;
+
+      return parity_v;
+    end;
+
+  begin
+    if res_n_i = '0' then
+      -- reset LFSR to "0000000000000001"
+      lfsr_q               <= (others => '0');
+      lfsr_q(lfsr_q'right) <= '1';
+
+    elsif clock_i'event and clock_i = '1' then
+      if clk_en_i then
+        if we_i and r2_i = '0' then
+          -- write to noise register
+          -- -> reset LFSR
+          lfsr_q               <= (others => '0');
+          lfsr_q(lfsr_q'right) <= '1';
+
+        elsif shift_rise_edge_s then
+
+          -- shift LFSR left towards MSB
+          for idx in lfsr_q'right-1 downto lfsr_q'left loop
+            lfsr_q(idx) <= lfsr_q(idx+1);
+          end loop;
+
+          -- determine input bit
+          if fb_q = '0' then
+            -- "Periodic" Noise
+            -- -> input to LFSR is output
+            lfsr_q(lfsr_q'right) <= lfsr_q(lfsr_q'left);
+          else
+            -- "White" Noise
+            -- -> input to LFSR is parity of tapped bits
+            lfsr_q(lfsr_q'right) <= lfsr_tapped_f(lfsr_q);
+          end if;
+
+        end if;
+
+      end if;
+    end if;
+  end process lfsr;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Map output of LFSR to signed value for attenuator.
+  -----------------------------------------------------------------------------
+  freq_s <=   to_signed(+1, 2)
+            when lfsr_q(0) = '1' else
+              to_signed( 0, 2);
+
+
+  -----------------------------------------------------------------------------
+  -- The attenuator itself
+  -----------------------------------------------------------------------------
+  attenuator_b : entity work.sn76489_attenuator
+    port map (
+      attenuation_i => a_q,
+      factor_i      => freq_s,
+      product_o     => noise_o
+    );
+
+end rtl;
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_tone.vhd b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_tone.vhd
new file mode 100644
index 00000000..3658efcc
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_tone.vhd
@@ -0,0 +1,188 @@
+-------------------------------------------------------------------------------
+--
+-- Synthesizable model of TI's SN76489AN.
+--
+-- $Id: sn76489_tone.vhd,v 1.5 2006/02/27 20:30:10 arnim Exp $
+--
+-- Tone Generator
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sn76489_tone is
+
+  port (
+    clock_i  : in  std_logic;
+    clk_en_i : in  boolean;
+    res_n_i  : in  std_logic;
+    we_i     : in  boolean;
+    d_i      : in  std_logic_vector(0 to 7);
+    r2_i     : in  std_logic;
+    ff_o     : out std_logic;
+    tone_o   : out signed(0 to 7)
+  );
+
+end sn76489_tone;
+
+architecture rtl of sn76489_tone is
+
+  signal f_q        : std_logic_vector(0 to 9);
+  signal a_q        : std_logic_vector(0 to 3);
+  signal freq_cnt_q : unsigned(0 to 9);
+  signal freq_ff_q  : std_logic;
+
+  signal freq_s     : signed(0 to 1);
+
+  function all_zero(a : in std_logic_vector) return boolean is
+    variable result_v : boolean;
+  begin
+    result_v := true;
+
+    for idx in a'low to a'high loop
+      if a(idx) /= '0' then
+        result_v := false;
+      end if;
+    end loop;
+
+    return result_v;
+  end;
+
+begin
+
+  -----------------------------------------------------------------------------
+  -- Process cpu_regs
+  --
+  -- Purpose:
+  --   Implements the registers writable by the CPU.
+  --
+  cpu_regs: process (clock_i, res_n_i)
+  begin
+    if res_n_i = '0' then
+      f_q <= (others => '0');
+      a_q <= (others => '1');
+
+    elsif clock_i'event and clock_i = '1' then
+      if clk_en_i and we_i then
+        if r2_i = '0' then
+          -- access to frequency register
+          if d_i(0) = '0' then
+            f_q(0 to 5) <= d_i(2 to 7);
+          else
+            f_q(6 to 9) <= d_i(4 to 7);
+          end if;
+
+        else
+          -- access to attenuator register
+          -- both access types can write to the attenuator register!
+          a_q <= d_i(4 to 7);
+
+        end if;
+      end if;
+    end if;
+  end process cpu_regs;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process freq_gen
+  --
+  -- Purpose:
+  --   Implements the frequency generation components.
+  --
+  freq_gen: process (clock_i, res_n_i)
+  begin
+    if res_n_i = '0' then
+      freq_cnt_q <= (others => '0');
+      freq_ff_q  <= '0';
+
+    elsif clock_i'event and clock_i = '1' then
+      if clk_en_i then
+        if freq_cnt_q = 0 then
+          -- update counter from frequency register
+          freq_cnt_q <= unsigned(f_q);
+
+          -- and toggle the frequency flip-flop if enabled
+          if not all_zero(f_q) then
+            freq_ff_q <= not freq_ff_q;
+          else
+            -- if frequency setting is 0, then keep flip-flop at +1
+            freq_ff_q <= '1';
+          end if;
+
+        else
+          -- decrement frequency counter
+          freq_cnt_q <= freq_cnt_q - 1;
+
+        end if;
+      end if;
+    end if;
+  end process freq_gen;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Map frequency flip-flop to signed value for attenuator.
+  -----------------------------------------------------------------------------
+  freq_s <=   to_signed(+1, 2)
+            when freq_ff_q = '1' else
+              to_signed(-1, 2);
+
+
+  -----------------------------------------------------------------------------
+  -- The attenuator itself
+  -----------------------------------------------------------------------------
+  attenuator_b : entity work.sn76489_attenuator
+    port map (
+      attenuation_i => a_q,
+      factor_i      => freq_s,
+      product_o     => tone_o
+    );
+
+
+  -----------------------------------------------------------------------------
+  -- Output mapping
+  -----------------------------------------------------------------------------
+  ff_o <= freq_ff_q;
+
+end rtl;
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_top.vhd b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_top.vhd
new file mode 100644
index 00000000..c26d0e1a
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_top.vhd
@@ -0,0 +1,200 @@
+-------------------------------------------------------------------------------
+--
+-- Synthesizable model of TI's SN76489AN.
+--
+-- $Id: sn76489_top.vhd,v 1.9 2006/02/27 20:30:10 arnim Exp $
+--
+-- Chip Toplevel
+--
+-- References:
+--
+--   * TI Data sheet SN76489.pdf
+--     ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
+--
+--   * John Kortink's article on the SN76489:
+--     http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
+--
+--   * Maxim's "SN76489 notes" in
+--     http://www.smspower.org/maxim/docs/SN76489.txt
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sn76489_top is
+
+  generic (
+    clock_div_16_g : integer := 1
+  );
+  port (
+    clock_i    : in  std_logic;
+    clock_en_i : in  std_logic;
+    res_n_i    : in  std_logic;
+    ce_n_i     : in  std_logic;
+    we_n_i     : in  std_logic;
+    ready_o    : out std_logic;
+    d_i        : in  std_logic_vector(0 to 7);
+    aout_o     : out signed(0 to 7)
+  );
+
+end sn76489_top;
+
+architecture struct of sn76489_top is
+
+  signal clk_en_s    : boolean;
+
+  signal tone1_we_s,
+         tone2_we_s,
+         tone3_we_s,
+         noise_we_s  : boolean;
+  signal r2_s        : std_logic;
+
+  signal tone1_s,
+         tone2_s,
+         tone3_s,
+         noise_s     : signed(0 to 7);
+
+  signal tone3_ff_s  : std_logic;
+
+begin
+
+  -----------------------------------------------------------------------------
+  -- Clock Divider
+  -----------------------------------------------------------------------------
+  clock_div_b : entity work.sn76489_clock_div
+    generic map (
+      clock_div_16_g => clock_div_16_g
+    )
+    port map (
+      clock_i    => clock_i,
+      clock_en_i => clock_en_i,
+      res_n_i    => res_n_i,
+      clk_en_o   => clk_en_s
+    );
+
+
+  -----------------------------------------------------------------------------
+  -- Latch Control = CPU Interface
+  -----------------------------------------------------------------------------
+  latch_ctrl_b : entity work.sn76489_latch_ctrl
+    port map (
+      clock_i    => clock_i,
+      clk_en_i   => clk_en_s,
+      res_n_i    => res_n_i,
+      ce_n_i     => ce_n_i,
+      we_n_i     => we_n_i,
+      d_i        => d_i,
+      ready_o    => ready_o,
+      tone1_we_o => tone1_we_s,
+      tone2_we_o => tone2_we_s,
+      tone3_we_o => tone3_we_s,
+      noise_we_o => noise_we_s,
+      r2_o       => r2_s
+    );
+
+
+  -----------------------------------------------------------------------------
+  -- Tone Channel 1
+  -----------------------------------------------------------------------------
+  tone1_b : entity work.sn76489_tone
+    port map (
+      clock_i  => clock_i,
+      clk_en_i => clk_en_s,
+      res_n_i  => res_n_i,
+      we_i     => tone1_we_s,
+      d_i      => d_i,
+      r2_i     => r2_s,
+      ff_o     => open,
+      tone_o   => tone1_s
+    );
+
+  -----------------------------------------------------------------------------
+  -- Tone Channel 2
+  -----------------------------------------------------------------------------
+  tone2_b : entity work.sn76489_tone
+    port map (
+      clock_i  => clock_i,
+      clk_en_i => clk_en_s,
+      res_n_i  => res_n_i,
+      we_i     => tone2_we_s,
+      d_i      => d_i,
+      r2_i     => r2_s,
+      ff_o     => open,
+      tone_o   => tone2_s
+    );
+
+  -----------------------------------------------------------------------------
+  -- Tone Channel 3
+  -----------------------------------------------------------------------------
+  tone3_b : entity work.sn76489_tone
+    port map (
+      clock_i  => clock_i,
+      clk_en_i => clk_en_s,
+      res_n_i  => res_n_i,
+      we_i     => tone3_we_s,
+      d_i      => d_i,
+      r2_i     => r2_s,
+      ff_o     => tone3_ff_s,
+      tone_o   => tone3_s
+    );
+
+  -----------------------------------------------------------------------------
+  -- Noise Channel
+  -----------------------------------------------------------------------------
+  noise_b : entity work.sn76489_noise
+    port map (
+      clock_i    => clock_i,
+      clk_en_i   => clk_en_s,
+      res_n_i    => res_n_i,
+      we_i       => noise_we_s,
+      d_i        => d_i,
+      r2_i       => r2_s,
+      tone3_ff_i => tone3_ff_s,
+      noise_o    => noise_s
+    );
+
+
+  aout_o <= tone1_s + tone2_s + tone3_s + noise_s;
+
+end struct;
diff --git a/Computer_MiST/Laser310_MiST/rtl/spram.vhd b/Computer_MiST/Laser310_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/spram.vhd
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Computer_MiST/Laser310_MiST/rtl/sprom.vhd b/Computer_MiST/Laser310_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/sprom.vhd
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_alu.v b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_alu.v
new file mode 100644
index 00000000..f90bc70a
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_alu.v
@@ -0,0 +1,442 @@
+//
+// TV80 8-Bit Microprocessor Core
+// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
+//
+// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a 
+// copy of this software and associated documentation files (the "Software"), 
+// to deal in the Software without restriction, including without limitation 
+// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
+// and/or sell copies of the Software, and to permit persons to whom the 
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included 
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+module tv80_alu (/*AUTOARG*/
+  // Outputs
+  Q, F_Out, 
+  // Inputs
+  Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In
+  );
+
+  parameter		Mode   = 0;
+  parameter		Flag_C = 0;
+  parameter		Flag_N = 1;
+  parameter		Flag_P = 2;
+  parameter		Flag_X = 3;
+  parameter		Flag_H = 4;
+  parameter		Flag_Y = 5;
+  parameter		Flag_Z = 6;
+  parameter		Flag_S = 7;
+
+  input 		Arith16;
+  input 		Z16;
+  input [3:0]           ALU_Op ;
+  input [5:0]           IR;
+  input [1:0]           ISet;
+  input [7:0]           BusA;
+  input [7:0]           BusB;
+  input [7:0]           F_In;
+  output [7:0]          Q;
+  output [7:0]          F_Out;
+  reg [7:0]             Q;
+  reg [7:0]             F_Out;
+
+  function [4:0] AddSub4;
+    input [3:0] A;
+    input [3:0] B;
+    input Sub;
+    input Carry_In;
+    begin
+      AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {4'h0,Carry_In};
+    end
+  endfunction // AddSub4
+  
+  function [3:0] AddSub3;
+    input [2:0] A;
+    input [2:0] B;
+    input Sub;
+    input Carry_In;
+    begin
+      AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {3'h0,Carry_In};
+    end
+  endfunction // AddSub4
+
+  function [1:0] AddSub1;
+    input A;
+    input B;
+    input Sub;
+    input Carry_In;
+    begin
+      AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {1'h0,Carry_In};
+    end
+  endfunction // AddSub4
+
+  // AddSub variables (temporary signals)
+  reg UseCarry;
+  reg Carry7_v;
+  reg OverFlow_v;
+  reg HalfCarry_v;
+  reg Carry_v;
+  reg [7:0] Q_v;
+
+  reg [7:0] BitMask;
+
+
+  always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR)
+    begin
+      case (IR[5:3])
+        3'b000 : BitMask = 8'b00000001;
+        3'b001 : BitMask = 8'b00000010;
+        3'b010 : BitMask = 8'b00000100; 
+        3'b011 : BitMask = 8'b00001000; 
+        3'b100 : BitMask = 8'b00010000; 
+        3'b101 : BitMask = 8'b00100000; 
+        3'b110 : BitMask = 8'b01000000; 
+        default: BitMask = 8'b10000000; 
+      endcase // case(IR[5:3])
+      
+      UseCarry = ~ ALU_Op[2] && ALU_Op[0];
+      { HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) );
+      { Carry7_v, Q_v[6:4]  } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v);
+      { Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v);
+      OverFlow_v = Carry_v ^ Carry7_v;
+    end // always @ *
+  
+  reg [7:0] Q_t;
+  reg [8:0] DAA_Q;
+  
+  always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB
+	    or Carry_v or F_In or HalfCarry_v or IR or ISet
+	    or OverFlow_v or Q_v or Z16)
+    begin
+      Q_t = 8'hxx;
+      DAA_Q = {9{1'bx}};
+      
+      F_Out = F_In;
+      case (ALU_Op)
+	4'b0000, 4'b0001,  4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 :
+          begin
+	    F_Out[Flag_N] = 1'b0;
+	    F_Out[Flag_C] = 1'b0;
+            
+	    case (ALU_Op[2:0])
+              
+	      3'b000, 3'b001 : // ADD, ADC
+                begin
+		  Q_t = Q_v;
+		  F_Out[Flag_C] = Carry_v;
+		  F_Out[Flag_H] = HalfCarry_v;
+		  F_Out[Flag_P] = OverFlow_v;
+                end
+              
+	      3'b010, 3'b011, 3'b111 : // SUB, SBC, CP
+                begin
+		  Q_t = Q_v;
+		  F_Out[Flag_N] = 1'b1;
+		  F_Out[Flag_C] = ~ Carry_v;
+		  F_Out[Flag_H] = ~ HalfCarry_v;
+		  F_Out[Flag_P] = OverFlow_v;
+                end
+              
+	      3'b100 : // AND
+                begin
+		  Q_t[7:0] = BusA & BusB;
+		  F_Out[Flag_H] = 1'b1;
+                end
+              
+	      3'b101 : // XOR
+                begin
+		  Q_t[7:0] = BusA ^ BusB;
+		  F_Out[Flag_H] = 1'b0;
+                end
+              
+	      default : // OR 3'b110
+                begin
+		  Q_t[7:0] = BusA | BusB;
+		  F_Out[Flag_H] = 1'b0;
+                end
+              
+	    endcase // case(ALU_OP[2:0])
+            
+	    if (ALU_Op[2:0] == 3'b111 ) 
+              begin // CP
+		F_Out[Flag_X] = BusB[3];
+		F_Out[Flag_Y] = BusB[5];
+	      end 
+            else 
+              begin
+		F_Out[Flag_X] = Q_t[3];
+		F_Out[Flag_Y] = Q_t[5];
+	      end
+            
+	    if (Q_t[7:0] == 8'b00000000 ) 
+              begin
+		F_Out[Flag_Z] = 1'b1;
+		if (Z16 == 1'b1 ) 
+                  begin
+		    F_Out[Flag_Z] = F_In[Flag_Z];	// 16 bit ADC,SBC
+		  end
+	      end 
+            else 
+              begin
+		F_Out[Flag_Z] = 1'b0;
+	      end // else: !if(Q_t[7:0] == 8'b00000000 )
+            
+	    F_Out[Flag_S] = Q_t[7];
+	    case (ALU_Op[2:0])
+	      3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP
+                ;
+              
+	      default :
+	        F_Out[Flag_P] = ~(^Q_t);                    
+	    endcase // case(ALU_Op[2:0])
+            
+	    if (Arith16 == 1'b1 ) 
+              begin
+		F_Out[Flag_S] = F_In[Flag_S];
+		F_Out[Flag_Z] = F_In[Flag_Z];
+		F_Out[Flag_P] = F_In[Flag_P];
+	      end
+          end // case: 4'b0000, 4'b0001,  4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111
+        
+	4'b1100 :
+          begin
+	    // DAA
+	    F_Out[Flag_H] = F_In[Flag_H];
+	    F_Out[Flag_C] = F_In[Flag_C];
+	    DAA_Q[7:0] = BusA;
+	    DAA_Q[8] = 1'b0;
+	    if (F_In[Flag_N] == 1'b0 ) 
+              begin
+		// After addition
+		// Alow > 9 || H == 1
+		if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) 
+                  begin
+		    if ((DAA_Q[3:0] > 9) ) 
+                      begin
+			F_Out[Flag_H] = 1'b1;
+		      end 
+                    else 
+                      begin
+			F_Out[Flag_H] = 1'b0;
+		      end
+		    DAA_Q = DAA_Q + 6;
+		  end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
+                
+		// new Ahigh > 9 || C == 1
+		if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 ) 
+                  begin
+		    DAA_Q = DAA_Q + 96; // 0x60
+		  end
+	      end 
+            else 
+              begin
+		// After subtraction
+		if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) 
+                  begin
+		    if (DAA_Q[3:0] > 5 ) 
+                      begin
+			F_Out[Flag_H] = 1'b0;
+		      end
+		    DAA_Q[7:0] = DAA_Q[7:0] - 6;
+		  end
+		if (BusA > 153 || F_In[Flag_C] == 1'b1 ) 
+                  begin
+		    DAA_Q = DAA_Q - 352; // 0x160
+		  end
+	      end // else: !if(F_In[Flag_N] == 1'b0 )
+            
+	    F_Out[Flag_X] = DAA_Q[3];
+	    F_Out[Flag_Y] = DAA_Q[5];
+	    F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8];
+	    Q_t = DAA_Q[7:0];
+            
+	    if (DAA_Q[7:0] == 8'b00000000 ) 
+              begin
+		F_Out[Flag_Z] = 1'b1;
+	      end 
+            else 
+              begin
+		F_Out[Flag_Z] = 1'b0;
+	      end
+            
+	    F_Out[Flag_S] = DAA_Q[7];
+	    F_Out[Flag_P] = ~ (^DAA_Q);
+          end // case: 4'b1100
+        
+	4'b1101, 4'b1110 :
+          begin
+	    // RLD, RRD
+	    Q_t[7:4] = BusA[7:4];
+	    if (ALU_Op[0] == 1'b1 ) 
+              begin
+		Q_t[3:0] = BusB[7:4];
+	      end 
+            else 
+              begin
+		Q_t[3:0] = BusB[3:0];
+	      end
+	    F_Out[Flag_H] = 1'b0;
+	    F_Out[Flag_N] = 1'b0;
+	    F_Out[Flag_X] = Q_t[3];
+	    F_Out[Flag_Y] = Q_t[5];
+	    if (Q_t[7:0] == 8'b00000000 ) 
+              begin
+		F_Out[Flag_Z] = 1'b1;
+	      end 
+            else 
+              begin
+		F_Out[Flag_Z] = 1'b0;
+	      end
+	    F_Out[Flag_S] = Q_t[7];
+            F_Out[Flag_P] = ~(^Q_t);
+          end // case: when 4'b1101, 4'b1110
+        
+	4'b1001 :
+          begin
+	    // BIT
+	    Q_t[7:0] = BusB & BitMask;
+	    F_Out[Flag_S] = Q_t[7];
+	    if (Q_t[7:0] == 8'b00000000 ) 
+              begin
+		F_Out[Flag_Z] = 1'b1;
+		F_Out[Flag_P] = 1'b1;
+	      end 
+            else 
+              begin
+		F_Out[Flag_Z] = 1'b0;
+		F_Out[Flag_P] = 1'b0;
+	      end
+	    F_Out[Flag_H] = 1'b1;
+	    F_Out[Flag_N] = 1'b0;
+	    F_Out[Flag_X] = 1'b0;
+	    F_Out[Flag_Y] = 1'b0;
+	    if (IR[2:0] != 3'b110 ) 
+              begin
+		F_Out[Flag_X] = BusB[3];
+		F_Out[Flag_Y] = BusB[5];
+	      end
+          end // case: when 4'b1001
+        
+	4'b1010 :
+	  // SET
+	  Q_t[7:0] = BusB | BitMask;
+        
+	4'b1011 :
+	  // RES
+	  Q_t[7:0] = BusB & ~ BitMask;
+        
+	4'b1000 :
+          begin
+	    // ROT
+	    case (IR[5:3])
+	      3'b000 : // RLC
+                begin
+		  Q_t[7:1] = BusA[6:0];
+		  Q_t[0] = BusA[7];
+		  F_Out[Flag_C] = BusA[7];
+                end
+              
+	      3'b010 : // RL
+                begin
+		  Q_t[7:1] = BusA[6:0];
+		  Q_t[0] = F_In[Flag_C];
+		  F_Out[Flag_C] = BusA[7];
+                end
+              
+	      3'b001 : // RRC
+                begin
+		  Q_t[6:0] = BusA[7:1];
+		  Q_t[7] = BusA[0];
+		  F_Out[Flag_C] = BusA[0];
+                end
+              
+	      3'b011 : // RR
+                begin                        
+		  Q_t[6:0] = BusA[7:1];
+		  Q_t[7] = F_In[Flag_C];
+		  F_Out[Flag_C] = BusA[0];
+                end
+              
+	      3'b100 : // SLA
+                begin
+		  Q_t[7:1] = BusA[6:0];
+		  Q_t[0] = 1'b0;
+		  F_Out[Flag_C] = BusA[7];
+                end
+              
+	      3'b110 : // SLL (Undocumented) / SWAP
+                begin
+		  if (Mode == 3 ) 
+                    begin
+		      Q_t[7:4] = BusA[3:0];
+		      Q_t[3:0] = BusA[7:4];
+		      F_Out[Flag_C] = 1'b0;                            
+		    end 
+                  else 
+                    begin
+		      Q_t[7:1] = BusA[6:0];
+		      Q_t[0] = 1'b1;
+		      F_Out[Flag_C] = BusA[7];
+		    end // else: !if(Mode == 3 )
+                end // case: 3'b110
+              
+	      3'b101 : // SRA
+                begin
+		  Q_t[6:0] = BusA[7:1];
+		  Q_t[7] = BusA[7];
+		  F_Out[Flag_C] = BusA[0];
+                end
+              
+	      default : // SRL
+                begin
+		  Q_t[6:0] = BusA[7:1];
+		  Q_t[7] = 1'b0;
+		  F_Out[Flag_C] = BusA[0];
+                end
+	    endcase // case(IR[5:3])
+            
+	    F_Out[Flag_H] = 1'b0;
+	    F_Out[Flag_N] = 1'b0;
+	    F_Out[Flag_X] = Q_t[3];
+	    F_Out[Flag_Y] = Q_t[5];
+	    F_Out[Flag_S] = Q_t[7];
+	    if (Q_t[7:0] == 8'b00000000 ) 
+              begin
+		F_Out[Flag_Z] = 1'b1;
+	      end 
+            else 
+              begin
+		F_Out[Flag_Z] = 1'b0;
+	      end
+            F_Out[Flag_P] = ~(^Q_t);
+
+	    if (ISet == 2'b00 ) 
+              begin
+		F_Out[Flag_P] = F_In[Flag_P];
+		F_Out[Flag_S] = F_In[Flag_S];
+		F_Out[Flag_Z] = F_In[Flag_Z];
+	      end
+          end // case: 4'b1000
+        
+        
+	default :
+	  ;
+        
+      endcase // case(ALU_Op)
+      
+      Q = Q_t;
+    end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+  
+endmodule // T80_ALU
diff --git a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_core.v b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_core.v
new file mode 100644
index 00000000..e3f7d247
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_core.v
@@ -0,0 +1,1389 @@
+//
+// TV80 8-Bit Microprocessor Core
+// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
+//
+// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a 
+// copy of this software and associated documentation files (the "Software"), 
+// to deal in the Software without restriction, including without limitation 
+// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
+// and/or sell copies of the Software, and to permit persons to whom the 
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included 
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+module tv80_core (/*AUTOARG*/
+  // Outputs
+  m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, dout, mc,
+  ts, intcycle_n, IntE, stop,
+  // Inputs
+  reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di
+  );
+  // Beginning of automatic inputs (from unused autoinst inputs)
+  // End of automatics
+  
+  parameter Mode = 1;   // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+  parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
+  parameter Flag_C = 0;
+  parameter Flag_N = 1;
+  parameter Flag_P = 2;
+  parameter Flag_X = 3;
+  parameter Flag_H = 4;
+  parameter Flag_Y = 5;
+  parameter Flag_Z = 6;
+  parameter Flag_S = 7;
+
+  input     reset_n;            
+  input     clk;                
+  input     cen;                
+  input     wait_n;             
+  input     int_n;              
+  input     nmi_n;              
+  input     busrq_n;            
+  output    m1_n;               
+  output    iorq;               
+  output    no_read;            
+  output    write;              
+  output    rfsh_n;             
+  output    halt_n;             
+  output    busak_n;            
+  output [15:0] A; 
+  input [7:0]   dinst;  
+  input [7:0]   di;     
+  output [7:0]  dout;     
+  output [6:0]  mc;     
+  output [6:0]  ts;     
+  output        intcycle_n;     
+  output        IntE;           
+  output        stop;           
+
+  reg    m1_n;          
+  reg    iorq; 
+`ifdef TV80_REFRESH         
+  reg    rfsh_n;   
+`endif             
+  reg    halt_n;                
+  reg    busak_n;               
+  reg [15:0] A; 
+  reg [7:0]  dout;        
+  reg [6:0]  mc;        
+  reg [6:0]  ts;        
+  reg   intcycle_n;     
+  reg   IntE;           
+  reg   stop;           
+
+  parameter     aNone    = 3'b111;
+  parameter     aBC      = 3'b000;
+  parameter     aDE      = 3'b001;
+  parameter     aXY      = 3'b010;
+  parameter     aIOA     = 3'b100;
+  parameter     aSP      = 3'b101;
+  parameter     aZI      = 3'b110;
+
+  // Registers
+  reg [7:0]     ACC, F;
+  reg [7:0]     Ap, Fp;
+  reg [7:0]     I;
+`ifdef TV80_REFRESH
+  reg [7:0]     R;
+`endif
+  reg [15:0]    SP, PC;
+  reg [7:0]     RegDIH;
+  reg [7:0]     RegDIL;
+  wire [15:0]   RegBusA;
+  wire [15:0]   RegBusB;
+  wire [15:0]   RegBusC;
+  reg [2:0]     RegAddrA_r;
+  reg [2:0]     RegAddrA;
+  reg [2:0]     RegAddrB_r;
+  reg [2:0]     RegAddrB;
+  reg [2:0]     RegAddrC;
+  reg           RegWEH;
+  reg           RegWEL;
+  reg           Alternate;
+
+  // Help Registers
+  reg [15:0]    TmpAddr;        // Temporary address register
+  reg [7:0]     IR;             // Instruction register
+  reg [1:0]     ISet;           // Instruction set selector
+  reg [15:0]    RegBusA_r;
+
+  reg [15:0]    ID16;
+  reg [7:0]     Save_Mux;
+
+  reg [6:0]     tstate;
+  reg [6:0]     mcycle;
+  reg           last_mcycle, last_tstate;
+  reg           IntE_FF1;
+  reg           IntE_FF2;
+  reg           Halt_FF;
+  reg           BusReq_s;
+  reg           BusAck;
+  reg           ClkEn;
+  reg           NMI_s;
+  reg           INT_s;
+  reg [1:0]     IStatus;
+
+  reg [7:0]     DI_Reg;
+  reg           T_Res;
+  reg [1:0]     XY_State;
+  reg [2:0]     Pre_XY_F_M;
+  reg           NextIs_XY_Fetch;
+  reg           XY_Ind;
+  reg           No_BTR;
+  reg           BTR_r;
+  reg           Auto_Wait;
+  reg           Auto_Wait_t1;
+  reg           Auto_Wait_t2;
+  reg           IncDecZ;
+
+  // ALU signals
+  reg [7:0]     BusB;
+  reg [7:0]     BusA;
+  wire [7:0]    ALU_Q;
+  wire [7:0]    F_Out;
+
+  // Registered micro code outputs
+  reg [4:0]     Read_To_Reg_r;
+  reg           Arith16_r;
+  reg           Z16_r;
+  reg [3:0]     ALU_Op_r;
+  reg           Save_ALU_r;
+  reg           PreserveC_r;
+  reg [2:0]     mcycles;
+
+  // Micro code outputs
+  wire [2:0]    mcycles_d;
+  wire [2:0]    tstates;
+  reg           IntCycle;
+  reg           NMICycle;
+  wire          Inc_PC;
+  wire          Inc_WZ;
+  wire [3:0]    IncDec_16;
+  wire [1:0]    Prefix;
+  wire          Read_To_Acc;
+  wire          Read_To_Reg;
+  wire [3:0]     Set_BusB_To;
+  wire [3:0]     Set_BusA_To;
+  wire [3:0]     ALU_Op;
+  wire           Save_ALU;
+  wire           PreserveC;
+  wire           Arith16;
+  wire [2:0]     Set_Addr_To;
+  wire           Jump;
+  wire           JumpE;
+  wire           JumpXY;
+  wire           Call;
+  wire           RstP;
+  wire           LDZ;
+  wire           LDW;
+  wire           LDSPHL;
+  wire           iorq_i;
+  wire [2:0]     Special_LD;
+  wire           ExchangeDH;
+  wire           ExchangeRp;
+  wire           ExchangeAF;
+  wire           ExchangeRS;
+  wire           I_DJNZ;
+  wire           I_CPL;
+  wire           I_CCF;
+  wire           I_SCF;
+  wire           I_RETN;
+  wire           I_BT;
+  wire           I_BC;
+  wire           I_BTR;
+  wire           I_RLD;
+  wire           I_RRD;
+  wire           I_INRC;
+  wire           SetDI;
+  wire           SetEI;
+  wire [1:0]     IMode;
+  wire           Halt;
+
+  reg [15:0]     PC16;
+  reg [15:0]     PC16_B;
+  reg [15:0]     SP16, SP16_A, SP16_B;
+  reg [15:0]     ID16_B;
+  reg            Oldnmi_n;
+  
+  tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode
+    (
+     .IR                   (IR),
+     .ISet                 (ISet),
+     .MCycle               (mcycle),
+     .F                    (F),
+     .NMICycle             (NMICycle),
+     .IntCycle             (IntCycle),
+     .MCycles              (mcycles_d),
+     .TStates              (tstates),
+     .Prefix               (Prefix),
+     .Inc_PC               (Inc_PC),
+     .Inc_WZ               (Inc_WZ),
+     .IncDec_16            (IncDec_16),
+     .Read_To_Acc          (Read_To_Acc),
+     .Read_To_Reg          (Read_To_Reg),
+     .Set_BusB_To          (Set_BusB_To),
+     .Set_BusA_To          (Set_BusA_To),
+     .ALU_Op               (ALU_Op),
+     .Save_ALU             (Save_ALU),
+     .PreserveC            (PreserveC),
+     .Arith16              (Arith16),
+     .Set_Addr_To          (Set_Addr_To),
+     .IORQ                 (iorq_i),
+     .Jump                 (Jump),
+     .JumpE                (JumpE),
+     .JumpXY               (JumpXY),
+     .Call                 (Call),
+     .RstP                 (RstP),
+     .LDZ                  (LDZ),
+     .LDW                  (LDW),
+     .LDSPHL               (LDSPHL),
+     .Special_LD           (Special_LD),
+     .ExchangeDH           (ExchangeDH),
+     .ExchangeRp           (ExchangeRp),
+     .ExchangeAF           (ExchangeAF),
+     .ExchangeRS           (ExchangeRS),
+     .I_DJNZ               (I_DJNZ),
+     .I_CPL                (I_CPL),
+     .I_CCF                (I_CCF),
+     .I_SCF                (I_SCF),
+     .I_RETN               (I_RETN),
+     .I_BT                 (I_BT),
+     .I_BC                 (I_BC),
+     .I_BTR                (I_BTR),
+     .I_RLD                (I_RLD),
+     .I_RRD                (I_RRD),
+     .I_INRC               (I_INRC),
+     .SetDI                (SetDI),
+     .SetEI                (SetEI),
+     .IMode                (IMode),
+     .Halt                 (Halt),
+     .NoRead               (no_read),
+     .Write                (write)
+     );
+
+  tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu
+    (
+     .Arith16              (Arith16_r),
+     .Z16                  (Z16_r),
+     .ALU_Op               (ALU_Op_r),
+     .IR                   (IR[5:0]),
+     .ISet                 (ISet),
+     .BusA                 (BusA),
+     .BusB                 (BusB),
+     .F_In                 (F),
+     .Q                    (ALU_Q),
+     .F_Out                (F_Out)
+     );
+
+  function [6:0] number_to_bitvec;
+    input [2:0] num;
+    begin
+      case (num)
+        1 : number_to_bitvec = 7'b0000001;
+        2 : number_to_bitvec = 7'b0000010;
+        3 : number_to_bitvec = 7'b0000100;
+        4 : number_to_bitvec = 7'b0001000;
+        5 : number_to_bitvec = 7'b0010000;
+        6 : number_to_bitvec = 7'b0100000;
+        7 : number_to_bitvec = 7'b1000000;
+        default : number_to_bitvec = 7'bx;
+      endcase // case(num)
+    end
+  endfunction // number_to_bitvec
+
+  function [2:0] mcyc_to_number;
+    input [6:0] mcyc;
+    begin
+      casez (mcyc)
+        7'b1zzzzzz : mcyc_to_number = 3'h7;
+        7'b01zzzzz : mcyc_to_number = 3'h6;
+        7'b001zzzz : mcyc_to_number = 3'h5;
+        7'b0001zzz : mcyc_to_number = 3'h4;
+        7'b00001zz : mcyc_to_number = 3'h3;
+        7'b000001z : mcyc_to_number = 3'h2;
+        7'b0000001 : mcyc_to_number = 3'h1;
+        default : mcyc_to_number = 3'h1;
+      endcase
+    end
+  endfunction
+  
+  always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates)
+    begin
+      case (mcycles)
+        1 : last_mcycle = mcycle[0];
+        2 : last_mcycle = mcycle[1];
+        3 : last_mcycle = mcycle[2];
+        4 : last_mcycle = mcycle[3];
+        5 : last_mcycle = mcycle[4];
+        6 : last_mcycle = mcycle[5];
+        7 : last_mcycle = mcycle[6];
+        default : last_mcycle = 1'bx;
+      endcase // case(mcycles)
+
+      case (tstates)
+        0 : last_tstate = tstate[0];
+        1 : last_tstate = tstate[1];
+        2 : last_tstate = tstate[2];
+        3 : last_tstate = tstate[3];
+        4 : last_tstate = tstate[4];
+        5 : last_tstate = tstate[5];
+        6 : last_tstate = tstate[6];
+        default : last_tstate = 1'bx;
+      endcase
+    end // always @ (...
+  
+          
+  always @(/*AUTOSENSE*/ALU_Q or BusAck or BusB or DI_Reg
+	   or ExchangeRp or IR or Save_ALU_r or Set_Addr_To or XY_Ind
+	   or XY_State or cen or last_tstate or mcycle)
+    begin
+      ClkEn = cen && ~ BusAck;
+
+      if (last_tstate)
+        T_Res = 1'b1;
+      else T_Res = 1'b0;
+      
+      if (XY_State != 2'b00 && XY_Ind == 1'b0 &&
+          ((Set_Addr_To == aXY) ||
+           (mcycle[0] && IR == 8'b11001011) ||
+           (mcycle[0] && IR == 8'b00110110)))
+        NextIs_XY_Fetch = 1'b1;
+      else 
+        NextIs_XY_Fetch = 1'b0;
+
+      if (ExchangeRp)
+        Save_Mux = BusB;
+      else if (!Save_ALU_r)
+        Save_Mux = DI_Reg;
+      else
+        Save_Mux = ALU_Q;
+    end // always @ *
+  
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 1'b0 ) 
+        begin
+          PC <= #1 0;  // Program Counter
+          A <= #1 0;
+          TmpAddr <= #1 0;
+          IR <= #1 8'b00000000;
+          ISet <= #1 2'b00;
+          XY_State <= #1 2'b00;
+          IStatus <= #1 2'b00;
+          mcycles <= #1 3'b000;
+          dout <= #1 8'b00000000;
+
+          ACC <= #1 8'hFF;
+          F <= #1 8'hFF;
+          Ap <= #1 8'hFF;
+          Fp <= #1 8'hFF;
+          I <= #1 0;
+          `ifdef TV80_REFRESH
+          R <= #1 0;
+          `endif
+          SP <= #1 16'hFFFF;
+          Alternate <= #1 1'b0;
+
+          Read_To_Reg_r <= #1 5'b00000;
+          Arith16_r <= #1 1'b0;
+          BTR_r <= #1 1'b0;
+          Z16_r <= #1 1'b0;
+          ALU_Op_r <= #1 4'b0000;
+          Save_ALU_r <= #1 1'b0;
+          PreserveC_r <= #1 1'b0;
+          XY_Ind <= #1 1'b0;
+        end 
+      else 
+        begin
+
+          if (ClkEn == 1'b1 ) 
+            begin
+
+              ALU_Op_r <= #1 4'b0000;
+              Save_ALU_r <= #1 1'b0;
+              Read_To_Reg_r <= #1 5'b00000;
+
+              mcycles <= #1 mcycles_d;
+
+              if (IMode != 2'b11 ) 
+                begin
+                  IStatus <= #1 IMode;
+                end
+
+              Arith16_r <= #1 Arith16;
+              PreserveC_r <= #1 PreserveC;
+              if (ISet == 2'b10 && ALU_Op[2] == 1'b0 && ALU_Op[0] == 1'b1 && mcycle[2] ) 
+                begin
+                  Z16_r <= #1 1'b1;
+                end 
+              else 
+                begin
+                  Z16_r <= #1 1'b0;
+                end
+
+              if (mcycle[0] && (tstate[1] | tstate[2] | tstate[3] )) 
+                begin
+                  // mcycle == 1 && tstate == 1, 2, || 3
+                  if (tstate[2] && wait_n == 1'b1 ) 
+                    begin
+                      `ifdef TV80_REFRESH
+                      if (Mode < 2 ) 
+                        begin
+                          A[7:0] <= #1 R;
+                          A[15:8] <= #1 I;
+                          R[6:0] <= #1 R[6:0] + 1;
+                        end
+                      `endif
+                      if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 || Halt == 1'b1) ) 
+                        begin
+                          PC <= #1 PC16;
+                        end
+
+                      if (IntCycle == 1'b1 && IStatus == 2'b01 ) 
+                        begin
+                          IR <= #1 8'b11111111;
+                        end 
+                      else if (Halt_FF == 1'b1 || (IntCycle == 1'b1 && IStatus == 2'b10) || NMICycle == 1'b1 ) 
+                        begin
+                          IR <= #1 8'b00000000;
+			  TmpAddr[7:0] <= #1 dinst; // Special M1 vector fetch
+                        end 
+                      else 
+                        begin
+                          IR <= #1 dinst;
+                        end
+
+                      ISet <= #1 2'b00;
+                      if (Prefix != 2'b00 ) 
+                        begin
+                          if (Prefix == 2'b11 ) 
+                            begin
+                              if (IR[5] == 1'b1 ) 
+                                begin
+                                  XY_State <= #1 2'b10;
+                                end 
+                              else 
+                                begin
+                                  XY_State <= #1 2'b01;
+                                end
+                            end 
+                          else 
+                            begin
+                              if (Prefix == 2'b10 ) 
+                                begin
+                                  XY_State <= #1 2'b00;
+                                  XY_Ind <= #1 1'b0;
+                                end
+                              ISet <= #1 Prefix;
+                            end
+                        end 
+                      else 
+                        begin
+                          XY_State <= #1 2'b00;
+                          XY_Ind <= #1 1'b0;
+                        end
+                    end // if (tstate == 2 && wait_n == 1'b1 )
+                  
+
+                end 
+              else 
+                begin
+                  // either (mcycle > 1) OR (mcycle == 1 AND tstate > 3)
+
+                  if (mcycle[5] ) 
+                    begin
+                      XY_Ind <= #1 1'b1;
+                      if (Prefix == 2'b01 ) 
+                        begin
+                          ISet <= #1 2'b01;
+                        end
+                    end
+                  
+                  if (T_Res == 1'b1 ) 
+                    begin
+                      BTR_r <= #1 (I_BT || I_BC || I_BTR) && ~ No_BTR;
+                      if (Jump == 1'b1 ) 
+                        begin
+                          A[15:8] <= #1 DI_Reg;
+                          A[7:0] <= #1 TmpAddr[7:0];
+                          PC[15:8] <= #1 DI_Reg;
+                          PC[7:0] <= #1 TmpAddr[7:0];
+                        end 
+                      else if (JumpXY == 1'b1 ) 
+                        begin
+                          A <= #1 RegBusC;
+                          PC <= #1 RegBusC;
+                        end else if (Call == 1'b1 || RstP == 1'b1 ) 
+                          begin
+                            A <= #1 TmpAddr;
+                            PC <= #1 TmpAddr;
+                          end 
+                        else if (last_mcycle && NMICycle == 1'b1 ) 
+                          begin
+                            A <= #1 16'b0000000001100110;
+                            PC <= #1 16'b0000000001100110;
+                          end 
+                        else if (mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 ) 
+                          begin
+                            A[15:8] <= #1 I;
+                            A[7:0] <= #1 TmpAddr[7:0];
+                            PC[15:8] <= #1 I;
+                            PC[7:0] <= #1 TmpAddr[7:0];
+                          end 
+                        else 
+                          begin
+                            case (Set_Addr_To)
+                              aXY :
+                                begin
+                                  if (XY_State == 2'b00 ) 
+                                    begin
+                                      A <= #1 RegBusC;
+                                    end 
+                                  else 
+                                    begin
+                                      if (NextIs_XY_Fetch == 1'b1 )
+                                        begin
+                                          A <= #1 PC;
+                                        end 
+                                      else 
+                                        begin
+                                          A <= #1 TmpAddr;
+                                        end
+                                    end // else: !if(XY_State == 2'b00 )
+                                end // case: aXY
+                              
+                              aIOA :
+                                begin
+                                  if (Mode == 3 ) 
+                                    begin
+                                      // Memory map I/O on GBZ80
+                                      A[15:8] <= #1 8'hFF;
+                                    end 
+                                  else if (Mode == 2 ) 
+                                    begin
+                                      // Duplicate I/O address on 8080
+                                      A[15:8] <= #1 DI_Reg;
+                                    end 
+                                  else 
+                                    begin
+                                      A[15:8] <= #1 ACC;
+                                    end
+                                  A[7:0] <= #1 DI_Reg;
+                                end // case: aIOA
+
+                              
+                              aSP :
+                                begin
+                                  A <= #1 SP;
+                                end
+                              
+                              aBC :
+                                begin
+                                  if (Mode == 3 && iorq_i == 1'b1 ) 
+                                    begin
+                                      // Memory map I/O on GBZ80
+                                      A[15:8] <= #1 8'hFF;
+                                      A[7:0] <= #1 RegBusC[7:0];
+                                    end 
+                                  else 
+                                    begin
+                                      A <= #1 RegBusC;
+                                    end
+                                end // case: aBC
+                              
+                              aDE :
+                                begin
+                                  A <= #1 RegBusC;
+                                end
+                              
+                              aZI :
+                                begin                                  
+                                  if (Inc_WZ == 1'b1 ) 
+                                    begin
+                                      A <= #1 TmpAddr + 1;
+                                    end 
+                                  else 
+                                    begin
+                                      A[15:8] <= #1 DI_Reg;
+                                      A[7:0] <= #1 TmpAddr[7:0];
+                                    end
+                                end // case: aZI
+                              
+                              default   :
+                                begin                                    
+                                  A <= #1 PC;
+                                end
+                            endcase // case(Set_Addr_To)
+                            
+                          end // else: !if(mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 )
+                      
+
+                      Save_ALU_r <= #1 Save_ALU;
+                      ALU_Op_r <= #1 ALU_Op;
+                      
+                      if (I_CPL == 1'b1 ) 
+                        begin
+                          // CPL
+                          ACC <= #1 ~ ACC;
+                          F[Flag_Y] <= #1 ~ ACC[5];
+                          F[Flag_H] <= #1 1'b1;
+                          F[Flag_X] <= #1 ~ ACC[3];
+                          F[Flag_N] <= #1 1'b1;
+                        end
+                      if (I_CCF == 1'b1 ) 
+                        begin
+                          // CCF
+                          F[Flag_C] <= #1 ~ F[Flag_C];
+                          F[Flag_Y] <= #1 ACC[5];
+                          F[Flag_H] <= #1 F[Flag_C];
+                          F[Flag_X] <= #1 ACC[3];
+                          F[Flag_N] <= #1 1'b0;
+                        end
+                      if (I_SCF == 1'b1 ) 
+                        begin
+                          // SCF
+                          F[Flag_C] <= #1 1'b1;
+                          F[Flag_Y] <= #1 ACC[5];
+                          F[Flag_H] <= #1 1'b0;
+                          F[Flag_X] <= #1 ACC[3];
+                          F[Flag_N] <= #1 1'b0;
+                        end
+                    end // if (T_Res == 1'b1 )
+                  
+
+                  if (tstate[2] && wait_n == 1'b1 ) 
+                    begin
+                      if (ISet == 2'b01 && mcycle[6] ) 
+                        begin
+                          IR <= #1 dinst;
+                        end
+                      if (JumpE == 1'b1 ) 
+                        begin
+                          PC <= #1 PC16;
+                        end 
+                      else if (Inc_PC == 1'b1 ) 
+                        begin
+                          //PC <= #1 PC + 1;
+                          PC <= #1 PC16;
+                        end
+                      if (BTR_r == 1'b1 ) 
+                        begin
+                          //PC <= #1 PC - 2;
+                          PC <= #1 PC16;
+                        end
+                      if (RstP == 1'b1 ) 
+                        begin
+                          TmpAddr <= #1 { 10'h0, IR[5:3], 3'h0 };
+                          //TmpAddr <= #1 (others =>1'b0);
+                          //TmpAddr[5:3] <= #1 IR[5:3];
+                        end
+                    end
+                  if (tstate[3] && mcycle[5] ) 
+                    begin
+                      TmpAddr <= #1 SP16;
+                    end
+
+                  if ((tstate[2] && wait_n == 1'b1) || (tstate[4] && mcycle[0]) ) 
+                    begin
+                      if (IncDec_16[2:0] == 3'b111 ) 
+                        begin
+                          SP <= #1 SP16;
+                        end
+                    end
+
+                  if (LDSPHL == 1'b1 ) 
+                    begin
+                      SP <= #1 RegBusC;
+                    end
+                  if (ExchangeAF == 1'b1 ) 
+                    begin
+                      Ap <= #1 ACC;
+                      ACC <= #1 Ap;
+                      Fp <= #1 F;
+                      F <= #1 Fp;
+                    end
+                  if (ExchangeRS == 1'b1 ) 
+                    begin
+                      Alternate <= #1 ~ Alternate;
+                    end
+                end // else: !if(mcycle  == 3'b001 && tstate(2) == 1'b0 )
+              
+
+              if (tstate[3] ) 
+                begin
+                  if (LDZ == 1'b1 ) 
+                    begin
+                      TmpAddr[7:0] <= #1 DI_Reg;
+                    end
+                  if (LDW == 1'b1 ) 
+                    begin
+                      TmpAddr[15:8] <= #1 DI_Reg;
+                    end
+
+                  if (Special_LD[2] == 1'b1 ) 
+                    begin
+                      case (Special_LD[1:0])
+                        2'b00 :
+                          begin
+                            ACC <= #1 I;
+                            F[Flag_P] <= #1 IntE_FF2;
+			    F[Flag_Z] <= (I == 0);
+			    F[Flag_S] <= I[7];
+			    F[Flag_H] <= 0;
+			    F[Flag_N] <= 0; 
+                          end
+                        
+                        2'b01 :
+                          begin
+                            `ifdef TV80_REFRESH
+                            ACC <= #1 R;
+                            `else
+                            ACC <= #1 0;
+                            `endif
+                            F[Flag_P] <= #1 IntE_FF2;
+			    F[Flag_Z] <= (I == 0);
+			    F[Flag_S] <= I[7];
+			    F[Flag_H] <= 0;
+			    F[Flag_N] <= 0; 
+                          end
+                        
+                        2'b10 :
+                          I <= #1 ACC;
+
+                        `ifdef TV80_REFRESH                        
+                        default :
+                          R <= #1 ACC;
+                        `else
+                        default : ;
+                        `endif                        
+                      endcase
+                    end
+                end // if (tstate == 3 )
+              
+
+              if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 ) 
+                begin
+                  if (Mode == 3 ) 
+                    begin
+                      F[6] <= #1 F_Out[6];
+                      F[5] <= #1 F_Out[5];
+                      F[7] <= #1 F_Out[7];
+                      if (PreserveC_r == 1'b0 ) 
+                        begin
+                          F[4] <= #1 F_Out[4];
+                        end
+                    end 
+                  else 
+                    begin
+                      F[7:1] <= #1 F_Out[7:1];
+                      if (PreserveC_r == 1'b0 ) 
+                        begin
+                          F[Flag_C] <= #1 F_Out[0];
+                        end
+                    end
+                end // if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 )
+              
+              if (T_Res == 1'b1 && I_INRC == 1'b1 ) 
+                begin
+                  F[Flag_H] <= #1 1'b0;
+                  F[Flag_N] <= #1 1'b0;
+                  if (DI_Reg[7:0] == 8'b00000000 ) 
+                    begin
+                      F[Flag_Z] <= #1 1'b1;
+                    end 
+                  else 
+                    begin
+                      F[Flag_Z] <= #1 1'b0;
+                    end
+                  F[Flag_S] <= #1 DI_Reg[7];
+                  F[Flag_P] <= #1 ~ (^DI_Reg[7:0]);
+                end // if (T_Res == 1'b1 && I_INRC == 1'b1 )
+              
+
+              if (tstate[1] && Auto_Wait_t1 == 1'b0 ) 
+                begin
+                  dout <= #1 BusB;
+                  if (I_RLD == 1'b1 ) 
+                    begin
+                      dout[3:0] <= #1 BusA[3:0];
+                      dout[7:4] <= #1 BusB[3:0];
+                    end
+                  if (I_RRD == 1'b1 ) 
+                    begin
+                      dout[3:0] <= #1 BusB[7:4];
+                      dout[7:4] <= #1 BusA[3:0];
+                    end
+                end
+
+              if (T_Res == 1'b1 ) 
+                begin
+                  Read_To_Reg_r[3:0] <= #1 Set_BusA_To;
+                  Read_To_Reg_r[4] <= #1 Read_To_Reg;
+                  if (Read_To_Acc == 1'b1 ) 
+                    begin
+                      Read_To_Reg_r[3:0] <= #1 4'b0111;
+                      Read_To_Reg_r[4] <= #1 1'b1;
+                    end
+                end
+
+              if (tstate[1] && I_BT == 1'b1 ) 
+                begin
+                  F[Flag_X] <= #1 ALU_Q[3];
+                  F[Flag_Y] <= #1 ALU_Q[1];
+                  F[Flag_H] <= #1 1'b0;
+                  F[Flag_N] <= #1 1'b0;
+                end
+              if (I_BC == 1'b1 || I_BT == 1'b1 ) 
+                begin
+                  F[Flag_P] <= #1 IncDecZ;
+                end
+
+              if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||
+                  (Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) ) 
+                begin
+                  case (Read_To_Reg_r)
+                    5'b10111 :
+                      ACC <= #1 Save_Mux;
+                    5'b10110 :
+                      dout <= #1 Save_Mux;
+                    5'b11000 :
+                      SP[7:0] <= #1 Save_Mux;
+                    5'b11001 :
+                      SP[15:8] <= #1 Save_Mux;
+                    5'b11011 :
+                      F <= #1 Save_Mux;
+                    default : ;
+                  endcase
+                end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...              
+            end // if (ClkEn == 1'b1 )         
+        end // else: !if(reset_n == 1'b0 )
+    end
+  
+
+  //-------------------------------------------------------------------------
+  //
+  // BC('), DE('), HL('), IX && IY
+  //
+  //-------------------------------------------------------------------------
+  always @ (posedge clk)
+    begin
+      if (ClkEn == 1'b1 ) 
+        begin
+          // Bus A / Write
+          RegAddrA_r <= #1  { Alternate, Set_BusA_To[2:1] };
+          if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusA_To[2:1] == 2'b10 ) 
+            begin
+              RegAddrA_r <= #1 { XY_State[1],  2'b11 };
+            end
+
+          // Bus B
+          RegAddrB_r <= #1 { Alternate, Set_BusB_To[2:1] };
+          if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusB_To[2:1] == 2'b10 ) 
+            begin
+              RegAddrB_r <= #1 { XY_State[1],  2'b11 };
+            end
+
+          // Address from register
+          RegAddrC <= #1 { Alternate,  Set_Addr_To[1:0] };
+          // Jump (HL), LD SP,HL
+          if ((JumpXY == 1'b1 || LDSPHL == 1'b1) ) 
+            begin
+              RegAddrC <= #1 { Alternate, 2'b10 };
+            end
+          if (((JumpXY == 1'b1 || LDSPHL == 1'b1) && XY_State != 2'b00) || (mcycle[5]) ) 
+            begin
+              RegAddrC <= #1 { XY_State[1],  2'b11 };
+            end
+
+          if (I_DJNZ == 1'b1 && Save_ALU_r == 1'b1 && Mode < 2 ) 
+            begin
+              IncDecZ <= #1 F_Out[Flag_Z];
+            end
+          if ((tstate[2] || (tstate[3] && mcycle[0])) && IncDec_16[2:0] == 3'b100 ) 
+            begin
+              if (ID16 == 0 ) 
+                begin
+                  IncDecZ <= #1 1'b0;
+                end 
+              else 
+                begin
+                  IncDecZ <= #1 1'b1;
+                end
+            end
+          
+          RegBusA_r <= #1 RegBusA;
+        end
+      
+    end // always @ (posedge clk)
+  
+
+  always @(/*AUTOSENSE*/Alternate or ExchangeDH or IncDec_16
+	   or RegAddrA_r or RegAddrB_r or XY_State or mcycle or tstate)
+    begin
+      if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && XY_State == 2'b00)
+        RegAddrA = { Alternate, IncDec_16[1:0] };
+      else if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && IncDec_16[1:0] == 2'b10)
+        RegAddrA = { XY_State[1], 2'b11 };
+      else if (ExchangeDH == 1'b1 && tstate[3])
+        RegAddrA = { Alternate, 2'b10 };
+      else if (ExchangeDH == 1'b1 && tstate[4])
+        RegAddrA = { Alternate, 2'b01 };
+      else
+        RegAddrA = RegAddrA_r;
+      
+      if (ExchangeDH == 1'b1 && tstate[3])
+        RegAddrB = { Alternate, 2'b01 };
+      else
+        RegAddrB = RegAddrB_r;
+    end // always @ *
+  
+
+  always @(/*AUTOSENSE*/ALU_Op_r or Auto_Wait_t1 or ExchangeDH
+	   or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle
+	   or tstate or wait_n)
+    begin
+      RegWEH = 1'b0;
+      RegWEL = 1'b0;
+      if ((tstate[1] && ~Save_ALU_r && ~Auto_Wait_t1) ||
+          (Save_ALU_r && (ALU_Op_r != 4'b0111)) ) 
+        begin
+          case (Read_To_Reg_r)
+            5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 :
+              begin
+                RegWEH = ~ Read_To_Reg_r[0];
+                RegWEL = Read_To_Reg_r[0];
+              end // UNMATCHED !!
+            default : ;
+          endcase // case(Read_To_Reg_r)
+          
+        end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
+      
+
+      if (ExchangeDH && (tstate[3] || tstate[4]) ) 
+        begin
+          RegWEH = 1'b1;
+          RegWEL = 1'b1;
+        end
+
+      if (IncDec_16[2] && ((tstate[2] && wait_n && ~mcycle[0]) || (tstate[3] && mcycle[0])) ) 
+        begin
+          case (IncDec_16[1:0])
+            2'b00 , 2'b01 , 2'b10 :
+              begin
+                RegWEH = 1'b1;
+                RegWEL = 1'b1;
+              end // UNMATCHED !!
+            default : ;
+          endcase
+        end
+    end // always @ *
+  
+
+  always @(/*AUTOSENSE*/ExchangeDH or ID16 or IncDec_16 or RegBusA_r
+	   or RegBusB or Save_Mux or mcycle or tstate)
+    begin
+      RegDIH = Save_Mux;
+      RegDIL = Save_Mux;
+
+      if (ExchangeDH == 1'b1 && tstate[3] ) 
+        begin
+          RegDIH = RegBusB[15:8];
+          RegDIL = RegBusB[7:0];
+        end
+      else if (ExchangeDH == 1'b1 && tstate[4] ) 
+        begin
+          RegDIH = RegBusA_r[15:8];
+          RegDIL = RegBusA_r[7:0];
+        end
+      else if (IncDec_16[2] == 1'b1 && ((tstate[2] && ~mcycle[0]) || (tstate[3] && mcycle[0])) ) 
+        begin
+          RegDIH = ID16[15:8];
+          RegDIL = ID16[7:0];
+        end
+    end
+
+  tv80_reg i_reg
+    (
+     .clk                  (clk),
+     .CEN                  (ClkEn),
+     .WEH                  (RegWEH),
+     .WEL                  (RegWEL),
+     .AddrA                (RegAddrA),
+     .AddrB                (RegAddrB),
+     .AddrC                (RegAddrC),
+     .DIH                  (RegDIH),
+     .DIL                  (RegDIL),
+     .DOAH                 (RegBusA[15:8]),
+     .DOAL                 (RegBusA[7:0]),
+     .DOBH                 (RegBusB[15:8]),
+     .DOBL                 (RegBusB[7:0]),
+     .DOCH                 (RegBusC[15:8]),
+     .DOCL                 (RegBusC[7:0])
+     );
+
+  //-------------------------------------------------------------------------
+  //
+  // Buses
+  //
+  //-------------------------------------------------------------------------
+
+  always @ (posedge clk)
+    begin
+      if (ClkEn == 1'b1 ) 
+        begin
+          case (Set_BusB_To)
+            4'b0111 :
+              BusB <= #1 ACC;
+            4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
+              begin
+                if (Set_BusB_To[0] == 1'b1 ) 
+                  begin
+                    BusB <= #1 RegBusB[7:0];
+                  end 
+                else 
+                  begin
+                    BusB <= #1 RegBusB[15:8];
+                  end
+              end
+            4'b0110 :
+              BusB <= #1 DI_Reg;
+            4'b1000 :
+              BusB <= #1 SP[7:0];
+            4'b1001 :
+              BusB <= #1 SP[15:8];
+            4'b1010 :
+              BusB <= #1 8'b00000001;
+            4'b1011 :
+              BusB <= #1 F;
+            4'b1100 :
+              BusB <= #1 PC[7:0];
+            4'b1101 :
+              BusB <= #1 PC[15:8];
+            4'b1110 :
+              BusB <= #1 8'b00000000;
+            default :
+              BusB <= #1 8'h0;
+          endcase
+
+          case (Set_BusA_To)
+            4'b0111 :
+              BusA <= #1 ACC;
+            4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
+              begin
+                if (Set_BusA_To[0] == 1'b1 )
+                  begin
+                    BusA <= #1 RegBusA[7:0];
+                  end 
+                else 
+                  begin
+                    BusA <= #1 RegBusA[15:8];
+                  end
+              end
+            4'b0110 :
+              BusA <= #1 DI_Reg;
+            4'b1000 :
+              BusA <= #1 SP[7:0];
+            4'b1001 :
+              BusA <= #1 SP[15:8];
+            4'b1010 :
+              BusA <= #1 8'b00000000;
+            default :
+              BusA <= #1  8'h0;
+          endcase
+        end
+    end
+
+  //-------------------------------------------------------------------------
+  //
+  // Generate external control signals
+  //
+  //-------------------------------------------------------------------------
+`ifdef TV80_REFRESH
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 1'b0 ) 
+        begin
+          rfsh_n <= #1 1'b1;
+        end 
+      else
+        begin
+          if (cen == 1'b1 ) 
+            begin
+              if (mcycle[0] && ((tstate[2]  && wait_n == 1'b1) || tstate[3]) ) 
+                begin
+                  rfsh_n <= #1 1'b0;
+                end 
+              else 
+                begin
+                  rfsh_n <= #1 1'b1;
+                end
+            end
+        end
+    end // always @ (posedge clk or negedge reset_n)
+`else // !`ifdef TV80_REFRESH
+  assign rfsh_n = 1'b1;
+`endif  
+
+  always @(/*AUTOSENSE*/BusAck or Halt_FF or I_DJNZ or IntCycle
+	   or IntE_FF1 or di or iorq_i or mcycle or tstate)
+    begin
+      mc = mcycle;
+      ts = tstate;
+      DI_Reg = di;
+      halt_n = ~ Halt_FF;
+      busak_n = ~ BusAck;
+      intcycle_n = ~ IntCycle;
+      IntE = IntE_FF1;
+      iorq = iorq_i;
+      stop = I_DJNZ;
+    end
+
+  //-----------------------------------------------------------------------
+  //
+  // Syncronise inputs
+  //
+  //-----------------------------------------------------------------------
+
+  always @ (posedge clk or negedge reset_n)
+    begin : sync_inputs
+      if (~reset_n) 
+        begin
+          BusReq_s <= #1 1'b0;
+          INT_s <= #1 1'b0;
+          NMI_s <= #1 1'b0;
+          Oldnmi_n <= #1 1'b0;
+        end 
+      else
+        begin
+          if (cen == 1'b1 ) 
+            begin
+              BusReq_s <= #1 ~ busrq_n;
+              INT_s <= #1 ~ int_n;
+              if (NMICycle == 1'b1 ) 
+                begin
+                  NMI_s <= #1 1'b0;
+                end 
+              else if (nmi_n == 1'b0 && Oldnmi_n == 1'b1 ) 
+                begin
+                  NMI_s <= #1 1'b1;
+                end
+              Oldnmi_n <= #1 nmi_n;
+            end
+        end
+    end
+
+  //-----------------------------------------------------------------------
+  //
+  // Main state machine
+  //
+  //-----------------------------------------------------------------------
+
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 1'b0 ) 
+        begin
+          mcycle <= #1 7'b0000001;
+          tstate <= #1 7'b0000001;
+          Pre_XY_F_M <= #1 3'b000;
+          Halt_FF <= #1 1'b0;
+          BusAck <= #1 1'b0;
+          NMICycle <= #1 1'b0;
+          IntCycle <= #1 1'b0;
+          IntE_FF1 <= #1 1'b0;
+          IntE_FF2 <= #1 1'b0;
+          No_BTR <= #1 1'b0;
+          Auto_Wait_t1 <= #1 1'b0;
+          Auto_Wait_t2 <= #1 1'b0;
+          m1_n <= #1 1'b1;
+        end 
+      else
+        begin
+          if (cen == 1'b1 ) 
+            begin
+              if (T_Res == 1'b1 ) 
+                begin
+                  Auto_Wait_t1 <= #1 1'b0;
+                end 
+              else 
+                begin
+		  Auto_Wait_t1 <= #1 Auto_Wait || (iorq_i & ~Auto_Wait_t2);
+                end
+              Auto_Wait_t2 <= #1 Auto_Wait_t1 & !T_Res;
+              No_BTR <= #1 (I_BT && (~ IR[4] || ~ F[Flag_P])) ||
+                        (I_BC && (~ IR[4] || F[Flag_Z] || ~ F[Flag_P])) ||
+                        (I_BTR && (~ IR[4] || F[Flag_Z]));
+              if (tstate[2] ) 
+                begin
+                  if (SetEI == 1'b1 ) 
+                    begin
+                      if (!NMICycle)
+                        IntE_FF1 <= #1 1'b1;
+                      IntE_FF2 <= #1 1'b1;
+                    end
+                  if (I_RETN == 1'b1 ) 
+                    begin
+                      IntE_FF1 <= #1 IntE_FF2;
+                    end
+                end
+              if (tstate[3] ) 
+                begin
+                  if (SetDI == 1'b1 ) 
+                    begin
+                      IntE_FF1 <= #1 1'b0;
+                      IntE_FF2 <= #1 1'b0;
+                    end
+                end
+              if (IntCycle == 1'b1 || NMICycle == 1'b1 ) 
+                begin
+                  Halt_FF <= #1 1'b0;
+                end
+              if (mcycle[0] && tstate[2] && wait_n == 1'b1 ) 
+                begin
+                  m1_n <= #1 1'b1;
+                end
+              if (BusReq_s == 1'b1 && BusAck == 1'b1 ) 
+                begin
+                end 
+              else 
+                begin
+                  BusAck <= #1 1'b0;
+                  if (tstate[2] && wait_n == 1'b0 ) 
+                    begin
+                    end 
+                  else if (T_Res == 1'b1 ) 
+                    begin
+                      if (Halt == 1'b1 ) 
+                        begin
+                          Halt_FF <= #1 1'b1;
+                        end
+                      if (BusReq_s == 1'b1 ) 
+                        begin
+                          BusAck <= #1 1'b1;
+                        end 
+                      else 
+                        begin
+                          tstate <= #1 7'b0000010;
+                          if (NextIs_XY_Fetch == 1'b1 ) 
+                            begin
+                              mcycle <= #1 7'b0100000;
+                              Pre_XY_F_M <= #1 mcyc_to_number(mcycle);
+                              if (IR == 8'b00110110 && Mode == 0 ) 
+                                begin
+                                  Pre_XY_F_M <= #1 3'b010;
+                                end
+                            end 
+                          else if ((mcycle[6]) || (mcycle[5] && Mode == 1 && ISet != 2'b01) ) 
+                            begin
+                              mcycle <= #1 number_to_bitvec(Pre_XY_F_M + 1);
+                            end 
+                          else if ((last_mcycle) ||
+                                   No_BTR == 1'b1 ||
+                                   (mcycle[1] && I_DJNZ == 1'b1 && IncDecZ == 1'b1) ) 
+                            begin
+                              m1_n <= #1 1'b0;
+                              mcycle <= #1 7'b0000001;
+                              IntCycle <= #1 1'b0;
+                              NMICycle <= #1 1'b0;
+                              if (NMI_s == 1'b1 && Prefix == 2'b00 ) 
+                                begin
+                                  NMICycle <= #1 1'b1;
+                                  IntE_FF1 <= #1 1'b0;
+                                end 
+                              else if ((IntE_FF1 == 1'b1 && INT_s == 1'b1) && Prefix == 2'b00 && SetEI == 1'b0 ) 
+                                begin
+                                  IntCycle <= #1 1'b1;
+                                  IntE_FF1 <= #1 1'b0;
+                                  IntE_FF2 <= #1 1'b0;
+                                end
+                            end 
+                          else 
+                            begin
+                              mcycle <= #1 { mcycle[5:0], mcycle[6] };
+                            end
+                        end
+                    end 
+                  else 
+                    begin   // verilog has no "nor" operator
+                      if ( ~(Auto_Wait == 1'b1 && Auto_Wait_t2 == 1'b0) &&
+                           ~(IOWait == 1 && iorq_i == 1'b1 && Auto_Wait_t1 == 1'b0) ) 
+                        begin
+                          tstate <= #1 { tstate[5:0], tstate[6] };
+                        end
+                    end
+                end
+              if (tstate[0]) 
+                begin
+                  m1_n <= #1 1'b0;
+                end
+            end
+        end
+    end
+
+  always @(/*AUTOSENSE*/BTR_r or DI_Reg or IncDec_16 or JumpE or PC
+	   or RegBusA or RegBusC or SP or tstate)
+    begin
+      if (JumpE == 1'b1 ) 
+        begin
+          PC16_B = { {8{DI_Reg[7]}}, DI_Reg };
+        end 
+      else if (BTR_r == 1'b1 ) 
+        begin
+          PC16_B = -2;
+        end
+      else
+        begin
+          PC16_B = 1;
+        end
+
+      if (tstate[3])
+        begin
+          SP16_A = RegBusC;
+          SP16_B = { {8{DI_Reg[7]}}, DI_Reg };
+        end
+      else
+        begin
+          // suspect that ID16 and SP16 could be shared
+          SP16_A = SP;
+          
+          if (IncDec_16[3] == 1'b1)
+            SP16_B = -1;
+          else
+            SP16_B = 1;
+        end
+
+      if (IncDec_16[3])  
+        ID16_B = -1;
+      else
+        ID16_B = 1;
+
+      ID16 = RegBusA + ID16_B;
+      PC16 = PC + PC16_B;
+      SP16 = SP16_A + SP16_B;
+    end // always @ *
+  
+
+  always @(/*AUTOSENSE*/IntCycle or NMICycle or mcycle)
+    begin
+      Auto_Wait = 1'b0;
+      if (IntCycle == 1'b1 || NMICycle == 1'b1 ) 
+        begin
+          if (mcycle[0] ) 
+            begin
+              Auto_Wait = 1'b1;
+            end
+        end
+    end // always @ *
+  
+endmodule // T80
+
diff --git a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_mcode.v b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_mcode.v
new file mode 100644
index 00000000..40622d2b
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_mcode.v
@@ -0,0 +1,2650 @@
+//
+// TV80 8-Bit Microprocessor Core
+// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
+//
+// Copyright (c) 2004,2007 Guy Hutchison (ghutchis@opencores.org)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a 
+// copy of this software and associated documentation files (the "Software"), 
+// to deal in the Software without restriction, including without limitation 
+// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
+// and/or sell copies of the Software, and to permit persons to whom the 
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included 
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+module tv80_mcode 
+  (/*AUTOARG*/
+  // Outputs
+  MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg, 
+  Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC, 
+  Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ, 
+  LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF, 
+  ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR, 
+  I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write, 
+  // Inputs
+  IR, ISet, MCycle, F, NMICycle, IntCycle
+  );
+  
+  parameter             Mode   = 0;
+  parameter             Flag_C = 0;
+  parameter             Flag_N = 1;
+  parameter             Flag_P = 2;
+  parameter             Flag_X = 3;
+  parameter             Flag_H = 4;
+  parameter             Flag_Y = 5;
+  parameter             Flag_Z = 6;
+  parameter             Flag_S = 7;
+
+  input [7:0]           IR;
+  input [1:0]           ISet                    ;
+  input [6:0]           MCycle                  ;
+  input [7:0]           F                       ;
+  input                 NMICycle                ;
+  input                 IntCycle                ;
+  output [2:0]          MCycles                 ;
+  output [2:0]          TStates                 ;
+  output [1:0]          Prefix                  ; // None,BC,ED,DD/FD
+  output                Inc_PC                  ;
+  output                Inc_WZ                  ;
+  output [3:0]          IncDec_16               ; // BC,DE,HL,SP   0 is inc
+  output                Read_To_Reg             ;
+  output                Read_To_Acc             ;
+  output [3:0]          Set_BusA_To     ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+  output [3:0]          Set_BusB_To     ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+  output [3:0]          ALU_Op                  ;
+  output                Save_ALU                ;
+  output                PreserveC               ;
+  output                Arith16                 ;
+  output [2:0]          Set_Addr_To             ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+  output                IORQ                    ;
+  output                Jump                    ;
+  output                JumpE                   ;
+  output                JumpXY                  ;
+  output                Call                    ;
+  output                RstP                    ;
+  output                LDZ                     ;
+  output                LDW                     ;
+  output                LDSPHL                  ;
+  output [2:0]          Special_LD              ; // A,I;A,R;I,A;R,A;None
+  output                ExchangeDH              ;
+  output                ExchangeRp              ;
+  output                ExchangeAF              ;
+  output                ExchangeRS              ;
+  output                I_DJNZ                  ;
+  output                I_CPL                   ;
+  output                I_CCF                   ;
+  output                I_SCF                   ;
+  output                I_RETN                  ;
+  output                I_BT                    ;
+  output                I_BC                    ;
+  output                I_BTR                   ;
+  output                I_RLD                   ;
+  output                I_RRD                   ;
+  output                I_INRC                  ;
+  output                SetDI                   ;
+  output                SetEI                   ;
+  output [1:0]          IMode                   ;
+  output                Halt                    ;
+  output                NoRead                  ;
+  output                Write   ;                
+
+  // regs
+  reg [2:0]             MCycles                 ;
+  reg [2:0]             TStates                 ;
+  reg [1:0]             Prefix                  ; // None,BC,ED,DD/FD
+  reg                   Inc_PC                  ;
+  reg                   Inc_WZ                  ;
+  reg [3:0]             IncDec_16               ; // BC,DE,HL,SP   0 is inc
+  reg                   Read_To_Reg             ;
+  reg                   Read_To_Acc             ;
+  reg [3:0]             Set_BusA_To     ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+  reg [3:0]             Set_BusB_To     ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+  reg [3:0]             ALU_Op                  ;
+  reg                   Save_ALU                ;
+  reg                   PreserveC               ;
+  reg                   Arith16                 ;
+  reg [2:0]             Set_Addr_To             ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+  reg                   IORQ                    ;
+  reg                   Jump                    ;
+  reg                   JumpE                   ;
+  reg                   JumpXY                  ;
+  reg                   Call                    ;
+  reg                   RstP                    ;
+  reg                   LDZ                     ;
+  reg                   LDW                     ;
+  reg                   LDSPHL                  ;
+  reg [2:0]             Special_LD              ; // A,I;A,R;I,A;R,A;None
+  reg                   ExchangeDH              ;
+  reg                   ExchangeRp              ;
+  reg                   ExchangeAF              ;
+  reg                   ExchangeRS              ;
+  reg                   I_DJNZ                  ;
+  reg                   I_CPL                   ;
+  reg                   I_CCF                   ;
+  reg                   I_SCF                   ;
+  reg                   I_RETN                  ;
+  reg                   I_BT                    ;
+  reg                   I_BC                    ;
+  reg                   I_BTR                   ;
+  reg                   I_RLD                   ;
+  reg                   I_RRD                   ;
+  reg                   I_INRC                  ;
+  reg                   SetDI                   ;
+  reg                   SetEI                   ;
+  reg [1:0]             IMode                   ;
+  reg                   Halt                    ;
+  reg                   NoRead                  ;
+  reg                   Write   ;                
+
+  parameter             aNone   = 3'b111;
+  parameter             aBC     = 3'b000;
+  parameter             aDE     = 3'b001;
+  parameter             aXY     = 3'b010;
+  parameter             aIOA    = 3'b100;
+  parameter             aSP     = 3'b101;
+  parameter             aZI     = 3'b110;
+  //    constant aNone  : std_logic_vector[2:0] = 3'b000;
+  //    constant aXY    : std_logic_vector[2:0] = 3'b001;
+  //    constant aIOA   : std_logic_vector[2:0] = 3'b010;
+  //    constant aSP    : std_logic_vector[2:0] = 3'b011;
+  //    constant aBC    : std_logic_vector[2:0] = 3'b100;
+  //    constant aDE    : std_logic_vector[2:0] = 3'b101;
+  //    constant aZI    : std_logic_vector[2:0] = 3'b110;
+
+  function is_cc_true;
+    input [7:0] FF;
+    input [2:0] cc;
+    begin
+      if (Mode == 3 ) 
+        begin
+          case (cc)
+            3'b000  : is_cc_true = FF[7] == 1'b0; // NZ
+            3'b001  : is_cc_true = FF[7] == 1'b1; // Z
+            3'b010  : is_cc_true = FF[4] == 1'b0; // NC
+            3'b011  : is_cc_true = FF[4] == 1'b1; // C
+            3'b100  : is_cc_true = 0;
+            3'b101  : is_cc_true = 0;
+            3'b110  : is_cc_true = 0;
+            3'b111  : is_cc_true = 0;
+          endcase
+        end 
+      else 
+        begin
+          case (cc)
+            3'b000  : is_cc_true = FF[6] == 1'b0; // NZ
+            3'b001  : is_cc_true = FF[6] == 1'b1; // Z
+            3'b010  : is_cc_true = FF[0] == 1'b0; // NC
+            3'b011  : is_cc_true = FF[0] == 1'b1; // C
+            3'b100  : is_cc_true = FF[2] == 1'b0; // PO
+            3'b101  : is_cc_true = FF[2] == 1'b1; // PE
+            3'b110  : is_cc_true = FF[7] == 1'b0; // P
+            3'b111  : is_cc_true = FF[7] == 1'b1; // M
+          endcase
+        end
+    end
+  endfunction // is_cc_true
+  
+
+  reg [2:0] DDD;
+  reg [2:0] SSS;
+  reg [1:0] DPAIR;
+  
+  always @ (/*AUTOSENSE*/F or IR or ISet or IntCycle or MCycle
+            or NMICycle)
+    begin
+      DDD = IR[5:3];
+      SSS = IR[2:0];
+      DPAIR = IR[5:4];
+
+      MCycles = 3'b001;
+      if (MCycle[0] ) 
+        begin
+          TStates = 3'b100;
+        end 
+      else 
+        begin
+          TStates = 3'b011;
+        end
+      Prefix = 2'b00;
+      Inc_PC = 1'b0;
+      Inc_WZ = 1'b0;
+      IncDec_16 = 4'b0000;
+      Read_To_Acc = 1'b0;
+      Read_To_Reg = 1'b0;
+      Set_BusB_To = 4'b0000;
+      Set_BusA_To = 4'b0000;
+      ALU_Op = { 1'b0, IR[5:3] };
+      Save_ALU = 1'b0;
+      PreserveC = 1'b0;
+      Arith16 = 1'b0;
+      IORQ = 1'b0;
+      Set_Addr_To = aNone;
+      Jump = 1'b0;
+      JumpE = 1'b0;
+      JumpXY = 1'b0;
+      Call = 1'b0;
+      RstP = 1'b0;
+      LDZ = 1'b0;
+      LDW = 1'b0;
+      LDSPHL = 1'b0;
+      Special_LD = 3'b000;
+      ExchangeDH = 1'b0;
+      ExchangeRp = 1'b0;
+      ExchangeAF = 1'b0;
+      ExchangeRS = 1'b0;
+      I_DJNZ = 1'b0;
+      I_CPL = 1'b0;
+      I_CCF = 1'b0;
+      I_SCF = 1'b0;
+      I_RETN = 1'b0;
+      I_BT = 1'b0;
+      I_BC = 1'b0;
+      I_BTR = 1'b0;
+      I_RLD = 1'b0;
+      I_RRD = 1'b0;
+      I_INRC = 1'b0;
+      SetDI = 1'b0;
+      SetEI = 1'b0;
+      IMode = 2'b11;
+      Halt = 1'b0;
+      NoRead = 1'b0;
+      Write = 1'b0;
+      
+      case (ISet)
+        2'b00  :
+          begin
+
+            //----------------------------------------------------------------------------
+            //
+            //  Unprefixed instructions
+            //
+            //----------------------------------------------------------------------------
+
+            casez (IR)
+              // 8 BIT LOAD GROUP
+              8'b01zzzzzz :
+                begin
+                  if (IR[5:0] == 6'b110110)
+                    Halt = 1'b1;
+                  else if (IR[2:0] == 3'b110)
+                    begin
+                      // LD r,(HL)
+                      MCycles = 3'b010;
+                      if (MCycle[0])
+                        Set_Addr_To = aXY;
+                      if (MCycle[1])
+                        begin
+                          Set_BusA_To[2:0] = DDD;
+                          Read_To_Reg = 1'b1;
+                        end
+                    end // if (IR[2:0] == 3'b110)
+                  else if (IR[5:3] == 3'b110)
+                    begin
+                      // LD (HL),r
+                      MCycles = 3'b010;
+                      if (MCycle[0])
+                        begin
+                          Set_Addr_To = aXY;
+                          Set_BusB_To[2:0] = SSS;
+                          Set_BusB_To[3] = 1'b0;
+                        end
+                      if (MCycle[1])
+                        Write = 1'b1;
+                    end // if (IR[5:3] == 3'b110)
+                  else
+                    begin
+                      Set_BusB_To[2:0] = SSS;
+                      ExchangeRp = 1'b1;
+                      Set_BusA_To[2:0] = DDD;
+                      Read_To_Reg = 1'b1;
+                    end // else: !if(IR[5:3] == 3'b110)
+                end // case: 8'b01zzzzzz                                    
+
+              8'b00zzz110 :
+                begin
+                  if (IR[5:3] == 3'b110)
+                    begin
+                      // LD (HL),n
+                      MCycles = 3'b011;
+                      if (MCycle[1])
+                        begin
+                          Inc_PC = 1'b1;
+                          Set_Addr_To = aXY;
+                          Set_BusB_To[2:0] = SSS;
+                          Set_BusB_To[3] = 1'b0;
+                        end
+                      if (MCycle[2])
+                        Write = 1'b1;
+                    end // if (IR[5:3] == 3'b110)
+                  else
+                    begin
+                      // LD r,n
+                      MCycles = 3'b010;
+                      if (MCycle[1])
+                        begin
+                          Inc_PC = 1'b1;
+                          Set_BusA_To[2:0] = DDD;
+                          Read_To_Reg = 1'b1;
+                        end
+                    end
+                end
+              
+              8'b00001010  :
+                begin
+                  // LD A,(BC)
+                  MCycles = 3'b010;
+                  if (MCycle[0])
+                    Set_Addr_To = aBC;
+                  if (MCycle[1])
+                    Read_To_Acc = 1'b1;
+                end // case: 8'b00001010
+              
+              8'b00011010  :
+                begin
+                  // LD A,(DE)
+                  MCycles = 3'b010;
+                  if (MCycle[0])
+                    Set_Addr_To = aDE;
+                  if (MCycle[1])
+                    Read_To_Acc = 1'b1;
+                end // case: 8'b00011010
+              
+              8'b00111010  :
+                begin
+                  if (Mode == 3 ) 
+                    begin
+                      // LDD A,(HL)
+                      MCycles = 3'b010;
+                      if (MCycle[0])
+                        Set_Addr_To = aXY;
+                      if (MCycle[1])
+                        begin
+                          Read_To_Acc = 1'b1;
+                          IncDec_16 = 4'b1110;
+                        end
+                    end 
+                  else 
+                    begin
+                      // LD A,(nn)
+                      MCycles = 3'b100;
+                      if (MCycle[1])
+                        begin
+                          Inc_PC = 1'b1;
+                          LDZ = 1'b1;
+                        end
+                      if (MCycle[2])
+                        begin
+                          Set_Addr_To = aZI;
+                          Inc_PC = 1'b1;
+                        end
+                      if (MCycle[3])
+                        begin
+                          Read_To_Acc = 1'b1;
+                        end
+                    end // else: !if(Mode == 3 )
+                end // case: 8'b00111010
+              
+              8'b00000010  :
+                begin
+                  // LD (BC),A
+                  MCycles = 3'b010;
+                  if (MCycle[0])
+                    begin
+                      Set_Addr_To = aBC;
+                      Set_BusB_To = 4'b0111;
+                    end
+                  if (MCycle[1])
+                    begin
+                      Write = 1'b1;
+                    end
+                end // case: 8'b00000010
+              
+              8'b00010010  :
+                begin
+                  // LD (DE),A
+                  MCycles = 3'b010;
+                  case (1'b1) // MCycle
+                    MCycle[0] :
+                      begin
+                        Set_Addr_To = aDE;
+                        Set_BusB_To = 4'b0111;
+                      end
+                    MCycle[1] :
+                      Write = 1'b1;
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b00010010
+              
+              8'b00110010  :
+                begin
+                  if (Mode == 3 ) 
+                    begin
+                      // LDD (HL),A
+                      MCycles = 3'b010;
+                      case (1'b1) // MCycle
+                        MCycle[0] :
+                          begin
+                            Set_Addr_To = aXY;
+                            Set_BusB_To = 4'b0111;
+                          end
+                        MCycle[1] :
+                          begin
+                            Write = 1'b1;
+                            IncDec_16 = 4'b1110;
+                          end
+                        default :;
+                      endcase // case(MCycle)
+                      
+                    end 
+                  else 
+                    begin
+                      // LD (nn),A
+                      MCycles = 3'b100;
+                      case (1'b1) // MCycle
+                        MCycle[1] :
+                          begin
+                            Inc_PC = 1'b1;
+                            LDZ = 1'b1;
+                          end
+                        MCycle[2] :
+                          begin
+                            Set_Addr_To = aZI;
+                            Inc_PC = 1'b1;
+                            Set_BusB_To = 4'b0111;
+                          end
+                        MCycle[3] :
+                          begin
+                            Write = 1'b1;
+                          end
+                        default :;
+                      endcase
+                    end // else: !if(Mode == 3 )
+                end // case: 8'b00110010
+              
+
+              // 16 BIT LOAD GROUP
+              8'b00000001,8'b00010001,8'b00100001,8'b00110001  :
+                begin
+                  // LD dd,nn
+                  MCycles = 3'b011;
+                  case (1'b1) // MCycle
+                    MCycle[1] :
+                      begin
+                        Inc_PC = 1'b1;
+                        Read_To_Reg = 1'b1;
+                        if (DPAIR == 2'b11 ) 
+                          begin
+                            Set_BusA_To[3:0] = 4'b1000;
+                          end 
+                        else 
+                          begin
+                            Set_BusA_To[2:1] = DPAIR;
+                            Set_BusA_To[0] = 1'b1;
+                          end
+                      end // case: 2
+                    
+                    MCycle[2] :
+                      begin
+                        Inc_PC = 1'b1;
+                        Read_To_Reg = 1'b1;
+                        if (DPAIR == 2'b11 ) 
+                          begin
+                            Set_BusA_To[3:0] = 4'b1001;
+                          end 
+                        else 
+                          begin
+                            Set_BusA_To[2:1] = DPAIR;
+                            Set_BusA_To[0] = 1'b0;
+                          end
+                      end // case: 3
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b00000001,8'b00010001,8'b00100001,8'b00110001
+              
+              8'b00101010  :
+                begin
+                  if (Mode == 3 ) 
+                    begin
+                      // LDI A,(HL)
+                      MCycles = 3'b010;
+                      case (1'b1) // MCycle
+                        MCycle[0] :
+                          Set_Addr_To = aXY;
+                        MCycle[1] :
+                          begin
+                            Read_To_Acc = 1'b1;
+                            IncDec_16 = 4'b0110;
+                          end
+                        
+                        default :;
+                      endcase
+                    end 
+                  else 
+                    begin
+                      // LD HL,(nn)
+                      MCycles = 3'b101;
+                      case (1'b1) // MCycle
+                        MCycle[1] :
+                          begin
+                            Inc_PC = 1'b1;
+                            LDZ = 1'b1;
+                          end
+                        MCycle[2] :
+                          begin
+                            Set_Addr_To = aZI;
+                            Inc_PC = 1'b1;
+                            LDW = 1'b1;
+                          end
+                        MCycle[3] :
+                          begin
+                            Set_BusA_To[2:0] = 3'b101; // L
+                            Read_To_Reg = 1'b1;
+                            Inc_WZ = 1'b1;
+                            Set_Addr_To = aZI;
+                          end
+                        MCycle[4] :
+                          begin
+                            Set_BusA_To[2:0] = 3'b100; // H
+                            Read_To_Reg = 1'b1;
+                          end
+                        default :;
+                      endcase
+                    end // else: !if(Mode == 3 )
+                end // case: 8'b00101010
+              
+              8'b00100010  :
+                begin
+                  if (Mode == 3 ) 
+                    begin
+                      // LDI (HL),A
+                      MCycles = 3'b010;
+                      case (1'b1) // MCycle
+                        MCycle[0] :
+                          begin
+                            Set_Addr_To = aXY;
+                            Set_BusB_To = 4'b0111;
+                          end
+                        MCycle[1] :
+                          begin
+                            Write = 1'b1;
+                            IncDec_16 = 4'b0110;
+                          end
+                        default :;
+                      endcase
+                    end 
+                  else 
+                    begin
+                      // LD (nn),HL
+                      MCycles = 3'b101;
+                      case (1'b1) // MCycle                        
+                        MCycle[1] :
+                          begin
+                            Inc_PC = 1'b1;
+                            LDZ = 1'b1;
+                          end
+                        
+                        MCycle[2] :
+                          begin
+                            Set_Addr_To = aZI;
+                            Inc_PC = 1'b1;
+                            LDW = 1'b1;
+                            Set_BusB_To = 4'b0101; // L
+                          end
+                        
+                        MCycle[3] :
+                          begin
+                            Inc_WZ = 1'b1;
+                            Set_Addr_To = aZI;
+                            Write = 1'b1;
+                            Set_BusB_To = 4'b0100; // H
+                          end
+                        MCycle[4] :                          
+                          Write = 1'b1;
+                        default :;
+                      endcase
+                    end // else: !if(Mode == 3 )
+                end // case: 8'b00100010
+              
+              8'b11111001  :
+                begin
+                  // LD SP,HL
+                  TStates = 3'b110;
+                  LDSPHL = 1'b1;
+                end
+              
+              8'b11zz0101 :
+                begin
+                  // PUSH qq
+                  MCycles = 3'b011;
+                  case (1'b1) // MCycle                    
+                    MCycle[0] :
+                      begin
+                        TStates = 3'b101;
+                        IncDec_16 = 4'b1111;
+                        Set_Addr_To = aSP;
+                        if (DPAIR == 2'b11 ) 
+                          begin
+                            Set_BusB_To = 4'b0111;
+                          end 
+                        else
+                          begin
+                            Set_BusB_To[2:1] = DPAIR;
+                            Set_BusB_To[0] = 1'b0;
+                            Set_BusB_To[3] = 1'b0;
+                          end
+                      end // case: 1
+                    
+                    MCycle[1] :
+                      begin
+                        IncDec_16 = 4'b1111;
+                        Set_Addr_To = aSP;
+                        if (DPAIR == 2'b11 ) 
+                          begin
+                            Set_BusB_To = 4'b1011;
+                          end 
+                        else 
+                          begin
+                            Set_BusB_To[2:1] = DPAIR;
+                            Set_BusB_To[0] = 1'b1;
+                            Set_BusB_To[3] = 1'b0;
+                          end
+                        Write = 1'b1;
+                      end // case: 2
+                    
+                    MCycle[2] :
+                      Write = 1'b1;
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101
+              
+              8'b11zz0001 :
+                begin
+                  // POP qq
+                  MCycles = 3'b011;
+                  case (1'b1) // MCycle
+                    MCycle[0] :
+                      Set_Addr_To = aSP;
+                    MCycle[1] :
+                      begin
+                        IncDec_16 = 4'b0111;
+                        Set_Addr_To = aSP;
+                        Read_To_Reg = 1'b1;
+                        if (DPAIR == 2'b11 ) 
+                          begin
+                            Set_BusA_To[3:0] = 4'b1011;
+                          end 
+                        else 
+                          begin
+                            Set_BusA_To[2:1] = DPAIR;
+                            Set_BusA_To[0] = 1'b1;
+                          end
+                      end // case: 2
+                    
+                    MCycle[2] :
+                      begin
+                        IncDec_16 = 4'b0111;
+                        Read_To_Reg = 1'b1;
+                        if (DPAIR == 2'b11 ) 
+                          begin
+                            Set_BusA_To[3:0] = 4'b0111;
+                          end 
+                        else 
+                          begin
+                            Set_BusA_To[2:1] = DPAIR;
+                            Set_BusA_To[0] = 1'b0;
+                          end
+                      end // case: 3
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b11000001,8'b11010001,8'b11100001,8'b11110001
+              
+
+              // EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+              8'b11101011  :
+                begin
+                  if (Mode != 3 ) 
+                    begin
+                      // EX DE,HL
+                      ExchangeDH = 1'b1;
+                    end
+                end
+              
+              8'b00001000  :
+                begin
+                  if (Mode == 3 ) 
+                    begin
+                      // LD (nn),SP
+                      MCycles = 3'b101;
+                      case (1'b1) // MCycle
+                        MCycle[1] :
+                          begin
+                            Inc_PC = 1'b1;
+                            LDZ = 1'b1;
+                          end
+                        
+                        MCycle[2] :
+                          begin
+                            Set_Addr_To = aZI;
+                            Inc_PC = 1'b1;
+                            LDW = 1'b1;
+                            Set_BusB_To = 4'b1000;
+                          end
+                        
+                        MCycle[3] :
+                          begin
+                            Inc_WZ = 1'b1;
+                            Set_Addr_To = aZI;
+                            Write = 1'b1;
+                            Set_BusB_To = 4'b1001;
+                          end
+                        
+                        MCycle[4] :
+                          Write = 1'b1;
+                        default :;
+                      endcase
+                    end 
+                  else if (Mode < 2 ) 
+                    begin
+                      // EX AF,AF'
+                      ExchangeAF = 1'b1;
+                    end
+                end // case: 8'b00001000
+              
+              8'b11011001  :
+                begin
+                  if (Mode == 3 ) 
+                    begin
+                      // RETI
+                      MCycles = 3'b011;
+                      case (1'b1) // MCycle
+                        MCycle[0] :
+                          Set_Addr_To = aSP;
+                        MCycle[1] :
+                          begin
+                            IncDec_16 = 4'b0111;
+                            Set_Addr_To = aSP;
+                            LDZ = 1'b1;
+                          end
+                        
+                        MCycle[2] :
+                          begin
+                            Jump = 1'b1;
+                            IncDec_16 = 4'b0111;
+                            I_RETN = 1'b1;
+                            SetEI = 1'b1;
+                          end
+                        default :;
+                      endcase
+                    end 
+                  else if (Mode < 2 ) 
+                    begin
+                      // EXX
+                      ExchangeRS = 1'b1;
+                    end
+                end // case: 8'b11011001
+              
+              8'b11100011  :
+                begin
+                  if (Mode != 3 ) 
+                    begin
+                      // EX (SP),HL
+                      MCycles = 3'b101;
+                      case (1'b1) // MCycle
+                        MCycle[0] :
+                          Set_Addr_To = aSP;
+                        MCycle[1] :
+                          begin
+                            Read_To_Reg = 1'b1;
+                            Set_BusA_To = 4'b0101;
+                            Set_BusB_To = 4'b0101;
+                            Set_Addr_To = aSP;
+                          end
+                        MCycle[2] :
+                          begin
+                            IncDec_16 = 4'b0111;
+                            Set_Addr_To = aSP;
+                            TStates = 3'b100;
+                            Write = 1'b1;
+                          end
+                        MCycle[3] :
+                          begin
+                            Read_To_Reg = 1'b1;
+                            Set_BusA_To = 4'b0100;
+                            Set_BusB_To = 4'b0100;
+                            Set_Addr_To = aSP;
+                          end
+                        MCycle[4] :
+                          begin
+                            IncDec_16 = 4'b1111;
+                            TStates = 3'b101;
+                            Write = 1'b1;
+                          end
+                        
+                        default :;
+                      endcase
+                    end // if (Mode != 3 )
+                end // case: 8'b11100011
+              
+
+              // 8 BIT ARITHMETIC AND LOGICAL GROUP
+              8'b10zzzzzz :
+                begin
+                  if (IR[2:0] == 3'b110)
+                    begin
+                      // ADD A,(HL)
+                      // ADC A,(HL)
+                      // SUB A,(HL)
+                      // SBC A,(HL)
+                      // AND A,(HL)
+                      // OR A,(HL)
+                      // XOR A,(HL)
+                      // CP A,(HL)
+                      MCycles = 3'b010;
+                      case (1'b1) // MCycle
+                        MCycle[0] :
+                          Set_Addr_To = aXY;
+                        MCycle[1] :
+                          begin
+                            Read_To_Reg = 1'b1;
+                            Save_ALU = 1'b1;
+                            Set_BusB_To[2:0] = SSS;
+                            Set_BusA_To[2:0] = 3'b111;
+                          end
+                        
+                        default :;
+                      endcase // case(MCycle)
+                    end // if (IR[2:0] == 3'b110)
+                  else
+                    begin
+                      // ADD A,r
+                      // ADC A,r
+                      // SUB A,r
+                      // SBC A,r
+                      // AND A,r
+                      // OR A,r
+                      // XOR A,r
+                      // CP A,r
+                      Set_BusB_To[2:0] = SSS;
+                      Set_BusA_To[2:0] = 3'b111;
+                      Read_To_Reg = 1'b1;
+                      Save_ALU = 1'b1;
+                    end // else: !if(IR[2:0] == 3'b110)                  
+                end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
+              
+              8'b11zzz110 :
+                begin
+                  // ADD A,n
+                  // ADC A,n
+                  // SUB A,n
+                  // SBC A,n
+                  // AND A,n
+                  // OR A,n
+                  // XOR A,n
+                  // CP A,n
+                  MCycles = 3'b010;
+                  if (MCycle[1] ) 
+                    begin
+                      Inc_PC = 1'b1;
+                      Read_To_Reg = 1'b1;
+                      Save_ALU = 1'b1;
+                      Set_BusB_To[2:0] = SSS;
+                      Set_BusA_To[2:0] = 3'b111;
+                    end
+                end
+              
+              8'b00zzz100 :
+                begin
+                  if (IR[5:3] == 3'b110)
+                    begin
+                      // INC (HL)
+                      MCycles = 3'b011;
+                      case (1'b1) // MCycle
+                        MCycle[0] :
+                          Set_Addr_To = aXY;
+                        MCycle[1] :
+                          begin
+                            TStates = 3'b100;
+                            Set_Addr_To = aXY;
+                            Read_To_Reg = 1'b1;
+                            Save_ALU = 1'b1;
+                            PreserveC = 1'b1;
+                            ALU_Op = 4'b0000;
+                            Set_BusB_To = 4'b1010;
+                            Set_BusA_To[2:0] = DDD;
+                          end // case: 2
+                        
+                        MCycle[2] :
+                          Write = 1'b1;
+                        default :;
+                      endcase // case(MCycle)
+                    end // case: 8'b00110100
+                  else
+                    begin
+                      // INC r
+                      Set_BusB_To = 4'b1010;
+                      Set_BusA_To[2:0] = DDD;
+                      Read_To_Reg = 1'b1;
+                      Save_ALU = 1'b1;
+                      PreserveC = 1'b1;
+                      ALU_Op = 4'b0000;
+                    end
+                end
+              
+              8'b00zzz101 :
+                begin               
+                  if (IR[5:3] == 3'b110)
+                    begin
+                      // DEC (HL)
+                      MCycles = 3'b011;
+                      case (1'b1) // MCycle
+                        MCycle[0] :
+                          Set_Addr_To = aXY;
+                        MCycle[1] :
+                          begin
+                            TStates = 3'b100;
+                            Set_Addr_To = aXY;
+                            ALU_Op = 4'b0010;
+                            Read_To_Reg = 1'b1;
+                            Save_ALU = 1'b1;
+                            PreserveC = 1'b1;
+                            Set_BusB_To = 4'b1010;
+                            Set_BusA_To[2:0] = DDD;
+                          end // case: 2
+                        
+                        MCycle[2] :
+                          Write = 1'b1;
+                        default :;
+                      endcase // case(MCycle)
+                    end
+                  else
+                    begin
+                      // DEC r
+                      Set_BusB_To = 4'b1010;
+                      Set_BusA_To[2:0] = DDD;
+                      Read_To_Reg = 1'b1;
+                      Save_ALU = 1'b1;
+                      PreserveC = 1'b1;
+                      ALU_Op = 4'b0010;
+                    end
+                end
+              
+              // GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+              8'b00100111  :
+                begin
+                  // DAA
+                  Set_BusA_To[2:0] = 3'b111;
+                  Read_To_Reg = 1'b1;
+                  ALU_Op = 4'b1100;
+                  Save_ALU = 1'b1;
+                end
+              
+              8'b00101111  :
+                // CPL
+                I_CPL = 1'b1;
+              
+              8'b00111111  :
+                // CCF
+                I_CCF = 1'b1;
+              
+              8'b00110111  :
+                // SCF
+                I_SCF = 1'b1;
+              
+              8'b00000000  :
+                begin
+                  if (NMICycle == 1'b1 ) 
+                    begin
+                      // NMI
+                      MCycles = 3'b011;
+                      case (1'b1) // MCycle
+                        MCycle[0] :
+                          begin
+                            TStates = 3'b101;
+                            IncDec_16 = 4'b1111;
+                            Set_Addr_To = aSP;
+                            Set_BusB_To = 4'b1101;
+                          end
+                        
+                        MCycle[1] :
+                          begin
+                            TStates = 3'b100;
+                            Write = 1'b1;
+                            IncDec_16 = 4'b1111;
+                            Set_Addr_To = aSP;
+                            Set_BusB_To = 4'b1100;
+                          end
+                        
+                        MCycle[2] :
+                          begin
+                            TStates = 3'b100;
+                            Write = 1'b1;
+                          end
+                        
+                        default :;
+                      endcase // case(MCycle)
+                      
+                    end 
+                  else if (IntCycle == 1'b1 ) 
+                    begin
+                      // INT (IM 2)
+                      MCycles = 3'b101;
+                      case (1'b1) // MCycle
+                        MCycle[0] :
+                          begin
+                            LDZ = 1'b1;
+                            TStates = 3'b101;
+                            IncDec_16 = 4'b1111;
+                            Set_Addr_To = aSP;
+                            Set_BusB_To = 4'b1101;
+                          end
+                        
+                        MCycle[1] :
+                          begin
+                            TStates = 3'b100;
+                            Write = 1'b1;
+                            IncDec_16 = 4'b1111;
+                            Set_Addr_To = aSP;
+                            Set_BusB_To = 4'b1100;
+                          end
+                        
+                        MCycle[2] :
+                          begin
+                            TStates = 3'b100;
+                            Write = 1'b1;
+                          end
+                        
+                        MCycle[3] :
+                          begin
+                            Inc_PC = 1'b1;
+                            LDZ = 1'b1;
+                          end
+                        
+                        MCycle[4] :
+                          Jump = 1'b1;
+                        default :;
+                      endcase
+                    end
+                end // case: 8'b00000000
+              
+              8'b11110011  :
+                // DI
+                SetDI = 1'b1;
+              
+              8'b11111011  :
+                // EI
+                SetEI = 1'b1;
+
+              // 16 BIT ARITHMETIC GROUP
+              8'b00zz1001  :
+                begin
+                  // ADD HL,ss
+                  MCycles = 3'b011;
+                  case (1'b1) // MCycle
+                    MCycle[1] :
+                      begin
+                        NoRead = 1'b1;
+                        ALU_Op = 4'b0000;
+                        Read_To_Reg = 1'b1;
+                        Save_ALU = 1'b1;
+                        Set_BusA_To[2:0] = 3'b101;
+                        case (IR[5:4])
+                          0,1,2  :
+                            begin
+                              Set_BusB_To[2:1] = IR[5:4];
+                              Set_BusB_To[0] = 1'b1;
+                            end
+                          
+                          default :
+                            Set_BusB_To = 4'b1000;
+                        endcase // case(IR[5:4])
+                        
+                        TStates = 3'b100;
+                        Arith16 = 1'b1;
+                      end // case: 2
+                    
+                    MCycle[2] :
+                      begin
+                        NoRead = 1'b1;
+                        Read_To_Reg = 1'b1;
+                        Save_ALU = 1'b1;
+                        ALU_Op = 4'b0001;
+                        Set_BusA_To[2:0] = 3'b100;
+                        case (IR[5:4])
+                          0,1,2  :
+                            Set_BusB_To[2:1] = IR[5:4];
+                          default :
+                            Set_BusB_To = 4'b1001;
+                        endcase
+                        Arith16 = 1'b1;
+                      end // case: 3
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001              
+              
+              8'b00zz0011 :
+                begin
+                  // INC ss
+                  TStates = 3'b110;
+                  IncDec_16[3:2] = 2'b01;
+                  IncDec_16[1:0] = DPAIR;
+                end
+              
+              8'b00zz1011 :
+                begin
+                  // DEC ss
+                  TStates = 3'b110;
+                  IncDec_16[3:2] = 2'b11;
+                  IncDec_16[1:0] = DPAIR;
+                end
+
+              // ROTATE AND SHIFT GROUP
+              8'b00000111,
+                  // RLCA
+                  8'b00010111,
+                  // RLA
+                  8'b00001111,
+                  // RRCA
+                  8'b00011111 :
+                    // RRA
+                    begin
+                      Set_BusA_To[2:0] = 3'b111;
+                      ALU_Op = 4'b1000;
+                      Read_To_Reg = 1'b1;
+                      Save_ALU = 1'b1;
+                    end // case: 8'b00000111,...
+              
+
+              // JUMP GROUP
+              8'b11000011  :
+                begin
+                  // JP nn
+                  MCycles = 3'b011;
+                  if (MCycle[1])
+                    begin
+                      Inc_PC = 1'b1;
+                      LDZ = 1'b1;
+                    end
+                  
+                  if (MCycle[2])
+                    begin
+                      Inc_PC = 1'b1;
+                      Jump = 1'b1;
+                    end
+                  
+                end // case: 8'b11000011
+              
+              8'b11zzz010  :
+                begin
+                  if (IR[5] == 1'b1 && Mode == 3 ) 
+                    begin
+                      case (IR[4:3])
+                        2'b00  :
+                          begin
+                            // LD ($FF00+C),A
+                            MCycles = 3'b010;
+                            case (1'b1) // MCycle
+                              MCycle[0] :
+                                begin
+                                  Set_Addr_To = aBC;
+                                  Set_BusB_To   = 4'b0111;
+                                end
+                              MCycle[1] :
+                                begin
+                                  Write = 1'b1;
+                                  IORQ = 1'b1;
+                                end
+                              
+                              default :;
+                            endcase // case(MCycle)
+                          end // case: 2'b00
+                        
+                        2'b01  :
+                          begin
+                            // LD (nn),A
+                            MCycles = 3'b100;
+                            case (1'b1) // MCycle
+                              MCycle[1] :
+                                begin
+                                  Inc_PC = 1'b1;
+                                  LDZ = 1'b1;
+                                end
+                              
+                              MCycle[2] :
+                                begin
+                                  Set_Addr_To = aZI;
+                                  Inc_PC = 1'b1;
+                                  Set_BusB_To = 4'b0111;
+                                end
+                              
+                              MCycle[3] :
+                                Write = 1'b1;
+                              default :;
+                            endcase // case(MCycle)
+                          end // case: default :...
+                        
+                        2'b10  :
+                          begin
+                            // LD A,($FF00+C)
+                            MCycles = 3'b010;
+                            case (1'b1) // MCycle
+                              MCycle[0] :
+                                Set_Addr_To = aBC;
+                              MCycle[1] :
+                                begin
+                                  Read_To_Acc = 1'b1;
+                                  IORQ = 1'b1;
+                                end
+                              default :;
+                            endcase // case(MCycle)
+                          end // case: 2'b10
+                        
+                        2'b11  :
+                          begin
+                            // LD A,(nn)
+                            MCycles = 3'b100;
+                            case (1'b1) // MCycle
+                              MCycle[1] :
+                                begin
+                                  Inc_PC = 1'b1;
+                                  LDZ = 1'b1;
+                                end
+                              MCycle[2] :
+                                begin
+                                  Set_Addr_To = aZI;
+                                  Inc_PC = 1'b1;
+                                end
+                              MCycle[3] :
+                                Read_To_Acc = 1'b1;
+                              default :;
+                            endcase // case(MCycle)
+                          end
+                      endcase
+                    end 
+                  else 
+                    begin
+                      // JP cc,nn
+                      MCycles = 3'b011;
+                      case (1'b1) // MCycle
+                        MCycle[1] :
+                          begin
+                            Inc_PC = 1'b1;
+                            LDZ = 1'b1;
+                          end
+                        MCycle[2] :
+                          begin
+                            Inc_PC = 1'b1;
+                            if (is_cc_true(F, IR[5:3]) ) 
+                              begin
+                                Jump = 1'b1;
+                              end
+                          end
+                        
+                        default :;
+                      endcase
+                    end // else: !if(DPAIR == 2'b11 )
+                end // case: 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010
+              
+              8'b00011000  :
+                begin
+                  if (Mode != 2 ) 
+                    begin
+                      // JR e
+                      MCycles = 3'b011;
+                      case (1'b1) // MCycle
+                        MCycle[1] :
+                          Inc_PC = 1'b1;
+                        MCycle[2] :
+                          begin
+                            NoRead = 1'b1;
+                            JumpE = 1'b1;
+                            TStates = 3'b101;
+                          end
+                        default :;
+                      endcase
+                    end // if (Mode != 2 )
+                end // case: 8'b00011000
+
+              // Conditional relative jumps (JR [C/NC/Z/NZ], e)
+              8'b001zz000  :
+                begin
+                  if (Mode != 2 ) 
+                    begin
+                      MCycles = 3'd3;
+                      case (1'b1) // MCycle
+                        MCycle[1] :
+                          begin
+                            Inc_PC = 1'b1;
+
+                            case (IR[4:3])
+                              0 : MCycles = (F[Flag_Z]) ? 3'd2 : 3'd3;
+                              1 : MCycles = (!F[Flag_Z]) ? 3'd2 : 3'd3;
+                              2 : MCycles = (F[Flag_C]) ? 3'd2 : 3'd3;
+                              3 : MCycles = (!F[Flag_C]) ? 3'd2 : 3'd3;
+                            endcase
+                          end
+                        
+                        MCycle[2] :
+                          begin
+                            NoRead = 1'b1;
+                            JumpE = 1'b1;
+                            TStates = 3'd5;
+                          end
+                        default :;
+                      endcase
+                    end // if (Mode != 2 )
+                end // case: 8'b00111000              
+              
+              8'b11101001  :
+                // JP (HL)
+                JumpXY = 1'b1;
+              
+              8'b00010000  :
+                begin
+                  if (Mode == 3 ) 
+                    begin
+                      I_DJNZ = 1'b1;
+                    end 
+                  else if (Mode < 2 ) 
+                    begin
+                      // DJNZ,e
+                      MCycles = 3'b011;
+                      case (1'b1) // MCycle
+                        MCycle[0] :
+                          begin
+                            TStates = 3'b101;
+                            I_DJNZ = 1'b1;
+                            Set_BusB_To = 4'b1010;
+                            Set_BusA_To[2:0] = 3'b000;
+                            Read_To_Reg = 1'b1;
+                            Save_ALU = 1'b1;
+                            ALU_Op = 4'b0010;
+                          end
+                        MCycle[1] :
+                          begin
+                            I_DJNZ = 1'b1;
+                            Inc_PC = 1'b1;
+                          end
+                        MCycle[2] :
+                          begin
+                            NoRead = 1'b1;
+                            JumpE = 1'b1;
+                            TStates = 3'b101;
+                          end
+                        default :;
+                      endcase
+                    end // if (Mode < 2 )
+                end // case: 8'b00010000
+              
+
+              // CALL AND RETURN GROUP
+              8'b11001101  :
+                begin
+                  // CALL nn
+                  MCycles = 3'b101;
+                  case (1'b1) // MCycle
+                    MCycle[1] :
+                      begin
+                        Inc_PC = 1'b1;
+                        LDZ = 1'b1;
+                      end
+                    MCycle[2] :
+                      begin
+                        IncDec_16 = 4'b1111;
+                        Inc_PC = 1'b1;
+                        TStates = 3'b100;
+                        Set_Addr_To = aSP;
+                        LDW = 1'b1;
+                        Set_BusB_To = 4'b1101;
+                      end
+                    MCycle[3] :
+                      begin
+                        Write = 1'b1;
+                        IncDec_16 = 4'b1111;
+                        Set_Addr_To = aSP;
+                        Set_BusB_To = 4'b1100;
+                      end
+                    MCycle[4] :
+                      begin
+                        Write = 1'b1;
+                        Call = 1'b1;
+                      end
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b11001101
+              
+              8'b11zzz100  :
+                begin
+                  if (IR[5] == 1'b0 || Mode != 3 ) 
+                    begin
+                      // CALL cc,nn
+                      MCycles = 3'b101;
+                      case (1'b1) // MCycle
+                        MCycle[1] :
+                          begin
+                            Inc_PC = 1'b1;
+                            LDZ = 1'b1;
+                          end
+                        MCycle[2] :
+                          begin
+                            Inc_PC = 1'b1;
+                            LDW = 1'b1;
+                            if (is_cc_true(F, IR[5:3]) ) 
+                              begin
+                                IncDec_16 = 4'b1111;
+                                Set_Addr_To = aSP;
+                                TStates = 3'b100;
+                                Set_BusB_To = 4'b1101;
+                              end 
+                            else 
+                              begin
+                                MCycles = 3'b011;
+                              end // else: !if(is_cc_true(F, IR[5:3]) )
+                          end // case: 3
+                        
+                        MCycle[3] :
+                          begin
+                            Write = 1'b1;
+                            IncDec_16 = 4'b1111;
+                            Set_Addr_To = aSP;
+                            Set_BusB_To = 4'b1100;
+                          end
+                        
+                        MCycle[4] :
+                          begin
+                            Write = 1'b1;
+                            Call = 1'b1;
+                          end
+                        
+                        default :;
+                      endcase
+                    end // if (IR[5] == 1'b0 || Mode != 3 )
+                end // case: 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100
+              
+              8'b11001001  :
+                begin
+                  // RET
+                  MCycles = 3'b011;
+                  case (1'b1) // MCycle
+                    MCycle[0] :
+                      begin
+                        TStates = 3'b101;
+                        Set_Addr_To = aSP;
+                      end
+                    
+                    MCycle[1] :
+                      begin
+                        IncDec_16 = 4'b0111;
+                        Set_Addr_To = aSP;
+                        LDZ = 1'b1;
+                      end
+                    
+                    MCycle[2] :
+                      begin
+                        Jump = 1'b1;
+                        IncDec_16 = 4'b0111;
+                      end
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b11001001
+              
+              8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000  :
+                begin                  
+                  if (IR[5] == 1'b1 && Mode == 3 ) 
+                    begin
+                      case (IR[4:3])
+                        2'b00  :
+                          begin
+                            // LD ($FF00+nn),A
+                            MCycles = 3'b011;
+                            case (1'b1) // MCycle
+                              MCycle[1] :
+                                begin
+                                  Inc_PC = 1'b1;
+                                  Set_Addr_To = aIOA;
+                                  Set_BusB_To   = 4'b0111;
+                                end
+                              
+                              MCycle[2] :
+                                Write = 1'b1;
+                              default :;
+                            endcase // case(MCycle)
+                          end // case: 2'b00
+                        
+                        2'b01  :
+                          begin
+                            // ADD SP,n
+                            MCycles = 3'b011;
+                            case (1'b1) // MCycle
+                              MCycle[1] :
+                                begin
+                                  ALU_Op = 4'b0000;
+                                  Inc_PC = 1'b1;
+                                  Read_To_Reg = 1'b1;
+                                  Save_ALU = 1'b1;
+                                  Set_BusA_To = 4'b1000;
+                                  Set_BusB_To = 4'b0110;
+                                end
+                              
+                              MCycle[2] :
+                                begin
+                                  NoRead = 1'b1;
+                                  Read_To_Reg = 1'b1;
+                                  Save_ALU = 1'b1;
+                                  ALU_Op = 4'b0001;
+                                  Set_BusA_To = 4'b1001;
+                                  Set_BusB_To = 4'b1110;        // Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+                                end
+                              
+                              default :;
+                            endcase // case(MCycle)
+                          end // case: 2'b01
+                        
+                        2'b10  :
+                          begin
+                            // LD A,($FF00+nn)
+                            MCycles = 3'b011;
+                            case (1'b1) // MCycle
+                              MCycle[1] :
+                                begin
+                                  Inc_PC = 1'b1;
+                                  Set_Addr_To = aIOA;
+                                end
+                              
+                              MCycle[2] :
+                                Read_To_Acc = 1'b1;
+                              default :;
+                            endcase // case(MCycle)
+                          end // case: 2'b10
+                        
+                        2'b11  :
+                          begin
+                            // LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+                            MCycles = 3'b101;
+                            case (1'b1) // MCycle
+                              MCycle[1] :
+                                begin
+                                  Inc_PC = 1'b1;
+                                  LDZ = 1'b1;
+                                end
+                              
+                              MCycle[2] :
+                                begin
+                                  Set_Addr_To = aZI;
+                                  Inc_PC = 1'b1;
+                                  LDW = 1'b1;
+                                end
+                              
+                              MCycle[3] :
+                                begin
+                                  Set_BusA_To[2:0] = 3'b101; // L
+                                  Read_To_Reg = 1'b1;
+                                  Inc_WZ = 1'b1;
+                                  Set_Addr_To = aZI;
+                                end
+                              
+                              MCycle[4] :
+                                begin
+                                  Set_BusA_To[2:0] = 3'b100; // H
+                                  Read_To_Reg = 1'b1;
+                                end
+                              
+                              default :;
+                            endcase // case(MCycle)
+                          end // case: 2'b11
+                        
+                      endcase // case(IR[4:3])
+                      
+                    end 
+                  else 
+                    begin
+                      // RET cc
+                      MCycles = 3'b011;
+                      case (1'b1) // MCycle
+                        MCycle[0] :
+                          begin
+                            if (is_cc_true(F, IR[5:3]) )                              
+                              begin
+                                Set_Addr_To = aSP;
+                              end 
+                            else 
+                              begin
+                                MCycles = 3'b001;
+                              end
+                            TStates = 3'b101;
+                          end // case: 1
+                        
+                        MCycle[1] :
+                          begin
+                            IncDec_16 = 4'b0111;
+                            Set_Addr_To = aSP;
+                            LDZ = 1'b1;
+                          end
+                        MCycle[2] :
+                          begin
+                            Jump = 1'b1;
+                            IncDec_16 = 4'b0111;
+                          end
+                        default :;
+                      endcase
+                    end // else: !if(IR[5] == 1'b1 && Mode == 3 )
+                end // case: 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000
+              
+              8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111  :
+                begin
+                  // RST p
+                  MCycles = 3'b011;
+                  case (1'b1) // MCycle
+                    MCycle[0] :
+                      begin
+                        TStates = 3'b101;
+                        IncDec_16 = 4'b1111;
+                        Set_Addr_To = aSP;
+                        Set_BusB_To = 4'b1101;
+                      end
+                    
+                    MCycle[1] :
+                      begin
+                        Write = 1'b1;
+                        IncDec_16 = 4'b1111;
+                        Set_Addr_To = aSP;
+                        Set_BusB_To = 4'b1100;
+                      end
+                    
+                    MCycle[2] :
+                      begin
+                        Write = 1'b1;
+                        RstP = 1'b1;
+                      end
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111
+              
+              // INPUT AND OUTPUT GROUP
+              8'b11011011  :
+                begin
+                  if (Mode != 3 ) 
+                    begin
+                      // IN A,(n)
+                      MCycles = 3'b011;
+                      case (1'b1) // MCycle
+                        MCycle[1] :
+                          begin
+                            Inc_PC = 1'b1;
+                            Set_Addr_To = aIOA;
+                          end
+                        
+                        MCycle[2] :
+                          begin
+                            Read_To_Acc = 1'b1;
+                            IORQ = 1'b1;
+                          end
+                        
+                        default :;
+                      endcase
+                    end // if (Mode != 3 )
+                end // case: 8'b11011011
+              
+              8'b11010011  :
+                begin
+                  if (Mode != 3 ) 
+                    begin
+                      // OUT (n),A
+                      MCycles = 3'b011;
+                      case (1'b1) // MCycle
+                        MCycle[1] :
+                          begin
+                            Inc_PC = 1'b1;
+                            Set_Addr_To = aIOA;
+                            Set_BusB_To = 4'b0111;
+                          end
+                        
+                        MCycle[2] :
+                          begin
+                            Write = 1'b1;
+                            IORQ = 1'b1;
+                          end
+                        
+                        default :;
+                      endcase
+                    end // if (Mode != 3 )
+                end // case: 8'b11010011
+              
+
+              //----------------------------------------------------------------------------
+              //----------------------------------------------------------------------------
+              // MULTIBYTE INSTRUCTIONS
+              //----------------------------------------------------------------------------
+              //----------------------------------------------------------------------------
+
+              8'b11001011  :
+                begin
+                  if (Mode != 2 ) 
+                    begin
+                      Prefix = 2'b01;
+                    end
+                end              
+
+              8'b11101101  :
+                begin
+                  if (Mode < 2 ) 
+                    begin
+                      Prefix = 2'b10;
+                    end
+                end
+
+              8'b11011101,8'b11111101  :
+                begin
+                  if (Mode < 2 ) 
+                    begin
+                      Prefix = 2'b11;
+                    end
+                end
+              
+            endcase // case(IR)
+          end // case: 2'b00
+        
+
+        2'b01  :
+          begin
+            
+
+            //----------------------------------------------------------------------------
+            //
+            //  CB prefixed instructions
+            //
+            //----------------------------------------------------------------------------
+            
+            Set_BusA_To[2:0] = IR[2:0];
+            Set_BusB_To[2:0] = IR[2:0];
+            
+            casez (IR)
+              8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,
+              8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111,
+              8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111,
+              8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111,
+              8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111,
+              8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111,
+              8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111,
+              8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 :
+                begin
+                  // RLC r
+                  // RL r
+                  // RRC r
+                  // RR r
+                  // SLA r
+                  // SRA r
+                  // SRL r
+                  // SLL r (Undocumented) / SWAP r
+                  if (MCycle[0] ) begin
+                    ALU_Op = 4'b1000;
+                    Read_To_Reg = 1'b1;
+                    Save_ALU = 1'b1;
+                  end
+                end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,...
+              
+              8'b00zzz110  :
+                begin
+                  // RLC (HL)
+                  // RL (HL)
+                  // RRC (HL)
+                  // RR (HL)
+                  // SRA (HL)
+                  // SRL (HL)
+                  // SLA (HL)
+                  // SLL (HL) (Undocumented) / SWAP (HL)
+                  MCycles = 3'b011;
+                  case (1'b1) // MCycle
+                    MCycle[0], MCycle[6] :
+                      Set_Addr_To = aXY;
+                    MCycle[1] :
+                      begin
+                        ALU_Op = 4'b1000;
+                        Read_To_Reg = 1'b1;
+                        Save_ALU = 1'b1;
+                        Set_Addr_To = aXY;
+                        TStates = 3'b100;
+                      end
+                    
+                    MCycle[2] :
+                      Write = 1'b1;
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110
+              
+              8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,
+                  8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111,
+                  8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111,
+                  8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111,
+                  8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111,
+                  8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111,
+                  8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111,
+                  8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 :
+                    begin
+                      // BIT b,r
+                      if (MCycle[0] )
+                        begin
+                          Set_BusB_To[2:0] = IR[2:0];
+                          ALU_Op = 4'b1001;
+                        end
+                    end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,...
+              
+              8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110  :
+                begin
+                  // BIT b,(HL)
+                  MCycles = 3'b010;
+                  case (1'b1) // MCycle
+                    MCycle[0], MCycle[6] :
+                      Set_Addr_To = aXY;
+                    MCycle[1] :
+                      begin
+                        ALU_Op = 4'b1001;
+                        TStates = 3'b100;
+                      end
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110
+              
+              8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,
+                  8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111,
+                  8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111,
+                  8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111,
+                  8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111,
+                  8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111,
+                  8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111,
+                  8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 :
+                    begin
+                      // SET b,r
+                      if (MCycle[0] ) 
+                        begin
+                          ALU_Op = 4'b1010;
+                          Read_To_Reg = 1'b1;
+                          Save_ALU = 1'b1;
+                        end
+                    end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,...
+              
+              8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110  :
+                begin
+                  // SET b,(HL)
+                  MCycles = 3'b011;
+                  case (1'b1) // MCycle
+                    MCycle[0], MCycle[6] :
+                      Set_Addr_To = aXY;
+                    MCycle[1] :
+                      begin
+                        ALU_Op = 4'b1010;
+                        Read_To_Reg = 1'b1;
+                        Save_ALU = 1'b1;
+                        Set_Addr_To = aXY;
+                        TStates = 3'b100;
+                      end
+                    MCycle[2] :
+                      Write = 1'b1;
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110
+              
+              8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,
+                  8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111,
+                  8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111,
+                  8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111,
+                  8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111,
+                  8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111,
+                  8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111,
+                  8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 :
+                    begin
+                      // RES b,r
+                      if (MCycle[0] ) 
+                        begin
+                          ALU_Op = 4'b1011;
+                          Read_To_Reg = 1'b1;
+                          Save_ALU = 1'b1;
+                        end
+                    end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
+              
+              8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110  :
+                begin
+                  // RES b,(HL)
+                  MCycles = 3'b011;
+                  case (1'b1) // MCycle
+                    MCycle[0], MCycle[6] :
+                      Set_Addr_To = aXY;
+                    MCycle[1] :
+                      begin
+                        ALU_Op = 4'b1011;
+                        Read_To_Reg = 1'b1;
+                        Save_ALU = 1'b1;
+                        Set_Addr_To = aXY;
+                        TStates = 3'b100;
+                      end
+                    
+                    MCycle[2] :
+                      Write = 1'b1;
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110
+              
+            endcase // case(IR)
+          end // case: 2'b01
+        
+        
+        default :
+          begin : default_ed_block
+            
+            //----------------------------------------------------------------------------
+            //
+            //  ED prefixed instructions
+            //
+            //----------------------------------------------------------------------------
+
+            casez (IR)
+	      /*
+	       * Undocumented NOP instructions commented out to reduce size of mcode
+	       *
+              8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111
+                ,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111
+                  ,8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010110,8'b00010111
+                    ,8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011110,8'b00011111
+                      ,8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100110,8'b00100111
+                        ,8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101110,8'b00101111
+                          ,8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110110,8'b00110111
+                            ,8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111110,8'b00111111
+                
+
+                              ,8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000110,8'b10000111
+                                ,8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001110,8'b10001111
+                                  ,8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010110,8'b10010111
+                                    ,8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011110,8'b10011111
+                                      ,                                            8'b10100100,8'b10100101,8'b10100110,8'b10100111
+                                        ,                                            8'b10101100,8'b10101101,8'b10101110,8'b10101111
+                                          ,                                            8'b10110100,8'b10110101,8'b10110110,8'b10110111
+                                            ,                                            8'b10111100,8'b10111101,8'b10111110,8'b10111111
+                                              ,8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000110,8'b11000111
+                                                ,8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001110,8'b11001111
+                                                  ,8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010110,8'b11010111
+                                                    ,8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011110,8'b11011111
+                                                      ,8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100110,8'b11100111
+                                                        ,8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101110,8'b11101111
+                                                          ,8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110110,8'b11110111
+                                                            ,8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111110,8'b11111111 :
+                                                              ; // NOP, undocumented
+              
+              8'b01111110,8'b01111111  :
+                // NOP, undocumented
+                ;
+	       */
+	      
+              // 8 BIT LOAD GROUP
+              8'b01010111  :
+                begin
+                  // LD A,I
+                  Special_LD = 3'b100;
+                  TStates = 3'b101;
+                end
+              
+              8'b01011111  :
+                begin
+                  // LD A,R
+                  Special_LD = 3'b101;
+                  TStates = 3'b101;
+                end
+              
+              8'b01000111  :
+                begin
+                  // LD I,A
+                  Special_LD = 3'b110;
+                  TStates = 3'b101;
+                end
+              
+              8'b01001111  :
+                begin
+                  // LD R,A
+                  Special_LD = 3'b111;
+                  TStates = 3'b101;
+                end
+              
+              // 16 BIT LOAD GROUP
+              8'b01001011,8'b01011011,8'b01101011,8'b01111011  :
+                begin
+                  // LD dd,(nn)
+                  MCycles = 3'b101;
+                  case (1'b1) // MCycle
+                    MCycle[1] :
+                      begin
+                        Inc_PC = 1'b1;
+                        LDZ = 1'b1;
+                      end
+                    
+                    MCycle[2] :
+                      begin
+                        Set_Addr_To = aZI;
+                        Inc_PC = 1'b1;
+                        LDW = 1'b1;
+                      end
+                    
+                    MCycle[3] :
+                      begin
+                        Read_To_Reg = 1'b1;
+                        if (IR[5:4] == 2'b11 ) 
+                          begin
+                            Set_BusA_To = 4'b1000;
+                          end 
+                        else 
+                          begin
+                            Set_BusA_To[2:1] = IR[5:4];
+                            Set_BusA_To[0] = 1'b1;
+                          end
+                        Inc_WZ = 1'b1;
+                        Set_Addr_To = aZI;
+                      end // case: 4
+                    
+                    MCycle[4] :
+                      begin
+                        Read_To_Reg = 1'b1;
+                        if (IR[5:4] == 2'b11 ) 
+                          begin
+                            Set_BusA_To = 4'b1001;
+                          end 
+                        else 
+                          begin
+                            Set_BusA_To[2:1] = IR[5:4];
+                            Set_BusA_To[0] = 1'b0;
+                          end
+                      end // case: 5
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011
+              
+              
+              8'b01000011,8'b01010011,8'b01100011,8'b01110011  :
+                begin
+                  // LD (nn),dd
+                  MCycles = 3'b101;
+                  case (1'b1) // MCycle
+                    MCycle[1] :
+                      begin
+                        Inc_PC = 1'b1;
+                        LDZ = 1'b1;
+                      end
+                    
+                    MCycle[2] :
+                      begin
+                        Set_Addr_To = aZI;
+                        Inc_PC = 1'b1;
+                        LDW = 1'b1;
+                        if (IR[5:4] == 2'b11 ) 
+                          begin
+                            Set_BusB_To = 4'b1000;
+                          end 
+                        else 
+                          begin
+                            Set_BusB_To[2:1] = IR[5:4];
+                            Set_BusB_To[0] = 1'b1;
+                            Set_BusB_To[3] = 1'b0;
+                          end
+                      end // case: 3
+                    
+                    MCycle[3] :
+                      begin
+                        Inc_WZ = 1'b1;
+                        Set_Addr_To = aZI;
+                        Write = 1'b1;
+                        if (IR[5:4] == 2'b11 ) 
+                          begin
+                            Set_BusB_To = 4'b1001;
+                          end 
+                        else 
+                          begin
+                            Set_BusB_To[2:1] = IR[5:4];
+                            Set_BusB_To[0] = 1'b0;
+                            Set_BusB_To[3] = 1'b0;
+                          end
+                      end // case: 4
+                    
+                    MCycle[4] :
+                      begin
+                        Write = 1'b1;
+                      end
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011
+              
+              8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000  :
+                begin
+                  // LDI, LDD, LDIR, LDDR
+                  MCycles = 3'b100;
+                  case (1'b1) // MCycle
+                    MCycle[0] :
+                      begin
+                        Set_Addr_To = aXY;
+                        IncDec_16 = 4'b1100; // BC
+                      end
+                    
+                    MCycle[1] :
+                      begin
+                        Set_BusB_To = 4'b0110;
+                        Set_BusA_To[2:0] = 3'b111;
+                        ALU_Op = 4'b0000;
+                        Set_Addr_To = aDE;
+                        if (IR[3] == 1'b0 ) 
+                          begin
+                            IncDec_16 = 4'b0110; // IX
+                          end 
+                        else 
+                          begin
+                            IncDec_16 = 4'b1110;
+                          end
+                      end // case: 2
+                    
+                    MCycle[2] :
+                      begin
+                        I_BT = 1'b1;
+                        TStates = 3'b101;
+                        Write = 1'b1;
+                        if (IR[3] == 1'b0 ) 
+                          begin
+                            IncDec_16 = 4'b0101; // DE
+                          end 
+                        else 
+                          begin
+                            IncDec_16 = 4'b1101;
+                          end
+                      end // case: 3
+                    
+                    MCycle[3] :
+                      begin
+                        NoRead = 1'b1;
+                        TStates = 3'b101;
+                      end
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000
+              
+              8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001  :
+                begin
+                  // CPI, CPD, CPIR, CPDR
+                  MCycles = 3'b100;
+                  case (1'b1) // MCycle
+                    MCycle[0] :
+                      begin
+                        Set_Addr_To = aXY;
+                        IncDec_16 = 4'b1100; // BC
+                      end
+                    
+                    MCycle[1] :
+                      begin
+                        Set_BusB_To = 4'b0110;
+                        Set_BusA_To[2:0] = 3'b111;
+                        ALU_Op = 4'b0111;
+                        Save_ALU = 1'b1;
+                        PreserveC = 1'b1;
+                        if (IR[3] == 1'b0 ) 
+                          begin
+                            IncDec_16 = 4'b0110;
+                          end 
+                        else 
+                          begin
+                            IncDec_16 = 4'b1110;
+                          end
+                      end // case: 2
+                    
+                    MCycle[2] :
+                      begin
+                        NoRead = 1'b1;
+                        I_BC = 1'b1;
+                        TStates = 3'b101;
+                      end
+                    
+                    MCycle[3] :
+                      begin
+                        NoRead = 1'b1;
+                        TStates = 3'b101;
+                      end
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001
+              
+              8'b01000100,8'b01001100,8'b01010100,8'b01011100,8'b01100100,8'b01101100,8'b01110100,8'b01111100  :
+                begin
+                  // NEG
+                  ALU_Op = 4'b0010;
+                  Set_BusB_To = 4'b0111;
+                  Set_BusA_To = 4'b1010;
+                  Read_To_Acc = 1'b1;
+                  Save_ALU = 1'b1;
+                end
+              
+              8'b01000110,8'b01001110,8'b01100110,8'b01101110  :
+                begin
+                  // IM 0
+                  IMode = 2'b00;
+                end
+              
+              8'b01010110,8'b01110110  :
+                // IM 1
+                IMode = 2'b01;
+              
+              8'b01011110,8'b01110111  :
+                // IM 2
+                IMode = 2'b10;
+              
+              // 16 bit arithmetic
+              8'b01001010,8'b01011010,8'b01101010,8'b01111010  :
+                begin
+                  // ADC HL,ss
+                  MCycles = 3'b011;
+                  case (1'b1) // MCycle
+                    MCycle[1] :
+                      begin
+                        NoRead = 1'b1;
+                        ALU_Op = 4'b0001;
+                        Read_To_Reg = 1'b1;
+                        Save_ALU = 1'b1;
+                        Set_BusA_To[2:0] = 3'b101;
+                        case (IR[5:4])
+                          0,1,2  :
+                            begin
+                              Set_BusB_To[2:1] = IR[5:4];
+                              Set_BusB_To[0] = 1'b1;
+                            end
+                          default :
+                            Set_BusB_To = 4'b1000;
+                        endcase
+                        TStates = 3'b100;
+                      end // case: 2
+                    
+                    MCycle[2] :
+                      begin
+                        NoRead = 1'b1;
+                        Read_To_Reg = 1'b1;
+                        Save_ALU = 1'b1;
+                        ALU_Op = 4'b0001;
+                        Set_BusA_To[2:0] = 3'b100;
+                        case (IR[5:4])
+                          0,1,2  :
+                            begin
+                              Set_BusB_To[2:1] = IR[5:4];
+                              Set_BusB_To[0] = 1'b0;
+                            end
+                          default :
+                            Set_BusB_To = 4'b1001;
+                        endcase // case(IR[5:4])
+                      end // case: 3
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010
+              
+              8'b01000010,8'b01010010,8'b01100010,8'b01110010  :
+                begin
+                  // SBC HL,ss
+                  MCycles = 3'b011;
+                  case (1'b1) // MCycle
+                    MCycle[1] :
+                      begin
+                        NoRead = 1'b1;
+                        ALU_Op = 4'b0011;
+                        Read_To_Reg = 1'b1;
+                        Save_ALU = 1'b1;
+                        Set_BusA_To[2:0] = 3'b101;
+                        case (IR[5:4])
+                          0,1,2  :
+                            begin
+                              Set_BusB_To[2:1] = IR[5:4];
+                              Set_BusB_To[0] = 1'b1;
+                            end
+                          default :
+                            Set_BusB_To = 4'b1000;
+                        endcase
+                        TStates = 3'b100;
+                      end // case: 2
+                    
+                    MCycle[2] :
+                      begin
+                        NoRead = 1'b1;
+                        ALU_Op = 4'b0011;
+                        Read_To_Reg = 1'b1;
+                        Save_ALU = 1'b1;
+                        Set_BusA_To[2:0] = 3'b100;
+                        case (IR[5:4])
+                          0,1,2  :
+                            Set_BusB_To[2:1] = IR[5:4];
+                          default :
+                            Set_BusB_To = 4'b1001;
+                        endcase
+                      end // case: 3
+                    
+                    default :;
+                    
+                  endcase // case(MCycle)
+                end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010
+              
+              8'b01101111  :
+                begin
+                  // RLD
+                  MCycles = 3'b100;
+                  case (1'b1) // MCycle
+                    MCycle[1] :
+                      begin
+                        NoRead = 1'b1;
+                        Set_Addr_To = aXY;
+                      end
+                    
+                    MCycle[2] :
+                      begin
+                        Read_To_Reg = 1'b1;
+                        Set_BusB_To[2:0] = 3'b110;
+                        Set_BusA_To[2:0] = 3'b111;
+                        ALU_Op = 4'b1101;
+                        TStates = 3'b100;
+                        Set_Addr_To = aXY;
+                        Save_ALU = 1'b1;
+                      end
+                    
+                    MCycle[3] :
+                      begin
+                        I_RLD = 1'b1;
+                        Write = 1'b1;
+                      end
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b01101111
+              
+              8'b01100111  :
+                begin
+                  // RRD
+                  MCycles = 3'b100;
+                  case (1'b1) // MCycle
+                    MCycle[1] :
+                      Set_Addr_To = aXY;
+                    MCycle[2] :
+                      begin
+                        Read_To_Reg = 1'b1;
+                        Set_BusB_To[2:0] = 3'b110;
+                        Set_BusA_To[2:0] = 3'b111;
+                        ALU_Op = 4'b1110;
+                        TStates = 3'b100;
+                        Set_Addr_To = aXY;
+                        Save_ALU = 1'b1;
+                      end
+                    
+                    MCycle[3] :
+                      begin
+                        I_RRD = 1'b1;
+                        Write = 1'b1;
+                      end
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b01100111
+              
+              8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101  :
+                begin
+                  // RETI, RETN
+                  MCycles = 3'b011;
+                  case (1'b1) // MCycle
+                    MCycle[0] :
+                      Set_Addr_To = aSP;
+                    
+                    MCycle[1] :
+                      begin
+                        IncDec_16 = 4'b0111;
+                        Set_Addr_To = aSP;
+                        LDZ = 1'b1;
+                      end
+                    
+                    MCycle[2] :
+                      begin
+                        Jump = 1'b1;
+                        IncDec_16 = 4'b0111;
+                        I_RETN = 1'b1;
+                      end
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101
+              
+              8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000  :
+                begin
+                  // IN r,(C)
+                  MCycles = 3'b010;
+                  case (1'b1) // MCycle
+                    MCycle[0] :
+                      Set_Addr_To = aBC;
+                    
+                    MCycle[1] :
+                      begin
+                        IORQ = 1'b1;
+                        if (IR[5:3] != 3'b110 ) 
+                          begin
+                            Read_To_Reg = 1'b1;
+                            Set_BusA_To[2:0] = IR[5:3];
+                          end
+                        I_INRC = 1'b1;
+                      end
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000
+              
+              8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001  :
+                begin
+                  // OUT (C),r
+                  // OUT (C),0
+                  MCycles = 3'b010;
+                  case (1'b1) // MCycle
+                    MCycle[0] :
+                      begin
+                        Set_Addr_To = aBC;
+                        Set_BusB_To[2:0]        = IR[5:3];
+                        if (IR[5:3] == 3'b110 ) 
+                          begin
+                            Set_BusB_To[3] = 1'b1;
+                          end
+                      end
+                    
+                    MCycle[1] :
+                      begin
+                        Write = 1'b1;
+                        IORQ = 1'b1;
+                      end
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001
+              
+              8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010  :
+                begin
+                  // INI, IND, INIR, INDR
+                  MCycles = 3'b100;
+                  case (1'b1) // MCycle
+                    MCycle[0] :
+                      begin
+                        Set_Addr_To = aBC;
+                        Set_BusB_To = 4'b1010;
+                        Set_BusA_To = 4'b0000;
+                        Read_To_Reg = 1'b1;
+                        Save_ALU = 1'b1;
+                        ALU_Op = 4'b0010;
+                      end
+                    
+                    MCycle[1] :
+                      begin
+                        IORQ = 1'b1;
+                        Set_BusB_To = 4'b0110;
+                        Set_Addr_To = aXY;
+                      end
+                    
+                    MCycle[2] :
+                      begin
+                        if (IR[3] == 1'b0 ) 
+                          begin
+			    IncDec_16 = 4'b0110;
+                          end 
+                        else 
+                          begin
+			    IncDec_16 = 4'b1110;
+                          end
+                        TStates = 3'b100;
+                        Write = 1'b1;
+                        I_BTR = 1'b1;
+                      end // case: 3
+                    
+                    MCycle[3] :
+                      begin
+                        NoRead = 1'b1;
+                        TStates = 3'b101;
+                      end
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010
+              
+              8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011  :
+                begin
+                  // OUTI, OUTD, OTIR, OTDR
+                  MCycles = 3'b100;
+                  case (1'b1) // MCycle
+                    MCycle[0] :
+                      begin
+                        TStates = 3'b101;
+                        Set_Addr_To = aXY;
+                        Set_BusB_To = 4'b1010;
+                        Set_BusA_To = 4'b0000;
+                        Read_To_Reg = 1'b1;
+                        Save_ALU = 1'b1;
+                        ALU_Op = 4'b0010;
+                      end
+                    
+                    MCycle[1] :
+                      begin
+                        Set_BusB_To = 4'b0110;
+                        Set_Addr_To = aBC;
+                        if (IR[3] == 1'b0 ) 
+                          begin
+                            IncDec_16 = 4'b0110;
+                          end 
+                        else 
+                          begin
+                            IncDec_16 = 4'b1110;
+                          end
+                      end
+                    
+                    MCycle[2] :
+                      begin
+                        if (IR[3] == 1'b0 ) 
+                          begin
+                            IncDec_16 = 4'b0010;
+                          end 
+                        else 
+                          begin
+                            IncDec_16 = 4'b1010;
+                          end
+                        IORQ = 1'b1;
+                        Write = 1'b1;
+                        I_BTR = 1'b1;
+                      end // case: 3
+                    
+                    MCycle[3] :
+                      begin
+                        NoRead = 1'b1;
+                        TStates = 3'b101;
+                      end
+                    
+                    default :;
+                  endcase // case(MCycle)
+                end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011
+
+              default : ;
+              
+            endcase // case(IR)                  
+          end // block: default_ed_block        
+      endcase // case(ISet)
+      
+      if (Mode == 1 ) 
+        begin
+          if (MCycle[0] ) 
+            begin
+              //TStates = 3'b100;
+            end 
+          else 
+            begin
+              TStates = 3'b011;
+            end
+        end
+
+      if (Mode == 3 ) 
+        begin
+          if (MCycle[0] ) 
+            begin
+              //TStates = 3'b100;
+            end 
+          else 
+            begin
+              TStates = 3'b100;
+            end
+        end
+
+      if (Mode < 2 ) 
+        begin
+          if (MCycle[5] ) 
+            begin
+              Inc_PC = 1'b1;
+              if (Mode == 1 ) 
+                begin
+                  Set_Addr_To = aXY;
+                  TStates = 3'b100;
+                  Set_BusB_To[2:0] = SSS;
+                  Set_BusB_To[3] = 1'b0;
+                end
+              if (IR == 8'b00110110 || IR == 8'b11001011 ) 
+                begin
+                  Set_Addr_To = aNone;
+                end
+            end
+          if (MCycle[6] ) 
+            begin
+              if (Mode == 0 ) 
+                begin
+                  TStates = 3'b101;
+                end
+              if (ISet != 2'b01 ) 
+                begin
+                  Set_Addr_To = aXY;
+                end
+              Set_BusB_To[2:0] = SSS;
+              Set_BusB_To[3] = 1'b0;
+              if (IR == 8'b00110110 || ISet == 2'b01 ) 
+                begin
+                  // LD (HL),n
+                  Inc_PC = 1'b1;
+                end 
+              else 
+                begin
+                  NoRead = 1'b1;
+                end
+            end
+        end // if (Mode < 2 )      
+      
+    end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
+endmodule // T80_MCode
diff --git a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_reg.v b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_reg.v
new file mode 100644
index 00000000..889766cf
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_reg.v
@@ -0,0 +1,77 @@
+//
+// TV80 8-Bit Microprocessor Core
+// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
+//
+// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a 
+// copy of this software and associated documentation files (the "Software"), 
+// to deal in the Software without restriction, including without limitation 
+// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
+// and/or sell copies of the Software, and to permit persons to whom the 
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included 
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+module tv80_reg (/*AUTOARG*/
+  // Outputs
+  DOBH, DOAL, DOCL, DOBL, DOCH, DOAH, 
+  // Inputs
+  AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
+  );
+    input  [2:0] AddrC;
+    output [7:0] DOBH;
+    input  [2:0] AddrA;
+    input  [2:0] AddrB;
+    input  [7:0] DIH;
+    output [7:0] DOAL;
+    output [7:0] DOCL;
+    input  [7:0] DIL;
+    output [7:0] DOBL;
+    output [7:0] DOCH;
+    output [7:0] DOAH;
+    input  clk, CEN, WEH, WEL;
+
+  reg [7:0] RegsH [0:7];
+  reg [7:0] RegsL [0:7];
+
+  always @(posedge clk)
+    begin
+      if (CEN)
+        begin
+          if (WEH) RegsH[AddrA] <= DIH;
+          if (WEL) RegsL[AddrA] <= DIL;
+        end
+    end
+          
+  assign DOAH = RegsH[AddrA];
+  assign DOAL = RegsL[AddrA];
+  assign DOBH = RegsH[AddrB];
+  assign DOBL = RegsL[AddrB];
+  assign DOCH = RegsH[AddrC];
+  assign DOCL = RegsL[AddrC];
+
+  // break out ram bits for waveform debug
+// synopsys translate_off
+  wire [7:0] B = RegsH[0];
+  wire [7:0] C = RegsL[0];
+  wire [7:0] D = RegsH[1];
+  wire [7:0] E = RegsL[1];
+  wire [7:0] H = RegsH[2];
+  wire [7:0] L = RegsL[2];
+
+  wire [15:0] IX = { RegsH[3], RegsL[3] };
+  wire [15:0] IY = { RegsH[7], RegsL[7] };
+// synopsys translate_on
+  
+endmodule
+
diff --git a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80n.v b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80n.v
new file mode 100644
index 00000000..d672608e
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80n.v
@@ -0,0 +1,182 @@
+//
+// TV80 8-Bit Microprocessor Core
+// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
+//
+// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a 
+// copy of this software and associated documentation files (the "Software"), 
+// to deal in the Software without restriction, including without limitation 
+// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
+// and/or sell copies of the Software, and to permit persons to whom the 
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included 
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+// Negative-edge based wrapper allows memory wait_n signal to work
+// correctly without resorting to asynchronous logic.
+
+module tv80n (/*AUTOARG*/
+  // Outputs
+  m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
+  // Inputs
+  reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
+  );
+
+  parameter Mode = 0;    // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+  parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2
+  parameter IOWait  = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
+
+
+  input         reset_n; 
+  input         clk; 
+  input         wait_n; 
+  input         int_n; 
+  input         nmi_n; 
+  input         busrq_n; 
+  output        m1_n; 
+  output        mreq_n; 
+  output        iorq_n; 
+  output        rd_n; 
+  output        wr_n; 
+  output        rfsh_n; 
+  output        halt_n; 
+  output        busak_n; 
+  output [15:0] A;
+  input [7:0]   di;
+  output [7:0]  dout;
+
+  reg           mreq_n; 
+  reg           iorq_n; 
+  reg           rd_n; 
+  reg           wr_n; 
+  reg           nxt_mreq_n; 
+  reg           nxt_iorq_n; 
+  reg           nxt_rd_n; 
+  reg           nxt_wr_n; 
+  
+  wire          cen;
+  wire          intcycle_n;
+  wire          no_read;
+  wire          write;
+  wire          iorq;
+  reg [7:0]     di_reg;
+  wire [6:0]    mcycle;
+  wire [6:0]    tstate;
+
+  assign    cen = 1;
+
+  tv80_core #(Mode, IOWait) i_tv80_core
+    (
+     .cen (cen),
+     .m1_n (m1_n),
+     .iorq (iorq),
+     .no_read (no_read),
+     .write (write),
+     .rfsh_n (rfsh_n),
+     .halt_n (halt_n),
+     .wait_n (wait_n),
+     .int_n (int_n),
+     .nmi_n (nmi_n),
+     .reset_n (reset_n),
+     .busrq_n (busrq_n),
+     .busak_n (busak_n),
+     .clk (clk),
+     .IntE (),
+     .stop (),
+     .A (A),
+     .dinst (di),
+     .di (di_reg),
+     .dout (dout),
+     .mc (mcycle),
+     .ts (tstate),
+     .intcycle_n (intcycle_n)
+     );  
+
+  always @*
+    begin
+      nxt_mreq_n = 1;
+      nxt_rd_n   = 1;
+      nxt_iorq_n = 1;
+      nxt_wr_n   = 1;
+      
+      if (mcycle[0])
+        begin
+	  if (tstate[1] || tstate[2])
+            begin
+	      nxt_rd_n = ~ intcycle_n;
+	      nxt_mreq_n = ~ intcycle_n;
+	      nxt_iorq_n = intcycle_n;
+	    end
+        end // if (mcycle[0])          
+      else
+        begin
+	  if ((tstate[1] || tstate[2]) && !no_read && !write)
+            begin
+	      nxt_rd_n = 1'b0;
+	      nxt_iorq_n = ~ iorq;
+	      nxt_mreq_n = iorq;
+	    end
+	  if (T2Write == 0)
+            begin                          
+	      if (tstate[2] && write)
+                begin
+		  nxt_wr_n = 1'b0;
+		  nxt_iorq_n = ~ iorq;
+		  nxt_mreq_n = iorq;
+                end
+            end
+	  else
+            begin
+	      if ((tstate[1] || (tstate[2] && !wait_n)) && write)
+                begin
+		  nxt_wr_n = 1'b0;
+		  nxt_iorq_n = ~ iorq;
+		  nxt_mreq_n = iorq;
+		end
+	    end // else: !if(T2write == 0)          
+	end // else: !if(mcycle[0])
+    end // always @ *
+
+  always @(negedge clk)
+    begin
+      if (!reset_n)
+        begin
+	  rd_n   <= #1 1'b1;
+	  wr_n   <= #1 1'b1;
+	  iorq_n <= #1 1'b1;
+	  mreq_n <= #1 1'b1;
+        end
+      else
+        begin
+	  rd_n <= #1 nxt_rd_n;
+	  wr_n <= #1 nxt_wr_n;
+	  iorq_n <= #1 nxt_iorq_n;
+	  mreq_n <= #1 nxt_mreq_n;
+	end // else: !if(!reset_n)
+    end // always @ (posedge clk or negedge reset_n)
+
+  always @(posedge clk)
+    begin
+      if (!reset_n)
+        begin
+	  di_reg <= #1 0;
+        end
+      else
+        begin
+	  if (tstate[2] && wait_n == 1'b1)
+	    di_reg <= #1 di;
+	end // else: !if(!reset_n)
+    end // always @ (posedge clk)
+  
+endmodule // t80n
+
diff --git a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80s.v b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80s.v
new file mode 100644
index 00000000..3d825cb7
--- /dev/null
+++ b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80s.v
@@ -0,0 +1,162 @@
+//
+// TV80 8-Bit Microprocessor Core
+// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
+//
+// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a 
+// copy of this software and associated documentation files (the "Software"), 
+// to deal in the Software without restriction, including without limitation 
+// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
+// and/or sell copies of the Software, and to permit persons to whom the 
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included 
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+module tv80s (/*AUTOARG*/
+  // Outputs
+  m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout, 
+  // Inputs
+  reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
+  );
+
+  parameter Mode = 0;    // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+  parameter T2Write = 1; // 0 => wr_n active in T3, /=0 => wr_n active in T2
+  parameter IOWait  = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
+
+
+  input         reset_n; 
+  input         clk; 
+  input         wait_n; 
+  input         int_n; 
+  input         nmi_n; 
+  input         busrq_n; 
+  output        m1_n; 
+  output        mreq_n; 
+  output        iorq_n; 
+  output        rd_n; 
+  output        wr_n; 
+  output        rfsh_n; 
+  output        halt_n; 
+  output        busak_n; 
+  output [15:0] A;
+  input [7:0]   di;
+  output [7:0]  dout;
+
+  reg           mreq_n; 
+  reg           iorq_n; 
+  reg           rd_n; 
+  reg           wr_n; 
+  
+  wire          cen;
+  wire          intcycle_n;
+  wire          no_read;
+  wire          write;
+  wire          iorq;
+  reg [7:0]     di_reg;
+  wire [6:0]    mcycle;
+  wire [6:0]    tstate;
+
+  assign    cen = 1;
+
+  tv80_core #(Mode, IOWait) i_tv80_core
+    (
+     .cen (cen),
+     .m1_n (m1_n),
+     .iorq (iorq),
+     .no_read (no_read),
+     .write (write),
+     .rfsh_n (rfsh_n),
+     .halt_n (halt_n),
+     .wait_n (wait_n),
+     .int_n (int_n),
+     .nmi_n (nmi_n),
+     .reset_n (reset_n),
+     .busrq_n (busrq_n),
+     .busak_n (busak_n),
+     .clk (clk),
+     .IntE (),
+     .stop (),
+     .A (A),
+     .dinst (di),
+     .di (di_reg),
+     .dout (dout),
+     .mc (mcycle),
+     .ts (tstate),
+     .intcycle_n (intcycle_n)
+     );  
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (!reset_n)
+        begin
+          rd_n   <= #1 1'b1;
+          wr_n   <= #1 1'b1;
+          iorq_n <= #1 1'b1;
+          mreq_n <= #1 1'b1;
+          di_reg <= #1 0;
+        end
+      else
+        begin
+          rd_n <= #1 1'b1;
+          wr_n <= #1 1'b1;
+          iorq_n <= #1 1'b1;
+          mreq_n <= #1 1'b1;
+          if (mcycle[0])
+            begin
+              if (tstate[1] || (tstate[2] && wait_n == 1'b0))
+                begin
+                  rd_n <= #1 ~ intcycle_n;
+                  mreq_n <= #1 ~ intcycle_n;
+                  iorq_n <= #1 intcycle_n;
+                end
+            `ifdef TV80_REFRESH
+              if (tstate[3])
+            mreq_n <= #1 1'b0;
+            `endif
+            end // if (mcycle[0])          
+          else
+            begin
+              if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0)
+                begin
+                  rd_n <= #1 1'b0;
+                  iorq_n <= #1 ~ iorq;
+                  mreq_n <= #1 iorq;
+                end
+              if (T2Write == 0)
+                begin                          
+                  if (tstate[2] && write == 1'b1)
+                    begin
+                      wr_n <= #1 1'b0;
+                      iorq_n <= #1 ~ iorq;
+                      mreq_n <= #1 iorq;
+                    end
+                end
+              else
+                begin
+                  if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && write == 1'b1)
+                    begin
+                      wr_n <= #1 1'b0;
+                      iorq_n <= #1 ~ iorq;
+                      mreq_n <= #1 iorq;
+                  end
+                end // else: !if(T2write == 0)
+              
+            end // else: !if(mcycle[0])
+          
+          if (tstate[2] && wait_n == 1'b1)
+            di_reg <= #1 di;
+        end // else: !if(!reset_n)
+    end // always @ (posedge clk or negedge reset_n)
+  
+endmodule // t80s
+