diff --git a/Computer_MiST/Laser310_MiST/Laser310_MiST.qpf b/Computer_MiST/Laser310_MiST/Laser310_MiST.qpf
deleted file mode 100644
index 6e4b53bc..00000000
--- a/Computer_MiST/Laser310_MiST/Laser310_MiST.qpf
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 12:11:46  March 17, 2019
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "12:11:46  March 17, 2019"
-
-# Revisions
-
-PROJECT_REVISION = "Laser310_MiST"
diff --git a/Computer_MiST/Laser310_MiST/Laser310_MiST.qsf b/Computer_MiST/Laser310_MiST/Laser310_MiST.qsf
deleted file mode 100644
index d112c6a2..00000000
--- a/Computer_MiST/Laser310_MiST/Laser310_MiST.qsf
+++ /dev/null
@@ -1,433 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 17:28:40  June 04, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		Laser310_MiST_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24  MAY 17, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Laser310_MiST.sv
-set_global_assignment -name VERILOG_FILE rtl/LASER310_TOP.v
-set_global_assignment -name VERILOG_FILE rtl/mc6847_vga.v
-set_global_assignment -name VERILOG_FILE rtl/PIXEL_DISPLAY.v
-set_global_assignment -name VERILOG_FILE rtl/CHAR_GEN.v
-set_global_assignment -name VERILOG_FILE rtl/PIXEL_GEN.v
-set_global_assignment -name VERILOG_FILE rtl/VIDEO_OUT.v
-set_global_assignment -name VERILOG_FILE rtl/SVGA_DEFINES.v
-set_global_assignment -name VERILOG_FILE rtl/SVGA_TIMING_GENERATION.v
-set_global_assignment -name VERILOG_FILE rtl/ps2_keyboard_glb.v
-set_global_assignment -name VERILOG_FILE rtl/tv80/tv80s.v
-set_global_assignment -name VERILOG_FILE rtl/tv80/tv80n.v
-set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_reg.v
-set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_mcode.v
-set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_core.v
-set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_alu.v
-set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_top.vhd
-set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_tone.vhd
-set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_noise.vhd
-set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_latch_ctrl.vhd
-set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_clock_div.vhd
-set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_attenuator.vhd
-set_global_assignment -name VHDL_FILE rtl/sprom.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name VERILOG_FILE rtl/reset_de.v
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name TEXT_FILE rtl/tv80/Text1.txt
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/LaserKeyboard.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/LaserCassEmu.sv
-set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PIN_49 -to SDRAM_A[0]
-set_location_assignment PIN_44 -to SDRAM_A[1]
-set_location_assignment PIN_42 -to SDRAM_A[2]
-set_location_assignment PIN_39 -to SDRAM_A[3]
-set_location_assignment PIN_4 -to SDRAM_A[4]
-set_location_assignment PIN_6 -to SDRAM_A[5]
-set_location_assignment PIN_8 -to SDRAM_A[6]
-set_location_assignment PIN_10 -to SDRAM_A[7]
-set_location_assignment PIN_11 -to SDRAM_A[8]
-set_location_assignment PIN_28 -to SDRAM_A[9]
-set_location_assignment PIN_50 -to SDRAM_A[10]
-set_location_assignment PIN_30 -to SDRAM_A[11]
-set_location_assignment PIN_32 -to SDRAM_A[12]
-set_location_assignment PIN_83 -to SDRAM_DQ[0]
-set_location_assignment PIN_79 -to SDRAM_DQ[1]
-set_location_assignment PIN_77 -to SDRAM_DQ[2]
-set_location_assignment PIN_76 -to SDRAM_DQ[3]
-set_location_assignment PIN_72 -to SDRAM_DQ[4]
-set_location_assignment PIN_71 -to SDRAM_DQ[5]
-set_location_assignment PIN_69 -to SDRAM_DQ[6]
-set_location_assignment PIN_68 -to SDRAM_DQ[7]
-set_location_assignment PIN_86 -to SDRAM_DQ[8]
-set_location_assignment PIN_87 -to SDRAM_DQ[9]
-set_location_assignment PIN_98 -to SDRAM_DQ[10]
-set_location_assignment PIN_99 -to SDRAM_DQ[11]
-set_location_assignment PIN_100 -to SDRAM_DQ[12]
-set_location_assignment PIN_101 -to SDRAM_DQ[13]
-set_location_assignment PIN_103 -to SDRAM_DQ[14]
-set_location_assignment PIN_104 -to SDRAM_DQ[15]
-set_location_assignment PIN_58 -to SDRAM_BA[0]
-set_location_assignment PIN_51 -to SDRAM_BA[1]
-set_location_assignment PIN_85 -to SDRAM_DQMH
-set_location_assignment PIN_67 -to SDRAM_DQML
-set_location_assignment PIN_60 -to SDRAM_nRAS
-set_location_assignment PIN_64 -to SDRAM_nCAS
-set_location_assignment PIN_66 -to SDRAM_nWE
-set_location_assignment PIN_59 -to SDRAM_nCS
-set_location_assignment PIN_33 -to SDRAM_CKE
-set_location_assignment PIN_43 -to SDRAM_CLK
-set_location_assignment PLL_1 -to "pll27:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name TOP_LEVEL_ENTITY Laser310_MiST
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# SignalTap II Assignments
-# ========================
-set_global_assignment -name ENABLE_SIGNALTAP OFF
-set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# ---------------------------
-# start ENTITY(Laser310_MiST)
-
-	# Pin & Location Assignments
-	# ==========================
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
-
-	# Fitter Assignments
-	# ==================
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[0]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[1]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[2]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[3]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[4]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[5]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[6]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[7]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[8]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[9]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[10]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[11]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[12]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[0]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[1]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[2]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[3]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[4]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[5]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[6]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[7]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[8]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[9]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[10]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[11]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[12]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[13]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[14]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[15]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_BA[0]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_BA[1]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQML
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQMH
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nRAS
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nCAS
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nWE
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nCS
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_CKE
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_CLK
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[5]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[4]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[3]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[2]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[1]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[0]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[5]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[4]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[3]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[2]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[1]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[0]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[5]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[4]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[3]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[2]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[1]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[0]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_HS
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_VS
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to LED
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_L
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_DO
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to CONF_DATA0
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_L
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_R
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CONF_DATA0
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DI
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DO
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCK
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS2
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS3
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[0]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[1]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[2]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[3]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[4]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[5]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[6]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[7]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[8]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[9]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[10]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[11]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[12]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQMH
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQML
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nRAS
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nCAS
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nWE
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nCS
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to CLOCK_27
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_DI
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SCK
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SS2
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SS3
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(Laser310_MiST)
-# -------------------------
-set_global_assignment -name VERILOG_FILE rtl/fdc.v
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Computer_MiST/Laser310_MiST/Laser310_MiST.sdc b/Computer_MiST/Laser310_MiST/Laser310_MiST.sdc
deleted file mode 100644
index 3eba3b05..00000000
--- a/Computer_MiST/Laser310_MiST/Laser310_MiST.sdc
+++ /dev/null
@@ -1,33 +0,0 @@
-#************************************************************
-# THIS IS A WIZARD-GENERATED FILE.                           
-#
-# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
-#
-#************************************************************
-
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-
-
-
-# Clock constraints
-
-create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}]
-create_clock -name {SPI_SCK}  -period 10.000 -waveform { 0.000 0.500 } [get_ports {SPI_SCK}]
-
-# Automatically constrain PLL and other generated clocks
-derive_pll_clocks -create_base_clocks
-
-# Automatically calculate clock uncertainty to jitter and other effects.
-derive_clock_uncertainty
diff --git a/Computer_MiST/Laser310_MiST/Laser310_MiST.srf b/Computer_MiST/Laser310_MiST/Laser310_MiST.srf
deleted file mode 100644
index 4eb6b36c..00000000
--- a/Computer_MiST/Laser310_MiST/Laser310_MiST.srf
+++ /dev/null
@@ -1,11 +0,0 @@
-{ "" "" "" "Verilog HDL warning at hq2x.sv(247): extended using \"x\" or \"z\"" {  } {  } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL warning at tv80_core.v(300): extended using \"x\" or \"z\"" {  } {  } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL macro warning at hq2x.sv(26): overriding existing definition for macro \"BITS_TO_FIT\", which was defined in \"rtl/scandoubler.v\", line 109" {  } {  } 0 10274 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10090 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332060 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10259 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10030 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Computer_MiST/Laser310_MiST/clean.bat b/Computer_MiST/Laser310_MiST/clean.bat
deleted file mode 100644
index 83fb0c47..00000000
--- a/Computer_MiST/Laser310_MiST/clean.bat
+++ /dev/null
@@ -1,15 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-del PLLJ_PLLSPE_INFO.txt
-del *.qws
-del *.ppf
-del *.qip
-del *.ddb
-pause
diff --git a/Computer_MiST/Laser310_MiST/compumuse.pdf b/Computer_MiST/Laser310_MiST/compumuse.pdf
deleted file mode 100644
index 98e067ee..00000000
Binary files a/Computer_MiST/Laser310_MiST/compumuse.pdf and /dev/null differ
diff --git a/Computer_MiST/Laser310_MiST/rtl/CHAR_GEN.v b/Computer_MiST/Laser310_MiST/rtl/CHAR_GEN.v
deleted file mode 100644
index a9d45ce9..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/CHAR_GEN.v
+++ /dev/null
@@ -1,68 +0,0 @@
-module CHAR_GEN(
-	// control
-	reset,
-
-	char_code,
-	subchar_line,
-	subchar_pixel,
-
-	pixel_clock,
-	pixel_on
-);
-
-input			pixel_clock;
-input			reset;
-
-input	[7:0]	char_code;
-input	[4:0]	subchar_line;			// line number within 12 line block
-input	[3:0]	subchar_pixel;			// pixel position within 8 pixel block
-
-output			pixel_on;
-
-reg		[7:0]	latched_data;
-reg				pixel_on;
-
-wire	[11:0]	rom_addr = {char_code[7:0], subchar_line[4:1]};
-wire	[7:0]	rom_data;
- 
-
-// instantiate the character generator ROM
-//CHAR_GEN_ROM CHAR_GEN_ROM
-//(
-//	pixel_clock,
-//	rom_addr,
-//	rom_data
-//);
-
-sprom #(
-	.init_file("./roms/charrom_4k.mif"),
-	.widthad_a(12),
-	.width_a(8))
-CHAR_GEN_ROM(
-	.address(rom_addr),
-	.clock(pixel_clock),
-	.q(rom_data)
-	);
-
-
-// serialize the CHARACTER MODE data
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
- 		begin
-			pixel_on = 1'b0;
-			latched_data  = 8'h00;
-		end
-
-	else begin
-		case(subchar_pixel)
-			4'b0101:
-				latched_data [7:0] = {rom_data[0],rom_data[1],rom_data[2],rom_data[3],rom_data[4],rom_data[5],rom_data[6],rom_data[7]};
-			default:
-			if(subchar_pixel[0]==1'b0)
-				{pixel_on,latched_data [7:1]} <= latched_data [7:0];
-		endcase
-		end
-
-	end
-
-endmodule //CHAR_GEN
diff --git a/Computer_MiST/Laser310_MiST/rtl/CHAR_GEN_ROM.v b/Computer_MiST/Laser310_MiST/rtl/CHAR_GEN_ROM.v
deleted file mode 100644
index 691de90e..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/CHAR_GEN_ROM.v
+++ /dev/null
@@ -1,19 +0,0 @@
-module CHAR_GEN_ROM
-(
-	pixel_clock,
-	address,
-	data
-);
-
-input				pixel_clock;
-input		[11:0]	address;
-output wire [7:0] 	data;
-
-// Character generator
-char_rom_4k_altera char_rom(
-	.address(address),
-	.clock(pixel_clock),
-	.q(data)
-);
-
-endmodule //CHAR_GEN_ROM
diff --git a/Computer_MiST/Laser310_MiST/rtl/LASER310_TOP.v b/Computer_MiST/Laser310_MiST/rtl/LASER310_TOP.v
deleted file mode 100644
index 58a9fa71..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/LASER310_TOP.v
+++ /dev/null
@@ -1,1179 +0,0 @@
-`timescale 1 ns / 1 ns
-`define BASE_SYS_ROM
-`define BASE_DOS_ROM
-`define BOOT_ROM_6000
-`define BASE_RAM_78//2k
-`define BASE_RAM_16K
-//`define RAM_16K_EXPANSION
-`define VRAM_2K
-//`define VRAM_8K
-`define SHRG
-//`ifdef CASS_EMU
-//`ifdef CASS_EMU_16K
-//`ifdef CASS_EMU_8K
-//`ifdef CASS_EMU_4K
-//`ifdef CASS_EMU_2K
-
-//Switches
-//  9 Latch BANK_4000
-//  8 Latch BANK_4000
-//  7 Latch BANK_4000
-//  6 Latch BANK_0000
-//  5 Latch BANK_0000
-//  4 Latch BANK_0000
-//  3 
-//  2 SHRG_EN
-//  1 Dosrom Enable
-//  0 Turbo
-
-								
-module LASER310_TOP(
-input				CLK50MHZ,
-input				CLK25MHZ,
-input				CLK10MHZ,
-input				RESET,//Active Low
-output	[7:0]	VGA_RED,
-output	[7:0]	VGA_GREEN,
-output	[7:0]	VGA_BLUE,
-output			VGA_HS,
-output			VGA_VS,
-output			blank,
-input				VIDEO_MODE,
-output	[1:0]	AUD_ADCDAT,
-output	[7:0]	audio_s,
-input				key_strobe,
-input				key_pressed,
-input		[7:0]	key_code,
-input		[9:0]	SWITCH,
-input				UART_RXD,
-output			UART_TXD
-               );
-
-reg		[3:0]		CLK;
-
-reg					MEM_OP_WR;
-//reg					MEM_RD;
-(*keep*)reg				GPIO_CPU_CLK;
-// Processor
-(*keep*)reg				CPU_CLK;
-(*keep*)wire[15:0]	CPU_A;
-(*keep*)wire [7:0]	CPU_DI;
-(*keep*)wire [7:0]	CPU_DO;
-(*keep*)wire			CPU_RESET;
-(*keep*)wire			CPU_HALT;
-(*keep*)wire			CPU_MREQ;
-(*keep*)wire			CPU_RD;
-(*keep*)wire			CPU_WR;
-(*keep*)wire			CPU_IORQ;
-(*keep*)reg				CPU_INT;
-(*keep*)wire			CPU_M1;
-wire						CPU_BUSRQ;
-wire						CPU_BUSAK;
-wire						CPU_RFSH;
-(*keep*)wire			CPU_RESET_N;
-(*keep*)wire			CPU_HALT_N;
-(*keep*)wire			CPU_MREQ_N;
-(*keep*)wire			CPU_RD_N;
-(*keep*)wire			CPU_WR_N;
-(*keep*)wire			CPU_IORQ_N;
-(*keep*)wire			CPU_INT_N;
-(*keep*)wire			CPU_M1_N;
-wire						CPU_BUSRQ_N;
-wire						CPU_BUSAK_N;
-wire						CPU_RFSH_N;
-// VRAM
-(*keep*)wire[12:0]	VRAM_ADDRESS;
-(*keep*)wire			VRAM_WR;
-(*keep*)wire [7:0]	VRAM_DATA_OUT;
-(*keep*)wire			VDG_RD;
-(*keep*)wire[12:0]	VDG_ADDRESS;
-(*keep*)wire [7:0]	VDG_DATA;
-// ROM IO RAM
-reg					LATCHED_DOSROM_EN;
-reg					LATCHED_BOOTROM_EN;
-reg					LATCHED_AUTOSTARTROM_EN;
-wire	[7:0]		SYS_ROM_DATA;
-wire	[7:0]		DOS_ROM_DATA;
-wire	[7:0]		AUTOSTART_ROM_DATA;
-wire	[7:0]		BOOT_ROM_6000_DATA;
-reg					BOOTROM_EN;
-reg		[7:0]		BOOTROM_BANK;
-reg					AUTOSTARTROM_EN;
-reg		[7:0]		AUTOSTARTROM_BANK;
-//wire	[7:0]		IO_DATA;
-//wire	[7:0]		IO_WR;
-wire				RAM_16K_WR;
-wire	[7:0]		RAM_16K_DATA_OUT;
-wire				RAM_78_WR;
-wire	[7:0]		RAM_78_DATA;
-wire				RAM_16K_EXP_WR;
-wire	[7:0]		RAM_16K_EXP_DATA_OUT;
-wire				RAM_89AB_WR;
-wire	[7:0]		RAM_89AB_DATA;
-wire				RAM_CDEF_WR;
-wire	[7:0]		RAM_CDEF_DATA;
-wire	[7:0]		MEM_CDEF_DATA_OUT;
-wire	[7:0]		RAM_89AB_DATA_OUT;
-wire	[7:0]		RAM_CDEF_DATA_OUT;
-wire				ADDRESS_ROM;
-wire				ADDRESS_DOSROM;
-wire				ADDRESS_IO;
-wire				ADDRESS_VRAM;
-wire				ADDRESS_BOOTROM_6000;
-wire				ADDRESS_AUTOSTARTROM;
-wire				ADDRESS_89AB;
-wire				ADDRESS_CDEF;
-wire				ADDRESS_RAM_78;
-wire				ADDRESS_RAM_16K;
-wire				ADDRESS_RAM_16K_EXP;
-wire				ADDRESS_IO_SHRG;
-wire				ADDRESS_IO_BANK;
-wire				ADDRESS_RAM_CHIP;
-reg		[7:0]		LATCHED_IO_DATA_WR;
-//reg	[7:0]		LATCHED_IO_DATA_RD;
-reg		[7:0]		LATCHED_BANK_0000;
-reg		[7:0]		LATCHED_BANK_4000;
-reg		[7:0]		LATCHED_BANK_C000;
-reg		[7:0]		LATCHED_BANK_4DEF;
-`ifdef SHRG
-reg					LATCHED_SHRG_EN;
-reg		[7:0]		LATCHED_IO_SHRG;
-`endif
-
-// keyboard
-reg		[4:0]		KB_CLK;
-
-wire	[7:0]		SCAN;
-wire				PRESS;
-wire				PRESS_N;
-wire				EXTENDED;
-
-reg		[63:0]		KEY;
-reg		[9:0]		KEY_EX;
-reg		[11:0]		KEY_Fxx;
-wire	[7:0]		KEY_DATA;
-//reg	[63:0]		LAST_KEY;
-//reg				CAPS_CLK;
-//reg				CAPS;
-wire				A_KEY_PRESSED;
-
-reg		[7:0]		LATCHED_KEY_DATA;
-
-// emu keyboard
-wire	[63:0]		EMU_KEY;
-wire	[9:0]		EMU_KEY_EX;
-wire				EMU_KEY_EN;
-// cassette
-
-(*keep*)wire	[1:0]	CASS_OUT;
-(*keep*)wire			CASS_IN;
-(*keep*)wire			CASS_IN_L;
-(*keep*)wire			CASS_IN_R;
-
-
-// 用于外部磁带仿真计数
-//(*keep*)reg				EMU_CASS_CLK;
-
-(*keep*)wire			EMU_CASS_EN;
-(*keep*)wire	[1:0]	EMU_CASS_DAT;
-
-
-reg		[16:0]		RESET_KEY_COUNT;
-wire				RESET_KEY_N, RESET_N;
-
-wire				TURBO_SPEED		=	SWITCH[0];
-
-
-RESET_DE RESET_DE(
-	.CLK(CLK50MHZ),
-	.SYS_RESET_N(RESET),
-	.RESET_N(RESET_N)
-);
-
-
-// 键盘 ctrl + f12 系统复位
-assign RESET_KEY_N = RESET_KEY_COUNT[16];
-
-reg 		[17:0]	INT_CNT;
-
-always @ (negedge CLK10MHZ)
-	case(INT_CNT[17:0])
-		18'd0:
-		begin
-			CPU_INT <= 1'b1;
-			INT_CNT <= 18'd1;
-		end
-		18'd640:
-		begin
-			CPU_INT <= 1'b0;
-			INT_CNT <= 18'd641;
-		end
-		18'd199999:
-		begin
-			INT_CNT <= 18'd0;
-		end
-		default:
-		begin
-			INT_CNT <= INT_CNT + 1;
-		end
-	endcase
-
-always @(posedge CLK50MHZ or negedge RESET_N)
-	if(~RESET_N)
-	begin
-		CPU_CLK					<=	1'b0;
-		GPIO_CPU_CLK			<=	1'b0;
-		// 复位期间设置，避免拨动开关引起错误
-		LATCHED_DOSROM_EN		<=	SWITCH[1];
-		LATCHED_BANK_0000		<=	{5'b0,SWITCH[6:4]};
-		LATCHED_BANK_4000		<=	{5'b0,SWITCH[9:7]};
-		LATCHED_BOOTROM_EN		<=	BOOTROM_EN;
-		LATCHED_AUTOSTARTROM_EN	<=	AUTOSTARTROM_EN;
-		//LATCHED_BOOTROM_EN		<=	1'b0;
-`ifdef SHRG
-		LATCHED_IO_SHRG			<=	8'b00001000;
-		// 复位期间设置，避免拨动开关引起错误
-		LATCHED_SHRG_EN			<=	SWITCH[2];
-`endif
-`ifdef IO_BANK
-		if(BOOTROM_EN)
-			LATCHED_BANK_C000		<=	BOOTROM_BANK;
-		else
-			LATCHED_BANK_C000		<=	8'b0;
-		if(AUTOSTARTROM_EN)
-			LATCHED_BANK_4DEF		<=	AUTOSTARTROM_BANK;
-		else
-			LATCHED_BANK_4DEF		<=	8'b0;
-`endif
-
-
-		MEM_OP_WR				<=	1'b0;
-
-		LATCHED_KEY_DATA		<=	8'b0;
-		LATCHED_IO_DATA_WR		<=	8'b0;
-		//EMU_CASS_CLK <= 1'b0;
-		CLK						<=	4'd0;
-	end
-	else
-	begin
-		case (CLK[3:0])
-		4'd0:
-			begin
-				// 同步内存，等待读写信号建立
-				CPU_CLK				<=	1'b1;
-				GPIO_CPU_CLK		<=	1'b1;
-				MEM_OP_WR			<=	1'b1;
-				//EMU_CASS_CLK <= ~EMU_CASS_CLK;
-				CLK					<=	4'd1;
-			end
-
-		4'd1:
-			begin
-				// 同步内存，锁存读写信号和地址
-				CPU_CLK				<=	1'b0;
-				MEM_OP_WR			<=	1'b0;
-				LATCHED_KEY_DATA	<=	KEY_DATA;
-				if({CPU_MREQ,CPU_RD,CPU_WR,ADDRESS_IO}==4'b1011)
-					LATCHED_IO_DATA_WR	<=	CPU_DO;
-`ifdef SHRG
-				if(LATCHED_SHRG_EN)
-					if({CPU_IORQ,CPU_RD,CPU_WR,ADDRESS_IO_SHRG}==4'b1011)
-						LATCHED_IO_SHRG		<=	CPU_DO;
-`endif
-`ifdef IO_BANK
-				if({CPU_IORQ,CPU_RD,CPU_WR,ADDRESS_IO_BANK}==4'b1011)
-					LATCHED_BANK_C000	<=	CPU_DO;
-`endif
-				CLK					<=	4'd2;
-			end
-
-		4'd2:
-			begin
-				// 完成读写操作，开始输出
-				CPU_CLK				<=	1'b0;
-				GPIO_CPU_CLK		<=	~TURBO_SPEED;
-
-				MEM_OP_WR			<=	1'b0;
-				CLK					<=	4'd3;
-			end
-		4'd3:
-			begin
-				if(TURBO_SPEED)
-					CLK				<=	4'd0;
-				else
-					CLK				<=	4'd4;
-			end
-		4'd7:
-			begin
-				CPU_CLK				<=	1'b0;
-				GPIO_CPU_CLK		<=	1'b0;
-				MEM_OP_WR			<=	1'b0;
-				CLK					<=	4'd8;
-			end
-		4'd13:// 正常速度
-			begin
-				CPU_CLK				<=	1'b0;
-				MEM_OP_WR			<=	1'b0;
-				CLK					<=	4'd0;
-			end
-		default:
-			begin
-				CPU_CLK				<=	1'b0;
-				MEM_OP_WR			<=	1'b0;
-				CLK					<=	CLK + 1'b1;
-			end
-		endcase
-	end
-
-// CPU
-assign CPU_RESET = ~RESET_N;
-assign CPU_M1 = ~CPU_M1_N;
-assign CPU_MREQ = ~CPU_MREQ_N;
-assign CPU_IORQ = ~CPU_IORQ_N;
-assign CPU_RD = ~CPU_RD_N;
-assign CPU_WR = ~CPU_WR_N;
-assign CPU_RFSH = ~CPU_RFSH_N;
-assign CPU_HALT= ~CPU_HALT_N;
-assign CPU_BUSAK = ~CPU_BUSAK_N;
-assign CPU_RESET_N = ~CPU_RESET;
-assign CPU_INT_N = VIDEO_MODE ? ~CPU_INT : ~VGA_VS;
-assign CPU_BUSRQ_N = ~CPU_BUSRQ;
-
-tv80s Z80CPU (
-	.m1_n(CPU_M1_N),
-	.mreq_n(CPU_MREQ_N),
-	.iorq_n(CPU_IORQ_N),
-	.rd_n(CPU_RD_N),
-	.wr_n(CPU_WR_N),
-	.rfsh_n(CPU_RFSH_N),
-	.halt_n(CPU_HALT_N),
-	.busak_n(CPU_BUSAK_N),
-	.A(CPU_A),
-	.dout(CPU_DO),
-	.reset_n(CPU_RESET_N),
-	.clk(CPU_CLK),
-	.wait_n(1'b1),
-	.int_n(CPU_INT_N),
-	.nmi_n(1'b1),
-	.busrq_n(CPU_BUSRQ_N),
-	.di(CPU_DI)
-);
-
-
-// 0000 -- 3FFF ROM 16KB
-// 4000 -- 5FFF DOS
-// 6000 -- 67FF BOOT ROM
-// 6800 -- 6FFF I/O
-// 7000 -- 77FF VRAM 2KB (SRAM 6116)
-// 7800 -- 7FFF RAM 2KB
-// 8000 -- B7FF RAM 14KB
-// B800 -- BFFF RAM ext 2KB
-// C000 -- F7FF RAM ext 14KB
-
-assign ADDRESS_ROM				=	(CPU_A[15:14] == 2'b00)?1'b1:1'b0;
-assign ADDRESS_DOSROM			=	(CPU_A[15:13] == 3'b010)?LATCHED_DOSROM_EN:1'b0;
-assign ADDRESS_BOOTROM_6000		=	(CPU_A[15:11] == 5'b01100)?LATCHED_BOOTROM_EN:1'b0;
-assign ADDRESS_AUTOSTARTROM		=	(CPU_A[15:12] == 4'h4||CPU_A[15:12] == 4'hD||CPU_A[15:12] == 4'hE||CPU_A[15:12] == 4'hF)?LATCHED_AUTOSTARTROM_EN:1'b0;
-assign ADDRESS_IO				=	(CPU_A[15:11] == 5'b01101)?1'b1:1'b0;
-assign ADDRESS_VRAM				=	(CPU_A[15:11] == 5'b01110)?1'b1:1'b0;
-assign ADDRESS_89AB				=	(CPU_A[15:14] == 2'b10)?1'b1:1'b0;
-assign ADDRESS_CDEF				=	(CPU_A[15:14] == 2'b11)?1'b1:1'b0;
-// 7800 -- 7FFF RAM 2KB
-assign ADDRESS_RAM_78			=	(CPU_A[15:11] == 5'b01111)?1'b1:1'b0;
-// 7800 -- 7FFF RAM 2KB
-// 8000 -- B7FF RAM 14KB
-
-assign ADDRESS_RAM_16K		=	(CPU_A[15:12] == 4'h8)?1'b1:
-								(CPU_A[15:12] == 4'h9)?1'b1:
-								(CPU_A[15:12] == 4'hA)?1'b1:
-								(CPU_A[15:11] == 5'b01111)?1'b1:
-								(CPU_A[15:11] == 5'b10110)?1'b1:
-								1'b0;
-
-// B800 -- BFFF RAM ext 2KB
-// C000 -- F7FF RAM ext 14KB
-
-assign ADDRESS_RAM_16K_EXP	=	(CPU_A[15:12] == 4'hC)?1'b1:
-								(CPU_A[15:12] == 4'hD)?1'b1:
-								(CPU_A[15:12] == 4'hE)?1'b1:
-								(CPU_A[15:11] == 5'b10111)?1'b1:
-								(CPU_A[15:11] == 5'b11110)?1'b1:
-								1'b0;
-
-assign ADDRESS_IO_SHRG		=	(CPU_A[7:0] == 8'd32)?1'b1:1'b0;
-
-// 64K RAM expansion cartridge vz300_review.pdf 中的端口号是 IO 7FH 127
-// 128K SIDEWAYS RAM SHRG2 HVVZUG23 (Mar-Apr 1989).PDF 中的端口号是 IO 112
-
-assign ADDRESS_IO_BANK	=	(CPU_A[7:0] == 8'd127 || CPU_A[7:0] == 8'd112)?1'b1:1'b0;
-
-
-
-
-`ifdef RAM_16K_EXPANSION
-assign	ADDRESS_RAM_CHIP	=	ADDRESS_RAM_16K|ADDRESS_RAM_16K_EXP;
-`else
-assign	ADDRESS_RAM_CHIP	=	ADDRESS_RAM_16K;
-`endif
-
-
-
-assign VRAM_WR			= ({ADDRESS_VRAM,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
-assign RAM_78_WR		= ({ADDRESS_RAM_78,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
-assign RAM_16K_WR		= ({ADDRESS_RAM_16K,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
-assign RAM_16K_EXP_WR	= ({ADDRESS_RAM_16K_EXP,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
-
-
-assign RAM_89AB_WR		= ({ADDRESS_89AB,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
-assign RAM_CDEF_WR		= ({ADDRESS_CDEF,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
-
-assign RAM_89AB_WR		= ({ADDRESS_89AB,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
-assign RAM_CDEF_WR		= ({ADDRESS_CDEF,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
-
-
-assign CPU_DI = 	ADDRESS_ROM				? SYS_ROM_DATA			:
-						ADDRESS_AUTOSTARTROM	? AUTOSTART_ROM_DATA	:
-						ADDRESS_DOSROM			? DOS_ROM_DATA			:
-`ifdef BOOT_ROM_6000
-						ADDRESS_BOOTROM_6000	? BOOT_ROM_6000_DATA	:
-`endif
-						ADDRESS_IO				? LATCHED_KEY_DATA		:
-						ADDRESS_VRAM			? VRAM_DATA_OUT			:
-`ifdef BASE_RAM_16K
-						ADDRESS_RAM_16K			? RAM_16K_DATA_OUT		:
-`endif
-`ifdef RAM_16K_EXPANSION
-						ADDRESS_RAM_16K_EXP		? RAM_16K_EXP_DATA_OUT	:
-`endif
-					8'hzz;
-
-
-
-
-`ifdef BASE_SYS_ROM
-sprom #(
-	.init_file("./roms/sysrom.mif"),
-	.widthad_a(14),
-	.width_a(8))
-sys_rom(
-	.address(CPU_A[13:0]),
-	.clock(CLK50MHZ),
-	.q(SYS_ROM_DATA)
-	);
-`endif
-
-`ifdef BASE_DOS_ROM
-sprom #(
-	.init_file("./roms/dosrom.mif"),
-	.widthad_a(13),
-	.width_a(8))
-DOS_ROM(
-	.address(CPU_A[12:0]),
-	.clock(CLK50MHZ),
-	.q(DOS_ROM_DATA)
-	);
-`endif
-
-`ifdef BOOT_ROM_6000
-sprom #(
-	.init_file("./roms/boot_rom_6000.mif"),
-	.widthad_a(9),
-	.width_a(8))
-BOOT_ROM(
-	.address(CPU_A[8:0]),
-	.clock(CLK50MHZ),
-	.q(BOOT_ROM_6000_DATA)
-	);
-`endif
-
-`ifdef BASE_RAM_78
-spram #(
-	. addr_width_g(11),
-	.data_width_g(8))
-BASE_RAM78(
-	.address(CPU_A[10:0]),
-	.clken(1),
-	.clock(CLK50MHZ),
-	.data(CPU_DO),
-	.wren(CPU_MREQ & RAM_78_WR),
-	.q(RAM_78_DATA)
-	);
-`endif
-
-`ifdef BASE_RAM_16K
-spram #(
-	. addr_width_g(14),
-	.data_width_g(8))
-BASE_RAM16k(
-	.address(CPU_A[13:0]),
-	.clken(1),
-	.clock(CLK50MHZ),
-	.data(CPU_DO),
-	.wren(CPU_MREQ & RAM_16K_WR),
-	.q(RAM_16K_DATA_OUT)
-	);
-`else
-assign	RAM_16K_DATA_OUT		=	8'bz;
-`endif
-
-`ifdef RAM_16K_EXPANSION
-spram #(
-	. addr_width_g(14),
-	.data_width_g(8))
-BASE_RAM16kex(
-	.address(CPU_A[13:0]),
-	.clken(1),
-	.clock(CLK50MHZ),
-	.data(CPU_DO),
-	.wren(CPU_MREQ & RAM_16K_EXP_WR),
-	.q(RAM_16K_EXP_DATA_OUT)
-	);
-`else
-assign	RAM_16K_EXP_DATA_OUT	=	8'bz;
-`endif
-
-
-`ifdef VRAM_2K
-dpram #(
-	.addr_width_g(11),
-	.data_width_g(8))
-vram_2k(
-	.clk_a_i(CLK50MHZ),
-	.en_a_i(1),
-	.we_i(CPU_MREQ & VRAM_WR),
-	.addr_a_i(CPU_A[10:0]),
-	.data_a_i(CPU_DO),
-	.data_a_o(VRAM_DATA_OUT),
-	.clk_b_i(VDG_RD),
-	.addr_b_i(VDG_ADDRESS[10:0]),
-	.data_b_o(VDG_DATA)
-	);
-`endif
-
-
-`ifdef VRAM_8K
-dpram #(
-	.addr_width_g(13),
-	.data_width_g(8))
-vram_8k(
-	.clk_a_i(CLK50MHZ),
-	.en_a_i(1),
-	.we_i(CPU_MREQ & VRAM_WR),
-	.addr_a_i({LATCHED_IO_SHRG[1:0],CPU_A[10:0]}),
-	.data_a_i(CPU_DO),
-	.data_a_o(VRAM_DATA_OUT),
-	.clk_b_i(VDG_RD),
-	.addr_b_i(VDG_ADDRESS[12:0]),
-	.data_b_o(VDG_DATA)
-	);
-`endif
-
-MC6847_VGA MC6847_VGA(
-	.PIX_CLK(CLK25MHZ),
-	.RESET_N(RESET_N),
-	.RD(VDG_RD),
-	.DD(VDG_DATA),
-	.DA(VDG_ADDRESS),
-	.AG(LATCHED_IO_DATA_WR[3]),
-	.AS(1'b0),
-	.EXT(1'b0),
-	.INV(1'b0),
-`ifdef SHRG
-	.GM(LATCHED_IO_SHRG[4:2]),
-`else
-	.GM(3'b010),
-`endif
-	.CSS(LATCHED_IO_DATA_WR[4]),
-	// vga
-	.blank(blank),
-	.VGA_OUT_HSYNC(VGA_HS),
-	.VGA_OUT_VSYNC(VGA_VS),
-	.VGA_OUT_RED(VGA_RED),
-	.VGA_OUT_GREEN(VGA_GREEN),
-	.VGA_OUT_BLUE(VGA_BLUE)
-);
-
-
-// keyboard
-
-/*****************************************************************************
-* Convert PS/2 keyboard to ASCII keyboard
-******************************************************************************/
-
-/*
-   KD5 KD4 KD3 KD2 KD1 KD0 扫描用地址
-A0  R   Q   E       W   T  68FEH       0
-A1  F   A   D  CTRL S   G  68FDH       8
-A2  V   Z   C  SHFT X   B  68FBH      16
-A3  4   1   3       2   5  68F7H      24
-A4  M  空格 ，      .   N  68EFH      32
-A5  7   0   8   -   9   6  68DFH      40
-A6  U   P   I  RETN O   Y  68BFH      48
-A7  J   ；  K   :   L   H  687FH      56
-*/
-
-//  7: 0
-// 15: 8
-// 23:16
-// 31:24
-// 39:32
-// 47:40
-// 55:48
-// 63:56
-
-
-
-// 键盘检测的方法，就是循环地问每一行线发送低电平信号，也就是用该地址线为“0”的地址去读取数据。
-// 例如，检测第一行时，使A0为0，其余为1；加上选通IC4的高五位地址01101，成为01101***11111110B（A8~A10不起作用，
-// 可为任意值，故68FEH，69FEH，6AFEH，6BFEH，6CFEH，6DFEH，6EFEH，6FFEH均可）。
-// 读 6800H 判断是否有按键按下。
-
-// The method of keyboard detection is to cyclically ask each line to send a low level signal, 
-// that is, to read the data with the address line "0".
-// For example, when detecting the first line, make A0 0 and the rest 1; plus the high five-bit address 01101 of the strobe IC4, 
-// become 01101***11111110B (A8~A10 does not work,
-// It can be any value, so 68FEH, 69FEH, 6AFEH, 6BFEH, 6CFEH, 6DFEH, 6EFEH, 6FFEH can be).
-// Read 6800H to determine if there is a button press.
-
-// 键盘选通，整个竖列有一个选通的位置被按下，对应值为0。
-// The keyboard is strobed, and a strobe position is pressed in the entire vertical column, and the corresponding value is 0.
-
-// 键盘扩展
-// 加入方向键盘
-// Keyboard extension
-
-// left:  ctrl M      37 KEY_EX[5]
-// right: ctrl ,      35 KEY_EX[6]
-// up:    ctrl .      33 KEY_EX[4]
-// down:  ctrl space  36 KEY_EX[7]
-// esc:   ctrl -      42 KEY_EX[3]
-// backspace:  ctrl M      37 KEY_EX[8]
-
-// R-Shift
-
-
-wire	[63:0]	KEY_C		=	EMU_KEY_EN?EMU_KEY:KEY;
-wire	[9:0]	KEY_EX_C	=	EMU_KEY_EN?EMU_KEY_EX:KEY_EX;
-
-//wire KEY_CTRL_ULRD = (KEY_EX[7:4]==4'b1111);
-wire KEY_CTRL_ULRD_BRK = (KEY_EX[8:3]==6'b111111);
-
-wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY_C[61], KEY_C[53], KEY_C[45],           KEY_C[37]&KEY_EX_C[5]&KEY_EX_C[8], KEY_C[29], KEY_C[21],           KEY_C[13],                   KEY_C[ 5]})==8'hff;
-wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY_C[60], KEY_C[52], KEY_C[44],           KEY_C[36]&KEY_EX_C[7], KEY_C[28], KEY_C[20],           KEY_C[12],                   KEY_C[ 4]})==8'hff;
-wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY_C[59], KEY_C[51], KEY_C[43],           KEY_C[35]&KEY_EX_C[6], KEY_C[27], KEY_C[19],           KEY_C[11],                   KEY_C[ 3]})==8'hff;
-wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY_C[58], KEY_C[50], KEY_C[42]&KEY_EX_C[3], KEY_C[34],           KEY_C[26], KEY_C[18]&KEY_EX_C[0], KEY_C[10]&KEY_CTRL_ULRD_BRK, KEY_C[ 2]})==8'hff;
-wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY_C[57], KEY_C[49], KEY_C[41],           KEY_C[33]&KEY_EX_C[4], KEY_C[25], KEY_C[17],           KEY_C[ 9],                   KEY_C[ 1]})==8'hff;
-wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY_C[56], KEY_C[48], KEY_C[40],           KEY_C[32],             KEY_C[24], KEY_C[16],           KEY_C[ 8],                   KEY_C[ 0]})==8'hff;
-
-/*
-wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY[61], KEY[53], KEY[45], KEY[37], KEY[29], KEY[21], KEY[13], KEY[ 5]})==8'hff;
-wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY[60], KEY[52], KEY[44], KEY[36], KEY[28], KEY[20], KEY[12], KEY[ 4]})==8'hff;
-wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY[59], KEY[51], KEY[43], KEY[35], KEY[27], KEY[19], KEY[11], KEY[ 3]})==8'hff;
-wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY[58], KEY[50], KEY[42], KEY[34], KEY[26], KEY[18], KEY[10], KEY[ 2]})==8'hff;
-wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY[57], KEY[49], KEY[41], KEY[33], KEY[25], KEY[17], KEY[ 9], KEY[ 1]})==8'hff;
-wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY[56], KEY[48], KEY[40], KEY[32], KEY[24], KEY[16], KEY[ 8], KEY[ 0]})==8'hff;
-*/
-
-wire KEY_DATA_BIT7 = 1'b1;	// 没有空置，具体用途没有理解
-//wire KEY_DATA_BIT6 = CASS_IN;
-wire KEY_DATA_BIT6 = ~CASS_IN;
-
-assign KEY_DATA = { KEY_DATA_BIT7, KEY_DATA_BIT6, KEY_DATA_BIT5, KEY_DATA_BIT4, KEY_DATA_BIT3, KEY_DATA_BIT2, KEY_DATA_BIT1, KEY_DATA_BIT0 };
-
-/*
-assign KEY_DATA = 	(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
-					(CPU_A[1]==1'b0) ? KEY[15: 8] :
-					(CPU_A[2]==1'b0) ? KEY[23:16] :
-					(CPU_A[3]==1'b0) ? KEY[31:24] :
-					(CPU_A[4]==1'b0) ? KEY[39:32] :
-					(CPU_A[5]==1'b0) ? KEY[47:40] :
-					(CPU_A[6]==1'b0) ? KEY[55:48] :
-					(CPU_A[7]==1'b0) ? KEY[63:56] :
-					8'hff;
-
-assign KEY_DATA =
-					(CPU_A[7]==1'b0) ? KEY[63:56] :
-					(CPU_A[6]==1'b0) ? KEY[55:48] :
-					(CPU_A[5]==1'b0) ? KEY[47:40] :
-					(CPU_A[4]==1'b0) ? KEY[39:32] :
-					(CPU_A[3]==1'b0) ? KEY[31:24] :
-					(CPU_A[2]==1'b0) ? KEY[23:16] :
-					(CPU_A[1]==1'b0) ? KEY[15: 8] :
-					(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
-					8'hff;
-*/
-
-
-assign A_KEY_PRESSED = (KEY[63:0] == 64'hFFFFFFFFFFFFFFFF) ? 1'b0:1'b1;
-
-always @(posedge KB_CLK[3] or negedge RESET)
-begin
-	if(~RESET)
-	begin
-		KEY					<=	64'hFFFFFFFFFFFFFFFF;
-		KEY_EX				<=	10'h3FF;
-		KEY_Fxx				<=	12'h000;
-//		CAPS_CLK			<=	1'b0;
-		RESET_KEY_COUNT		<=	17'h1FFFF;
-
-		BOOTROM_BANK		<=	0;
-		BOOTROM_EN			<=	1'b0;
-
-		AUTOSTARTROM_BANK	<=	0;
-		AUTOSTARTROM_EN		<=	1'b0;
-	end
-	else
-	begin
-		//KEY[?] <= CAPS;
-		if(RESET_KEY_COUNT[16]==1'b0)
-			RESET_KEY_COUNT <= RESET_KEY_COUNT+1;
-
-		case(key_code)
-		8'h07:
-		begin
-				KEY_Fxx[11]	<= PRESS;	// F12 RESET
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b0;
-					BOOTROM_BANK		<=	0;
-					AUTOSTARTROM_EN		<=	1'b0;
-					AUTOSTARTROM_BANK	<=	0;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h78:	KEY_Fxx[10] <= PRESS;	// F11
-		8'h09:	KEY_Fxx[ 9] <= PRESS;	// F10 CASS STOP
-		8'h01:	KEY_Fxx[ 8] <= PRESS;	// F9  CASS PLAY
-		8'h0A:
-		begin
-				KEY_Fxx[ 7] <= PRESS;	// F8  Ctrl or L-Shift BOOT 8
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	39;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	23;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h83:
-		begin
-				KEY_Fxx[ 6] <= PRESS;	// F7  Ctrl or L-Shift BOOT 7
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	38;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	22;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h0B:
-		begin
-				KEY_Fxx[ 5] <= PRESS;	// F6  Ctrl or L-Shift BOOT 6
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	37;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	21;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h03:
-		begin
-				KEY_Fxx[ 4] <= PRESS;	// F5  Ctrl or L-Shift BOOT 5
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	36;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	20;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h0C:
-		begin
-				KEY_Fxx[ 3] <= PRESS;	// F4  Ctrl or L-Shift BOOT 4
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	35;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	19;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h04:
-		begin
-				KEY_Fxx[ 2] <= PRESS;	// F3  Ctrl or L-Shift BOOT 3
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	34;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	18;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h06:
-		begin
-				KEY_Fxx[ 1] <= PRESS;	// F2  Ctrl or L-Shift BOOT 2
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	33;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	17;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h05:
-		begin
-				KEY_Fxx[ 0] <= PRESS;	// F1  Ctrl or L-Shift BOOT 1
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	32;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	16;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-
-		8'h16:	KEY[28] <= PRESS_N;	// 1 !
-		8'h1E:	KEY[25] <= PRESS_N;	// 2 @
-		8'h26:	KEY[27] <= PRESS_N;	// 3 #
-		8'h25:	KEY[29] <= PRESS_N;	// 4 $
-		8'h2E:	KEY[24] <= PRESS_N;	// 5 %
-		8'h36:	KEY[40] <= PRESS_N;	// 6 ^
-		8'h3D:	KEY[45] <= PRESS_N;	// 7 &
-//		8'h0D:	KEY[?] <= PRESS_N;	// TAB
-		8'h3E:	KEY[43] <= PRESS_N;	// 8 *
-		8'h46:	KEY[41] <= PRESS_N;	// 9 (
-		8'h45:	KEY[44] <= PRESS_N;	// 0 )
-		8'h4E:	KEY[42] <= PRESS_N;	// - _
-//		8'h55:	KEY[?] <= PRESS_N;	// = +
-		8'h66:	KEY_EX[8] <= PRESS_N;	// backspace
-//		8'h0E:	KEY[?] <= PRESS_N;	// ` ~
-//		8'h5D:	KEY[?] <= PRESS_N;	// \ |
-		8'h49:	KEY[33] <= PRESS_N;	// . >
-		8'h4b:	KEY[57] <= PRESS_N;	// L
-		8'h44:	KEY[49] <= PRESS_N;	// O
-//		8'h11	KEY[?] <= PRESS_N; // line feed (really right ALT (Extended) see below
-		8'h5A:	KEY[50] <= PRESS_N;	// CR
-//		8'h54:	KEY[?] <= PRESS_N;	// [ {
-//		8'h5B:	KEY[?] <= PRESS_N;	// ] }
-		8'h52:	KEY[58] <= PRESS_N;	// ' "
-		8'h1D:	KEY[ 1] <= PRESS_N;	// W
-		8'h24:	KEY[ 3] <= PRESS_N;	// E
-		8'h2D:	KEY[ 5] <= PRESS_N;	// R
-		8'h2C:	KEY[ 0] <= PRESS_N;	// T
-		8'h35:	KEY[48] <= PRESS_N;	// Y
-		8'h3C:	KEY[53] <= PRESS_N;	// U
-		8'h43:	KEY[51] <= PRESS_N;	// I
-		8'h1B:	KEY[ 9] <= PRESS_N;	// S
-		8'h23:	KEY[11] <= PRESS_N;	// D
-		8'h2B:	KEY[13] <= PRESS_N;	// F
-		8'h34:	KEY[ 8] <= PRESS_N;	// G
-		8'h33:	KEY[56] <= PRESS_N;	// H
-		8'h3B:	KEY[61] <= PRESS_N;	// J
-		8'h42:	KEY[59] <= PRESS_N;	// K
-		8'h22:	KEY[17] <= PRESS_N;	// X
-		8'h21:	KEY[19] <= PRESS_N;	// C
-		8'h2a:	KEY[21] <= PRESS_N;	// V
-		8'h32:	KEY[16] <= PRESS_N;	// B
-		8'h31:	KEY[32] <= PRESS_N;	// N
-		8'h3a:	KEY[37] <= PRESS_N;	// M
-		8'h41:	KEY[35] <= PRESS_N;	// , <
-		8'h15:	KEY[ 4] <= PRESS_N;	// Q
-		8'h1C:	KEY[12] <= PRESS_N;	// A
-		8'h1A:	KEY[20] <= PRESS_N;	// Z
-		8'h29:	KEY[36] <= PRESS_N;	// Space
-//		8'h4A:	KEY[?] <= PRESS_N;	// / ?
-		8'h4C:	KEY[60] <= PRESS_N;	// ; :
-		8'h4D:	KEY[52] <= PRESS_N;	// P
-		8'h14:	KEY[10] <= PRESS_N;	// Ctrl either left or right
-		8'h12:	KEY[18] <= PRESS_N;	// L-Shift
-		8'h59:	KEY_EX[0] <= PRESS_N;	// R-Shift
-		8'h11:
-		begin
-			if(~EXTENDED)
-					KEY_EX[1] <= PRESS_N;	// Repeat really left ALT
-			else
-					KEY_EX[2] <= PRESS_N;	// LF really right ALT
-		end
-		8'h76:	KEY_EX[3] <= PRESS_N;	// Esc
-		8'h75:	KEY_EX[4] <= PRESS_N;	// up
-		8'h6B:	KEY_EX[5] <= PRESS_N;	// left
-		8'h74:	KEY_EX[6] <= PRESS_N;	// right
-		8'h72:	KEY_EX[7] <= PRESS_N;	// down
-		endcase
-	end
-end
-
-
-
-
-always @ (posedge CLK50MHZ)				// 50MHz
-	KB_CLK <= KB_CLK + 1'b1;			// 50/32 = 1.5625 MHz
-
-assign PRESS_N = ~key_pressed;
-
-
-`ifdef CASS_EMU
-
-wire			CASS_BUF_RD;
-wire	[15:0]	CASS_BUF_A;
-wire			CASS_BUF_WR;
-wire	[7:0]	CASS_BUF_DAT;
-wire	[7:0]	CASS_BUF_Q;
-
-// F9    CASS PLAY
-// F10   CASS STOP
-
-EMU_CASS_KEY	EMU_CASS_KEY(
-	KEY_Fxx[8],
-	KEY_Fxx[9],
-	// cass emu
-	CASS_BUF_RD,
-	//
-	CASS_BUF_A,
-	CASS_BUF_WR,
-	CASS_BUF_DAT,
-	CASS_BUF_Q,
-	//	Control Signals
-	EMU_CASS_EN,
-	EMU_CASS_DAT,
-
-	// key emu
-	EMU_KEY,
-	EMU_KEY_EX,
-	EMU_KEY_EN,
-    /*
-     * UART: 115200 bps, 8N1
-     */
-    UART_RXD,
-    UART_TXD,
-
-	// System
-	TURBO_SPEED,
-	// Clock: 10MHz
-	CLK10MHZ,
-	RESET_N
-);
-
-
-`ifdef CASS_EMU_16K
-
-cass_ram_16k_altera cass_buf(
-	.address(CASS_BUF_A[13:0]),
-	.clock(CLK10MHZ),
-	.data(CASS_BUF_DI),
-	.wren(CASS_BUF_WR),
-	.q(CASS_BUF_Q)
-);
-
-`endif
-
-
-`ifdef CASS_EMU_8K
-
-cass_ram_8k_altera cass_buf(
-	.address(CASS_BUF_A[12:0]),
-	.clock(CLK10MHZ),
-	.data(CASS_BUF_DI),
-	.wren(CASS_BUF_WR),
-	.q(CASS_BUF_Q)
-);
-
-`endif
-
-
-`ifdef CASS_EMU_4K
-
-cass_ram_4k_altera cass_buf(
-	.address(CASS_BUF_A[11:0]),
-	.clock(CLK10MHZ),
-	.data(CASS_BUF_DAT),
-	.wren(CASS_BUF_WR),
-	.q(CASS_BUF_Q)
-);
-
-`endif
-
-
-`ifdef CASS_EMU_2K
-
-cass_ram_2k_altera cass_buf(
-	.address(CASS_BUF_A[10:0]),
-	.clock(CLK10MHZ),
-	.data(CASS_BUF_DAT),
-	.wren(CASS_BUF_WR),
-	.q(CASS_BUF_Q)
-);
-
-`endif
-
-`endif
-
-sn76489_top #(
-	.clock_div_16_g(1))
-sn76489(
-   .clock_i(CLK25MHZ),
-   .clock_en_i(CPU_CLK),
-   .res_n_i(RESET),
-   .ce_n_i(),//todo
-   .we_n_i(),//todo
-   .ready_o(),
-   .d_i(CPU_DO),
-   .aout_o(audio_s)
-  );
-
-assign	CASS_OUT = EMU_CASS_EN ? EMU_CASS_DAT : {LATCHED_IO_DATA_WR[2], 1'b0};
-
-(*keep*)wire trap = (CPU_RD|CPU_WR) && (CPU_A[15:12] == 4'h0);
-
-assign AUD_ADCDAT = {LATCHED_IO_DATA_WR[0],LATCHED_IO_DATA_WR[5]};
-
-
-// floppy
-wire				ADDRESS_IO_FDC;
-wire				ADDRESS_IO_FDC_CT;
-wire				ADDRESS_IO_FDC_DATA;
-wire				ADDRESS_IO_FDC_POLL;
-wire				ADDRESS_IO_FDC_WP;
-reg		[7:0]		LATCHED_IO_FDC;
-reg		[7:0]		LATCHED_IO_FDC_CT;
-reg		[7:0]		LATCHED_RAM_DATA_FDC;
-
-// floppy
-(*keep*)wire					FDC_RAM_R;
-(*keep*)wire					FDC_RAM_W;
-(*keep*)wire		[17:0]		FDC_RAM_ADDR_R;
-(*keep*)wire		[17:0]		FDC_RAM_ADDR_W;
-reg			[7:0]		LAST_WRITE_DATA;
-(*keep*)wire		[7:0]		FDC_RAM_DATA_W;
-
-(*keep*)wire	[7:0]		FLOPPY_RD_DATA;
-(*keep*)wire	[7:0]		FLOPPY_DATA;
-
-// FDC
-//				if({CPU_IORQ,CPU_RD,CPU_WR,ADDRESS_IO_FDC_CT}==4'b1011)
-//					LATCHED_IO_FDC_CT	<=	CPU_DO;
-
-//				if({CPU_IORQ,CPU_RD,CPU_WR}==3'b110)
-//					LATCHED_IO_FDC	<=	ADDRESS_IO_FDC_POLL	?	{FDC_POLL, 7'h7F}	:
-//										ADDRESS_IO_FDC_DATA	?	FDC_DATA			:
-//										ADDRESS_IO_FDC_WP	?	{FDC_WP, 7'h7F}		:
-//										8'hFF;
-wire FLOPPY_WP_READ	= 1'b0;
-wire RAM_ADDRESS_FD_R	=		FDC_RAM_ADDR_R;
-wire RAM_ADDRESS_FD_W	=		FDC_RAM_ADDR_W;
-
-assign ADDRESS_IO_FDC	=	(CPU_A[7:2] == 6'b000100)?1'b1:1'b0;
-
-assign ADDRESS_IO_FDC_CT	=	(CPU_A[7:0] == 8'h10)?1'b1:1'b0;
-assign ADDRESS_IO_FDC_DATA	=	(CPU_A[7:0] == 8'h11)?1'b1:1'b0;
-assign ADDRESS_IO_FDC_POLL	=	(CPU_A[7:0] == 8'h12)?1'b1:1'b0;
-assign ADDRESS_IO_FDC_WP	=	(CPU_A[7:0] == 8'h13)?1'b1:1'b0;
-
-
-wire	[7:0]		FDC_DATA;
-wire				FDC_POLL;
-wire				FDC_WP;
-
-wire	[7:0]		SECTOR_BYTE;
-wire	[7:0]		TRACK1_NO;
-wire	[7:0]		TRACK2_NO;
-wire				DRIVE1;
-wire				DRIVE2;
-wire				MOTOR;
-
-wire		FDC_IO_R;
-wire		FDC_IO_W;
-
-wire		FDC_SIG;
-wire		FDC_SIG_CLK;
-
-wire FDC_IO		=	(CPU_IORQ&ADDRESS_IO_FDC);
-wire FDC_IO_POLL	=	(CPU_IORQ&ADDRESS_IO_FDC_POLL);
-wire FDC_IO_DATA	=	(CPU_IORQ&ADDRESS_IO_FDC_DATA);
-wire FDC_IO_CT	=	(CPU_IORQ&ADDRESS_IO_FDC_CT);
-
-FDC_IF FDC_U (
-	.FDC_CLK(CPU_CLK),
-	.RESET_N(RESET_N),
-	.SW(SWITCH[3:2]),
-	.DBG(SWITCH[9:6]),
-
-	.FDC_RAM_R(FDC_RAM_R),
-	.FDC_RAM_W(FDC_RAM_W),
-	.FDC_RAM_ADDR_R(FDC_RAM_ADDR_R),
-	.FDC_RAM_ADDR_W(FDC_RAM_ADDR_W),
-	.FDC_RAM_DATA_R(LATCHED_RAM_DATA_FDC),
-	.FDC_RAM_DATA_W(FDC_RAM_DATA_W),
-
-	.FDC_IO(FDC_IO),
-	.FDC_IO_POLL(FDC_IO_POLL),
-	.FDC_IO_DATA(FDC_IO_DATA),
-	.FDC_IO_CT(FDC_IO_CT),
-
-	.FDC_SIG(FDC_SIG),
-	.FDC_SIG_CLK(FDC_SIG_CLK),
-
-	.FDC_CT(LATCHED_IO_FDC_CT),
-	.FDC_DATA(FDC_DATA),
-	.FDC_POLL(FDC_POLL),
-	.FDC_WP(FDC_WP),
-
-	.FLOPPY_SECTOR_BYTE(SECTOR_BYTE),
-	.TRACK1_NO(TRACK1_NO),
-	.TRACK2_NO(TRACK2_NO),
-	.DRIVE1(DRIVE1),
-	.DRIVE2(DRIVE2),
-	.MOTOR(MOTOR)
-);
-
-
-endmodule
diff --git a/Computer_MiST/Laser310_MiST/rtl/Laser310_MiST.sv b/Computer_MiST/Laser310_MiST/rtl/Laser310_MiST.sv
deleted file mode 100644
index 9b9eeb12..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/Laser310_MiST.sv
+++ /dev/null
@@ -1,133 +0,0 @@
-
-module Laser310_MiST
-(
-	output        LED,						
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,	
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"Laser310;;",
-	"O1,Turbo,Off,On;",
-	"O2,Dos Rom,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"O5,SHRG,Off,On;",
-	"T6,Reset;",
-	"V,v1.00.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_50, clk_25, clk_10, clk_6p25;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_50),
-	.c1(clk_25),
-	.c2(clk_10),
-	.c3(clk_6p25)
-	);
-
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire       		key_pressed;
-wire 		[7:0] key_code;
-wire       		key_strobe;
-reg  [1:0] audio;
-wire  [7:0] audio_s;
-wire 			ce_pix;
-wire 			hs, vs;
-wire  [7:0] r,g,b;
-
-LASER310_TOP LASER310_TOP(
-	.CLK50MHZ(clk_50),
-	.CLK25MHZ(clk_25),
-	.CLK10MHZ(clk_10),
-	.RESET(~(status[0] | status[6] | buttons[1])),
-	.VGA_RED(r),
-	.VGA_GREEN(g),
-	.VGA_BLUE(b),
-	.VGA_HS(hs),
-	.VGA_VS(vs),
-	.AUD_ADCDAT(audio),
-//	.VIDEO_MODE(1'b0),
-	.audio_s(audio_s),
-	.key_strobe     (key_strobe     ),
-	.key_pressed    (key_pressed    ),
-	.key_code       (key_code       ),
-	.SWITCH({"00000",~status[5],~status[2],~status[1]}),
-	.UART_RXD(),
-	.UART_TXD()
-	);
-	
-mist_video #(.COLOR_DEPTH(6)) mist_video(
-	.clk_sys(clk_25),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(r[5:0]),
-	.G(g[5:0]),
-	.B(b[5:0]),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.scandoubler_disable(1'b1),//scandoublerD),
-	.scanlines(status[4:3]),
-	.ypbpr(ypbpr)
-	);
-
-user_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-user_io(
-	.clk_sys        (clk_25         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_CLK        (SPI_SCK        ),
-	.SPI_SS_IO      (CONF_DATA0     ),
-	.SPI_MISO       (SPI_DO         ),
-	.SPI_MOSI       (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches       (switches       ),
-	.scandoubler_disable (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.key_strobe     (key_strobe     ),
-	.key_pressed    (key_pressed    ),
-	.key_code       (key_code       ),
-	.status         (status         )
-	);
-
-dac #(
-	.C_bits(15))
-dac(
-	.clk_i(clk_25),
-	.res_n_i(1),
-//	.dac_i({~audio_s[7],audio_s[6:0],{4{audio}}}),
-	.dac_i({8{audio}}),
-	.dac_o(AUDIO_L)
-	);
-
-endmodule 
\ No newline at end of file
diff --git a/Computer_MiST/Laser310_MiST/rtl/LaserCassEmu.sv b/Computer_MiST/Laser310_MiST/rtl/LaserCassEmu.sv
deleted file mode 100644
index 73c05ec9..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/LaserCassEmu.sv
+++ /dev/null
@@ -1,122 +0,0 @@
-module LaserCassEmu(
-input wire	[15:0]	CPU_A,
-input wire				CPU_RD,
-input wire				CPU_WR
-);
-// cassette
-
-(*keep*)wire	[1:0]	CASS_OUT;
-(*keep*)wire			CASS_IN;
-(*keep*)wire			CASS_IN_L;
-(*keep*)wire			CASS_IN_R;
-
-reg		[7:0]		LATCHED_IO_DATA_WR;
-// 用于外部磁带仿真计数
-//(*keep*)reg				EMU_CASS_CLK;
-
-(*keep*)wire			EMU_CASS_EN;
-(*keep*)wire	[1:0]	EMU_CASS_DAT;
-
-`ifdef CASS_EMU
-
-wire			CASS_BUF_RD;
-wire	[15:0]	CASS_BUF_A;
-wire			CASS_BUF_WR;
-wire	[7:0]	CASS_BUF_DAT;
-wire	[7:0]	CASS_BUF_Q;
-
-// F9    CASS PLAY
-// F10   CASS STOP
-
-EMU_CASS_KEY	EMU_CASS_KEY(
-	KEY_Fxx[8],
-	KEY_Fxx[9],
-	// cass emu
-	CASS_BUF_RD,
-	//
-	CASS_BUF_A,
-	CASS_BUF_WR,
-	CASS_BUF_DAT,
-	CASS_BUF_Q,
-	//	Control Signals
-	EMU_CASS_EN,
-	EMU_CASS_DAT,
-
-	// key emu
-	EMU_KEY,
-	EMU_KEY_EX,
-	EMU_KEY_EN,
-    /*
-     * UART: 115200 bps, 8N1
-     */
-    UART_RXD,
-    UART_TXD,
-
-	// System
-	TURBO_SPEED,
-	// Clock: 10MHz
-	CLK10MHZ,
-	RESET_N
-);
-
-
-`ifdef CASS_EMU_16K
-
-cass_ram_16k_altera cass_buf(
-	.address(CASS_BUF_A[13:0]),
-	.clock(CLK10MHZ),
-	.data(CASS_BUF_DI),
-	.wren(CASS_BUF_WR),
-	.q(CASS_BUF_Q)
-);
-
-`endif
-
-
-`ifdef CASS_EMU_8K
-
-cass_ram_8k_altera cass_buf(
-	.address(CASS_BUF_A[12:0]),
-	.clock(CLK10MHZ),
-	.data(CASS_BUF_DI),
-	.wren(CASS_BUF_WR),
-	.q(CASS_BUF_Q)
-);
-
-`endif
-
-
-`ifdef CASS_EMU_4K
-
-cass_ram_4k_altera cass_buf(
-	.address(CASS_BUF_A[11:0]),
-	.clock(CLK10MHZ),
-	.data(CASS_BUF_DAT),
-	.wren(CASS_BUF_WR),
-	.q(CASS_BUF_Q)
-);
-
-`endif
-
-
-`ifdef CASS_EMU_2K
-
-cass_ram_2k_altera cass_buf(
-	.address(CASS_BUF_A[10:0]),
-	.clock(CLK10MHZ),
-	.data(CASS_BUF_DAT),
-	.wren(CASS_BUF_WR),
-	.q(CASS_BUF_Q)
-);
-
-`endif
-
-`endif
-
-
-
-assign	CASS_OUT = EMU_CASS_EN ? EMU_CASS_DAT : {LATCHED_IO_DATA_WR[2], 1'b0};
-
-(*keep*)wire trap = (CPU_RD|CPU_WR) && (CPU_A[15:12] == 4'h0);
-
-endmodule 
\ No newline at end of file
diff --git a/Computer_MiST/Laser310_MiST/rtl/LaserKeyboard.sv b/Computer_MiST/Laser310_MiST/rtl/LaserKeyboard.sv
deleted file mode 100644
index f7698728..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/LaserKeyboard.sv
+++ /dev/null
@@ -1,414 +0,0 @@
-module LaserKeyboard(
-input wire				CLK50MHZ,
-input wire	[15:0]	CPU_A,
-input wire				RESET,
-input wire				CASS_IN,
-input wire				PS2_KBCLK,
-input wire				PS2_KBDAT
-);
-
-
-// keyboard
-reg		[4:0]		KB_CLK;
-reg		[16:0]		RESET_KEY_COUNT;
-wire	[7:0]		SCAN;
-wire				PRESS;
-wire				PRESS_N;
-wire				EXTENDED;
-reg					BOOTROM_EN;
-reg		[7:0]		BOOTROM_BANK;
-reg					AUTOSTARTROM_EN;
-reg		[7:0]		AUTOSTARTROM_BANK;
-reg		[63:0]		KEY;
-reg		[9:0]		KEY_EX;
-reg		[11:0]		KEY_Fxx;
-wire	[7:0]		KEY_DATA;
-//reg	[63:0]		LAST_KEY;
-//reg				CAPS_CLK;
-//reg				CAPS;
-wire				A_KEY_PRESSED;
-
-reg		[7:0]		LATCHED_KEY_DATA;
-
-// emu keyboard
-wire	[63:0]		EMU_KEY;
-wire	[9:0]		EMU_KEY_EX;
-wire				EMU_KEY_EN;
-// keyboard
-
-/*****************************************************************************
-* Convert PS/2 keyboard to ASCII keyboard
-******************************************************************************/
-
-/*
-   KD5 KD4 KD3 KD2 KD1 KD0 扫描用地址
-A0  R   Q   E       W   T  68FEH       0
-A1  F   A   D  CTRL S   G  68FDH       8
-A2  V   Z   C  SHFT X   B  68FBH      16
-A3  4   1   3       2   5  68F7H      24
-A4  M  空格 ，      .   N  68EFH      32
-A5  7   0   8   -   9   6  68DFH      40
-A6  U   P   I  RETN O   Y  68BFH      48
-A7  J   ；  K   :   L   H  687FH      56
-*/
-
-//  7: 0
-// 15: 8
-// 23:16
-// 31:24
-// 39:32
-// 47:40
-// 55:48
-// 63:56
-
-
-
-// 键盘检测的方法，就是循环地问每一行线发送低电平信号，也就是用该地址线为“0”的地址去读取数据。
-// 例如，检测第一行时，使A0为0，其余为1；加上选通IC4的高五位地址01101，成为01101***11111110B（A8~A10不起作用，
-// 可为任意值，故68FEH，69FEH，6AFEH，6BFEH，6CFEH，6DFEH，6EFEH，6FFEH均可）。
-// 读 6800H 判断是否有按键按下。
-
-// The method of keyboard detection is to cyclically ask each line to send a low level signal, 
-// that is, to read the data with the address line "0".
-// For example, when detecting the first line, make A0 0 and the rest 1; plus the high five-bit address 01101 of the strobe IC4, 
-// become 01101***11111110B (A8~A10 does not work,
-// It can be any value, so 68FEH, 69FEH, 6AFEH, 6BFEH, 6CFEH, 6DFEH, 6EFEH, 6FFEH can be).
-// Read 6800H to determine if there is a button press.
-
-// 键盘选通，整个竖列有一个选通的位置被按下，对应值为0。
-// The keyboard is strobed, and a strobe position is pressed in the entire vertical column, and the corresponding value is 0.
-
-// 键盘扩展
-// 加入方向键盘
-// Keyboard extension
-
-// left:  ctrl M      37 KEY_EX[5]
-// right: ctrl ,      35 KEY_EX[6]
-// up:    ctrl .      33 KEY_EX[4]
-// down:  ctrl space  36 KEY_EX[7]
-// esc:   ctrl -      42 KEY_EX[3]
-// backspace:  ctrl M      37 KEY_EX[8]
-
-// R-Shift
-
-
-wire	[63:0]	KEY_C		=	EMU_KEY_EN?EMU_KEY:KEY;
-wire	[9:0]	KEY_EX_C	=	EMU_KEY_EN?EMU_KEY_EX:KEY_EX;
-
-//wire KEY_CTRL_ULRD = (KEY_EX[7:4]==4'b1111);
-wire KEY_CTRL_ULRD_BRK = (KEY_EX[8:3]==6'b111111);
-
-wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY_C[61], KEY_C[53], KEY_C[45],           KEY_C[37]&KEY_EX_C[5]&KEY_EX_C[8], KEY_C[29], KEY_C[21],           KEY_C[13],                   KEY_C[ 5]})==8'hff;
-wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY_C[60], KEY_C[52], KEY_C[44],           KEY_C[36]&KEY_EX_C[7], KEY_C[28], KEY_C[20],           KEY_C[12],                   KEY_C[ 4]})==8'hff;
-wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY_C[59], KEY_C[51], KEY_C[43],           KEY_C[35]&KEY_EX_C[6], KEY_C[27], KEY_C[19],           KEY_C[11],                   KEY_C[ 3]})==8'hff;
-wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY_C[58], KEY_C[50], KEY_C[42]&KEY_EX_C[3], KEY_C[34],           KEY_C[26], KEY_C[18]&KEY_EX_C[0], KEY_C[10]&KEY_CTRL_ULRD_BRK, KEY_C[ 2]})==8'hff;
-wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY_C[57], KEY_C[49], KEY_C[41],           KEY_C[33]&KEY_EX_C[4], KEY_C[25], KEY_C[17],           KEY_C[ 9],                   KEY_C[ 1]})==8'hff;
-wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY_C[56], KEY_C[48], KEY_C[40],           KEY_C[32],             KEY_C[24], KEY_C[16],           KEY_C[ 8],                   KEY_C[ 0]})==8'hff;
-
-/*
-wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY[61], KEY[53], KEY[45], KEY[37], KEY[29], KEY[21], KEY[13], KEY[ 5]})==8'hff;
-wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY[60], KEY[52], KEY[44], KEY[36], KEY[28], KEY[20], KEY[12], KEY[ 4]})==8'hff;
-wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY[59], KEY[51], KEY[43], KEY[35], KEY[27], KEY[19], KEY[11], KEY[ 3]})==8'hff;
-wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY[58], KEY[50], KEY[42], KEY[34], KEY[26], KEY[18], KEY[10], KEY[ 2]})==8'hff;
-wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY[57], KEY[49], KEY[41], KEY[33], KEY[25], KEY[17], KEY[ 9], KEY[ 1]})==8'hff;
-wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY[56], KEY[48], KEY[40], KEY[32], KEY[24], KEY[16], KEY[ 8], KEY[ 0]})==8'hff;
-*/
-
-wire KEY_DATA_BIT7 = 1'b1;	// 没有空置，具体用途没有理解
-//wire KEY_DATA_BIT6 = CASS_IN;
-wire KEY_DATA_BIT6 = ~CASS_IN;
-
-assign KEY_DATA = { KEY_DATA_BIT7, KEY_DATA_BIT6, KEY_DATA_BIT5, KEY_DATA_BIT4, KEY_DATA_BIT3, KEY_DATA_BIT2, KEY_DATA_BIT1, KEY_DATA_BIT0 };
-
-/*
-assign KEY_DATA = 	(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
-					(CPU_A[1]==1'b0) ? KEY[15: 8] :
-					(CPU_A[2]==1'b0) ? KEY[23:16] :
-					(CPU_A[3]==1'b0) ? KEY[31:24] :
-					(CPU_A[4]==1'b0) ? KEY[39:32] :
-					(CPU_A[5]==1'b0) ? KEY[47:40] :
-					(CPU_A[6]==1'b0) ? KEY[55:48] :
-					(CPU_A[7]==1'b0) ? KEY[63:56] :
-					8'hff;
-
-assign KEY_DATA =
-					(CPU_A[7]==1'b0) ? KEY[63:56] :
-					(CPU_A[6]==1'b0) ? KEY[55:48] :
-					(CPU_A[5]==1'b0) ? KEY[47:40] :
-					(CPU_A[4]==1'b0) ? KEY[39:32] :
-					(CPU_A[3]==1'b0) ? KEY[31:24] :
-					(CPU_A[2]==1'b0) ? KEY[23:16] :
-					(CPU_A[1]==1'b0) ? KEY[15: 8] :
-					(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
-					8'hff;
-*/
-
-
-assign A_KEY_PRESSED = (KEY[63:0] == 64'hFFFFFFFFFFFFFFFF) ? 1'b0:1'b1;
-
-always @(posedge KB_CLK[3] or negedge RESET)
-begin
-	if(~RESET)
-	begin
-		KEY					<=	64'hFFFFFFFFFFFFFFFF;
-		KEY_EX				<=	10'h3FF;
-		KEY_Fxx				<=	12'h000;
-//		CAPS_CLK			<=	1'b0;
-		RESET_KEY_COUNT		<=	17'h1FFFF;
-
-		BOOTROM_BANK		<=	0;
-		BOOTROM_EN			<=	1'b0;
-
-		AUTOSTARTROM_BANK	<=	0;
-		AUTOSTARTROM_EN		<=	1'b0;
-	end
-	else
-	begin
-		//KEY[?] <= CAPS;
-		if(RESET_KEY_COUNT[16]==1'b0)
-			RESET_KEY_COUNT <= RESET_KEY_COUNT+1;
-
-		case(SCAN)
-		/*8'h07:
-		begin
-				KEY_Fxx[11]	<= PRESS;	// F12 RESET
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b0;
-					BOOTROM_BANK		<=	0;
-					AUTOSTARTROM_EN		<=	1'b0;
-					AUTOSTARTROM_BANK	<=	0;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h78:	KEY_Fxx[10] <= PRESS;	// F11
-		8'h09:	KEY_Fxx[ 9] <= PRESS;	// F10 CASS STOP
-		8'h01:	KEY_Fxx[ 8] <= PRESS;	// F9  CASS PLAY
-		8'h0A:
-		begin
-				KEY_Fxx[ 7] <= PRESS;	// F8  Ctrl or L-Shift BOOT 8
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	39;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	23;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h83:
-		begin
-				KEY_Fxx[ 6] <= PRESS;	// F7  Ctrl or L-Shift BOOT 7
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	38;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	22;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h0B:
-		begin
-				KEY_Fxx[ 5] <= PRESS;	// F6  Ctrl or L-Shift BOOT 6
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	37;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	21;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h03:
-		begin
-				KEY_Fxx[ 4] <= PRESS;	// F5  Ctrl or L-Shift BOOT 5
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	36;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	20;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h0C:
-		begin
-				KEY_Fxx[ 3] <= PRESS;	// F4  Ctrl or L-Shift BOOT 4
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	35;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	19;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h04:
-		begin
-				KEY_Fxx[ 2] <= PRESS;	// F3  Ctrl or L-Shift BOOT 3
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	34;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	18;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h06:
-		begin
-				KEY_Fxx[ 1] <= PRESS;	// F2  Ctrl or L-Shift BOOT 2
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	33;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	17;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h05:
-		begin
-				KEY_Fxx[ 0] <= PRESS;	// F1  Ctrl or L-Shift BOOT 1
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	32;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	16;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end*/
-
-		8'h16:	KEY[28] <= PRESS_N;	// 1 !
-		8'h1E:	KEY[25] <= PRESS_N;	// 2 @
-		8'h26:	KEY[27] <= PRESS_N;	// 3 #
-		8'h25:	KEY[29] <= PRESS_N;	// 4 $
-		8'h2E:	KEY[24] <= PRESS_N;	// 5 %
-		8'h36:	KEY[40] <= PRESS_N;	// 6 ^
-		8'h3D:	KEY[45] <= PRESS_N;	// 7 &
-//		8'h0D:	KEY[?] <= PRESS_N;	// TAB
-		8'h3E:	KEY[43] <= PRESS_N;	// 8 *
-		8'h46:	KEY[41] <= PRESS_N;	// 9 (
-		8'h45:	KEY[44] <= PRESS_N;	// 0 )
-		8'h4E:	KEY[42] <= PRESS_N;	// - _
-//		8'h55:	KEY[?] <= PRESS_N;	// = +
-		8'h66:	KEY_EX[8] <= PRESS_N;	// backspace
-//		8'h0E:	KEY[?] <= PRESS_N;	// ` ~
-//		8'h5D:	KEY[?] <= PRESS_N;	// \ |
-		8'h49:	KEY[33] <= PRESS_N;	// . >
-		8'h4b:	KEY[57] <= PRESS_N;	// L
-		8'h44:	KEY[49] <= PRESS_N;	// O
-//		8'h11	KEY[?] <= PRESS_N; // line feed (really right ALT (Extended) see below
-		8'h5A:	KEY[50] <= PRESS_N;	// CR
-//		8'h54:	KEY[?] <= PRESS_N;	// [ {
-//		8'h5B:	KEY[?] <= PRESS_N;	// ] }
-		8'h52:	KEY[58] <= PRESS_N;	// ' "
-		8'h1D:	KEY[ 1] <= PRESS_N;	// W
-		8'h24:	KEY[ 3] <= PRESS_N;	// E
-		8'h2D:	KEY[ 5] <= PRESS_N;	// R
-		8'h2C:	KEY[ 0] <= PRESS_N;	// T
-		8'h35:	KEY[48] <= PRESS_N;	// Y
-		8'h3C:	KEY[53] <= PRESS_N;	// U
-		8'h43:	KEY[51] <= PRESS_N;	// I
-		8'h1B:	KEY[ 9] <= PRESS_N;	// S
-		8'h23:	KEY[11] <= PRESS_N;	// D
-		8'h2B:	KEY[13] <= PRESS_N;	// F
-		8'h34:	KEY[ 8] <= PRESS_N;	// G
-		8'h33:	KEY[56] <= PRESS_N;	// H
-		8'h3B:	KEY[61] <= PRESS_N;	// J
-		8'h42:	KEY[59] <= PRESS_N;	// K
-		8'h22:	KEY[17] <= PRESS_N;	// X
-		8'h21:	KEY[19] <= PRESS_N;	// C
-		8'h2a:	KEY[21] <= PRESS_N;	// V
-		8'h32:	KEY[16] <= PRESS_N;	// B
-		8'h31:	KEY[32] <= PRESS_N;	// N
-		8'h3a:	KEY[37] <= PRESS_N;	// M
-		8'h41:	KEY[35] <= PRESS_N;	// , <
-		8'h15:	KEY[ 4] <= PRESS_N;	// Q
-		8'h1C:	KEY[12] <= PRESS_N;	// A
-		8'h1A:	KEY[20] <= PRESS_N;	// Z
-		8'h29:	KEY[36] <= PRESS_N;	// Space
-//		8'h4A:	KEY[?] <= PRESS_N;	// / ?
-		8'h4C:	KEY[60] <= PRESS_N;	// ; :
-		8'h4D:	KEY[52] <= PRESS_N;	// P
-		8'h14:	KEY[10] <= PRESS_N;	// Ctrl either left or right
-		8'h12:	KEY[18] <= PRESS_N;	// L-Shift
-		8'h59:	KEY_EX[0] <= PRESS_N;	// R-Shift
-		8'h11:
-		begin
-			if(~EXTENDED)
-					KEY_EX[1] <= PRESS_N;	// Repeat really left ALT
-			else
-					KEY_EX[2] <= PRESS_N;	// LF really right ALT
-		end
-		8'h76:	KEY_EX[3] <= PRESS_N;	// Esc
-		8'h75:	KEY_EX[4] <= PRESS_N;	// up
-		8'h6B:	KEY_EX[5] <= PRESS_N;	// left
-		8'h74:	KEY_EX[6] <= PRESS_N;	// right
-		8'h72:	KEY_EX[7] <= PRESS_N;	// down
-		endcase
-	end
-end
-
-
-
-
-always @ (posedge CLK50MHZ)				// 50MHz
-	KB_CLK <= KB_CLK + 1'b1;			// 50/32 = 1.5625 MHz
-
-ps2_keyboard KEYBOARD(
-		.RESET_N(~RESET),
-		.CLK(KB_CLK[4]),
-		.PS2_CLK(PS2_KBCLK),
-		.PS2_DATA(PS2_KBDAT),
-		.RX_SCAN(SCAN),
-		.RX_PRESSED(PRESS),
-		.RX_EXTENDED(EXTENDED)
-);
-
-assign PRESS_N = ~PRESS;
-
-
-endmodule 
\ No newline at end of file
diff --git a/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80ALU.v b/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80ALU.v
deleted file mode 100644
index 610781a2..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80ALU.v
+++ /dev/null
@@ -1,372 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////////
-//
-// This file is part of the NextZ80 project
-// http://www.opencores.org/cores/nextz80/
-//
-// Filename: NextZ80ALU.v
-// Description: Implementation of Z80 compatible CPU - ALU
-// Version 1.0
-// Creation date: 28Jan2011 - 18Mar2011
-//
-// Author: Nicolae Dumitrache 
-// e-mail: ndumitrache@opencores.org
-//
-/////////////////////////////////////////////////////////////////////////////////
-// 
-// Copyright (C) 2011 Nicolae Dumitrache
-// 
-// This source file may be used and distributed without 
-// restriction provided that this copyright statement is not 
-// removed from the file and that any derivative work contains 
-// the original copyright notice and the associated disclaimer.
-// 
-// This source file is free software; you can redistribute it 
-// and/or modify it under the terms of the GNU Lesser General 
-// Public License as published by the Free Software Foundation;
-// either version 2.1 of the License, or (at your option) any 
-// later version. 
-// 
-// This source is distributed in the hope that it will be 
-// useful, but WITHOUT ANY WARRANTY; without even the implied 
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
-// PURPOSE. See the GNU Lesser General Public License for more 
-// details. 
-// 
-// You should have received a copy of the GNU Lesser General 
-// Public License along with this source; if not, download it 
-// from http://www.opencores.org/lgpl.shtml 
-// 
-///////////////////////////////////////////////////////////////////////////////////
-
-//FLAGS: S Z X1 N X2 PV N C
-//	OP[4:0]
-//	00000	-	ADD	D0,D1
-//	00001	-	ADC	D0,D1
-//	00010	-	SUB	D0,D1
-//	00011	-	SBC	D0,D1
-//	00100	-	AND	D0,D1
-//	00101	-	XOR	D0,D1
-//	00110	-	OR		D0,D1
-//	00111	-	CP		D0,D1
-//	01000	-	INC	D0
-//	01001	-	CPL	D0
-// 01010	-	DEC	D0
-//	01011	-	RRD
-// 01100	-	RLD
-//	01101	-	DAA
-//	01110	-	INC16
-//	01111	-  DEC16
-// 10000	-	ADD16LO
-//	10001	-	ADD16HI
-//	10010	-	
-//	10011	-	
-//	10100	-	CCF, pass D0
-// 10101	-	SCF, pass D0
-// 10110	-	
-//	10111	-	
-//	11000	-	RLCA	D0
-//	11001	-	RRCA	D0
-//	11010	-	RLA	D0
-//	11011	- 	RRA	D0
-//	11100	-	{ROT, BIT, SET, RES} D0,EXOP 
-//				  RLC		D0			C <-- D0 <-- D0[7]
-//            RRC		D0			D0[0] --> D0 --> C
-//            RL		D0			C <-- D0 <-- C
-//            RR		D0			C --> D0 --> C
-//            SLA		D0			C <-- D0 <-- 0
-//            SRA		D0			D0[7] --> D0 --> C
-//            SLL		D0			C <-- D0 <-- 1
-//            SRL		D0			0 --> D0 --> C
-//	11101	-	IN, pass D1
-//	11110	-	FLAGS <- D0
-//	11111	-	NEG	D1	
-///////////////////////////////////////////////////////////////////////////////////
-`timescale 1ns / 1ps
-
-module ALU8(
-    input [7:0] D0,
-    input [7:0] D1,
-	 input [7:0] FIN,
-    output reg[7:0] FOUT,
-    output reg [15:0] ALU8DOUT,
-    input [4:0] OP,
-	 input [5:0] EXOP, // EXOP[5:4] = 2'b11 for CPI/D/R
-	 input LDIFLAGS,	 // zero HF and NF on inc/dec16
-	 input DSTHI		 // destination lo
-    );
-	
-	wire [7:0] daaadjust;
-	wire cdaa, hdaa;
-	daa daa_adjust(.flags(FIN), .val(D0), .adjust(daaadjust), .cdaa(cdaa), .hdaa(hdaa));
-	
-	wire parity = ~^ALU8DOUT[15:8];
-	wire zero = ALU8DOUT[15:8] == 0;
-	reg csin, cin;
-	wire [7:0]d0mux = OP[4:1] == 4'b1111 ? 0 : D0;
-	reg [7:0]_d1mux;
-	wire [7:0]d1mux = OP[1] ? ~_d1mux : _d1mux;
-	wire [8:0]sum;
-	wire hf;
-	assign {hf, sum[3:0]} = d0mux[3:0] + d1mux[3:0] + cin;
-	assign sum[8:4] = d0mux[7:4] + d1mux[7:4] + hf;
-	wire overflow = (d0mux[7] & d1mux[7] & !sum[7]) | (!d0mux[7] & !d1mux[7] & sum[7]);
-	reg [7:0]dbit;
-
-	always @* begin
-		ALU8DOUT = 16'hxxxx;
-		FOUT = 8'hxx;
-		case({OP[4:2]})
-			0,1,4,7: _d1mux = D1;
-			2: _d1mux = 1;
-			3: _d1mux = daaadjust;		// DAA
-			6,5: _d1mux = 8'hxx;
-		endcase
-		case({OP[2:0], FIN[0]})
-			0,1,2,7,8,9,10,11,12,13:	cin = 0;
-			3,4,5,6,14,15: cin = 1;
-		endcase
-		case(EXOP[3:0])
-			0: dbit =  8'b11111110;
-			1: dbit =  8'b11111101;
-			2: dbit =  8'b11111011;
-			3: dbit =  8'b11110111;
-			4: dbit =  8'b11101111;
-			5: dbit =  8'b11011111;
-			6: dbit =  8'b10111111;
-			7: dbit =  8'b01111111;
-			8: dbit =  8'b00000001;
-			9: dbit =  8'b00000010;
-			10: dbit = 8'b00000100;
-			11: dbit = 8'b00001000;
-			12: dbit = 8'b00010000;
-			13: dbit = 8'b00100000;
-			14: dbit = 8'b01000000;
-			15: dbit = 8'b10000000;
-		endcase
-		case(OP[3] ? EXOP[2:0] : OP[2:0])
-			0,5:	csin = D0[7];
-			1: 	csin = D0[0];
-			2,3:	csin = FIN[0];
-			4,7:	csin = 0;
-			6:		csin = 1;
-		endcase
-		case(OP[4:0])
-			0,1,2,3,8,10:	begin		// ADD, ADC, SUB, SBC, INC, DEC
-				ALU8DOUT[15:8] = sum[7:0];
-				ALU8DOUT[7:0] = sum[7:0];
-				FOUT[0] = OP[3] ? FIN[0] : (sum[8] ^ OP[1]); // inc/dec
-				FOUT[1] = OP[1];
-				FOUT[2] = overflow;
-				FOUT[3] = ALU8DOUT[11];
-				FOUT[4] = hf ^ OP[1];
-				FOUT[5] = ALU8DOUT[13];
-				FOUT[6] = zero & (FIN[6] | ~EXOP[5] | ~DSTHI | OP[3]); //(EXOP[5] & DSTHI) ? (zero & FIN[6]) : zero;				// adc16/sbc16
-				FOUT[7] = ALU8DOUT[15];
-			end
-			16,17:	begin		// ADD16LO, ADD16HI
-				ALU8DOUT[15:8] = sum[7:0];
-				ALU8DOUT[7:0] = sum[7:0];
-				FOUT[0] = sum[8];
-				FOUT[1] = OP[1];
-				FOUT[2] = FIN[2];
-				FOUT[3] = ALU8DOUT[11];
-				FOUT[4] = hf ^ OP[1];
-				FOUT[5] = ALU8DOUT[13];
-				FOUT[6] = FIN[6];
-				FOUT[7] = FIN[7];
-			end
-			7: begin		// CP
-				ALU8DOUT[15:8] = sum[7:0];
-				FOUT[0] = EXOP[5] ? FIN[0] : !sum[8]; // CPI/D/R
-				FOUT[1] = OP[1];
-				FOUT[2] = overflow;
-				FOUT[3] = D1[3];
-				FOUT[4] = !hf;
-				FOUT[5] = D1[5];
-				FOUT[6] = zero;
-				FOUT[7] = ALU8DOUT[15];
-			end
-			31:	begin		// NEG
-				ALU8DOUT[15:8] = sum[7:0];
-				FOUT[0] = !sum[8];
-				FOUT[1] = OP[1];
-				FOUT[2] = overflow;
-				FOUT[3] = ALU8DOUT[11];
-				FOUT[4] = !hf;
-				FOUT[5] = ALU8DOUT[13];
-				FOUT[6] = zero;
-				FOUT[7] = ALU8DOUT[15];
-			end
-			4: begin			// AND
-				ALU8DOUT[15:8] = D0 & D1;
-				FOUT[0] = 0;
-				FOUT[1] = 0;
-				FOUT[2] = parity;
-				FOUT[3] = ALU8DOUT[11];
-				FOUT[4] = 1;
-				FOUT[5] = ALU8DOUT[13];
-				FOUT[6] = zero;
-				FOUT[7] = ALU8DOUT[15];
-			end
-			5,6: begin		//XOR, OR
-				ALU8DOUT[15:8] = OP[0] ? (D0 ^ D1) : (D0 | D1);
-				FOUT[0] = 0;
-				FOUT[1] = 0;
-				FOUT[2] = parity;
-				FOUT[3] = ALU8DOUT[11];
-				FOUT[4] = 0;
-				FOUT[5] = ALU8DOUT[13];
-				FOUT[6] = zero;
-				FOUT[7] = ALU8DOUT[15];
-			end
-			9: begin			// CPL
-				ALU8DOUT[15:8] = ~D0;
-				FOUT[0] = FIN[0];
-				FOUT[1] = 1;
-				FOUT[2] = FIN[2];
-				FOUT[3] = ALU8DOUT[11];
-				FOUT[4] = 1;
-				FOUT[5] = ALU8DOUT[13];
-				FOUT[7:6] = FIN[7:6];
-			end
-			11,12: begin					// RLD, RRD
-				if(OP[0]) ALU8DOUT = {D0[7:4], D1[3:0], D0[3:0], D1[7:4]};
-				else ALU8DOUT = {D0[7:4], D1[7:0], D0[3:0]};
-				FOUT[0] = FIN[0];
-				FOUT[1] = 0;
-				FOUT[2] = parity;
-				FOUT[3] = ALU8DOUT[11];
-				FOUT[4] = 0;
-				FOUT[5] = ALU8DOUT[13];
-				FOUT[6] = zero;
-				FOUT[7] = ALU8DOUT[15];
-			end			
-			13: begin	// DAA
-				ALU8DOUT[15:8] = sum[7:0];
-				FOUT[0] = cdaa;
-				FOUT[1] = FIN[1];
-				FOUT[2] = parity;
-				FOUT[3] = ALU8DOUT[11];
-				FOUT[4] = hdaa;
-				FOUT[5] = ALU8DOUT[13];
-				FOUT[6] = zero;
-				FOUT[7] = ALU8DOUT[15];
-			end
-			14,15: begin	// inc/dec 16
-				ALU8DOUT = {D0, D1} + (OP[0] ? 16'hffff : 16'h0001);
-				FOUT[0] = FIN[0];
-				FOUT[1] = LDIFLAGS ? 1'b0 : FIN[1];
-				FOUT[2] = ALU8DOUT != 0;
-				FOUT[3] = FIN[3];
-				FOUT[4] = LDIFLAGS ? 1'b0 : FIN[4];
-				FOUT[5] = FIN[5];
-				FOUT[6] = FIN[6];
-				FOUT[7] = FIN[7];
-			end
-			20,21: begin		// CCF, SCF
-				ALU8DOUT[15:8] = D0;
-				FOUT[0] = OP[0] ? 1'b1 : !FIN[0];
-				FOUT[1] = 1'b0;
-				FOUT[2] = FIN[2];
-				FOUT[3] = ALU8DOUT[11];
-				FOUT[4] = OP[0] ? 1'b0 : FIN[0];
-				FOUT[5] = ALU8DOUT[13];
-				FOUT[6] = FIN[6];
-				FOUT[7] = FIN[7];				
-			end
-			24,25,26,27, 28: begin 							// ROT, BIT, RES, SET
-				case({OP[2], EXOP[4:3]})
-					0,1,2,3,4:	// rot - shift
-						if(OP[2] ? EXOP[0] : OP[0]){ALU8DOUT[15:8], FOUT[0]} = {csin, D0};		// right
-						else							 	{FOUT[0], ALU8DOUT[15:8]} = {D0, csin};		// left
-					5,6: begin	// BIT, RES 
-						FOUT[0] = FIN[0]; 
-						ALU8DOUT[15:8] = D0 & dbit; 
-					end		
-					7: begin 	// SET
-						FOUT[0] = FIN[0]; 
-						ALU8DOUT[15:8] = D0 | dbit; 
-					end			
-				endcase
-				ALU8DOUT[7:0] = ALU8DOUT[15:8];
-				FOUT[1] = 0;
-				FOUT[2] = OP[2] ? (EXOP[3] ? zero : parity) : FIN[2];
-				FOUT[3] = ALU8DOUT[11];
-				FOUT[4] = OP[2] & EXOP[3];
-				FOUT[5] = ALU8DOUT[13];
-				FOUT[6] = OP[2] ? zero : FIN[6];
-				FOUT[7] = OP[2] ? ALU8DOUT[15] : FIN[7];
-			end
-			29:	begin		// IN, pass D1
-				ALU8DOUT = {D1, D1};
-				FOUT[0] = FIN[0];
-				FOUT[1] = 0;
-				FOUT[2] = parity;
-				FOUT[3] = ALU8DOUT[11];
-				FOUT[4] = 0;
-				FOUT[5] = ALU8DOUT[13];
-				FOUT[6] = zero;
-				FOUT[7] = ALU8DOUT[15];
-			end
-			30: FOUT = D0;		// FLAGS <- D0
-			default:;
-		endcase
-	end
-endmodule
-
-module daa (
-	input [7:0]flags,
-	input [7:0]val,
-	output wire [7:0]adjust,
-	output reg cdaa,
-	output reg hdaa
-	);
-	
-	wire h08 = val[7:4] < 9;
-	wire h09 = val[7:4] < 10;
-	wire l05 = val[3:0] < 6;
-	wire l09 = val[3:0] < 10;
-	reg [1:0]aa;
-	assign adjust = ({1'b0, aa[1], aa[1], 2'b0, aa[0], aa[0], 1'b0} ^ {8{flags[1]}}) + flags[1];
-	
-	always @* begin
-		case({flags[0], h08, h09, flags[4], l09})
-			5'b00101, 5'b01101:	aa = 0;
-			5'b00111, 5'b01111, 5'b01000, 5'b01010, 5'b01100, 5'b01110:	aa = 1;
-			5'b00001, 5'b01001, 5'b10001, 5'b10101, 5'b11001, 5'b11101:	aa = 2;
-			default: aa = 3;
-		endcase
-		case({flags[0], h08, h09, l09})
-			4'b0011, 4'b0111, 4'b0100, 4'b0110:	cdaa = 0;
-			default: cdaa = 1;
-		endcase
-		case({flags[1], flags[4], l05, l09})
-			4'b0000, 4'b0010, 4'b0100, 4'b0110, 4'b1110, 4'b1111:	hdaa = 1;
-			default:	hdaa = 0;
-		endcase
-	end
-endmodule
-
-
-module ALU16(
-    input [15:0] D0,
-    input [7:0] D1,
-    output wire[15:0] DOUT,
-    input [2:0]OP	// 0-NOP, 1-INC, 2-INC2, 3-ADD, 4-NOP, 5-DEC, 6-DEC2
-    );
-	
-	reg [15:0] mux;
-	always @*
-		case(OP)
-			0: mux = 0;				// post inc
-			1: mux = 1;				// post inc
-			2: mux = 2;				// post inc
-			3: mux = {D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7:0]};	// post inc
-			4: mux = 0;				// no post inc			
-			5: mux = 16'hffff;	// no post inc
-			6: mux = 16'hfffe;	// no post inc
-			default: mux = 16'hxxxx;
-		endcase
-	
-	assign DOUT = D0 + mux;
-endmodule
diff --git a/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80CPU.v b/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80CPU.v
deleted file mode 100644
index 25d26af8..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80CPU.v
+++ /dev/null
@@ -1,1499 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////////
-//
-// This file is part of the NextZ80 project
-// http://www.opencores.org/cores/nextz80/
-//
-// Filename: NextZ80CPU.v
-// Description: Implementation of Z80 compatible CPU
-// Version 1.0
-// Creation date: 28Jan2011 - 18Mar2011
-//
-// Author: Nicolae Dumitrache 
-// e-mail: ndumitrache@opencores.org
-//
-/////////////////////////////////////////////////////////////////////////////////
-// 
-// Copyright (C) 2011 Nicolae Dumitrache
-// 
-// This source file may be used and distributed without 
-// restriction provided that this copyright statement is not 
-// removed from the file and that any derivative work contains 
-// the original copyright notice and the associated disclaimer.
-// 
-// This source file is free software; you can redistribute it 
-// and/or modify it under the terms of the GNU Lesser General 
-// Public License as published by the Free Software Foundation;
-// either version 2.1 of the License, or (at your option) any 
-// later version. 
-// 
-// This source is distributed in the hope that it will be 
-// useful, but WITHOUT ANY WARRANTY; without even the implied 
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
-// PURPOSE. See the GNU Lesser General Public License for more 
-// details. 
-// 
-// You should have received a copy of the GNU Lesser General 
-// Public License along with this source; if not, download it 
-// from http://www.opencores.org/lgpl.shtml 
-// 
-///////////////////////////////////////////////////////////////////////////////////
-//
-// Comments:
-// This project was developed and tested on a XILINX Spartan3AN board.
-//
-//	NextZ80 processor features:
-//		All documented/undocumented intstructions are implemented
-//		All documented/undocumented flags are implemented
-//		All (doc/undoc)flags are changed accordingly by all (doc/undoc)instructions. 
-//			The block instructions (LDx, CPx, INx, OUTx) have only the documented effects on flags. 
-//			The Bit n,(IX/IY+d) and BIT n,(HL) undocumented flags XF and YF are implemented like the BIT n,r and not actually like on the real Z80 CPU.
-//		All interrupt modes implemented: NMI, IM0, IM1, IM2
-//		R register available
-//		Fast conditional jump/call/ret takes only 1 T state if not executed
-//		Fast block instructions: LDxR - 3 T states/byte, INxR/OTxR - 2 T states/byte, CPxR - 4 T states / byte
-//		Each CPU machine cycle takes (mainly) one clock T state. This makes this processor over 4 times faster than a Z80 at the same 
-//			clock frequency (some instructions are up to 10 times faster). 
-//		Works at ~40MHZ on Spartan XC3S700AN speed grade -4)
-//		Small size ( ~12%  ~700 slices - on Spartan XC3S700AN )
-//		Tested with ZEXDOC (fully compliant).
-//		Tested with ZEXALL (all OK except CPx(R), LDx(R), BIT n, (IX/IY+d), BIT n, (HL) - fail because of the un-documented XF and YF flags).
-// 
-///////////////////////////////////////////////////////////////////////////////////
-`timescale 1ns / 1ps
-
-module NextZ80
-(
-		input wire[7:0] DI,
-		output wire[7:0] DO,
-		output wire[15:0] ADDR,
-		output reg WR,
-		output reg MREQ,
-		output reg IORQ,
-		output reg HALT,
-		output reg M1,
-		input wire CLK,
-		input wire RESET,
-		input wire INT,
-		input wire NMI,
-		input	wire WAIT
-);
-
-// connections and registers
-	reg	[9:0] CPUStatus = 0;	// 0=AF-AF', 1=HL-HL', 2=DE-HL, 3=DE'-HL', 4=HL-X, 5=IX-IY, 6=IFF1,7=IFF2, 9:8=IMODE
-	wire	[7:0] ALU8FLAGS;
-	wire	[7:0]	FLAGS;
-	wire 	[7:0] ALU80;
-	wire 	[7:0] ALU81;
-	wire 	[15:0]ALU160;
-	wire 	[7:0] ALU161;
-	wire	[15:0]ALU8OUT;
-
-	reg 	[9:0]	FETCH = 0;
-	reg 	[2:0]	STAGE = 0;
-	wire	[5:0]	opd;
-	wire	[2:0] op16;
-	wire	op0mem = FETCH[2:0] == 6;
-	wire	op1mem = FETCH[5:3] == 6;
-	reg	[1:0]fetch98;
-
-// stage status
-	reg	[1:0]DO_SEL;			// ALU80 - th - flags - ALU8OUT[7:0]
-	reg	ALU160_SEL;				// regs - pc
-	reg	DINW_SEL;				// ALU8OUT - DI
-	reg 	[5:0]WE;					// 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo
-	reg 	[4:0] ALU8OP;
-	reg 	[2:0] ALU16OP;
-	reg 	next_stage;
-	reg 	[3:0]REG_WSEL;
-	reg 	[3:0]REG_RSEL;
-	reg	[11:0]status;			// 0=AF-AF', 1=HL-HL', 2=DE-HL, 3=DE'-HL', 4=HL-X, 5=IX-IY, 7:6=IFFVAL, 9:8=imode, 10=setIMODE, 11=set IFFVAL
-// FETCH[5:3]: 000 NZ, 001 Z, 010 NC, 011 C, 100 PO, 101 PE, 110 P, 111 M
-	wire	[7:0]FlagMux = {FLAGS[7], !FLAGS[7], FLAGS[2], !FLAGS[2], FLAGS[0], !FLAGS[0], FLAGS[6], !FLAGS[6]};
-	reg	tzf;
-	reg 	FNMI = 0, SNMI = 0;
-	reg 	SRESET = 0;
-	reg	SINT = 0;
-	wire	[2:0]intop = FETCH[1] ? 4 : (FETCH[0] ? 5 : 6);
-	reg 	xmask;
-
-	Z80Reg CPU_REGS (
-		 .rstatus(CPUStatus[7:0]), 
-		 .M1(M1), 
-		 .WE(WE), 
-		 .CLK(CLK), 
-		 .ALU8OUT(ALU8OUT), 
-		 .DI(DI), 
-		 .DO(DO), 
-		 .ADDR(ADDR), 									
-		 .CONST(FETCH[7] ? {2'b00, FETCH[5:3], 3'b000} : 8'h66),	// RST/NMI address
-		 .ALU80(ALU80), 
-		 .ALU81(ALU81), 
-		 .ALU160(ALU160), 
-		 .ALU161(ALU161), 
-		 .ALU8FLAGS(ALU8FLAGS), 
-		 .FLAGS(FLAGS),
-		 .DO_SEL(DO_SEL), 
-		 .ALU160_sel(ALU160_SEL), 
-		 .REG_WSEL(REG_WSEL), 
-		 .REG_RSEL(REG_RSEL), 
-		 .DINW_SEL(DINW_SEL),
-		 .XMASK(xmask),
-		 .ALU16OP(ALU16OP),			// used for post increment for ADDR, SP mux re-direct
-		 .WAIT(WAIT)
-		 );
-
-	ALU8 CPU_ALU8 (
-		 .D0(ALU80), 
-		 .D1(ALU81), 
-		 .FIN(FLAGS), 
-		 .FOUT(ALU8FLAGS), 
-		 .ALU8DOUT(ALU8OUT), 
-		 .OP(ALU8OP),
-		 .EXOP(FETCH[8:3]),
-		 .LDIFLAGS(REG_WSEL[2]),	// inc16 HL
-		 .DSTHI(!REG_WSEL[0])
-		 );
-
-	ALU16 CPU_ALU16 (
-		 .D0(ALU160), 
-		 .D1(ALU161), 
-		 .DOUT(ADDR), 
-		 .OP(ALU16OP)
-		 );
-
-	always @(posedge CLK)
-		if(!WAIT) begin
-			SRESET <= RESET;
-			SNMI <= NMI;
-			SINT <= INT;
-			if(!SNMI) FNMI <= 0; 
-			if(SRESET) FETCH <= 10'b1110000000;
-			else 
-				if(FETCH[9:6] == 4'b1110) {FETCH[9:7]} <= 3'b000;	// exit RESET state
-				else begin 
-					if(M1 || (fetch98 == 2'b10))	// [DD/FD CB disp op] -  M1 is inactive during <op> byte read, but FETCH is performed
-						case({MREQ, CPUStatus[9:8]})
-							3'b000, 3'b001, 3'b100, 3'b101, 3'b110, 3'b111: FETCH <= {fetch98, DI};
-							3'b010: FETCH <= {fetch98, 8'hff};	// IM1 - RST38
-							3'b011: ; // IM2 - get addrLO
-						endcase
-					if(~|{next_stage, fetch98[1:0], status[4]})				// INT or NMI sample
-						if(SNMI & !FNMI) begin						// NMI posedge
-							{FETCH[9:6], FETCH[1:0]} <= {4'b1101, HALT, M1};
-							FNMI <= 1;	// NMI acknowledged
-						end else if(SINT & CPUStatus[6] & !status[11]) {FETCH[9:6], FETCH[1:0]} <= {4'b1100, HALT, M1};	// INT request
-				end
-			if(next_stage) STAGE <= STAGE + 3'b001;
-			else STAGE <= 0;
-			if(status[4]) CPUStatus[5:4] <= status[5:4];
-			else if(~|{next_stage, fetch98[1]} | fetch98[0]) CPUStatus[4] <= 1'b0;		// clear X
-			CPUStatus[3:0] <= CPUStatus[3:0] ^ status[3:0];
-			if(status[11]) CPUStatus[7:6] <= status[7:6]; 	// IFF2:1
-			if(status[10]) CPUStatus[9:8] <= status[9:8];	// IMM
-			tzf <= ALU8FLAGS[6];
-		end
-
-	assign opd[0] = FETCH[0] ^ &FETCH[2:1];
-	assign opd[2:1] = FETCH[2:1];
-	assign opd[3] = FETCH[3] ^ &FETCH[5:4];
-	assign opd[5:4] = FETCH[5:4];
-	assign op16[2:0] = &FETCH[5:4] ? 3'b101 : {1'b0, FETCH[5:4]};
-
-	always @* begin
-		DO_SEL	= 2'bxx;						// ALU80 - th - flags - ALU8OUT[7:0]
-		ALU160_SEL = 1'bx;					// regs - pc
-		DINW_SEL = 1'bx;						// ALU8OUT - DI
-		WE 		= 6'bxxxxxx;				// 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo
-		ALU8OP	= 5'bxxxxx;
-		ALU16OP	= 3'b000;					// NOP, post inc
-		next_stage = 0;
-		REG_WSEL	= 4'bxxxx;
-		REG_RSEL	= 4'bx0xx;				// prevents default 4'b0100 which leads to incorrect P flag value in some cases (like RLA)
-		M1 		= 1;
-		MREQ		= 1;
-		WR			= 0;
-
-		HALT = 0;
-		IORQ = 0;
-		status	= 12'b00xxxxx00000;
-		fetch98 = 2'b00;
-		
-		case({FETCH[7:6], op1mem, op0mem})
-			4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b1000, 4'b1100: xmask = 1;
-			default: xmask = 0;
-		endcase
-		
-		case(FETCH[9:6])	
-//------------------------------------------- block 00 ----------------------------------------------------
-			4'b0000:
-				case(FETCH[3:0])
-//				-----------------------		NOP, EX AF, AF', DJNZ, JR, JR c --------------------
-					4'b0000, 4'b1000:	
-						case(FETCH[5:4])
-							2'b00: begin					// NOP, EX AF, AF'
-								DO_SEL	= 2'bxx;			
-								ALU160_SEL = 1;			// PC
-								WE 		= 6'b010x00;	// PC
-								status[0] = FETCH[3];
-							end
-							2'b01:				
-								if(!STAGE[0]) begin		// DJNZ, JR - stage1
-									ALU160_SEL = 1;				// pc
-									WE 		= 6'b010100;		// PC, tmpHI
-									if(!FETCH[3]) begin
-										ALU8OP	= 5'b01010;			// DEC, for tzf only
-										REG_WSEL	= 4'b0000;			// B
-									end
-									next_stage = 1;
-									M1 		= 0;
-								end else if(FETCH[3]) begin	// JR - stage2
-									ALU160_SEL = 1;				// pc
-									WE 		= 6'b010x00;		// PC
-									ALU16OP	= 3;					// ADD
-								end else begin				// DJNZ - stage2
-									ALU160_SEL = 1;				// pc
-									DINW_SEL = 0;					// ALU8OUT
-									WE 		= 6'b010x10;		// PC, hi
-									ALU8OP	= 5'b01010;			// DEC
-									ALU16OP	= tzf ? 3'd0 : 3'd3;		// NOP/ADD
-									REG_WSEL	= 4'b0000;			// B
-								end
-							2'b10, 2'b11: 							// JR cc, stage1, stage2
-								case({STAGE[0], FlagMux[{1'b0, FETCH[4:3]}]})
-									2'b00, 2'b11: begin
-										ALU160_SEL = 1;				// pc
-										WE 		= 6'b010x00;		// PC
-										ALU16OP	= STAGE[0] ? 3'd3 : 3'd1;		// ADD/ INC, post inc
-									end 
-									2'b01: begin
-										ALU160_SEL = 1;				// pc
-										WE 		= 6'b010100;		// PC, tmpHI
-										next_stage = 1; 
-										M1 		= 0;
-									end
-								endcase
-						endcase
-//				-----------------------		LD rr,nn  --------------------
-					4'b0001: 			// LD rr,nn, stage1
-						case({STAGE[1:0], op16[2]})
-							3'b00_0, 3'b00_1, 3'b01_0, 3'b01_1: begin			// LD rr,nn, stage1,2
-								ALU160_SEL = 1;			// pc
-								DINW_SEL = 1;				// DI
-								WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};	// PC, lo/HI
-								next_stage = 1;
-								REG_WSEL	= {op16, 1'bx}; 
-								M1 		= 0;
-							end
-							3'b10_0, 3'b11_1: begin		// BC, DE, HL, stage3, SP stage4
-								ALU160_SEL = 1;			// pc
-								WE 		= 6'b010x00;	// PC
-							end
-							3'b10_1: begin				// SP stage3
-								ALU160_SEL = 0;			// regs
-								WE 		= 6'b001x00;	// SP
-								ALU16OP	= 4;				// NOP
-								next_stage = 1;
-								REG_RSEL	= 4'b101x;		// tmpSP
-								M1 		= 0;
-								MREQ		= 0;
-							end
-						endcase
-//				-----------------------		LD (BC) A -  LD (DE) A - LD (nn) HL, LD (nn),A   --------------------
-//				-----------------------		LD A (BC) -  LD A (DE) - LD HL (nn), LD A (nn)   --------------------
-					4'b0010,	4'b1010:
-						case(STAGE[2:0])
-							3'b000:
-								if(FETCH[5] == 0) begin			// LD (BC) A, LD (DE) A - stage1
-									if(FETCH[3]) DINW_SEL = 1;		// DI
-									else DO_SEL	= 2'b00;				// ALU80
-									ALU160_SEL = 0;				// regs
-									WE 		= {4'b000x, FETCH[3], 1'bx};		// hi
-									next_stage = 1;
-									REG_WSEL	= FETCH[3] ? 4'b011x : 4'b0110;	// A
-									REG_RSEL	= {op16, 1'bx};
-									M1 		= 0;
-									WR = !FETCH[3];
-								end else begin						// LD (nn) A - LD (nn) HL - stage 1
-									ALU160_SEL = 1;				// PC
-									DINW_SEL = 1;					// DI
-									WE 		= 6'b010xx1;		// PC, lo
-									next_stage = 1;
-									REG_WSEL	= 4'b111x;
-									M1 		= 0;
-								end
-							3'b001:
-								if(FETCH[5] == 0) begin			// LD (BC), A, LD (DE), A - stage2
-									ALU160_SEL = 1;				// pc
-									WE 		= 6'b010x00;		// PC
-								end else begin						// LD (nn),A  - LH (nn),HL - stage 2
-									ALU160_SEL = 1;				// pc
-									DINW_SEL = 1;					// DI
-									WE 		= 6'b010x10;		// PC, hi
-									next_stage = 1;
-									REG_WSEL	= 4'b111x;
-									M1 		= 0;
-								end
-							3'b010: begin					
-								ALU160_SEL = 1'b0;		// regs
-								REG_RSEL	= 4'b111x;
-								M1 		= 0;
-								WR			= !FETCH[3];
-								next_stage = 1;
-								if(FETCH[3]) begin		// LD A (nn)  - LD HL (nn) - stage 3
-									DINW_SEL = 1;				// DI
-									WE 		= {4'b000x, FETCH[4] ? 1'b1 : 1'bx, FETCH[4] ? 1'bx : 1'b1};	// lo/hi
-									REG_WSEL = FETCH[4] ? 4'b011x : 4'b010x;	// A or L
-								end else begin				// LD (nn),A  - LD (nn),HL - stage 3
-									DO_SEL	= 2'b00;			// ALU80
-									WE 		= 6'b000x00;	// nothing
-									REG_WSEL = FETCH[4] ? 4'b0110 : 4'b0101;	// A or L
-								end
-							end
-							3'b011:
-								if(FETCH[4]) begin			// LD (nn),A - stage 4
-									ALU160_SEL = 1;			// pc
-									WE 		= 6'b010x00;	// PC
-								end else begin					
-									REG_RSEL	= 4'b111x;
-									M1 		= 0;
-									WR			= !FETCH[3];
-									ALU160_SEL = 1'b0;		// regs
-									ALU16OP	= 1;				// INC
-									next_stage = 1;
-									if(FETCH[3]) begin	// LD HL (nn) - stage 4
-										DINW_SEL = 1;				// DI
-										WE 		= 6'b000x10;	// hi
-										REG_WSEL = 4'b010x;		// H
-									end else begin			// LD (nn),HL - stage 4
-										DO_SEL	= 2'b00;			// ALU80
-										WE 		= 6'b000x00;	// nothing
-										REG_WSEL = 4'b0100;		// H
-									end
-								end
-							3'b100: begin				// LD (nn),HL - stage 5
-								ALU160_SEL = 1;			// pc
-								WE 		= 6'b010x00;	// PC
-							end
-						endcase
-//				-----------------------		inc/dec rr   --------------------
-					4'b0011, 4'b1011:
-						if(!STAGE[0])
-							if(op16[2]) begin				// SP - stage1
-								ALU160_SEL = 0;			// regs
-								WE 		= 6'b001x00;	// SP
-								ALU16OP	= {FETCH[3], 1'b0, FETCH[3]};		// post inc, dec
-								next_stage = 1;
-								REG_RSEL	= 4'b101x;		// sp
-								M1 		= 0;
-								MREQ		= 0;
-							end else begin					// BC, DE, HL - stage 1
-								ALU160_SEL = 1;			// pc
-								DINW_SEL = 0;				// ALU8OUT
-								WE 		= 6'b010x11;	// PC, hi, lo
-								ALU8OP	= {4'b0111, FETCH[3]};			// INC16 / DEC16
-								REG_WSEL	= {op16, 1'b0};	// hi
-								REG_RSEL	= {op16, 1'b1};	// lo
-							end
-						else 	begin				// SP, stage2
-							ALU160_SEL = 1;			// pc
-							WE 		= 6'b010x00;	// PC
-						end
-//				-----------------------		inc/dec 8  --------------------
-					4'b0100, 4'b0101, 4'b1100, 4'b1101: 
-						if(!op1mem) begin						//regs
-							DINW_SEL = 0;						// ALU8OUT
-							ALU160_SEL = 1;					// pc
-							WE 		= opd[3] ? 6'b110x01 : 6'b110x10;	// flags, PC, hi/lo
-							ALU8OP	= {3'b010, FETCH[0], 1'b0};		// inc / dec
-							REG_WSEL	= {1'b0, opd[5:3]};
-						end else case({STAGE[1:0], CPUStatus[4]})
-							3'b00_0, 3'b01_1: begin				// (HL) - stage1, (X) - stage2
-								ALU160_SEL = 0;					// regs
-								DINW_SEL = 1;						// DI
-								WE 		= 6'b000001;			// lo
-								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
-								next_stage = 1;
-								REG_WSEL	= 4'b011x;				// tmpLO
-								REG_RSEL	= 4'b010x;				// HL
-								M1 		= 0;
-							end
-							3'b00_1:	begin							// (X) - stage1
-								ALU160_SEL = 1;					// pc
-								WE 		= 6'b010100;			// PC, tmpHI
-								next_stage = 1;
-								M1 		= 0;
-							end 
-							3'b01_0, 3'b10_1: begin					// (HL) stage2, (X) - stage3
-								DO_SEL	= 2'b11;						// ALU80OUT
-								ALU160_SEL = 0;						// regs
-								WE 		= 6'b100x0x;				// flags
-								ALU8OP	= {3'b010, FETCH[0], 1'b0};		// inc / dec
-								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
-								next_stage = 1;
-								REG_WSEL	= 4'b0111;					// tmpLO
-								REG_RSEL	= 4'b010x;					// HL
-								M1 		= 0;
-								WR			= 1;
-							end
-							3'b10_0, 3'b11_1: begin					// (HL) - stage3, (X) - stage 4
-								ALU160_SEL = 1;						// pc
-								WE 		= 6'b010x00;				// PC
-							end
-						endcase
-//				-----------------------		ld r/(HL-X), n  --------------------						
-					4'b0110, 4'b1110: 				
-						case({STAGE[1:0], CPUStatus[4], op1mem})
-							4'b00_0_0, 4'b00_0_1, 4'b00_1_0, 4'b01_1_1: begin		// r, (HL) - stage1, (X) - stage2 (read n)
-								ALU160_SEL = 1;					// pc
-								DINW_SEL = 1;						// DI
-								WE 		= opd[3] ? 6'b010001 : 6'b010010;			// PC, hi/lo
-								next_stage = 1;
-								REG_WSEL	= {1'b0, opd[5:4], 1'bx};
-								M1 		= 0;
-							end
-							4'b01_0_0, 4'b01_1_0, 4'b10_0_1, 4'b11_1_1: begin		// r - stage2, (HL) - stage3, (X) - stage4
-								ALU160_SEL = 1;						// pc
-								WE 		= 6'b010x00;				// PC
-							end
-							4'b01_0_1, 4'b10_1_1: begin			// (HL) - stage2, (X) - stage3
-								DO_SEL	= 2'b00;						// ALU80
-								ALU160_SEL = 0;						// regs
-								WE 		= 6'b000x0x;				// nothing
-								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
-								next_stage = 1;
-								REG_WSEL	= 4'b0111;					// tmpLO
-								REG_RSEL	= 4'b010x;					// HL
-								M1 		= 0;
-								WR			= 1;
-							end
-							4'b00_1_1: begin							// (X) - stage1
-								ALU160_SEL = 1;						// pc
-								WE 		= 6'b010100;				// PC, tmpHI
-								next_stage = 1;
-								M1 		= 0;
-							end
-						endcase
-//				-----------------------		rlca, rrca, rla, rra, daa, cpl, scf, ccf  --------------------						
-					4'b0111, 4'b1111: 				
-						case(FETCH[5:3])
-							3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101: begin		// rlca, rrca, rla, rra, daa, cpl
-								ALU160_SEL = 1;					// pc
-								DINW_SEL = 0;						// ALU8OUT
-								WE 		= 6'b110x1x;			// flags, PC, hi
-								ALU8OP	= FETCH[5] ? {2'b01, !FETCH[3], 2'b01} : {3'b110, FETCH[4:3]};
-								REG_WSEL	= 4'b0110;				// A
-							end
-							3'b110, 3'b111:	begin				// scf, ccf
-								ALU160_SEL = 1;					// pc
-								DINW_SEL = 0;						// ALU8OUT
-								WE 		= 6'b110x0x;			// flags, PC
-								ALU8OP	= {4'b1010, !FETCH[3]};
-							end
-						endcase
-//				-----------------------		add 16  --------------------						
-					4'b1001: 
-						if(!STAGE[0]) begin
-							DINW_SEL = 0;						// ALU8OUT
-							WE 		= 6'b100x01;			// flags, lo
-							ALU8OP	= 5'b10000;				// ADD16LO
-							next_stage = 1;
-							REG_WSEL	= 4'b0101;				// L
-							REG_RSEL	= {op16, 1'b1};
-							M1 		= 0;
-							MREQ		= 0;
-						end else begin
-							ALU160_SEL = 1;					// pc
-							DINW_SEL = 0;						// ALU8OUT
-							WE 		= 6'b110x10;			// flags, PC, hi
-							ALU8OP	= 5'b10001;				// ADD16HI
-							REG_WSEL	= 4'b0100;				// H
-							REG_RSEL	= {op16, 1'b0};
-						end
-				endcase
-
-// ---------------------------------------------- block 01 LD8 ---------------------------------------------------
-			4'b0001:	
-				case({STAGE[1:0], CPUStatus[4], op1mem, op0mem})
-					5'b00_0_00, 5'b00_1_00,		// LD r, r 1st stage
-					5'b01_0_01,						// LD r, (HL) 2nd stage
-					5'b10_1_01:						// LD r, (X) 3rd stage
-					begin	
-						ALU160_SEL = 1;			// PC
-						DINW_SEL	  = 0;			// ALU8
-						WE = opd[3] ? 6'b010x01 : 6'b010x10;	// PC and LO or HI
-						ALU8OP = 29;				// PASS D1
-						REG_WSEL = {1'b0, opd[5:4], 1'bx};
-						REG_RSEL = {1'b0, opd[2:0]};
-					end
-					5'b00_0_01,						// LD r, (HL) 1st stage
-					5'b01_1_01:						// LD r, (X) 2nd stage
-					begin	
-						ALU160_SEL = 0;			// regs
-						DINW_SEL = 1;				// DI		
-						WE 		= 6'b000x01;	// LO
-						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;		// ADD - NOP
-						next_stage = 1;
-						REG_WSEL	= 4'b011x;		// A - tmpLO
-						REG_RSEL = 4'b010x;		// HL
-						M1 = 0;
-					end
-					5'b00_1_01,						// LD r, (X) 1st stage
-					5'b00_1_10:						// LD (X), r 1st stage
-					begin
-						ALU160_SEL = 1;			// pc
-						WE 		= 6'b010100;	// PC, tmpHI
-						next_stage = 1;
-						M1 		= 0;
-					end
-					5'b00_0_10, 					// LD (HL), r 1st stage
-					5'b01_1_10:						// LD (X), r 2nd stage
-					begin	
-						DO_SEL	= 0;				// ALU80
-						ALU160_SEL = 0;			// regs
-						WE 		= 6'b000x00;	// no write
-						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;			// ADD - NOP
-						next_stage = 1;
-						REG_WSEL	= {1'b0, opd[2:0]};
-						REG_RSEL	= 4'b010x;		// HL
-						M1 		= 0;
-						WR			= 1;			
-					end
-					5'b01_0_10, 					// LD (HL), r 2nd stage
-					5'b10_1_10:						// LD (X), r 3rd stage
-					begin	
-						ALU160_SEL = 1;			// pc
-						WE 		= 6'b010x00;	// PC
-					end
-					5'b00_0_11, 5'b00_1_11: begin	// HALT
-						WE 		= 6'b000x00;	// no write
-						M1 		= 0;
-						MREQ		= 0;
-						HALT 		= 1;
-					end
-				endcase
-// ---------------------------------------------- block 10 arith8 ---------------------------------------------------
-			4'b0010:	
-				case({STAGE[1:0], CPUStatus[4], op0mem})
-					4'b00_0_0, 4'b00_1_0,		// OP r,r 1st stage
-					4'b01_0_1,						// OP r, (HL) 2nd stage
-					4'b10_1_1:						// OP r, (X) 3rd stage
-					begin
-						ALU160_SEL = 1;			// pc
-						DINW_SEL = 0;				// ALU8OUT
-						WE 		= {4'b110x, ~&FETCH[5:3], 1'bx};	// flags, PC, hi
-						ALU8OP	= {2'b00, FETCH[5:3]};
-						REG_WSEL	= 4'b0110;		// A
-						REG_RSEL	= {1'b0, opd[2:0]};
-					end
-					4'b00_0_1,						// OP r, (HL) 1st stage
-					4'b01_1_1:						// OP r, (X) 2nd stage
-					begin
-						ALU160_SEL = 0;			// HL
-						DINW_SEL = 1;				// DI
-						WE 		= 6'b000x01;	// lo
-						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;			// ADD - NOP
-						next_stage = 1;
-						REG_WSEL	= 4'b011x;		// A-tmpLO
-						REG_RSEL	= 4'b010x;		// HL
-						M1 		= 0;
-					end
-					4'b00_1_1:						// OP r, (X) 1st stage
-					begin
-						ALU160_SEL = 1;			// pc
-						WE 		= 6'b010100;	// PC, tmpHI
-						next_stage = 1;
-						M1 		= 0;
-					end
-				endcase
-//------------------------------------------- block 11 ----------------------------------------------------
-			4'b0011:
-				case(FETCH[3:0])
-//				-----------------------		RET cc --------------------
-					4'b0000, 4'b1000:
-						case(STAGE[1:0])
-							2'b00, 2'b01:			// stage1, stage2
-								if(FlagMux[FETCH[5:3]]) begin	// POP addr
-									ALU160_SEL = 0;				// regs
-									DINW_SEL = 1;					// DI
-									WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};		// SP, lo/hi
-									next_stage = 1;
-									REG_WSEL	= 4'b111x;			// tmp16
-									REG_RSEL	= 4'b101x;			// SP
-									M1 		= 0;
-								end else begin
-									ALU160_SEL = 1;				// pc
-									WE 		= 6'b010x00;		// PC
-								end
-							2'b10: begin			// stage3
-								ALU160_SEL = 0;					// regs
-								WE 		= 6'b010x00;			// PC
-								REG_RSEL	= 4'b111x;				// tmp16
-							end
-						endcase
-//				-----------------------		POP --------------------
-					4'b0001:
-						case(STAGE[1:0])
-							2'b00, 2'b01: begin
-								if(op16[2]) begin	// AF
-									WE 		= STAGE[0] ? 6'b101x1x : 6'b001xx1;		// flags, SP, lo/hi
-									REG_WSEL	= {3'b011, STAGE[0] ? 1'b1 : 1'bx};
-									if(STAGE[0]) ALU8OP	= 30;						// FLAGS <- D0
-								end else begin		// r16
-									WE 		= STAGE[0] ? 6'b001x10 : 6'b001xx1;		// SP, lo/hi
-									REG_WSEL	= {1'b0, FETCH[5:4], 1'bx};
-								end
-								ALU160_SEL = 0;			// regs
-								DINW_SEL = 1;				// DI
-								next_stage = 1;
-								REG_RSEL	= 4'b101x;		// SP
-								M1 		= 0;
-							end
-							2'b10: begin					// stage3
-								ALU160_SEL = 1;			// PC
-								WE 		= 6'b010x00;	// PC
-							end
-						endcase
-//				-----------------------		JP cc --------------------
-					4'b0010, 4'b1010:
-						case(STAGE[1:0])
-							2'b00, 2'b01:	begin				// stage1,2
-								if(FlagMux[FETCH[5:3]]) begin
-									ALU160_SEL = 1;					// pc
-									DINW_SEL = 1;						// DI
-									WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};		// PC, hi/lo
-									next_stage = 1;
-									REG_WSEL	= 4'b111x;				// tmp7
-									M1 		= 0;
-								end else begin
-									ALU160_SEL = 1;					// pc
-									WE 		= 6'b010x00;			// PC
-									ALU16OP	= 2;						// add2
-								end
-							end
-							2'b10: begin						// stage3
-								ALU160_SEL = 0;					// regs
-								WE 		= 6'b010x00;			// PC
-								REG_RSEL	= 4'b111x;				// tmp7
-							end
-						endcase
-//				-----------------------		JP, OUT (n) A, EX (SP) HL, DI --------------------
-					4'b0011:
-						case(FETCH[5:4])
-							2'b00:					// JP
-								case(STAGE[1:0])
-									2'b00, 2'b01:	begin				// stage1,2 - read addr
-										ALU160_SEL = 1;					// pc
-										DINW_SEL = 1;						// DI
-										WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};		// PC, hi/lo
-										next_stage = 1;
-										REG_WSEL	= 4'b111x;				// tmp7
-										M1 		= 0;
-									end
-									2'b10: begin						// stage3
-										ALU160_SEL = 0;					// regs
-										WE 		= 6'b010x00;			// PC
-										REG_RSEL	= 4'b111x;				// tmp7
-									end
-								endcase
-							2'b01: 					// OUT (n), a - stage1 - read n
-								case(STAGE[1:0])
-									2'b00: begin
-										ALU160_SEL = 1;					// pc
-										DINW_SEL = 1;						// DI
-										WE 		= 6'b010x01;			// PC, lo
-										next_stage = 1;
-										REG_WSEL	= 4'b011x;				// tmpLO
-										M1 		= 0;
-									end
-									2'b01: begin		// stage2 - OUT
-										DO_SEL	= 2'b00;					// ALU80
-										ALU160_SEL = 0;					// regs
-										WE 		= 6'b000x00;			// nothing
-										next_stage = 1;
-										REG_WSEL	= 4'b0110;				// A
-										REG_RSEL	= 4'b011x;				// A-tmpLO
-										M1 		= 0;
-										MREQ		= 0;
-										WR 		= 1;
-										IORQ		= 1;
-									end
-									2'b10: begin		// stage3 - fetch
-										ALU160_SEL = 1;			// PC
-										WE 		= 6'b010x00;	// PC
-									end
-								endcase
-							2'b10:				// EX (SP), HL
-								case(STAGE[2:0])
-									3'b000, 3'b001:	begin			// stage1,2 - pop tmp16
-										ALU160_SEL = 0;					// regs
-										DINW_SEL = 1;						// DI
-										WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};			// SP, lo/hi
-										next_stage = 1;
-										REG_WSEL	= 4'b111x;				// tmp16
-										REG_RSEL	= 4'b101x;				// SP
-										M1 		= 0;
-									end
-									3'b010, 3'b011: begin			// stage3,4 - push hl
-										DO_SEL	= 2'b00;					// ALU80
-										ALU160_SEL = 0;					// regs
-										WE 		= 6'b001x00;			// SP
-										ALU16OP	= 5;						// dec
-										next_stage = 1;
-										REG_WSEL	= {3'b010, STAGE[0]};// H/L	
-										REG_RSEL	= 4'b101x;				// SP
-										M1 		= 0;
-										WR			= 1;
-									end
-									3'b100, 3'b101: begin		// stage5,6
-										ALU160_SEL = 1;					// pc
-										DINW_SEL = 0;						// ALU8OUT
-										WE 		= {1'b0, STAGE[0], 2'b0x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};	// PC, lo/hi
-										ALU8OP	= 29;		// pass D1
-										next_stage = !STAGE[0];
-										REG_WSEL	= 4'b010x;		// HL
-										REG_RSEL	= {3'b111, !STAGE[0]};		// tmp16
-										M1 		= STAGE[0];
-										MREQ		= STAGE[0];
-									end
-								endcase
-							2'b11:	begin			// DI
-								ALU160_SEL = 1;			// PC
-								WE 		= 6'b010x00;	// PC
-								status[11] = 1'b1;		// set IFF flags
-								status[7:6] = 2'b00;
-							end
-						endcase
-//				-----------------------		CALL cc --------------------
-					4'b0100, 4'b1100:	
-						case(STAGE[2:0])
-							3'b000, 3'b001:		// stage 1,2 - load addr
-								if(FlagMux[FETCH[5:3]]) begin
-									ALU160_SEL = 1;					// pc
-									DINW_SEL = 1;						// DI
-									WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};		// PC, hi/lo
-									next_stage = 1;
-									REG_WSEL	= 4'b111x;				// tmp7
-									M1 		= 0;
-								end else begin
-									ALU160_SEL = 1;					// pc
-									WE 		= 6'b010x00;			// PC
-									ALU16OP	= 2;						// add2
-								end
-							3'b010, 3'b011: begin		// stage 3,4 - push pc
-								DO_SEL	= {1'b0, STAGE[0]};	// pc hi/lo
-								ALU160_SEL = 0;					// regs
-								WE 		= 6'b001x00;			// SP
-								ALU16OP	= 5;						// DEC
-								next_stage = 1;
-								REG_WSEL	= 4'b1xxx;				// pc
-								REG_RSEL	= 4'b101x;				// sp
-								M1 		= 0;
-								WR			= 1;
-							end
-							3'b100:	begin	// stage5
-								ALU160_SEL = 0;					// regs
-								WE 		= 6'b010x00;			// PC
-								REG_RSEL	= 4'b111x;				// tmp7
-							end
-						endcase
-//				-----------------------		PUSH --------------------
-					4'b0101: 
-						case(STAGE[1:0])
-							2'b00, 2'b01: begin			// stage1,2
-								DO_SEL	= {STAGE[0] & op16[2], 1'b0};		// FLAGS/ALU80
-								ALU160_SEL = 0;				// regs
-								WE 		= 6'b001x00;		// SP
-								ALU16OP	= 5;  				// dec
-								next_stage = 1;
-								REG_WSEL	= {1'b0, FETCH[5:4], STAGE[0]};
-								REG_RSEL	= 4'b101x;				// SP
-								M1 		= 0;
-								WR			= 1;
-							end
-							2'b10: begin					//stage3
-								ALU160_SEL = 1;				// PC
-								WE 		= 6'b010x00;		// PC
-							end
-						endcase
-//				-----------------------		op A, n  --------------------
-					4'b0110, 4'b1110:
-						if(!STAGE[0]) begin			// stage1, read n
-							ALU160_SEL = 1;					// pc
-							DINW_SEL = 1;						// DI
-							WE 		= 6'b010x01;			// PC, lo
-							next_stage = 1;
-							REG_WSEL	= 4'b011x;				// tmpLO
-							M1 		= 0;
-						end else begin					// stage 2
-							DINW_SEL = 0;						// ALU8OUT[7:0]
-							ALU160_SEL = 1;					// pc
-							WE 		= {4'b110x, ~&FETCH[5:3], 1'bx};			// flags, PC, hi
-							ALU8OP	= {2'b00, FETCH[5:3]};
-							REG_WSEL	= 4'b0110;				// A
-							REG_RSEL	= 4'b0111;				// tmpLO
-						end
-//				-----------------------		RST  --------------------
-					4'b0111, 4'b1111:
-						case(STAGE[1:0])
-							2'b00, 2'b01: begin		// stage 1,2 - push pc
-								DO_SEL	= {1'b0, STAGE[0]};	// pc hi/lo
-								ALU160_SEL = 0;					// regs
-								WE 		= 6'b001x00;			// SP
-								ALU16OP	= 5;						// DEC
-								next_stage = 1;
-								REG_WSEL	= 4'b1xxx;				// pc
-								REG_RSEL	= 4'b101x;				// sp
-								M1 		= 0;
-								WR			= 1;
-							end
-							2'b10:	begin				// stage3
-								ALU160_SEL = 0;					// regs
-								WE 		= 6'b010x00;			// PC
-								REG_RSEL	= 4'b110x;				// const
-							end
-						endcase
-//				-----------------------		RET, EXX, JP (HL), LD SP HL --------------------
-					4'b1001:	
-						case(FETCH[5:4])	
-							2'b00: 				// RET
-								case(STAGE[1:0])
-									2'b00, 2'b01:	begin		// stage1, stage2 - pop addr
-										ALU160_SEL = 0;				// regs
-										DINW_SEL = 1;					// DI
-										WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};		// SP, lo/hi
-										next_stage = 1;
-										REG_WSEL	= 4'b111x;			// tmp16
-										REG_RSEL	= 4'b101x;			// SP
-										M1 		= 0;
-									end		
-									2'b10: begin			// stage3 - jump
-										ALU160_SEL = 0;					// regs
-										WE 		= 6'b010x00;			// PC
-										REG_RSEL	= 4'b111x;				// tmp16
-									end
-								endcase
-							2'b01: begin			// EXX
-								ALU160_SEL = 1;			// PC
-								WE 		= 6'b010x00;	// PC
-								status[1] = 1;			
-							end
-							2'b10:	begin		// JP (HL)
-								ALU160_SEL = 0;					// regs
-								WE 		= 6'b010x00;			// PC
-								REG_RSEL	= 4'b010x;				// HL
-							end
-							2'b11: begin	// LD SP,HL	
-								if(!STAGE[0]) begin			// stage1
-									ALU160_SEL = 0;				// regs
-									WE 		= 6'b001x00;		// SP
-									ALU16OP	= 4;					// NOP, no post inc
-									next_stage = 1;
-									REG_RSEL	= 4'b010x;			// HL
-									M1 		= 0;
-									MREQ		= 0;
-								end else begin						// stage2
-									ALU160_SEL = 1;				// pc
-									WE 		= 6'b010x00;		// PC
-								end
-							end
-						endcase
-//				-----------------------		CB, IN A (n), EX DE HL, EI --------------------
-					4'b1011:
-						case(FETCH[5:4])
-							2'b00:  					// CB prefix
-								case({STAGE[0], CPUStatus[4]})
-									2'b00, 2'b11: begin
-										ALU160_SEL = 1;			// PC
-										WE 		= 6'b010000;	// PC
-										fetch98 = 2'b10;		
-										M1 = !CPUStatus[4]; 	// [DD/FD CB disp op] -  M1 is inactive during <op> byte read
-									end
-									2'b01: begin
-										ALU160_SEL = 1;			// PC
-										WE 		= 6'b010100;	// PC, tmpHI
-										next_stage = 1;
-										M1 		= 0;
-									end
-								endcase
-							2'b01:					// IN A, (n)
-								case(STAGE[1:0])
-									2'b00: begin		//stage1 - read n
-										ALU160_SEL = 1;				// pc
-										DINW_SEL = 1;					// DI
-										WE 		= 6'b010x01;		// PC, lo
-										next_stage = 1;
-										REG_WSEL	= 4'b011x;			// tmpLO
-										M1 		= 0;
-									end
-									2'b01: begin		// stage2 - IN
-										ALU160_SEL = 0;				// regs
-										DINW_SEL = 1;					// DI
-										WE 		= 6'b000x1x;		// hi
-										next_stage = 1;
-										REG_WSEL	= 4'b011x;			// A
-										REG_RSEL	= 4'b011x;			// A - tmpLO
-										M1 		= 0;
-										MREQ		= 0;
-										IORQ		= 1;
-									end
-									2'b10: begin		// stage3 - fetch
-										ALU160_SEL = 1;			// PC
-										WE 		= 6'b010x00;	// PC
-									end
-								endcase
-							2'b10: begin			// EX DE, HL
-								ALU160_SEL = 1;			// PC
-								WE 		= 6'b010x00;	// PC
-								if(CPUStatus[1]) status[3] = 1;	
-								else status[2] = 1;
-							end
-							2'b11: begin			// EI
-								ALU160_SEL = 1;			// PC
-								WE 		= 6'b010x00;	// PC
-								status[11] = 1'b1;
-								status[7:6] = 2'b11;
-							end
-						endcase
-//				-----------------------		CALL , IX, ED, IY --------------------
-					4'b1101:	
-						case(FETCH[5:4])
-							2'b00: 					// CALL
-								case(STAGE[2:0])
-									3'b000, 3'b001: begin		// stage 1,2 - load addr
-										ALU160_SEL = 1;					// pc
-										DINW_SEL = 1;						// DI
-										WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};		// PC, hi/lo
-										next_stage = 1;
-										REG_WSEL	= 4'b111x;				// tmp7
-										M1 		= 0;
-									end
-									3'b010, 3'b011: begin		// stage 3,4 - push pc
-										DO_SEL	= {1'b0, STAGE[0]};	// pc hi/lo
-										ALU160_SEL = 0;					// regs
-										WE 		= 6'b001x00;			// SP
-										ALU16OP	= 5;						// DEC
-										next_stage = 1;
-										REG_WSEL	= 4'b1xxx;				// pc
-										REG_RSEL	= 4'b101x;				// sp
-										M1 		= 0;
-										WR			= 1;
-									end
-									3'b100:	begin	// stage5 - jump
-										ALU160_SEL = 0;					// regs
-										WE 		= 6'b010x00;			// PC
-										REG_RSEL	= 4'b111x;				// tmp7
-									end
-								endcase
-							2'b01: begin			// DD - IX
-								ALU160_SEL = 1;			// PC
-								WE 		= 6'b010x00;	// PC
-								status[5:4] = 2'b01;
-							end
-							2'b10: begin			// ED prefix
-								ALU160_SEL = 1;			// PC
-								WE 		= 6'b010x00;	// PC
-								fetch98 = 2'b01;		
-							end
-							2'b11:	begin			// FD - IY
-								ALU160_SEL = 1;			// PC
-								WE 		= 6'b010x00;	// PC
-								status[5:4]	= 2'b11;	
-							end
-						endcase
-				endcase
-
-//	------------------------------------------- ED + opcode ----------------------------------------------------
-			4'b0100, 4'b0111: begin		// ED + 2'b00, ED + 2'b11 		= NOP
-				ALU160_SEL = 1;			// PC
-				WE 		= 6'b010x00;	// PC
-			end
-			4'b0101:
-				case(FETCH[2:0])
-//				-----------------------		in r (C)  --------------------
-					3'b000:
-						if(!STAGE[0]) begin
-							ALU160_SEL = 0;					// regs
-							DINW_SEL = 1;						// DI
-							WE 		= {4'b000x, !opd[3], opd[3]} ;	// hi/lo
-							next_stage = 1;
-							REG_WSEL	= {1'b0, opd[5:4], 1'bx};
-							REG_RSEL	= 4'b000x;				// BC
-							M1 		= 0;
-							MREQ		= 0;
-							IORQ 		= 1;
-						end else begin
-							ALU160_SEL = 1;					// pc
-							WE 		= 6'b110x00;			// flags, PC
-							ALU8OP	= 29;						// IN
-							REG_RSEL	= {1'b0, opd[5:3]};	// reg
-						end
-//				-----------------------		out (C) r  --------------------
-					3'b001:
-						if(!STAGE[0]) begin
-							DO_SEL	= 2'b00;					// ALU80
-							ALU160_SEL = 0;					// regs
-							WE 		= 6'b000x00;			// nothing
-							next_stage = 1;
-							REG_WSEL	= &opd[5:3] ? 4'b110x : {1'b0, opd[5:3]}; // zero/reg
-							REG_RSEL	= 4'b000x;				// BC
-							M1 		= 0;
-							MREQ		= 0;
-							WR			= 1;
-							IORQ 		= 1;
-						end else begin
-							ALU160_SEL = 1;					// pc
-							WE 		= 6'b010x00;			// PC
-						end
-//				-----------------------		SBC16, ADC16  --------------------
-					3'b010:
-						if(!STAGE[0]) begin			// stage1
-							DINW_SEL = 0;						// ALU8OUT
-							WE 		= 6'b100x01;			// flags, lo
-							ALU8OP	= {3'b000, !FETCH[3], 1'b1};	// SBC/ADC
-							next_stage = 1;
-							REG_WSEL	= 4'b0101;				// L			
-							REG_RSEL	= {op16, 1'b1};
-							M1 		= 0;
-							MREQ		= 0;
-						end else begin
-							ALU160_SEL = 1;					// pc
-							DINW_SEL = 0;						// ALU8OUT
-							WE 		= 6'b110x10;			// flags, PC, hi
-							ALU8OP	= {3'b000, !FETCH[3], 1'b1};
-							REG_WSEL	= 4'b0100;				// H
-							REG_RSEL	= {op16, 1'b0};
-						end
-//				-----------------------		LD (nn) r16, ld r16 (nn)  --------------------
-					3'b011:
-						case(STAGE[2:1])
-							2'b00:	begin // stage 1,2 - read address
-								ALU160_SEL = 1;				// pc
-								DINW_SEL = 1;					// DI
-								WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};	// PC, hi/lo
-								next_stage = 1;
-								REG_WSEL	= 4'b111x;			// tmp16
-								M1 		= 0;
-							end
-							2'b01: begin
-								ALU160_SEL = 0;			// regs
-								next_stage = 1;
-								ALU16OP	= {2'b00, STAGE[0]};				
-								REG_RSEL	= 4'b111x;		// tmp16
-								REG_WSEL	= {op16, !STAGE[0]};
-								M1 		= 0;
-								if(FETCH[3]) begin	// LD rr, (nn) - stage3,4
-									DINW_SEL = 1;				// DI
-									WE 		= {4'b000x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};	// lo
-								end else begin			// LD (nn), rr - stage3,4
-									DO_SEL	= op16[2] ? {1'b1, !STAGE[0]} : 2'b00;				// ALU80/sp
-									WE 		= 6'b000x00;		// nothing
-									WR			= 1;
-								end
-							end
-							2'b10:		// stage5 
-								if(FETCH[3] & op16[2] & !STAGE[0]) begin	// LD sp, (nn) - stage5
-									ALU160_SEL = 0;					// regs
-									WE 		= 6'b001x00;			// SP
-									ALU16OP	= 4;						// NOP
-									next_stage = 1;
-									REG_RSEL	= 4'b101x;				// tmp SP
-									M1 		= 0;
-									MREQ		= 0;
-								end else begin
-									ALU160_SEL = 1;					// pc
-									WE 		= 6'b010x00;			// PC
-								end
-							endcase
-//				-----------------------		NEG  --------------------
-					3'b100: begin
-						ALU160_SEL = 1;					// pc
-						DINW_SEL = 0;						// ALU8OUT
-						WE 		= 6'b110x10;			// flags, PC, hi
-						ALU8OP	= 5'b11111;				// NEG
-						REG_WSEL	= 4'b011x;				// A
-						REG_RSEL	= 4'b0110;				// A
-					end
-//				-----------------------		RETN, RETI  --------------------
-					3'b101:
-						case(STAGE[1:0])
-							2'b00, 2'b01:	begin		// stage1, stage2 - pop addr
-								ALU160_SEL = 0;				// regs
-								DINW_SEL = 1;					// DI
-								WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};		// SP, lo/hi
-								next_stage = 1;
-								REG_WSEL	= 4'b111x;			// tmp16
-								REG_RSEL	= 4'b101x;			// SP
-								M1 		= 0;
-							end		
-							2'b10: begin			// stage3 - jump
-								ALU160_SEL = 0;					// regs
-								WE 		= 6'b010x00;			// PC
-								REG_RSEL	= 4'b111x;				// tmp16
-								status[11] = 1'b1;
-								status[7:6] = {CPUStatus[7], CPUStatus[7]};
-							end
-						endcase
-//				-----------------------		IM  --------------------
-					3'b110: begin
-						ALU160_SEL = 1;					// PC
-						WE 		= 6'b010x00;			// PC
-						status[10:8] = {1'b1, FETCH[4:3]};
-					end
-//				-----------------------		LD I A, LD R A, LD A I, LD A R, RRD, RLD  --------------------
-					3'b111:
-						case(FETCH[5:4])
-							2'b00: begin	// LD I/R A
-								ALU160_SEL = 1;					// pc
-								DINW_SEL = 1'b0;					// ALU8OUT
-								WE 		= {4'b010x, !FETCH[3], FETCH[3]};	// PC, hi/lo
-								ALU8OP	= 29;						// pass D1
-								REG_WSEL	= 4'b1001;				// IR, write r
-								REG_RSEL	= 4'b0110;				// A
-							end
-							2'b01: begin	// LD A I/R
-								ALU160_SEL = 1;					// pc
-								DINW_SEL = 1'b0;					// ALU8OUT
-								WE 		= 6'b110x1x;			// flags, PC, hi
-								ALU8OP	= 29;						// PASS D1
-								REG_WSEL	= 4'b011x;				// A
-								REG_RSEL	= {3'b100, FETCH[3]};// I/R
-							end
-							2'b10: 			// RRD, RLD
-								case(STAGE[1:0])
-									2'b00:begin		// stage1, read data
-										ALU160_SEL = 0;					// regs
-										DINW_SEL = 1;						// DI
-										WE 		= 6'b000x01;			// lo
-										next_stage = 1;
-										REG_WSEL	= 4'b011x;				// tmpLO
-										REG_RSEL	= 4'b010x;				// HL
-										M1 		= 0;
-									end
-									2'b01: begin	// stage2, shift data
-										DINW_SEL = 0;						// ALU8OUT
-										WE 		= 6'b100x11;			// flags, hi, lo
-										ALU8OP	= FETCH[3] ? 5'b01100 : 5'b01011;	// RRD/RLD
-										next_stage = 1;
-										REG_WSEL	= 4'b0110;				// A
-										REG_RSEL	= 4'b0111;				// tmpLO
-										M1 		= 0;
-										MREQ		= 0;
-									end
-									2'b10: begin // stage3 - write
-										DO_SEL	= 2'b00;					// ALU80
-										ALU160_SEL = 0;					// regs
-										WE 		= 6'b000x0x;			// nothing
-										next_stage = 1;
-										REG_WSEL	= 4'b0111;				// tmpLO
-										REG_RSEL	= 4'b010x;				// HL
-										M1 		= 0;
-										WR			= 1;
-									end
-									2'b11: begin
-										ALU160_SEL = 1;					// PC
-										WE 		= 6'b010x00;			// PC
-									end
-								endcase
-							2'b11: begin	// NOP
-								ALU160_SEL = 1;					// PC
-								WE 		= 6'b010x00;			// PC
-							end
-						endcase
-				endcase
-//				-----------------------		block instructions  --------------------
-			4'b0110:
-				if({FETCH[5], FETCH[2]} == 4'b10)
-					case(FETCH[1:0])
-						2'b00:	// LDI, LDD, LDIR, LDDR
-							case(STAGE[1:0])
-								2'b00:	begin			// stage1, read data, inc/dec HL
-									ALU160_SEL = 0;					// regs
-									DINW_SEL = 0;						// ALU8OUT
-									WE 		= 6'b100111;			// flags, tmpHI, hi, lo
-									ALU8OP	= {4'b0111, FETCH[3]};	// INC/DEC16
-									next_stage = 1;
-									REG_WSEL	= 4'b0100;				// H
-									REG_RSEL	= 4'b0101;				// L
-									M1 		= 0;
-								end
-								2'b01:	begin			// stage2, dec BC
-									DINW_SEL = 0;						// ALU8OUT
-									WE 		= 6'b100011;			// flags, hi, lo (affects PF only)
-									ALU8OP	= 5'b01111;				// DEC
-									next_stage = 1;
-									REG_WSEL	= 4'b0000;				// B
-									REG_RSEL	= 4'b0001;				// C
-									M1 		= 0;
-									MREQ		= 0;
-								end
-								2'b10:	begin			// stage2, write data, inc/dec DE
-									DO_SEL	= 2'b01;					// th
-									ALU160_SEL = 0;					// regs
-									DINW_SEL = 0;						// ALU8OUT
-									WE 		= 6'b000x11;			// hi, lo
-									ALU8OP	= {4'b0111, FETCH[3]};	// INC / DEC
-									next_stage = FETCH[4] ? !FLAGS[2] : 1'b1;
-									REG_WSEL	= 4'b0010;				// D
-									REG_RSEL	= 4'b0011;				// E
-									M1 		= 0;
-									WR			= 1;
-								end
-								2'b11: begin
-									ALU160_SEL = 1;					// PC
-									WE 		= 6'b010x00;			// PC
-								end
-							endcase
-						2'b01:	// CPI, CPD, CPIR, CPDR
-							case(STAGE[1:0])
-								2'b00: begin			// stage1, load data
-									ALU160_SEL = 0;					// regs
-									DINW_SEL = 1;						// DI
-									WE 		= 6'b000x01;			// lo
-									next_stage = 1;
-									REG_WSEL	= 4'b011x;				// tmpLO
-									REG_RSEL	= 4'b010x;				// HL
-									M1 		= 0;
-								end
-								2'b01: begin			// stage2, CP
-									WE 		= 6'b100x0x;			// flags
-									ALU8OP	= 7;						// CP
-									next_stage = 1;
-									REG_WSEL	= 4'b0110;				// A
-									REG_RSEL	= 4'b0111;				// tmpLO
-									M1 		= 0;
-									MREQ		= 0;
-								end
-								2'b10: begin			// stage3, dec BC
-									DINW_SEL = 0;						// ALU8OUT
-									WE 		= 6'b100x11;			// flags, hi, lo
-									ALU8OP	= 5'b01111;				// DEC16
-									next_stage = 1;
-									REG_WSEL	= 4'b0000;				// B
-									REG_RSEL	= 4'b0001;				// C
-									M1 		= 0;
-									MREQ		= 0;
-								end
-								2'b11: begin			// stage4, inc/dec HL
-									ALU160_SEL = 1;					// pc
-									DINW_SEL = 0;						// ALU8OUT
-									M1 		= FETCH[4] ? (!FLAGS[2] || FLAGS[6]) : 1'b1;
-									WE 		= {1'b0, M1, 4'b0x11};	// PC, hi, lo
-									ALU8OP	= {4'b0111, FETCH[3]};	// INC / DEC
-									REG_WSEL	= 4'b0100;				// H
-									REG_RSEL	= 4'b0101;				// L
-									MREQ		= M1;
-								end
-							endcase
-						2'b10:	// INI, IND, INIR, INDR
-							case(STAGE[1:0])
-								2'b00: 	begin			// stage1, in data, dec B
-									ALU160_SEL = 0;					// regs
-									DINW_SEL = 0;						// ALU8OUT
-									WE 		= 6'b100110;			// flags, tmpHI, hi
-									ALU8OP	= 10;						// DEC
-									next_stage = 1;
-									REG_WSEL	= 4'b0000;				// B
-									REG_RSEL	= 4'b000x;				// BC
-									M1 		= 0;
-									MREQ		= 0;
-									IORQ		= 1;
-								end
-								2'b01:	begin			// stage2, write data, inc/dec HL
-									DO_SEL	= 2'b01;					// th
-									ALU160_SEL = 0;					// regs
-									DINW_SEL = 0;						// ALU8OUT
-									WE 		= 6'b000x11;			// hi, lo
-									ALU8OP	= {4'b0111, FETCH[3]};	// INC / DEC
-									next_stage = FETCH[4] ? FLAGS[6] : 1'b1;
-									REG_WSEL	= 4'b0100;				// H
-									REG_RSEL	= 4'b0101;				// L
-									M1 		= 0;
-									WR			= 1;
-								end
-								2'b10:	begin			// stage3
-									ALU160_SEL = 1;					// pc
-									WE 		= 6'b010x00;			// PC
-								end
-							endcase
-						2'b11:	// OUTI/OUTD/OTIR/OTDR
-							case(STAGE[1:0])
-								2'b00:	begin			// stage1, load data, inc/dec HL
-									ALU160_SEL = 0;					// regs
-									DINW_SEL = 0;						// ALU8OUT
-									WE 		= 6'b000111;			// tmpHI, hi, lo
-									ALU8OP	= {4'b0111, FETCH[3]};	// INC / DEC
-									next_stage = 1;
-									REG_WSEL	= 4'b0100;				// H
-									REG_RSEL	= 4'b0101;				// L
-									M1 		= 0;
-								end
-								2'b01: 	begin			// stage2, out data, dec B
-									DO_SEL	= 2'b01;					// th
-									ALU160_SEL = 0;					// regs
-									DINW_SEL = 0;						// ALU8OUT
-									WE 		= 6'b100x10;			// flags, hi
-									ALU8OP	= 10;						// DEC
-									next_stage = FETCH[4] ? (ALU80 == 8'b00000001) : 1'b1;
-									REG_WSEL	= 4'b0000;				// B
-									REG_RSEL	= 4'b000x;				// BC
-									M1 		= 0;
-									MREQ		= 0;
-									IORQ		= 1;
-									WR			= 1;
-								end
-								2'b10:	begin			// stage3
-									ALU160_SEL = 1;					// pc
-									WE 		= 6'b010x00;			// PC
-								end
-							endcase
-					endcase
-				else begin			// NOP
-					ALU160_SEL = 1;					// PC
-					WE 		= 6'b010x00;			// PC
-				end
-//------------------------------------------- CB + opcode ----------------------------------------------------
-			4'b1000, 4'b1001, 4'b1010, 4'b1011:										// CB class (rot/shift, bit/res/set)
-				case({STAGE[1:0], CPUStatus[4], op0mem})				
-					4'b00_0_0: begin						// execute reg-reg
-						DINW_SEL = 0;						// ALU8OUT
-						ALU160_SEL = 1;					// pc
-						WE 		= {!FETCH[7], 3'b10x, FETCH[7:6] == 2'b01 ? 2'b00 : {!opd[0], opd[0]}};	// flags, hi/lo
-						ALU8OP	= 28;					// BIT
-						REG_WSEL	= {1'b0, opd[2:0]};
-					end
-					4'b00_0_1, 4'b00_1_0, 4'b00_1_1: begin				// stage1, (HL-X) - read data
-						ALU160_SEL = 0;				// regs
-						DINW_SEL = 1;					// DI
-						WE 		= opd[0] ? 6'b000001 : 6'b000010;	// lo/hi
-						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;					// ADD - NOP
-						next_stage = 1;
-						REG_WSEL = FETCH[7:6] == 2'b01 ? 4'b111x : {1'b0, opd[2:0]};	// dest, tmp16 for BIT
-						REG_RSEL	= 4'b010x;			// HL
-						M1 		= 0;
-					end
-					4'b01_0_1, 4'b01_1_0, 4'b01_1_1:		// stage2 (HL-X) - execute, write
-						case(FETCH[7:6])
-							2'b00, 2'b10, 2'b11: begin		// exec + write
-								DINW_SEL = 0;					// ALU8OUT
-								DO_SEL	= 2'b11;				// ALU8OUT[7:0]
-								ALU160_SEL = 0;				// regs
-								WE 		= {!FETCH[7], 3'b00x, !opd[0], opd[0]};	// flags, hi/lo
-								ALU8OP	= 28;
-								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
-								next_stage = 1;
-								REG_WSEL	= {1'b0, opd[2:0]};
-								REG_RSEL	= 4'b010x;				// HL
-								M1 		= 0;
-								WR			= 1;
-							end
-							2'b01: begin							// BIT, no write
-								ALU160_SEL = 1;					// pc
-								WE 		= 6'b110xxx;			// flags, PC
-								ALU8OP	= 28;						// BIT
-								REG_WSEL	= {3'b111, opd[0]};	// tmp
-							end 
-						endcase
-					4'b10_0_1, 4'b10_1_0, 4'b10_1_1: begin	// (HL-X) - load next op
-						ALU160_SEL = 1;							// pc
-						WE 		= 6'b010x00;					// PC
-					end
-				endcase
-//------------------------------------------- // RST, NMI, INT ----------------------------------------------------
-			4'b1110: begin 			// RESET: IR <- 0, IM <- 0, IFF1,IFF2 <- 0, pC <- 0
-					ALU160_SEL = 0;					// regs
-					DINW_SEL = 0;						// ALU8OUT
-					WE 		= 6'bx1xx11;			// PC, hi, lo
-					ALU8OP	= 29;						// pass D1
-					ALU16OP	= 4;						// NOP
-					REG_WSEL	= 4'b1001;				// IR, write r
-					REG_RSEL	= 4'b110x;				// const
-					M1 		= 0;
-					MREQ		= 0;
-					status[11:6] = 6'b110000;		// IM0, DI
-				end 
-			4'b1101:						// NMI
-				case(STAGE[1:0])
-					2'b00: begin		
-						ALU160_SEL = 1;				// pc
-						WE 		= 6'b010x00;		// PC
-						ALU16OP	= intop;				// DEC/DEC2 (if block instruction interrupted)
-						next_stage = 1;
-						M1 		= 0;
-						MREQ		= 0;
-					end
-					2'b01, 2'b10: begin
-						DO_SEL	= {1'b0, !STAGE[0]};	// pc hi/lo
-						ALU160_SEL = 0;					// regs
-						WE 		= 6'b001x00;			// SP
-						ALU16OP	= 5;						// DEC
-						next_stage = 1;
-						REG_WSEL	= 4'b1xxx;				// pc
-						REG_RSEL	= 4'b101x;				// sp
-						M1 		= 0;
-						WR			= 1;
-						status[11]	= 1'b1;
-						status[7:6] = {CPUStatus[7], 1'b0};	// reset IFF1
-					end
-					2'b11: begin
-						ALU160_SEL = 0;					// regs
-						WE 		= 6'b010x00;			// PC
-						REG_RSEL	= 4'b110x;				// const
-					end
-				endcase
-			4'b1100:				// INT
-				case(CPUStatus[9:8])
-					2'b00, 2'b01, 2'b10: begin		// IM0, IM1	
-						ALU160_SEL = 1;					// pc
-						WE 		= 6'b010x00;			// PC
-						ALU16OP	= intop;					// DEC/DEC2 (if block instruction interrupted)
-						MREQ		= 0;
-						IORQ		= 1;
-						status[11]	= 1'b1;
-						status[7:6] = 2'b0;				// reset IFF1, IFF2
-					end
-					2'b11: 								// IM2
-						case(STAGE[2:0])
-							3'b000: begin
-								ALU160_SEL = 1;				// pc
-								DINW_SEL = 1;					// DI
-								WE 		= 6'b010x01;		// PC, lo
-								ALU16OP	= intop;				// DEC/DEC2 (if block instruction interrupted)
-								next_stage = 1;
-								REG_WSEL	= 4'b1000;			// Itmp, no write r
-								MREQ		= 0;
-								IORQ		= 1;
-								status[11]	= 1'b1;
-								status[7:6] = 2'b0;			// reset IFF1, IFF2
-							end
-							3'b001, 3'b010: begin			// push pc
-								DO_SEL	= {1'b0, !STAGE[0]};	// pc hi/lo
-								ALU160_SEL = 0;					// regs
-								WE 		= 6'b001x00;			// SP
-								ALU16OP	= 5;						// DEC
-								next_stage = 1;
-								REG_WSEL	= 4'b1xxx;				// pc
-								REG_RSEL	= 4'b101x;				// sp
-								M1 		= 0;
-								WR			= 1;
-							end
-							3'b011, 3'b100:	begin			// read address
-								ALU160_SEL = 0;					// regs
-								DINW_SEL = 1;						// DI
-								WE 		= {4'b0x0x, STAGE[0] ? 1'bx : 1'b1, STAGE[0]};				// hi/lo
-								ALU16OP	= {2'b00, !STAGE[0]};// NOP/INC
-								next_stage = 1;
-								REG_WSEL	= 4'b111x;				// tmp16
-								REG_RSEL	= 4'b1000;				// I-Itmp
-								M1 		= 0;
-							end
-							3'b101: begin						// jump
-								ALU160_SEL = 0;					// regs
-								WE 		= 6'b010x00;			// PC
-								REG_RSEL	= 4'b111x;				// tmp16
-							end
-						endcase
-				endcase
-		endcase	
-	end
-
-endmodule
diff --git a/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80Reg.v b/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80Reg.v
deleted file mode 100644
index 65d99661..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80Reg.v
+++ /dev/null
@@ -1,199 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////////
-//
-// This file is part of the NextZ80 project
-// http://www.opencores.org/cores/nextz80/
-//
-// Filename: NextZ80Regs.v
-// Description: Implementation of Z80 compatible CPU - registers
-// Version 1.0
-// Creation date: 28Jan2011 - 18Mar2011
-//
-// Author: Nicolae Dumitrache 
-// e-mail: ndumitrache@opencores.org
-//
-/////////////////////////////////////////////////////////////////////////////////
-// 
-// Copyright (C) 2011 Nicolae Dumitrache
-// 
-// This source file may be used and distributed without 
-// restriction provided that this copyright statement is not 
-// removed from the file and that any derivative work contains 
-// the original copyright notice and the associated disclaimer.
-// 
-// This source file is free software; you can redistribute it 
-// and/or modify it under the terms of the GNU Lesser General 
-// Public License as published by the Free Software Foundation;
-// either version 2.1 of the License, or (at your option) any 
-// later version. 
-// 
-// This source is distributed in the hope that it will be 
-// useful, but WITHOUT ANY WARRANTY; without even the implied 
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
-// PURPOSE. See the GNU Lesser General Public License for more 
-// details. 
-// 
-// You should have received a copy of the GNU Lesser General 
-// Public License along with this source; if not, download it 
-// from http://www.opencores.org/lgpl.shtml 
-// 
-///////////////////////////////////////////////////////////////////////////////////
-`timescale 1ns / 1ps
-
-module Z80Reg(
-	input wire [7:0]rstatus,	// 0=af-af', 1=exx, 2=hl-de, 3=hl'-de',4=hl-ixy, 5=ix-iy, 6=IFF1, 7=IFF2
-	input wire M1,
-	input wire [5:0]WE,			// 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo
-	input wire CLK,
-	input wire [15:0]ALU8OUT,	// CPU data out bus (output of alu8)
-	input wire [7:0]DI,			// CPU data in bus
-	output reg [7:0]DO,			// CPU data out bus
-	input wire [15:0]ADDR,		// CPU addr bus
-	input wire [7:0]CONST,
-	output reg [7:0]ALU80,
-	output reg [7:0]ALU81,
-	output reg [15:0]ALU160,
-	output wire[7:0]ALU161,
-	input wire [7:0]ALU8FLAGS,			
-	output wire [7:0]FLAGS,
-	
-	input wire [1:0]DO_SEL,		// select DO betwen ALU8OUT lo and th register
-	input wire ALU160_sel,		// 0=REG_RSEL, 1=PC
-	input wire [3:0]REG_WSEL,	// rdow:    	[3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-x  ----- [0] = 0HI,1LO
-	input wire [3:0]REG_RSEL,	// mux_rdor:   [3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-R, 5=SP, 7=tmpSP   ----- [0] = 0HI, 1LO
-	input wire DINW_SEL,			// select RAM write data between (0)ALU8OUT, and 1(DI)
-	input wire XMASK,				// 0 if REG_WSEL should not use IX, IY, even if rstatus[4] == 1
-	input wire [2:0]ALU16OP,	// ALU16OP
-	input wire WAIT				// wait
-	);
-	
-// latch registers
-	reg [15:0]pc=0;				// program counter
-	reg [15:0]sp;					// stack pointer
-	reg [7:0]r;						// refresh
-	reg [15:0]flg = 0;
-	reg [7:0]th;					// temp high
-
-// internal wires	
-	wire [15:0]rdor;		// R out from RAM
-	wire [15:0]rdow;		// W out from RAM
-	wire [3:0]SELW;		// RAM W port sel
-	wire [3:0]SELR;		// RAM R port sel
-	reg  [15:0]DIN;		// RAM W in data
-	reg [15:0]mux_rdor;	// (3)A reversed mixed with TL, (4)I mixed with R (5)SP
-	
-//------------------------------------ RAM block registers ----------------------------------
-// 0:BC, 1:DE, 2:HL, 3:A-x, 4:I-x, 5:IX, 6:IY, 7:x-x, 8:BC', 9:DE', 10:HL', 11:A'-x, 12: tmpSP, 13:zero
-   RAM16X8D_regs regs_lo (
-      .DPO(rdor[7:0]),   // Read-only data output
-      .SPO(rdow[7:0]),   // R/W data output
-      .A(SELW),       	 // R/W address
-      .D(DIN[7:0]),      // Write data input
-      .DPRA(SELR), 		 // Read-only address
-      .WCLK(CLK),   		 // Write clock input
-      .WE(WE[0] & !WAIT) // Write enable input
-   );
-
-   RAM16X8D_regs regs_hi (
-      .DPO(rdor[15:8]),  // Read-only data output
-      .SPO(rdow[15:8]),  // R/W data output
-      .A(SELW),       	 // R/W address
-      .D(DIN[15:8]),     // Write data input
-      .DPRA(SELR), 		 // Read-only address
-      .WCLK(CLK),   		 // Write clock input
-      .WE(WE[1] & !WAIT) // Write enable input
-   );
-
-	wire [15:0]ADDR1 = ADDR + !ALU16OP[2]; // address post increment
-	wire [7:0]flgmux = {ALU8FLAGS[7:3], SELR[3:0] == 4'b0100 ? rstatus[7] : ALU8FLAGS[2], ALU8FLAGS[1:0]}; // LD A, I/R IFF2 flag on parity
-	always @(posedge CLK)
-		if(!WAIT) begin
-			if(WE[2]) th <= DI;
-			if(WE[3]) sp <= ADDR1;
-			if(WE[4]) pc <= ADDR1;
-			if({REG_WSEL, WE[0]} == 5'b10011) r <= ALU8OUT[7:0]; 
-			else if(M1) r[6:0] <= r[6:0] + 1;
-			if(WE[5])
-				if(rstatus[0]) flg[15:8] <= flgmux;
-				else flg[7:0] <= flgmux;
-		end
-	
-	assign ALU161 = th;
-	assign FLAGS = rstatus[0] ? flg[15:8] : flg[7:0];
-	
-	always @* begin
-		DIN = DINW_SEL ? {DI, DI} : ALU8OUT;
-		ALU80 = REG_WSEL[0] ? rdow[7:0] : rdow[15:8];
-		ALU81 = REG_RSEL[0] ? mux_rdor[7:0] : mux_rdor[15:8];
-		ALU160 = ALU160_sel ? pc : mux_rdor;
-	
-		case({REG_WSEL[3], DO_SEL})
-			0:	DO = ALU80;
-			1:	DO = th;
-			2: DO = FLAGS;
-			3: DO = ALU8OUT[7:0];
-			4: DO = pc[15:8];
-			5: DO = pc[7:0];
-			6:	DO = sp[15:8];
-			7: DO = sp[7:0];
-		endcase
-		case({ALU16OP == 4, REG_RSEL[3:0]})
-			5'b01001, 5'b11001:								mux_rdor = {rdor[15:8], r};
-			5'b01010, 5'b01011: 								mux_rdor = sp;
-			5'b01100, 5'b01101, 5'b11100, 5'b11101:	mux_rdor = {8'b0, CONST};
-			default:		mux_rdor = rdor;
-		endcase 
-	end
-	
-	RegSelect WSelectW(.SEL(REG_WSEL[3:1]), .RAMSEL(SELW), .rstatus({rstatus[5], rstatus[4] & XMASK, rstatus[3:0]}));
-	RegSelect WSelectR(.SEL(REG_RSEL[3:1]), .RAMSEL(SELR), .rstatus(rstatus[5:0]));
-
-endmodule
-
-
-module RegSelect(
-	input [2:0]SEL,
-	output reg [3:0]RAMSEL,
-	input [5:0]rstatus			// 0=af-af', 1=exx, 2=hl-de, 3=hl'-de',4=hl-ixy, 5=ix-iy
-	);
-	
-	always @* begin
-		RAMSEL = 4'bxxxx;
-		case(SEL)
-			0: RAMSEL = {rstatus[1], 3'b000};	// BC
-			1:  //DE
-				if(rstatus[{1'b1, rstatus[1]}]) RAMSEL = {rstatus[1], 3'b010};		//	HL
-				else RAMSEL = {rstatus[1], 3'b001};				// DE
-			2:	// HL
-				case({rstatus[5:4], rstatus[{1'b1, rstatus[1]}]})
-					0,4: 	RAMSEL = {rstatus[1], 3'b010}; 		// HL
-					1,5: 	RAMSEL = {rstatus[1], 3'b001};		// DE
-					2,3:	RAMSEL = 4'b0101;  	//	IX
-					6,7:	RAMSEL = 4'b0110;		// IY
-				endcase
-			3: RAMSEL = {rstatus[0], 3'b011}; // A-TL
-			4:	RAMSEL = 4; // I-R
-			5: RAMSEL = 12;	// tmp SP
-			6: RAMSEL = 13;	// zero
-			7: RAMSEL = 7;	// temp reg for BIT/SET/RES
-		endcase
-	end
-endmodule	
-
-module RAM16X8D_regs(
-      output [7:0]DPO,     // Read-only data output
-      output [7:0]SPO,     // R/W data output
-      input [3:0]A,       	// R/W address 
-      input [7:0]D,        // Write data input
-      input [3:0]DPRA, 		// Read-only address
-      input WCLK,   			// Write clock
-      input WE        		// Write enable
-   );
-	
-	reg [7:0]data[15:0];
-	assign DPO = data[DPRA];
-	assign SPO = data[A];
-	
-	always @(posedge WCLK)
-		if(WE) data[A] <= D;		
-
-endmodule
diff --git a/Computer_MiST/Laser310_MiST/rtl/PIXEL_DISPLAY.v b/Computer_MiST/Laser310_MiST/rtl/PIXEL_DISPLAY.v
deleted file mode 100644
index 585fea04..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/PIXEL_DISPLAY.v
+++ /dev/null
@@ -1,296 +0,0 @@
-module PIXEL_DISPLAY (
-	pixel_clock,
-	reset,
-
-	show_border,
-
-	// mode
-	ag,
-	gm,
-	css,
-
-	// text
-	char_column,
-	char_line,
-	subchar_line,
-	subchar_pixel,
-
-	// graph
-	graph_pixel,
-	graph_line_2x,
-	graph_line_3x,
-
-	// vram
-	vram_rd_enable,
-	vram_addr,
-	vram_data,
-
-	// vga
-	vga_red,
-	vga_green,
-	vga_blue
-);
-
-input					pixel_clock;
-input					reset;
-
-input					show_border;
-
-// mode
-input					ag;
-input			[2:0]	gm;
-input					css;
-
-// text
-input			[6:0]	char_column;		// character number on the current line
-input			[6:0]	char_line;			// line number on the screen
-input			[4:0]	subchar_line;		// the line number within a character block 0-8
-input			[3:0]	subchar_pixel;		// the pixel number within a character block 0-8
-
-// graph
-input			[8:0]	graph_pixel;		// pixel number on the current line
-input			[9:0]	graph_line_2x;		// line number on the screen
-input			[9:0]	graph_line_3x;		// line number on the screen
-
-output					vram_rd_enable;
-output	reg		[12:0]	vram_addr;
-input			[7:0] 	vram_data;
-
-output			[7:0]	vga_red;
-output			[7:0]	vga_green;
-output			[7:0]	vga_blue;
-
-
-//// Label Definitions ////
-
-// Note: all labels must match their defined length--shorter labels will be padded with solid blocks,
-// and longer labels will be truncated
-
-// 48 character label for the example text
-
-wire				pixel_on;					// high => output foreground color, low => output background color
-
-
-// 8p   代表每个点占用VGA水平 8 pixel
-// 2bit 代表每个点取2位值
-
-wire	[1:0]		pixel_8p_2bit;				// high => output foreground color, low => output background color
-wire	[1:0]		pixel_4p_2bit;				// high => output foreground color, low => output background color
-wire				pixel_4p_1bit;				// high => output foreground color, low => output background color
-wire				pixel_2p_1bit;				// high => output foreground color, low => output background color
-
-reg		[7:0] 		latched_vram_data;			// the data that will be written to character memory at the clock rise
-
-// 锁存数据用于选择调色板
-reg		[7:0] 		latched_palette_data;
-
-assign vram_rd_enable = pixel_clock;
-
-reg		[23:0] latched_vga_rgb;
-wire	[23:0] vga_rgb;
-
-// write the appropriate character data to memory
-
-always @ (posedge pixel_clock) begin
-	if(ag==1'b0)
-	begin
-			if(subchar_pixel==4'b0001)
-				vram_addr <= {4'b0,char_line[3:0], char_column[4:0]};
-			// 对于同步sram需要等待 1 个时钟周期
-			if(subchar_pixel==4'b0011)
-				latched_vram_data <= vram_data;
-			if(graph_pixel[3:0]==4'b0110)
-				latched_palette_data <= latched_vram_data;
-	end
-	else
-	begin
-		case(gm)
-		3'b000:
-		begin
-			// 64 x 64 x 4	gm: 000
-			if(graph_pixel[4:0]==5'b00001)
-				vram_addr <= {3'b0, graph_line_3x[9:4], graph_pixel[8:5]};
-			// 对于同步sram需要等待 1 个时钟周期
-			if(graph_pixel[4:0]==5'b00011)
-				latched_vram_data <= vram_data;
-		end
-		3'b001:
-		begin
-			// 128 x 64 x 2	gm: 001
-			if(graph_pixel[4:0]==5'b00001)
-				vram_addr <= {3'b0, graph_line_3x[9:4], graph_pixel[8:5]};
-			// 对于同步sram需要等待 1 个时钟周期
-			if(graph_pixel[4:0]==5'b00011)
-				latched_vram_data <= vram_data;
-		end
-		3'b011:
-		begin
-			// 128 x 96 x 2	gm: 011
-			if(graph_pixel[4:0]==5'b00001)
-				vram_addr <= {2'b0, graph_line_2x[9:3], graph_pixel[8:5]};
-			// 对于同步sram需要等待 1 个时钟周期
-			if(graph_pixel[4:0]==5'b00011)
-				latched_vram_data <= vram_data;
-		end
-		3'b100:
-		begin
-			// 128 x 96 x 4	gm: 100
-			if(graph_pixel[3:0]==4'b0001)
-				vram_addr <= {1'b0, graph_line_2x[8:1], graph_pixel[8:4]};
-			// 对于同步sram需要等待 1 个时钟周期
-			if(graph_pixel[3:0]==4'b0011)
-				latched_vram_data <= vram_data;
-		end
-		3'b101:
-		begin
-			// 128 x 192 x 2	gm: 101
-			if(graph_pixel[4:0]==5'b00001)
-				vram_addr <= {1'b0, graph_line_2x[9:1], graph_pixel[8:5]};
-			// 对于同步sram需要等待 1 个时钟周期
-			if(graph_pixel[4:0]==5'b00011)
-				latched_vram_data <= vram_data;
-		end
-		3'b110:
-		begin
-			// 128 x 192 x 4	gm: 110
-			if(graph_pixel[3:0]==4'b0001)
-				vram_addr <= {graph_line_2x[9:1], graph_pixel[8:4]};
-			// 对于同步sram需要等待 1 个时钟周期
-			if(graph_pixel[3:0]==4'b0011)
-				latched_vram_data <= vram_data;
-		end
-		3'b111:
-		begin
-			// 256 x 192 x 2	gm: 111
-			if(graph_pixel[3:0]==4'b0001)
-				vram_addr <= {graph_line_2x[9:1], graph_pixel[8:4]};
-			// 对于同步sram需要等待 1 个时钟周期
-			if(graph_pixel[3:0]==4'b0011)
-				latched_vram_data <= vram_data;
-		end
-		default:
-		begin
-			// 128 x 64 x 4 	gm: 010
-			if(graph_pixel[3:0]==4'b0001)
-				vram_addr <= {2'b0,graph_line_3x[9:3], graph_pixel[8:4]};
-				//vram_addr <= {2'b0,graph_line_3x[8:3], graph_pixel[6:2]};
-			// 对于同步sram需要等待 1 个时钟周期
-			if(graph_pixel[3:0]==4'b0011)
-				latched_vram_data <= vram_data;
-		end
-		endcase
-	end
-	latched_vga_rgb <= vga_rgb;
-end
-
-// palette
-/*
-位\色  绿   黄   蓝   红   浅黄  浅蓝  紫   橙
-D6     0    0    0    0    1     1     1    1
-D5     0    0    1    1    0     0     1    1
-D4     0    1    0    1    0     1     0    1
-
-0x07 0xff 0x00 // GREEN
-0xff 0xff 0x00 // YELLOW
-0x3b 0x08 0xff // BLUE
-0xcc 0x00 0x3b // RED
-0xff 0xff 0xff // BUFF
-0x07 0xe3 0x99 // CYAN
-0xff 0x1c 0xff // MAGENTA
-0xff 0x81 0x00 // ORANGE
-
-0x00 0x00 0x00 // BLACK
-0x07 0xff 0x00 // GREEN
-0x3b 0x08 0xff // BLUE
-0xff 0xff 0xff // BUFF
-
-*/
-
-wire [2:0]	palette_bit_graph;
-
-wire [23:0]	palette_rgb_border =	(~ag)?24'h000000:				// 字符模式背景
-									(css)?24'hffffff:24'h07ff00;	// 图形模式背景
-
-wire [23:0] palette_rgb_pixel = 24'h000000;
-wire [23:0] palette_rgb_background = 24'h07ff00;
-
-// 64 x 64 x 4		gm: 000
-// 128 x 64 x 2		gm: 001
-// 128 x 64 x 4 	gm: 010
-// 128 x 96 x 2		gm: 011
-// 128 x 96 x 4		gm: 100
-// 128 x 192 x 2	gm: 101
-// 128 x 192 x 4	gm: 110
-// 256 x 192 x 2	gm: 111
-
-//assign palette_bit_graph = (ag)? {css, pixel_4p_2bit} : latched_palette_data[6:4];
-
-assign palette_bit_graph		=	(~ag)			?	latched_palette_data[6:4]				:
-									(gm==3'b000)	?	{css, pixel_8p_2bit					}	:
-									(gm==3'b001)	?	{css, pixel_4p_1bit, pixel_4p_1bit	}	:
-									(gm==3'b010)	?	{css, pixel_4p_2bit					}	:
-									(gm==3'b011)	?	{css, pixel_4p_1bit, pixel_4p_1bit	}	:
-									(gm==3'b100)	?	{css, pixel_4p_2bit					}	:
-									(gm==3'b101)	?	{css, pixel_4p_1bit, pixel_4p_1bit	}	:
-									(gm==3'b110)	?	{css, pixel_4p_2bit					}	:
-														{css, pixel_2p_1bit, pixel_2p_1bit	}	;
-
-wire [23:0] palette_rgb_graph =	(palette_bit_graph==3'b000) ?	24'h07ff00 : // GREEN
-								(palette_bit_graph==3'b001) ?	24'hffff00 : // YELLOW
-								(palette_bit_graph==3'b010) ?	24'h3b08ff : // BLUE
-								(palette_bit_graph==3'b011) ?	24'hcc003b : // RED
-								(palette_bit_graph==3'b100) ?	24'hffffff : // BUFF
-								(palette_bit_graph==3'b101) ?	24'h07e399 : // CYAN
-								(palette_bit_graph==3'b110) ?	24'hff1cff : // MAGENTA
-																24'hff8100 ; // ORANGE
-
-/*
-	24'h000000 // BLACK
-	24'h07ff00 // GREEN
-	24'h3b08ff // BLUE
-	24'hffffff // BUFF
-*/
-
-
-// use the result of the character generator module to choose between the foreground and background color
-
-assign vga_rgb =	(show_border)	? palette_rgb_border :
-					(ag)			? palette_rgb_graph :
-					(~pixel_on)		? palette_rgb_pixel :
-					(latched_palette_data[7])	? palette_rgb_graph : palette_rgb_background;
-
-assign vga_red = latched_vga_rgb[23:16];
-assign vga_green = latched_vga_rgb[15:8];
-assign vga_blue = latched_vga_rgb[7:0];
-
-
-// the character generator block includes the character RAM
-// and the character generator ROM
-CHAR_GEN CHAR_GEN
-(
-	.reset(reset),					// reset signal
-
-	.char_code(latched_vram_data),
-	.subchar_line(subchar_line),	// current line of pixels within current character
-	.subchar_pixel(subchar_pixel),	// current column of pixels withing current character
-
-	.pixel_clock(pixel_clock),		// read clock
-	.pixel_on(pixel_on)				// read data
-);
-
-PIXEL_GEN PIXEL_GEN
-(
-	.reset(reset),					// reset signal
-
-	.pixel_code(latched_vram_data),
-	.graph_pixel(graph_pixel),		// current column of pixels withing current character
-
-	.pixel_clock(pixel_clock),		// read clock
-
-	.pixel_8p_2bit(pixel_8p_2bit),	//	64x64x4
-	.pixel_4p_2bit(pixel_4p_2bit),	//	128x64x4 128x96x4 128x192x4
-	.pixel_4p_1bit(pixel_4p_1bit),	//	128x64x2 128x96x2 128x192x2
-	.pixel_2p_1bit(pixel_2p_1bit)	//	256x192x2
-);
-
-endmodule //CHAR_DISPLAY
diff --git a/Computer_MiST/Laser310_MiST/rtl/PIXEL_GEN.v b/Computer_MiST/Laser310_MiST/rtl/PIXEL_GEN.v
deleted file mode 100644
index cc2f61f3..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/PIXEL_GEN.v
+++ /dev/null
@@ -1,129 +0,0 @@
-module PIXEL_GEN(
-	// control
-	reset,
-
-	pixel_code,
-	graph_pixel,
-
-	pixel_clock,
-
-	pixel_8p_2bit,	//	64x64x4
-	pixel_4p_2bit,	//	128x64x4 128x96x4 128x192x4
-	pixel_4p_1bit,	//	128x64x2 128x96x2 128x192x2
-	pixel_2p_1bit	//	256x192x2
-);
-
-
-input				reset;
-
-input	[7:0]		pixel_code;
-input	[8:0]		graph_pixel;		// pixel number on the current line
-
-input				pixel_clock;
-
-output	reg	[1:0]	pixel_8p_2bit;
-output	reg	[1:0]	pixel_4p_2bit;
-output	reg			pixel_4p_1bit;
-output	reg			pixel_2p_1bit;
-
-reg		[7:0]		latched_8p_2bit_data;
-reg		[7:0]		latched_4p_2bit_data;
-reg		[7:0]		latched_4p_1bit_data;
-reg		[7:0]		latched_2p_1bit_data;
-
-
-// 移位寄存器有四种模式
-// 每2个点 移 1 位
-// 每4个点 移 2 位
-// 每4个点 移 1 位
-// 每8个点 移 2 位
-
-
-// serialize the GRAPH MODE data
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
- 		begin
-			pixel_8p_2bit			<=	2'b00;
-			latched_8p_2bit_data	<=	8'h00;
-		end
-	else begin
-		case(graph_pixel[4:0])
-			5'b00101:
-				latched_8p_2bit_data[7:0]	<=	pixel_code;
-			default:
-				if(graph_pixel[3:0]==3'b110)
-					{pixel_8p_2bit,latched_8p_2bit_data[7:2]}	<=	latched_8p_2bit_data[7:0];
-		endcase
-		end
-
-	end
-
-
-// 延时：图形模式 128x64 4色
-// 1、(001)锁存 vram 地址，2、(010)读取 vram  3、(011)锁存 vram 数据 4、(100)空 5、(101)数据锁存至移位寄存器
-// 6、(110)移位得到点阵 7、(111)建立调色板，锁存色彩
-
-// serialize the GRAPH MODE data
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
- 		begin
-			pixel_4p_2bit			<=	2'b00;
-			latched_4p_2bit_data	<=	8'h00;
-		end
-	else begin
-		case(graph_pixel[3:0])
-			4'b0101:
-				latched_4p_2bit_data[7:0]	<=	pixel_code;
-			default:
-				if(graph_pixel[1:0]==2'b10)
-					{pixel_4p_2bit,latched_4p_2bit_data[7:2]}	<=	latched_4p_2bit_data[7:0];
-		endcase
-		end
-
-	end
-
-
-// serialize the GRAPH MODE data
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
- 		begin
-			pixel_4p_1bit			<=	2'b00;
-			latched_4p_1bit_data	<=	8'h00;
-		end
-	else begin
-		case(graph_pixel[4:0])
-			5'b00101:
-				latched_4p_1bit_data[7:0]	<=	pixel_code;
-			default:
-				if(graph_pixel[1:0]==2'b10)
-					{pixel_4p_1bit,latched_4p_1bit_data[7:1]}	<=	latched_4p_1bit_data[7:0];
-		endcase
-		end
-
-	end
-
-
-// 延时：图形模式 256x192 2色
-// 1、(001)锁存 vram 地址，2、(010)读取 vram  3、(011)锁存 vram 数据 4、(100)空 5、(101)数据锁存至移位寄存器
-// 6、(110)移位得到点阵 7、(111)建立调色板，锁存色彩
-
-// serialize the GRAPH MODE data
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
-		begin
-			pixel_2p_1bit			<=	1'b0;
-			latched_2p_1bit_data	<=	8'h00;
-		end
-	else begin
-		case(graph_pixel[3:0])
-			4'b0101:
-				latched_2p_1bit_data[7:0]	<=	pixel_code;
-			default:
-				if(graph_pixel[0]==1'b0)
-					{pixel_2p_1bit,latched_2p_1bit_data[7:1]}	<=	latched_2p_1bit_data[7:0];
-		endcase
-		end
-
-	end
-
-endmodule //PIXEL_GEN
diff --git a/Computer_MiST/Laser310_MiST/rtl/SVGA_DEFINES.v b/Computer_MiST/Laser310_MiST/rtl/SVGA_DEFINES.v
deleted file mode 100644
index 85aa9901..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/SVGA_DEFINES.v
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
----------------------------------------------------------------------------------
-To select a resolution and refresh rate, remove the comments around the desired
-block in this file. The pixel clock output by the DCM module should approximately
-equal the rate specified above the timing block that is uncommented.
----------------------------------------------------------------------------------
-*/
-
-// DEFINE THE VARIOUS PIPELINE DELAYS
-
-`define CHARACTER_DECODE_DELAY  4
-
-
-//  640 X 480 @ 60Hz with a 25.175MHz pixel clock
-`define H_ACTIVE				640	// pixels
-`define H_FRONT_PORCH		16		// pixels
-`define H_SYNCH				96		// pixels
-`define H_BACK_PORCH			48		// pixels
-`define H_TOTAL				800	// pixels
-
-`define V_ACTIVE				480	// lines
-`define V_FRONT_PORCH		11		// lines
-`define V_SYNCH				2		// lines
-`define V_BACK_PORCH			31		// lines
-`define V_TOTAL				524	// lines
-
-`define CLK_MULTIPLY			2		// 50 * 2/4 = 25.000 MHz
-`define CLK_DIVIDE			4
-/*
-//generic composite,720x288p clk=13.5MHz
-`define H_ACTIVE				720		
-`define H_FRONT_PORCH		20
-`define H_SYNCH				64
-`define H_BACK_PORCH			60
-`define H_TOTAL				800		// todo
-
-`define V_ACTIVE				288
-`define V_FRONT_PORCH		1
-`define V_SYNCH				3
-`define V_BACK_PORCH			20
-`define V_TOTAL				524		// todo
-
-`define CLK_MULTIPLY			27		// 50 * 27/100 = 13.500 MHz
-`define CLK_DIVIDE			100
-
-//  640 X 480 @ 72Hz with a 31.500MHz pixel clock
-`define H_ACTIVE			640	// pixels
-`define H_FRONT_PORCH	24		// pixels
-`define H_SYNCH			40		// pixels
-`define H_BACK_PORCH		128	// pixels
-`define H_TOTAL			832	// pixels
-
-`define V_ACTIVE			480	// lines
-`define V_FRONT_PORCH	9		// lines
-`define V_SYNCH			3		// lines
-`define V_BACK_PORCH		28		// lines
-`define V_TOTAL			520	// lines
-
-`define CLK_MULTIPLY		5		// 50 * 5/8 = 31.250 MHz
-`define CLK_DIVIDE		8
-*/
-
-/*
-//  640 X 480 @ 75Hz with a 31.500MHz pixel clock
-`define H_ACTIVE			640	// pixels
-`define H_FRONT_PORCH	16		// pixels
-`define H_SYNCH			96		// pixels
-`define H_BACK_PORCH		48		// pixels
-`define H_TOTAL			800	// pixels
-
-`define V_ACTIVE			480	// lines
-`define V_FRONT_PORCH	11		// lines
-`define V_SYNCH			2		// lines
-`define V_BACK_PORCH		32		// lines
-`define V_TOTAL			525	// lines
-
-`define CLK_MULTIPLY		5		// 50 * 5/8 = 31.250 MHz
-`define CLK_DIVIDE		8
-*/
-
-/*
-// 640 X 480 @ 85Hz with a 36.000MHz pixel clock
-`define H_ACTIVE			640	// pixels
-`define H_FRONT_PORCH	32		// pixels
-`define H_SYNCH			48		// pixels
-`define H_BACK_PORCH		112	// pixels
-`define H_TOTAL			832	// pixels
-
-`define V_ACTIVE			480	// lines
-`define V_FRONT_PORCH	1		// lines
-`define V_SYNCH			3		// lines
-`define V_BACK_PORCH		25		// lines
-`define V_TOTAL			509	// lines
-
-`define CLK_MULTIPLY		18		// 50 * 18/25 = 36.000 MHz
-`define CLK_DIVIDE		25
-*/
-
-/*
-// 800 X 600 @ 56Hz with a 38.100MHz pixel clock
-`define H_ACTIVE			800	// pixels
-`define H_FRONT_PORCH	32		// pixels
-`define H_SYNCH			128	// pixels
-`define H_BACK_PORCH		128	// pixels
-`define H_TOTAL			1088	// pixels
-
-`define V_ACTIVE			600	// lines
-`define V_FRONT_PORCH	1		// lines
-`define V_SYNCH			4		// lines
-`define V_BACK_PORCH		14		// lines
-`define V_TOTAL			619	// lines
-
-`define CLK_MULTIPLY		16		// 50 * 16/21 = 38.095 MHz
-`define CLK_DIVIDE		21
-*/
-
-/*
-// 800 X 600 @ 60Hz with a 40.000MHz pixel clock
-`define H_ACTIVE			800	// pixels
-`define H_FRONT_PORCH	40		// pixels
-`define H_SYNCH			128	// pixels
-`define H_BACK_PORCH		88		// pixels
-`define H_TOTAL			1056	// pixels
-
-`define V_ACTIVE			600	// lines
-`define V_FRONT_PORCH	1		// lines
-`define V_SYNCH			4		// lines
-`define V_BACK_PORCH		23		// lines
-`define V_TOTAL			628	// lines
-
-`define CLK_MULTIPLY		4		// 50 * 4/5 = 40.000 MHz
-`define CLK_DIVIDE		5
-*/
-
-/*
-// 800 X 600 @ 72Hz with a 50.000MHz pixel clock
-`define H_ACTIVE			800	// pixels
-`define H_FRONT_PORCH	56		// pixels
-`define H_SYNCH			120	// pixels
-`define H_BACK_PORCH		64		// pixels
-`define H_TOTAL			1040	// pixels
-
-`define V_ACTIVE			600	// lines
-`define V_FRONT_PORCH	37		// lines
-`define V_SYNCH			6		// lines
-`define V_BACK_PORCH		23		// lines
-`define V_TOTAL			666	// lines
-
-`define CLK_MULTIPLY		2		// 50 * 2/2 = 50.000 MHz
-`define CLK_DIVIDE		2
-*/
-
-/*
-// 800 X 600 @ 75Hz with a 49.500MHz pixel clock
-`define H_ACTIVE			800	// pixels
-`define H_FRONT_PORCH	16		// pixels
-`define H_SYNCH			80		// pixels
-`define H_BACK_PORCH		160	// pixels
-`define H_TOTAL			1056	// pixels
-
-`define V_ACTIVE			600	// lines
-`define V_FRONT_PORCH	1		// lines
-`define V_SYNCH			2		// lines
-`define V_BACK_PORCH		21		// lines
-`define V_TOTAL			624	// lines
-
-`define CLK_MULTIPLY		2		// 50 * 2/2 = 50.000 MHz
-`define CLK_DIVIDE		2
-*/
-
-/*
-// 800 X 600 @ 85Hz with a 56.250MHz pixel clock
-`define H_ACTIVE			800	// pixels
-`define H_FRONT_PORCH	32		// pixels
-`define H_SYNCH			64		// pixels
-`define H_BACK_PORCH		152	// pixels
-`define H_TOTAL			1048	// pixels
-
-`define V_ACTIVE			600	// lines
-`define V_FRONT_PORCH	1		// lines
-`define V_SYNCH			3		// lines
-`define V_BACK_PORCH		27		// lines
-`define V_TOTAL			631	// lines
-
-`define CLK_MULTIPLY		9		// 50 * 9/8 = 56.250 MHz
-`define CLK_DIVIDE		8
-*/
-
-/*
-// 1024 X 768 @ 60Hz with a 65.000MHz pixel clock
-`define H_ACTIVE			1024	// pixels
-`define H_FRONT_PORCH	24		// pixels
-`define H_SYNCH			136	// pixels
-`define H_BACK_PORCH		160	// pixels
-`define H_TOTAL			1344	// pixels
-
-`define V_ACTIVE			768	// lines
-`define V_FRONT_PORCH	3		// lines
-`define V_SYNCH			6		// lines
-`define V_BACK_PORCH		29		// lines
-`define V_TOTAL			806	// lines
-
-`define CLK_MULTIPLY		13		// 50 * 13/10 = 65.000 MHz
-`define CLK_DIVIDE		10
-/*
-
-/*
-// 1024 X 768 @ 70Hz with a 75.000MHz pixel clock
-`define H_ACTIVE			1024	// pixels
-`define H_FRONT_PORCH	24		// pixels
-`define H_SYNCH			136	// pixels
-`define H_BACK_PORCH		144	// pixels
-`define H_TOTAL			1328	// pixels
-
-`define V_ACTIVE			768	// lines
-`define V_FRONT_PORCH	3		// lines
-`define V_SYNCH			6		// lines
-`define V_BACK_PORCH		29		// lines
-`define V_TOTAL			806	// lines
-
-`define CLK_MULTIPLY		3		// 50 * 3/2 = 75.000 MHz
-`define CLK_DIVIDE		2
-*/
-
-/*
-// 1024 X 768 @ 75Hz with a 78.750MHz pixel clock
-`define H_ACTIVE			1024	// pixels
-`define H_FRONT_PORCH	16		// pixels
-`define H_SYNCH			96		// pixels
-`define H_BACK_PORCH		176	// pixels
-`define H_TOTAL			1312	// pixels
-
-`define V_ACTIVE			768	// lines
-`define V_FRONT_PORCH	1		// lines
-`define V_SYNCH			3		// lines
-`define V_BACK_PORCH		28		// lines
-`define V_TOTAL			800	// lines
-
-`define CLK_MULTIPLY		11		// 50 * 11/7 = 78.571 MHz
-`define CLK_DIVIDE		7
-*/
-
-/*
-// 1024 X 768 @ 85Hz with a 94.500MHz pixel clock
-`define H_ACTIVE			1024	// pixels
-`define H_FRONT_PORCH	48		// pixels
-`define H_SYNCH			96		// pixels
-`define H_BACK_PORCH		208	// pixels
-`define H_TOTAL			1376	// pixels
-
-`define V_ACTIVE			768	// lines
-`define V_FRONT_PORCH	1		// lines
-`define V_SYNCH			3		// lines
-`define V_BACK_PORCH		36		// lines
-`define V_TOTAL			808	// lines
-
-`define CLK_MULTIPLY		17		// 50 * 17/9 = 94.444 MHz
-`define CLK_DIVIDE		9
-*/
-
diff --git a/Computer_MiST/Laser310_MiST/rtl/SVGA_TIMING_GENERATION.v b/Computer_MiST/Laser310_MiST/rtl/SVGA_TIMING_GENERATION.v
deleted file mode 100644
index 42a99da6..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/SVGA_TIMING_GENERATION.v
+++ /dev/null
@@ -1,353 +0,0 @@
-`include "SVGA_DEFINES.v"
-
-
-`define SVGA_DECODE_DELAY  7
-// 延时：字符模式
-// 1、(001)锁存 vram 地址，2、(010)读取 vram  3、(011)锁存 vram 数据 4、(100)字库地址 5、(101)锁存字库 
-// 6、(110)移位得到点阵，同时锁存vram数据用于调色板 7、(111)建立调色板，锁存色彩
-
-// Delay: Character mode
-// 1 (001) latch vram address, 2, (010) read vram 3, (011) latch vram data 4, (100) font address 5, (101) latch font
-// 6, (110) shift to get a lattice, while latching vram data for the palette 7, (111) to create a palette, latch color
-
-// 延时：图形模式 128x64 4色
-// 1、(001)锁存 vram 地址，2、(010)读取 vram  3、(011)锁存 vram 数据 4、(100)空 5、(101)数据锁存至移位寄存器
-// 6、(110)移位得到点阵 7、(111)建立调色板，锁存色彩
-
-// Delay: graphics mode 128x64 4 colors
-// 1, (001) latch vram address, 2, (010) read vram 3, (011) latch vram data 4, (100) empty 5, (101) data latched to the shift register
-// 6, (110) shift to get the dot matrix 7, (111) to create a palette, latch color
-
-module SVGA_TIMING_GENERATION
-(
-	pixel_clock,
-	reset,
-	h_synch,
-	v_synch,
-	blank,
-	pixel_count,
-	line_count,
-
-	show_border,
-
-	// text
-	subchar_pixel,
-	subchar_line,
-	char_column,
-	char_line,
-
-	// graph
-	graph_pixel,
-	graph_line_2x,
-	graph_line_3x
-);
-
-input 				pixel_clock;		// pixel clock
-input 				reset;				// reset
-(*keep*)output	reg			h_synch;			// horizontal synch for VGA connector
-(*keep*)output	reg			v_synch;			// vertical synch for VGA connector
-output	reg			blank;				// composite blanking
-output	reg	[10:0]	pixel_count;		// counts the pixels in a line
-output	reg	[9:0]	line_count;			// counts the display lines
-
-(*keep*)output	reg			show_border;
-
-// 字符控制
-(*keep*)output	reg	[3:0]	subchar_pixel;		// pixel position within the character
-(*keep*)output	reg	[4:0]	subchar_line;		// identifies the line number within a character block
-(*keep*)output	reg	[6:0]	char_column;		// character number on the current line
-(*keep*)output	reg	[6:0]	char_line;			// line number on the screen
-
-// 图形控制 128*64
-(*keep*)output	reg		[8:0]	graph_pixel;
-(*keep*)output	reg		[9:0]	graph_line_3x;
-
-// 图形控制 256*192
-(*keep*)output	reg		[9:0]	graph_line_2x;
-
-(*keep*)reg			h_blank;
-reg			v_blank;
-
-reg			show_pixel;
-reg			show_line;
-
-// CREATE THE HORIZONTAL LINE PIXEL COUNTER
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
-		// on reset set pixel counter to 0
-		pixel_count <= 11'd0;
-
-	else if (pixel_count == (`H_TOTAL - 1))
-		// last pixel in the line, so reset pixel counter
-		pixel_count <= 11'd0;
-
-	else
-		pixel_count <= pixel_count + 1;
-end
-
-// CREATE THE HORIZONTAL SYNCH PULSE
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
-		// on reset remove h_synch
-		h_synch <= 1'b0;
-
-	else if (pixel_count == (`H_ACTIVE + `H_FRONT_PORCH - 1))
-		// start of h_synch
-		h_synch <= 1'b1;
-
-	else if (pixel_count == (`H_TOTAL - `H_BACK_PORCH - 1))
-		// end of h_synch
-		h_synch <= 1'b0;
-end
-
-// CREATE THE VERTICAL FRAME LINE COUNTER
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
-		// on reset set line counter to 0
-		line_count <= 10'd0;
-
-	else if ((line_count == (`V_TOTAL - 1)) & (pixel_count == (`H_TOTAL - 1)))
-		// last pixel in last line of frame, so reset line counter
-		line_count <= 10'd0;
-
-	else if ((pixel_count == (`H_TOTAL - 1)))
-		// last pixel but not last line, so increment line counter
-		line_count <= line_count + 1;
-end
-
-// CREATE THE VERTICAL SYNCH PULSE
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
-		// on reset remove v_synch
-		v_synch <= 1'b0;
-
-	else if ((line_count == (`V_ACTIVE + `V_FRONT_PORCH - 1) &
-		   (pixel_count == `H_TOTAL - 1)))
-		// start of v_synch
-		v_synch <= 1'b1;
-
-	else if ((line_count == (`V_TOTAL - `V_BACK_PORCH - 1)) &
-		   (pixel_count == (`H_TOTAL - 1)))
-		// end of v_synch
-		v_synch <= 1'b0;
-end
-
-
-// CREATE THE HORIZONTAL BLANKING SIGNAL
-// the "-2" is used instead of "-1" because of the extra register delay
-// for the composite blanking signal
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
-		// on reset remove the h_blank
-		h_blank <= 1'b0;
-
-	else if (pixel_count == (`H_ACTIVE -2))
-		// start of HBI
-		h_blank <= 1'b1;
-
-	else if (pixel_count == (`H_TOTAL -2))
-		// end of HBI
-		h_blank <= 1'b0;
-end
-
-
-// CREATE THE VERTICAL BLANKING SIGNAL
-// the "-2" is used instead of "-1"  in the horizontal factor because of the extra
-// register delay for the composite blanking signal
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
-		// on reset remove v_blank
-		v_blank <= 1'b0;
-
-	else if ((line_count == (`V_ACTIVE - 1) &
-		   (pixel_count == `H_TOTAL - 2)))
-		// start of VBI
-		v_blank <= 1'b1;
-
-	else if ((line_count == (`V_TOTAL - 1)) &
-		   (pixel_count == (`H_TOTAL - 2)))
-		// end of VBI
-		v_blank <= 1'b0;
-end
-
-
-// CREATE THE COMPOSITE BANKING SIGNAL
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
-		// on reset remove blank
-		blank <= 1'b0;
-
-	// blank during HBI or VBI
-	else if (h_blank || v_blank)
-		blank <= 1'b1;
-
-	else
-		// active video do not blank
-		blank <= 1'b0;
-end
-
-
-////////////////////////////////////////////////////
-// 以上部分内容相对固定，是VGA的控制信号和计数器  //
-////////////////////////////////////////////////////
-
-
-/*
-   CREATE THE CHARACTER COUNTER.
-   CHARACTERS ARE DEFINED WITHIN AN 8 x 8 PIXEL BLOCK.
-
-	A 640  x 480 video mode will display 80  characters on 60 lines.
-	A 800  x 600 video mode will display 100 characters on 75 lines.
-	A 1024 x 768 video mode will display 128 characters on 96 lines.
-
-	"subchar_line" identifies the row in the 8 x 8 block.
-	"subchar_pixel" identifies the column in the 8 x 8 block.
-*/
-
-// 8x12点阵 32x16个字符 256x192
-// 640x480 倍线 512x384 左右各空64个点，上下空 48 个点。
-// 需要生成四个数据：
-// 字符点阵 subchar_line subchar_pixel
-// 字符寻址 char_column char_line
-
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
-		show_pixel <= 1'b0;
-	else if (pixel_count == (-1) + 64 - `SVGA_DECODE_DELAY)
-		show_pixel <= 1'b1;
-	else if (pixel_count == (`H_ACTIVE - 1) - 64 - `SVGA_DECODE_DELAY)
-		show_pixel <= 1'b0;
-end
-
-always @ (posedge h_synch or posedge reset) begin
-	if (reset)
-		show_line <= 1'b0;
-	else if (line_count == (-1) + 48)
-		show_line <= 1'b1;
-	else if (line_count == (`V_ACTIVE - 1) - 48)
-		show_line <= 1'b0;
-end
-
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
-		show_border <= 1'b1;
-	else if (pixel_count == (-1) + 64)
-		show_border <= ~show_line;
-	else if (pixel_count == (`H_ACTIVE - 1) - 64)
-		show_border <= 1'b1;
-end
-
-
-// text 32x16
-
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
-	begin
-		// reset to 5 so that the first character data can be latched
-		subchar_pixel <= 4'b0000;
-		char_column <= 7'd0;
-	end
-	else if (h_synch)
-	begin
-		// reset to 5 so that the first character data can be latched
-		subchar_pixel <= 4'b0000;
-		char_column <= 7'd0;
-	end
-	else if(show_pixel)
-	begin
-		subchar_pixel <= subchar_pixel + 1;
-		if(subchar_pixel == 4'b1111)			// 8*2-1
-			char_column <= char_column + 1;
-	end
-end
-
-
-always @ (posedge h_synch or posedge reset) begin
-	if (reset)
-	begin
-		// on reset set line counter to 0
-		subchar_line <= 5'b00000;
-		char_line <= 7'd0;
-	end
-	else if(v_synch)
-	begin
-		// reset line counter
-		subchar_line <= 5'b00000;
-		char_line <= 7'd0;
-	end
-	else if(show_line)
-		if(subchar_line == 5'd23)		// 12*2-1
-		begin
-			subchar_line <= 5'b00000;
-			char_line <= char_line + 1;
-		end
-		else
-			// increment line counter
-			subchar_line <= subchar_line + 1;
-end
-
-
-// 为所有图形模式提供水平计数
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset)
-	begin
-		// reset to 5 so that the first character data can be latched
-		graph_pixel <= 9'd0;
-	end
-	else if (h_synch)
-	begin
-		// reset to 5 so that the first character data can be latched
-		graph_pixel <= 9'd0;
-	end
-	else if(show_pixel)
-	begin
-		graph_pixel <= graph_pixel + 1;
-	end
-end
-
-// 为图形模式提供垂直计数
-// 64x64  4色
-// 128x64  2色
-// 128x64  4色
-always @ (posedge h_synch or posedge reset) begin
-	if (reset)
-	begin
-		// on reset set line counter to 0
-		graph_line_3x <= 10'd0;
-	end
-	else if(v_synch)
-	begin
-		// reset line counter
-		graph_line_3x <= 10'd0;
-	end
-	else if(show_line)
-		if(graph_line_3x[1:0] == 2'b10)		// 3行为单位计数
-			graph_line_3x <= graph_line_3x + 2;
-		else
-			// increment line counter
-			graph_line_3x <= graph_line_3x + 1;
-end
-
-// 为图形模式提供垂直计数
-// 128x96  2色
-// 128x96  4色
-// 128x192 2色
-// 128x192 4色
-// 256x192 2色
-always @ (posedge h_synch or posedge reset) begin
-	if (reset)
-	begin
-		// on reset set line counter to 0
-		graph_line_2x <= 10'd0;
-	end
-	else if(v_synch)
-	begin
-		// reset line counter
-		graph_line_2x <= 10'd0;
-	end
-	else if(show_line)
-		// increment line counter
-		graph_line_2x <= graph_line_2x + 1;
-end
-
-endmodule //SVGA_TIMING_GENERATION
diff --git a/Computer_MiST/Laser310_MiST/rtl/T80/T80.vhd b/Computer_MiST/Laser310_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index da01f6b4..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/T80/T80.vhd
+++ /dev/null
@@ -1,1080 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in  std_logic;
-		CLK_n           : in  std_logic;
-		CEN             : in  std_logic;
-		WAIT_n          : in  std_logic;
-		INT_n           : in  std_logic;
-		NMI_n           : in  std_logic;
-		BUSRQ_n         : in  std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A               : out std_logic_vector(15 downto 0);
-		DInst           : in  std_logic_vector(7 downto 0);
-		DI              : in  std_logic_vector(7 downto 0);
-		DO              : out std_logic_vector(7 downto 0);
-		MC              : out std_logic_vector(2 downto 0);
-		TS              : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone              : std_logic_vector(2 downto 0) := "111";
-	constant aBC                : std_logic_vector(2 downto 0) := "000";
-	constant aDE                : std_logic_vector(2 downto 0) := "001";
-	constant aXY                : std_logic_vector(2 downto 0) := "010";
-	constant aIOA               : std_logic_vector(2 downto 0) := "100";
-	constant aSP                : std_logic_vector(2 downto 0) := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR          => IR,
-			ISet        => ISet,
-			MCycle      => MCycle,
-			F           => F,
-			NMICycle    => NMICycle,
-			IntCycle    => IntCycle,
-			MCycles     => MCycles_d,
-			TStates     => TStates,
-			Prefix      => Prefix,
-			Inc_PC      => Inc_PC,
-			Inc_WZ      => Inc_WZ,
-			IncDec_16   => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op      => ALU_Op,
-			Save_ALU    => Save_ALU,
-			PreserveC   => PreserveC,
-			Arith16     => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ        => IORQ_i,
-			Jump        => Jump,
-			JumpE       => JumpE,
-			JumpXY      => JumpXY,
-			Call        => Call,
-			RstP        => RstP,
-			LDZ         => LDZ,
-			LDW         => LDW,
-			LDSPHL      => LDSPHL,
-			Special_LD  => Special_LD,
-			ExchangeDH  => ExchangeDH,
-			ExchangeRp  => ExchangeRp,
-			ExchangeAF  => ExchangeAF,
-			ExchangeRS  => ExchangeRS,
-			I_DJNZ      => I_DJNZ,
-			I_CPL       => I_CPL,
-			I_CCF       => I_CCF,
-			I_SCF       => I_SCF,
-			I_RETN      => I_RETN,
-			I_BT        => I_BT,
-			I_BC        => I_BC,
-			I_BTR       => I_BTR,
-			I_RLD       => I_RLD,
-			I_RRD       => I_RRD,
-			I_INRC      => I_INRC,
-			SetDI       => SetDI,
-			SetEI       => SetEI,
-			IMode       => IMode,
-			Halt        => Halt,
-			NoRead      => NoRead,
-			Write       => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16     => Z16_r,
-			ALU_Op  => ALU_Op_r,
-			IR      => IR(5 downto 0),
-			ISet    => ISet,
-			BusA    => BusA,
-			BusB    => BusB,
-			F_In    => F,
-			Q       => ALU_Q,
-			F_Out   => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Computer_MiST/Laser310_MiST/rtl/T80/T80_ALU.vhd b/Computer_MiST/Laser310_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index 95c98dab..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/T80/T80_ALU.vhd
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Computer_MiST/Laser310_MiST/rtl/T80/T80_MCode.vhd b/Computer_MiST/Laser310_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 43cea1b5..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/T80/T80_MCode.vhd
+++ /dev/null
@@ -1,1944 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-				  ALU_Op <= "1000";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-				  ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-				  ALU_Op <= "1010";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Computer_MiST/Laser310_MiST/rtl/T80/T80_Pack.vhd b/Computer_MiST/Laser310_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index 42cf6105..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/T80/T80_Pack.vhd
+++ /dev/null
@@ -1,217 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Computer_MiST/Laser310_MiST/rtl/T80/T80_Reg.vhd b/Computer_MiST/Laser310_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/T80/T80_Reg.vhd
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Computer_MiST/Laser310_MiST/rtl/T80/T80sed.vhd b/Computer_MiST/Laser310_MiST/rtl/T80/T80sed.vhd
deleted file mode 100644
index 0c28ec21..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/T80/T80sed.vhd
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n         : in  std_logic;
-		CLK_n           : in  std_logic;
-		CLKEN           : in  std_logic;
-		WAIT_n          : in  std_logic;
-		INT_n           : in  std_logic;
-		NMI_n           : in  std_logic;
-		BUSRQ_n         : in  std_logic;
-		M1_n            : out std_logic;
-		MREQ_n          : out std_logic;
-		IORQ_n          : out std_logic;
-		RD_n            : out std_logic;
-		WR_n            : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A               : out std_logic_vector(15 downto 0);
-		DI              : in  std_logic_vector(7 downto 0);
-		DO              : out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n   : std_logic;
-	signal NoRead       : std_logic;
-	signal Write        : std_logic;
-	signal IORQ         : std_logic;
-	signal DI_Reg       : std_logic_vector(7 downto 0);
-	signal MCycle       : std_logic_vector(2 downto 0);
-	signal TState       : std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode      => 0,
-			IOWait    => 1)
-		port map(
-			CEN        => CLKEN,
-			M1_n       => M1_n,
-			IORQ       => IORQ,
-			NoRead     => NoRead,
-			Write      => Write,
-			RFSH_n     => RFSH_n,
-			HALT_n     => HALT_n,
-			WAIT_n     => Wait_n,
-			INT_n      => INT_n,
-			NMI_n      => NMI_n,
-			RESET_n    => RESET_n,
-			BUSRQ_n    => BUSRQ_n,
-			BUSAK_n    => BUSAK_n,
-			CLK_n      => CLK_n,
-			A          => A,
-			DInst      => DI,
-			DI         => DI_Reg,
-			DO         => DO,
-			MC         => MCycle,
-			TS         => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Computer_MiST/Laser310_MiST/rtl/Text1.txt b/Computer_MiST/Laser310_MiST/rtl/Text1.txt
deleted file mode 100644
index b8bd2837..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/Text1.txt
+++ /dev/null
@@ -1,483 +0,0 @@
-
-
-
-
-// keyboard
-
-/*****************************************************************************
-* Convert PS/2 keyboard to ASCII keyboard
-******************************************************************************/
-
-/*
-   KD5 KD4 KD3 KD2 KD1 KD0 扫描用地址
-A0  R   Q   E       W   T  68FEH       0
-A1  F   A   D  CTRL S   G  68FDH       8
-A2  V   Z   C  SHFT X   B  68FBH      16
-A3  4   1   3       2   5  68F7H      24
-A4  M  空格 ，      .   N  68EFH      32
-A5  7   0   8   -   9   6  68DFH      40
-A6  U   P   I  RETN O   Y  68BFH      48
-A7  J   ；  K   :   L   H  687FH      56
-*/
-
-//  7: 0
-// 15: 8
-// 23:16
-// 31:24
-// 39:32
-// 47:40
-// 55:48
-// 63:56
-
-
-
-// 键盘检测的方法，就是循环地问每一行线发送低电平信号，也就是用该地址线为“0”的地址去读取数据。
-// 例如，检测第一行时，使A0为0，其余为1；加上选通IC4的高五位地址01101，成为01101***11111110B（A8~A10不起作用，
-// 可为任意值，故68FEH，69FEH，6AFEH，6BFEH，6CFEH，6DFEH，6EFEH，6FFEH均可）。
-// 读 6800H 判断是否有按键按下。
-
-// The method of keyboard detection is to cyclically ask each line to send a low level signal, 
-// that is, to read the data with the address line "0".
-// For example, when detecting the first line, make A0 0 and the rest 1; plus the high five-bit address 01101 of the strobe IC4, 
-// become 01101***11111110B (A8~A10 does not work,
-// It can be any value, so 68FEH, 69FEH, 6AFEH, 6BFEH, 6CFEH, 6DFEH, 6EFEH, 6FFEH can be).
-// Read 6800H to determine if there is a button press.
-
-// 键盘选通，整个竖列有一个选通的位置被按下，对应值为0。
-// The keyboard is strobed, and a strobe position is pressed in the entire vertical column, and the corresponding value is 0.
-
-// 键盘扩展
-// 加入方向键盘
-// Keyboard extension
-
-// left:  ctrl M      37 KEY_EX[5]
-// right: ctrl ,      35 KEY_EX[6]
-// up:    ctrl .      33 KEY_EX[4]
-// down:  ctrl space  36 KEY_EX[7]
-// esc:   ctrl -      42 KEY_EX[3]
-// backspace:  ctrl M      37 KEY_EX[8]
-
-// R-Shift
-
-
-wire	[63:0]	KEY_C		=	EMU_KEY_EN?EMU_KEY:KEY;
-wire	[9:0]	KEY_EX_C	=	EMU_KEY_EN?EMU_KEY_EX:KEY_EX;
-
-//wire KEY_CTRL_ULRD = (KEY_EX[7:4]==4'b1111);
-wire KEY_CTRL_ULRD_BRK = (KEY_EX[8:3]==6'b111111);
-
-wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY_C[61], KEY_C[53], KEY_C[45],           KEY_C[37]&KEY_EX_C[5]&KEY_EX_C[8], KEY_C[29], KEY_C[21],           KEY_C[13],                   KEY_C[ 5]})==8'hff;
-wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY_C[60], KEY_C[52], KEY_C[44],           KEY_C[36]&KEY_EX_C[7], KEY_C[28], KEY_C[20],           KEY_C[12],                   KEY_C[ 4]})==8'hff;
-wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY_C[59], KEY_C[51], KEY_C[43],           KEY_C[35]&KEY_EX_C[6], KEY_C[27], KEY_C[19],           KEY_C[11],                   KEY_C[ 3]})==8'hff;
-wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY_C[58], KEY_C[50], KEY_C[42]&KEY_EX_C[3], KEY_C[34],           KEY_C[26], KEY_C[18]&KEY_EX_C[0], KEY_C[10]&KEY_CTRL_ULRD_BRK, KEY_C[ 2]})==8'hff;
-wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY_C[57], KEY_C[49], KEY_C[41],           KEY_C[33]&KEY_EX_C[4], KEY_C[25], KEY_C[17],           KEY_C[ 9],                   KEY_C[ 1]})==8'hff;
-wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY_C[56], KEY_C[48], KEY_C[40],           KEY_C[32],             KEY_C[24], KEY_C[16],           KEY_C[ 8],                   KEY_C[ 0]})==8'hff;
-
-/*
-wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY[61], KEY[53], KEY[45], KEY[37], KEY[29], KEY[21], KEY[13], KEY[ 5]})==8'hff;
-wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY[60], KEY[52], KEY[44], KEY[36], KEY[28], KEY[20], KEY[12], KEY[ 4]})==8'hff;
-wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY[59], KEY[51], KEY[43], KEY[35], KEY[27], KEY[19], KEY[11], KEY[ 3]})==8'hff;
-wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY[58], KEY[50], KEY[42], KEY[34], KEY[26], KEY[18], KEY[10], KEY[ 2]})==8'hff;
-wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY[57], KEY[49], KEY[41], KEY[33], KEY[25], KEY[17], KEY[ 9], KEY[ 1]})==8'hff;
-wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY[56], KEY[48], KEY[40], KEY[32], KEY[24], KEY[16], KEY[ 8], KEY[ 0]})==8'hff;
-*/
-
-wire KEY_DATA_BIT7 = 1'b1;	// 没有空置，具体用途没有理解
-//wire KEY_DATA_BIT6 = CASS_IN;
-wire KEY_DATA_BIT6 = ~CASS_IN;
-
-assign KEY_DATA = { KEY_DATA_BIT7, KEY_DATA_BIT6, KEY_DATA_BIT5, KEY_DATA_BIT4, KEY_DATA_BIT3, KEY_DATA_BIT2, KEY_DATA_BIT1, KEY_DATA_BIT0 };
-
-/*
-assign KEY_DATA = 	(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
-					(CPU_A[1]==1'b0) ? KEY[15: 8] :
-					(CPU_A[2]==1'b0) ? KEY[23:16] :
-					(CPU_A[3]==1'b0) ? KEY[31:24] :
-					(CPU_A[4]==1'b0) ? KEY[39:32] :
-					(CPU_A[5]==1'b0) ? KEY[47:40] :
-					(CPU_A[6]==1'b0) ? KEY[55:48] :
-					(CPU_A[7]==1'b0) ? KEY[63:56] :
-					8'hff;
-
-assign KEY_DATA =
-					(CPU_A[7]==1'b0) ? KEY[63:56] :
-					(CPU_A[6]==1'b0) ? KEY[55:48] :
-					(CPU_A[5]==1'b0) ? KEY[47:40] :
-					(CPU_A[4]==1'b0) ? KEY[39:32] :
-					(CPU_A[3]==1'b0) ? KEY[31:24] :
-					(CPU_A[2]==1'b0) ? KEY[23:16] :
-					(CPU_A[1]==1'b0) ? KEY[15: 8] :
-					(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
-					8'hff;
-*/
-
-
-assign A_KEY_PRESSED = (KEY[63:0] == 64'hFFFFFFFFFFFFFFFF) ? 1'b0:1'b1;
-
-always @(posedge KB_CLK[3] or negedge SYS_RESET_N)
-begin
-	if(~SYS_RESET_N)
-	begin
-		KEY					<=	64'hFFFFFFFFFFFFFFFF;
-		KEY_EX				<=	10'h3FF;
-		KEY_Fxx				<=	12'h000;
-//		CAPS_CLK			<=	1'b0;
-		RESET_KEY_COUNT		<=	17'h1FFFF;
-
-		BOOTROM_BANK		<=	0;
-		BOOTROM_EN			<=	1'b0;
-
-		AUTOSTARTROM_BANK	<=	0;
-		AUTOSTARTROM_EN		<=	1'b0;
-	end
-	else
-	begin
-		//KEY[?] <= CAPS;
-		if(RESET_KEY_COUNT[16]==1'b0)
-			RESET_KEY_COUNT <= RESET_KEY_COUNT+1;
-
-		case(SCAN)
-		8'h07:
-		begin
-				KEY_Fxx[11]	<= PRESS;	// F12 RESET
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b0;
-					BOOTROM_BANK		<=	0;
-					AUTOSTARTROM_EN		<=	1'b0;
-					AUTOSTARTROM_BANK	<=	0;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h78:	KEY_Fxx[10] <= PRESS;	// F11
-		8'h09:	KEY_Fxx[ 9] <= PRESS;	// F10 CASS STOP
-		8'h01:	KEY_Fxx[ 8] <= PRESS;	// F9  CASS PLAY
-		8'h0A:
-		begin
-				KEY_Fxx[ 7] <= PRESS;	// F8  Ctrl or L-Shift BOOT 8
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	39;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	23;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h83:
-		begin
-				KEY_Fxx[ 6] <= PRESS;	// F7  Ctrl or L-Shift BOOT 7
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	38;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	22;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h0B:
-		begin
-				KEY_Fxx[ 5] <= PRESS;	// F6  Ctrl or L-Shift BOOT 6
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	37;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	21;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h03:
-		begin
-				KEY_Fxx[ 4] <= PRESS;	// F5  Ctrl or L-Shift BOOT 5
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	36;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	20;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h0C:
-		begin
-				KEY_Fxx[ 3] <= PRESS;	// F4  Ctrl or L-Shift BOOT 4
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	35;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	19;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h04:
-		begin
-				KEY_Fxx[ 2] <= PRESS;	// F3  Ctrl or L-Shift BOOT 3
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	34;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	18;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h06:
-		begin
-				KEY_Fxx[ 1] <= PRESS;	// F2  Ctrl or L-Shift BOOT 2
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	33;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	17;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-		8'h05:
-		begin
-				KEY_Fxx[ 0] <= PRESS;	// F1  Ctrl or L-Shift BOOT 1
-				if(PRESS && (KEY[18]==PRESS_N))
-				begin
-					BOOTROM_EN			<=	1'b1;
-					BOOTROM_BANK		<=	32;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-				else
-				if(PRESS && (KEY[10]==PRESS_N))
-				begin
-					AUTOSTARTROM_EN		<=	1'b1;
-					AUTOSTARTROM_BANK	<=	16;
-					RESET_KEY_COUNT		<=	17'h0;
-				end
-		end
-
-		8'h16:	KEY[28] <= PRESS_N;	// 1 !
-		8'h1E:	KEY[25] <= PRESS_N;	// 2 @
-		8'h26:	KEY[27] <= PRESS_N;	// 3 #
-		8'h25:	KEY[29] <= PRESS_N;	// 4 $
-		8'h2E:	KEY[24] <= PRESS_N;	// 5 %
-		8'h36:	KEY[40] <= PRESS_N;	// 6 ^
-		8'h3D:	KEY[45] <= PRESS_N;	// 7 &
-//		8'h0D:	KEY[?] <= PRESS_N;	// TAB
-		8'h3E:	KEY[43] <= PRESS_N;	// 8 *
-		8'h46:	KEY[41] <= PRESS_N;	// 9 (
-		8'h45:	KEY[44] <= PRESS_N;	// 0 )
-		8'h4E:	KEY[42] <= PRESS_N;	// - _
-//		8'h55:	KEY[?] <= PRESS_N;	// = +
-		8'h66:	KEY_EX[8] <= PRESS_N;	// backspace
-//		8'h0E:	KEY[?] <= PRESS_N;	// ` ~
-//		8'h5D:	KEY[?] <= PRESS_N;	// \ |
-		8'h49:	KEY[33] <= PRESS_N;	// . >
-		8'h4b:	KEY[57] <= PRESS_N;	// L
-		8'h44:	KEY[49] <= PRESS_N;	// O
-//		8'h11	KEY[?] <= PRESS_N; // line feed (really right ALT (Extended) see below
-		8'h5A:	KEY[50] <= PRESS_N;	// CR
-//		8'h54:	KEY[?] <= PRESS_N;	// [ {
-//		8'h5B:	KEY[?] <= PRESS_N;	// ] }
-		8'h52:	KEY[58] <= PRESS_N;	// ' "
-		8'h1D:	KEY[ 1] <= PRESS_N;	// W
-		8'h24:	KEY[ 3] <= PRESS_N;	// E
-		8'h2D:	KEY[ 5] <= PRESS_N;	// R
-		8'h2C:	KEY[ 0] <= PRESS_N;	// T
-		8'h35:	KEY[48] <= PRESS_N;	// Y
-		8'h3C:	KEY[53] <= PRESS_N;	// U
-		8'h43:	KEY[51] <= PRESS_N;	// I
-		8'h1B:	KEY[ 9] <= PRESS_N;	// S
-		8'h23:	KEY[11] <= PRESS_N;	// D
-		8'h2B:	KEY[13] <= PRESS_N;	// F
-		8'h34:	KEY[ 8] <= PRESS_N;	// G
-		8'h33:	KEY[56] <= PRESS_N;	// H
-		8'h3B:	KEY[61] <= PRESS_N;	// J
-		8'h42:	KEY[59] <= PRESS_N;	// K
-		8'h22:	KEY[17] <= PRESS_N;	// X
-		8'h21:	KEY[19] <= PRESS_N;	// C
-		8'h2a:	KEY[21] <= PRESS_N;	// V
-		8'h32:	KEY[16] <= PRESS_N;	// B
-		8'h31:	KEY[32] <= PRESS_N;	// N
-		8'h3a:	KEY[37] <= PRESS_N;	// M
-		8'h41:	KEY[35] <= PRESS_N;	// , <
-		8'h15:	KEY[ 4] <= PRESS_N;	// Q
-		8'h1C:	KEY[12] <= PRESS_N;	// A
-		8'h1A:	KEY[20] <= PRESS_N;	// Z
-		8'h29:	KEY[36] <= PRESS_N;	// Space
-//		8'h4A:	KEY[?] <= PRESS_N;	// / ?
-		8'h4C:	KEY[60] <= PRESS_N;	// ; :
-		8'h4D:	KEY[52] <= PRESS_N;	// P
-		8'h14:	KEY[10] <= PRESS_N;	// Ctrl either left or right
-		8'h12:	KEY[18] <= PRESS_N;	// L-Shift
-		8'h59:	KEY_EX[0] <= PRESS_N;	// R-Shift
-		8'h11:
-		begin
-			if(~EXTENDED)
-					KEY_EX[1] <= PRESS_N;	// Repeat really left ALT
-			else
-					KEY_EX[2] <= PRESS_N;	// LF really right ALT
-		end
-		8'h76:	KEY_EX[3] <= PRESS_N;	// Esc
-		8'h75:	KEY_EX[4] <= PRESS_N;	// up
-		8'h6B:	KEY_EX[5] <= PRESS_N;	// left
-		8'h74:	KEY_EX[6] <= PRESS_N;	// right
-		8'h72:	KEY_EX[7] <= PRESS_N;	// down
-		endcase
-	end
-end
-
-
-
-
-always @ (posedge CLK50MHZ)				// 50MHz
-	KB_CLK <= KB_CLK + 1'b1;			// 50/32 = 1.5625 MHz
-
-ps2_keyboard KEYBOARD(
-		.RESET_N(RESET_N),
-		.CLK(KB_CLK[4]),
-		.PS2_CLK(PS2_KBCLK),
-		.PS2_DATA(PS2_KBDAT),
-		.RX_SCAN(SCAN),
-		.RX_PRESSED(PRESS),
-		.RX_EXTENDED(EXTENDED)
-);
-
-assign PRESS_N = ~PRESS;
-
-
-`ifdef CASS_EMU
-
-wire			CASS_BUF_RD;
-wire	[15:0]	CASS_BUF_A;
-wire			CASS_BUF_WR;
-wire	[7:0]	CASS_BUF_DAT;
-wire	[7:0]	CASS_BUF_Q;
-
-// F9    CASS PLAY
-// F10   CASS STOP
-
-EMU_CASS_KEY	EMU_CASS_KEY(
-	KEY_Fxx[8],
-	KEY_Fxx[9],
-	// cass emu
-	CASS_BUF_RD,
-	//
-	CASS_BUF_A,
-	CASS_BUF_WR,
-	CASS_BUF_DAT,
-	CASS_BUF_Q,
-	//	Control Signals
-	EMU_CASS_EN,
-	EMU_CASS_DAT,
-
-	// key emu
-	EMU_KEY,
-	EMU_KEY_EX,
-	EMU_KEY_EN,
-    /*
-     * UART: 115200 bps, 8N1
-     */
-    UART_RXD,
-    UART_TXD,
-
-	// System
-	TURBO_SPEED,
-	// Clock: 10MHz
-	CLK10MHZ,
-	RESET_N
-);
-
-
-`ifdef CASS_EMU_16K
-
-cass_ram_16k_altera cass_buf(
-	.address(CASS_BUF_A[13:0]),
-	.clock(CLK10MHZ),
-	.data(CASS_BUF_DI),
-	.wren(CASS_BUF_WR),
-	.q(CASS_BUF_Q)
-);
-
-`endif
-
-
-`ifdef CASS_EMU_8K
-
-cass_ram_8k_altera cass_buf(
-	.address(CASS_BUF_A[12:0]),
-	.clock(CLK10MHZ),
-	.data(CASS_BUF_DI),
-	.wren(CASS_BUF_WR),
-	.q(CASS_BUF_Q)
-);
-
-`endif
-
-
-`ifdef CASS_EMU_4K
-
-cass_ram_4k_altera cass_buf(
-	.address(CASS_BUF_A[11:0]),
-	.clock(CLK10MHZ),
-	.data(CASS_BUF_DAT),
-	.wren(CASS_BUF_WR),
-	.q(CASS_BUF_Q)
-);
-
-`endif
-
-
-`ifdef CASS_EMU_2K
-
-cass_ram_2k_altera cass_buf(
-	.address(CASS_BUF_A[10:0]),
-	.clock(CLK10MHZ),
-	.data(CASS_BUF_DAT),
-	.wren(CASS_BUF_WR),
-	.q(CASS_BUF_Q)
-);
-
-`endif
-
-`endif
-
-
-
-assign	CASS_OUT = EMU_CASS_EN ? EMU_CASS_DAT : {LATCHED_IO_DATA_WR[2], 1'b0};
-
-(*keep*)wire trap = (CPU_RD|CPU_WR) && (CPU_A[15:12] == 4'h0);
-
diff --git a/Computer_MiST/Laser310_MiST/rtl/VIDEO_OUT.v b/Computer_MiST/Laser310_MiST/rtl/VIDEO_OUT.v
deleted file mode 100644
index 2c8f8a25..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/VIDEO_OUT.v
+++ /dev/null
@@ -1,70 +0,0 @@
-module VIDEO_OUT
-(
-	pixel_clock,
-	reset,
-	vga_red_data,
-	vga_green_data,
-	vga_blue_data,
-	h_synch,
-	v_synch,
-	blank,
-
-	VGA_OUT_HSYNC,
-	VGA_OUT_VSYNC,
-	VGA_OUT_RED,
-	VGA_OUT_GREEN,
-	VGA_OUT_BLUE
-);
-
-input			pixel_clock;
-input			reset;
-input	[7:0]	vga_red_data;
-input	[7:0]	vga_green_data;
-input	[7:0]	vga_blue_data;
-input			h_synch;
-input			v_synch;
-input			blank;
-
-output			VGA_OUT_HSYNC;
-output			VGA_OUT_VSYNC;
-output	[7:0]	VGA_OUT_RED;
-output	[7:0]	VGA_OUT_GREEN;
-output	[7:0]	VGA_OUT_BLUE;
-
-reg				VGA_OUT_HSYNC;
-reg				VGA_OUT_VSYNC;
-reg		[7:0]	VGA_OUT_RED;
-reg		[7:0]	VGA_OUT_GREEN;
-reg		[7:0]	VGA_OUT_BLUE;
-
-// make the external video connections
-always @ (posedge pixel_clock or posedge reset) begin
-	if (reset) begin
-		// shut down the video output during reset
-		VGA_OUT_HSYNC 			<= 1'b1;
-		VGA_OUT_VSYNC 			<= 1'b1;
-		VGA_OUT_RED				<= 8'b0;
-		VGA_OUT_GREEN			<= 8'b0;
-		VGA_OUT_BLUE			<= 8'b0;
-	end
-	
-	else if (blank) begin
-		// output black during the blank signal
-		VGA_OUT_HSYNC	 		<= h_synch;
-		VGA_OUT_VSYNC 	 		<= v_synch;
-		VGA_OUT_RED				<= 8'b0;
-		VGA_OUT_GREEN			<= 8'b0;
-		VGA_OUT_BLUE			<= 8'b0;
-	end
-	
-	else begin
-		// output color data otherwise
-		VGA_OUT_HSYNC	 		<= h_synch;
-		VGA_OUT_VSYNC 	 		<= v_synch;
-		VGA_OUT_RED				<= vga_red_data;
-		VGA_OUT_GREEN			<= vga_green_data;
-		VGA_OUT_BLUE			<= vga_blue_data;
-	end
-end
-
-endmodule // VIDEO_OUT
diff --git a/Computer_MiST/Laser310_MiST/rtl/build_id.tcl b/Computer_MiST/Laser310_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/build_id.tcl
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Computer_MiST/Laser310_MiST/rtl/dac.vhd b/Computer_MiST/Laser310_MiST/rtl/dac.vhd
deleted file mode 100644
index 9685a6cc..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/dac.vhd
+++ /dev/null
@@ -1,48 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity dac is
-	generic (
-		C_bits  : integer := 12
-	);
-	port (
-		clk_i   : in  std_logic;
-		res_n_i : in  std_logic;
-		dac_i   : in  std_logic_vector(C_bits-1 downto 0);
-		dac_o   : out std_logic
-	);
-end dac;
-
-architecture rtl of dac is
-	signal sig_in: unsigned(C_bits downto 0);
-begin
-	seq: process(clk_i, res_n_i)
-	begin
-		if res_n_i = '0' then
-			sig_in <= to_unsigned(2**C_bits, sig_in'length);
-			dac_o  <= '0';
-		elsif rising_edge(clk_i) then
-		        -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
-			--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
-			sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
-			dac_o  <= sig_in(C_bits);
-		end if;
-	end process seq;
-end rtl;
diff --git a/Computer_MiST/Laser310_MiST/rtl/dpram.vhd b/Computer_MiST/Laser310_MiST/rtl/dpram.vhd
deleted file mode 100644
index 78823ec4..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/dpram.vhd
+++ /dev/null
@@ -1,58 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dpram is
-
-generic (
-	 addr_width_g : integer := 8;
-	 data_width_g : integer := 8
-);
-port (
-	clk_a_i  : in  std_logic;
-	en_a_i   : in  std_logic;
-	we_i     : in  std_logic;
-	addr_a_i : in  std_logic_vector(addr_width_g-1 downto 0);
-	data_a_i : in  std_logic_vector(data_width_g-1 downto 0);
-	data_a_o : out std_logic_vector(data_width_g-1 downto 0);
-	clk_b_i  : in  std_logic;
-	addr_b_i : in  std_logic_vector(addr_width_g-1 downto 0);
-	data_b_o : out std_logic_vector(data_width_g-1 downto 0)
-);
-
-end dpram;
-
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dpram is
-
-  type   ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0);
-  signal ram_q : ram_t;
-
-begin
-
-  mem_a: process (clk_a_i)
-  begin
-    if rising_edge(clk_a_i) then
-      if we_i = '1' and en_a_i = '1' then
-        ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i;
-		  data_a_o <= data_a_i;
-		else
-		  data_a_o <= ram_q(to_integer(unsigned(addr_a_i)));
-      end if;
-    end if;
-  end process mem_a;
-
-  mem_b: process (clk_b_i)
-  begin
-    if rising_edge(clk_b_i) then
-		data_b_o <= ram_q(to_integer(unsigned(addr_b_i)));
-    end if;
-  end process mem_b;
-
-end rtl;
diff --git a/Computer_MiST/Laser310_MiST/rtl/fdc.v b/Computer_MiST/Laser310_MiST/rtl/fdc.v
deleted file mode 100644
index b63ae324..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/fdc.v
+++ /dev/null
@@ -1,967 +0,0 @@
-/*****************************************************************************
-* Floppy
-******************************************************************************/
-
-// POLLING after Clock
-
-// vz dsk Parameter
-// 154 * 16  * 40 = 98560 = 0x18100
-// 154 * 16 = 2464 = 0x9A0 = 0x4D0 * 2
-`define	FD_MAX_LEN		17'h18100
-`define	FD_TRACK_LEN	12'h9A0
-`define	FD_TRACK_STEP	8'h4D
-
-// 40*2		0 --- 78
-`define	FD_MAX_TRACK_NO	8'd78
-
-
-module FDC_IF (
-	FDC_CLK,
-	RESET_N,
-	SW,
-	DBG,
-
-	FDC_RAM_R,
-	FDC_RAM_W,
-	FDC_RAM_ADDR_R,
-	FDC_RAM_ADDR_W,
-	FDC_RAM_DATA_R,
-	FDC_RAM_DATA_W,
-
-	FDC_IO,
-	FDC_IO_POLL,
-	FDC_IO_DATA,
-	FDC_IO_CT,
-
-	FDC_SIG,
-	FDC_SIG_CLK,
-
-	FDC_CT,
-	FDC_DATA,
-	FDC_POLL,
-	FDC_WP,
-
-	FLOPPY_SECTOR_BYTE,
-	TRACK1_NO,
-	TRACK2_NO,
-	DRIVE1,
-	DRIVE2,
-	MOTOR
-);
-
-
-input						FDC_CLK;
-input						RESET_N;
-input			[1:0]		SW;
-input			[3:0]		DBG;
-
-output			[17:0]		FDC_RAM_ADDR_R;
-output			[17:0]		FDC_RAM_ADDR_W;
-output	reg					FDC_RAM_R;
-output	reg					FDC_RAM_W;
-input			[7:0]		FDC_RAM_DATA_R;
-output			[7:0]		FDC_RAM_DATA_W;
-
-
-input						FDC_IO;
-input						FDC_IO_POLL;
-input						FDC_IO_DATA;
-input						FDC_IO_CT;
-
-output						FDC_SIG;
-output	reg					FDC_SIG_CLK;
-
-input			[7:0]		FDC_CT;
-
-output			[7:0]		FDC_DATA;
-output						FDC_POLL;
-output						FDC_WP;
-
-
-reg		[11:0]		FLOPPY_BYTE;
-output	reg		[7:0]		FLOPPY_SECTOR_BYTE;	// Count Sector Bytes
-
-reg		[6:0]		CLK_CNT;
-reg		[6:0]		CLK_CNT_W;
-
-reg		[18:0]		SYNC_CNT;
-reg		[7:0]		FLOPPY_SECTOR_DELAY;	// Delay on Sector End
-
-
-reg					FD_REC1;
-reg					FDC_POLL1;
-reg					FDC_REC_DATA_BIT1;
-reg					FDC_DATA_BIT1;
-reg		[7:0]		FDC_DATA1;
-reg		[7:0]		LATCHED_FDC_DATA1;
-reg					FDC_DATA_SET1;
-
-reg					FD_REC2;
-reg					FDC_POLL2;
-reg					FDC_REC_DATA_BIT2;
-reg					FDC_DATA_BIT2;
-reg		[7:0]		FDC_DATA2;
-reg		[7:0]		LATCHED_FDC_DATA2;
-
-reg		[3:0]		BIT_CNT_W;
-reg		[2:0]		BIT_CNT;
-
-wire				FDC_RAM_DATA_R_BIT;
-
-
-reg		[1:0]		STEPPER1;
-reg		[1:0]		STEPPER2;
-output	reg		[7:0]		TRACK1_NO;
-output	reg		[7:0]		TRACK2_NO;
-reg		[12:0]		TRACK1;
-reg		[12:0]		TRACK2;
-(*keep*)wire	[13:0]		TRACK;
-wire	[12:0]		TRACK1_UP;
-wire	[12:0]		TRACK1_DOWN;
-wire	[12:0]		TRACK2_UP;
-wire	[12:0]		TRACK2_DOWN;
-reg		[17:0]		FLOPPY_ADDRESS_R;
-reg		[17:0]		FLOPPY_ADDRESS_W;
-//reg		[7:0]		FLOPPY_WRITE_DATA;
-
-reg					WRITE_WAIT_FIRST_OP;
-reg					WRITE_DATA_BIT_VAL;
-
-reg		[7:0]		WRITE_DATA1;
-reg					WRITE_DATA_MODI1;
-reg		[7:0]		WRITE_DATA2;
-reg					WRITE_DATA2_MODI;
-
-
-(*keep*)wire	[7:0]		FLOPPY_RD_DATA;
-(*keep*)wire	[7:0]		FLOPPY_DATA;
-(*keep*)wire				FLOPPY_READ;
-(*keep*)wire				FLOPPY_WRITE;
-wire				FLOPPY_WP_READ;
-reg					PHASE0;
-reg					PHASE0_1;
-reg					PHASE0_2;
-reg					PHASE1;
-reg					PHASE1_1;
-reg					PHASE1_2;
-reg					PHASE2;
-reg					PHASE2_1;
-reg					PHASE2_2;
-reg					PHASE3;
-reg					PHASE3_1;
-reg					PHASE3_2;
-output	reg					DRIVE1;
-output	reg					DRIVE2;
-output	reg					MOTOR;
-
-reg					WRITE_REQUEST_N;
-reg					WRITE_DATA_BIT;
-
-reg					Q6;
-reg					Q7;
-wire				DRIVE1_EN;
-wire				DRIVE2_EN;
-wire				DRIVE1_X;
-wire				DRIVE2_X;
-wire				DRIVE_SWAP;
-wire				DRIVE1_FLOPPY_WP;
-wire				DRIVE2_FLOPPY_WP;
-
-reg					MODIFY_DRIVE1;
-reg					MODIFY_DRIVE2;
-
-assign	FDC_RAM_ADDR_R	=	FLOPPY_ADDRESS_R;
-assign	FDC_RAM_ADDR_W	=	FLOPPY_ADDRESS_W;
-
-
-(*preserve*)reg	[7:0]	FDC_CNT;
-(*preserve*)reg	[7:0]	FDC_CNT_POLL;
-(*preserve*)reg	[7:0]	FDC_CNT_DATA;
-(*preserve*)reg	[19:0]	FDC_CNT_CT;
-
-always @(posedge FDC_CLK or negedge RESET_N)
-begin
-	if(~RESET_N)
-	begin
-		FDC_CNT			<=	8'hFF;
-		FDC_CNT_POLL	<=	8'hFF;
-		FDC_CNT_DATA	<=	8'hFF;
-		FDC_CNT_CT		<=	20'hFFFFF;
-	end
-	else
-	begin
-		if(FDC_IO)
-			FDC_CNT	<=	0;
-		else if(~FDC_CNT[7])
-			FDC_CNT	<=	FDC_CNT + 1;
-
-		if(FDC_IO_POLL)
-			FDC_CNT_POLL	<=	0;
-		else if(~FDC_CNT_POLL[7])
-			FDC_CNT_POLL	<=	FDC_CNT_POLL + 1;
-
-		if(FDC_IO_DATA)
-			FDC_CNT_DATA	<=	0;
-		else if(~FDC_CNT_DATA[7])
-			FDC_CNT_DATA	<=	FDC_CNT_DATA + 1;
-
-		if(FDC_IO_CT)
-			FDC_CNT_CT		<=	0;
-		else if(~FDC_CNT_CT[19])
-			FDC_CNT_CT		<=	FDC_CNT_CT + 1;
-	end
-end
-
-
-
-assign	FDC_POLL	=	(DRIVE1_EN)?FDC_POLL1:
-						(DRIVE2_EN)?FDC_POLL2:
-									1'b0;
-
-
-assign	FDC_DATA	=	(DRIVE1_EN)?FDC_DATA1:
-						(DRIVE2_EN)?FDC_DATA2:
-									8'hFF;
-
-
-
-assign	FDC_RAM_DATA_R_BIT	=	(BIT_CNT==3'd7)?FDC_RAM_DATA_R[7]:
-								(BIT_CNT==3'd6)?FDC_RAM_DATA_R[6]:
-								(BIT_CNT==3'd5)?FDC_RAM_DATA_R[5]:
-								(BIT_CNT==3'd4)?FDC_RAM_DATA_R[4]:
-								(BIT_CNT==3'd3)?FDC_RAM_DATA_R[3]:
-								(BIT_CNT==3'd2)?FDC_RAM_DATA_R[2]:
-								(BIT_CNT==3'd1)?FDC_RAM_DATA_R[1]:
-												FDC_RAM_DATA_R[0];
-
-
-// 读取
-
-reg		LATCHED_FD_REC1;
-reg		LATCHED_FDC_IO_DATA1;
-reg		GET_FDC_POLLING;
-
-reg		[5:0]		FDC_POLL1_CNT;
-
-reg		[5:0]		GET_FDC_POLL1_CNT;
-
-
-always @(posedge FDC_CLK or negedge RESET_N)
-	if(~RESET_N)
-	begin
-		FDC_DATA_BIT1			<=	1'b0;
-
-		LATCHED_FD_REC1			<=	1'b0;
-		LATCHED_FDC_IO_DATA1	<=	1'b0;
-	end
-	else
-	begin
-		// 磁道记录信号上沿，翻转 DATA_BIT
-		if({LATCHED_FD_REC1, FD_REC1}==2'b01)
-		begin
-			FDC_DATA_BIT1	<=	FDC_POLL1;
-		end
-
-		if(FDC_DATA_SET1)
-			LATCHED_FDC_DATA1	<=	{LATCHED_FDC_DATA1[6:0], FDC_DATA_BIT1};
-
-		// 读取DATA信号上沿
-		if({LATCHED_FDC_IO_DATA1, FDC_IO_DATA}==2'b01)
-		begin
-			FDC_DATA1		<=	LATCHED_FDC_DATA1;
-		end
-
-		LATCHED_FD_REC1			<=	FD_REC1;
-		LATCHED_FDC_IO_DATA1	<=	FDC_IO_DATA;
-	end
-		
-////////////////////////////////////////
-// 物理软驱模拟
-////////////////////////////////////////
-
-//WRITE_REQUEST_N
-(*preserve*)reg	[9:0]	WRITE_DATA_CNT;
-
-assign	FDC_RAM_DATA_W	=	WRITE_DATA1;
-
-// 对写入操作计数
-always @(posedge FDC_CLK or negedge RESET_N)
-begin
-	if(~RESET_N)
-	begin
-		WRITE_DATA_CNT		<=	0;
-	end
-	else
-	begin
-		if( (~FDC_CT[6]) && (FDC_CT[5]==LATCHED_FDC_CT[5]) )
-		begin
-			if(~WRITE_DATA_CNT[9])
-				WRITE_DATA_CNT		<=	WRITE_DATA_CNT+1;
-		end
-		else
-		begin
-			WRITE_DATA_CNT		<=	0;
-		end
-	end
-end
-
-
-// 模拟磁道信号
-
-// 等待第1个写入数据变化
-always @(posedge FDC_CLK or negedge RESET_N)
-	if(~RESET_N)
-	begin
-		WRITE_WAIT_FIRST_OP	<=	1'b0;
-	end
-	else
-	begin
-		if( LATCHED_FDC_CT[6]!=FDC_CT[6] )
-		begin
-			// 信号下拉，开始写入，并等待第1个写入数据变化。
-			WRITE_WAIT_FIRST_OP		<=	({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b10);
-		end
-		else
-		begin
-			// 找到第1个写入数据变化
-			if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && (FDC_CT[5]!=LATCHED_FDC_CT[5]) )
-				WRITE_WAIT_FIRST_OP		<=	1'b0;
-		end
-	end
-
-// 判断是否有写入数据产生
-always @(posedge FDC_CLK or negedge RESET_N)
-	if(~RESET_N)
-	begin
-		WRITE_DATA_MODI1		<=	1'b0;
-	end
-	else
-	begin
-		// 写入信号变化
-		if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && (FDC_CT[5]!=LATCHED_FDC_CT[5]) )
-		begin
-			WRITE_DATA_MODI1		<=	1'b1;
-		end
-		else
-		begin
-			if(FDC_RAM_W)
-				WRITE_DATA_MODI1		<=	1'b0;
-		end
-	end
-
-
-// 判断写入的值
-always @(posedge FDC_CLK or negedge RESET_N)
-	if(~RESET_N)
-	begin
-		WRITE_DATA_BIT_VAL	<=	1'b0;
-	end
-	else
-	begin
-		// 写入信号变化
-		if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && (FDC_CT[5]!=LATCHED_FDC_CT[5]) )
-		begin
-			//	9'h01B 9'h056 9'h072
-			if(WRITE_DATA_CNT==10'h01B)
-			begin
-				WRITE_DATA_BIT_VAL	<=	1'b1;
-			end
-			else
-			begin
-				WRITE_DATA_BIT_VAL	<=	1'b0;
-			end
-		end
-	end
-
-
-// 模拟磁盘数据位
-always @(posedge FDC_CLK or negedge RESET_N)
-begin
-	if(~RESET_N)
-	begin
-		SYNC_CNT			<=	19'b0;
-
-		BIT_CNT				<=	3'd0;
-
-		FDC_RAM_R			<=	1'b0;
-		FDC_RAM_W			<=	1'b0;
-		
-		FDC_DATA_SET1		<=	1'b0;
-
-		FDC_POLL1			<=	1'b0;
-		FDC_POLL2			<=	1'b0;
-
-		FLOPPY_BYTE			<=	12'h000;
-		FLOPPY_SECTOR_BYTE	<=	8'h00;
-		FLOPPY_SECTOR_DELAY	<=	8'h00;
-		FLOPPY_ADDRESS_R	<=	18'b0;
-		FLOPPY_ADDRESS_W	<=	18'b0;
-
-		WRITE_DATA1			<=	8'b0;
-
-		FD_REC1				<=	1'b0;
-		CLK_CNT				<=	7'h00;
-	end
-	else
-	begin
-		begin
-			if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && (FDC_CT[5]!=LATCHED_FDC_CT[5]) && WRITE_DATA_CNT[9] )
-			begin
-				// INIT 磁道空白区，约1/10圈空白。
-				// 找到第1个时钟位
-				BIT_CNT					<=	3'd7;
-
-				// 下一个需要读取的位置
-				FLOPPY_BYTE				<=	12'h001;
-				FLOPPY_SECTOR_BYTE		<=	8'h00;
-
-				FLOPPY_ADDRESS_R		<=	{TRACK, 4'b0};
-				SYNC_CNT				<=	19'b0;
-				FDC_RAM_R				<=	1'b1;
-
-				FDC_RAM_W				<=	1'b0;
-
-				FDC_DATA_SET1			<=	1'b0;
-
-				FD_REC1					<=	1'b1;
-				FDC_POLL1				<=	1'b0;
-				FDC_POLL2				<=	1'b0;
-				CLK_CNT					<=	7'h03;
-			end
-			else
-			begin
-				if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && (FDC_CT[5]!=LATCHED_FDC_CT[5]) && WRITE_DATA_CNT==10'h02F )
-				begin
-					// 格式化时，数据区之前无空白。数据存盘时，写入数据区留有50个左右的时钟周期空白。
-					// 写入扇区定位，写入扇区前有约0x28个时钟周期的空白。
-					FDC_RAM_W				<=	1'b0;
-
-					FDC_DATA_SET1			<=	1'b0;
-
-					FD_REC1					<=	1'b1;
-					FDC_POLL1				<=	1'b0;
-					FDC_POLL2				<=	1'b0;
-					CLK_CNT					<=	7'h03;
-				end
-				else
-				begin
-					case(CLK_CNT)
-					7'h00:	// 同步信号 324 * 8 * 0x70 = 290304
-						begin
-							FD_REC1			<=	1'b0;
-							SYNC_CNT		<=	SYNC_CNT+1;
-
-							FDC_RAM_R		<=	1'b0;
-							FDC_RAM_W		<=	1'b0;
-
-							if(SYNC_CNT[18])
-							//if(SYNC_CNT[10])
-							begin
-								CLK_CNT		<=	CLK_CNT + 1;
-							end
-						end
-
-					7'h01:
-						begin
-							FDC_RAM_R	<=	1'b0;
-							FDC_RAM_W	<=	1'b0;
-
-							// 如果是写入，等待时钟沿的变化
-							if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && ({LATCHED_FDC_CT[5],FDC_CT[5]}==2'b01) )
-							begin
-								CLK_CNT			<=	CLK_CNT;
-							end
-							else
-							begin
-								CLK_CNT			<=	CLK_CNT + 1;
-							end
-						end
-
-					// CLOCK DOMAIN
-					7'h02:
-						begin
-							BIT_CNT				<=	BIT_CNT-1;
-
-							// 读取
-							if(BIT_CNT==3'd0)
-							begin
-								begin
-									FLOPPY_BYTE			<=	FLOPPY_BYTE + 1'b1;
-
-									FLOPPY_ADDRESS_R	<=	{TRACK, 4'b0} + {6'b000000, FLOPPY_BYTE};
-								end
-
-								FDC_RAM_R		<=	1'b1;
-							end
-
-							FD_REC1				<=	1'b1;
-
-							CLK_CNT				<=	CLK_CNT + 1;
-						end
-
-
-					// POOLING
-					// 从读取POLLING成功（值为1），到读取DATA中间间隔了0x43 个时钟周期。
-					7'h03:
-						begin
-							FDC_RAM_R			<=	1'b0;
-							FDC_RAM_W			<=	1'b0;
-
-							FDC_POLL1			<=	1'b1;
-							FDC_POLL2			<=	1'b1;
-							CLK_CNT				<=	CLK_CNT + 1;
-						end
-
-					7'h06:	// 1us
-						begin
-							FD_REC1			<=	1'b0;
-							CLK_CNT			<=	CLK_CNT + 1;
-						end
-
-					// DATA DOMAIN
-					7'h1E:
-						begin
-							FD_REC1			<=	FDC_RAM_DATA_R_BIT;
-							CLK_CNT			<=	CLK_CNT + 1;
-						end
-
-					7'h1F:
-						begin
-							FDC_DATA_SET1	<=	1'b1;
-							CLK_CNT			<=	CLK_CNT + 1;
-						end
-
-					7'h20:
-						begin
-							FDC_DATA_SET1	<=	1'b0;
-							CLK_CNT			<=	CLK_CNT + 1;
-						end
-
-					7'h22:
-						begin
-							FD_REC1			<=	1'b0;
-							CLK_CNT			<=	CLK_CNT + 1;
-						end
-
-					7'h25:
-						begin
-							FDC_POLL1		<=	1'b0;
-							FDC_POLL2		<=	1'b0;
-							CLK_CNT			<=	CLK_CNT + 1;
-						end
-
-					// 扇区结束延时
-					7'h70:
-						begin
-							// 写入
-							WRITE_DATA1		<=	{WRITE_DATA1[6:0],WRITE_DATA_BIT_VAL};
-
-							if(BIT_CNT==3'd0)
-							begin
-								FLOPPY_ADDRESS_W	<=	FLOPPY_ADDRESS_R;
-								FDC_RAM_W			<=	WRITE_DATA_MODI1;
-							end
-
-							CLK_CNT			<=	CLK_CNT + 1;
-						end
-
-					7'h71:
-						begin
-							// 写入结束
-							FDC_RAM_W			<=	1'b0;
-
-							FDC_SIG_CLK			<=	WRITE_DATA_MODI1;
-
-							// 扇区结束时的延时
-							if(BIT_CNT==3'd0 && FLOPPY_SECTOR_BYTE==8'h99)
-							begin
-								FLOPPY_SECTOR_DELAY	<=	8'hA5;
-							end
-							else
-							begin
-								FLOPPY_SECTOR_DELAY	<=	8'h00;
-							end
-
-							CLK_CNT			<=	CLK_CNT + 1;
-						end
-
-					// 扇区结束时的延时
-					7'h72:
-						begin
-							FDC_SIG_CLK			<=	1'b0;
-
-							// 扇区结束时的延时
-							if(FLOPPY_SECTOR_DELAY==8'h00)
-							begin
-								CLK_CNT		<=	CLK_CNT + 1;
-							end
-							else
-							begin
-								FLOPPY_SECTOR_DELAY	<=	FLOPPY_SECTOR_DELAY-1;
-							end
-						end
-
-					7'h73:
-						begin
-							if(BIT_CNT==3'd0)
-							begin
-								if(FLOPPY_BYTE==`FD_TRACK_LEN||FLOPPY_SECTOR_BYTE==8'h99)
-								begin
-									FLOPPY_SECTOR_BYTE	<=	8'h00;
-								end
-								else
-								begin
-									FLOPPY_SECTOR_BYTE	<=	FLOPPY_SECTOR_BYTE+1;
-								end
-							end
-
-							if(BIT_CNT==3'd0 && FLOPPY_BYTE==`FD_TRACK_LEN)
-							begin
-								FLOPPY_BYTE			<=	12'h000;
-								//FLOPPY_SECTOR_BYTE	<=	8'h00;
-
-								FLOPPY_ADDRESS_R	<=	{TRACK, 4'b0};
-								SYNC_CNT			<=	19'b0;
-
-								CLK_CNT				<=	7'h00;
-							end
-							else
-							begin
-								CLK_CNT		<=	7'h01;
-							end
-						end
-
-					default:
-						begin
-							FDC_RAM_R	<=	1'b0;
-							FDC_RAM_W	<=	1'b0;
-							CLK_CNT		<=	CLK_CNT + 1;
-						end
-					endcase
-				end
-			end
-		end
-	end
-end
-
-
-always @(posedge FDC_CLK or negedge RESET_N)
-begin
-	if(~RESET_N)
-	begin
-		PHASE0	<=	1'b0;
-		PHASE1	<=	1'b0;
-		PHASE2	<=	1'b0;
-		PHASE3	<=	1'b0;
-		MOTOR	<=	1'b0;
-		DRIVE1	<=	1'b0;
-		DRIVE2	<=	1'b0;
-		WRITE_REQUEST_N	<=	1'b1;
-		WRITE_DATA_BIT	<=	1'b0;
-	end
-	else
-	begin
-		PHASE0	<=	FDC_CT[0];
-		PHASE1	<=	FDC_CT[1];
-		PHASE2	<=	FDC_CT[2];
-		PHASE3	<=	FDC_CT[3];
-		DRIVE1	<=	FDC_CT[4];
-		DRIVE2	<=	FDC_CT[7];
-		MOTOR	<=	(FDC_CT[4])|(FDC_CT[7]);
-		WRITE_REQUEST_N	<=	FDC_CT[6];
-		WRITE_DATA_BIT	<=	FDC_CT[5];
-	end
-end
-
-//assign DRIVE1_X =  DRIVE1 & MOTOR;
-//assign DRIVE2_X = !DRIVE1 & MOTOR;
-
-assign DRIVE1_X =	DRIVE1 & MOTOR;
-assign DRIVE2_X =	DRIVE2 & MOTOR;
-
-assign DRIVE1_FLOPPY_WP	=	~SW[0];
-assign DRIVE2_FLOPPY_WP	=	~SW[1];
-
-assign FDC_WP	=	DRIVE1?DRIVE1_FLOPPY_WP:
-					DRIVE2?DRIVE2_FLOPPY_WP:
-					1'b1;
-
-
-assign DRIVE1_EN =	(DRIVE1) & MOTOR;
-assign DRIVE2_EN =	(DRIVE2) & MOTOR;
-
-
-assign TRACK		=	(DRIVE1_EN)		?	{1'b0,TRACK1}:
-						(DRIVE2_EN)		?	{1'b1,TRACK2}:
-											14'b0;
-
-assign TRACK1_UP	= TRACK1 + `FD_TRACK_STEP;
-assign TRACK1_DOWN	= TRACK1 - `FD_TRACK_STEP;
-assign TRACK2_UP	= TRACK2 + `FD_TRACK_STEP;
-assign TRACK2_DOWN	= TRACK2 - `FD_TRACK_STEP;
-
-
-//assign FLOPPY_ADDRESS_R = {TRACK, 4'b0} + {5'b00000, FLOPPY_BYTE};
-
-
-//always @ (posedge PH_2)
-always @(negedge FDC_CLK)
-begin
-	PHASE0_1 <= PHASE0;
-	PHASE0_2 <= PHASE0_1;					// Delay 2 clock cycles
-	PHASE1_1 <= PHASE1;
-	PHASE1_2 <= PHASE1_1;					// Delay 2 clock cycles
-	PHASE2_1 <= PHASE2;
-	PHASE2_2 <= PHASE2_1;					// Delay 2 clock cycles
-	PHASE3_1 <= PHASE3;
-	PHASE3_2 <= PHASE3_1;					// Delay 2 clock cycles
-end
-
-always @(posedge FDC_CLK or negedge RESET_N)
-begin
-	if(~RESET_N)
-	begin
-		STEPPER1	<=	2'b00;
-		STEPPER2	<=	2'b00;
-		TRACK1		<=	13'd0;
-		TRACK2		<=	13'd0;
-
-		TRACK1_NO	<=	8'd0;
-		TRACK2_NO	<=	8'd0;
-	end
-	else
-	begin
-//		if(DRIVE1^DRIVE_SWAP)
-		if(DRIVE1)
-		begin
-			case ({PHASE0_2, PHASE1_2, PHASE2_2, PHASE3_2})
-			4'b1000:
-			begin
-				if(STEPPER1 == 2'b11)
-				begin
-					//if(TRACK1 != `FD_MAX_LEN)
-					if(TRACK1_NO != `FD_MAX_TRACK_NO)
-					begin
-						TRACK1 <= TRACK1_UP;
-						TRACK1_NO <= TRACK1_NO+1;
-						STEPPER1 <= 2'b00;
-					end
-				end
-				else
-				if(STEPPER1 == 2'b01)
-				begin
-					//if(TRACK1 != 17'h0)
-					if(TRACK1_NO != 8'd0)
-					begin
-						TRACK1 <= TRACK1_DOWN;
-						TRACK1_NO <= TRACK1_NO-1;
-						STEPPER1 <= 2'b00;
-					end
-				end
-			end
-			4'b0100:
-			begin
-				if(STEPPER1 == 2'b00)
-				begin
-					//if(TRACK1 != `FD_MAX_LEN)
-					if(TRACK1_NO != `FD_MAX_TRACK_NO)
-					begin
-						TRACK1 <= TRACK1_UP;
-						TRACK1_NO <= TRACK1_NO+1;
-						STEPPER1 <= 2'b01;
-					end
-				end
-				else
-				if(STEPPER1 == 2'b10)
-				begin
-					//if(TRACK1 != 17'h0)
-					if(TRACK1_NO != 8'd0)
-					begin
-						TRACK1 <= TRACK1_DOWN;
-						TRACK1_NO <= TRACK1_NO-1;
-						STEPPER1 <= 2'b01;
-					end
-				end
-			end
-			4'b0010:
-			begin
-				if(STEPPER1 == 2'b01)
-				begin
-					//if(TRACK1 != `FD_MAX_LEN)
-					if(TRACK1_NO != `FD_MAX_TRACK_NO)
-					begin
-						TRACK1 <= TRACK1_UP;
-						TRACK1_NO <= TRACK1_NO+1;
-						STEPPER1 <= 2'b10;
-					end
-				end
-				else
-				if(STEPPER1 == 2'b11)
-				begin
-					//if(TRACK1 != 17'h0)
-					if(TRACK1_NO != 8'd0)
-					begin
-						TRACK1 <= TRACK1_DOWN;
-						TRACK1_NO <= TRACK1_NO-1;
-						STEPPER1 <= 2'b10;
-					end
-				end
-			end
-			4'b0001:
-			begin
-				if(STEPPER1 == 2'b10)
-				begin
-					//if(TRACK1 != `FD_MAX_LEN)
-					if(TRACK1_NO != `FD_MAX_TRACK_NO)
-					begin
-						TRACK1 <= TRACK1_UP;
-						TRACK1_NO <= TRACK1_NO+1;
-						STEPPER1 <= 2'b11;
-					end
-				end
-				else
-				if(STEPPER1 == 2'b00)
-				begin
-					//if(TRACK1 != 17'h0)
-					if(TRACK1_NO != 8'd0)
-					begin
-						TRACK1 <= TRACK1_DOWN;
-						TRACK1_NO <= TRACK1_NO-1;
-						STEPPER1 <= 2'b11;
-					end
-				end
-			end
-			endcase
-		end
-
-		else
-
-		begin
-			case ({PHASE0_2, PHASE1_2, PHASE2_2, PHASE3_2})
-			4'b1000:
-			begin
-				if(STEPPER2 == 2'b11)
-				begin
-					//if(TRACK2 != `FD_MAX_LEN)
-					if(TRACK2_NO != `FD_MAX_TRACK_NO)
-					begin
-						TRACK2 <= TRACK2_UP;
-						TRACK2_NO <= TRACK2_NO+1;
-						STEPPER2 <= 2'b00;
-					end
-				end
-				else
-				if(STEPPER2 == 2'b01)
-				begin
-					//if(TRACK2 != 17'h0)
-					if(TRACK2_NO != 8'd0)
-					begin
-						TRACK2 <= TRACK2_DOWN;
-						TRACK2_NO <= TRACK2_NO-1;
-						STEPPER2 <= 2'b00;
-					end
-				end
-			end
-			4'b0100:
-			begin
-				if(STEPPER2 == 2'b00)
-				begin
-					//if(TRACK2 != `FD_MAX_LEN)
-					if(TRACK2_NO != `FD_MAX_TRACK_NO)
-					begin
-						TRACK2 <= TRACK2_UP;
-						TRACK2_NO <= TRACK2_NO+1;
-						STEPPER2 <= 2'b01;
-					end
-				end
-				else
-				if(STEPPER2 == 2'b10)
-				begin
-					//if(TRACK2 != 17'h0)
-					if(TRACK2_NO != 8'd0)
-					begin
-						TRACK2 <= TRACK2_DOWN;
-						TRACK2_NO <= TRACK2_NO-1;
-						STEPPER2 <= 2'b01;
-					end
-				end
-			end
-			4'b0010:
-			begin
-				if(STEPPER2 == 2'b01)
-				begin
-					//if(TRACK2 != `FD_MAX_LEN)
-					if(TRACK2_NO != `FD_MAX_TRACK_NO)
-					begin
-						TRACK2 <= TRACK2_UP;
-						TRACK2_NO <= TRACK2_NO+1;
-						STEPPER2 <= 2'b10;
-					end
-				end
-				else
-				if(STEPPER2 == 2'b11)
-				begin
-					//if(TRACK2 != 17'h0)
-					if(TRACK2_NO != 8'd0)
-					begin
-						TRACK2 <= TRACK2_DOWN;
-						TRACK2_NO <= TRACK2_NO-1;
-						STEPPER2 <= 2'b10;
-					end
-				end
-			end
-			4'b0001:
-			begin
-				if(STEPPER2 == 2'b10)
-				begin
-					//if(TRACK2 != `FD_MAX_LEN)
-					if(TRACK2_NO != `FD_MAX_TRACK_NO)
-					begin
-						TRACK2 <= TRACK2_UP;
-						TRACK2_NO <= TRACK2_NO+1;
-						STEPPER2 <= 2'b11;
-					end
-				end
-				else
-				if(STEPPER2 == 2'b00)
-				begin
-					//if(TRACK2 != 17'h0)
-					if(TRACK2_NO != 8'd0)
-					begin
-						TRACK2 <= TRACK2_DOWN;
-						TRACK2_NO <= TRACK2_NO-1;
-						STEPPER2 <= 2'b11;
-					end
-				end
-			end
-			endcase
-		end
-	end
-end
-
-
-
-reg	[19:0]	LATCHED_FDC_CNT_CT;
-reg	[7:0]	LATCHED_FDC_CT;
-
-
-always @(posedge FDC_CLK or negedge RESET_N)
-begin
-	if(~RESET_N)
-	begin
-		LATCHED_FDC_CT		<=	8'hFF;
-		//FDC_SIG_CLK			<=	1'b0;
-		LATCHED_FDC_CNT_CT	<=	20'hFFFFF;
-	end
-	else
-	begin
-		LATCHED_FDC_CT		<=	FDC_CT;
-		LATCHED_FDC_CNT_CT	<=	FDC_CNT_CT;
-		//FDC_SIG_CLK			<=	(LATCHED_FDC_CT!=FDC_CT);
-	end
-end
-
-assign FDC_SIG = (FDC_CNT[7]|FDC_CNT_POLL[7]|FDC_CNT_DATA[7]|FDC_CNT_CT[19]|(LATCHED_FDC_CNT_CT==0));
-
-
-endmodule 
diff --git a/Computer_MiST/Laser310_MiST/rtl/mc6847_vga.v b/Computer_MiST/Laser310_MiST/rtl/mc6847_vga.v
deleted file mode 100644
index 9b638ead..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/mc6847_vga.v
+++ /dev/null
@@ -1,199 +0,0 @@
-// LASER310 VZ200
-// mc6847
-
-module MC6847_VGA(
-PIX_CLK,
-RESET_N,
-
-RD,
-DD,
-DA,
-
-AG,
-AS,
-EXT,
-INV,
-GM,
-CSS,
-
-// vga
-blank,
-VGA_OUT_HSYNC,
-VGA_OUT_VSYNC,
-VGA_OUT_RED,
-VGA_OUT_GREEN,
-VGA_OUT_BLUE
-);
-
-input			PIX_CLK;
-input			RESET_N;
-
-output	wire			RD;
-output	wire	[12:0]	DA;		// 8KB
-input			[7:0]	DD;
-input					AG;
-input					AS;
-input					EXT;
-input					INV;
-input					CSS;
-input			[2:0]	GM;
-output	wire			blank;
-output	wire			VGA_OUT_HSYNC;
-output	wire			VGA_OUT_VSYNC;
-output	wire	[7:0]	VGA_OUT_RED;
-output	wire	[7:0]	VGA_OUT_GREEN;
-output	wire	[7:0]	VGA_OUT_BLUE;
-
-
-reg				LATCHED_AG;
-reg				LATCHED_AS;
-reg				LATCHED_EXT;
-reg				LATCHED_INV;
-reg		[2:0]	LATCHED_GM;
-reg				LATCHED_CSS;
-
-wire			pixel_clock;				// generated from SYSTEM CLOCK
-wire			reset;						// reset asserted when DCMs are NOT LOCKED
-
-wire	[7:0]	vga_red;				// red video data
-wire	[7:0]	vga_green;				// green video data
-wire	[7:0]	vga_blue;				// blue video data
-
-// internal video timing signals
-wire 			h_synch;					// horizontal synch for VGA connector
-wire 			v_synch;					// vertical synch for VGA connector
-//wire 			blank;						// composite blanking
-wire	[10:0]	pixel_count;				// bit mapped pixel position within the line
-wire	[9:0]	line_count;					// bit mapped line number in a frame lines within the frame
-
-wire			show_border;
-
-// text
-wire	[3:0]	subchar_pixel;				// pixel position within the character
-wire	[4:0]	subchar_line;				// identifies the line number within a character block
-wire	[6:0]	char_column;				// character number on the current line
-wire	[6:0]	char_line;					// line number on the screen
-
-// graph
-wire	[8:0]	graph_pixel;				// pixel number on the current line
-wire	[9:0]	graph_line_2x;				// line number on the screen
-wire	[9:0]	graph_line_3x;				// line number on the screen
-
-/*
-wire	[11:0]	ROM_ADDRESS;
-wire	[7:0]	ROM_DATA;
-*/
-
-assign	reset = ~RESET_N;
-assign	pixel_clock = PIX_CLK;
-
-//assign	vga_red = 8'hff;
-//assign	vga_green = 8'h7f;
-//assign	vga_blue = 8'h7f;
-
-// Character generator
-/*
-char_rom_4k_altera char_rom(
-	.address(ROM_ADDRESS),
-	.clock(pixel_clock),
-	.q(ROM_DATA)
-);
-*/
-
-// 为了防止闪屏，再垂直回扫信号产生时，锁存模式信号。
-
-always @ (posedge v_synch or negedge RESET_N)
-begin
-	if(!RESET_N)
-	begin
-		LATCHED_AG		<=	1'b0;
-		LATCHED_AS		<=	1'b0;
-		LATCHED_EXT		<=	1'b0;
-		LATCHED_INV		<=	1'b0;
-		LATCHED_GM		<=	3'b0;
-		LATCHED_CSS		<=	1'b0;
-	end
-	else
-	begin
-		LATCHED_AG <= AG;
-		LATCHED_AS <= AS;
-		LATCHED_EXT <= EXT;
-		LATCHED_INV <= INV;
-		LATCHED_GM <= GM;
-		LATCHED_CSS <= CSS;
-	end
-end
-
-// instantiate the character generator
-PIXEL_DISPLAY PIXEL_DISPLAY(
-	.pixel_clock(pixel_clock),
-	.reset(reset),
-	.show_border(show_border),
-	// mode
-	.ag(LATCHED_AG),
-	.gm(LATCHED_GM),
-	.css(LATCHED_CSS),
-	// text
-	.char_column(char_column),
-	.char_line(char_line),
-	.subchar_line(subchar_line),
-	.subchar_pixel(subchar_pixel),
-	// graph
-	.graph_pixel(graph_pixel),
-	.graph_line_2x(graph_line_2x),
-	.graph_line_3x(graph_line_3x),
-	// vram
-	.vram_rd_enable(RD),
-	.vram_addr(DA),
-	.vram_data(DD),
-	// vga
-	.vga_red(vga_red),
-	.vga_green(vga_green),
-	.vga_blue(vga_blue)
-);
-
-// instantiate the video timing generator
-SVGA_TIMING_GENERATION SVGA_TIMING_GENERATION
-(
-	pixel_clock,
-	reset,
-	h_synch,
-	v_synch,
-	blank,
-	pixel_count,
-	line_count,
-
-	show_border,
-
-	// text
-	subchar_pixel,
-	subchar_line,
-	char_column,
-	char_line,
-
-	// graph
-	graph_pixel,
-	graph_line_2x,
-	graph_line_3x
-);
-
-// instantiate the video output mux
-VIDEO_OUT VIDEO_OUT
-(
-	pixel_clock,
-	reset,
-	vga_red,
-	vga_green,
-	vga_blue,
-	h_synch,
-	v_synch,
-	blank,
-
-	VGA_OUT_HSYNC,
-	VGA_OUT_VSYNC,
-	VGA_OUT_RED,
-	VGA_OUT_GREEN,
-	VGA_OUT_BLUE
-);
-
-endmodule
diff --git a/Computer_MiST/Laser310_MiST/rtl/pll.qip b/Computer_MiST/Laser310_MiST/rtl/pll.qip
deleted file mode 100644
index 48665362..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/pll.qip
+++ /dev/null
@@ -1,4 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Computer_MiST/Laser310_MiST/rtl/pll.vhd b/Computer_MiST/Laser310_MiST/rtl/pll.vhd
deleted file mode 100644
index 7194c647..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/pll.vhd
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2014 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 27,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 50,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 27,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 25,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 27,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 10,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 108,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 25,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "108"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "10.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.250000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "10"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "25"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "10.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.25000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "10"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "108"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "25"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Computer_MiST/Laser310_MiST/rtl/reset_de.v b/Computer_MiST/Laser310_MiST/rtl/reset_de.v
deleted file mode 100644
index fd26e271..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/reset_de.v
+++ /dev/null
@@ -1,59 +0,0 @@
-module RESET_DE(
-	CLK,			// 50MHz
-	SYS_RESET_N,
-	RESET_N,		// 50MHz/32/65536
-	RESET_AHEAD_N	// 提前恢复，可以接 FLASH_RESET_N
-);
-
-
-input				CLK;
-input				SYS_RESET_N;
-output				RESET_N;
-output				RESET_AHEAD_N;
-
-
-wire	RESET_N;
-wire	RESET_AHEAD_N;
-
-reg		[5:0]		CLK_CNT;
-reg		[16:0]		RESET_COUNT;
-
-wire	RESET_COUNT_CLK;
-wire	RESET_DE_N;
-wire	RESET_AHEAD_DE_N;
-
-assign RESET_COUNT_CLK = CLK_CNT[5];
-
-assign RESET_DE_N = RESET_COUNT[16]!=1'b0;
-assign RESET_N = SYS_RESET_N && RESET_DE_N;
-
-assign RESET_AHEAD_DE_N = RESET_COUNT[16:15]!=2'b00;
-assign RESET_AHEAD_N = SYS_RESET_N && RESET_AHEAD_DE_N;
-
-`ifdef SIMULATE
-initial
-	begin
-		CLK_CNT = 6'b0;
-	end
-`endif
-
-// 50MHz/32 = 1.5625MHz
-always @ (posedge CLK)
-	CLK_CNT <= CLK_CNT+1;
-
-// 50MHz/32/65536 = 23.84HZ
-always @ (posedge RESET_COUNT_CLK or negedge SYS_RESET_N)
-begin
-	if(~SYS_RESET_N)
-	begin
-		RESET_COUNT <= 17'h00000;
-	end
-	else
-	begin
-		if(RESET_COUNT!=17'h10000)
-			RESET_COUNT <= RESET_COUNT+1;
-
-	end
-end
-
-endmodule
diff --git a/Computer_MiST/Laser310_MiST/rtl/roms/boot_rom_6000.mif b/Computer_MiST/Laser310_MiST/rtl/roms/boot_rom_6000.mif
deleted file mode 100644
index a60543fb..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/roms/boot_rom_6000.mif
+++ /dev/null
@@ -1,122 +0,0 @@
-DEPTH = 115;
-WIDTH = 8;
-ADDRESS_RADIX = HEX;
-DATA_RADIX = HEX;
-CONTENT
-BEGIN
-0000:AA;
-0001:55;
-0002:E7;
-0003:18;
-0004:AF;
-0005:2A;
-0006:00;
-0007:C0;
-0008:11;
-0009:00;
-000A:80;
-000B:ED;
-000C:52;
-000D:30;
-000E:63;
-000F:3A;
-0010:02;
-0011:C0;
-0012:FE;
-0013:56;
-0014:20;
-0015:18;
-0016:3A;
-0017:03;
-0018:C0;
-0019:FE;
-001A:5A;
-001B:20;
-001C:55;
-001D:3A;
-001E:04;
-001F:C0;
-0020:FE;
-0021:46;
-0022:20;
-0023:4E;
-0024:3A;
-0025:05;
-0026:C0;
-0027:FE;
-0028:20;
-0029:20;
-002A:47;
-002B:C3;
-002C:B7;
-002D:17;
-002E:FE;
-002F:20;
-0030:20;
-0031:40;
-0032:3A;
-0033:03;
-0034:C0;
-0035:FE;
-0036:20;
-0037:20;
-0038:39;
-0039:3A;
-003A:04;
-003B:C0;
-003C:FE;
-003D:00;
-003E:20;
-003F:32;
-0040:3A;
-0041:05;
-0042:C0;
-0043:FE;
-0044:00;
-0045:20;
-0046:2B;
-0047:3A;
-0048:17;
-0049:C0;
-004A:FE;
-004B:F0;
-004C:28;
-004D:07;
-004E:3A;
-004F:17;
-0050:C0;
-0051:FE;
-0052:F1;
-0053:20;
-0054:1D;
-0055:AF;
-0056:2A;
-0057:00;
-0058:C0;
-0059:11;
-005A:18;
-005B:00;
-005C:ED;
-005D:52;
-005E:44;
-005F:4D;
-0060:21;
-0061:1A;
-0062:C0;
-0063:ED;
-0064:5B;
-0065:18;
-0066:C0;
-0067:ED;
-0068:B0;
-0069:AF;
-006A:3E;
-006B:00;
-006C:D3;
-006D:70;
-006E:2A;
-006F:18;
-0070:C0;
-0071:E9;
-0072:76;
-END;
diff --git a/Computer_MiST/Laser310_MiST/rtl/roms/cass_ram.mif b/Computer_MiST/Laser310_MiST/rtl/roms/cass_ram.mif
deleted file mode 100644
index 1a8f22b4..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/roms/cass_ram.mif
+++ /dev/null
@@ -1,1313 +0,0 @@
-DEPTH = 1306;
-WIDTH = 8;
-ADDRESS_RADIX = HEX;
-DATA_RADIX = HEX;
-CONTENT
-BEGIN
-0000:17;
-0001:05;
-0002:8F;
-0003:80;
-0004:80;
-0005:80;
-0006:80;
-0007:80;
-0008:80;
-0009:80;
-000A:80;
-000B:80;
-000C:80;
-000D:80;
-000E:80;
-000F:80;
-0010:80;
-0011:80;
-0012:80;
-0013:80;
-0014:80;
-0015:80;
-0016:80;
-0017:80;
-0018:80;
-0019:80;
-001A:80;
-001B:80;
-001C:80;
-001D:80;
-001E:80;
-001F:80;
-0020:80;
-0021:80;
-0022:80;
-0023:80;
-0024:80;
-0025:80;
-0026:80;
-0027:80;
-0028:80;
-0029:80;
-002A:80;
-002B:80;
-002C:80;
-002D:80;
-002E:80;
-002F:80;
-0030:80;
-0031:80;
-0032:80;
-0033:80;
-0034:80;
-0035:80;
-0036:80;
-0037:80;
-0038:80;
-0039:80;
-003A:80;
-003B:80;
-003C:80;
-003D:80;
-003E:80;
-003F:80;
-0040:80;
-0041:80;
-0042:80;
-0043:80;
-0044:80;
-0045:80;
-0046:80;
-0047:80;
-0048:80;
-0049:80;
-004A:80;
-004B:80;
-004C:80;
-004D:80;
-004E:80;
-004F:80;
-0050:80;
-0051:80;
-0052:80;
-0053:80;
-0054:80;
-0055:80;
-0056:80;
-0057:80;
-0058:80;
-0059:80;
-005A:80;
-005B:80;
-005C:80;
-005D:80;
-005E:80;
-005F:80;
-0060:80;
-0061:80;
-0062:80;
-0063:80;
-0064:80;
-0065:80;
-0066:80;
-0067:80;
-0068:80;
-0069:80;
-006A:80;
-006B:80;
-006C:80;
-006D:80;
-006E:80;
-006F:80;
-0070:80;
-0071:80;
-0072:80;
-0073:80;
-0074:80;
-0075:80;
-0076:80;
-0077:80;
-0078:80;
-0079:80;
-007A:80;
-007B:80;
-007C:80;
-007D:80;
-007E:80;
-007F:80;
-0080:80;
-0081:80;
-0082:80;
-0083:FE;
-0084:FE;
-0085:FE;
-0086:FE;
-0087:FE;
-0088:F1;
-0089:50;
-008A:31;
-008B:2E;
-008C:35;
-008D:43;
-008E:00;
-008F:04;
-0090:7B;
-0091:75;
-0092:7F;
-0093:21;
-0094:74;
-0095:7F;
-0096:11;
-0097:A6;
-0098:79;
-0099:01;
-009A:55;
-009B:00;
-009C:ED;
-009D:B8;
-009E:11;
-009F:7D;
-00A0:78;
-00A1:01;
-00A2:21;
-00A3:00;
-00A4:ED;
-00A5:B8;
-00A6:11;
-00A7:9C;
-00A8:7A;
-00A9:01;
-00AA:64;
-00AB:00;
-00AC:ED;
-00AD:B8;
-00AE:ED;
-00AF:5B;
-00B0:B1;
-00B1:78;
-00B2:01;
-00B3:35;
-00B4:01;
-00B5:ED;
-00B6:B8;
-00B7:ED;
-00B8:53;
-00B9:9E;
-00BA:79;
-00BB:01;
-00BC:58;
-00BD:00;
-00BE:ED;
-00BF:B8;
-00C0:ED;
-00C1:53;
-00C2:86;
-00C3:79;
-00C4:01;
-00C5:7D;
-00C6:00;
-00C7:ED;
-00C8:B8;
-00C9:ED;
-00CA:53;
-00CB:A7;
-00CC:79;
-00CD:01;
-00CE:DC;
-00CF:00;
-00D0:ED;
-00D1:B8;
-00D2:00;
-00D3:ED;
-00D4:53;
-00D5:B1;
-00D6:78;
-00D7:13;
-00D8:ED;
-00D9:53;
-00DA:5E;
-00DB:78;
-00DC:21;
-00DD:CE;
-00DE:FF;
-00DF:19;
-00E0:22;
-00E1:A0;
-00E2:78;
-00E3:2B;
-00E4:F9;
-00E5:21;
-00E6:54;
-00E7:7A;
-00E8:22;
-00E9:D1;
-00EA:79;
-00EB:21;
-00EC:6B;
-00ED:79;
-00EE:22;
-00EF:BC;
-00F0:79;
-00F1:3E;
-00F2:C3;
-00F3:32;
-00F4:BB;
-00F5:79;
-00F6:21;
-00F7:E9;
-00F8:7A;
-00F9:22;
-00FA:A4;
-00FB:78;
-00FC:CD;
-00FD:4A;
-00FE:1B;
-00FF:21;
-0100:86;
-0101:7B;
-0102:CD;
-0103:A7;
-0104:28;
-0105:CD;
-0106:F9;
-0107:20;
-0108:21;
-0109:94;
-010A:7B;
-010B:CD;
-010C:A7;
-010D:28;
-010E:CD;
-010F:F9;
-0110:20;
-0111:C3;
-0112:19;
-0113:1A;
-0114:00;
-0115:4C;
-0116:41;
-0117:53;
-0118:45;
-0119:52;
-011A:20;
-011B:32;
-011C:30;
-011D:30;
-011E:2D;
-011F:33;
-0120:31;
-0121:30;
-0122:00;
-0123:42;
-0124:41;
-0125:53;
-0126:49;
-0127:43;
-0128:20;
-0129:20;
-012A:50;
-012B:31;
-012C:2E;
-012D:35;
-012E:43;
-012F:20;
-0130:20;
-0131:20;
-0132:20;
-0133:20;
-0134:20;
-0135:20;
-0136:20;
-0137:20;
-0138:20;
-0139:20;
-013A:20;
-013B:20;
-013C:20;
-013D:20;
-013E:20;
-013F:20;
-0140:20;
-0141:20;
-0142:20;
-0143:00;
-0144:20;
-0145:55;
-0146:BD;
-0147:07;
-0148:B7;
-0149:33;
-014A:52;
-014B:4F;
-014C:4E;
-014D:07;
-014E:A7;
-014F:33;
-0150:52;
-0151:4F;
-0152:46;
-0153:46;
-0154:07;
-0155:A8;
-0156:23;
-0157:45;
-0158:4C;
-0159:07;
-015A:B6;
-015B:21;
-015C:59;
-015D:45;
-015E:07;
-015F:AE;
-0160:32;
-0161:50;
-0162:45;
-0163:45;
-0164:44;
-0165:07;
-0166:14;
-0167:31;
-0168:45;
-0169:4E;
-016A:55;
-016B:4D;
-016C:07;
-016D:15;
-016E:2F;
-016F:53;
-0170:54;
-0171:07;
-0172:C5;
-0173:2C;
-0174:45;
-0175:52;
-0176:47;
-0177:45;
-0178:07;
-0179:17;
-017A:2B;
-017B:4F;
-017C:4D;
-017D:45;
-017E:4D;
-017F:07;
-0180:1C;
-0181:22;
-0182:41;
-0183:4C;
-0184:4C;
-0185:07;
-0186:18;
-0187:32;
-0188:41;
-0189:56;
-018A:45;
-018B:07;
-018C:1D;
-018D:31;
-018E:53;
-018F:54;
-0190:07;
-0191:19;
-0192:2F;
-0193:4F;
-0194:50;
-0195:07;
-0196:1A;
-0197:31;
-0198:45;
-0199:53;
-019A:55;
-019B:4D;
-019C:45;
-019D:07;
-019E:1B;
-019F:2F;
-01A0:4C;
-01A1:4F;
-01A2:41;
-01A3:44;
-01A4:07;
-01A5:16;
-01A6:2E;
-01A7:4E;
-01A8:45;
-01A9:52;
-01AA:52;
-01AB:07;
-01AC:85;
-01AD:23;
-01AE:45;
-01AF:46;
-01B0:44;
-01B1:42;
-01B2:4C;
-01B3:07;
-01B4:9B;
-01B5:23;
-01B6:45;
-01B7:46;
-01B8:D8;
-01B9:07;
-01BA:99;
-01BB:23;
-01BC:45;
-01BD:46;
-01BE:53;
-01BF:54;
-01C0:52;
-01C1:07;
-01C2:AA;
-01C3:23;
-01C4:45;
-01C5:46;
-01C6:53;
-01C7:4E;
-01C8:47;
-01C9:07;
-01CA:9A;
-01CB:2E;
-01CC:4E;
-01CD:07;
-01CE:A1;
-01CF:24;
-01D0:52;
-01D1:52;
-01D2:D3;
-01D3:07;
-01D4:A9;
-01D5:31;
-01D6:D2;
-01D7:4F;
-01D8:4D;
-01D9:07;
-01DA:86;
-01DB:2C;
-01DC:45;
-01DD:4D;
-01DE:07;
-01DF:C8;
-01E0:25;
-01E1:52;
-01E2:45;
-01E3:07;
-01E4:DA;
-01E5:2B;
-01E6:41;
-01E7:44;
-01E8:07;
-01E9:BE;
-01EA:35;
-01EB:41;
-01EC:52;
-01ED:50;
-01EE:54;
-01EF:52;
-01F0:07;
-01F1:C0;
-01F2:32;
-01F3:54;
-01F4:52;
-01F5:49;
-01F6:4E;
-01F7:47;
-01F8:24;
-01F9:07;
-01FA:C4;
-01FB:2F;
-01FC:4F;
-01FD:53;
-01FE:07;
-01FF:DC;
-0200:24;
-0201:52;
-0202:52;
-0203:07;
-0204:C3;
-0205:24;
-0206:52;
-0207:4C;
-0208:07;
-0209:C2;
-020A:25;
-020B:49;
-020C:58;
-020D:07;
-020E:F2;
-020F:22;
-0210:44;
-0211:42;
-0212:4C;
-0213:07;
-0214:F1;
-0215:22;
-0216:D8;
-0217:07;
-0218:EF;
-0219:22;
-021A:53;
-021B:4E;
-021C:47;
-021D:07;
-021E:F0;
-021F:3D;
-0220:32;
-0221:F2;
-0222:78;
-0223:3E;
-0224:22;
-0225:93;
-0226:20;
-0227:06;
-0228:CD;
-0229:6B;
-022A:79;
-022B:CA;
-022C:19;
-022D:1A;
-022E:D5;
-022F:E5;
-0230:2A;
-0231:EE;
-0232:78;
-0233:7E;
-0234:B7;
-0235:20;
-0236:04;
-0237:01;
-0238:04;
-0239:00;
-023A:09;
-023B:CD;
-023C:5D;
-023D:78;
-023E:20;
-023F:2D;
-0240:FE;
-0241:7F;
-0242:2A;
-0243:AA;
-0244:79;
-0245:45;
-0246:21;
-0247:9A;
-0248:78;
-0249:70;
-024A:2A;
-024B:6F;
-024C:79;
-024D:22;
-024E:EA;
-024F:78;
-0250:EB;
-0251:22;
-0252:E6;
-0253:78;
-0254:C1;
-0255:C1;
-0256:C1;
-0257:D2;
-0258:5B;
-0259:1D;
-025A:11;
-025B:1E;
-025C:1D;
-025D:D5;
-025E:EB;
-025F:2A;
-0260:86;
-0261:79;
-0262:D6;
-0263:14;
-0264:4F;
-0265:06;
-0266:00;
-0267:09;
-0268:4E;
-0269:09;
-026A:E5;
-026B:C3;
-026C:77;
-026D:1D;
-026E:2A;
-026F:9A;
-0270:78;
-0271:22;
-0272:AA;
-0273:79;
-0274:2A;
-0275:EA;
-0276:78;
-0277:22;
-0278:6F;
-0279:79;
-027A:2A;
-027B:EE;
-027C:78;
-027D:22;
-027E:71;
-027F:79;
-0280:2A;
-0281:F0;
-0282:78;
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-END;
diff --git a/Computer_MiST/Laser310_MiST/rtl/roms/charrom.mif b/Computer_MiST/Laser310_MiST/rtl/roms/charrom.mif
deleted file mode 100644
index e5c8c283..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/roms/charrom.mif
+++ /dev/null
@@ -1,3079 +0,0 @@
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-DATA_RADIX = HEX;
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diff --git a/Computer_MiST/Laser310_MiST/rtl/roms/charrom_4k.mif b/Computer_MiST/Laser310_MiST/rtl/roms/charrom_4k.mif
deleted file mode 100644
index 35435b03..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/roms/charrom_4k.mif
+++ /dev/null
@@ -1,4103 +0,0 @@
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diff --git a/Computer_MiST/Laser310_MiST/rtl/roms/dosrom.mif b/Computer_MiST/Laser310_MiST/rtl/roms/dosrom.mif
deleted file mode 100644
index dc81212c..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/roms/dosrom.mif
+++ /dev/null
@@ -1,8199 +0,0 @@
-DEPTH = 8192;
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-DATA_RADIX = HEX;
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-1FFE:FF;
-1FFF:FF;
-END;
diff --git a/Computer_MiST/Laser310_MiST/rtl/roms/sysrom.mif b/Computer_MiST/Laser310_MiST/rtl/roms/sysrom.mif
deleted file mode 100644
index e125b8a7..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/roms/sysrom.mif
+++ /dev/null
@@ -1,16391 +0,0 @@
-DEPTH = 16384;
-WIDTH = 8;
-ADDRESS_RADIX = HEX;
-DATA_RADIX = HEX;
-CONTENT
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-3E5E:62;
-3E5F:20;
-3E60:39;
-3E61:E6;
-3E62:BF;
-3E63:12;
-3E64:23;
-3E65:13;
-3E66:05;
-3E67:CA;
-3E68:EE;
-3E69:04;
-3E6A:7E;
-3E6B:CB;
-3E6C:7F;
-3E6D:20;
-3E6E:06;
-3E6F:CB;
-3E70:77;
-3E71:20;
-3E72:0C;
-3E73:18;
-3E74:06;
-3E75:E6;
-3E76:8F;
-3E77:F6;
-3E78:80;
-3E79:18;
-3E7A:17;
-3E7B:F6;
-3E7C:C0;
-3E7D:18;
-3E7E:13;
-3E7F:FE;
-3E80:62;
-3E81:20;
-3E82:09;
-3E83:E5;
-3E84:21;
-3E85:39;
-3E86:78;
-3E87:CB;
-3E88:66;
-3E89:E1;
-3E8A:28;
-3E8B:0E;
-3E8C:CB;
-3E8D:6F;
-3E8E:28;
-3E8F:02;
-3E90:E6;
-3E91:BF;
-3E92:12;
-3E93:23;
-3E94:13;
-3E95:10;
-3E96:D3;
-3E97:C3;
-3E98:EE;
-3E99:04;
-3E9A:CB;
-3E9B:6F;
-3E9C:28;
-3E9D:02;
-3E9E:E6;
-3E9F:BF;
-3EA0:12;
-3EA1:23;
-3EA2:13;
-3EA3:10;
-3EA4:9B;
-3EA5:C3;
-3EA6:EE;
-3EA7:04;
-3EA8:3A;
-3EA9:18;
-3EAA:78;
-3EAB:B7;
-3EAC:C2;
-3EAD:B8;
-3EAE:04;
-3EAF:C3;
-3EB0:6A;
-3EB1:3E;
-3EB2:3A;
-3EB3:18;
-3EB4:78;
-3EB5:B7;
-3EB6:20;
-3EB7:03;
-3EB8:CB;
-3EB9:B6;
-3EBA:C9;
-3EBB:CB;
-3EBC:F6;
-3EBD:C9;
-3EBE:3A;
-3EBF:18;
-3EC0:78;
-3EC1:B7;
-3EC2:3E;
-3EC3:20;
-3EC4:20;
-3EC5:02;
-3EC6:F6;
-3EC7:40;
-3EC8:77;
-3EC9:C9;
-3ECA:F5;
-3ECB:3A;
-3ECC:18;
-3ECD:78;
-3ECE:B7;
-3ECF:28;
-3ED0:07;
-3ED1:F1;
-3ED2:E6;
-3ED3:3F;
-3ED4:E5;
-3ED5:C3;
-3ED6:AB;
-3ED7:31;
-3ED8:F1;
-3ED9:F6;
-3EDA:40;
-3EDB:E5;
-3EDC:21;
-3EDD:38;
-3EDE:78;
-3EDF:CB;
-3EE0:4E;
-3EE1:E1;
-3EE2:28;
-3EE3:02;
-3EE4:E6;
-3EE5:BF;
-3EE6:C3;
-3EE7:B5;
-3EE8:31;
-3EE9:3A;
-3EEA:18;
-3EEB:78;
-3EEC:B7;
-3EED:7E;
-3EEE:20;
-3EEF:03;
-3EF0:FE;
-3EF1:60;
-3EF2:C9;
-3EF3:FE;
-3EF4:20;
-3EF5:C9;
-3EF6:3A;
-3EF7:18;
-3EF8:78;
-3EF9:B7;
-3EFA:3E;
-3EFB:20;
-3EFC:20;
-3EFD:02;
-3EFE:F6;
-3EFF:40;
-3F00:12;
-3F01:C9;
-3F02:06;
-3F03:20;
-3F04:3A;
-3F05:18;
-3F06:78;
-3F07:B7;
-3F08:3E;
-3F09:20;
-3F0A:C0;
-3F0B:F6;
-3F0C:40;
-3F0D:C9;
-3F0E:11;
-3F0F:E0;
-3F10:71;
-3F11:3A;
-3F12:18;
-3F13:78;
-3F14:B7;
-3F15:C0;
-3F16:F1;
-3F17:7E;
-3F18:B7;
-3F19:C8;
-3F1A:CB;
-3F1B:B7;
-3F1C:12;
-3F1D:13;
-3F1E:23;
-3F1F:18;
-3F20:F6;
-3F21:3A;
-3F22:18;
-3F23:78;
-3F24:B7;
-3F25:7E;
-3F26:20;
-3F27:07;
-3F28:CB;
-3F29:F7;
-3F2A:12;
-3F2B:13;
-3F2C:3E;
-3F2D:7A;
-3F2E:C9;
-3F2F:12;
-3F30:3E;
-3F31:3A;
-3F32:C9;
-3F33:F5;
-3F34:3A;
-3F35:18;
-3F36:78;
-3F37:B7;
-3F38:20;
-3F39:05;
-3F3A:F1;
-3F3B:F6;
-3F3C:40;
-3F3D:12;
-3F3E:C9;
-3F3F:F1;
-3F40:E6;
-3F41:3F;
-3F42:12;
-3F43:C9;
-3F44:F5;
-3F45:3A;
-3F46:18;
-3F47:78;
-3F48:B7;
-3F49:20;
-3F4A:09;
-3F4B:F1;
-3F4C:CB;
-3F4D:77;
-3F4E:C2;
-3F4F:38;
-3F50:39;
-3F51:C3;
-3F52:31;
-3F53:39;
-3F54:F1;
-3F55:CB;
-3F56:77;
-3F57:CA;
-3F58:38;
-3F59:39;
-3F5A:C3;
-3F5B:31;
-3F5C:39;
-3F5D:C3;
-3F5E:31;
-3F5F:39;
-3F60:F5;
-3F61:3A;
-3F62:18;
-3F63:78;
-3F64:B7;
-3F65:20;
-3F66:06;
-3F67:F1;
-3F68:E6;
-3F69:3F;
-3F6A:C3;
-3F6B:54;
-3F6C:31;
-3F6D:F1;
-3F6E:E6;
-3F6F:7F;
-3F70:C3;
-3F71:54;
-3F72:31;
-3F73:CD;
-3F74:75;
-3F75:37;
-3F76:D0;
-3F77:E1;
-3F78:C3;
-3F79:11;
-3F7A:37;
-3F7B:3A;
-3F7C:19;
-3F7D:78;
-3F7E:47;
-3F7F:3A;
-3F80:18;
-3F81:78;
-3F82:B8;
-3F83:CA;
-3F84:E8;
-3F85:30;
-3F86:32;
-3F87:19;
-3F88:78;
-3F89:21;
-3F8A:00;
-3F8B:70;
-3F8C:01;
-3F8D:00;
-3F8E:02;
-3F8F:7E;
-3F90:B7;
-3F91:FA;
-3F92:97;
-3F93:3F;
-3F94:EE;
-3F95:40;
-3F96:77;
-3F97:23;
-3F98:0B;
-3F99:78;
-3F9A:B1;
-3F9B:20;
-3F9C:F2;
-3F9D:C3;
-3F9E:E8;
-3F9F:30;
-3FA0:3A;
-3FA1:FD;
-3FA2:68;
-3FA3:CB;
-3FA4:57;
-3FA5:3E;
-3FA6:20;
-3FA7:20;
-3FA8:08;
-3FA9:F6;
-3FAA:40;
-3FAB:32;
-3FAC:18;
-3FAD:78;
-3FAE:32;
-3FAF:19;
-3FB0:78;
-3FB1:32;
-3FB2:3C;
-3FB3:78;
-3FB4:C3;
-3FB5:C9;
-3FB6:01;
-3FB7:00;
-3FB8:00;
-3FB9:00;
-3FBA:00;
-3FBB:00;
-3FBC:00;
-3FBD:00;
-3FBE:00;
-3FBF:00;
-3FC0:00;
-3FC1:00;
-3FC2:00;
-3FC3:00;
-3FC4:00;
-3FC5:00;
-3FC6:00;
-3FC7:00;
-3FC8:00;
-3FC9:00;
-3FCA:00;
-3FCB:00;
-3FCC:00;
-3FCD:00;
-3FCE:00;
-3FCF:00;
-3FD0:00;
-3FD1:00;
-3FD2:00;
-3FD3:00;
-3FD4:00;
-3FD5:00;
-3FD6:00;
-3FD7:00;
-3FD8:00;
-3FD9:00;
-3FDA:00;
-3FDB:00;
-3FDC:00;
-3FDD:00;
-3FDE:00;
-3FDF:00;
-3FE0:00;
-3FE1:00;
-3FE2:00;
-3FE3:00;
-3FE4:00;
-3FE5:00;
-3FE6:00;
-3FE7:00;
-3FE8:00;
-3FE9:00;
-3FEA:00;
-3FEB:00;
-3FEC:00;
-3FED:00;
-3FEE:00;
-3FEF:00;
-3FF0:FF;
-3FF1:FF;
-3FF2:FF;
-3FF3:FF;
-3FF4:FF;
-3FF5:FF;
-3FF6:FF;
-3FF7:FF;
-3FF8:FF;
-3FF9:FF;
-3FFA:FF;
-3FFB:FF;
-3FFC:FF;
-3FFD:FF;
-3FFE:FF;
-3FFF:FF;
-END;
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/COPYING b/Computer_MiST/Laser310_MiST/rtl/sn76489/COPYING
deleted file mode 100644
index 60549be5..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/sn76489/COPYING
+++ /dev/null
@@ -1,340 +0,0 @@
-		    GNU GENERAL PUBLIC LICENSE
-		       Version 2, June 1991
-
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.
-                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
-			    Preamble
-
-  The licenses for most software are designed to take away your
-freedom to share and change it.  By contrast, the GNU General Public
-License is intended to guarantee your freedom to share and change free
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-the GNU Library General Public License instead.)  You can apply it to
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-  We protect your rights with two steps: (1) copyright the software, and
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-
-		    GNU GENERAL PUBLIC LICENSE
-   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
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-
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-
-  To do so, attach the following notices to the program.  It is safest
-to attach them to the start of each source file to most effectively
-convey the exclusion of warranty; and each file should have at least
-the "copyright" line and a pointer to where the full notice is found.
-
-    <one line to give the program's name and a brief idea of what it does.>
-    Copyright (C) 19yy  <name of author>
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-
-Also add information on how to contact you by electronic and paper mail.
-
-If the program is interactive, make it output a short notice like this
-when it starts in an interactive mode:
-
-    Gnomovision version 69, Copyright (C) 19yy name of author
-    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
-    This is free software, and you are welcome to redistribute it
-    under certain conditions; type `show c' for details.
-
-The hypothetical commands `show w' and `show c' should show the appropriate
-parts of the General Public License.  Of course, the commands you use may
-be called something other than `show w' and `show c'; they could even be
-mouse-clicks or menu items--whatever suits your program.
-
-You should also get your employer (if you work as a programmer) or your
-school, if any, to sign a "copyright disclaimer" for the program, if
-necessary.  Here is a sample; alter the names:
-
-  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
-  `Gnomovision' (which makes passes at compilers) written by James Hacker.
-
-  <signature of Ty Coon>, 1 April 1989
-  Ty Coon, President of Vice
-
-This General Public License does not permit incorporating your program into
-proprietary programs.  If your program is a subroutine library, you may
-consider it more useful to permit linking proprietary applications with the
-library.  If this is what you want to do, use the GNU Library General
-Public License instead of this License.
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/README b/Computer_MiST/Laser310_MiST/rtl/sn76489/README
deleted file mode 100644
index 33630144..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/sn76489/README
+++ /dev/null
@@ -1,143 +0,0 @@
-
-An SN76489AN Compatible Implementation in VHDL
-==============================================
-Version: $Date: 2006/06/18 19:28:40 $
-
-Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
-See the file COPYING.
-
-
-Integration
------------
-
-The sn76489 design exhibits all interface signals as the original chip. It
-only differs in the audio data output which is provided as an 8 bit signed
-vector instead of an analog output pin.
-
-  generic (
-    clock_div_16_g : integer := 1
-    -- Set to '1' when operating the design in SN76489 mode. The primary clock
-    -- input is divided by 16 in this variant. The data sheet mentions the
-    -- SN76494 which contains a divide-by-2 clock input stage. Set the generic
-    -- to '0' to enable this mode.
-  );
-  port (
-    clock_i    : in  std_logic;
-    -- Primary clock input
-    -- Drive with the target frequency or any integer multiple of it.
-
-    clock_en_i : in  std_logic;
-    -- Clock enable
-    -- A '1' on this input qualifies a valid rising edge on clock_i. A '0'
-    -- disables the next rising clock edge, effectivley halting the design
-    -- until the next enabled rising clock edge.
-    -- Can be used to run the core at lower frequencies than applied on
-    -- clock_i.
-
-    res_n_i    : in  std_logic;
-    -- Asynchronous low active reset input.
-    -- Sets all sequential elements to a known state.
-
-    ce_n_i     : in  std_logic;
-    -- Chip enable, low active.
-
-    we_n_i     : in  std_logic;
-    -- Write enable, low active.
-
-    ready_o    : out std_logic;
-    -- Ready indication to microprocessor.
-
-    d_i        : in  std_logic_vector(0 to 7);
-    -- Data input
-    -- MSB 0 ... 7 LSB
-
-    aout_o     : out signed(0 to 7)
-    -- Audio output, signed vector
-    -- MSB/SIGN 0 ... 7 LSB
-  );
-
-
-Both 8 bit vector ports are defined (0 to 7) which declares bit 0 to be the
-MSB and bit 7 to be the LSB. This has been implemented according to TI's data
-sheet, thus all register/data format figures apply 1:1 for this design.
-Many systems will flip the system data bus bit wise before it is connected to
-this PSG. This is simply achieved with the following VHDL construct:
-
-  signal data_s : std_logic_vector(7 downto 0);
-
-  ...
-  d_i => data_s,
-  ...
-
-d_i and data_s will be assigned from left to right, resulting in the expected
-bit assignment:
-
-  d_i    data_s
-   0       7
-   1       6
-      ...
-   6       1
-   7       0
-
-
-As this design is fully synchronous, care has to be taken when the design
-replaces an SN76489 in asynchronous mode. No problems are expected when
-interfacing the code to other synchronous components.
-
-
-Design Hierarchy
-----------------
-
-  sn76489_top
-    |
-    +-- sn76489_latch_ctrl
-    |
-    +-- sn76489_clock_div
-    |
-    +-- sn76489_tone
-    |     |
-    |     \-- sn76489_attentuator
-    |
-    +-- sn76489_tone
-    |     |
-    |     \-- sn76489_attentuator
-    |
-    +-- sn76489_tone
-    |     |
-    |     \-- sn76489_attentuator
-    |
-    \-- sn76489_noise
-          |
-          \-- sn76489_attentuator
-
-Resulting compilation sequence:
-
-  sn76489_comp_pack-p.vhd
-  sn76489_top.vhd
-  sn76489_latch_ctrl.vhd
-  sn76489_latch_ctrl-c.vhd
-  sn76489_clock_div.vhd
-  sn76489_clock_div-c.vhd
-  sn76489_attenuator.vhd
-  sn76489_attenuator-c.vhd
-  sn76489_tone.vhd
-  sn76489_tone-c.vhd
-  sn76489_noise.vhd
-  sn76489_noise-c.vhd
-  sn76489_top-c.vhd
-
-Skip the files containing VHDL configurations when analyzing the code for
-synthesis.
-
-
-References
-----------
-
-* TI Data sheet SN76489.pdf
-  ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
-
-* John Kortink's article on the SN76489:
-  http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
-
-* Maxim's "SN76489 notes" in
-  http://www.smspower.org/maxim/docs/SN76489.txt
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_attenuator.vhd b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_attenuator.vhd
deleted file mode 100644
index 444064e5..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_attenuator.vhd
+++ /dev/null
@@ -1,114 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_attenuator.vhd,v 1.7 2006/02/27 20:30:10 arnim Exp $
---
--- Attenuator Module
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sn76489_attenuator is
-
-  port (
-    attenuation_i : in  std_logic_vector(0 to 3);
-    factor_i      : in  signed(0 to 1);
-    product_o     : out signed(0 to 7)
-  );
-
-end sn76489_attenuator;
-
-
-architecture rtl of sn76489_attenuator is
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process attenuate
-  --
-  -- Purpose:
-  --   Determine the attenuation and generate the resulting product.
-  --
-  --   The maximum attenuation value is 31 which corresponds to volume off.
-  --   As described in the data sheet, the maximum "playing" attenuation is
-  --     28 = 16 + 8 + 4
-  --
-  --   The table for the volume constants is derived from the following
-  --   formula (each step is 2dB voltage):
-  --     v(0)   = 31
-  --     v(n+1) = v(n) * 0.79432823
-  --
-  attenuate: process (attenuation_i,
-                      factor_i)
-
-    type     volume_t is array (natural range 0 to 15) of natural;
-    constant volume_c : volume_t :=
-      (31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0);
-
-    variable attenuation_v  : unsigned(attenuation_i'range);
-    variable volume_v       : signed(product_o'range);
-
-  begin
-
-    attenuation_v := unsigned(attenuation_i);
-
-    -- volume look-up table
-    volume_v := to_signed(volume_c(to_integer(attenuation_v)),
-                          product_o'length);
-
-    -- this replaces a multiplier and consumes a bit fewer
-    -- resources
-    case to_integer(factor_i) is
-      when +1 =>
-        product_o <= volume_v;
-      when -1 =>
-        product_o <= -volume_v;
-      when others =>
-        product_o <= (others => '0');
-    end case;
-
-  end process attenuate;
-  --
-  -----------------------------------------------------------------------------
-
-end rtl;
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_clock_div.vhd b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_clock_div.vhd
deleted file mode 100644
index eab86beb..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_clock_div.vhd
+++ /dev/null
@@ -1,134 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_clock_div.vhd,v 1.4 2005/10/10 21:51:27 arnim Exp $
---
--- Clock Divider Circuit
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity sn76489_clock_div is
-
-  generic (
-    clock_div_16_g : integer := 1
-  );
-  port (
-    clock_i    : in  std_logic;
-    clock_en_i : in  std_logic;
-    res_n_i    : in  std_logic;
-    clk_en_o   : out boolean
-  );
-
-end sn76489_clock_div;
-
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of sn76489_clock_div is
-
-  signal cnt_s,
-         cnt_q  : unsigned(3 downto 0);
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process seq
-  --
-  -- Purpose:
-  --   Implements the sequential counter element.
-  --
-  seq: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      cnt_q <= (others => '0');
-    elsif clock_i'event and clock_i = '1' then
-      cnt_q <= cnt_s;
-    end if;
-  end process seq;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Process comb
-  --
-  -- Purpose:
-  --   Implements the combinational counter logic.
-  --
-  comb: process (clock_en_i,
-                 cnt_q)
-  begin
-    -- default assignments
-    cnt_s    <= cnt_q;
-    clk_en_o <= false;
-
-    if clock_en_i = '1' then
-
-      if cnt_q = 0 then
-        clk_en_o <= true;
-
-        if clock_div_16_g = 1 then
-          cnt_s  <= to_unsigned(15, cnt_q'length);
-        elsif clock_div_16_g = 0 then
-          cnt_s  <= to_unsigned( 1, cnt_q'length);
-        else
-          -- pragma translate_off
-          assert false
-            report "Generic clock_div_16_g must be either 0 or 1."
-            severity failure;
-          -- pragma translate_on
-        end if;
-
-      else
-        cnt_s    <= cnt_q - 1;
-
-      end if;
-
-    end if;
-
-  end process comb;
-  --
-  -----------------------------------------------------------------------------
-
-end rtl;
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd
deleted file mode 100644
index 789720c2..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd
+++ /dev/null
@@ -1,138 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_latch_ctrl.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
---
--- Latch Control Unit
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity sn76489_latch_ctrl is
-
-  port (
-    clock_i    : in  std_logic;
-    clk_en_i   : in  boolean;
-    res_n_i    : in  std_logic;
-    ce_n_i     : in  std_logic;
-    we_n_i     : in  std_logic;
-    d_i        : in  std_logic_vector(0 to 7);
-    ready_o    : out std_logic;
-    tone1_we_o : out boolean;
-    tone2_we_o : out boolean;
-    tone3_we_o : out boolean;
-    noise_we_o : out boolean;
-    r2_o       : out std_logic
-  );
-
-end sn76489_latch_ctrl;
-
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of sn76489_latch_ctrl is
-
-  signal reg_q   : std_logic_vector(0 to 2);
-  signal we_q    : boolean;
-  signal ready_q : std_logic;
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process seq
-  --
-  -- Purpose:
-  --   Implements the sequential elements.
-  --
-  seq: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      reg_q     <= (others => '0');
-      we_q      <= false;
-      ready_q   <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      -- READY Flag Output ----------------------------------------------------
-      if ready_q = '0' and we_q then
-        if clk_en_i then
-          -- assert READY when write access happened
-          ready_q <= '1';
-        end if;
-      elsif ce_n_i = '1' then
-        -- deassert READY when access has finished
-        ready_q <= '0';
-      end if;
-
-      -- Register Selection ---------------------------------------------------
-      if ce_n_i = '0' and we_n_i = '0' then
-        if clk_en_i then
-          if d_i(0) = '1' then
-            reg_q <= d_i(1 to 3);
-          end if;
-          we_q  <= true;
-        end if;
-      else
-        we_q  <= false;
-      end if;
-
-    end if;
-  end process seq;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Output mapping
-  -----------------------------------------------------------------------------
-  tone1_we_o <= reg_q(0 to 1) = "00" and we_q;
-  tone2_we_o <= reg_q(0 to 1) = "01" and we_q;
-  tone3_we_o <= reg_q(0 to 1) = "10" and we_q;
-  noise_we_o <= reg_q(0 to 1) = "11" and we_q;
-
-  r2_o       <= reg_q(2);
-
-  ready_o    <=   ready_q
-                when ce_n_i = '0' else
-                  '1';
-
-end rtl;
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_noise.vhd b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_noise.vhd
deleted file mode 100644
index 688bdd56..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_noise.vhd
+++ /dev/null
@@ -1,278 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_noise.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
---
--- Noise Generator
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sn76489_noise is
-
-  port (
-    clock_i    : in  std_logic;
-    clk_en_i   : in  boolean;
-    res_n_i    : in  std_logic;
-    we_i       : in  boolean;
-    d_i        : in  std_logic_vector(0 to 7);
-    r2_i       : in  std_logic;
-    tone3_ff_i : in  std_logic;
-    noise_o    : out signed(0 to 7)
-  );
-
-end sn76489_noise;
-
-architecture rtl of sn76489_noise is
-
-  signal nf_q       : std_logic_vector(0 to 1);
-  signal fb_q       : std_logic;
-  signal a_q        : std_logic_vector(0 to 3);
-  signal freq_cnt_q : unsigned(0 to 6);
-  signal freq_ff_q  : std_logic;
-
-  signal shift_source_s,
-         shift_source_q    : std_logic;
-  signal shift_rise_edge_s : boolean;
-
-  signal lfsr_q            : std_logic_vector(0 to 15);
-
-  signal freq_s      : signed(0 to 1);
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process cpu_regs
-  --
-  -- Purpose:
-  --   Implements the registers writable by the CPU.
-  --
-  cpu_regs: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      nf_q <= (others => '0');
-      fb_q <= '0';
-      a_q  <= (others => '1');
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i and we_i then
-        if r2_i = '0' then
-          -- access to control register
-          -- both access types can write to the control register!
-          nf_q <= d_i(6 to 7);
-          fb_q <= d_i(5);
-
-        else
-          -- access to attenuator register
-          -- both access types can write to the attenuator register!
-          a_q <= d_i(4 to 7);
-
-        end if;
-      end if;
-    end if;
-  end process cpu_regs;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Process freq_gen
-  --
-  -- Purpose:
-  --   Implements the frequency generation components.
-  --
-  freq_gen: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      freq_cnt_q <= (others => '0');
-      freq_ff_q  <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        if freq_cnt_q = 0 then
-          -- reload frequency counter according to NF setting
-          case nf_q is
-            when "00" =>
-              freq_cnt_q <= to_unsigned(16 * 2 - 1, freq_cnt_q'length);
-            when "01" =>
-              freq_cnt_q <= to_unsigned(16 * 4 - 1, freq_cnt_q'length);
-            when "10" =>
-              freq_cnt_q <= to_unsigned(16 * 8 - 1, freq_cnt_q'length);
-            when others =>
-              null;
-          end case;
-
-          freq_ff_q <= not freq_ff_q;
-
-        else
-          -- decrement frequency counter
-          freq_cnt_q <= freq_cnt_q - 1;
-
-        end if;
-
-      end if;
-    end if;
-  end process freq_gen;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Multiplex the source of the LFSR's shift enable
-  -----------------------------------------------------------------------------
-  shift_source_s <=   tone3_ff_i
-                    when nf_q = "11" else
-                      freq_ff_q;
-
-  -----------------------------------------------------------------------------
-  -- Process rise_edge
-  --
-  -- Purpose:
-  --   Detect the rising edge of the selected LFSR shift source.
-  --
-  rise_edge: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      shift_source_q <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        shift_source_q <= shift_source_s;
-      end if;
-    end if;
-  end process rise_edge;
-  --
-  -----------------------------------------------------------------------------
-
-  -- detect rising edge on shift source
-  shift_rise_edge_s <= shift_source_q = '0' and shift_source_s = '1';
-
-
-  -----------------------------------------------------------------------------
-  -- Process lfsr
-  --
-  -- Purpose:
-  --   Implements the LFSR that generates noise.
-  --   Note: This implementation shifts the register right, i.e. from index
-  --         15 towards 0 => bit 15 is the input, bit 0 is the output
-  --
-  --   Tapped bits according to MAME's sn76496.c, implemented in function
-  --   lfsr_tapped_f.
-  --
-  lfsr: process (clock_i, res_n_i)
-
-    function lfsr_tapped_f(lfsr : in std_logic_vector) return std_logic is
-      constant tapped_bits_c : std_logic_vector(0 to 15)
-        -- tapped bits are 0, 2, 15
-        := "1010000000000001";
-      variable parity_v : std_logic;
-    begin
-      parity_v := '0';
-
-      for idx in lfsr'low to lfsr'high loop
-        parity_v := parity_v xor (lfsr(idx) and tapped_bits_c(idx));
-      end loop;
-
-      return parity_v;
-    end;
-
-  begin
-    if res_n_i = '0' then
-      -- reset LFSR to "0000000000000001"
-      lfsr_q               <= (others => '0');
-      lfsr_q(lfsr_q'right) <= '1';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        if we_i and r2_i = '0' then
-          -- write to noise register
-          -- -> reset LFSR
-          lfsr_q               <= (others => '0');
-          lfsr_q(lfsr_q'right) <= '1';
-
-        elsif shift_rise_edge_s then
-
-          -- shift LFSR left towards MSB
-          for idx in lfsr_q'right-1 downto lfsr_q'left loop
-            lfsr_q(idx) <= lfsr_q(idx+1);
-          end loop;
-
-          -- determine input bit
-          if fb_q = '0' then
-            -- "Periodic" Noise
-            -- -> input to LFSR is output
-            lfsr_q(lfsr_q'right) <= lfsr_q(lfsr_q'left);
-          else
-            -- "White" Noise
-            -- -> input to LFSR is parity of tapped bits
-            lfsr_q(lfsr_q'right) <= lfsr_tapped_f(lfsr_q);
-          end if;
-
-        end if;
-
-      end if;
-    end if;
-  end process lfsr;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Map output of LFSR to signed value for attenuator.
-  -----------------------------------------------------------------------------
-  freq_s <=   to_signed(+1, 2)
-            when lfsr_q(0) = '1' else
-              to_signed( 0, 2);
-
-
-  -----------------------------------------------------------------------------
-  -- The attenuator itself
-  -----------------------------------------------------------------------------
-  attenuator_b : entity work.sn76489_attenuator
-    port map (
-      attenuation_i => a_q,
-      factor_i      => freq_s,
-      product_o     => noise_o
-    );
-
-end rtl;
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_tone.vhd b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_tone.vhd
deleted file mode 100644
index 3658efcc..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_tone.vhd
+++ /dev/null
@@ -1,188 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_tone.vhd,v 1.5 2006/02/27 20:30:10 arnim Exp $
---
--- Tone Generator
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sn76489_tone is
-
-  port (
-    clock_i  : in  std_logic;
-    clk_en_i : in  boolean;
-    res_n_i  : in  std_logic;
-    we_i     : in  boolean;
-    d_i      : in  std_logic_vector(0 to 7);
-    r2_i     : in  std_logic;
-    ff_o     : out std_logic;
-    tone_o   : out signed(0 to 7)
-  );
-
-end sn76489_tone;
-
-architecture rtl of sn76489_tone is
-
-  signal f_q        : std_logic_vector(0 to 9);
-  signal a_q        : std_logic_vector(0 to 3);
-  signal freq_cnt_q : unsigned(0 to 9);
-  signal freq_ff_q  : std_logic;
-
-  signal freq_s     : signed(0 to 1);
-
-  function all_zero(a : in std_logic_vector) return boolean is
-    variable result_v : boolean;
-  begin
-    result_v := true;
-
-    for idx in a'low to a'high loop
-      if a(idx) /= '0' then
-        result_v := false;
-      end if;
-    end loop;
-
-    return result_v;
-  end;
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process cpu_regs
-  --
-  -- Purpose:
-  --   Implements the registers writable by the CPU.
-  --
-  cpu_regs: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      f_q <= (others => '0');
-      a_q <= (others => '1');
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i and we_i then
-        if r2_i = '0' then
-          -- access to frequency register
-          if d_i(0) = '0' then
-            f_q(0 to 5) <= d_i(2 to 7);
-          else
-            f_q(6 to 9) <= d_i(4 to 7);
-          end if;
-
-        else
-          -- access to attenuator register
-          -- both access types can write to the attenuator register!
-          a_q <= d_i(4 to 7);
-
-        end if;
-      end if;
-    end if;
-  end process cpu_regs;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Process freq_gen
-  --
-  -- Purpose:
-  --   Implements the frequency generation components.
-  --
-  freq_gen: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      freq_cnt_q <= (others => '0');
-      freq_ff_q  <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        if freq_cnt_q = 0 then
-          -- update counter from frequency register
-          freq_cnt_q <= unsigned(f_q);
-
-          -- and toggle the frequency flip-flop if enabled
-          if not all_zero(f_q) then
-            freq_ff_q <= not freq_ff_q;
-          else
-            -- if frequency setting is 0, then keep flip-flop at +1
-            freq_ff_q <= '1';
-          end if;
-
-        else
-          -- decrement frequency counter
-          freq_cnt_q <= freq_cnt_q - 1;
-
-        end if;
-      end if;
-    end if;
-  end process freq_gen;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Map frequency flip-flop to signed value for attenuator.
-  -----------------------------------------------------------------------------
-  freq_s <=   to_signed(+1, 2)
-            when freq_ff_q = '1' else
-              to_signed(-1, 2);
-
-
-  -----------------------------------------------------------------------------
-  -- The attenuator itself
-  -----------------------------------------------------------------------------
-  attenuator_b : entity work.sn76489_attenuator
-    port map (
-      attenuation_i => a_q,
-      factor_i      => freq_s,
-      product_o     => tone_o
-    );
-
-
-  -----------------------------------------------------------------------------
-  -- Output mapping
-  -----------------------------------------------------------------------------
-  ff_o <= freq_ff_q;
-
-end rtl;
diff --git a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_top.vhd b/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_top.vhd
deleted file mode 100644
index c26d0e1a..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/sn76489/sn76489_top.vhd
+++ /dev/null
@@ -1,200 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_top.vhd,v 1.9 2006/02/27 20:30:10 arnim Exp $
---
--- Chip Toplevel
---
--- References:
---
---   * TI Data sheet SN76489.pdf
---     ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
---
---   * John Kortink's article on the SN76489:
---     http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
---
---   * Maxim's "SN76489 notes" in
---     http://www.smspower.org/maxim/docs/SN76489.txt
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library ieee;
-use ieee.numeric_std.all;
-
-entity sn76489_top is
-
-  generic (
-    clock_div_16_g : integer := 1
-  );
-  port (
-    clock_i    : in  std_logic;
-    clock_en_i : in  std_logic;
-    res_n_i    : in  std_logic;
-    ce_n_i     : in  std_logic;
-    we_n_i     : in  std_logic;
-    ready_o    : out std_logic;
-    d_i        : in  std_logic_vector(0 to 7);
-    aout_o     : out signed(0 to 7)
-  );
-
-end sn76489_top;
-
-architecture struct of sn76489_top is
-
-  signal clk_en_s    : boolean;
-
-  signal tone1_we_s,
-         tone2_we_s,
-         tone3_we_s,
-         noise_we_s  : boolean;
-  signal r2_s        : std_logic;
-
-  signal tone1_s,
-         tone2_s,
-         tone3_s,
-         noise_s     : signed(0 to 7);
-
-  signal tone3_ff_s  : std_logic;
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Clock Divider
-  -----------------------------------------------------------------------------
-  clock_div_b : entity work.sn76489_clock_div
-    generic map (
-      clock_div_16_g => clock_div_16_g
-    )
-    port map (
-      clock_i    => clock_i,
-      clock_en_i => clock_en_i,
-      res_n_i    => res_n_i,
-      clk_en_o   => clk_en_s
-    );
-
-
-  -----------------------------------------------------------------------------
-  -- Latch Control = CPU Interface
-  -----------------------------------------------------------------------------
-  latch_ctrl_b : entity work.sn76489_latch_ctrl
-    port map (
-      clock_i    => clock_i,
-      clk_en_i   => clk_en_s,
-      res_n_i    => res_n_i,
-      ce_n_i     => ce_n_i,
-      we_n_i     => we_n_i,
-      d_i        => d_i,
-      ready_o    => ready_o,
-      tone1_we_o => tone1_we_s,
-      tone2_we_o => tone2_we_s,
-      tone3_we_o => tone3_we_s,
-      noise_we_o => noise_we_s,
-      r2_o       => r2_s
-    );
-
-
-  -----------------------------------------------------------------------------
-  -- Tone Channel 1
-  -----------------------------------------------------------------------------
-  tone1_b : entity work.sn76489_tone
-    port map (
-      clock_i  => clock_i,
-      clk_en_i => clk_en_s,
-      res_n_i  => res_n_i,
-      we_i     => tone1_we_s,
-      d_i      => d_i,
-      r2_i     => r2_s,
-      ff_o     => open,
-      tone_o   => tone1_s
-    );
-
-  -----------------------------------------------------------------------------
-  -- Tone Channel 2
-  -----------------------------------------------------------------------------
-  tone2_b : entity work.sn76489_tone
-    port map (
-      clock_i  => clock_i,
-      clk_en_i => clk_en_s,
-      res_n_i  => res_n_i,
-      we_i     => tone2_we_s,
-      d_i      => d_i,
-      r2_i     => r2_s,
-      ff_o     => open,
-      tone_o   => tone2_s
-    );
-
-  -----------------------------------------------------------------------------
-  -- Tone Channel 3
-  -----------------------------------------------------------------------------
-  tone3_b : entity work.sn76489_tone
-    port map (
-      clock_i  => clock_i,
-      clk_en_i => clk_en_s,
-      res_n_i  => res_n_i,
-      we_i     => tone3_we_s,
-      d_i      => d_i,
-      r2_i     => r2_s,
-      ff_o     => tone3_ff_s,
-      tone_o   => tone3_s
-    );
-
-  -----------------------------------------------------------------------------
-  -- Noise Channel
-  -----------------------------------------------------------------------------
-  noise_b : entity work.sn76489_noise
-    port map (
-      clock_i    => clock_i,
-      clk_en_i   => clk_en_s,
-      res_n_i    => res_n_i,
-      we_i       => noise_we_s,
-      d_i        => d_i,
-      r2_i       => r2_s,
-      tone3_ff_i => tone3_ff_s,
-      noise_o    => noise_s
-    );
-
-
-  aout_o <= tone1_s + tone2_s + tone3_s + noise_s;
-
-end struct;
diff --git a/Computer_MiST/Laser310_MiST/rtl/spram.vhd b/Computer_MiST/Laser310_MiST/rtl/spram.vhd
deleted file mode 100644
index d8043481..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/spram.vhd
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone III",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Computer_MiST/Laser310_MiST/rtl/sprom.vhd b/Computer_MiST/Laser310_MiST/rtl/sprom.vhd
deleted file mode 100644
index a81ac959..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/sprom.vhd
+++ /dev/null
@@ -1,82 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY sprom IS
-	GENERIC
-	(
-		init_file		  : string := "";
-		widthad_a		  : natural;
-		width_a			  : natural := 8;
-    outdata_reg_a : string := "UNREGISTERED"
-	);
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
-		clock		: IN STD_LOGIC ;
-		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
-	);
-END sprom;
-
-
-ARCHITECTURE SYN OF sprom IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-
-
-
-	COMPONENT altsyncram
-	GENERIC (
-		address_aclr_a		: STRING;
-		clock_enable_input_a		: STRING;
-		clock_enable_output_a		: STRING;
-		init_file		: STRING;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		numwords_a		: NATURAL;
-		operation_mode		: STRING;
-		outdata_aclr_a		: STRING;
-		outdata_reg_a		: STRING;
-		widthad_a		: NATURAL;
-		width_a		: NATURAL;
-		width_byteena_a		: NATURAL
-	);
-	PORT (
-			clock0	: IN STD_LOGIC ;
-			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
-			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	q    <= sub_wire0(width_a-1 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_aclr_a => "NONE",
-		clock_enable_input_a => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		init_file => init_file,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**widthad_a,
-		operation_mode => "ROM",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => outdata_reg_a,
-		widthad_a => widthad_a,
-		width_a => width_a,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		clock0 => clock,
-		address_a => address,
-		q_a => sub_wire0
-	);
-
-
-
-END SYN;
diff --git a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_alu.v b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_alu.v
deleted file mode 100644
index f90bc70a..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_alu.v
+++ /dev/null
@@ -1,442 +0,0 @@
-//
-// TV80 8-Bit Microprocessor Core
-// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
-//
-// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
-//
-// Permission is hereby granted, free of charge, to any person obtaining a 
-// copy of this software and associated documentation files (the "Software"), 
-// to deal in the Software without restriction, including without limitation 
-// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
-// and/or sell copies of the Software, and to permit persons to whom the 
-// Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included 
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-module tv80_alu (/*AUTOARG*/
-  // Outputs
-  Q, F_Out, 
-  // Inputs
-  Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In
-  );
-
-  parameter		Mode   = 0;
-  parameter		Flag_C = 0;
-  parameter		Flag_N = 1;
-  parameter		Flag_P = 2;
-  parameter		Flag_X = 3;
-  parameter		Flag_H = 4;
-  parameter		Flag_Y = 5;
-  parameter		Flag_Z = 6;
-  parameter		Flag_S = 7;
-
-  input 		Arith16;
-  input 		Z16;
-  input [3:0]           ALU_Op ;
-  input [5:0]           IR;
-  input [1:0]           ISet;
-  input [7:0]           BusA;
-  input [7:0]           BusB;
-  input [7:0]           F_In;
-  output [7:0]          Q;
-  output [7:0]          F_Out;
-  reg [7:0]             Q;
-  reg [7:0]             F_Out;
-
-  function [4:0] AddSub4;
-    input [3:0] A;
-    input [3:0] B;
-    input Sub;
-    input Carry_In;
-    begin
-      AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {4'h0,Carry_In};
-    end
-  endfunction // AddSub4
-  
-  function [3:0] AddSub3;
-    input [2:0] A;
-    input [2:0] B;
-    input Sub;
-    input Carry_In;
-    begin
-      AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {3'h0,Carry_In};
-    end
-  endfunction // AddSub4
-
-  function [1:0] AddSub1;
-    input A;
-    input B;
-    input Sub;
-    input Carry_In;
-    begin
-      AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {1'h0,Carry_In};
-    end
-  endfunction // AddSub4
-
-  // AddSub variables (temporary signals)
-  reg UseCarry;
-  reg Carry7_v;
-  reg OverFlow_v;
-  reg HalfCarry_v;
-  reg Carry_v;
-  reg [7:0] Q_v;
-
-  reg [7:0] BitMask;
-
-
-  always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR)
-    begin
-      case (IR[5:3])
-        3'b000 : BitMask = 8'b00000001;
-        3'b001 : BitMask = 8'b00000010;
-        3'b010 : BitMask = 8'b00000100; 
-        3'b011 : BitMask = 8'b00001000; 
-        3'b100 : BitMask = 8'b00010000; 
-        3'b101 : BitMask = 8'b00100000; 
-        3'b110 : BitMask = 8'b01000000; 
-        default: BitMask = 8'b10000000; 
-      endcase // case(IR[5:3])
-      
-      UseCarry = ~ ALU_Op[2] && ALU_Op[0];
-      { HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) );
-      { Carry7_v, Q_v[6:4]  } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v);
-      { Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v);
-      OverFlow_v = Carry_v ^ Carry7_v;
-    end // always @ *
-  
-  reg [7:0] Q_t;
-  reg [8:0] DAA_Q;
-  
-  always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB
-	    or Carry_v or F_In or HalfCarry_v or IR or ISet
-	    or OverFlow_v or Q_v or Z16)
-    begin
-      Q_t = 8'hxx;
-      DAA_Q = {9{1'bx}};
-      
-      F_Out = F_In;
-      case (ALU_Op)
-	4'b0000, 4'b0001,  4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 :
-          begin
-	    F_Out[Flag_N] = 1'b0;
-	    F_Out[Flag_C] = 1'b0;
-            
-	    case (ALU_Op[2:0])
-              
-	      3'b000, 3'b001 : // ADD, ADC
-                begin
-		  Q_t = Q_v;
-		  F_Out[Flag_C] = Carry_v;
-		  F_Out[Flag_H] = HalfCarry_v;
-		  F_Out[Flag_P] = OverFlow_v;
-                end
-              
-	      3'b010, 3'b011, 3'b111 : // SUB, SBC, CP
-                begin
-		  Q_t = Q_v;
-		  F_Out[Flag_N] = 1'b1;
-		  F_Out[Flag_C] = ~ Carry_v;
-		  F_Out[Flag_H] = ~ HalfCarry_v;
-		  F_Out[Flag_P] = OverFlow_v;
-                end
-              
-	      3'b100 : // AND
-                begin
-		  Q_t[7:0] = BusA & BusB;
-		  F_Out[Flag_H] = 1'b1;
-                end
-              
-	      3'b101 : // XOR
-                begin
-		  Q_t[7:0] = BusA ^ BusB;
-		  F_Out[Flag_H] = 1'b0;
-                end
-              
-	      default : // OR 3'b110
-                begin
-		  Q_t[7:0] = BusA | BusB;
-		  F_Out[Flag_H] = 1'b0;
-                end
-              
-	    endcase // case(ALU_OP[2:0])
-            
-	    if (ALU_Op[2:0] == 3'b111 ) 
-              begin // CP
-		F_Out[Flag_X] = BusB[3];
-		F_Out[Flag_Y] = BusB[5];
-	      end 
-            else 
-              begin
-		F_Out[Flag_X] = Q_t[3];
-		F_Out[Flag_Y] = Q_t[5];
-	      end
-            
-	    if (Q_t[7:0] == 8'b00000000 ) 
-              begin
-		F_Out[Flag_Z] = 1'b1;
-		if (Z16 == 1'b1 ) 
-                  begin
-		    F_Out[Flag_Z] = F_In[Flag_Z];	// 16 bit ADC,SBC
-		  end
-	      end 
-            else 
-              begin
-		F_Out[Flag_Z] = 1'b0;
-	      end // else: !if(Q_t[7:0] == 8'b00000000 )
-            
-	    F_Out[Flag_S] = Q_t[7];
-	    case (ALU_Op[2:0])
-	      3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP
-                ;
-              
-	      default :
-	        F_Out[Flag_P] = ~(^Q_t);                    
-	    endcase // case(ALU_Op[2:0])
-            
-	    if (Arith16 == 1'b1 ) 
-              begin
-		F_Out[Flag_S] = F_In[Flag_S];
-		F_Out[Flag_Z] = F_In[Flag_Z];
-		F_Out[Flag_P] = F_In[Flag_P];
-	      end
-          end // case: 4'b0000, 4'b0001,  4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111
-        
-	4'b1100 :
-          begin
-	    // DAA
-	    F_Out[Flag_H] = F_In[Flag_H];
-	    F_Out[Flag_C] = F_In[Flag_C];
-	    DAA_Q[7:0] = BusA;
-	    DAA_Q[8] = 1'b0;
-	    if (F_In[Flag_N] == 1'b0 ) 
-              begin
-		// After addition
-		// Alow > 9 || H == 1
-		if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) 
-                  begin
-		    if ((DAA_Q[3:0] > 9) ) 
-                      begin
-			F_Out[Flag_H] = 1'b1;
-		      end 
-                    else 
-                      begin
-			F_Out[Flag_H] = 1'b0;
-		      end
-		    DAA_Q = DAA_Q + 6;
-		  end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
-                
-		// new Ahigh > 9 || C == 1
-		if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 ) 
-                  begin
-		    DAA_Q = DAA_Q + 96; // 0x60
-		  end
-	      end 
-            else 
-              begin
-		// After subtraction
-		if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) 
-                  begin
-		    if (DAA_Q[3:0] > 5 ) 
-                      begin
-			F_Out[Flag_H] = 1'b0;
-		      end
-		    DAA_Q[7:0] = DAA_Q[7:0] - 6;
-		  end
-		if (BusA > 153 || F_In[Flag_C] == 1'b1 ) 
-                  begin
-		    DAA_Q = DAA_Q - 352; // 0x160
-		  end
-	      end // else: !if(F_In[Flag_N] == 1'b0 )
-            
-	    F_Out[Flag_X] = DAA_Q[3];
-	    F_Out[Flag_Y] = DAA_Q[5];
-	    F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8];
-	    Q_t = DAA_Q[7:0];
-            
-	    if (DAA_Q[7:0] == 8'b00000000 ) 
-              begin
-		F_Out[Flag_Z] = 1'b1;
-	      end 
-            else 
-              begin
-		F_Out[Flag_Z] = 1'b0;
-	      end
-            
-	    F_Out[Flag_S] = DAA_Q[7];
-	    F_Out[Flag_P] = ~ (^DAA_Q);
-          end // case: 4'b1100
-        
-	4'b1101, 4'b1110 :
-          begin
-	    // RLD, RRD
-	    Q_t[7:4] = BusA[7:4];
-	    if (ALU_Op[0] == 1'b1 ) 
-              begin
-		Q_t[3:0] = BusB[7:4];
-	      end 
-            else 
-              begin
-		Q_t[3:0] = BusB[3:0];
-	      end
-	    F_Out[Flag_H] = 1'b0;
-	    F_Out[Flag_N] = 1'b0;
-	    F_Out[Flag_X] = Q_t[3];
-	    F_Out[Flag_Y] = Q_t[5];
-	    if (Q_t[7:0] == 8'b00000000 ) 
-              begin
-		F_Out[Flag_Z] = 1'b1;
-	      end 
-            else 
-              begin
-		F_Out[Flag_Z] = 1'b0;
-	      end
-	    F_Out[Flag_S] = Q_t[7];
-            F_Out[Flag_P] = ~(^Q_t);
-          end // case: when 4'b1101, 4'b1110
-        
-	4'b1001 :
-          begin
-	    // BIT
-	    Q_t[7:0] = BusB & BitMask;
-	    F_Out[Flag_S] = Q_t[7];
-	    if (Q_t[7:0] == 8'b00000000 ) 
-              begin
-		F_Out[Flag_Z] = 1'b1;
-		F_Out[Flag_P] = 1'b1;
-	      end 
-            else 
-              begin
-		F_Out[Flag_Z] = 1'b0;
-		F_Out[Flag_P] = 1'b0;
-	      end
-	    F_Out[Flag_H] = 1'b1;
-	    F_Out[Flag_N] = 1'b0;
-	    F_Out[Flag_X] = 1'b0;
-	    F_Out[Flag_Y] = 1'b0;
-	    if (IR[2:0] != 3'b110 ) 
-              begin
-		F_Out[Flag_X] = BusB[3];
-		F_Out[Flag_Y] = BusB[5];
-	      end
-          end // case: when 4'b1001
-        
-	4'b1010 :
-	  // SET
-	  Q_t[7:0] = BusB | BitMask;
-        
-	4'b1011 :
-	  // RES
-	  Q_t[7:0] = BusB & ~ BitMask;
-        
-	4'b1000 :
-          begin
-	    // ROT
-	    case (IR[5:3])
-	      3'b000 : // RLC
-                begin
-		  Q_t[7:1] = BusA[6:0];
-		  Q_t[0] = BusA[7];
-		  F_Out[Flag_C] = BusA[7];
-                end
-              
-	      3'b010 : // RL
-                begin
-		  Q_t[7:1] = BusA[6:0];
-		  Q_t[0] = F_In[Flag_C];
-		  F_Out[Flag_C] = BusA[7];
-                end
-              
-	      3'b001 : // RRC
-                begin
-		  Q_t[6:0] = BusA[7:1];
-		  Q_t[7] = BusA[0];
-		  F_Out[Flag_C] = BusA[0];
-                end
-              
-	      3'b011 : // RR
-                begin                        
-		  Q_t[6:0] = BusA[7:1];
-		  Q_t[7] = F_In[Flag_C];
-		  F_Out[Flag_C] = BusA[0];
-                end
-              
-	      3'b100 : // SLA
-                begin
-		  Q_t[7:1] = BusA[6:0];
-		  Q_t[0] = 1'b0;
-		  F_Out[Flag_C] = BusA[7];
-                end
-              
-	      3'b110 : // SLL (Undocumented) / SWAP
-                begin
-		  if (Mode == 3 ) 
-                    begin
-		      Q_t[7:4] = BusA[3:0];
-		      Q_t[3:0] = BusA[7:4];
-		      F_Out[Flag_C] = 1'b0;                            
-		    end 
-                  else 
-                    begin
-		      Q_t[7:1] = BusA[6:0];
-		      Q_t[0] = 1'b1;
-		      F_Out[Flag_C] = BusA[7];
-		    end // else: !if(Mode == 3 )
-                end // case: 3'b110
-              
-	      3'b101 : // SRA
-                begin
-		  Q_t[6:0] = BusA[7:1];
-		  Q_t[7] = BusA[7];
-		  F_Out[Flag_C] = BusA[0];
-                end
-              
-	      default : // SRL
-                begin
-		  Q_t[6:0] = BusA[7:1];
-		  Q_t[7] = 1'b0;
-		  F_Out[Flag_C] = BusA[0];
-                end
-	    endcase // case(IR[5:3])
-            
-	    F_Out[Flag_H] = 1'b0;
-	    F_Out[Flag_N] = 1'b0;
-	    F_Out[Flag_X] = Q_t[3];
-	    F_Out[Flag_Y] = Q_t[5];
-	    F_Out[Flag_S] = Q_t[7];
-	    if (Q_t[7:0] == 8'b00000000 ) 
-              begin
-		F_Out[Flag_Z] = 1'b1;
-	      end 
-            else 
-              begin
-		F_Out[Flag_Z] = 1'b0;
-	      end
-            F_Out[Flag_P] = ~(^Q_t);
-
-	    if (ISet == 2'b00 ) 
-              begin
-		F_Out[Flag_P] = F_In[Flag_P];
-		F_Out[Flag_S] = F_In[Flag_S];
-		F_Out[Flag_Z] = F_In[Flag_Z];
-	      end
-          end // case: 4'b1000
-        
-        
-	default :
-	  ;
-        
-      endcase // case(ALU_Op)
-      
-      Q = Q_t;
-    end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-  
-endmodule // T80_ALU
diff --git a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_core.v b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_core.v
deleted file mode 100644
index e3f7d247..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_core.v
+++ /dev/null
@@ -1,1389 +0,0 @@
-//
-// TV80 8-Bit Microprocessor Core
-// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
-//
-// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
-//
-// Permission is hereby granted, free of charge, to any person obtaining a 
-// copy of this software and associated documentation files (the "Software"), 
-// to deal in the Software without restriction, including without limitation 
-// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
-// and/or sell copies of the Software, and to permit persons to whom the 
-// Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included 
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-module tv80_core (/*AUTOARG*/
-  // Outputs
-  m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, dout, mc,
-  ts, intcycle_n, IntE, stop,
-  // Inputs
-  reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di
-  );
-  // Beginning of automatic inputs (from unused autoinst inputs)
-  // End of automatics
-  
-  parameter Mode = 1;   // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-  parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
-  parameter Flag_C = 0;
-  parameter Flag_N = 1;
-  parameter Flag_P = 2;
-  parameter Flag_X = 3;
-  parameter Flag_H = 4;
-  parameter Flag_Y = 5;
-  parameter Flag_Z = 6;
-  parameter Flag_S = 7;
-
-  input     reset_n;            
-  input     clk;                
-  input     cen;                
-  input     wait_n;             
-  input     int_n;              
-  input     nmi_n;              
-  input     busrq_n;            
-  output    m1_n;               
-  output    iorq;               
-  output    no_read;            
-  output    write;              
-  output    rfsh_n;             
-  output    halt_n;             
-  output    busak_n;            
-  output [15:0] A; 
-  input [7:0]   dinst;  
-  input [7:0]   di;     
-  output [7:0]  dout;     
-  output [6:0]  mc;     
-  output [6:0]  ts;     
-  output        intcycle_n;     
-  output        IntE;           
-  output        stop;           
-
-  reg    m1_n;          
-  reg    iorq; 
-`ifdef TV80_REFRESH         
-  reg    rfsh_n;   
-`endif             
-  reg    halt_n;                
-  reg    busak_n;               
-  reg [15:0] A; 
-  reg [7:0]  dout;        
-  reg [6:0]  mc;        
-  reg [6:0]  ts;        
-  reg   intcycle_n;     
-  reg   IntE;           
-  reg   stop;           
-
-  parameter     aNone    = 3'b111;
-  parameter     aBC      = 3'b000;
-  parameter     aDE      = 3'b001;
-  parameter     aXY      = 3'b010;
-  parameter     aIOA     = 3'b100;
-  parameter     aSP      = 3'b101;
-  parameter     aZI      = 3'b110;
-
-  // Registers
-  reg [7:0]     ACC, F;
-  reg [7:0]     Ap, Fp;
-  reg [7:0]     I;
-`ifdef TV80_REFRESH
-  reg [7:0]     R;
-`endif
-  reg [15:0]    SP, PC;
-  reg [7:0]     RegDIH;
-  reg [7:0]     RegDIL;
-  wire [15:0]   RegBusA;
-  wire [15:0]   RegBusB;
-  wire [15:0]   RegBusC;
-  reg [2:0]     RegAddrA_r;
-  reg [2:0]     RegAddrA;
-  reg [2:0]     RegAddrB_r;
-  reg [2:0]     RegAddrB;
-  reg [2:0]     RegAddrC;
-  reg           RegWEH;
-  reg           RegWEL;
-  reg           Alternate;
-
-  // Help Registers
-  reg [15:0]    TmpAddr;        // Temporary address register
-  reg [7:0]     IR;             // Instruction register
-  reg [1:0]     ISet;           // Instruction set selector
-  reg [15:0]    RegBusA_r;
-
-  reg [15:0]    ID16;
-  reg [7:0]     Save_Mux;
-
-  reg [6:0]     tstate;
-  reg [6:0]     mcycle;
-  reg           last_mcycle, last_tstate;
-  reg           IntE_FF1;
-  reg           IntE_FF2;
-  reg           Halt_FF;
-  reg           BusReq_s;
-  reg           BusAck;
-  reg           ClkEn;
-  reg           NMI_s;
-  reg           INT_s;
-  reg [1:0]     IStatus;
-
-  reg [7:0]     DI_Reg;
-  reg           T_Res;
-  reg [1:0]     XY_State;
-  reg [2:0]     Pre_XY_F_M;
-  reg           NextIs_XY_Fetch;
-  reg           XY_Ind;
-  reg           No_BTR;
-  reg           BTR_r;
-  reg           Auto_Wait;
-  reg           Auto_Wait_t1;
-  reg           Auto_Wait_t2;
-  reg           IncDecZ;
-
-  // ALU signals
-  reg [7:0]     BusB;
-  reg [7:0]     BusA;
-  wire [7:0]    ALU_Q;
-  wire [7:0]    F_Out;
-
-  // Registered micro code outputs
-  reg [4:0]     Read_To_Reg_r;
-  reg           Arith16_r;
-  reg           Z16_r;
-  reg [3:0]     ALU_Op_r;
-  reg           Save_ALU_r;
-  reg           PreserveC_r;
-  reg [2:0]     mcycles;
-
-  // Micro code outputs
-  wire [2:0]    mcycles_d;
-  wire [2:0]    tstates;
-  reg           IntCycle;
-  reg           NMICycle;
-  wire          Inc_PC;
-  wire          Inc_WZ;
-  wire [3:0]    IncDec_16;
-  wire [1:0]    Prefix;
-  wire          Read_To_Acc;
-  wire          Read_To_Reg;
-  wire [3:0]     Set_BusB_To;
-  wire [3:0]     Set_BusA_To;
-  wire [3:0]     ALU_Op;
-  wire           Save_ALU;
-  wire           PreserveC;
-  wire           Arith16;
-  wire [2:0]     Set_Addr_To;
-  wire           Jump;
-  wire           JumpE;
-  wire           JumpXY;
-  wire           Call;
-  wire           RstP;
-  wire           LDZ;
-  wire           LDW;
-  wire           LDSPHL;
-  wire           iorq_i;
-  wire [2:0]     Special_LD;
-  wire           ExchangeDH;
-  wire           ExchangeRp;
-  wire           ExchangeAF;
-  wire           ExchangeRS;
-  wire           I_DJNZ;
-  wire           I_CPL;
-  wire           I_CCF;
-  wire           I_SCF;
-  wire           I_RETN;
-  wire           I_BT;
-  wire           I_BC;
-  wire           I_BTR;
-  wire           I_RLD;
-  wire           I_RRD;
-  wire           I_INRC;
-  wire           SetDI;
-  wire           SetEI;
-  wire [1:0]     IMode;
-  wire           Halt;
-
-  reg [15:0]     PC16;
-  reg [15:0]     PC16_B;
-  reg [15:0]     SP16, SP16_A, SP16_B;
-  reg [15:0]     ID16_B;
-  reg            Oldnmi_n;
-  
-  tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode
-    (
-     .IR                   (IR),
-     .ISet                 (ISet),
-     .MCycle               (mcycle),
-     .F                    (F),
-     .NMICycle             (NMICycle),
-     .IntCycle             (IntCycle),
-     .MCycles              (mcycles_d),
-     .TStates              (tstates),
-     .Prefix               (Prefix),
-     .Inc_PC               (Inc_PC),
-     .Inc_WZ               (Inc_WZ),
-     .IncDec_16            (IncDec_16),
-     .Read_To_Acc          (Read_To_Acc),
-     .Read_To_Reg          (Read_To_Reg),
-     .Set_BusB_To          (Set_BusB_To),
-     .Set_BusA_To          (Set_BusA_To),
-     .ALU_Op               (ALU_Op),
-     .Save_ALU             (Save_ALU),
-     .PreserveC            (PreserveC),
-     .Arith16              (Arith16),
-     .Set_Addr_To          (Set_Addr_To),
-     .IORQ                 (iorq_i),
-     .Jump                 (Jump),
-     .JumpE                (JumpE),
-     .JumpXY               (JumpXY),
-     .Call                 (Call),
-     .RstP                 (RstP),
-     .LDZ                  (LDZ),
-     .LDW                  (LDW),
-     .LDSPHL               (LDSPHL),
-     .Special_LD           (Special_LD),
-     .ExchangeDH           (ExchangeDH),
-     .ExchangeRp           (ExchangeRp),
-     .ExchangeAF           (ExchangeAF),
-     .ExchangeRS           (ExchangeRS),
-     .I_DJNZ               (I_DJNZ),
-     .I_CPL                (I_CPL),
-     .I_CCF                (I_CCF),
-     .I_SCF                (I_SCF),
-     .I_RETN               (I_RETN),
-     .I_BT                 (I_BT),
-     .I_BC                 (I_BC),
-     .I_BTR                (I_BTR),
-     .I_RLD                (I_RLD),
-     .I_RRD                (I_RRD),
-     .I_INRC               (I_INRC),
-     .SetDI                (SetDI),
-     .SetEI                (SetEI),
-     .IMode                (IMode),
-     .Halt                 (Halt),
-     .NoRead               (no_read),
-     .Write                (write)
-     );
-
-  tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu
-    (
-     .Arith16              (Arith16_r),
-     .Z16                  (Z16_r),
-     .ALU_Op               (ALU_Op_r),
-     .IR                   (IR[5:0]),
-     .ISet                 (ISet),
-     .BusA                 (BusA),
-     .BusB                 (BusB),
-     .F_In                 (F),
-     .Q                    (ALU_Q),
-     .F_Out                (F_Out)
-     );
-
-  function [6:0] number_to_bitvec;
-    input [2:0] num;
-    begin
-      case (num)
-        1 : number_to_bitvec = 7'b0000001;
-        2 : number_to_bitvec = 7'b0000010;
-        3 : number_to_bitvec = 7'b0000100;
-        4 : number_to_bitvec = 7'b0001000;
-        5 : number_to_bitvec = 7'b0010000;
-        6 : number_to_bitvec = 7'b0100000;
-        7 : number_to_bitvec = 7'b1000000;
-        default : number_to_bitvec = 7'bx;
-      endcase // case(num)
-    end
-  endfunction // number_to_bitvec
-
-  function [2:0] mcyc_to_number;
-    input [6:0] mcyc;
-    begin
-      casez (mcyc)
-        7'b1zzzzzz : mcyc_to_number = 3'h7;
-        7'b01zzzzz : mcyc_to_number = 3'h6;
-        7'b001zzzz : mcyc_to_number = 3'h5;
-        7'b0001zzz : mcyc_to_number = 3'h4;
-        7'b00001zz : mcyc_to_number = 3'h3;
-        7'b000001z : mcyc_to_number = 3'h2;
-        7'b0000001 : mcyc_to_number = 3'h1;
-        default : mcyc_to_number = 3'h1;
-      endcase
-    end
-  endfunction
-  
-  always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates)
-    begin
-      case (mcycles)
-        1 : last_mcycle = mcycle[0];
-        2 : last_mcycle = mcycle[1];
-        3 : last_mcycle = mcycle[2];
-        4 : last_mcycle = mcycle[3];
-        5 : last_mcycle = mcycle[4];
-        6 : last_mcycle = mcycle[5];
-        7 : last_mcycle = mcycle[6];
-        default : last_mcycle = 1'bx;
-      endcase // case(mcycles)
-
-      case (tstates)
-        0 : last_tstate = tstate[0];
-        1 : last_tstate = tstate[1];
-        2 : last_tstate = tstate[2];
-        3 : last_tstate = tstate[3];
-        4 : last_tstate = tstate[4];
-        5 : last_tstate = tstate[5];
-        6 : last_tstate = tstate[6];
-        default : last_tstate = 1'bx;
-      endcase
-    end // always @ (...
-  
-          
-  always @(/*AUTOSENSE*/ALU_Q or BusAck or BusB or DI_Reg
-	   or ExchangeRp or IR or Save_ALU_r or Set_Addr_To or XY_Ind
-	   or XY_State or cen or last_tstate or mcycle)
-    begin
-      ClkEn = cen && ~ BusAck;
-
-      if (last_tstate)
-        T_Res = 1'b1;
-      else T_Res = 1'b0;
-      
-      if (XY_State != 2'b00 && XY_Ind == 1'b0 &&
-          ((Set_Addr_To == aXY) ||
-           (mcycle[0] && IR == 8'b11001011) ||
-           (mcycle[0] && IR == 8'b00110110)))
-        NextIs_XY_Fetch = 1'b1;
-      else 
-        NextIs_XY_Fetch = 1'b0;
-
-      if (ExchangeRp)
-        Save_Mux = BusB;
-      else if (!Save_ALU_r)
-        Save_Mux = DI_Reg;
-      else
-        Save_Mux = ALU_Q;
-    end // always @ *
-  
-  always @ (posedge clk or negedge reset_n)
-    begin
-      if (reset_n == 1'b0 ) 
-        begin
-          PC <= #1 0;  // Program Counter
-          A <= #1 0;
-          TmpAddr <= #1 0;
-          IR <= #1 8'b00000000;
-          ISet <= #1 2'b00;
-          XY_State <= #1 2'b00;
-          IStatus <= #1 2'b00;
-          mcycles <= #1 3'b000;
-          dout <= #1 8'b00000000;
-
-          ACC <= #1 8'hFF;
-          F <= #1 8'hFF;
-          Ap <= #1 8'hFF;
-          Fp <= #1 8'hFF;
-          I <= #1 0;
-          `ifdef TV80_REFRESH
-          R <= #1 0;
-          `endif
-          SP <= #1 16'hFFFF;
-          Alternate <= #1 1'b0;
-
-          Read_To_Reg_r <= #1 5'b00000;
-          Arith16_r <= #1 1'b0;
-          BTR_r <= #1 1'b0;
-          Z16_r <= #1 1'b0;
-          ALU_Op_r <= #1 4'b0000;
-          Save_ALU_r <= #1 1'b0;
-          PreserveC_r <= #1 1'b0;
-          XY_Ind <= #1 1'b0;
-        end 
-      else 
-        begin
-
-          if (ClkEn == 1'b1 ) 
-            begin
-
-              ALU_Op_r <= #1 4'b0000;
-              Save_ALU_r <= #1 1'b0;
-              Read_To_Reg_r <= #1 5'b00000;
-
-              mcycles <= #1 mcycles_d;
-
-              if (IMode != 2'b11 ) 
-                begin
-                  IStatus <= #1 IMode;
-                end
-
-              Arith16_r <= #1 Arith16;
-              PreserveC_r <= #1 PreserveC;
-              if (ISet == 2'b10 && ALU_Op[2] == 1'b0 && ALU_Op[0] == 1'b1 && mcycle[2] ) 
-                begin
-                  Z16_r <= #1 1'b1;
-                end 
-              else 
-                begin
-                  Z16_r <= #1 1'b0;
-                end
-
-              if (mcycle[0] && (tstate[1] | tstate[2] | tstate[3] )) 
-                begin
-                  // mcycle == 1 && tstate == 1, 2, || 3
-                  if (tstate[2] && wait_n == 1'b1 ) 
-                    begin
-                      `ifdef TV80_REFRESH
-                      if (Mode < 2 ) 
-                        begin
-                          A[7:0] <= #1 R;
-                          A[15:8] <= #1 I;
-                          R[6:0] <= #1 R[6:0] + 1;
-                        end
-                      `endif
-                      if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 || Halt == 1'b1) ) 
-                        begin
-                          PC <= #1 PC16;
-                        end
-
-                      if (IntCycle == 1'b1 && IStatus == 2'b01 ) 
-                        begin
-                          IR <= #1 8'b11111111;
-                        end 
-                      else if (Halt_FF == 1'b1 || (IntCycle == 1'b1 && IStatus == 2'b10) || NMICycle == 1'b1 ) 
-                        begin
-                          IR <= #1 8'b00000000;
-			  TmpAddr[7:0] <= #1 dinst; // Special M1 vector fetch
-                        end 
-                      else 
-                        begin
-                          IR <= #1 dinst;
-                        end
-
-                      ISet <= #1 2'b00;
-                      if (Prefix != 2'b00 ) 
-                        begin
-                          if (Prefix == 2'b11 ) 
-                            begin
-                              if (IR[5] == 1'b1 ) 
-                                begin
-                                  XY_State <= #1 2'b10;
-                                end 
-                              else 
-                                begin
-                                  XY_State <= #1 2'b01;
-                                end
-                            end 
-                          else 
-                            begin
-                              if (Prefix == 2'b10 ) 
-                                begin
-                                  XY_State <= #1 2'b00;
-                                  XY_Ind <= #1 1'b0;
-                                end
-                              ISet <= #1 Prefix;
-                            end
-                        end 
-                      else 
-                        begin
-                          XY_State <= #1 2'b00;
-                          XY_Ind <= #1 1'b0;
-                        end
-                    end // if (tstate == 2 && wait_n == 1'b1 )
-                  
-
-                end 
-              else 
-                begin
-                  // either (mcycle > 1) OR (mcycle == 1 AND tstate > 3)
-
-                  if (mcycle[5] ) 
-                    begin
-                      XY_Ind <= #1 1'b1;
-                      if (Prefix == 2'b01 ) 
-                        begin
-                          ISet <= #1 2'b01;
-                        end
-                    end
-                  
-                  if (T_Res == 1'b1 ) 
-                    begin
-                      BTR_r <= #1 (I_BT || I_BC || I_BTR) && ~ No_BTR;
-                      if (Jump == 1'b1 ) 
-                        begin
-                          A[15:8] <= #1 DI_Reg;
-                          A[7:0] <= #1 TmpAddr[7:0];
-                          PC[15:8] <= #1 DI_Reg;
-                          PC[7:0] <= #1 TmpAddr[7:0];
-                        end 
-                      else if (JumpXY == 1'b1 ) 
-                        begin
-                          A <= #1 RegBusC;
-                          PC <= #1 RegBusC;
-                        end else if (Call == 1'b1 || RstP == 1'b1 ) 
-                          begin
-                            A <= #1 TmpAddr;
-                            PC <= #1 TmpAddr;
-                          end 
-                        else if (last_mcycle && NMICycle == 1'b1 ) 
-                          begin
-                            A <= #1 16'b0000000001100110;
-                            PC <= #1 16'b0000000001100110;
-                          end 
-                        else if (mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 ) 
-                          begin
-                            A[15:8] <= #1 I;
-                            A[7:0] <= #1 TmpAddr[7:0];
-                            PC[15:8] <= #1 I;
-                            PC[7:0] <= #1 TmpAddr[7:0];
-                          end 
-                        else 
-                          begin
-                            case (Set_Addr_To)
-                              aXY :
-                                begin
-                                  if (XY_State == 2'b00 ) 
-                                    begin
-                                      A <= #1 RegBusC;
-                                    end 
-                                  else 
-                                    begin
-                                      if (NextIs_XY_Fetch == 1'b1 )
-                                        begin
-                                          A <= #1 PC;
-                                        end 
-                                      else 
-                                        begin
-                                          A <= #1 TmpAddr;
-                                        end
-                                    end // else: !if(XY_State == 2'b00 )
-                                end // case: aXY
-                              
-                              aIOA :
-                                begin
-                                  if (Mode == 3 ) 
-                                    begin
-                                      // Memory map I/O on GBZ80
-                                      A[15:8] <= #1 8'hFF;
-                                    end 
-                                  else if (Mode == 2 ) 
-                                    begin
-                                      // Duplicate I/O address on 8080
-                                      A[15:8] <= #1 DI_Reg;
-                                    end 
-                                  else 
-                                    begin
-                                      A[15:8] <= #1 ACC;
-                                    end
-                                  A[7:0] <= #1 DI_Reg;
-                                end // case: aIOA
-
-                              
-                              aSP :
-                                begin
-                                  A <= #1 SP;
-                                end
-                              
-                              aBC :
-                                begin
-                                  if (Mode == 3 && iorq_i == 1'b1 ) 
-                                    begin
-                                      // Memory map I/O on GBZ80
-                                      A[15:8] <= #1 8'hFF;
-                                      A[7:0] <= #1 RegBusC[7:0];
-                                    end 
-                                  else 
-                                    begin
-                                      A <= #1 RegBusC;
-                                    end
-                                end // case: aBC
-                              
-                              aDE :
-                                begin
-                                  A <= #1 RegBusC;
-                                end
-                              
-                              aZI :
-                                begin                                  
-                                  if (Inc_WZ == 1'b1 ) 
-                                    begin
-                                      A <= #1 TmpAddr + 1;
-                                    end 
-                                  else 
-                                    begin
-                                      A[15:8] <= #1 DI_Reg;
-                                      A[7:0] <= #1 TmpAddr[7:0];
-                                    end
-                                end // case: aZI
-                              
-                              default   :
-                                begin                                    
-                                  A <= #1 PC;
-                                end
-                            endcase // case(Set_Addr_To)
-                            
-                          end // else: !if(mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 )
-                      
-
-                      Save_ALU_r <= #1 Save_ALU;
-                      ALU_Op_r <= #1 ALU_Op;
-                      
-                      if (I_CPL == 1'b1 ) 
-                        begin
-                          // CPL
-                          ACC <= #1 ~ ACC;
-                          F[Flag_Y] <= #1 ~ ACC[5];
-                          F[Flag_H] <= #1 1'b1;
-                          F[Flag_X] <= #1 ~ ACC[3];
-                          F[Flag_N] <= #1 1'b1;
-                        end
-                      if (I_CCF == 1'b1 ) 
-                        begin
-                          // CCF
-                          F[Flag_C] <= #1 ~ F[Flag_C];
-                          F[Flag_Y] <= #1 ACC[5];
-                          F[Flag_H] <= #1 F[Flag_C];
-                          F[Flag_X] <= #1 ACC[3];
-                          F[Flag_N] <= #1 1'b0;
-                        end
-                      if (I_SCF == 1'b1 ) 
-                        begin
-                          // SCF
-                          F[Flag_C] <= #1 1'b1;
-                          F[Flag_Y] <= #1 ACC[5];
-                          F[Flag_H] <= #1 1'b0;
-                          F[Flag_X] <= #1 ACC[3];
-                          F[Flag_N] <= #1 1'b0;
-                        end
-                    end // if (T_Res == 1'b1 )
-                  
-
-                  if (tstate[2] && wait_n == 1'b1 ) 
-                    begin
-                      if (ISet == 2'b01 && mcycle[6] ) 
-                        begin
-                          IR <= #1 dinst;
-                        end
-                      if (JumpE == 1'b1 ) 
-                        begin
-                          PC <= #1 PC16;
-                        end 
-                      else if (Inc_PC == 1'b1 ) 
-                        begin
-                          //PC <= #1 PC + 1;
-                          PC <= #1 PC16;
-                        end
-                      if (BTR_r == 1'b1 ) 
-                        begin
-                          //PC <= #1 PC - 2;
-                          PC <= #1 PC16;
-                        end
-                      if (RstP == 1'b1 ) 
-                        begin
-                          TmpAddr <= #1 { 10'h0, IR[5:3], 3'h0 };
-                          //TmpAddr <= #1 (others =>1'b0);
-                          //TmpAddr[5:3] <= #1 IR[5:3];
-                        end
-                    end
-                  if (tstate[3] && mcycle[5] ) 
-                    begin
-                      TmpAddr <= #1 SP16;
-                    end
-
-                  if ((tstate[2] && wait_n == 1'b1) || (tstate[4] && mcycle[0]) ) 
-                    begin
-                      if (IncDec_16[2:0] == 3'b111 ) 
-                        begin
-                          SP <= #1 SP16;
-                        end
-                    end
-
-                  if (LDSPHL == 1'b1 ) 
-                    begin
-                      SP <= #1 RegBusC;
-                    end
-                  if (ExchangeAF == 1'b1 ) 
-                    begin
-                      Ap <= #1 ACC;
-                      ACC <= #1 Ap;
-                      Fp <= #1 F;
-                      F <= #1 Fp;
-                    end
-                  if (ExchangeRS == 1'b1 ) 
-                    begin
-                      Alternate <= #1 ~ Alternate;
-                    end
-                end // else: !if(mcycle  == 3'b001 && tstate(2) == 1'b0 )
-              
-
-              if (tstate[3] ) 
-                begin
-                  if (LDZ == 1'b1 ) 
-                    begin
-                      TmpAddr[7:0] <= #1 DI_Reg;
-                    end
-                  if (LDW == 1'b1 ) 
-                    begin
-                      TmpAddr[15:8] <= #1 DI_Reg;
-                    end
-
-                  if (Special_LD[2] == 1'b1 ) 
-                    begin
-                      case (Special_LD[1:0])
-                        2'b00 :
-                          begin
-                            ACC <= #1 I;
-                            F[Flag_P] <= #1 IntE_FF2;
-			    F[Flag_Z] <= (I == 0);
-			    F[Flag_S] <= I[7];
-			    F[Flag_H] <= 0;
-			    F[Flag_N] <= 0; 
-                          end
-                        
-                        2'b01 :
-                          begin
-                            `ifdef TV80_REFRESH
-                            ACC <= #1 R;
-                            `else
-                            ACC <= #1 0;
-                            `endif
-                            F[Flag_P] <= #1 IntE_FF2;
-			    F[Flag_Z] <= (I == 0);
-			    F[Flag_S] <= I[7];
-			    F[Flag_H] <= 0;
-			    F[Flag_N] <= 0; 
-                          end
-                        
-                        2'b10 :
-                          I <= #1 ACC;
-
-                        `ifdef TV80_REFRESH                        
-                        default :
-                          R <= #1 ACC;
-                        `else
-                        default : ;
-                        `endif                        
-                      endcase
-                    end
-                end // if (tstate == 3 )
-              
-
-              if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 ) 
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      F[6] <= #1 F_Out[6];
-                      F[5] <= #1 F_Out[5];
-                      F[7] <= #1 F_Out[7];
-                      if (PreserveC_r == 1'b0 ) 
-                        begin
-                          F[4] <= #1 F_Out[4];
-                        end
-                    end 
-                  else 
-                    begin
-                      F[7:1] <= #1 F_Out[7:1];
-                      if (PreserveC_r == 1'b0 ) 
-                        begin
-                          F[Flag_C] <= #1 F_Out[0];
-                        end
-                    end
-                end // if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 )
-              
-              if (T_Res == 1'b1 && I_INRC == 1'b1 ) 
-                begin
-                  F[Flag_H] <= #1 1'b0;
-                  F[Flag_N] <= #1 1'b0;
-                  if (DI_Reg[7:0] == 8'b00000000 ) 
-                    begin
-                      F[Flag_Z] <= #1 1'b1;
-                    end 
-                  else 
-                    begin
-                      F[Flag_Z] <= #1 1'b0;
-                    end
-                  F[Flag_S] <= #1 DI_Reg[7];
-                  F[Flag_P] <= #1 ~ (^DI_Reg[7:0]);
-                end // if (T_Res == 1'b1 && I_INRC == 1'b1 )
-              
-
-              if (tstate[1] && Auto_Wait_t1 == 1'b0 ) 
-                begin
-                  dout <= #1 BusB;
-                  if (I_RLD == 1'b1 ) 
-                    begin
-                      dout[3:0] <= #1 BusA[3:0];
-                      dout[7:4] <= #1 BusB[3:0];
-                    end
-                  if (I_RRD == 1'b1 ) 
-                    begin
-                      dout[3:0] <= #1 BusB[7:4];
-                      dout[7:4] <= #1 BusA[3:0];
-                    end
-                end
-
-              if (T_Res == 1'b1 ) 
-                begin
-                  Read_To_Reg_r[3:0] <= #1 Set_BusA_To;
-                  Read_To_Reg_r[4] <= #1 Read_To_Reg;
-                  if (Read_To_Acc == 1'b1 ) 
-                    begin
-                      Read_To_Reg_r[3:0] <= #1 4'b0111;
-                      Read_To_Reg_r[4] <= #1 1'b1;
-                    end
-                end
-
-              if (tstate[1] && I_BT == 1'b1 ) 
-                begin
-                  F[Flag_X] <= #1 ALU_Q[3];
-                  F[Flag_Y] <= #1 ALU_Q[1];
-                  F[Flag_H] <= #1 1'b0;
-                  F[Flag_N] <= #1 1'b0;
-                end
-              if (I_BC == 1'b1 || I_BT == 1'b1 ) 
-                begin
-                  F[Flag_P] <= #1 IncDecZ;
-                end
-
-              if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||
-                  (Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) ) 
-                begin
-                  case (Read_To_Reg_r)
-                    5'b10111 :
-                      ACC <= #1 Save_Mux;
-                    5'b10110 :
-                      dout <= #1 Save_Mux;
-                    5'b11000 :
-                      SP[7:0] <= #1 Save_Mux;
-                    5'b11001 :
-                      SP[15:8] <= #1 Save_Mux;
-                    5'b11011 :
-                      F <= #1 Save_Mux;
-                    default : ;
-                  endcase
-                end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...              
-            end // if (ClkEn == 1'b1 )         
-        end // else: !if(reset_n == 1'b0 )
-    end
-  
-
-  //-------------------------------------------------------------------------
-  //
-  // BC('), DE('), HL('), IX && IY
-  //
-  //-------------------------------------------------------------------------
-  always @ (posedge clk)
-    begin
-      if (ClkEn == 1'b1 ) 
-        begin
-          // Bus A / Write
-          RegAddrA_r <= #1  { Alternate, Set_BusA_To[2:1] };
-          if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusA_To[2:1] == 2'b10 ) 
-            begin
-              RegAddrA_r <= #1 { XY_State[1],  2'b11 };
-            end
-
-          // Bus B
-          RegAddrB_r <= #1 { Alternate, Set_BusB_To[2:1] };
-          if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusB_To[2:1] == 2'b10 ) 
-            begin
-              RegAddrB_r <= #1 { XY_State[1],  2'b11 };
-            end
-
-          // Address from register
-          RegAddrC <= #1 { Alternate,  Set_Addr_To[1:0] };
-          // Jump (HL), LD SP,HL
-          if ((JumpXY == 1'b1 || LDSPHL == 1'b1) ) 
-            begin
-              RegAddrC <= #1 { Alternate, 2'b10 };
-            end
-          if (((JumpXY == 1'b1 || LDSPHL == 1'b1) && XY_State != 2'b00) || (mcycle[5]) ) 
-            begin
-              RegAddrC <= #1 { XY_State[1],  2'b11 };
-            end
-
-          if (I_DJNZ == 1'b1 && Save_ALU_r == 1'b1 && Mode < 2 ) 
-            begin
-              IncDecZ <= #1 F_Out[Flag_Z];
-            end
-          if ((tstate[2] || (tstate[3] && mcycle[0])) && IncDec_16[2:0] == 3'b100 ) 
-            begin
-              if (ID16 == 0 ) 
-                begin
-                  IncDecZ <= #1 1'b0;
-                end 
-              else 
-                begin
-                  IncDecZ <= #1 1'b1;
-                end
-            end
-          
-          RegBusA_r <= #1 RegBusA;
-        end
-      
-    end // always @ (posedge clk)
-  
-
-  always @(/*AUTOSENSE*/Alternate or ExchangeDH or IncDec_16
-	   or RegAddrA_r or RegAddrB_r or XY_State or mcycle or tstate)
-    begin
-      if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && XY_State == 2'b00)
-        RegAddrA = { Alternate, IncDec_16[1:0] };
-      else if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && IncDec_16[1:0] == 2'b10)
-        RegAddrA = { XY_State[1], 2'b11 };
-      else if (ExchangeDH == 1'b1 && tstate[3])
-        RegAddrA = { Alternate, 2'b10 };
-      else if (ExchangeDH == 1'b1 && tstate[4])
-        RegAddrA = { Alternate, 2'b01 };
-      else
-        RegAddrA = RegAddrA_r;
-      
-      if (ExchangeDH == 1'b1 && tstate[3])
-        RegAddrB = { Alternate, 2'b01 };
-      else
-        RegAddrB = RegAddrB_r;
-    end // always @ *
-  
-
-  always @(/*AUTOSENSE*/ALU_Op_r or Auto_Wait_t1 or ExchangeDH
-	   or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle
-	   or tstate or wait_n)
-    begin
-      RegWEH = 1'b0;
-      RegWEL = 1'b0;
-      if ((tstate[1] && ~Save_ALU_r && ~Auto_Wait_t1) ||
-          (Save_ALU_r && (ALU_Op_r != 4'b0111)) ) 
-        begin
-          case (Read_To_Reg_r)
-            5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 :
-              begin
-                RegWEH = ~ Read_To_Reg_r[0];
-                RegWEL = Read_To_Reg_r[0];
-              end // UNMATCHED !!
-            default : ;
-          endcase // case(Read_To_Reg_r)
-          
-        end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
-      
-
-      if (ExchangeDH && (tstate[3] || tstate[4]) ) 
-        begin
-          RegWEH = 1'b1;
-          RegWEL = 1'b1;
-        end
-
-      if (IncDec_16[2] && ((tstate[2] && wait_n && ~mcycle[0]) || (tstate[3] && mcycle[0])) ) 
-        begin
-          case (IncDec_16[1:0])
-            2'b00 , 2'b01 , 2'b10 :
-              begin
-                RegWEH = 1'b1;
-                RegWEL = 1'b1;
-              end // UNMATCHED !!
-            default : ;
-          endcase
-        end
-    end // always @ *
-  
-
-  always @(/*AUTOSENSE*/ExchangeDH or ID16 or IncDec_16 or RegBusA_r
-	   or RegBusB or Save_Mux or mcycle or tstate)
-    begin
-      RegDIH = Save_Mux;
-      RegDIL = Save_Mux;
-
-      if (ExchangeDH == 1'b1 && tstate[3] ) 
-        begin
-          RegDIH = RegBusB[15:8];
-          RegDIL = RegBusB[7:0];
-        end
-      else if (ExchangeDH == 1'b1 && tstate[4] ) 
-        begin
-          RegDIH = RegBusA_r[15:8];
-          RegDIL = RegBusA_r[7:0];
-        end
-      else if (IncDec_16[2] == 1'b1 && ((tstate[2] && ~mcycle[0]) || (tstate[3] && mcycle[0])) ) 
-        begin
-          RegDIH = ID16[15:8];
-          RegDIL = ID16[7:0];
-        end
-    end
-
-  tv80_reg i_reg
-    (
-     .clk                  (clk),
-     .CEN                  (ClkEn),
-     .WEH                  (RegWEH),
-     .WEL                  (RegWEL),
-     .AddrA                (RegAddrA),
-     .AddrB                (RegAddrB),
-     .AddrC                (RegAddrC),
-     .DIH                  (RegDIH),
-     .DIL                  (RegDIL),
-     .DOAH                 (RegBusA[15:8]),
-     .DOAL                 (RegBusA[7:0]),
-     .DOBH                 (RegBusB[15:8]),
-     .DOBL                 (RegBusB[7:0]),
-     .DOCH                 (RegBusC[15:8]),
-     .DOCL                 (RegBusC[7:0])
-     );
-
-  //-------------------------------------------------------------------------
-  //
-  // Buses
-  //
-  //-------------------------------------------------------------------------
-
-  always @ (posedge clk)
-    begin
-      if (ClkEn == 1'b1 ) 
-        begin
-          case (Set_BusB_To)
-            4'b0111 :
-              BusB <= #1 ACC;
-            4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
-              begin
-                if (Set_BusB_To[0] == 1'b1 ) 
-                  begin
-                    BusB <= #1 RegBusB[7:0];
-                  end 
-                else 
-                  begin
-                    BusB <= #1 RegBusB[15:8];
-                  end
-              end
-            4'b0110 :
-              BusB <= #1 DI_Reg;
-            4'b1000 :
-              BusB <= #1 SP[7:0];
-            4'b1001 :
-              BusB <= #1 SP[15:8];
-            4'b1010 :
-              BusB <= #1 8'b00000001;
-            4'b1011 :
-              BusB <= #1 F;
-            4'b1100 :
-              BusB <= #1 PC[7:0];
-            4'b1101 :
-              BusB <= #1 PC[15:8];
-            4'b1110 :
-              BusB <= #1 8'b00000000;
-            default :
-              BusB <= #1 8'h0;
-          endcase
-
-          case (Set_BusA_To)
-            4'b0111 :
-              BusA <= #1 ACC;
-            4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
-              begin
-                if (Set_BusA_To[0] == 1'b1 )
-                  begin
-                    BusA <= #1 RegBusA[7:0];
-                  end 
-                else 
-                  begin
-                    BusA <= #1 RegBusA[15:8];
-                  end
-              end
-            4'b0110 :
-              BusA <= #1 DI_Reg;
-            4'b1000 :
-              BusA <= #1 SP[7:0];
-            4'b1001 :
-              BusA <= #1 SP[15:8];
-            4'b1010 :
-              BusA <= #1 8'b00000000;
-            default :
-              BusA <= #1  8'h0;
-          endcase
-        end
-    end
-
-  //-------------------------------------------------------------------------
-  //
-  // Generate external control signals
-  //
-  //-------------------------------------------------------------------------
-`ifdef TV80_REFRESH
-  always @ (posedge clk or negedge reset_n)
-    begin
-      if (reset_n == 1'b0 ) 
-        begin
-          rfsh_n <= #1 1'b1;
-        end 
-      else
-        begin
-          if (cen == 1'b1 ) 
-            begin
-              if (mcycle[0] && ((tstate[2]  && wait_n == 1'b1) || tstate[3]) ) 
-                begin
-                  rfsh_n <= #1 1'b0;
-                end 
-              else 
-                begin
-                  rfsh_n <= #1 1'b1;
-                end
-            end
-        end
-    end // always @ (posedge clk or negedge reset_n)
-`else // !`ifdef TV80_REFRESH
-  assign rfsh_n = 1'b1;
-`endif  
-
-  always @(/*AUTOSENSE*/BusAck or Halt_FF or I_DJNZ or IntCycle
-	   or IntE_FF1 or di or iorq_i or mcycle or tstate)
-    begin
-      mc = mcycle;
-      ts = tstate;
-      DI_Reg = di;
-      halt_n = ~ Halt_FF;
-      busak_n = ~ BusAck;
-      intcycle_n = ~ IntCycle;
-      IntE = IntE_FF1;
-      iorq = iorq_i;
-      stop = I_DJNZ;
-    end
-
-  //-----------------------------------------------------------------------
-  //
-  // Syncronise inputs
-  //
-  //-----------------------------------------------------------------------
-
-  always @ (posedge clk or negedge reset_n)
-    begin : sync_inputs
-      if (~reset_n) 
-        begin
-          BusReq_s <= #1 1'b0;
-          INT_s <= #1 1'b0;
-          NMI_s <= #1 1'b0;
-          Oldnmi_n <= #1 1'b0;
-        end 
-      else
-        begin
-          if (cen == 1'b1 ) 
-            begin
-              BusReq_s <= #1 ~ busrq_n;
-              INT_s <= #1 ~ int_n;
-              if (NMICycle == 1'b1 ) 
-                begin
-                  NMI_s <= #1 1'b0;
-                end 
-              else if (nmi_n == 1'b0 && Oldnmi_n == 1'b1 ) 
-                begin
-                  NMI_s <= #1 1'b1;
-                end
-              Oldnmi_n <= #1 nmi_n;
-            end
-        end
-    end
-
-  //-----------------------------------------------------------------------
-  //
-  // Main state machine
-  //
-  //-----------------------------------------------------------------------
-
-  always @ (posedge clk or negedge reset_n)
-    begin
-      if (reset_n == 1'b0 ) 
-        begin
-          mcycle <= #1 7'b0000001;
-          tstate <= #1 7'b0000001;
-          Pre_XY_F_M <= #1 3'b000;
-          Halt_FF <= #1 1'b0;
-          BusAck <= #1 1'b0;
-          NMICycle <= #1 1'b0;
-          IntCycle <= #1 1'b0;
-          IntE_FF1 <= #1 1'b0;
-          IntE_FF2 <= #1 1'b0;
-          No_BTR <= #1 1'b0;
-          Auto_Wait_t1 <= #1 1'b0;
-          Auto_Wait_t2 <= #1 1'b0;
-          m1_n <= #1 1'b1;
-        end 
-      else
-        begin
-          if (cen == 1'b1 ) 
-            begin
-              if (T_Res == 1'b1 ) 
-                begin
-                  Auto_Wait_t1 <= #1 1'b0;
-                end 
-              else 
-                begin
-		  Auto_Wait_t1 <= #1 Auto_Wait || (iorq_i & ~Auto_Wait_t2);
-                end
-              Auto_Wait_t2 <= #1 Auto_Wait_t1 & !T_Res;
-              No_BTR <= #1 (I_BT && (~ IR[4] || ~ F[Flag_P])) ||
-                        (I_BC && (~ IR[4] || F[Flag_Z] || ~ F[Flag_P])) ||
-                        (I_BTR && (~ IR[4] || F[Flag_Z]));
-              if (tstate[2] ) 
-                begin
-                  if (SetEI == 1'b1 ) 
-                    begin
-                      if (!NMICycle)
-                        IntE_FF1 <= #1 1'b1;
-                      IntE_FF2 <= #1 1'b1;
-                    end
-                  if (I_RETN == 1'b1 ) 
-                    begin
-                      IntE_FF1 <= #1 IntE_FF2;
-                    end
-                end
-              if (tstate[3] ) 
-                begin
-                  if (SetDI == 1'b1 ) 
-                    begin
-                      IntE_FF1 <= #1 1'b0;
-                      IntE_FF2 <= #1 1'b0;
-                    end
-                end
-              if (IntCycle == 1'b1 || NMICycle == 1'b1 ) 
-                begin
-                  Halt_FF <= #1 1'b0;
-                end
-              if (mcycle[0] && tstate[2] && wait_n == 1'b1 ) 
-                begin
-                  m1_n <= #1 1'b1;
-                end
-              if (BusReq_s == 1'b1 && BusAck == 1'b1 ) 
-                begin
-                end 
-              else 
-                begin
-                  BusAck <= #1 1'b0;
-                  if (tstate[2] && wait_n == 1'b0 ) 
-                    begin
-                    end 
-                  else if (T_Res == 1'b1 ) 
-                    begin
-                      if (Halt == 1'b1 ) 
-                        begin
-                          Halt_FF <= #1 1'b1;
-                        end
-                      if (BusReq_s == 1'b1 ) 
-                        begin
-                          BusAck <= #1 1'b1;
-                        end 
-                      else 
-                        begin
-                          tstate <= #1 7'b0000010;
-                          if (NextIs_XY_Fetch == 1'b1 ) 
-                            begin
-                              mcycle <= #1 7'b0100000;
-                              Pre_XY_F_M <= #1 mcyc_to_number(mcycle);
-                              if (IR == 8'b00110110 && Mode == 0 ) 
-                                begin
-                                  Pre_XY_F_M <= #1 3'b010;
-                                end
-                            end 
-                          else if ((mcycle[6]) || (mcycle[5] && Mode == 1 && ISet != 2'b01) ) 
-                            begin
-                              mcycle <= #1 number_to_bitvec(Pre_XY_F_M + 1);
-                            end 
-                          else if ((last_mcycle) ||
-                                   No_BTR == 1'b1 ||
-                                   (mcycle[1] && I_DJNZ == 1'b1 && IncDecZ == 1'b1) ) 
-                            begin
-                              m1_n <= #1 1'b0;
-                              mcycle <= #1 7'b0000001;
-                              IntCycle <= #1 1'b0;
-                              NMICycle <= #1 1'b0;
-                              if (NMI_s == 1'b1 && Prefix == 2'b00 ) 
-                                begin
-                                  NMICycle <= #1 1'b1;
-                                  IntE_FF1 <= #1 1'b0;
-                                end 
-                              else if ((IntE_FF1 == 1'b1 && INT_s == 1'b1) && Prefix == 2'b00 && SetEI == 1'b0 ) 
-                                begin
-                                  IntCycle <= #1 1'b1;
-                                  IntE_FF1 <= #1 1'b0;
-                                  IntE_FF2 <= #1 1'b0;
-                                end
-                            end 
-                          else 
-                            begin
-                              mcycle <= #1 { mcycle[5:0], mcycle[6] };
-                            end
-                        end
-                    end 
-                  else 
-                    begin   // verilog has no "nor" operator
-                      if ( ~(Auto_Wait == 1'b1 && Auto_Wait_t2 == 1'b0) &&
-                           ~(IOWait == 1 && iorq_i == 1'b1 && Auto_Wait_t1 == 1'b0) ) 
-                        begin
-                          tstate <= #1 { tstate[5:0], tstate[6] };
-                        end
-                    end
-                end
-              if (tstate[0]) 
-                begin
-                  m1_n <= #1 1'b0;
-                end
-            end
-        end
-    end
-
-  always @(/*AUTOSENSE*/BTR_r or DI_Reg or IncDec_16 or JumpE or PC
-	   or RegBusA or RegBusC or SP or tstate)
-    begin
-      if (JumpE == 1'b1 ) 
-        begin
-          PC16_B = { {8{DI_Reg[7]}}, DI_Reg };
-        end 
-      else if (BTR_r == 1'b1 ) 
-        begin
-          PC16_B = -2;
-        end
-      else
-        begin
-          PC16_B = 1;
-        end
-
-      if (tstate[3])
-        begin
-          SP16_A = RegBusC;
-          SP16_B = { {8{DI_Reg[7]}}, DI_Reg };
-        end
-      else
-        begin
-          // suspect that ID16 and SP16 could be shared
-          SP16_A = SP;
-          
-          if (IncDec_16[3] == 1'b1)
-            SP16_B = -1;
-          else
-            SP16_B = 1;
-        end
-
-      if (IncDec_16[3])  
-        ID16_B = -1;
-      else
-        ID16_B = 1;
-
-      ID16 = RegBusA + ID16_B;
-      PC16 = PC + PC16_B;
-      SP16 = SP16_A + SP16_B;
-    end // always @ *
-  
-
-  always @(/*AUTOSENSE*/IntCycle or NMICycle or mcycle)
-    begin
-      Auto_Wait = 1'b0;
-      if (IntCycle == 1'b1 || NMICycle == 1'b1 ) 
-        begin
-          if (mcycle[0] ) 
-            begin
-              Auto_Wait = 1'b1;
-            end
-        end
-    end // always @ *
-  
-endmodule // T80
-
diff --git a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_mcode.v b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_mcode.v
deleted file mode 100644
index 40622d2b..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_mcode.v
+++ /dev/null
@@ -1,2650 +0,0 @@
-//
-// TV80 8-Bit Microprocessor Core
-// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
-//
-// Copyright (c) 2004,2007 Guy Hutchison (ghutchis@opencores.org)
-//
-// Permission is hereby granted, free of charge, to any person obtaining a 
-// copy of this software and associated documentation files (the "Software"), 
-// to deal in the Software without restriction, including without limitation 
-// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
-// and/or sell copies of the Software, and to permit persons to whom the 
-// Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included 
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-module tv80_mcode 
-  (/*AUTOARG*/
-  // Outputs
-  MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg, 
-  Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC, 
-  Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ, 
-  LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF, 
-  ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR, 
-  I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write, 
-  // Inputs
-  IR, ISet, MCycle, F, NMICycle, IntCycle
-  );
-  
-  parameter             Mode   = 0;
-  parameter             Flag_C = 0;
-  parameter             Flag_N = 1;
-  parameter             Flag_P = 2;
-  parameter             Flag_X = 3;
-  parameter             Flag_H = 4;
-  parameter             Flag_Y = 5;
-  parameter             Flag_Z = 6;
-  parameter             Flag_S = 7;
-
-  input [7:0]           IR;
-  input [1:0]           ISet                    ;
-  input [6:0]           MCycle                  ;
-  input [7:0]           F                       ;
-  input                 NMICycle                ;
-  input                 IntCycle                ;
-  output [2:0]          MCycles                 ;
-  output [2:0]          TStates                 ;
-  output [1:0]          Prefix                  ; // None,BC,ED,DD/FD
-  output                Inc_PC                  ;
-  output                Inc_WZ                  ;
-  output [3:0]          IncDec_16               ; // BC,DE,HL,SP   0 is inc
-  output                Read_To_Reg             ;
-  output                Read_To_Acc             ;
-  output [3:0]          Set_BusA_To     ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-  output [3:0]          Set_BusB_To     ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-  output [3:0]          ALU_Op                  ;
-  output                Save_ALU                ;
-  output                PreserveC               ;
-  output                Arith16                 ;
-  output [2:0]          Set_Addr_To             ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-  output                IORQ                    ;
-  output                Jump                    ;
-  output                JumpE                   ;
-  output                JumpXY                  ;
-  output                Call                    ;
-  output                RstP                    ;
-  output                LDZ                     ;
-  output                LDW                     ;
-  output                LDSPHL                  ;
-  output [2:0]          Special_LD              ; // A,I;A,R;I,A;R,A;None
-  output                ExchangeDH              ;
-  output                ExchangeRp              ;
-  output                ExchangeAF              ;
-  output                ExchangeRS              ;
-  output                I_DJNZ                  ;
-  output                I_CPL                   ;
-  output                I_CCF                   ;
-  output                I_SCF                   ;
-  output                I_RETN                  ;
-  output                I_BT                    ;
-  output                I_BC                    ;
-  output                I_BTR                   ;
-  output                I_RLD                   ;
-  output                I_RRD                   ;
-  output                I_INRC                  ;
-  output                SetDI                   ;
-  output                SetEI                   ;
-  output [1:0]          IMode                   ;
-  output                Halt                    ;
-  output                NoRead                  ;
-  output                Write   ;                
-
-  // regs
-  reg [2:0]             MCycles                 ;
-  reg [2:0]             TStates                 ;
-  reg [1:0]             Prefix                  ; // None,BC,ED,DD/FD
-  reg                   Inc_PC                  ;
-  reg                   Inc_WZ                  ;
-  reg [3:0]             IncDec_16               ; // BC,DE,HL,SP   0 is inc
-  reg                   Read_To_Reg             ;
-  reg                   Read_To_Acc             ;
-  reg [3:0]             Set_BusA_To     ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-  reg [3:0]             Set_BusB_To     ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-  reg [3:0]             ALU_Op                  ;
-  reg                   Save_ALU                ;
-  reg                   PreserveC               ;
-  reg                   Arith16                 ;
-  reg [2:0]             Set_Addr_To             ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-  reg                   IORQ                    ;
-  reg                   Jump                    ;
-  reg                   JumpE                   ;
-  reg                   JumpXY                  ;
-  reg                   Call                    ;
-  reg                   RstP                    ;
-  reg                   LDZ                     ;
-  reg                   LDW                     ;
-  reg                   LDSPHL                  ;
-  reg [2:0]             Special_LD              ; // A,I;A,R;I,A;R,A;None
-  reg                   ExchangeDH              ;
-  reg                   ExchangeRp              ;
-  reg                   ExchangeAF              ;
-  reg                   ExchangeRS              ;
-  reg                   I_DJNZ                  ;
-  reg                   I_CPL                   ;
-  reg                   I_CCF                   ;
-  reg                   I_SCF                   ;
-  reg                   I_RETN                  ;
-  reg                   I_BT                    ;
-  reg                   I_BC                    ;
-  reg                   I_BTR                   ;
-  reg                   I_RLD                   ;
-  reg                   I_RRD                   ;
-  reg                   I_INRC                  ;
-  reg                   SetDI                   ;
-  reg                   SetEI                   ;
-  reg [1:0]             IMode                   ;
-  reg                   Halt                    ;
-  reg                   NoRead                  ;
-  reg                   Write   ;                
-
-  parameter             aNone   = 3'b111;
-  parameter             aBC     = 3'b000;
-  parameter             aDE     = 3'b001;
-  parameter             aXY     = 3'b010;
-  parameter             aIOA    = 3'b100;
-  parameter             aSP     = 3'b101;
-  parameter             aZI     = 3'b110;
-  //    constant aNone  : std_logic_vector[2:0] = 3'b000;
-  //    constant aXY    : std_logic_vector[2:0] = 3'b001;
-  //    constant aIOA   : std_logic_vector[2:0] = 3'b010;
-  //    constant aSP    : std_logic_vector[2:0] = 3'b011;
-  //    constant aBC    : std_logic_vector[2:0] = 3'b100;
-  //    constant aDE    : std_logic_vector[2:0] = 3'b101;
-  //    constant aZI    : std_logic_vector[2:0] = 3'b110;
-
-  function is_cc_true;
-    input [7:0] FF;
-    input [2:0] cc;
-    begin
-      if (Mode == 3 ) 
-        begin
-          case (cc)
-            3'b000  : is_cc_true = FF[7] == 1'b0; // NZ
-            3'b001  : is_cc_true = FF[7] == 1'b1; // Z
-            3'b010  : is_cc_true = FF[4] == 1'b0; // NC
-            3'b011  : is_cc_true = FF[4] == 1'b1; // C
-            3'b100  : is_cc_true = 0;
-            3'b101  : is_cc_true = 0;
-            3'b110  : is_cc_true = 0;
-            3'b111  : is_cc_true = 0;
-          endcase
-        end 
-      else 
-        begin
-          case (cc)
-            3'b000  : is_cc_true = FF[6] == 1'b0; // NZ
-            3'b001  : is_cc_true = FF[6] == 1'b1; // Z
-            3'b010  : is_cc_true = FF[0] == 1'b0; // NC
-            3'b011  : is_cc_true = FF[0] == 1'b1; // C
-            3'b100  : is_cc_true = FF[2] == 1'b0; // PO
-            3'b101  : is_cc_true = FF[2] == 1'b1; // PE
-            3'b110  : is_cc_true = FF[7] == 1'b0; // P
-            3'b111  : is_cc_true = FF[7] == 1'b1; // M
-          endcase
-        end
-    end
-  endfunction // is_cc_true
-  
-
-  reg [2:0] DDD;
-  reg [2:0] SSS;
-  reg [1:0] DPAIR;
-  
-  always @ (/*AUTOSENSE*/F or IR or ISet or IntCycle or MCycle
-            or NMICycle)
-    begin
-      DDD = IR[5:3];
-      SSS = IR[2:0];
-      DPAIR = IR[5:4];
-
-      MCycles = 3'b001;
-      if (MCycle[0] ) 
-        begin
-          TStates = 3'b100;
-        end 
-      else 
-        begin
-          TStates = 3'b011;
-        end
-      Prefix = 2'b00;
-      Inc_PC = 1'b0;
-      Inc_WZ = 1'b0;
-      IncDec_16 = 4'b0000;
-      Read_To_Acc = 1'b0;
-      Read_To_Reg = 1'b0;
-      Set_BusB_To = 4'b0000;
-      Set_BusA_To = 4'b0000;
-      ALU_Op = { 1'b0, IR[5:3] };
-      Save_ALU = 1'b0;
-      PreserveC = 1'b0;
-      Arith16 = 1'b0;
-      IORQ = 1'b0;
-      Set_Addr_To = aNone;
-      Jump = 1'b0;
-      JumpE = 1'b0;
-      JumpXY = 1'b0;
-      Call = 1'b0;
-      RstP = 1'b0;
-      LDZ = 1'b0;
-      LDW = 1'b0;
-      LDSPHL = 1'b0;
-      Special_LD = 3'b000;
-      ExchangeDH = 1'b0;
-      ExchangeRp = 1'b0;
-      ExchangeAF = 1'b0;
-      ExchangeRS = 1'b0;
-      I_DJNZ = 1'b0;
-      I_CPL = 1'b0;
-      I_CCF = 1'b0;
-      I_SCF = 1'b0;
-      I_RETN = 1'b0;
-      I_BT = 1'b0;
-      I_BC = 1'b0;
-      I_BTR = 1'b0;
-      I_RLD = 1'b0;
-      I_RRD = 1'b0;
-      I_INRC = 1'b0;
-      SetDI = 1'b0;
-      SetEI = 1'b0;
-      IMode = 2'b11;
-      Halt = 1'b0;
-      NoRead = 1'b0;
-      Write = 1'b0;
-      
-      case (ISet)
-        2'b00  :
-          begin
-
-            //----------------------------------------------------------------------------
-            //
-            //  Unprefixed instructions
-            //
-            //----------------------------------------------------------------------------
-
-            casez (IR)
-              // 8 BIT LOAD GROUP
-              8'b01zzzzzz :
-                begin
-                  if (IR[5:0] == 6'b110110)
-                    Halt = 1'b1;
-                  else if (IR[2:0] == 3'b110)
-                    begin
-                      // LD r,(HL)
-                      MCycles = 3'b010;
-                      if (MCycle[0])
-                        Set_Addr_To = aXY;
-                      if (MCycle[1])
-                        begin
-                          Set_BusA_To[2:0] = DDD;
-                          Read_To_Reg = 1'b1;
-                        end
-                    end // if (IR[2:0] == 3'b110)
-                  else if (IR[5:3] == 3'b110)
-                    begin
-                      // LD (HL),r
-                      MCycles = 3'b010;
-                      if (MCycle[0])
-                        begin
-                          Set_Addr_To = aXY;
-                          Set_BusB_To[2:0] = SSS;
-                          Set_BusB_To[3] = 1'b0;
-                        end
-                      if (MCycle[1])
-                        Write = 1'b1;
-                    end // if (IR[5:3] == 3'b110)
-                  else
-                    begin
-                      Set_BusB_To[2:0] = SSS;
-                      ExchangeRp = 1'b1;
-                      Set_BusA_To[2:0] = DDD;
-                      Read_To_Reg = 1'b1;
-                    end // else: !if(IR[5:3] == 3'b110)
-                end // case: 8'b01zzzzzz                                    
-
-              8'b00zzz110 :
-                begin
-                  if (IR[5:3] == 3'b110)
-                    begin
-                      // LD (HL),n
-                      MCycles = 3'b011;
-                      if (MCycle[1])
-                        begin
-                          Inc_PC = 1'b1;
-                          Set_Addr_To = aXY;
-                          Set_BusB_To[2:0] = SSS;
-                          Set_BusB_To[3] = 1'b0;
-                        end
-                      if (MCycle[2])
-                        Write = 1'b1;
-                    end // if (IR[5:3] == 3'b110)
-                  else
-                    begin
-                      // LD r,n
-                      MCycles = 3'b010;
-                      if (MCycle[1])
-                        begin
-                          Inc_PC = 1'b1;
-                          Set_BusA_To[2:0] = DDD;
-                          Read_To_Reg = 1'b1;
-                        end
-                    end
-                end
-              
-              8'b00001010  :
-                begin
-                  // LD A,(BC)
-                  MCycles = 3'b010;
-                  if (MCycle[0])
-                    Set_Addr_To = aBC;
-                  if (MCycle[1])
-                    Read_To_Acc = 1'b1;
-                end // case: 8'b00001010
-              
-              8'b00011010  :
-                begin
-                  // LD A,(DE)
-                  MCycles = 3'b010;
-                  if (MCycle[0])
-                    Set_Addr_To = aDE;
-                  if (MCycle[1])
-                    Read_To_Acc = 1'b1;
-                end // case: 8'b00011010
-              
-              8'b00111010  :
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      // LDD A,(HL)
-                      MCycles = 3'b010;
-                      if (MCycle[0])
-                        Set_Addr_To = aXY;
-                      if (MCycle[1])
-                        begin
-                          Read_To_Acc = 1'b1;
-                          IncDec_16 = 4'b1110;
-                        end
-                    end 
-                  else 
-                    begin
-                      // LD A,(nn)
-                      MCycles = 3'b100;
-                      if (MCycle[1])
-                        begin
-                          Inc_PC = 1'b1;
-                          LDZ = 1'b1;
-                        end
-                      if (MCycle[2])
-                        begin
-                          Set_Addr_To = aZI;
-                          Inc_PC = 1'b1;
-                        end
-                      if (MCycle[3])
-                        begin
-                          Read_To_Acc = 1'b1;
-                        end
-                    end // else: !if(Mode == 3 )
-                end // case: 8'b00111010
-              
-              8'b00000010  :
-                begin
-                  // LD (BC),A
-                  MCycles = 3'b010;
-                  if (MCycle[0])
-                    begin
-                      Set_Addr_To = aBC;
-                      Set_BusB_To = 4'b0111;
-                    end
-                  if (MCycle[1])
-                    begin
-                      Write = 1'b1;
-                    end
-                end // case: 8'b00000010
-              
-              8'b00010010  :
-                begin
-                  // LD (DE),A
-                  MCycles = 3'b010;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        Set_Addr_To = aDE;
-                        Set_BusB_To = 4'b0111;
-                      end
-                    MCycle[1] :
-                      Write = 1'b1;
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b00010010
-              
-              8'b00110010  :
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      // LDD (HL),A
-                      MCycles = 3'b010;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          begin
-                            Set_Addr_To = aXY;
-                            Set_BusB_To = 4'b0111;
-                          end
-                        MCycle[1] :
-                          begin
-                            Write = 1'b1;
-                            IncDec_16 = 4'b1110;
-                          end
-                        default :;
-                      endcase // case(MCycle)
-                      
-                    end 
-                  else 
-                    begin
-                      // LD (nn),A
-                      MCycles = 3'b100;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDZ = 1'b1;
-                          end
-                        MCycle[2] :
-                          begin
-                            Set_Addr_To = aZI;
-                            Inc_PC = 1'b1;
-                            Set_BusB_To = 4'b0111;
-                          end
-                        MCycle[3] :
-                          begin
-                            Write = 1'b1;
-                          end
-                        default :;
-                      endcase
-                    end // else: !if(Mode == 3 )
-                end // case: 8'b00110010
-              
-
-              // 16 BIT LOAD GROUP
-              8'b00000001,8'b00010001,8'b00100001,8'b00110001  :
-                begin
-                  // LD dd,nn
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        Inc_PC = 1'b1;
-                        Read_To_Reg = 1'b1;
-                        if (DPAIR == 2'b11 ) 
-                          begin
-                            Set_BusA_To[3:0] = 4'b1000;
-                          end 
-                        else 
-                          begin
-                            Set_BusA_To[2:1] = DPAIR;
-                            Set_BusA_To[0] = 1'b1;
-                          end
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      begin
-                        Inc_PC = 1'b1;
-                        Read_To_Reg = 1'b1;
-                        if (DPAIR == 2'b11 ) 
-                          begin
-                            Set_BusA_To[3:0] = 4'b1001;
-                          end 
-                        else 
-                          begin
-                            Set_BusA_To[2:1] = DPAIR;
-                            Set_BusA_To[0] = 1'b0;
-                          end
-                      end // case: 3
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b00000001,8'b00010001,8'b00100001,8'b00110001
-              
-              8'b00101010  :
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      // LDI A,(HL)
-                      MCycles = 3'b010;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          Set_Addr_To = aXY;
-                        MCycle[1] :
-                          begin
-                            Read_To_Acc = 1'b1;
-                            IncDec_16 = 4'b0110;
-                          end
-                        
-                        default :;
-                      endcase
-                    end 
-                  else 
-                    begin
-                      // LD HL,(nn)
-                      MCycles = 3'b101;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDZ = 1'b1;
-                          end
-                        MCycle[2] :
-                          begin
-                            Set_Addr_To = aZI;
-                            Inc_PC = 1'b1;
-                            LDW = 1'b1;
-                          end
-                        MCycle[3] :
-                          begin
-                            Set_BusA_To[2:0] = 3'b101; // L
-                            Read_To_Reg = 1'b1;
-                            Inc_WZ = 1'b1;
-                            Set_Addr_To = aZI;
-                          end
-                        MCycle[4] :
-                          begin
-                            Set_BusA_To[2:0] = 3'b100; // H
-                            Read_To_Reg = 1'b1;
-                          end
-                        default :;
-                      endcase
-                    end // else: !if(Mode == 3 )
-                end // case: 8'b00101010
-              
-              8'b00100010  :
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      // LDI (HL),A
-                      MCycles = 3'b010;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          begin
-                            Set_Addr_To = aXY;
-                            Set_BusB_To = 4'b0111;
-                          end
-                        MCycle[1] :
-                          begin
-                            Write = 1'b1;
-                            IncDec_16 = 4'b0110;
-                          end
-                        default :;
-                      endcase
-                    end 
-                  else 
-                    begin
-                      // LD (nn),HL
-                      MCycles = 3'b101;
-                      case (1'b1) // MCycle                        
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDZ = 1'b1;
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            Set_Addr_To = aZI;
-                            Inc_PC = 1'b1;
-                            LDW = 1'b1;
-                            Set_BusB_To = 4'b0101; // L
-                          end
-                        
-                        MCycle[3] :
-                          begin
-                            Inc_WZ = 1'b1;
-                            Set_Addr_To = aZI;
-                            Write = 1'b1;
-                            Set_BusB_To = 4'b0100; // H
-                          end
-                        MCycle[4] :                          
-                          Write = 1'b1;
-                        default :;
-                      endcase
-                    end // else: !if(Mode == 3 )
-                end // case: 8'b00100010
-              
-              8'b11111001  :
-                begin
-                  // LD SP,HL
-                  TStates = 3'b110;
-                  LDSPHL = 1'b1;
-                end
-              
-              8'b11zz0101 :
-                begin
-                  // PUSH qq
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle                    
-                    MCycle[0] :
-                      begin
-                        TStates = 3'b101;
-                        IncDec_16 = 4'b1111;
-                        Set_Addr_To = aSP;
-                        if (DPAIR == 2'b11 ) 
-                          begin
-                            Set_BusB_To = 4'b0111;
-                          end 
-                        else
-                          begin
-                            Set_BusB_To[2:1] = DPAIR;
-                            Set_BusB_To[0] = 1'b0;
-                            Set_BusB_To[3] = 1'b0;
-                          end
-                      end // case: 1
-                    
-                    MCycle[1] :
-                      begin
-                        IncDec_16 = 4'b1111;
-                        Set_Addr_To = aSP;
-                        if (DPAIR == 2'b11 ) 
-                          begin
-                            Set_BusB_To = 4'b1011;
-                          end 
-                        else 
-                          begin
-                            Set_BusB_To[2:1] = DPAIR;
-                            Set_BusB_To[0] = 1'b1;
-                            Set_BusB_To[3] = 1'b0;
-                          end
-                        Write = 1'b1;
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      Write = 1'b1;
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101
-              
-              8'b11zz0001 :
-                begin
-                  // POP qq
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      Set_Addr_To = aSP;
-                    MCycle[1] :
-                      begin
-                        IncDec_16 = 4'b0111;
-                        Set_Addr_To = aSP;
-                        Read_To_Reg = 1'b1;
-                        if (DPAIR == 2'b11 ) 
-                          begin
-                            Set_BusA_To[3:0] = 4'b1011;
-                          end 
-                        else 
-                          begin
-                            Set_BusA_To[2:1] = DPAIR;
-                            Set_BusA_To[0] = 1'b1;
-                          end
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      begin
-                        IncDec_16 = 4'b0111;
-                        Read_To_Reg = 1'b1;
-                        if (DPAIR == 2'b11 ) 
-                          begin
-                            Set_BusA_To[3:0] = 4'b0111;
-                          end 
-                        else 
-                          begin
-                            Set_BusA_To[2:1] = DPAIR;
-                            Set_BusA_To[0] = 1'b0;
-                          end
-                      end // case: 3
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b11000001,8'b11010001,8'b11100001,8'b11110001
-              
-
-              // EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-              8'b11101011  :
-                begin
-                  if (Mode != 3 ) 
-                    begin
-                      // EX DE,HL
-                      ExchangeDH = 1'b1;
-                    end
-                end
-              
-              8'b00001000  :
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      // LD (nn),SP
-                      MCycles = 3'b101;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDZ = 1'b1;
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            Set_Addr_To = aZI;
-                            Inc_PC = 1'b1;
-                            LDW = 1'b1;
-                            Set_BusB_To = 4'b1000;
-                          end
-                        
-                        MCycle[3] :
-                          begin
-                            Inc_WZ = 1'b1;
-                            Set_Addr_To = aZI;
-                            Write = 1'b1;
-                            Set_BusB_To = 4'b1001;
-                          end
-                        
-                        MCycle[4] :
-                          Write = 1'b1;
-                        default :;
-                      endcase
-                    end 
-                  else if (Mode < 2 ) 
-                    begin
-                      // EX AF,AF'
-                      ExchangeAF = 1'b1;
-                    end
-                end // case: 8'b00001000
-              
-              8'b11011001  :
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      // RETI
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          Set_Addr_To = aSP;
-                        MCycle[1] :
-                          begin
-                            IncDec_16 = 4'b0111;
-                            Set_Addr_To = aSP;
-                            LDZ = 1'b1;
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            Jump = 1'b1;
-                            IncDec_16 = 4'b0111;
-                            I_RETN = 1'b1;
-                            SetEI = 1'b1;
-                          end
-                        default :;
-                      endcase
-                    end 
-                  else if (Mode < 2 ) 
-                    begin
-                      // EXX
-                      ExchangeRS = 1'b1;
-                    end
-                end // case: 8'b11011001
-              
-              8'b11100011  :
-                begin
-                  if (Mode != 3 ) 
-                    begin
-                      // EX (SP),HL
-                      MCycles = 3'b101;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          Set_Addr_To = aSP;
-                        MCycle[1] :
-                          begin
-                            Read_To_Reg = 1'b1;
-                            Set_BusA_To = 4'b0101;
-                            Set_BusB_To = 4'b0101;
-                            Set_Addr_To = aSP;
-                          end
-                        MCycle[2] :
-                          begin
-                            IncDec_16 = 4'b0111;
-                            Set_Addr_To = aSP;
-                            TStates = 3'b100;
-                            Write = 1'b1;
-                          end
-                        MCycle[3] :
-                          begin
-                            Read_To_Reg = 1'b1;
-                            Set_BusA_To = 4'b0100;
-                            Set_BusB_To = 4'b0100;
-                            Set_Addr_To = aSP;
-                          end
-                        MCycle[4] :
-                          begin
-                            IncDec_16 = 4'b1111;
-                            TStates = 3'b101;
-                            Write = 1'b1;
-                          end
-                        
-                        default :;
-                      endcase
-                    end // if (Mode != 3 )
-                end // case: 8'b11100011
-              
-
-              // 8 BIT ARITHMETIC AND LOGICAL GROUP
-              8'b10zzzzzz :
-                begin
-                  if (IR[2:0] == 3'b110)
-                    begin
-                      // ADD A,(HL)
-                      // ADC A,(HL)
-                      // SUB A,(HL)
-                      // SBC A,(HL)
-                      // AND A,(HL)
-                      // OR A,(HL)
-                      // XOR A,(HL)
-                      // CP A,(HL)
-                      MCycles = 3'b010;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          Set_Addr_To = aXY;
-                        MCycle[1] :
-                          begin
-                            Read_To_Reg = 1'b1;
-                            Save_ALU = 1'b1;
-                            Set_BusB_To[2:0] = SSS;
-                            Set_BusA_To[2:0] = 3'b111;
-                          end
-                        
-                        default :;
-                      endcase // case(MCycle)
-                    end // if (IR[2:0] == 3'b110)
-                  else
-                    begin
-                      // ADD A,r
-                      // ADC A,r
-                      // SUB A,r
-                      // SBC A,r
-                      // AND A,r
-                      // OR A,r
-                      // XOR A,r
-                      // CP A,r
-                      Set_BusB_To[2:0] = SSS;
-                      Set_BusA_To[2:0] = 3'b111;
-                      Read_To_Reg = 1'b1;
-                      Save_ALU = 1'b1;
-                    end // else: !if(IR[2:0] == 3'b110)                  
-                end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
-              
-              8'b11zzz110 :
-                begin
-                  // ADD A,n
-                  // ADC A,n
-                  // SUB A,n
-                  // SBC A,n
-                  // AND A,n
-                  // OR A,n
-                  // XOR A,n
-                  // CP A,n
-                  MCycles = 3'b010;
-                  if (MCycle[1] ) 
-                    begin
-                      Inc_PC = 1'b1;
-                      Read_To_Reg = 1'b1;
-                      Save_ALU = 1'b1;
-                      Set_BusB_To[2:0] = SSS;
-                      Set_BusA_To[2:0] = 3'b111;
-                    end
-                end
-              
-              8'b00zzz100 :
-                begin
-                  if (IR[5:3] == 3'b110)
-                    begin
-                      // INC (HL)
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          Set_Addr_To = aXY;
-                        MCycle[1] :
-                          begin
-                            TStates = 3'b100;
-                            Set_Addr_To = aXY;
-                            Read_To_Reg = 1'b1;
-                            Save_ALU = 1'b1;
-                            PreserveC = 1'b1;
-                            ALU_Op = 4'b0000;
-                            Set_BusB_To = 4'b1010;
-                            Set_BusA_To[2:0] = DDD;
-                          end // case: 2
-                        
-                        MCycle[2] :
-                          Write = 1'b1;
-                        default :;
-                      endcase // case(MCycle)
-                    end // case: 8'b00110100
-                  else
-                    begin
-                      // INC r
-                      Set_BusB_To = 4'b1010;
-                      Set_BusA_To[2:0] = DDD;
-                      Read_To_Reg = 1'b1;
-                      Save_ALU = 1'b1;
-                      PreserveC = 1'b1;
-                      ALU_Op = 4'b0000;
-                    end
-                end
-              
-              8'b00zzz101 :
-                begin               
-                  if (IR[5:3] == 3'b110)
-                    begin
-                      // DEC (HL)
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          Set_Addr_To = aXY;
-                        MCycle[1] :
-                          begin
-                            TStates = 3'b100;
-                            Set_Addr_To = aXY;
-                            ALU_Op = 4'b0010;
-                            Read_To_Reg = 1'b1;
-                            Save_ALU = 1'b1;
-                            PreserveC = 1'b1;
-                            Set_BusB_To = 4'b1010;
-                            Set_BusA_To[2:0] = DDD;
-                          end // case: 2
-                        
-                        MCycle[2] :
-                          Write = 1'b1;
-                        default :;
-                      endcase // case(MCycle)
-                    end
-                  else
-                    begin
-                      // DEC r
-                      Set_BusB_To = 4'b1010;
-                      Set_BusA_To[2:0] = DDD;
-                      Read_To_Reg = 1'b1;
-                      Save_ALU = 1'b1;
-                      PreserveC = 1'b1;
-                      ALU_Op = 4'b0010;
-                    end
-                end
-              
-              // GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-              8'b00100111  :
-                begin
-                  // DAA
-                  Set_BusA_To[2:0] = 3'b111;
-                  Read_To_Reg = 1'b1;
-                  ALU_Op = 4'b1100;
-                  Save_ALU = 1'b1;
-                end
-              
-              8'b00101111  :
-                // CPL
-                I_CPL = 1'b1;
-              
-              8'b00111111  :
-                // CCF
-                I_CCF = 1'b1;
-              
-              8'b00110111  :
-                // SCF
-                I_SCF = 1'b1;
-              
-              8'b00000000  :
-                begin
-                  if (NMICycle == 1'b1 ) 
-                    begin
-                      // NMI
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          begin
-                            TStates = 3'b101;
-                            IncDec_16 = 4'b1111;
-                            Set_Addr_To = aSP;
-                            Set_BusB_To = 4'b1101;
-                          end
-                        
-                        MCycle[1] :
-                          begin
-                            TStates = 3'b100;
-                            Write = 1'b1;
-                            IncDec_16 = 4'b1111;
-                            Set_Addr_To = aSP;
-                            Set_BusB_To = 4'b1100;
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            TStates = 3'b100;
-                            Write = 1'b1;
-                          end
-                        
-                        default :;
-                      endcase // case(MCycle)
-                      
-                    end 
-                  else if (IntCycle == 1'b1 ) 
-                    begin
-                      // INT (IM 2)
-                      MCycles = 3'b101;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          begin
-                            LDZ = 1'b1;
-                            TStates = 3'b101;
-                            IncDec_16 = 4'b1111;
-                            Set_Addr_To = aSP;
-                            Set_BusB_To = 4'b1101;
-                          end
-                        
-                        MCycle[1] :
-                          begin
-                            TStates = 3'b100;
-                            Write = 1'b1;
-                            IncDec_16 = 4'b1111;
-                            Set_Addr_To = aSP;
-                            Set_BusB_To = 4'b1100;
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            TStates = 3'b100;
-                            Write = 1'b1;
-                          end
-                        
-                        MCycle[3] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDZ = 1'b1;
-                          end
-                        
-                        MCycle[4] :
-                          Jump = 1'b1;
-                        default :;
-                      endcase
-                    end
-                end // case: 8'b00000000
-              
-              8'b11110011  :
-                // DI
-                SetDI = 1'b1;
-              
-              8'b11111011  :
-                // EI
-                SetEI = 1'b1;
-
-              // 16 BIT ARITHMETIC GROUP
-              8'b00zz1001  :
-                begin
-                  // ADD HL,ss
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        NoRead = 1'b1;
-                        ALU_Op = 4'b0000;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        Set_BusA_To[2:0] = 3'b101;
-                        case (IR[5:4])
-                          0,1,2  :
-                            begin
-                              Set_BusB_To[2:1] = IR[5:4];
-                              Set_BusB_To[0] = 1'b1;
-                            end
-                          
-                          default :
-                            Set_BusB_To = 4'b1000;
-                        endcase // case(IR[5:4])
-                        
-                        TStates = 3'b100;
-                        Arith16 = 1'b1;
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      begin
-                        NoRead = 1'b1;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        ALU_Op = 4'b0001;
-                        Set_BusA_To[2:0] = 3'b100;
-                        case (IR[5:4])
-                          0,1,2  :
-                            Set_BusB_To[2:1] = IR[5:4];
-                          default :
-                            Set_BusB_To = 4'b1001;
-                        endcase
-                        Arith16 = 1'b1;
-                      end // case: 3
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001              
-              
-              8'b00zz0011 :
-                begin
-                  // INC ss
-                  TStates = 3'b110;
-                  IncDec_16[3:2] = 2'b01;
-                  IncDec_16[1:0] = DPAIR;
-                end
-              
-              8'b00zz1011 :
-                begin
-                  // DEC ss
-                  TStates = 3'b110;
-                  IncDec_16[3:2] = 2'b11;
-                  IncDec_16[1:0] = DPAIR;
-                end
-
-              // ROTATE AND SHIFT GROUP
-              8'b00000111,
-                  // RLCA
-                  8'b00010111,
-                  // RLA
-                  8'b00001111,
-                  // RRCA
-                  8'b00011111 :
-                    // RRA
-                    begin
-                      Set_BusA_To[2:0] = 3'b111;
-                      ALU_Op = 4'b1000;
-                      Read_To_Reg = 1'b1;
-                      Save_ALU = 1'b1;
-                    end // case: 8'b00000111,...
-              
-
-              // JUMP GROUP
-              8'b11000011  :
-                begin
-                  // JP nn
-                  MCycles = 3'b011;
-                  if (MCycle[1])
-                    begin
-                      Inc_PC = 1'b1;
-                      LDZ = 1'b1;
-                    end
-                  
-                  if (MCycle[2])
-                    begin
-                      Inc_PC = 1'b1;
-                      Jump = 1'b1;
-                    end
-                  
-                end // case: 8'b11000011
-              
-              8'b11zzz010  :
-                begin
-                  if (IR[5] == 1'b1 && Mode == 3 ) 
-                    begin
-                      case (IR[4:3])
-                        2'b00  :
-                          begin
-                            // LD ($FF00+C),A
-                            MCycles = 3'b010;
-                            case (1'b1) // MCycle
-                              MCycle[0] :
-                                begin
-                                  Set_Addr_To = aBC;
-                                  Set_BusB_To   = 4'b0111;
-                                end
-                              MCycle[1] :
-                                begin
-                                  Write = 1'b1;
-                                  IORQ = 1'b1;
-                                end
-                              
-                              default :;
-                            endcase // case(MCycle)
-                          end // case: 2'b00
-                        
-                        2'b01  :
-                          begin
-                            // LD (nn),A
-                            MCycles = 3'b100;
-                            case (1'b1) // MCycle
-                              MCycle[1] :
-                                begin
-                                  Inc_PC = 1'b1;
-                                  LDZ = 1'b1;
-                                end
-                              
-                              MCycle[2] :
-                                begin
-                                  Set_Addr_To = aZI;
-                                  Inc_PC = 1'b1;
-                                  Set_BusB_To = 4'b0111;
-                                end
-                              
-                              MCycle[3] :
-                                Write = 1'b1;
-                              default :;
-                            endcase // case(MCycle)
-                          end // case: default :...
-                        
-                        2'b10  :
-                          begin
-                            // LD A,($FF00+C)
-                            MCycles = 3'b010;
-                            case (1'b1) // MCycle
-                              MCycle[0] :
-                                Set_Addr_To = aBC;
-                              MCycle[1] :
-                                begin
-                                  Read_To_Acc = 1'b1;
-                                  IORQ = 1'b1;
-                                end
-                              default :;
-                            endcase // case(MCycle)
-                          end // case: 2'b10
-                        
-                        2'b11  :
-                          begin
-                            // LD A,(nn)
-                            MCycles = 3'b100;
-                            case (1'b1) // MCycle
-                              MCycle[1] :
-                                begin
-                                  Inc_PC = 1'b1;
-                                  LDZ = 1'b1;
-                                end
-                              MCycle[2] :
-                                begin
-                                  Set_Addr_To = aZI;
-                                  Inc_PC = 1'b1;
-                                end
-                              MCycle[3] :
-                                Read_To_Acc = 1'b1;
-                              default :;
-                            endcase // case(MCycle)
-                          end
-                      endcase
-                    end 
-                  else 
-                    begin
-                      // JP cc,nn
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDZ = 1'b1;
-                          end
-                        MCycle[2] :
-                          begin
-                            Inc_PC = 1'b1;
-                            if (is_cc_true(F, IR[5:3]) ) 
-                              begin
-                                Jump = 1'b1;
-                              end
-                          end
-                        
-                        default :;
-                      endcase
-                    end // else: !if(DPAIR == 2'b11 )
-                end // case: 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010
-              
-              8'b00011000  :
-                begin
-                  if (Mode != 2 ) 
-                    begin
-                      // JR e
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          Inc_PC = 1'b1;
-                        MCycle[2] :
-                          begin
-                            NoRead = 1'b1;
-                            JumpE = 1'b1;
-                            TStates = 3'b101;
-                          end
-                        default :;
-                      endcase
-                    end // if (Mode != 2 )
-                end // case: 8'b00011000
-
-              // Conditional relative jumps (JR [C/NC/Z/NZ], e)
-              8'b001zz000  :
-                begin
-                  if (Mode != 2 ) 
-                    begin
-                      MCycles = 3'd3;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-
-                            case (IR[4:3])
-                              0 : MCycles = (F[Flag_Z]) ? 3'd2 : 3'd3;
-                              1 : MCycles = (!F[Flag_Z]) ? 3'd2 : 3'd3;
-                              2 : MCycles = (F[Flag_C]) ? 3'd2 : 3'd3;
-                              3 : MCycles = (!F[Flag_C]) ? 3'd2 : 3'd3;
-                            endcase
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            NoRead = 1'b1;
-                            JumpE = 1'b1;
-                            TStates = 3'd5;
-                          end
-                        default :;
-                      endcase
-                    end // if (Mode != 2 )
-                end // case: 8'b00111000              
-              
-              8'b11101001  :
-                // JP (HL)
-                JumpXY = 1'b1;
-              
-              8'b00010000  :
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      I_DJNZ = 1'b1;
-                    end 
-                  else if (Mode < 2 ) 
-                    begin
-                      // DJNZ,e
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          begin
-                            TStates = 3'b101;
-                            I_DJNZ = 1'b1;
-                            Set_BusB_To = 4'b1010;
-                            Set_BusA_To[2:0] = 3'b000;
-                            Read_To_Reg = 1'b1;
-                            Save_ALU = 1'b1;
-                            ALU_Op = 4'b0010;
-                          end
-                        MCycle[1] :
-                          begin
-                            I_DJNZ = 1'b1;
-                            Inc_PC = 1'b1;
-                          end
-                        MCycle[2] :
-                          begin
-                            NoRead = 1'b1;
-                            JumpE = 1'b1;
-                            TStates = 3'b101;
-                          end
-                        default :;
-                      endcase
-                    end // if (Mode < 2 )
-                end // case: 8'b00010000
-              
-
-              // CALL AND RETURN GROUP
-              8'b11001101  :
-                begin
-                  // CALL nn
-                  MCycles = 3'b101;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        Inc_PC = 1'b1;
-                        LDZ = 1'b1;
-                      end
-                    MCycle[2] :
-                      begin
-                        IncDec_16 = 4'b1111;
-                        Inc_PC = 1'b1;
-                        TStates = 3'b100;
-                        Set_Addr_To = aSP;
-                        LDW = 1'b1;
-                        Set_BusB_To = 4'b1101;
-                      end
-                    MCycle[3] :
-                      begin
-                        Write = 1'b1;
-                        IncDec_16 = 4'b1111;
-                        Set_Addr_To = aSP;
-                        Set_BusB_To = 4'b1100;
-                      end
-                    MCycle[4] :
-                      begin
-                        Write = 1'b1;
-                        Call = 1'b1;
-                      end
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b11001101
-              
-              8'b11zzz100  :
-                begin
-                  if (IR[5] == 1'b0 || Mode != 3 ) 
-                    begin
-                      // CALL cc,nn
-                      MCycles = 3'b101;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDZ = 1'b1;
-                          end
-                        MCycle[2] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDW = 1'b1;
-                            if (is_cc_true(F, IR[5:3]) ) 
-                              begin
-                                IncDec_16 = 4'b1111;
-                                Set_Addr_To = aSP;
-                                TStates = 3'b100;
-                                Set_BusB_To = 4'b1101;
-                              end 
-                            else 
-                              begin
-                                MCycles = 3'b011;
-                              end // else: !if(is_cc_true(F, IR[5:3]) )
-                          end // case: 3
-                        
-                        MCycle[3] :
-                          begin
-                            Write = 1'b1;
-                            IncDec_16 = 4'b1111;
-                            Set_Addr_To = aSP;
-                            Set_BusB_To = 4'b1100;
-                          end
-                        
-                        MCycle[4] :
-                          begin
-                            Write = 1'b1;
-                            Call = 1'b1;
-                          end
-                        
-                        default :;
-                      endcase
-                    end // if (IR[5] == 1'b0 || Mode != 3 )
-                end // case: 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100
-              
-              8'b11001001  :
-                begin
-                  // RET
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        TStates = 3'b101;
-                        Set_Addr_To = aSP;
-                      end
-                    
-                    MCycle[1] :
-                      begin
-                        IncDec_16 = 4'b0111;
-                        Set_Addr_To = aSP;
-                        LDZ = 1'b1;
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        Jump = 1'b1;
-                        IncDec_16 = 4'b0111;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b11001001
-              
-              8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000  :
-                begin                  
-                  if (IR[5] == 1'b1 && Mode == 3 ) 
-                    begin
-                      case (IR[4:3])
-                        2'b00  :
-                          begin
-                            // LD ($FF00+nn),A
-                            MCycles = 3'b011;
-                            case (1'b1) // MCycle
-                              MCycle[1] :
-                                begin
-                                  Inc_PC = 1'b1;
-                                  Set_Addr_To = aIOA;
-                                  Set_BusB_To   = 4'b0111;
-                                end
-                              
-                              MCycle[2] :
-                                Write = 1'b1;
-                              default :;
-                            endcase // case(MCycle)
-                          end // case: 2'b00
-                        
-                        2'b01  :
-                          begin
-                            // ADD SP,n
-                            MCycles = 3'b011;
-                            case (1'b1) // MCycle
-                              MCycle[1] :
-                                begin
-                                  ALU_Op = 4'b0000;
-                                  Inc_PC = 1'b1;
-                                  Read_To_Reg = 1'b1;
-                                  Save_ALU = 1'b1;
-                                  Set_BusA_To = 4'b1000;
-                                  Set_BusB_To = 4'b0110;
-                                end
-                              
-                              MCycle[2] :
-                                begin
-                                  NoRead = 1'b1;
-                                  Read_To_Reg = 1'b1;
-                                  Save_ALU = 1'b1;
-                                  ALU_Op = 4'b0001;
-                                  Set_BusA_To = 4'b1001;
-                                  Set_BusB_To = 4'b1110;        // Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-                                end
-                              
-                              default :;
-                            endcase // case(MCycle)
-                          end // case: 2'b01
-                        
-                        2'b10  :
-                          begin
-                            // LD A,($FF00+nn)
-                            MCycles = 3'b011;
-                            case (1'b1) // MCycle
-                              MCycle[1] :
-                                begin
-                                  Inc_PC = 1'b1;
-                                  Set_Addr_To = aIOA;
-                                end
-                              
-                              MCycle[2] :
-                                Read_To_Acc = 1'b1;
-                              default :;
-                            endcase // case(MCycle)
-                          end // case: 2'b10
-                        
-                        2'b11  :
-                          begin
-                            // LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-                            MCycles = 3'b101;
-                            case (1'b1) // MCycle
-                              MCycle[1] :
-                                begin
-                                  Inc_PC = 1'b1;
-                                  LDZ = 1'b1;
-                                end
-                              
-                              MCycle[2] :
-                                begin
-                                  Set_Addr_To = aZI;
-                                  Inc_PC = 1'b1;
-                                  LDW = 1'b1;
-                                end
-                              
-                              MCycle[3] :
-                                begin
-                                  Set_BusA_To[2:0] = 3'b101; // L
-                                  Read_To_Reg = 1'b1;
-                                  Inc_WZ = 1'b1;
-                                  Set_Addr_To = aZI;
-                                end
-                              
-                              MCycle[4] :
-                                begin
-                                  Set_BusA_To[2:0] = 3'b100; // H
-                                  Read_To_Reg = 1'b1;
-                                end
-                              
-                              default :;
-                            endcase // case(MCycle)
-                          end // case: 2'b11
-                        
-                      endcase // case(IR[4:3])
-                      
-                    end 
-                  else 
-                    begin
-                      // RET cc
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          begin
-                            if (is_cc_true(F, IR[5:3]) )                              
-                              begin
-                                Set_Addr_To = aSP;
-                              end 
-                            else 
-                              begin
-                                MCycles = 3'b001;
-                              end
-                            TStates = 3'b101;
-                          end // case: 1
-                        
-                        MCycle[1] :
-                          begin
-                            IncDec_16 = 4'b0111;
-                            Set_Addr_To = aSP;
-                            LDZ = 1'b1;
-                          end
-                        MCycle[2] :
-                          begin
-                            Jump = 1'b1;
-                            IncDec_16 = 4'b0111;
-                          end
-                        default :;
-                      endcase
-                    end // else: !if(IR[5] == 1'b1 && Mode == 3 )
-                end // case: 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000
-              
-              8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111  :
-                begin
-                  // RST p
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        TStates = 3'b101;
-                        IncDec_16 = 4'b1111;
-                        Set_Addr_To = aSP;
-                        Set_BusB_To = 4'b1101;
-                      end
-                    
-                    MCycle[1] :
-                      begin
-                        Write = 1'b1;
-                        IncDec_16 = 4'b1111;
-                        Set_Addr_To = aSP;
-                        Set_BusB_To = 4'b1100;
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        Write = 1'b1;
-                        RstP = 1'b1;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111
-              
-              // INPUT AND OUTPUT GROUP
-              8'b11011011  :
-                begin
-                  if (Mode != 3 ) 
-                    begin
-                      // IN A,(n)
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            Set_Addr_To = aIOA;
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            Read_To_Acc = 1'b1;
-                            IORQ = 1'b1;
-                          end
-                        
-                        default :;
-                      endcase
-                    end // if (Mode != 3 )
-                end // case: 8'b11011011
-              
-              8'b11010011  :
-                begin
-                  if (Mode != 3 ) 
-                    begin
-                      // OUT (n),A
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            Set_Addr_To = aIOA;
-                            Set_BusB_To = 4'b0111;
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            Write = 1'b1;
-                            IORQ = 1'b1;
-                          end
-                        
-                        default :;
-                      endcase
-                    end // if (Mode != 3 )
-                end // case: 8'b11010011
-              
-
-              //----------------------------------------------------------------------------
-              //----------------------------------------------------------------------------
-              // MULTIBYTE INSTRUCTIONS
-              //----------------------------------------------------------------------------
-              //----------------------------------------------------------------------------
-
-              8'b11001011  :
-                begin
-                  if (Mode != 2 ) 
-                    begin
-                      Prefix = 2'b01;
-                    end
-                end              
-
-              8'b11101101  :
-                begin
-                  if (Mode < 2 ) 
-                    begin
-                      Prefix = 2'b10;
-                    end
-                end
-
-              8'b11011101,8'b11111101  :
-                begin
-                  if (Mode < 2 ) 
-                    begin
-                      Prefix = 2'b11;
-                    end
-                end
-              
-            endcase // case(IR)
-          end // case: 2'b00
-        
-
-        2'b01  :
-          begin
-            
-
-            //----------------------------------------------------------------------------
-            //
-            //  CB prefixed instructions
-            //
-            //----------------------------------------------------------------------------
-            
-            Set_BusA_To[2:0] = IR[2:0];
-            Set_BusB_To[2:0] = IR[2:0];
-            
-            casez (IR)
-              8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,
-              8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111,
-              8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111,
-              8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111,
-              8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111,
-              8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111,
-              8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111,
-              8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 :
-                begin
-                  // RLC r
-                  // RL r
-                  // RRC r
-                  // RR r
-                  // SLA r
-                  // SRA r
-                  // SRL r
-                  // SLL r (Undocumented) / SWAP r
-                  if (MCycle[0] ) begin
-                    ALU_Op = 4'b1000;
-                    Read_To_Reg = 1'b1;
-                    Save_ALU = 1'b1;
-                  end
-                end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,...
-              
-              8'b00zzz110  :
-                begin
-                  // RLC (HL)
-                  // RL (HL)
-                  // RRC (HL)
-                  // RR (HL)
-                  // SRA (HL)
-                  // SRL (HL)
-                  // SLA (HL)
-                  // SLL (HL) (Undocumented) / SWAP (HL)
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[0], MCycle[6] :
-                      Set_Addr_To = aXY;
-                    MCycle[1] :
-                      begin
-                        ALU_Op = 4'b1000;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        Set_Addr_To = aXY;
-                        TStates = 3'b100;
-                      end
-                    
-                    MCycle[2] :
-                      Write = 1'b1;
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110
-              
-              8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,
-                  8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111,
-                  8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111,
-                  8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111,
-                  8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111,
-                  8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111,
-                  8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111,
-                  8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 :
-                    begin
-                      // BIT b,r
-                      if (MCycle[0] )
-                        begin
-                          Set_BusB_To[2:0] = IR[2:0];
-                          ALU_Op = 4'b1001;
-                        end
-                    end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,...
-              
-              8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110  :
-                begin
-                  // BIT b,(HL)
-                  MCycles = 3'b010;
-                  case (1'b1) // MCycle
-                    MCycle[0], MCycle[6] :
-                      Set_Addr_To = aXY;
-                    MCycle[1] :
-                      begin
-                        ALU_Op = 4'b1001;
-                        TStates = 3'b100;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110
-              
-              8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,
-                  8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111,
-                  8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111,
-                  8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111,
-                  8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111,
-                  8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111,
-                  8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111,
-                  8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 :
-                    begin
-                      // SET b,r
-                      if (MCycle[0] ) 
-                        begin
-                          ALU_Op = 4'b1010;
-                          Read_To_Reg = 1'b1;
-                          Save_ALU = 1'b1;
-                        end
-                    end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,...
-              
-              8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110  :
-                begin
-                  // SET b,(HL)
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[0], MCycle[6] :
-                      Set_Addr_To = aXY;
-                    MCycle[1] :
-                      begin
-                        ALU_Op = 4'b1010;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        Set_Addr_To = aXY;
-                        TStates = 3'b100;
-                      end
-                    MCycle[2] :
-                      Write = 1'b1;
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110
-              
-              8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,
-                  8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111,
-                  8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111,
-                  8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111,
-                  8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111,
-                  8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111,
-                  8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111,
-                  8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 :
-                    begin
-                      // RES b,r
-                      if (MCycle[0] ) 
-                        begin
-                          ALU_Op = 4'b1011;
-                          Read_To_Reg = 1'b1;
-                          Save_ALU = 1'b1;
-                        end
-                    end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
-              
-              8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110  :
-                begin
-                  // RES b,(HL)
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[0], MCycle[6] :
-                      Set_Addr_To = aXY;
-                    MCycle[1] :
-                      begin
-                        ALU_Op = 4'b1011;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        Set_Addr_To = aXY;
-                        TStates = 3'b100;
-                      end
-                    
-                    MCycle[2] :
-                      Write = 1'b1;
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110
-              
-            endcase // case(IR)
-          end // case: 2'b01
-        
-        
-        default :
-          begin : default_ed_block
-            
-            //----------------------------------------------------------------------------
-            //
-            //  ED prefixed instructions
-            //
-            //----------------------------------------------------------------------------
-
-            casez (IR)
-	      /*
-	       * Undocumented NOP instructions commented out to reduce size of mcode
-	       *
-              8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111
-                ,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111
-                  ,8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010110,8'b00010111
-                    ,8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011110,8'b00011111
-                      ,8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100110,8'b00100111
-                        ,8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101110,8'b00101111
-                          ,8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110110,8'b00110111
-                            ,8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111110,8'b00111111
-                
-
-                              ,8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000110,8'b10000111
-                                ,8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001110,8'b10001111
-                                  ,8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010110,8'b10010111
-                                    ,8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011110,8'b10011111
-                                      ,                                            8'b10100100,8'b10100101,8'b10100110,8'b10100111
-                                        ,                                            8'b10101100,8'b10101101,8'b10101110,8'b10101111
-                                          ,                                            8'b10110100,8'b10110101,8'b10110110,8'b10110111
-                                            ,                                            8'b10111100,8'b10111101,8'b10111110,8'b10111111
-                                              ,8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000110,8'b11000111
-                                                ,8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001110,8'b11001111
-                                                  ,8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010110,8'b11010111
-                                                    ,8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011110,8'b11011111
-                                                      ,8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100110,8'b11100111
-                                                        ,8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101110,8'b11101111
-                                                          ,8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110110,8'b11110111
-                                                            ,8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111110,8'b11111111 :
-                                                              ; // NOP, undocumented
-              
-              8'b01111110,8'b01111111  :
-                // NOP, undocumented
-                ;
-	       */
-	      
-              // 8 BIT LOAD GROUP
-              8'b01010111  :
-                begin
-                  // LD A,I
-                  Special_LD = 3'b100;
-                  TStates = 3'b101;
-                end
-              
-              8'b01011111  :
-                begin
-                  // LD A,R
-                  Special_LD = 3'b101;
-                  TStates = 3'b101;
-                end
-              
-              8'b01000111  :
-                begin
-                  // LD I,A
-                  Special_LD = 3'b110;
-                  TStates = 3'b101;
-                end
-              
-              8'b01001111  :
-                begin
-                  // LD R,A
-                  Special_LD = 3'b111;
-                  TStates = 3'b101;
-                end
-              
-              // 16 BIT LOAD GROUP
-              8'b01001011,8'b01011011,8'b01101011,8'b01111011  :
-                begin
-                  // LD dd,(nn)
-                  MCycles = 3'b101;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        Inc_PC = 1'b1;
-                        LDZ = 1'b1;
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        Set_Addr_To = aZI;
-                        Inc_PC = 1'b1;
-                        LDW = 1'b1;
-                      end
-                    
-                    MCycle[3] :
-                      begin
-                        Read_To_Reg = 1'b1;
-                        if (IR[5:4] == 2'b11 ) 
-                          begin
-                            Set_BusA_To = 4'b1000;
-                          end 
-                        else 
-                          begin
-                            Set_BusA_To[2:1] = IR[5:4];
-                            Set_BusA_To[0] = 1'b1;
-                          end
-                        Inc_WZ = 1'b1;
-                        Set_Addr_To = aZI;
-                      end // case: 4
-                    
-                    MCycle[4] :
-                      begin
-                        Read_To_Reg = 1'b1;
-                        if (IR[5:4] == 2'b11 ) 
-                          begin
-                            Set_BusA_To = 4'b1001;
-                          end 
-                        else 
-                          begin
-                            Set_BusA_To[2:1] = IR[5:4];
-                            Set_BusA_To[0] = 1'b0;
-                          end
-                      end // case: 5
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011
-              
-              
-              8'b01000011,8'b01010011,8'b01100011,8'b01110011  :
-                begin
-                  // LD (nn),dd
-                  MCycles = 3'b101;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        Inc_PC = 1'b1;
-                        LDZ = 1'b1;
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        Set_Addr_To = aZI;
-                        Inc_PC = 1'b1;
-                        LDW = 1'b1;
-                        if (IR[5:4] == 2'b11 ) 
-                          begin
-                            Set_BusB_To = 4'b1000;
-                          end 
-                        else 
-                          begin
-                            Set_BusB_To[2:1] = IR[5:4];
-                            Set_BusB_To[0] = 1'b1;
-                            Set_BusB_To[3] = 1'b0;
-                          end
-                      end // case: 3
-                    
-                    MCycle[3] :
-                      begin
-                        Inc_WZ = 1'b1;
-                        Set_Addr_To = aZI;
-                        Write = 1'b1;
-                        if (IR[5:4] == 2'b11 ) 
-                          begin
-                            Set_BusB_To = 4'b1001;
-                          end 
-                        else 
-                          begin
-                            Set_BusB_To[2:1] = IR[5:4];
-                            Set_BusB_To[0] = 1'b0;
-                            Set_BusB_To[3] = 1'b0;
-                          end
-                      end // case: 4
-                    
-                    MCycle[4] :
-                      begin
-                        Write = 1'b1;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011
-              
-              8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000  :
-                begin
-                  // LDI, LDD, LDIR, LDDR
-                  MCycles = 3'b100;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        Set_Addr_To = aXY;
-                        IncDec_16 = 4'b1100; // BC
-                      end
-                    
-                    MCycle[1] :
-                      begin
-                        Set_BusB_To = 4'b0110;
-                        Set_BusA_To[2:0] = 3'b111;
-                        ALU_Op = 4'b0000;
-                        Set_Addr_To = aDE;
-                        if (IR[3] == 1'b0 ) 
-                          begin
-                            IncDec_16 = 4'b0110; // IX
-                          end 
-                        else 
-                          begin
-                            IncDec_16 = 4'b1110;
-                          end
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      begin
-                        I_BT = 1'b1;
-                        TStates = 3'b101;
-                        Write = 1'b1;
-                        if (IR[3] == 1'b0 ) 
-                          begin
-                            IncDec_16 = 4'b0101; // DE
-                          end 
-                        else 
-                          begin
-                            IncDec_16 = 4'b1101;
-                          end
-                      end // case: 3
-                    
-                    MCycle[3] :
-                      begin
-                        NoRead = 1'b1;
-                        TStates = 3'b101;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000
-              
-              8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001  :
-                begin
-                  // CPI, CPD, CPIR, CPDR
-                  MCycles = 3'b100;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        Set_Addr_To = aXY;
-                        IncDec_16 = 4'b1100; // BC
-                      end
-                    
-                    MCycle[1] :
-                      begin
-                        Set_BusB_To = 4'b0110;
-                        Set_BusA_To[2:0] = 3'b111;
-                        ALU_Op = 4'b0111;
-                        Save_ALU = 1'b1;
-                        PreserveC = 1'b1;
-                        if (IR[3] == 1'b0 ) 
-                          begin
-                            IncDec_16 = 4'b0110;
-                          end 
-                        else 
-                          begin
-                            IncDec_16 = 4'b1110;
-                          end
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      begin
-                        NoRead = 1'b1;
-                        I_BC = 1'b1;
-                        TStates = 3'b101;
-                      end
-                    
-                    MCycle[3] :
-                      begin
-                        NoRead = 1'b1;
-                        TStates = 3'b101;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001
-              
-              8'b01000100,8'b01001100,8'b01010100,8'b01011100,8'b01100100,8'b01101100,8'b01110100,8'b01111100  :
-                begin
-                  // NEG
-                  ALU_Op = 4'b0010;
-                  Set_BusB_To = 4'b0111;
-                  Set_BusA_To = 4'b1010;
-                  Read_To_Acc = 1'b1;
-                  Save_ALU = 1'b1;
-                end
-              
-              8'b01000110,8'b01001110,8'b01100110,8'b01101110  :
-                begin
-                  // IM 0
-                  IMode = 2'b00;
-                end
-              
-              8'b01010110,8'b01110110  :
-                // IM 1
-                IMode = 2'b01;
-              
-              8'b01011110,8'b01110111  :
-                // IM 2
-                IMode = 2'b10;
-              
-              // 16 bit arithmetic
-              8'b01001010,8'b01011010,8'b01101010,8'b01111010  :
-                begin
-                  // ADC HL,ss
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        NoRead = 1'b1;
-                        ALU_Op = 4'b0001;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        Set_BusA_To[2:0] = 3'b101;
-                        case (IR[5:4])
-                          0,1,2  :
-                            begin
-                              Set_BusB_To[2:1] = IR[5:4];
-                              Set_BusB_To[0] = 1'b1;
-                            end
-                          default :
-                            Set_BusB_To = 4'b1000;
-                        endcase
-                        TStates = 3'b100;
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      begin
-                        NoRead = 1'b1;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        ALU_Op = 4'b0001;
-                        Set_BusA_To[2:0] = 3'b100;
-                        case (IR[5:4])
-                          0,1,2  :
-                            begin
-                              Set_BusB_To[2:1] = IR[5:4];
-                              Set_BusB_To[0] = 1'b0;
-                            end
-                          default :
-                            Set_BusB_To = 4'b1001;
-                        endcase // case(IR[5:4])
-                      end // case: 3
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010
-              
-              8'b01000010,8'b01010010,8'b01100010,8'b01110010  :
-                begin
-                  // SBC HL,ss
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        NoRead = 1'b1;
-                        ALU_Op = 4'b0011;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        Set_BusA_To[2:0] = 3'b101;
-                        case (IR[5:4])
-                          0,1,2  :
-                            begin
-                              Set_BusB_To[2:1] = IR[5:4];
-                              Set_BusB_To[0] = 1'b1;
-                            end
-                          default :
-                            Set_BusB_To = 4'b1000;
-                        endcase
-                        TStates = 3'b100;
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      begin
-                        NoRead = 1'b1;
-                        ALU_Op = 4'b0011;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        Set_BusA_To[2:0] = 3'b100;
-                        case (IR[5:4])
-                          0,1,2  :
-                            Set_BusB_To[2:1] = IR[5:4];
-                          default :
-                            Set_BusB_To = 4'b1001;
-                        endcase
-                      end // case: 3
-                    
-                    default :;
-                    
-                  endcase // case(MCycle)
-                end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010
-              
-              8'b01101111  :
-                begin
-                  // RLD
-                  MCycles = 3'b100;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        NoRead = 1'b1;
-                        Set_Addr_To = aXY;
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        Read_To_Reg = 1'b1;
-                        Set_BusB_To[2:0] = 3'b110;
-                        Set_BusA_To[2:0] = 3'b111;
-                        ALU_Op = 4'b1101;
-                        TStates = 3'b100;
-                        Set_Addr_To = aXY;
-                        Save_ALU = 1'b1;
-                      end
-                    
-                    MCycle[3] :
-                      begin
-                        I_RLD = 1'b1;
-                        Write = 1'b1;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01101111
-              
-              8'b01100111  :
-                begin
-                  // RRD
-                  MCycles = 3'b100;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      Set_Addr_To = aXY;
-                    MCycle[2] :
-                      begin
-                        Read_To_Reg = 1'b1;
-                        Set_BusB_To[2:0] = 3'b110;
-                        Set_BusA_To[2:0] = 3'b111;
-                        ALU_Op = 4'b1110;
-                        TStates = 3'b100;
-                        Set_Addr_To = aXY;
-                        Save_ALU = 1'b1;
-                      end
-                    
-                    MCycle[3] :
-                      begin
-                        I_RRD = 1'b1;
-                        Write = 1'b1;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01100111
-              
-              8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101  :
-                begin
-                  // RETI, RETN
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      Set_Addr_To = aSP;
-                    
-                    MCycle[1] :
-                      begin
-                        IncDec_16 = 4'b0111;
-                        Set_Addr_To = aSP;
-                        LDZ = 1'b1;
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        Jump = 1'b1;
-                        IncDec_16 = 4'b0111;
-                        I_RETN = 1'b1;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101
-              
-              8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000  :
-                begin
-                  // IN r,(C)
-                  MCycles = 3'b010;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      Set_Addr_To = aBC;
-                    
-                    MCycle[1] :
-                      begin
-                        IORQ = 1'b1;
-                        if (IR[5:3] != 3'b110 ) 
-                          begin
-                            Read_To_Reg = 1'b1;
-                            Set_BusA_To[2:0] = IR[5:3];
-                          end
-                        I_INRC = 1'b1;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000
-              
-              8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001  :
-                begin
-                  // OUT (C),r
-                  // OUT (C),0
-                  MCycles = 3'b010;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        Set_Addr_To = aBC;
-                        Set_BusB_To[2:0]        = IR[5:3];
-                        if (IR[5:3] == 3'b110 ) 
-                          begin
-                            Set_BusB_To[3] = 1'b1;
-                          end
-                      end
-                    
-                    MCycle[1] :
-                      begin
-                        Write = 1'b1;
-                        IORQ = 1'b1;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001
-              
-              8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010  :
-                begin
-                  // INI, IND, INIR, INDR
-                  MCycles = 3'b100;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        Set_Addr_To = aBC;
-                        Set_BusB_To = 4'b1010;
-                        Set_BusA_To = 4'b0000;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        ALU_Op = 4'b0010;
-                      end
-                    
-                    MCycle[1] :
-                      begin
-                        IORQ = 1'b1;
-                        Set_BusB_To = 4'b0110;
-                        Set_Addr_To = aXY;
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        if (IR[3] == 1'b0 ) 
-                          begin
-			    IncDec_16 = 4'b0110;
-                          end 
-                        else 
-                          begin
-			    IncDec_16 = 4'b1110;
-                          end
-                        TStates = 3'b100;
-                        Write = 1'b1;
-                        I_BTR = 1'b1;
-                      end // case: 3
-                    
-                    MCycle[3] :
-                      begin
-                        NoRead = 1'b1;
-                        TStates = 3'b101;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010
-              
-              8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011  :
-                begin
-                  // OUTI, OUTD, OTIR, OTDR
-                  MCycles = 3'b100;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        TStates = 3'b101;
-                        Set_Addr_To = aXY;
-                        Set_BusB_To = 4'b1010;
-                        Set_BusA_To = 4'b0000;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        ALU_Op = 4'b0010;
-                      end
-                    
-                    MCycle[1] :
-                      begin
-                        Set_BusB_To = 4'b0110;
-                        Set_Addr_To = aBC;
-                        if (IR[3] == 1'b0 ) 
-                          begin
-                            IncDec_16 = 4'b0110;
-                          end 
-                        else 
-                          begin
-                            IncDec_16 = 4'b1110;
-                          end
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        if (IR[3] == 1'b0 ) 
-                          begin
-                            IncDec_16 = 4'b0010;
-                          end 
-                        else 
-                          begin
-                            IncDec_16 = 4'b1010;
-                          end
-                        IORQ = 1'b1;
-                        Write = 1'b1;
-                        I_BTR = 1'b1;
-                      end // case: 3
-                    
-                    MCycle[3] :
-                      begin
-                        NoRead = 1'b1;
-                        TStates = 3'b101;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011
-
-              default : ;
-              
-            endcase // case(IR)                  
-          end // block: default_ed_block        
-      endcase // case(ISet)
-      
-      if (Mode == 1 ) 
-        begin
-          if (MCycle[0] ) 
-            begin
-              //TStates = 3'b100;
-            end 
-          else 
-            begin
-              TStates = 3'b011;
-            end
-        end
-
-      if (Mode == 3 ) 
-        begin
-          if (MCycle[0] ) 
-            begin
-              //TStates = 3'b100;
-            end 
-          else 
-            begin
-              TStates = 3'b100;
-            end
-        end
-
-      if (Mode < 2 ) 
-        begin
-          if (MCycle[5] ) 
-            begin
-              Inc_PC = 1'b1;
-              if (Mode == 1 ) 
-                begin
-                  Set_Addr_To = aXY;
-                  TStates = 3'b100;
-                  Set_BusB_To[2:0] = SSS;
-                  Set_BusB_To[3] = 1'b0;
-                end
-              if (IR == 8'b00110110 || IR == 8'b11001011 ) 
-                begin
-                  Set_Addr_To = aNone;
-                end
-            end
-          if (MCycle[6] ) 
-            begin
-              if (Mode == 0 ) 
-                begin
-                  TStates = 3'b101;
-                end
-              if (ISet != 2'b01 ) 
-                begin
-                  Set_Addr_To = aXY;
-                end
-              Set_BusB_To[2:0] = SSS;
-              Set_BusB_To[3] = 1'b0;
-              if (IR == 8'b00110110 || ISet == 2'b01 ) 
-                begin
-                  // LD (HL),n
-                  Inc_PC = 1'b1;
-                end 
-              else 
-                begin
-                  NoRead = 1'b1;
-                end
-            end
-        end // if (Mode < 2 )      
-      
-    end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
-endmodule // T80_MCode
diff --git a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_reg.v b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_reg.v
deleted file mode 100644
index 889766cf..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80_reg.v
+++ /dev/null
@@ -1,77 +0,0 @@
-//
-// TV80 8-Bit Microprocessor Core
-// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
-//
-// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
-//
-// Permission is hereby granted, free of charge, to any person obtaining a 
-// copy of this software and associated documentation files (the "Software"), 
-// to deal in the Software without restriction, including without limitation 
-// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
-// and/or sell copies of the Software, and to permit persons to whom the 
-// Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included 
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-module tv80_reg (/*AUTOARG*/
-  // Outputs
-  DOBH, DOAL, DOCL, DOBL, DOCH, DOAH, 
-  // Inputs
-  AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
-  );
-    input  [2:0] AddrC;
-    output [7:0] DOBH;
-    input  [2:0] AddrA;
-    input  [2:0] AddrB;
-    input  [7:0] DIH;
-    output [7:0] DOAL;
-    output [7:0] DOCL;
-    input  [7:0] DIL;
-    output [7:0] DOBL;
-    output [7:0] DOCH;
-    output [7:0] DOAH;
-    input  clk, CEN, WEH, WEL;
-
-  reg [7:0] RegsH [0:7];
-  reg [7:0] RegsL [0:7];
-
-  always @(posedge clk)
-    begin
-      if (CEN)
-        begin
-          if (WEH) RegsH[AddrA] <= DIH;
-          if (WEL) RegsL[AddrA] <= DIL;
-        end
-    end
-          
-  assign DOAH = RegsH[AddrA];
-  assign DOAL = RegsL[AddrA];
-  assign DOBH = RegsH[AddrB];
-  assign DOBL = RegsL[AddrB];
-  assign DOCH = RegsH[AddrC];
-  assign DOCL = RegsL[AddrC];
-
-  // break out ram bits for waveform debug
-// synopsys translate_off
-  wire [7:0] B = RegsH[0];
-  wire [7:0] C = RegsL[0];
-  wire [7:0] D = RegsH[1];
-  wire [7:0] E = RegsL[1];
-  wire [7:0] H = RegsH[2];
-  wire [7:0] L = RegsL[2];
-
-  wire [15:0] IX = { RegsH[3], RegsL[3] };
-  wire [15:0] IY = { RegsH[7], RegsL[7] };
-// synopsys translate_on
-  
-endmodule
-
diff --git a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80n.v b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80n.v
deleted file mode 100644
index d672608e..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80n.v
+++ /dev/null
@@ -1,182 +0,0 @@
-//
-// TV80 8-Bit Microprocessor Core
-// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
-//
-// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
-//
-// Permission is hereby granted, free of charge, to any person obtaining a 
-// copy of this software and associated documentation files (the "Software"), 
-// to deal in the Software without restriction, including without limitation 
-// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
-// and/or sell copies of the Software, and to permit persons to whom the 
-// Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included 
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-// Negative-edge based wrapper allows memory wait_n signal to work
-// correctly without resorting to asynchronous logic.
-
-module tv80n (/*AUTOARG*/
-  // Outputs
-  m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
-  // Inputs
-  reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
-  );
-
-  parameter Mode = 0;    // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-  parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2
-  parameter IOWait  = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
-
-
-  input         reset_n; 
-  input         clk; 
-  input         wait_n; 
-  input         int_n; 
-  input         nmi_n; 
-  input         busrq_n; 
-  output        m1_n; 
-  output        mreq_n; 
-  output        iorq_n; 
-  output        rd_n; 
-  output        wr_n; 
-  output        rfsh_n; 
-  output        halt_n; 
-  output        busak_n; 
-  output [15:0] A;
-  input [7:0]   di;
-  output [7:0]  dout;
-
-  reg           mreq_n; 
-  reg           iorq_n; 
-  reg           rd_n; 
-  reg           wr_n; 
-  reg           nxt_mreq_n; 
-  reg           nxt_iorq_n; 
-  reg           nxt_rd_n; 
-  reg           nxt_wr_n; 
-  
-  wire          cen;
-  wire          intcycle_n;
-  wire          no_read;
-  wire          write;
-  wire          iorq;
-  reg [7:0]     di_reg;
-  wire [6:0]    mcycle;
-  wire [6:0]    tstate;
-
-  assign    cen = 1;
-
-  tv80_core #(Mode, IOWait) i_tv80_core
-    (
-     .cen (cen),
-     .m1_n (m1_n),
-     .iorq (iorq),
-     .no_read (no_read),
-     .write (write),
-     .rfsh_n (rfsh_n),
-     .halt_n (halt_n),
-     .wait_n (wait_n),
-     .int_n (int_n),
-     .nmi_n (nmi_n),
-     .reset_n (reset_n),
-     .busrq_n (busrq_n),
-     .busak_n (busak_n),
-     .clk (clk),
-     .IntE (),
-     .stop (),
-     .A (A),
-     .dinst (di),
-     .di (di_reg),
-     .dout (dout),
-     .mc (mcycle),
-     .ts (tstate),
-     .intcycle_n (intcycle_n)
-     );  
-
-  always @*
-    begin
-      nxt_mreq_n = 1;
-      nxt_rd_n   = 1;
-      nxt_iorq_n = 1;
-      nxt_wr_n   = 1;
-      
-      if (mcycle[0])
-        begin
-	  if (tstate[1] || tstate[2])
-            begin
-	      nxt_rd_n = ~ intcycle_n;
-	      nxt_mreq_n = ~ intcycle_n;
-	      nxt_iorq_n = intcycle_n;
-	    end
-        end // if (mcycle[0])          
-      else
-        begin
-	  if ((tstate[1] || tstate[2]) && !no_read && !write)
-            begin
-	      nxt_rd_n = 1'b0;
-	      nxt_iorq_n = ~ iorq;
-	      nxt_mreq_n = iorq;
-	    end
-	  if (T2Write == 0)
-            begin                          
-	      if (tstate[2] && write)
-                begin
-		  nxt_wr_n = 1'b0;
-		  nxt_iorq_n = ~ iorq;
-		  nxt_mreq_n = iorq;
-                end
-            end
-	  else
-            begin
-	      if ((tstate[1] || (tstate[2] && !wait_n)) && write)
-                begin
-		  nxt_wr_n = 1'b0;
-		  nxt_iorq_n = ~ iorq;
-		  nxt_mreq_n = iorq;
-		end
-	    end // else: !if(T2write == 0)          
-	end // else: !if(mcycle[0])
-    end // always @ *
-
-  always @(negedge clk)
-    begin
-      if (!reset_n)
-        begin
-	  rd_n   <= #1 1'b1;
-	  wr_n   <= #1 1'b1;
-	  iorq_n <= #1 1'b1;
-	  mreq_n <= #1 1'b1;
-        end
-      else
-        begin
-	  rd_n <= #1 nxt_rd_n;
-	  wr_n <= #1 nxt_wr_n;
-	  iorq_n <= #1 nxt_iorq_n;
-	  mreq_n <= #1 nxt_mreq_n;
-	end // else: !if(!reset_n)
-    end // always @ (posedge clk or negedge reset_n)
-
-  always @(posedge clk)
-    begin
-      if (!reset_n)
-        begin
-	  di_reg <= #1 0;
-        end
-      else
-        begin
-	  if (tstate[2] && wait_n == 1'b1)
-	    di_reg <= #1 di;
-	end // else: !if(!reset_n)
-    end // always @ (posedge clk)
-  
-endmodule // t80n
-
diff --git a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80s.v b/Computer_MiST/Laser310_MiST/rtl/tv80/tv80s.v
deleted file mode 100644
index 3d825cb7..00000000
--- a/Computer_MiST/Laser310_MiST/rtl/tv80/tv80s.v
+++ /dev/null
@@ -1,162 +0,0 @@
-//
-// TV80 8-Bit Microprocessor Core
-// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
-//
-// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
-//
-// Permission is hereby granted, free of charge, to any person obtaining a 
-// copy of this software and associated documentation files (the "Software"), 
-// to deal in the Software without restriction, including without limitation 
-// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
-// and/or sell copies of the Software, and to permit persons to whom the 
-// Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included 
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-module tv80s (/*AUTOARG*/
-  // Outputs
-  m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout, 
-  // Inputs
-  reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
-  );
-
-  parameter Mode = 0;    // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-  parameter T2Write = 1; // 0 => wr_n active in T3, /=0 => wr_n active in T2
-  parameter IOWait  = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
-
-
-  input         reset_n; 
-  input         clk; 
-  input         wait_n; 
-  input         int_n; 
-  input         nmi_n; 
-  input         busrq_n; 
-  output        m1_n; 
-  output        mreq_n; 
-  output        iorq_n; 
-  output        rd_n; 
-  output        wr_n; 
-  output        rfsh_n; 
-  output        halt_n; 
-  output        busak_n; 
-  output [15:0] A;
-  input [7:0]   di;
-  output [7:0]  dout;
-
-  reg           mreq_n; 
-  reg           iorq_n; 
-  reg           rd_n; 
-  reg           wr_n; 
-  
-  wire          cen;
-  wire          intcycle_n;
-  wire          no_read;
-  wire          write;
-  wire          iorq;
-  reg [7:0]     di_reg;
-  wire [6:0]    mcycle;
-  wire [6:0]    tstate;
-
-  assign    cen = 1;
-
-  tv80_core #(Mode, IOWait) i_tv80_core
-    (
-     .cen (cen),
-     .m1_n (m1_n),
-     .iorq (iorq),
-     .no_read (no_read),
-     .write (write),
-     .rfsh_n (rfsh_n),
-     .halt_n (halt_n),
-     .wait_n (wait_n),
-     .int_n (int_n),
-     .nmi_n (nmi_n),
-     .reset_n (reset_n),
-     .busrq_n (busrq_n),
-     .busak_n (busak_n),
-     .clk (clk),
-     .IntE (),
-     .stop (),
-     .A (A),
-     .dinst (di),
-     .di (di_reg),
-     .dout (dout),
-     .mc (mcycle),
-     .ts (tstate),
-     .intcycle_n (intcycle_n)
-     );  
-
-  always @(posedge clk or negedge reset_n)
-    begin
-      if (!reset_n)
-        begin
-          rd_n   <= #1 1'b1;
-          wr_n   <= #1 1'b1;
-          iorq_n <= #1 1'b1;
-          mreq_n <= #1 1'b1;
-          di_reg <= #1 0;
-        end
-      else
-        begin
-          rd_n <= #1 1'b1;
-          wr_n <= #1 1'b1;
-          iorq_n <= #1 1'b1;
-          mreq_n <= #1 1'b1;
-          if (mcycle[0])
-            begin
-              if (tstate[1] || (tstate[2] && wait_n == 1'b0))
-                begin
-                  rd_n <= #1 ~ intcycle_n;
-                  mreq_n <= #1 ~ intcycle_n;
-                  iorq_n <= #1 intcycle_n;
-                end
-            `ifdef TV80_REFRESH
-              if (tstate[3])
-            mreq_n <= #1 1'b0;
-            `endif
-            end // if (mcycle[0])          
-          else
-            begin
-              if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0)
-                begin
-                  rd_n <= #1 1'b0;
-                  iorq_n <= #1 ~ iorq;
-                  mreq_n <= #1 iorq;
-                end
-              if (T2Write == 0)
-                begin                          
-                  if (tstate[2] && write == 1'b1)
-                    begin
-                      wr_n <= #1 1'b0;
-                      iorq_n <= #1 ~ iorq;
-                      mreq_n <= #1 iorq;
-                    end
-                end
-              else
-                begin
-                  if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && write == 1'b1)
-                    begin
-                      wr_n <= #1 1'b0;
-                      iorq_n <= #1 ~ iorq;
-                      mreq_n <= #1 iorq;
-                  end
-                end // else: !if(T2write == 0)
-              
-            end // else: !if(mcycle[0])
-          
-          if (tstate[2] && wait_n == 1'b1)
-            di_reg <= #1 di;
-        end // else: !if(!reset_n)
-    end // always @ (posedge clk or negedge reset_n)
-  
-endmodule // t80s
-