From c43fd58c3a451a6dd7f7bf195e770e8b656607a0 Mon Sep 17 00:00:00 2001
From: Gehstock <marceljenke@gmail.com>
Date: Sat, 4 Jan 2020 15:35:44 +0100
Subject: [PATCH] Move Midway 8080

---
 Arcade_MiST/.gitignore                        |    1 +
 .../280ZZZAP_MiST/280ZZZAP.qpf                |   30 +
 .../280ZZZAP_MiST/280ZZZAP.qsf                |  172 ++
 .../280ZZZAP_MiST/280ZZZAP.sdc                |  126 ++
 .../280ZZZAP_MiST/README.txt                  |   27 +
 .../280ZZZAP_MiST/Snapshot/280ZZZAP.rbf       |  Bin 0 -> 240973 bytes
 .../280ZZZAP_MiST/clean.bat                   |   15 +
 .../280ZZZAP_MiST/doc/Schematic.png           |  Bin 0 -> 594972 bytes
 .../280ZZZAP_MiST/rtl/D280ZZZAP_Overlay.vhd   |  111 +
 .../280ZZZAP_MiST/rtl/D280ZZZAP_memory.sv     |  104 +
 .../280ZZZAP_MiST/rtl/D280ZZZAP_mist.sv       |  228 ++
 .../280ZZZAP_MiST/rtl/T80/T80.vhd             | 1080 +++++++++
 .../280ZZZAP_MiST/rtl/T80/T8080se.vhd         |  194 ++
 .../280ZZZAP_MiST/rtl/T80/T80_ALU.vhd         |  361 +++
 .../280ZZZAP_MiST/rtl/T80/T80_MCode.vhd       | 1944 +++++++++++++++++
 .../280ZZZAP_MiST/rtl/T80/T80_Pack.vhd        |  217 ++
 .../280ZZZAP_MiST/rtl/T80/T80_Reg.vhd         |  114 +
 .../280ZZZAP_MiST/rtl/build_id.tcl            |   35 +
 .../280ZZZAP_MiST/rtl/invaders.vhd            |  245 +++
 .../280ZZZAP_MiST/rtl/invaders_audio.vhd      |  496 +++++
 .../280ZZZAP_MiST/rtl/mw8080.vhd              |  335 +++
 .../280ZZZAP_MiST/rtl/pll.qip                 |    4 +
 .../280ZZZAP_MiST/rtl/pll.vhd                 |  382 ++++
 .../280ZZZAP_MiST/rtl/roms/zzzap_c.hex        |   65 +
 .../280ZZZAP_MiST/rtl/roms/zzzap_d.hex        |   65 +
 .../280ZZZAP_MiST/rtl/roms/zzzap_e.hex        |   65 +
 .../280ZZZAP_MiST/rtl/roms/zzzap_f.hex        |   65 +
 .../280ZZZAP_MiST/rtl/roms/zzzap_g.hex        |   65 +
 .../280ZZZAP_MiST/rtl/roms/zzzap_h.hex        |   65 +
 .../280ZZZAP_MiST/rtl/spram.vhd               |   55 +
 .../280ZZZAP_MiST/rtl/sprom.vhd               |   82 +
 .../BalloonBomber_MiST/BalloonBomber.qpf      |   30 +
 .../BalloonBomber_MiST/BalloonBomber.qsf      |  177 ++
 .../README.txt}                               |    0
 .../BalloonBomber_MiST/clean.bat              |   16 +
 .../rtl/BalloonBomber_Overlay.vhd             |  366 ++++
 .../rtl/BalloonBomber_memory.sv               |   72 +
 .../rtl/BalloonBomber_mist.sv                 |  208 ++
 .../BalloonBomber_MiST/rtl/T80/T80.vhd        | 1080 +++++++++
 .../BalloonBomber_MiST/rtl/T80/T8080se.vhd    |  194 ++
 .../BalloonBomber_MiST/rtl/T80/T80_ALU.vhd    |  361 +++
 .../BalloonBomber_MiST/rtl/T80/T80_MCode.vhd  | 1944 +++++++++++++++++
 .../BalloonBomber_MiST/rtl/T80/T80_Pack.vhd   |  217 ++
 .../BalloonBomber_MiST/rtl/T80/T80_Reg.vhd    |  114 +
 .../BalloonBomber_MiST/rtl/build_id.tcl       |   35 +
 .../BalloonBomber_MiST/rtl/invaders.vhd       |  281 +++
 .../BalloonBomber_MiST/rtl/invaders_audio.vhd |  496 +++++
 .../BalloonBomber_MiST/rtl/mw8080.vhd         |  336 +++
 .../BalloonBomber_MiST/rtl/pll.qip            |    4 +
 .../BalloonBomber_MiST/rtl/pll.vhd            |  382 ++++
 .../BalloonBomber_MiST/rtl/roms/ballbomb.zip  |  Bin 0 -> 7424 bytes
 .../BalloonBomber_MiST/rtl/roms/tn01          |  Bin 0 -> 2048 bytes
 .../BalloonBomber_MiST/rtl/roms/tn01.vhd      |  150 ++
 .../BalloonBomber_MiST/rtl/roms/tn02          |  Bin 0 -> 2048 bytes
 .../BalloonBomber_MiST/rtl/roms/tn02.vhd      |  150 ++
 .../BalloonBomber_MiST/rtl/roms/tn03          |  Bin 0 -> 2048 bytes
 .../BalloonBomber_MiST/rtl/roms/tn03.vhd      |  150 ++
 .../BalloonBomber_MiST/rtl/roms/tn04          |  Bin 0 -> 2048 bytes
 .../BalloonBomber_MiST/rtl/roms/tn04.vhd      |  150 ++
 .../BalloonBomber_MiST/rtl/roms/tn05-1        |  Bin 0 -> 2048 bytes
 .../BalloonBomber_MiST/rtl/roms/tn05-1.vhd    |  150 ++
 .../BalloonBomber_MiST/rtl/roms/tn06          |    1 +
 .../BalloonBomber_MiST/rtl/roms/tn06.vhd      |   86 +
 .../BalloonBomber_MiST/rtl/roms/tn07          |    1 +
 .../BalloonBomber_MiST/rtl/roms/tn07.vhd      |   86 +
 .../BalloonBomber_MiST/rtl/spram.vhd          |   55 +
 .../BlueShark_MiST/BlueShark.qpf              |   30 +
 .../BlueShark_MiST/BlueShark.qsf              |  172 ++
 .../BlueShark_MiST/BlueShark.sdc              |  126 ++
 .../BlueShark_MiST/README.txt                 |   26 +
 .../BlueShark_MiST/Snapshot/BlueShark.rbf     |  Bin 0 -> 241979 bytes
 .../BlueShark_MiST/clean.bat                  |   15 +
 .../doc/Blue_Shark_-_1978_-_Midway_Games.pdf  |  Bin 0 -> 2564891 bytes
 .../BlueShark_MiST/rtl/BlueShark_Overlay.vhd  |  112 +
 .../BlueShark_MiST/rtl/BlueShark_memory.sv    |   68 +
 .../BlueShark_MiST/rtl/BlueShark_mist.sv      |  214 ++
 .../BlueShark_MiST/rtl/T80/T80.vhd            | 1080 +++++++++
 .../BlueShark_MiST/rtl/T80/T8080se.vhd        |  194 ++
 .../BlueShark_MiST/rtl/T80/T80_ALU.vhd        |  361 +++
 .../BlueShark_MiST/rtl/T80/T80_MCode.vhd      | 1944 +++++++++++++++++
 .../BlueShark_MiST/rtl/T80/T80_Pack.vhd       |  217 ++
 .../BlueShark_MiST/rtl/T80/T80_Reg.vhd        |  114 +
 .../BlueShark_MiST/rtl/build_id.tcl           |   35 +
 .../BlueShark_MiST/rtl/invaders.vhd           |  243 +++
 .../BlueShark_MiST/rtl/invaders_audio.vhd     |  496 +++++
 .../BlueShark_MiST/rtl/mw8080.vhd             |  335 +++
 .../BlueShark_MiST/rtl/pll.qip                |    4 +
 .../BlueShark_MiST/rtl/pll.vhd                |  382 ++++
 .../BlueShark_MiST/rtl/roms/blueshrk_f.hex    |  129 ++
 .../BlueShark_MiST/rtl/roms/blueshrk_g.hex    |  129 ++
 .../BlueShark_MiST/rtl/roms/blueshrk_h.hex    |  129 ++
 .../BlueShark_MiST/rtl/spram.vhd              |   55 +
 .../BlueShark_MiST/rtl/sprom.vhd              |   82 +
 .../Boothill_MiST/Boothill.qpf                |   30 +
 .../Boothill_MiST/Boothill.qsf                |  176 ++
 .../Boothill_MiST/README.txt                  |   26 +
 .../Boothill_MiST/clean.bat                   |   15 +
 .../Boothill_MiST/rtl/SpaceWalk_mist.sv       |  198 ++
 .../Boothill_MiST/rtl/T80/T80.vhd             | 1080 +++++++++
 .../Boothill_MiST/rtl/T80/T8080se.vhd         |  194 ++
 .../Boothill_MiST/rtl/T80/T80_ALU.vhd         |  361 +++
 .../Boothill_MiST/rtl/T80/T80_MCode.vhd       | 1944 +++++++++++++++++
 .../Boothill_MiST/rtl/T80/T80_Pack.vhd        |  217 ++
 .../Boothill_MiST/rtl/T80/T80_Reg.vhd         |  114 +
 .../Boothill_MiST/rtl/build_id.tcl            |   35 +
 .../Boothill_MiST/rtl/invaders.vhd            |  283 +++
 .../Boothill_MiST/rtl/invaders_audio.vhd      |  498 +++++
 .../Boothill_MiST/rtl/invaders_memory.sv      |   66 +
 .../Boothill_MiST/rtl/invaders_video.vhd      |  127 ++
 .../Boothill_MiST/rtl/mw8080.vhd              |  336 +++
 .../Boothill_MiST/rtl/pll.qip                 |    4 +
 .../Boothill_MiST/rtl/pll.vhd                 |  382 ++++
 .../Boothill_MiST/rtl/roms/rome.vhd           |  150 ++
 .../Boothill_MiST/rtl/roms/romf.vhd           |  150 ++
 .../Boothill_MiST/rtl/roms/romg.vhd           |  150 ++
 .../Boothill_MiST/rtl/roms/romh.vhd           |  150 ++
 .../Boothill_MiST/rtl/spram.vhd               |   55 +
 .../Boothill_MiST/rtl/sprom.vhd               |   82 +
 .../BowlingAlley_MiST/BowlingAlley.qpf        |   30 +
 .../BowlingAlley_MiST/BowlingAlley.qsf        |  171 ++
 .../BowlingAlley_MiST/BowlingAlley.sdc        |  126 ++
 .../BowlingAlley_MiST/README.txt              |   26 +
 .../Snapshot/BowlingAlley.rbf                 |  Bin 0 -> 245721 bytes
 .../BowlingAlley_MiST/clean.bat               |   15 +
 .../rtl/BowlingAlley_memory.sv                |   92 +
 .../rtl/BowlingAlley_mist.sv                  |  196 ++
 .../BowlingAlley_MiST/rtl/T80/T80.vhd         | 1080 +++++++++
 .../BowlingAlley_MiST/rtl/T80/T8080se.vhd     |  194 ++
 .../BowlingAlley_MiST/rtl/T80/T80_ALU.vhd     |  361 +++
 .../BowlingAlley_MiST/rtl/T80/T80_MCode.vhd   | 1944 +++++++++++++++++
 .../BowlingAlley_MiST/rtl/T80/T80_Pack.vhd    |  217 ++
 .../BowlingAlley_MiST/rtl/T80/T80_Reg.vhd     |  114 +
 .../BowlingAlley_MiST/rtl/build_id.tcl        |   35 +
 .../BowlingAlley_MiST/rtl/dac.vhd             |   48 +
 .../BowlingAlley_MiST/rtl/invaders.vhd        |  283 +++
 .../BowlingAlley_MiST/rtl/invaders_audio.vhd  |  496 +++++
 .../BowlingAlley_MiST/rtl/mw8080.vhd          |  336 +++
 .../BowlingAlley_MiST/rtl/pll.qip             |    4 +
 .../BowlingAlley_MiST/rtl/pll.vhd             |  382 ++++
 .../BowlingAlley_MiST/rtl/roms/d.cpu.hex      |  129 ++
 .../BowlingAlley_MiST/rtl/roms/e.cpu.hex      |  129 ++
 .../BowlingAlley_MiST/rtl/roms/f.cpu.hex      |  129 ++
 .../BowlingAlley_MiST/rtl/roms/g.cpu.hex      |  129 ++
 .../BowlingAlley_MiST/rtl/roms/h.cpu.hex      |  129 ++
 .../BowlingAlley_MiST/rtl/spram.vhd           |   55 +
 .../BowlingAlley_MiST/rtl/sprom.vhd           |   82 +
 .../GunFight_MiST/GunFight.qpf                |   30 +
 .../GunFight_MiST/GunFight.qsf                |  178 ++
 .../GunFight_MiST/GunFight.sdc                |  126 ++
 .../README.txt}                               |    0
 .../GunFight_MiST/clean.bat                   |   15 +
 .../GunFight_MiST/rtl/GunFight_memory.sv      |  129 ++
 .../GunFight_MiST/rtl/GunFight_mist.sv        |  197 ++
 .../GunFight_MiST/rtl/GunFight_overlay.vhd    |  127 ++
 .../GunFight_MiST/rtl/T80/T80.vhd             | 1080 +++++++++
 .../GunFight_MiST/rtl/T80/T8080se.vhd         |  194 ++
 .../GunFight_MiST/rtl/T80/T80_ALU.vhd         |  361 +++
 .../GunFight_MiST/rtl/T80/T80_MCode.vhd       | 1944 +++++++++++++++++
 .../GunFight_MiST/rtl/T80/T80_Pack.vhd        |  217 ++
 .../GunFight_MiST/rtl/T80/T80_Reg.vhd         |  114 +
 .../GunFight_MiST/rtl/build_id.tcl            |   35 +
 .../GunFight_MiST/rtl/gun.sv                  |   13 +
 .../GunFight_MiST/rtl/invaders.vhd            |  307 +++
 .../GunFight_MiST/rtl/invaders_audio.vhd      |  496 +++++
 .../GunFight_MiST/rtl/mw8080.vhd              |  336 +++
 .../GunFight_MiST/rtl/pll.qip                 |    4 +
 .../GunFight_MiST/rtl/pll.vhd                 |  350 +++
 .../GunFight_MiST/rtl/roms/gf-a.hex           |   18 +
 .../GunFight_MiST/rtl/roms/gf-b.hex           |   18 +
 .../GunFight_MiST/rtl/roms/gf-c.hex           |   18 +
 .../GunFight_MiST/rtl/roms/gf-d.hex           |   18 +
 .../GunFight_MiST/rtl/roms/gf-e.hex           |   18 +
 .../GunFight_MiST/rtl/roms/gf-f.hex           |   18 +
 .../GunFight_MiST/rtl/roms/gf-g.hex           |   18 +
 .../GunFight_MiST/rtl/roms/gf-h.hex           |   18 +
 .../GunFight_MiST/rtl/spram.vhd               |   55 +
 .../GunFight_MiST/rtl/sprom.vhd               |   82 +
 .../Lunar Rescue_MiST/LunarRescue.qpf         |   30 +
 .../Lunar Rescue_MiST/LunarRescue.qsf         |  168 ++
 .../Lunar Rescue_MiST/LunarRescue.sdc         |  126 ++
 .../README.txt}                               |    0
 .../Lunar Rescue_MiST/clean.bat               |   15 +
 .../rtl/LunarRescue_Overlay.vhd               |  366 ++++
 .../rtl/LunarRescue_memory.sv                 |  103 +
 .../Lunar Rescue_MiST/rtl/LunarRescue_mist.sv |  209 ++
 .../Lunar Rescue_MiST/rtl/build_id.tcl        |   35 +
 .../Lunar Rescue_MiST/rtl/invaders.vhd        |  245 +++
 .../Lunar Rescue_MiST/rtl/invaders_audio.vhd  |  496 +++++
 .../Lunar Rescue_MiST/rtl/mw8080.vhd          |  337 +++
 .../Lunar Rescue_MiST/rtl/pll.qip             |    4 +
 .../Lunar Rescue_MiST/rtl/pll.vhd             |  350 +++
 .../Lunar Rescue_MiST/rtl/roms/col.bin        |    1 +
 .../Lunar Rescue_MiST/rtl/roms/col.vhd        |   86 +
 .../Lunar Rescue_MiST/rtl/roms/lrescue_1.hex  |  129 ++
 .../Lunar Rescue_MiST/rtl/roms/lrescue_2.hex  |  129 ++
 .../Lunar Rescue_MiST/rtl/roms/lrescue_3.hex  |  129 ++
 .../Lunar Rescue_MiST/rtl/roms/lrescue_4.hex  |  129 ++
 .../Lunar Rescue_MiST/rtl/roms/lrescue_5.hex  |  129 ++
 .../Lunar Rescue_MiST/rtl/roms/lrescue_6.hex  |  129 ++
 .../Lunar Rescue_MiST/rtl/spram.vhd           |   55 +
 .../Lunar Rescue_MiST/rtl/sprom.vhd           |   82 +
 .../Ozma Wars_MiST/OzmaWars.qpf               |   30 +
 .../Ozma Wars_MiST/OzmaWars.qsf               |  178 ++
 .../Ozma Wars_MiST/OzmaWars.sdc               |  126 ++
 .../README.txt}                               |    0
 .../Ozma Wars_MiST/clean.bat                  |   15 +
 .../Ozma Wars_MiST/rtl/OzmaWars_memory.sv     |   80 +
 .../Ozma Wars_MiST/rtl/OzmaWars_mist.sv       |  210 ++
 .../Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd   |  225 ++
 .../Ozma Wars_MiST/rtl/T80/T80.vhd            | 1080 +++++++++
 .../Ozma Wars_MiST/rtl/T80/T8080se.vhd        |  194 ++
 .../Ozma Wars_MiST/rtl/T80/T80_ALU.vhd        |  361 +++
 .../Ozma Wars_MiST/rtl/T80/T80_MCode.vhd      | 1944 +++++++++++++++++
 .../Ozma Wars_MiST/rtl/T80/T80_Pack.vhd       |  217 ++
 .../Ozma Wars_MiST/rtl/T80/T80_Reg.vhd        |  114 +
 .../Ozma Wars_MiST/rtl/build_id.tcl           |   35 +
 .../Ozma Wars_MiST/rtl/dac.vhd                |   48 +
 .../Ozma Wars_MiST/rtl/invaders.vhd           |  273 +++
 .../Ozma Wars_MiST/rtl/invaders_audio.vhd     |  496 +++++
 .../Ozma Wars_MiST/rtl/mw8080.vhd             |  336 +++
 .../Ozma Wars_MiST/rtl/pll.qip                |    4 +
 .../Ozma Wars_MiST/rtl/pll.vhd                |  382 ++++
 .../Ozma Wars_MiST/rtl/roms/mw01.vhd          |  150 ++
 .../Ozma Wars_MiST/rtl/roms/mw02.vhd          |  150 ++
 .../Ozma Wars_MiST/rtl/roms/mw03.vhd          |  150 ++
 .../Ozma Wars_MiST/rtl/roms/mw04.vhd          |  150 ++
 .../Ozma Wars_MiST/rtl/roms/mw05.vhd          |  150 ++
 .../Ozma Wars_MiST/rtl/roms/mw06.vhd          |  150 ++
 .../Ozma Wars_MiST/rtl/spram.vhd              |   55 +
 .../Ozma Wars_MiST/rtl/sprom.vhd              |   82 +
 .../Shuffleboard_MiST/README.txt              |   26 +
 .../Shuffleboard_MiST/Shuffleboard.qpf        |   30 +
 .../Shuffleboard_MiST/Shuffleboard.qsf        |  173 ++
 .../Shuffleboard_MiST/Shuffleboard.sdc        |  126 ++
 .../Snapshot/Shuffleboard.rbf                 |  Bin 0 -> 246209 bytes
 .../Shuffleboard_MiST/clean.bat               |   15 +
 .../rtl/Shuffleboard_memory.sv                |   80 +
 .../rtl/Shuffleboard_mist.sv                  |  196 ++
 .../Shuffleboard_MiST/rtl/T80/T80.vhd         | 1080 +++++++++
 .../Shuffleboard_MiST/rtl/T80/T8080se.vhd     |  194 ++
 .../Shuffleboard_MiST/rtl/T80/T80_ALU.vhd     |  361 +++
 .../Shuffleboard_MiST/rtl/T80/T80_MCode.vhd   | 1944 +++++++++++++++++
 .../Shuffleboard_MiST/rtl/T80/T80_Pack.vhd    |  217 ++
 .../Shuffleboard_MiST/rtl/T80/T80_Reg.vhd     |  114 +
 .../Shuffleboard_MiST/rtl/build_id.tcl        |   35 +
 .../Shuffleboard_MiST/rtl/dac.vhd             |   48 +
 .../Shuffleboard_MiST/rtl/invaders.vhd        |  243 +++
 .../Shuffleboard_MiST/rtl/invaders_audio.vhd  |  496 +++++
 .../Shuffleboard_MiST/rtl/mw8080.vhd          |  335 +++
 .../Shuffleboard_MiST/rtl/pll.qip             |    4 +
 .../Shuffleboard_MiST/rtl/pll.vhd             |  350 +++
 .../Shuffleboard_MiST/rtl/roms/shuffle.e.bin  |  Bin 0 -> 2048 bytes
 .../Shuffleboard_MiST/rtl/roms/shuffle.e.hex  |  129 ++
 .../Shuffleboard_MiST/rtl/roms/shuffle.f.bin  |  Bin 0 -> 2048 bytes
 .../Shuffleboard_MiST/rtl/roms/shuffle.f.hex  |  129 ++
 .../Shuffleboard_MiST/rtl/roms/shuffle.g.bin  |  Bin 0 -> 2048 bytes
 .../Shuffleboard_MiST/rtl/roms/shuffle.g.hex  |  129 ++
 .../Shuffleboard_MiST/rtl/roms/shuffle.h.bin  |  Bin 0 -> 2048 bytes
 .../Shuffleboard_MiST/rtl/roms/shuffle.h.hex  |  129 ++
 .../Shuffleboard_MiST/rtl/spram.vhd           |   55 +
 .../Shuffleboard_MiST/rtl/sprom.vhd           |   82 +
 .../Space Invaders 2_MiST/Invaders2.qpf       |   30 +
 .../Space Invaders 2_MiST/Invaders2.qsf       |  173 ++
 .../Space Invaders 2_MiST/Invaders2.sdc       |  126 ++
 .../README.txt}                               |    0
 .../Space Invaders 2_MiST/clean.bat           |   15 +
 .../rtl/Invaders2_mist.sv                     |  211 ++
 .../Space Invaders 2_MiST/rtl/T80/T80.vhd     | 1080 +++++++++
 .../Space Invaders 2_MiST/rtl/T80/T8080se.vhd |  194 ++
 .../Space Invaders 2_MiST/rtl/T80/T80_ALU.vhd |  361 +++
 .../rtl/T80/T80_MCode.vhd                     | 1944 +++++++++++++++++
 .../rtl/T80/T80_Pack.vhd                      |  217 ++
 .../Space Invaders 2_MiST/rtl/T80/T80_Reg.vhd |  114 +
 .../Space Invaders 2_MiST/rtl/build_id.tcl    |   35 +
 .../Space Invaders 2_MiST/rtl/dac.vhd         |   48 +
 .../Space Invaders 2_MiST/rtl/invaders.vhd    |  271 +++
 .../rtl/invaders_audio.vhd                    |  496 +++++
 .../rtl/invaders_memory.sv                    |  104 +
 .../rtl/invaders_video.vhd                    |  127 ++
 .../Space Invaders 2_MiST/rtl/mw8080.vhd      |  336 +++
 .../Space Invaders 2_MiST/rtl/pll.qip         |    4 +
 .../Space Invaders 2_MiST/rtl/pll.vhd         |  350 +++
 .../rtl/roms/invad2ct.a.hex                   |  129 ++
 .../rtl/roms/invad2ct.b.hex                   |  129 ++
 .../rtl/roms/invad2ct.e.hex                   |  129 ++
 .../rtl/roms/invad2ct.f.hex                   |  129 ++
 .../rtl/roms/invad2ct.g.hex                   |  129 ++
 .../rtl/roms/invad2ct.h.hex                   |  129 ++
 .../Space Invaders 2_MiST/rtl/spram.vhd       |   55 +
 .../Space Invaders 2_MiST/rtl/sprom.vhd       |   82 +
 .../README.txt}                               |    0
 .../Space Invaders_MiST/SpaceInvaders.qpf     |   30 +
 .../Space Invaders_MiST/SpaceInvaders.qsf     |  173 ++
 .../Space Invaders_MiST/SpaceInvaders.sdc     |  126 ++
 .../Space Invaders_MiST/clean.bat             |   15 +
 .../Space Invaders_MiST/rtl/T80/T80.vhd       | 1080 +++++++++
 .../Space Invaders_MiST/rtl/T80/T8080se.vhd   |  194 ++
 .../Space Invaders_MiST/rtl/T80/T80_ALU.vhd   |  361 +++
 .../Space Invaders_MiST/rtl/T80/T80_MCode.vhd | 1944 +++++++++++++++++
 .../Space Invaders_MiST/rtl/T80/T80_Pack.vhd  |  217 ++
 .../Space Invaders_MiST/rtl/T80/T80_Reg.vhd   |  114 +
 .../Space Invaders_MiST/rtl/build_id.tcl      |   35 +
 .../Space Invaders_MiST/rtl/dac.vhd           |   48 +
 .../Space Invaders_MiST/rtl/invaders.vhd      |  271 +++
 .../rtl/invaders_audio.vhd                    |  496 +++++
 .../Space Invaders_MiST/rtl/mw8080.vhd        |  336 +++
 .../Space Invaders_MiST/rtl/pll.qip           |    4 +
 .../Space Invaders_MiST/rtl/pll.vhd           |  350 +++
 .../rtl/roms/invaders_e.hex                   |  129 ++
 .../rtl/roms/invaders_f.hex                   |  129 ++
 .../rtl/roms/invaders_g.hex                   |  129 ++
 .../rtl/roms/invaders_h.hex                   |  129 ++
 .../rtl/spaceinvaders_memory.sv               |   82 +
 .../rtl/spaceinvaders_mist.sv                 |  211 ++
 .../rtl/spaceinvaders_overlay.vhd             |  127 ++
 .../Space Invaders_MiST/rtl/spram.vhd         |   55 +
 .../Space Invaders_MiST/rtl/sprom.vhd         |   82 +
 .../README.txt}                               |    0
 .../SpaceLaser_MiST/SpaceLaser.qpf            |   30 +
 .../SpaceLaser_MiST/SpaceLaser.qsf            |  173 ++
 .../SpaceLaser_MiST/SpaceLaser.sdc            |  126 ++
 .../SpaceLaser_MiST/clean.bat                 |   15 +
 .../SpaceLaser_MiST/rtl/T80/T80.vhd           | 1080 +++++++++
 .../SpaceLaser_MiST/rtl/T80/T8080se.vhd       |  194 ++
 .../SpaceLaser_MiST/rtl/T80/T80_ALU.vhd       |  361 +++
 .../SpaceLaser_MiST/rtl/T80/T80_MCode.vhd     | 1944 +++++++++++++++++
 .../SpaceLaser_MiST/rtl/T80/T80_Pack.vhd      |  217 ++
 .../SpaceLaser_MiST/rtl/T80/T80_Reg.vhd       |  114 +
 .../SpaceLaser_MiST/rtl/build_id.tcl          |   35 +
 .../SpaceLaser_MiST/rtl/invaders.vhd          |  245 +++
 .../SpaceLaser_MiST/rtl/invaders_audio.vhd    |  496 +++++
 .../SpaceLaser_MiST/rtl/mw8080.vhd            |  336 +++
 .../SpaceLaser_MiST/rtl/pll.qip               |    4 +
 .../SpaceLaser_MiST/rtl/pll.vhd               |  382 ++++
 .../SpaceLaser_MiST/rtl/roms/clr.vhd          |   38 +
 .../SpaceLaser_MiST/rtl/roms/la01.hex         |  129 ++
 .../SpaceLaser_MiST/rtl/roms/la02.hex         |  129 ++
 .../SpaceLaser_MiST/rtl/roms/la03.hex         |  129 ++
 .../SpaceLaser_MiST/rtl/roms/la04.hex         |  129 ++
 .../SpaceLaser_MiST/rtl/spacelaser_memory.sv  |   81 +
 .../SpaceLaser_MiST/rtl/spacelaser_mist.sv    |  208 ++
 .../rtl/spacelaser_overlay.vhd                |  228 ++
 .../SpaceLaser_MiST/rtl/spram.vhd             |   55 +
 .../SpaceLaser_MiST/rtl/sprom.vhd             |   82 +
 .../SpaceWalk_MiST/README.txt                 |   26 +
 .../SpaceWalk_MiST/SpaceWalk.qpf              |   30 +
 .../SpaceWalk_MiST/SpaceWalk.qsf              |  172 ++
 .../SpaceWalk_MiST/SpaceWalk.sdc              |  126 ++
 .../SpaceWalk_MiST/clean.bat                  |   15 +
 .../SpaceWalk_MiST/rtl/SpaceWalk.sv           |  187 ++
 .../SpaceWalk_MiST/rtl/Spacewalk_memory.sv    |  132 ++
 .../SpaceWalk_MiST/rtl/Spacewalk_overlay.vhd  |  127 ++
 .../SpaceWalk_MiST/rtl/T80/T80.vhd            | 1080 +++++++++
 .../SpaceWalk_MiST/rtl/T80/T8080se.vhd        |  194 ++
 .../SpaceWalk_MiST/rtl/T80/T80_ALU.vhd        |  361 +++
 .../SpaceWalk_MiST/rtl/T80/T80_MCode.vhd      | 1944 +++++++++++++++++
 .../SpaceWalk_MiST/rtl/T80/T80_Pack.vhd       |  217 ++
 .../SpaceWalk_MiST/rtl/T80/T80_Reg.vhd        |  114 +
 .../SpaceWalk_MiST/rtl/build_id.tcl           |   35 +
 .../SpaceWalk_MiST/rtl/invaders.vhd           |  281 +++
 .../SpaceWalk_MiST/rtl/invaders_audio.vhd     |  496 +++++
 .../SpaceWalk_MiST/rtl/mw8080.vhd             |  336 +++
 .../SpaceWalk_MiST/rtl/pll.qip                |    4 +
 .../SpaceWalk_MiST/rtl/pll.vhd                |  382 ++++
 .../SpaceWalk_MiST/rtl/roms/sw.a.bin          |  Bin 0 -> 1024 bytes
 .../SpaceWalk_MiST/rtl/roms/sw.a.hex          |   65 +
 .../SpaceWalk_MiST/rtl/roms/sw.b.bin          |  Bin 0 -> 1024 bytes
 .../SpaceWalk_MiST/rtl/roms/sw.b.hex          |   65 +
 .../SpaceWalk_MiST/rtl/roms/sw.c.bin          |  Bin 0 -> 1024 bytes
 .../SpaceWalk_MiST/rtl/roms/sw.c.hex          |   65 +
 .../SpaceWalk_MiST/rtl/roms/sw.d.bin          |  Bin 0 -> 1024 bytes
 .../SpaceWalk_MiST/rtl/roms/sw.d.hex          |   65 +
 .../SpaceWalk_MiST/rtl/roms/sw.e.bin          |  Bin 0 -> 1024 bytes
 .../SpaceWalk_MiST/rtl/roms/sw.e.hex          |   65 +
 .../SpaceWalk_MiST/rtl/roms/sw.f.bin          |  Bin 0 -> 1024 bytes
 .../SpaceWalk_MiST/rtl/roms/sw.f.hex          |   65 +
 .../SpaceWalk_MiST/rtl/roms/sw.g.bin          |  Bin 0 -> 1024 bytes
 .../SpaceWalk_MiST/rtl/roms/sw.g.hex          |   65 +
 .../SpaceWalk_MiST/rtl/roms/sw.h.bin          |  Bin 0 -> 1024 bytes
 .../SpaceWalk_MiST/rtl/roms/sw.h.hex          |   65 +
 .../SpaceWalk_MiST/rtl/spram.vhd              |   55 +
 .../SpaceWalk_MiST/rtl/sprom.vhd              |   82 +
 .../README.txt}                               |    0
 .../SuperEarthInvasion.qpf                    |   30 +
 .../SuperEarthInvasion.qsf                    |  172 ++
 .../SuperEarthInvasion.sdc                    |  126 ++
 .../Super Earth Invasion_MiST/clean.bat       |   15 +
 .../rtl/SuperEarthInvasion_memory.sv          |   81 +
 .../rtl/SuperEarthInvasion_mist.sv            |  212 ++
 .../rtl/SuperEarthInvasion_overlay.vhd        |  128 ++
 .../Super Earth Invasion_MiST/rtl/T80/T80.vhd | 1080 +++++++++
 .../rtl/T80/T8080se.vhd                       |  194 ++
 .../rtl/T80/T80_ALU.vhd                       |  361 +++
 .../rtl/T80/T80_MCode.vhd                     | 1944 +++++++++++++++++
 .../rtl/T80/T80_Pack.vhd                      |  217 ++
 .../rtl/T80/T80_Reg.vhd                       |  114 +
 .../rtl/build_id.tcl                          |   35 +
 .../Super Earth Invasion_MiST/rtl/dac.vhd     |   48 +
 .../rtl/invaders.vhd                          |  243 +++
 .../rtl/invaders_audio.vhd                    |  496 +++++
 .../Super Earth Invasion_MiST/rtl/mw8080.vhd  |  335 +++
 .../Super Earth Invasion_MiST/rtl/pll.qip     |    4 +
 .../Super Earth Invasion_MiST/rtl/pll.vhd     |  382 ++++
 .../rtl/roms/earthinv_e.hex                   |  129 ++
 .../rtl/roms/earthinv_f.hex                   |  129 ++
 .../rtl/roms/earthinv_g.hex                   |  129 ++
 .../rtl/roms/earthinv_h.hex                   |  129 ++
 .../Super Earth Invasion_MiST/rtl/spram.vhd   |   55 +
 .../Super Earth Invasion_MiST/rtl/sprom.vhd   |   82 +
 .../Vortex_MiST/README.txt                    |   26 +
 .../Vortex_MiST/Vortex.qpf                    |   30 +
 .../Vortex_MiST/Vortex.qsf                    |  176 ++
 .../Vortex_MiST/clean.bat                     |   16 +
 .../Vortex_MiST/rtl/T80/T80.vhd               | 1080 +++++++++
 .../Vortex_MiST/rtl/T80/T8080se.vhd           |  194 ++
 .../Vortex_MiST/rtl/T80/T80_ALU.vhd           |  361 +++
 .../Vortex_MiST/rtl/T80/T80_MCode.vhd         | 1944 +++++++++++++++++
 .../Vortex_MiST/rtl/T80/T80_Pack.vhd          |  217 ++
 .../Vortex_MiST/rtl/T80/T80_Reg.vhd           |  114 +
 .../Vortex_MiST/rtl/Vortex_memory.sv          |   80 +
 .../Vortex_MiST/rtl/Vortex_mist.sv            |  191 ++
 .../Vortex_MiST/rtl/build_id.tcl              |   35 +
 .../Vortex_MiST/rtl/invaders.vhd              |  283 +++
 .../Vortex_MiST/rtl/invaders_audio.vhd        |  496 +++++
 .../Vortex_MiST/rtl/mw8080.vhd                |  336 +++
 .../Vortex_MiST/rtl/pll.qip                   |    4 +
 .../Vortex_MiST/rtl/pll.vhd                   |  382 ++++
 .../Vortex_MiST/rtl/roms/1.t36.vhd            |  150 ++
 .../Vortex_MiST/rtl/roms/2.t35.vhd            |  150 ++
 .../Vortex_MiST/rtl/roms/3.t34.vhd            |  150 ++
 .../Vortex_MiST/rtl/roms/4.t33.vhd            |  150 ++
 .../Vortex_MiST/rtl/roms/5.t32.vhd            |  150 ++
 .../Vortex_MiST/rtl/roms/6.t31.vhd            |  150 ++
 .../Vortex_MiST/rtl/spram.vhd                 |   55 +
 .../WesternGunPtII_MiST/README.txt            |   27 +
 .../WesternGunPtII_MiST/WesternGunPtII.qpf    |   31 +
 .../WesternGunPtII_MiST/WesternGunPtII.qsf    |  172 ++
 .../WesternGunPtII_MiST/WesternGunPtII.sdc    |  126 ++
 .../WesternGunPtII_MiST/clean.bat             |   15 +
 .../WesternGunPtII_MiST/rtl/T80/T80.vhd       | 1080 +++++++++
 .../WesternGunPtII_MiST/rtl/T80/T8080se.vhd   |  194 ++
 .../WesternGunPtII_MiST/rtl/T80/T80_ALU.vhd   |  361 +++
 .../WesternGunPtII_MiST/rtl/T80/T80_MCode.vhd | 1944 +++++++++++++++++
 .../WesternGunPtII_MiST/rtl/T80/T80_Pack.vhd  |  217 ++
 .../WesternGunPtII_MiST/rtl/T80/T80_Reg.vhd   |  114 +
 .../WesternGunPtII_MiST/rtl/build_id.tcl      |   35 +
 .../WesternGunPtII_MiST/rtl/invaders.vhd      |  277 +++
 .../rtl/invaders_audio.vhd                    |  496 +++++
 .../WesternGunPtII_MiST/rtl/mw8080.vhd        |  336 +++
 .../WesternGunPtII_MiST/rtl/pll.qip           |    4 +
 .../WesternGunPtII_MiST/rtl/pll.vhd           |  382 ++++
 .../WesternGunPtII_MiST/rtl/roms/ic32.hex     |   66 +
 .../WesternGunPtII_MiST/rtl/roms/ic33.hex     |   66 +
 .../WesternGunPtII_MiST/rtl/roms/ic34.hex     |   66 +
 .../WesternGunPtII_MiST/rtl/roms/ic35.hex     |   66 +
 .../rtl/roms/ic35sound.hex                    |   66 +
 .../WesternGunPtII_MiST/rtl/roms/ic36.hex     |   66 +
 .../WesternGunPtII_MiST/rtl/spram.vhd         |   55 +
 .../WesternGunPtII_MiST/rtl/sprom.vhd         |   82 +
 .../rtl/westerngun_memory.sv                  |   93 +
 .../rtl/westerngun_mist.sv                    |  218 ++
 .../rtl/westerngun_overlay.vhd                |  127 ++
 462 files changed, 107070 insertions(+)
 create mode 100644 Arcade_MiST/.gitignore
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qpf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qsf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.sdc
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/README.txt
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/Snapshot/280ZZZAP.rbf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/clean.bat
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/doc/Schematic.png
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_Overlay.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_memory.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_mist.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T8080se.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_ALU.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_MCode.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Pack.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Reg.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/build_id.tcl
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders_audio.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/mw8080.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.qip
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_c.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_d.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_e.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_f.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_g.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_h.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/spram.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/sprom.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qpf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qsf
 rename Arcade_MiST/Midway-Taito 8080 Hardware/{README Vortex.txt => BalloonBomber_MiST/README.txt} (100%)
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/clean.bat
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_Overlay.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_memory.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_mist.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T8080se.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_ALU.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_MCode.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Pack.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Reg.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/build_id.tcl
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders_audio.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/mw8080.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.qip
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/ballbomb.zip
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn01
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn01.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn02
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn02.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn03
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn03.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn04
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn04.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn05-1
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn05-1.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/spram.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qpf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qsf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.sdc
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/README.txt
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/Snapshot/BlueShark.rbf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/clean.bat
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/doc/Blue_Shark_-_1978_-_Midway_Games.pdf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_Overlay.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_memory.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_mist.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T8080se.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_ALU.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_MCode.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Pack.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Reg.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/build_id.tcl
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders_audio.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/mw8080.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.qip
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_f.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_g.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_h.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/spram.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/sprom.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qpf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qsf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/README.txt
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/clean.bat
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/SpaceWalk_mist.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T8080se.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_ALU.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_MCode.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_Pack.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_Reg.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/build_id.tcl
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_audio.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_memory.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_video.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/mw8080.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/pll.qip
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/pll.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/rome.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romf.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romg.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romh.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/spram.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/sprom.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qpf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qsf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.sdc
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/README.txt
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/Snapshot/BowlingAlley.rbf
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 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/build_id.tcl
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/invaders.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/invaders_audio.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/mw8080.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/pll.qip
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/pll.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/clr.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la01.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la02.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la03.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la04.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_memory.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_mist.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_overlay.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spram.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/sprom.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/README.txt
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qpf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qsf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.sdc
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/clean.bat
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/SpaceWalk.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_memory.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_overlay.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T8080se.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_ALU.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_MCode.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Pack.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Reg.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/build_id.tcl
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders_audio.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/mw8080.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.qip
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.vhd
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 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.a.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.b.bin
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.b.hex
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 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.c.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.d.bin
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.d.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.e.bin
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.e.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.f.bin
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.f.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.g.bin
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.g.hex
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 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.h.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/spram.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/sprom.vhd
 rename Arcade_MiST/Midway-Taito 8080 Hardware/{README SuperEarthInvasion.txt => Super Earth Invasion_MiST/README.txt} (100%)
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qpf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qsf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.sdc
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/clean.bat
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_memory.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_mist.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_overlay.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T8080se.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_ALU.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_MCode.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Pack.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Reg.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/build_id.tcl
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/dac.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/invaders.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/invaders_audio.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/mw8080.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.qip
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_e.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_f.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_g.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_h.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/spram.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/sprom.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/README.txt
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qpf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qsf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/clean.bat
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T8080se.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_ALU.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_MCode.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Pack.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Reg.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_memory.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_mist.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/build_id.tcl
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders_audio.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/mw8080.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.qip
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/1.t36.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/2.t35.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/3.t34.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/4.t33.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/5.t32.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/6.t31.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/spram.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/README.txt
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.qpf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.qsf
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.sdc
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/clean.bat
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T8080se.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_ALU.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_MCode.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_Pack.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_Reg.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/build_id.tcl
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/invaders.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/invaders_audio.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/mw8080.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/pll.qip
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/pll.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic32.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic33.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic34.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic35.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic35sound.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic36.hex
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/spram.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/sprom.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_memory.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_mist.sv
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_overlay.vhd

diff --git a/Arcade_MiST/.gitignore b/Arcade_MiST/.gitignore
new file mode 100644
index 00000000..345e6aef
--- /dev/null
+++ b/Arcade_MiST/.gitignore
@@ -0,0 +1 @@
+Test
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qpf
new file mode 100644
index 00000000..78f1c762
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:27:39  November 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:27:39  November 20, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "280ZZZAP"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qsf
new file mode 100644
index 00000000..d88d2228
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qsf	
@@ -0,0 +1,172 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 20:51:02  August 09, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		280ZZZAP_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/D280ZZZAP_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/D280ZZZAP_memory.sv
+set_global_assignment -name VHDL_FILE rtl/D280ZZZAP_Overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY D280ZZZAP_mist
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ----------------------------
+# start ENTITY(D280ZZZAP_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(D280ZZZAP_mist)
+# --------------------------
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.sdc
new file mode 100644
index 00000000..f91c127c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/README.txt
new file mode 100644
index 00000000..50120049
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/README.txt	
@@ -0,0 +1,27 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: 280zzzap port to MiST by Gehstock 
+-- 05 June 2019
+-- 
+---------------------------------------------------------------------------------
+-- 
+-- Midway 8080 Hardware
+-- Audio based on work by Paul Walsh.
+-- Audio and scan converter by MikeJ.
+---------------------------------------------------------------------------------
+-- 
+-- 
+-- Keyboard inputs :
+--
+--   F1          : Start
+--   SPACE       : Fire
+--   RIGHT/LEFT  : Movement
+--
+-- Joystick support.
+-- 
+-- 
+---------------------------------------------------------------------------------
+ToDo: Color Prom
+      Controls + DIP
+	
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/Snapshot/280ZZZAP.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/Snapshot/280ZZZAP.rbf
new file mode 100644
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/clean.bat
new file mode 100644
index 00000000..83fb0c47
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/doc/Schematic.png b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/doc/Schematic.png
new file mode 100644
index 0000000000000000000000000000000000000000..14892003c5b9de7ce7e86c16612fccf7bf803161
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_Overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_Overlay.vhd
new file mode 100644
index 00000000..54588682
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_Overlay.vhd	
@@ -0,0 +1,111 @@
+--Datsun 280 ZZZAP Color Overlay Gehstock 2019
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+entity D280ZZZAP_Overlay is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end D280ZZZAP_Overlay;
+
+architecture rtl of D280ZZZAP_Overlay is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_B1      : boolean;
+	signal Overlay_B1_VCnt : boolean;
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+	signal col_data        : std_logic_vector(3 downto 0);
+	signal col_addr        : std_logic_vector(9 downto 0);
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  Overlay_B1_VCnt <= false;
+	  Overlay_B1 <= false;
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt >= x"C4") then
+		  Overlay_B1_VCnt <= true;
+		else
+		  Overlay_B1_VCnt <= false;
+		end if;
+	  end if;
+
+	  if (HCnt <= x"0") and Overlay_B1_VCnt then
+		Overlay_B1 <= true;
+	  elsif (HCnt >= x"228") then
+		Overlay_B1 <= false;
+	  end if;
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video, Overlay_B1)
+  begin
+	if (Video = '0') then
+	  VideoRGB  <= "000";
+	else
+	  if Overlay_B1 then
+		VideoRGB  <= "001";
+	  else
+		VideoRGB  <= "111";
+	  end if;
+	end if;
+  end process;
+  
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_HSYNC   <= HSync;
+  O_VSYNC   <= VSync;
+
+
+end;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_memory.sv
new file mode 100644
index 00000000..fd2ac6a0
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_memory.sv	
@@ -0,0 +1,104 @@
+module D280ZZZAP_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+wire [7:0]rom_data_4;
+wire [7:0]rom_data_5;
+
+
+sprom #(
+	.init_file("./roms/zzzap_h.hex"),
+	.widthad_a(10), 
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_0)
+	);
+	
+sprom #(
+	.init_file("./roms/zzzap_g.hex"),
+	.widthad_a(10), 
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_1)
+	);	
+
+sprom #(
+	.init_file("./roms/zzzap_f.hex"),
+	.widthad_a(10), 
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_2)
+	);
+	
+sprom #(
+	.init_file("./roms/zzzap_e.hex"),
+	.widthad_a(10), 
+	.width_a(8))
+u_rom_e (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_3)
+	);
+
+sprom #(
+	.init_file("./roms/zzzap_d.hex"),
+	.widthad_a(10), 
+	.width_a(8))
+u_rom_d (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_4)
+	);
+	
+sprom #(
+	.init_file("./roms/zzzap_c.hex"),
+	.widthad_a(10), 
+	.width_a(8))
+u_rom_c (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_5)
+	);
+	
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5) begin
+	Rom_out = 8'b00000000;
+		case (Addr[15:10])
+			6'b000000 : Rom_out = rom_data_0; //0
+			6'b000001 : Rom_out = rom_data_1; //0400
+			6'b000010 : Rom_out = rom_data_2; //0800
+			6'b000011 : Rom_out = rom_data_3; //0c00		
+			6'b000100 : Rom_out = rom_data_4; //1000
+			6'b000101 : Rom_out = rom_data_5; //1400
+
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_mist.sv
new file mode 100644
index 00000000..da613e03
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_mist.sv	
@@ -0,0 +1,228 @@
+module D280ZZZAP_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"280ZZZAP;;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Overlay, On, Off;",
+	"T6,Reset;",
+	"V,v0.00.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_core, clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+/*
+Dip Switch:E3
+1		2		3		4		5		6		7		8		Function	Option
+Coinage
+On		On	 	 	 	 	 	 								1 Coin/1 Credit*
+Off	On	 	 	 	 	 	 								1 Coin/2 Credits
+On		Off	 	 	 	 	 	 							2 Coins/1 Credit
+Off	Off	 	 	 	 	 	 							2 Coins/3 Credits
+Game Time
+				Off	On	 	 	 	 						Test Mode
+When Extended Time At not set to None
+				Off	Off	 	 	 	 					60 seconds + 30 extended
+				On		On	 	 	 	 						80 seconds + 40 extended*
+				On		Off	 	 	 	 					99 seconds + 50 extended
+When Extended Time At set to None
+				Off	Off	 	 	 	 					60 seconds
+				On		On	 	 	 	 						80 seconds*
+				On		Off	 	 	 	 					99 seconds
+Extended Time At				
+								Off	On	 	 				2.00
+								On		On	 	 				2.50*
+								Off	Off	 	 			None
+								On		Off	 	 			None
+Language								
+												On		On		English*
+												On		Off	French
+												Off	On		German
+												Off	Off	Spanish
+*/
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+	.DIP("00000000"),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(HSync),
+	.VSync(VSync)
+	);
+		
+D280ZZZAP_memory D280ZZZAP_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_core),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);		
+	  
+D280ZZZAP_Overlay D280ZZZAP_Overlay (
+	.Video(Video),
+	.Overlay(~status[5]),
+	.CLK(clk_core),
+	.Rst_n_s(Rst_n_s),
+	.HSync(HSync),
+	.VSync(VSync),
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({r,r,r}),
+	.G({g,g,g}),
+	.B({b,b,b}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ce_divider(0),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_left   = btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_fire1 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T8080se.vhd
new file mode 100644
index 00000000..65b92d54
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T8080se.vhd	
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..e09def1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..1c0f2638
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..ce639856
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders.vhd	
@@ -0,0 +1,245 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: entity work.mw8080
+		port map(
+			Rst_n => Rst_n,--Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+--IN0
+	GDB0(0) <= '0';	-- PEDAL
+	GDB0(1) <= '0';	-- PEDAL
+	GDB0(2) <= '0';	-- PEDAL
+	GDB0(3) <= '1';	-- PEDAL
+	GDB0(4) <= not Fire;	-- fire
+	GDB0(5) <= '1';	-- UNUSED
+	GDB0(6) <= not Coin;	-- coin
+	GDB0(7) <= not Sel1Player;	-- start
+--IN1
+	GDB1(0) <= '0';	-- steering wheel 
+	GDB1(1) <= '0';	-- steering wheel 
+	GDB1(2) <= '0';	-- steering wheel 
+	GDB1(3) <= '0';	-- steering wheel 
+	GDB1(4) <= '0';	-- steering wheel 
+	GDB1(5) <= '0';	-- steering wheel 
+	GDB1(6) <= '0';	-- steering wheel 
+	GDB1(7) <= '1';	-- steering wheel 
+--IN2
+	GDB2(0) <= '0';--Coinage
+	GDB2(1) <= '0';--Coinage
+	GDB2(2) <= '1';--Game_Time
+	GDB2(3) <= '1';--Game_Time
+	GDB2(4) <= '1';--Extended Time At
+	GDB2(5) <= '1';--Extended Time At
+	GDB2(6) <= '0';--Language
+	GDB2(7) <= '0';--Language
+	
+
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..f16cf379
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..1d9ad578
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,335 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..f8d0b139
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.vhd	
@@ -0,0 +1,382 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 20,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_c.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_c.hex
new file mode 100644
index 00000000..11797d04
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_c.hex	
@@ -0,0 +1,65 @@
+:10000000821491141F139B14AA14BE145F13D014EE
+:10001000931228142F143614051511151F152C15BD
+:10002000D013D013870000000C313630404BCD0C7C
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+:1000A0003A080350554E4B5445BA03484F45434810
+:1000B0005354454050554E4B545A41484CBA034C4A
+:1000C00045545A54454050554E4B545A41484CBAE9
+:1000D0000247524154554C494552453F0253494508
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+:100390004C414E544552C107564140454E4053458D
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+:1003E0004741404C41404D4F4E4544C10841474173
+:1003F00043484140454C40424F544FCEFFFFFFFF22
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_d.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_d.hex
new file mode 100644
index 00000000..c9b37f45
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_d.hex	
@@ -0,0 +1,65 @@
+:10000000DB02070707E6065F1600195E2356C93AAA
+:100010004A20A7F8213620467E23BECA3710AE7884
+:10002000FA2B10BED22F1035C33010BED227103499
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+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_e.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_e.hex
new file mode 100644
index 00000000..305e1499
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_e.hex	
@@ -0,0 +1,65 @@
+:10000000B60D3E033223203A4420324220F781CD00
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_f.hex
new file mode 100644
index 00000000..a5046190
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_f.hex	
@@ -0,0 +1,65 @@
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+:1003F000094E213E207EE6F02B860F0F0F0FB9DA53
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_g.hex
new file mode 100644
index 00000000..10f77477
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_g.hex	
@@ -0,0 +1,65 @@
+:1000000008112000711905C20404E76DFF190405E9
+:100010003E042B000527050F043B002704139D0514
+:100020002204271D06220436FE3504033E04300454
+:1000300003B40439047F0000000327052B040326C2
+:100040000000800100800700E00F00BC1F00E61BDD
+:1000500000671B007F0F03EE81073CC00F10FC1FE1
+:1000600010C00F20400F40E00F80F00F80C10F80C4
+:10007000C10700030300830700FE3F00FE7F00E08E
+:10008000EF0080CF0080CF0080CF0080CF0080DFE6
+:1000900000C0DF00C01F00E01F00F00E00700E0067
+:1000A000380E00381C00303800707000606000604E
+:1000B0006000787803252000800100800700E00FB1
+:1000C00000BC1900F61900FF1F03EF8F07EEC10FE8
+:1000D0003CFC1F10C00F20400F40E00F80F00F804D
+:1000E000C10F80C10700030300830700FE0F00FE5D
+:1000F0000F00E00F00800F00800F00800F00800FC6
+:1001000000801F00801F00801F00801F00800F00E4
+:1001100080070080070080070080030000030000C4
+:100120000300000300C003032600008001008007D5
+:1001300000E00D00F81D009E1F009F1B00FF0F0335
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+:1001700000806F00806F00803F00801F00801F00A4
+:10018000C01F00C01F00C00700E00300E01900E02E
+:100190001C006038006070006060007878041FDF29
+:1001A0000000003000000078000000FC0000C0FFEC
+:1001B000013303FC003303F400CC00FE00CC00FF4D
+:1001C000003303FC0033037C00CC003000CC00F88B
+:1001D00000FFFFFF1F00F0FF3F0000FF700000FC6A
+:1001E000E00000FCC00000F8810000F8810000F889
+:1001F000810000FC030000FC030000DE0300008E11
+:1002000003000007070080030E008001FC0080014E
+:10021000F8008001800080018000E00180041FDF81
+:10022000009F0F3000930D7800830DFC0083CDFFFD
+:10023000019B0DFC00930DF4009F0FFE000000FCDD
+:10024000000020F80000807C00000030000000F872
+:1002500000FFFFFF1F33E3FF3F3303FF70CC00FCC1
+:10026000E0CC00FCC03303F8813303F881CC00F804
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+:1002D000E0062124207E3CE60177E1D1C1F1FBC993
+:1002E0003A2220A7FA9D0AC80FD231082A2720CD2A
+:1002F000C909CDC909CDC909CDC909CDC909CDC91A
+:1003000009012000CDE509CDE509CDE509CDE509D7
+:10031000CDE509CDE5092A2520CDFB09CDFB09CD89
+:10032000FB09CDFB09CDFB09CDFB09CD330ACD334C
+:100330000ACD330ACD330ACD330ACD330ACDEF08C7
+:100340003A3E2121432135F26D073603213E217EBD
+:1003500023BECA6D07DA6607FE04D26107AFC36B1E
+:1003600007D604C36B075F3A5A20832B775F1600CA
+:100370002A47207CA7CA7C07192247202A49207CCB
+:10038000A7CA880719224920EB29292929EB2A3BEA
+:100390002019223B207C2FE61FC6403203204A163C
+:1003A000003A3720CD5C08F5783202203A2220EE60
+:1003B00003CA30083A3E21A7CA30083A372047CD51
+:1003C00087080F0F0FE6062F3CC60BB9D2E8072FA0
+:1003D0003C813C0FE6034F324121F17842A7F20104
+:1003E00008792F3C4FC3FF07AF324121790FE60751
+:1003F00081793A3A20CD5C0842D1824FF201080659
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_h.hex
new file mode 100644
index 00000000..c013d6e0
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_h.hex	
@@ -0,0 +1,65 @@
+:100000000000AFD305C36400F5C5D50E00C39E063E
+:10001000F5C5D50E01C39E06E3D5C5F5E92530200B
+:10002000E1F1C1D1E1C93500C3160F05B4041404D0
+:10003000E37E23E3CD910F77DF215E207E23B6E6BA
+:100040001FCA5D0001FF1DCD6201215E207ECD5ED5
+:100050000F237ECD5E0FE701FF1DC3620101001D6E
+:10006000CD6201E7DB02E60CFE04C2610B06011162
+:100070000000210020D307707EA8CA8C004F7DE6C7
+:100080000179C28A00B257C38C00B35F237CFE4063
+:10009000C27500D3072B7CFE1FCAC9007EA8CAB058
+:1000A000004F7DE60179C2AE00B257C3B000B35F26
+:1000B000782F77AECA93004F7DE60179C2C400B2B3
+:1000C00057C3C600B35FC39300D307237CFE40CA67
+:1000D000EC00782FAECAE7004F7DE60179C2E5005B
+:1000E000B257C3E700B35FAF77C3C900780747D201
+:1000F00072007AB3CA1B01EBF9110020060021003F
+:1001000000390E10AF29DA0A012F12133E1812130C
+:100110000DC2040105C2FE00C35401310024210CAC
+:1001200028E5210000115901010004AF86D30723FF
+:100130000DC22C0105C22C01A7CA46011AE3EBC56A
+:10014000CD8103C1EBE3137CFE18C22801E17DFEE3
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+:10017000C5C5C5C5C5C5C5C5C5C5C5C5C5C5C53DB7
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+:1001B00066667E7E606060603E3E06063E7E6066ED
+:1001C0007E3C3C3E06063E7E66667E3C7E7E6070E1
+:1001D0003038181C0C0C3C7E66663C7E66667E3CA5
+:1001E0003C7E66667E7C60607C3C001818000000E7
+:1001F00000181800FFFFFFFFFFFF7777FFFF7F7FEB
+:100200007F7F7FFF7777FFFF1F7F1FDF1FFF7777DE
+:10021000FFFF000000000000000018181818181850
+:10022000181800001818000000000000000000006E
+:10023000183C7E6666667E7E66663E7E66663E7EAE
+:1002400066667E3E3C7E6606060606667E3C3E7E12
+:100250006666666666667E3E7E7E06063E3E0606EE
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+:100280003C3C1818181818183C3C606060606060AE
+:1002900060667E3C6666763E1E1E3E766666060696
+:1002A0000606060606067E7EC3C3E7E7FFFFDBC33E
+:1002B000C3C366666E6E7E7E767666663C7E6666D6
+:1002C000666666667E3C3E7E66667E3E0606060680
+:1002D0003C7E6666666666667E5C3E7E66667E3EE2
+:1002E000766666663C7E66063E7C60667E3C7E7E0A
+:1002F000181818181818181866666666666666660E
+:100300007E3C66666666667E3C3C1818C3C3C3DBEB
+:10031000FFFFE7E7C3C366667E3C18183C7E66664F
+:1003200066667E3C1818181818187E7E6070381C97
+:100330000E067E7E1155555511FF7777F7F7115749
+:10034000515D11FF7777F7F71555515717FF7777FD
+:10035000F7F7115D515511FF7777F7F711555155A3
+:1003600011FF7777F7F77EE6F0C275033E40CD8147
+:1003700003C37C037E07070707CD7D037EE60FC618
+:1003800030E67FFE300600D28F034FEB09EBC9E564
+:10039000D5CDB2037CFE3B3E00DA9D032F4FC51A3C
+:1003A00013A97701200009C105C29E03D113E1C939
+:1003B0000600D6304F6069292929090901860109FB
+:1003C000060AEBC9CD8810E61C4F060021A50F09CF
+:1003D0001100280604CDE2037BC6085F2305C2D5C1
+:1003E00003C97EDFCDB003E51A131FDCFA0323A790
+:1003F000C2EA03E12405C2E703E7E5D5C5F501FF3D
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qpf
new file mode 100644
index 00000000..e97e5097
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 16:15:41  June 05, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:15:41  June 05, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "BalloonBomber"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qsf
new file mode 100644
index 00000000..37310fc8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qsf	
@@ -0,0 +1,177 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 02:57:11  June 09, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		BalloonBomber_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name TOP_LEVEL_ENTITY BalloonBomber_mist
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ---------------------------
+# start ENTITY(OzmaWars_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(OzmaWars_mist)
+# -------------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/BalloonBomber_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/BalloonBomber_memory.sv
+set_global_assignment -name VHDL_FILE rtl/BalloonBomber_Overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+set_global_assignment -name VHDL_FILE rtl/roms/tn07.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/tn06.vhd
+set_global_assignment -name VHDL_FILE "rtl/roms/tn05-1.vhd"
+set_global_assignment -name VHDL_FILE rtl/roms/tn04.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/tn03.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/tn02.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/tn01.vhd
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/README Vortex.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Midway-Taito 8080 Hardware/README Vortex.txt
rename to Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/README.txt
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/clean.bat
new file mode 100644
index 00000000..ac9bf0a8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/clean.bat	
@@ -0,0 +1,16 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s build_id.v
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_Overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_Overlay.vhd
new file mode 100644
index 00000000..ceecfaf1
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_Overlay.vhd	
@@ -0,0 +1,366 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+
+--Not Cleaned, iam to lazy for this
+
+
+entity BalloonBomber_Overlay is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		CAB               : in    std_logic_vector(9 downto 0);
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end BalloonBomber_Overlay;
+
+architecture rtl of BalloonBomber_Overlay is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_A1      : boolean;
+	signal Overlay_A1_VCnt : boolean;
+	signal Overlay_A2      : boolean;
+	signal Overlay_A3      : boolean;
+	signal Overlay_A3_VCnt : boolean;	
+	signal Overlay_A4      : boolean;
+	signal Overlay_A4_VCnt : boolean;	
+	
+	signal Overlay_R1      : boolean;
+	signal Overlay_R1_VCnt : boolean;
+	signal Overlay_R2      : boolean;
+	signal Overlay_R3      : boolean;
+
+	signal Overlay_Y1      : boolean;
+	signal Overlay_Y1_VCnt : boolean;
+	signal Overlay_Y2      : boolean;
+	signal Overlay_Y3      : boolean;
+	signal Overlay_Y4      : boolean;
+	signal Overlay_Y4_VCnt : boolean;	
+	signal Overlay_Y5      : boolean;	
+	signal Overlay_Y5_VCnt : boolean;
+
+	signal Overlay_G1      : boolean;
+	signal Overlay_G1_VCnt : boolean;	
+	signal Overlay_G2      : boolean;
+   signal Overlay_G3      : boolean;
+	signal Overlay_G4      : boolean;
+	signal Overlay_G4_VCnt : boolean;	
+
+   signal Overlay_P1      : boolean;
+	signal Overlay_P2      : boolean;
+	signal Overlay_P2_VCnt : boolean;	
+	signal Overlay_P3      : boolean;
+	signal Overlay_P3_VCnt : boolean;
+	signal Overlay_P4      : boolean;
+	signal Overlay_P4_VCnt : boolean;
+	
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+	signal COLOR        : std_logic_vector(3 downto 0);
+
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  
+	  Overlay_G1 <= false;
+	  Overlay_G1_VCnt <= false;
+	  Overlay_G2 <= false;
+	  Overlay_G3 <= false;
+	  Overlay_G4 <= false;
+	  Overlay_G4_VCnt <= false;
+	  
+	  Overlay_A1 <= false;
+	  Overlay_A1_VCnt <= false;
+	  Overlay_A2 <= false;
+	  Overlay_A3 <= false;
+	  Overlay_A3_VCnt <= false;
+	  Overlay_A4 <= false;
+	  Overlay_A4_VCnt <= false;
+	  
+	  Overlay_R1 <= false;
+	  Overlay_R1_VCnt <= false;	  
+	  Overlay_R2 <= false;
+	  Overlay_R3 <= false;
+	  
+	  Overlay_Y1 <= false;
+	  Overlay_Y1_VCnt <= false;	  
+	  Overlay_Y2 <= false;
+	  Overlay_Y3 <= false;
+	  Overlay_Y4 <= false;
+	  Overlay_Y4_VCnt <= false;	  
+	  Overlay_Y5 <= false;
+	  Overlay_Y5_VCnt <= false;
+	  
+	  Overlay_P1 <= false;
+	  Overlay_P3 <= false;
+	  Overlay_P3_VCnt <= false;
+	  Overlay_P4 <= false;
+	  Overlay_P4_VCnt <= false;
+	  
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt >= 0) and (Vcnt <= 99) then
+		  Overlay_A1_VCnt <= true;
+		else
+		  Overlay_A1_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 100) and (Vcnt <= 149 ) then
+		  Overlay_R1_VCnt <= true;
+		else
+		  Overlay_R1_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 150) and (Vcnt <= 240) then
+		  Overlay_Y1_VCnt <= true;
+		else
+		  Overlay_Y1_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 236) and (Vcnt <= 16) then
+		  Overlay_G1_VCnt <= true;
+		else
+		  Overlay_G1_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 0) and (Vcnt <= 72) then
+		  Overlay_G4_VCnt <= true;
+		  Overlay_Y5_VCnt <= true;
+		else
+		  Overlay_G4_VCnt <= false;
+		  Overlay_Y5_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 73) and (Vcnt <= 200) then
+		  Overlay_P3_VCnt <= true;
+		else
+		  Overlay_P3_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 224) and (Vcnt <= 230) then
+		  Overlay_P4_VCnt <= true;
+		else
+		  Overlay_P4_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 160) and (Vcnt <= 166 ) then
+		  Overlay_A3_VCnt <= true;
+		else
+		  Overlay_A3_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 24 ) and (Vcnt <= 230 ) then
+		  Overlay_A4_VCnt <= true;
+		else
+		  Overlay_A4_VCnt <= false;
+		end if;
+	  
+	  	if (Vcnt >= 32 ) and (Vcnt <= 222 ) then
+		  Overlay_P2_VCnt <= true;
+		else
+		  Overlay_P2_VCnt <= false;
+		end if;
+	  end if;
+	  
+	  	if (Vcnt >= 42 ) and (Vcnt <= 216 ) then------------------------------------
+		  Overlay_Y4_VCnt <= true;
+		else
+		  Overlay_Y4_VCnt <= false;
+		end if;
+	  
+	  if (HCnt = 518)then--ok
+		if  Overlay_A1_VCnt then Overlay_A1 <= true; end if;
+		if  Overlay_R1_VCnt then Overlay_R1 <= true; end if;
+		if  Overlay_Y1_VCnt then Overlay_Y1 <= true; end if;
+	  elsif (HCnt >= 540) then
+		if  Overlay_A1_VCnt then Overlay_A1 <= false; end if;
+		if  Overlay_R1_VCnt then Overlay_R1 <= false; end if;
+		if  Overlay_Y1_VCnt then Overlay_Y1 <= false; end if;
+	  end if;
+	  
+	  if (HCnt = 528)then--check
+		if  Overlay_G1_VCnt then Overlay_G1 <= true; end if;
+	  elsif (HCnt >= 540) then
+		if  Overlay_G1_VCnt then Overlay_G1 <= false; end if;
+	  end if;
+	    
+	  if (HCnt = 486) then--ok
+		Overlay_R2 <= true;
+	  elsif (HCnt = 502) then
+		Overlay_R2 <= false;
+	  end if;
+
+	  if (HCnt = 438) then--ok
+		Overlay_Y2 <= true;
+	  elsif (HCnt = 470) then
+		Overlay_Y2 <= false;	
+	  end if;
+	  
+	  if (HCnt = 373) then--ok
+		Overlay_G2 <= true;
+	  elsif (HCnt = 445) then
+		Overlay_G2 <= false;
+	  end if;
+	  
+	  if (HCnt = 324) then--ok
+		Overlay_P1 <= true;
+	  elsif (HCnt = 380) then
+		Overlay_P1 <= false;
+	  end if;
+	  
+	  if (HCnt = 275) then--ok
+		Overlay_A2 <= true;
+	  elsif (HCnt = 327) then
+		Overlay_A2 <= false;
+	  end if;
+
+	  if (HCnt = 210) then--ok
+		Overlay_Y3 <= true;
+	  elsif (HCnt = 274) then
+		Overlay_Y3 <= false;
+	  end if;
+	  
+	  if (HCnt = 166) then--ok
+		Overlay_R3 <= true;
+	  elsif (HCnt = 214) then
+		Overlay_R3 <= false;
+	  end if;	  
+
+	  if (HCnt = 70) then--ok
+		Overlay_G3 <= true;
+	  elsif (HCnt = 170) then
+		Overlay_G3 <= false;
+	  end if;
+	  
+	  if (HCnt = 70) then--check
+		if  Overlay_P4_VCnt then Overlay_P4 <= true; end if;
+	  elsif (HCnt = 86) then
+		if  Overlay_P4_VCnt then Overlay_P4 <= false; end if;
+	  end if;
+	  
+	  if (HCnt = 0) then--ok
+		if  Overlay_Y5_VCnt then Overlay_Y5 <= true; end if;
+		if  Overlay_P3_VCnt then Overlay_P3 <= true; end if;
+	  elsif (HCnt = 70) then
+		if  Overlay_Y5_VCnt then Overlay_Y5 <= false; end if;
+		if  Overlay_P3_VCnt then Overlay_P3 <= false; end if;
+	  end if;
+	  
+	  if (HCnt = 164) then--check
+		if  Overlay_A3_VCnt then Overlay_A3 <= true; end if;
+	  elsif (HCnt = 172) then
+		if  Overlay_A3_VCnt then Overlay_A3 <= false; end if;
+	  end if;
+	  
+	  if (HCnt = 118) then--check
+		if  Overlay_A4_VCnt then Overlay_A4 <= true; end if;
+	  elsif (HCnt = 134) then
+		if  Overlay_A4_VCnt then Overlay_A4 <= false; end if;
+	  end if;
+	 
+	  if (HCnt = 102) then--check
+		if  Overlay_P2_VCnt then Overlay_P2 <= true; end if;
+	  elsif (HCnt = 118) then
+		if  Overlay_P2_VCnt then Overlay_P2 <= false; end if;
+	  end if;
+	  
+	  if (HCnt = 86) then--check
+		if  Overlay_Y4_VCnt then Overlay_Y4 <= true; end if;
+	  elsif (HCnt = 102) then
+		if  Overlay_Y4_VCnt then Overlay_Y4 <= false; end if;
+	  end if; 
+	  
+	  if (HCnt = 486) then--ok
+		if  Overlay_G4_VCnt then Overlay_G4 <= true; end if;
+	  elsif (HCnt = 470) then
+		if  Overlay_G4_VCnt then Overlay_G4 <= false; end if;
+	  end if;
+
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video)
+  begin
+	if (Video = '0') then
+		VideoRGB  <= "000";
+	elsif Overlay_R1 or Overlay_R2 or (Overlay_R3 and not Overlay_A3) then--Red      
+		VideoRGB  <= "100";
+	elsif Overlay_A1 or Overlay_A2 or Overlay_A3 or Overlay_A4 then--Aqua
+		VideoRGB  <= "011";
+	elsif (Overlay_Y1 and not Overlay_G1) or Overlay_Y2 or Overlay_Y3 or Overlay_Y4 or Overlay_Y5 then--Yellow
+		VideoRGB  <= "110";	
+	elsif Overlay_G1 or Overlay_G2 or (Overlay_G3 and not (Overlay_P4 or Overlay_A4 or Overlay_P2 or Overlay_Y4))-- or Overlay_G4 
+	then
+		VideoRGB  <= "010";	
+	elsif Overlay_P1 or Overlay_P2 or Overlay_P3 or Overlay_P4 then--Purple
+		VideoRGB  <= "101";		
+--	elsif not (Overlay_G4) then--white 
+	else
+		VideoRGB  <= "111";-- end if;
+	end if;
+  end process;
+  
+--colPROM: entity work.col
+--port map(
+--	clk  => Clk,
+--	addr => CAB, --should be Video Counters 
+--	data => COLOR
+--);
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  
+--  O_VIDEO_R <= COLOR(2);
+--  O_VIDEO_G <= COLOR(1);
+--  O_VIDEO_B <= COLOR(0);
+  O_HSYNC   <= HSync;
+  O_VSYNC   <= VSync;
+
+
+end;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_memory.sv
new file mode 100644
index 00000000..2dda36ca
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_memory.sv	
@@ -0,0 +1,72 @@
+
+module BalloonBomber_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+wire [7:0]rom_data_4;
+wire [10:0]rom_addr = {Addr[11:10],~Addr[9],Addr[8:4],~Addr[3],Addr[2:1],~Addr[0]};
+
+tn01 tn01 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_0)
+);
+
+tn02 tn02 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_1)
+);
+
+tn03 tn03 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_2)
+);
+
+tn04 tn04 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_3)
+);
+
+tn05_1 tn05_1 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_4)
+);
+	
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4) begin
+	Rom_out = 8'b00000000;
+		case (Addr[15:11])
+			5'b00000 : Rom_out = rom_data_0;
+			5'b00001 : Rom_out = rom_data_1;
+			5'b00010 : Rom_out = rom_data_2;
+			5'b00011 : Rom_out = rom_data_3;
+			5'b01000 : Rom_out = rom_data_4;//0100 0000 0000 0000
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_mist.sv
new file mode 100644
index 00000000..b596dae0
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_mist.sv	
@@ -0,0 +1,208 @@
+module BalloonBomber_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"BallBomb;;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Overlay, On, Off;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_sys, clk_core;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hs, vs;
+wire 			r,g,b;
+
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+	.MoveUp(~m_up),
+	.MoveDown(~m_down),	
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(HSync),
+	.VSync(VSync)
+	);
+		
+BalloonBomber_memory BalloonBomber_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+	
+BalloonBomber_Overlay BalloonBomber_Overlay (
+	.Video(Video),
+	.Overlay(~status[5]),
+	.CLK(clk_core),
+	.Rst_n_s(Rst_n_s),
+	.HSync(HSync),
+	.VSync(VSync),
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs)
+	);
+			
+invaders_audio invaders_audio (
+	.Clk(clk_core),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({r,r,r}),
+	.G({g,g,g}),
+	.B({b,b,b}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ce_divider(0),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_up     = status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+
+
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T8080se.vhd
new file mode 100644
index 00000000..65b92d54
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T8080se.vhd	
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..e09def1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..1c0f2638
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..ca17b82c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders.vhd	
@@ -0,0 +1,281 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		MoveUp          : in  std_logic;
+		MoveDown        : in  std_logic;
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+	component mw8080
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+	end component;
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+	signal GDB_A        : unsigned(1 downto 0);
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: mw8080
+		port map(
+			Rst_n => '1',--Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+--	with AD_i(9 downto 8) select
+--		GDB <= GDB0 when "00",
+--				GDB1 when "01",
+--				GDB2 when "10",
+--				S when others;
+				
+			GDB_A <= not AD_i(9) & AD_i(8);
+
+	with GDB_A select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+	GDB0(0) <= '0';
+	GDB0(1) <= '0';
+	GDB0(2) <= '0';
+	GDB0(3) <= '0';
+	GDB0(4) <= not Fire;
+	GDB0(5) <= not MoveLeft;
+	GDB0(6) <= not MoveRight;
+	GDB0(7) <= '0';
+	
+	GDB1(0) <= Coin;
+	GDB1(1) <= not Sel2Player;
+	GDB1(2) <= not Sel1Player;
+	GDB1(3) <= '1';
+	GDB1(4) <= not Fire;--controller
+	GDB1(5) <= not MoveLeft;--controller
+	GDB1(6) <= not MoveRight;--controller
+	GDB1(7) <= '1';
+
+	GDB2(0) <= '0';--active high
+	GDB2(1) <= '0';--active high
+	GDB2(2) <= '0';--active high
+	GDB2(3) <= '0';--active high
+	GDB2(4) <= '0';--active high
+	GDB2(5) <= '0';--active high
+	GDB2(6) <= '0';--active high
+	GDB2(7) <= '0';--active high
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..f16cf379
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..b9a88f96
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,336 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..f8d0b139
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.vhd	
@@ -0,0 +1,382 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 20,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/ballbomb.zip b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/ballbomb.zip
new file mode 100644
index 0000000000000000000000000000000000000000..02178e7f51e8d17d799287093b2e7ffbc81d32cd
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn01 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn01
new file mode 100644
index 0000000000000000000000000000000000000000..44a8c6ac8e6d6beeff710e1fbe830b5681128890
GIT binary patch
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HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn01.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn01.vhd
new file mode 100644
index 00000000..d27bab74
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn01.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity tn01 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of tn01 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"00",X"00",X"C3",X"18",X"00",X"00",X"00",X"FB",X"C9",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"E5",X"D5",X"C5",X"F5",X"C3",X"D8",X"04",X"FF",X"31",X"00",X"24",X"CD",X"76",X"01",X"06",X"00",
+		X"CD",X"BC",X"04",X"CD",X"C5",X"04",X"CD",X"D0",X"04",X"CD",X"4C",X"00",X"FB",X"AF",X"D3",X"03",
+		X"D3",X"05",X"CD",X"BC",X"00",X"CD",X"BB",X"01",X"CD",X"C1",X"00",X"CD",X"24",X"01",X"CD",X"01",
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+		X"A7",X"CA",X"3E",X"07",X"CD",X"F5",X"01",X"CD",X"1E",X"14",X"CD",X"16",X"07",X"CD",X"EF",X"12",
+		X"CD",X"B6",X"00",X"C3",X"67",X"06",X"3A",X"DB",X"20",X"0F",X"DA",X"33",X"07",X"AF",X"21",X"E5",
+		X"20",X"77",X"F3",X"D3",X"05",X"06",X"0A",X"0E",X"00",X"0D",X"C2",X"29",X"07",X"05",X"C2",X"27",
+		X"07",X"FB",X"C9",X"3E",X"20",X"C3",X"1E",X"07",X"CD",X"EA",X"01",X"C3",X"07",X"07",X"21",X"DB",
+		X"20",X"36",X"00",X"C3",X"38",X"07",X"CD",X"7A",X"06",X"21",X"DB",X"20",X"36",X"00",X"CD",X"44",
+		X"1A",X"A7",X"C2",X"38",X"07",X"21",X"DB",X"20",X"36",X"01",X"C3",X"04",X"07",X"21",X"07",X"28",
+		X"11",X"D4",X"44",X"06",X"14",X"CD",X"60",X"02",X"C3",X"FC",X"00",X"CD",X"52",X"1A",X"2E",X"25",
+		X"7E",X"FE",X"02",X"D8",X"21",X"54",X"20",X"36",X"01",X"C9",X"CD",X"21",X"02",X"21",X"00",X"00",
+		X"22",X"DA",X"20",X"22",X"E4",X"20",X"22",X"E5",X"20",X"22",X"E9",X"20",X"21",X"DA",X"20",X"36",
+		X"01",X"21",X"14",X"2D",X"11",X"DF",X"44",X"06",X"09",X"CD",X"60",X"02",X"3E",X"80",X"CD",X"D5",
+		X"14",X"CD",X"EA",X"01",X"C3",X"2D",X"00",X"11",X"99",X"04",X"CD",X"60",X"02",X"DB",X"01",X"0F",
+		X"0F",X"DA",X"BB",X"07",X"0F",X"DA",X"74",X"05",X"C3",X"57",X"05",X"3E",X"01",X"06",X"98",X"C3",
+		X"77",X"05",X"21",X"05",X"20",X"AF",X"BE",X"C8",X"CD",X"77",X"08",X"22",X"07",X"20",X"2A",X"09",
+		X"20",X"01",X"60",X"00",X"09",X"22",X"09",X"20",X"44",X"21",X"0B",X"20",X"AF",X"BE",X"C2",X"E7",
+		X"07",X"78",X"FE",X"2B",X"D2",X"32",X"08",X"23",X"AF",X"BE",X"C2",X"F3",X"07",X"78",X"FE",X"31",
+		X"D2",X"4D",X"08",X"23",X"AF",X"BE",X"C2",X"FF",X"07",X"78",X"FE",X"37",X"D2",X"5B",X"08",X"23");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn02 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn02
new file mode 100644
index 0000000000000000000000000000000000000000..1fc488a666b1a52fba24635a6f079373116649a3
GIT binary patch
literal 2048
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zut!XU1kk`A@(+T##B3qUD2ei6VhZ#D*{i#8Jb{c(10{4ZY1C<Af(+g~@3osB_m6w;
zIlpty@0@$jJ;_ws&GZ;ieLKtz*=i=hBKmn7`G~;|6sGWHn6!Wk6^eTGHXWY94otpa
z3bju1mM?#m+iB-Ih)%233_xrV;?zb{@)RYZC`m=>8IZ6Og_KD;eUQO>nlv14(r9E)
zUe70FNBS6(qY=ek^`t*$GzBkywQ)p>Q(pB;Cb_?|y{~d|N`$ewcT#l0_)3$0TIIB<
z!$NUA=_M=YlXde+(>(GTOCB*~D;s%;1~YyKIqW0lEU8<h`W?6uDT5=;kYN>4#IZ0H
z@S_4=iBt~<S=Cl4hJ758Po}Pfa2>1e^HG$`MN>58bkY<>m6gG4qiC9@Oy?tTQZZ&S
zaaPpdW~1{|!6w5{UpM#9+HjeftvxZAsqq?gW~JA#Wwv<@d*+~5gOdbvxWSyI(}>(-
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn02.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn02.vhd
new file mode 100644
index 00000000..85fd82b9
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn02.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity tn02 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of tn02 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"AF",X"BE",X"C2",X"0B",X"08",X"78",X"FE",X"3E",X"D2",X"69",X"08",X"78",X"FE",X"3C",X"DA",X"25",
+		X"08",X"2A",X"09",X"20",X"01",X"1E",X"02",X"CD",X"8C",X"08",X"21",X"05",X"20",X"36",X"00",X"21",
+		X"BF",X"20",X"36",X"00",X"C9",X"2A",X"07",X"20",X"EB",X"2A",X"09",X"20",X"01",X"1E",X"02",X"C3",
+		X"D5",X"01",X"36",X"FF",X"21",X"05",X"21",X"CD",X"A0",X"08",X"EB",X"2E",X"06",X"CD",X"52",X"1A",
+		X"E5",X"C1",X"0A",X"6F",X"03",X"0A",X"67",X"CD",X"D2",X"01",X"C3",X"25",X"08",X"36",X"FF",X"21",
+		X"09",X"21",X"CD",X"A0",X"08",X"EB",X"2E",X"0A",X"C3",X"3D",X"08",X"36",X"FF",X"21",X"0D",X"21",
+		X"CD",X"A0",X"08",X"EB",X"2E",X"0E",X"C3",X"3D",X"08",X"36",X"FF",X"21",X"11",X"21",X"CD",X"A0",
+		X"08",X"EB",X"2E",X"12",X"C3",X"3D",X"08",X"21",X"06",X"20",X"34",X"7E",X"E6",X"01",X"C2",X"85",
+		X"08",X"21",X"72",X"40",X"C9",X"21",X"36",X"40",X"C9",X"01",X"20",X"03",X"AF",X"C5",X"E5",X"77",
+		X"23",X"05",X"C2",X"8F",X"08",X"E1",X"01",X"20",X"00",X"09",X"C1",X"0D",X"C2",X"8D",X"08",X"C9",
+		X"7E",X"21",X"1D",X"41",X"3D",X"C8",X"11",X"60",X"00",X"19",X"C3",X"A4",X"08",X"AF",X"7C",X"1F",
+		X"57",X"7D",X"1F",X"E6",X"F0",X"0F",X"0F",X"0F",X"0F",X"5F",X"7A",X"E6",X"0F",X"07",X"07",X"07",
+		X"07",X"B3",X"C9",X"11",X"DD",X"43",X"06",X"02",X"C3",X"AD",X"0E",X"11",X"DD",X"43",X"06",X"02",
+		X"C3",X"9A",X"19",X"CD",X"38",X"14",X"CD",X"53",X"14",X"CD",X"40",X"10",X"CD",X"42",X"09",X"CD",
+		X"F8",X"08",X"CD",X"65",X"09",X"3A",X"E4",X"20",X"A7",X"CA",X"22",X"05",X"CD",X"89",X"1A",X"CD",
+		X"13",X"09",X"CD",X"35",X"1B",X"C3",X"22",X"05",X"21",X"1F",X"20",X"7E",X"A7",X"C8",X"46",X"36",
+		X"00",X"21",X"24",X"20",X"7E",X"0F",X"D0",X"36",X"00",X"2A",X"22",X"20",X"EB",X"21",X"38",X"20",
+		X"C3",X"0D",X"0A",X"CD",X"52",X"1A",X"2E",X"24",X"7E",X"FE",X"03",X"D8",X"21",X"BF",X"20",X"AF",
+		X"BE",X"C0",X"34",X"21",X"35",X"09",X"C3",X"7B",X"1A",X"00",X"00",X"07",X"07",X"01",X"00",X"01",
+		X"00",X"06",X"06",X"01",X"00",X"00",X"00",X"04",X"04",X"01",X"00",X"00",X"02",X"00",X"01",X"01",
+		X"01",X"00",X"3A",X"E4",X"20",X"A7",X"C8",X"21",X"38",X"20",X"7E",X"FE",X"FF",X"CA",X"60",X"09",
+		X"0F",X"D2",X"59",X"09",X"3E",X"10",X"C3",X"0E",X"02",X"23",X"23",X"23",X"23",X"C3",X"4A",X"09",
+		X"3E",X"10",X"C3",X"17",X"02",X"21",X"04",X"20",X"34",X"7E",X"E6",X"03",X"77",X"A7",X"CA",X"28",
+		X"19",X"FE",X"01",X"CA",X"38",X"19",X"FE",X"02",X"CA",X"66",X"19",X"FE",X"03",X"CA",X"85",X"19",
+		X"C9",X"21",X"38",X"20",X"CD",X"21",X"0A",X"21",X"3C",X"20",X"CD",X"21",X"0A",X"11",X"9D",X"20",
+		X"CD",X"DF",X"09",X"CD",X"07",X"13",X"CD",X"6A",X"0A",X"C3",X"D9",X"09",X"21",X"40",X"20",X"CD",
+		X"21",X"0A",X"21",X"44",X"20",X"CD",X"21",X"0A",X"11",X"9E",X"20",X"CD",X"DF",X"09",X"2E",X"0C",
+		X"CD",X"52",X"1A",X"CD",X"6A",X"0A",X"CD",X"D9",X"09",X"C3",X"15",X"15",X"21",X"48",X"20",X"CD",
+		X"21",X"0A",X"21",X"4C",X"20",X"CD",X"21",X"0A",X"11",X"9F",X"20",X"CD",X"DF",X"09",X"2E",X"14",
+		X"CD",X"52",X"1A",X"CD",X"6A",X"0A",X"C3",X"D9",X"09",X"21",X"9C",X"20",X"36",X"00",X"C9",X"21",
+		X"9B",X"20",X"7E",X"A7",X"CA",X"EB",X"09",X"23",X"36",X"00",X"C9",X"EB",X"34",X"7E",X"FE",X"02",
+		X"D2",X"F8",X"09",X"EB",X"23",X"36",X"FF",X"C9",X"36",X"00",X"EB",X"23",X"36",X"00",X"C9",X"57",
+		X"3A",X"9C",X"20",X"A7",X"7A",X"C2",X"0A",X"0A",X"37",X"C9",X"37",X"3F",X"C9",X"78",X"3D",X"CA",
+		X"19",X"0A",X"23",X"23",X"23",X"23",X"C3",X"0E",X"0A",X"36",X"01",X"23",X"23",X"73",X"23",X"72",
+		X"C9",X"7E",X"0F",X"D0",X"23",X"23",X"E5",X"CD",X"6C",X"11",X"CD",X"5B",X"0A",X"E1",X"E5",X"CD",
+		X"6C",X"11",X"7D",X"FE",X"18",X"DA",X"48",X"0A",X"01",X"F9",X"FF",X"09",X"EB",X"E1",X"73",X"23",
+		X"72",X"EB",X"11",X"DA",X"43",X"C3",X"CF",X"0E",X"E1",X"E5",X"CD",X"6C",X"11",X"22",X"B7",X"20",
+		X"E1",X"2B",X"AF",X"77",X"2B",X"77",X"21",X"B5",X"20",X"34",X"C9",X"11",X"DA",X"43",X"C3",X"AB",
+		X"0E",X"7C",X"B5",X"37",X"C8",X"7B",X"95",X"7A",X"9C",X"C9",X"E5",X"7E",X"47",X"07",X"D2",X"8A",
+		X"0A",X"23",X"23",X"CD",X"15",X"0B",X"78",X"0F",X"0F",X"7A",X"D2",X"DA",X"0A",X"FE",X"4B",X"DA",
+		X"A1",X"0A",X"36",X"25",X"E1",X"E5",X"3E",X"DF",X"A6",X"77",X"21",X"37",X"20",X"34",X"E1",X"23",
+		X"23",X"23",X"23",X"3A",X"37",X"20",X"FE",X"02",X"DA",X"6A",X"0A",X"21",X"37",X"20",X"36",X"00",
+		X"C9",X"FE",X"3C",X"D2",X"CC",X"0A",X"78",X"0F",X"E1",X"E5",X"23",X"7E",X"23",X"4E",X"23",X"46",
+		X"2B",X"2B",X"DA",X"2F",X"0B",X"CD",X"FF",X"09",X"D2",X"BF",X"0A",X"3D",X"CA",X"23",X"0B",X"77",
+		X"CD",X"A1",X"08",X"EB",X"60",X"69",X"CD",X"D2",X"01",X"C3",X"8A",X"0A",X"E1",X"E5",X"CD",X"03",
+		X"0B",X"E1",X"E5",X"7E",X"0F",X"0F",X"0F",X"C3",X"8A",X"0A",X"2B",X"2B",X"2B",X"FE",X"25",X"DA",
+		X"EE",X"0A",X"FE",X"3C",X"DA",X"FB",X"0A",X"7E",X"0F",X"0F",X"0F",X"C3",X"8A",X"0A",X"CD",X"08",
+		X"0B",X"E1",X"E5",X"23",X"23",X"23",X"36",X"48",X"C3",X"8A",X"0A",X"46",X"3E",X"DF",X"A6",X"77",
+		X"C3",X"A6",X"0A",X"7E",X"07",X"07",X"07",X"D8",X"3E",X"20",X"B6",X"77",X"23",X"23",X"5E",X"23",
+		X"56",X"EB",X"C3",X"89",X"08",X"E5",X"5E",X"23",X"56",X"2A",X"28",X"21",X"19",X"EB",X"E1",X"73",
+		X"23",X"72",X"C9",X"36",X"01",X"2B",X"3E",X"01",X"B6",X"77",X"3E",X"01",X"C3",X"C0",X"0A",X"CD",
+		X"FF",X"09",X"D2",X"BF",X"0A",X"3C",X"FE",X"08",X"DA",X"BF",X"0A",X"36",X"07",X"2B",X"3E",X"FE",
+		X"A6",X"77",X"3E",X"07",X"C3",X"C0",X"0A",X"CD",X"56",X"0B",X"CD",X"AB",X"0B",X"CD",X"D6",X"0B",
+		X"CD",X"40",X"15",X"C3",X"27",X"16",X"AF",X"21",X"B5",X"20",X"BE",X"C8",X"23",X"34",X"7E",X"FE",
+		X"01",X"CA",X"01",X"0C",X"FE",X"04",X"CA",X"07",X"0C",X"FE",X"07",X"D8",X"11",X"3C",X"44",X"CD",
+		X"0A",X"0C",X"CD",X"E0",X"15",X"21",X"B8",X"20",X"D2",X"81",X"0B",X"CD",X"9B",X"0B",X"C3",X"84",
+		X"0B",X"CD",X"8B",X"0B",X"21",X"00",X"00",X"22",X"B5",X"20",X"C9",X"AF",X"3A",X"34",X"20",X"BE",
+		X"D8",X"7E",X"21",X"7D",X"20",X"BE",X"D8",X"77",X"C3",X"0D",X"16",X"AF",X"3A",X"34",X"20",X"BE",
+		X"D0",X"7E",X"21",X"7F",X"20",X"BE",X"D0",X"77",X"C3",X"ED",X"15",X"AF",X"21",X"1D",X"20",X"BE",
+		X"C8",X"23",X"34",X"7E",X"FE",X"01",X"CA",X"16",X"0C",X"FE",X"04",X"CA",X"1C",X"0C",X"FE",X"07",
+		X"D8",X"2A",X"22",X"20",X"CD",X"76",X"03",X"01",X"10",X"02",X"CD",X"8C",X"08",X"21",X"00",X"00",
+		X"22",X"1D",X"20",X"C3",X"7D",X"15",X"AF",X"21",X"27",X"20",X"BE",X"C8",X"23",X"34",X"7E",X"FE",
+		X"01",X"CA",X"2B",X"0C",X"FE",X"04",X"CA",X"47",X"0C",X"FE",X"07",X"D8",X"2A",X"2D",X"20",X"01",
+		X"10",X"02",X"CD",X"8C",X"08",X"21",X"00",X"00",X"22",X"27",X"20",X"CD",X"6F",X"1A",X"C3",X"7D",
+		X"15",X"11",X"0C",X"44",X"C3",X"0A",X"0C",X"11",X"24",X"44",X"2A",X"B7",X"20",X"CD",X"76",X"03",
+		X"01",X"0C",X"02",X"C3",X"D5",X"01",X"11",X"54",X"44",X"C3",X"1F",X"0C",X"11",X"74",X"44",X"2A",
+		X"22",X"20",X"CD",X"76",X"03",X"01",X"10",X"02",X"C3",X"D5",X"01",X"2A",X"29",X"20",X"11",X"DA",
+		X"43",X"CD",X"AD",X"0E",X"2A",X"29",X"20",X"CD",X"76",X"03",X"22",X"2D",X"20",X"11",X"94",X"44",
+		X"01",X"10",X"02",X"CD",X"D5",X"01",X"C9",X"2A",X"2D",X"20",X"11",X"B4",X"44",X"C3",X"40",X"0C",
+		X"3A",X"E4",X"20",X"A7",X"C8",X"3A",X"DB",X"20",X"0F",X"DB",X"01",X"D0",X"DB",X"02",X"C9",X"21",
+		X"2F",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"C2",X"6E",X"0C",X"34",X"CD",X"E4",X"0C",X"3A",X"E4",
+		X"20",X"A7",X"C2",X"9D",X"0C",X"2A",X"E2",X"20",X"3A",X"E1",X"20",X"3C",X"32",X"E1",X"20",X"E6",
+		X"0F",X"C2",X"8B",X"0C",X"7D",X"FE",X"13",X"CC",X"9A",X"0C",X"23",X"22",X"E2",X"20",X"7E",X"0F",
+		X"DA",X"06",X"0D",X"0F",X"DA",X"23",X"0D",X"C3",X"A9",X"0C",X"2E",X"00",X"C9",X"CD",X"50",X"0C",
+		X"07",X"07",X"DA",X"06",X"0D",X"07",X"DA",X"23",X"0D",X"06",X"00",X"21",X"32",X"20",X"70",X"CD",
+		X"E4",X"0C",X"21",X"31",X"20",X"CD",X"A1",X"0D",X"2A",X"33",X"20",X"11",X"BE",X"43",X"01",X"02",
+		X"0E",X"CD",X"71",X"03",X"C5",X"E5",X"1A",X"A6",X"CA",X"D0",X"0C",X"3E",X"01",X"32",X"35",X"20",
+		X"1A",X"AE",X"77",X"23",X"13",X"0D",X"C2",X"C6",X"0C",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",
+		X"C2",X"C4",X"0C",X"C9",X"2A",X"33",X"20",X"11",X"BE",X"43",X"01",X"02",X"0E",X"CD",X"71",X"03",
+		X"C5",X"E5",X"1A",X"AE",X"77",X"23",X"13",X"0D",X"C2",X"F2",X"0C",X"E1",X"01",X"20",X"00",X"09",
+		X"C1",X"05",X"C2",X"F0",X"0C",X"C9",X"3A",X"34",X"20",X"FE",X"DA",X"D2",X"A9",X"0C",X"2A",X"33",
+		X"20",X"01",X"F8",X"0F",X"09",X"CD",X"76",X"03",X"7E",X"FE",X"7F",X"C2",X"A9",X"0C",X"06",X"02",
+		X"C3",X"AB",X"0C",X"3A",X"34",X"20",X"FE",X"38",X"DA",X"A9",X"0C",X"2A",X"33",X"20",X"01",X"F8",
+		X"FC",X"09",X"CD",X"76",X"03",X"7E",X"FE",X"7F",X"C2",X"A9",X"0C",X"06",X"FE",X"C3",X"AB",X"0C",
+		X"23",X"23",X"5E",X"23",X"7E",X"C6",X"02",X"57",X"EB",X"CD",X"AD",X"08",X"57",X"7D",X"E6",X"1F",
+		X"07",X"07",X"07",X"5F",X"EB",X"C9",X"21",X"54",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"C2",X"73",
+		X"0D",X"34",X"23",X"BE",X"21",X"00",X"FD",X"22",X"58",X"20",X"21",X"C8",X"D0",X"C4",X"1A",X"0E",
+		X"22",X"5A",X"20",X"3A",X"56",X"20",X"A7",X"21",X"5B",X"20",X"7E",X"C2",X"AD",X"0D",X"FE",X"28",
+		X"DA",X"C9",X"0D",X"21",X"57",X"20",X"34",X"E6",X"01",X"21",X"AE",X"40",X"CC",X"C1",X"0D",X"22",
+		X"5C",X"20",X"21",X"5A",X"20",X"CD",X"F0",X"0D",X"CD",X"02",X"0E",X"CD",X"24",X"0E",X"21",X"58",
+		X"20",X"4E",X"23",X"46",X"23",X"79",X"86",X"77",X"23",X"78",X"86",X"77",X"C9",X"FE",X"D0",X"D2",
+		X"C9",X"0D",X"21",X"57",X"20",X"34",X"E6",X"01",X"21",X"36",X"40",X"CC",X"C5",X"0D",X"C3",X"8F",
+		X"0D",X"21",X"E5",X"40",X"C9",X"21",X"72",X"40",X"C9",X"2A",X"5A",X"20",X"01",X"1B",X"02",X"CD",
+		X"76",X"03",X"CD",X"8C",X"08",X"06",X"0C",X"21",X"54",X"46",X"11",X"54",X"20",X"CD",X"8B",X"03",
+		X"21",X"13",X"20",X"34",X"7E",X"E6",X"01",X"21",X"56",X"20",X"36",X"01",X"C0",X"36",X"00",X"C9",
+		X"E5",X"23",X"23",X"5E",X"23",X"56",X"23",X"4E",X"23",X"46",X"E1",X"D5",X"5E",X"23",X"56",X"EB",
+		X"D1",X"C9",X"CD",X"76",X"03",X"C5",X"E5",X"1A",X"77",X"23",X"13",X"0D",X"C2",X"07",X"0E",X"E1",
+		X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"05",X"0E",X"C9",X"21",X"00",X"03",X"22",X"58",X"20",
+		X"21",X"C8",X"28",X"C9",X"3A",X"56",X"20",X"A7",X"C2",X"A1",X"0E",X"CD",X"35",X"0E",X"D6",X"0A",
+		X"B8",X"DA",X"3D",X"0E",X"C9",X"2A",X"34",X"20",X"44",X"3A",X"0A",X"20",X"C9",X"21",X"B0",X"20",
+		X"AF",X"BE",X"CA",X"47",X"0E",X"35",X"C9",X"E5",X"CD",X"4B",X"1A",X"23",X"7E",X"FE",X"04",X"06",
+		X"50",X"D2",X"56",X"0E",X"06",X"60",X"E1",X"70",X"FE",X"0B",X"D2",X"7A",X"0E",X"FE",X"09",X"CD",
+		X"52",X"1A",X"2E",X"24",X"7E",X"FE",X"04",X"D2",X"8F",X"0E",X"21",X"60",X"20",X"34",X"2E",X"67",
+		X"34",X"2E",X"6E",X"34",X"21",X"95",X"20",X"36",X"00",X"C9",X"21",X"FB",X"03",X"22",X"63",X"20",
+		X"21",X"FA",X"02",X"22",X"6A",X"20",X"21",X"FB",X"FA",X"22",X"71",X"20",X"C3",X"6A",X"0E",X"21",
+		X"FC",X"02",X"22",X"63",X"20",X"21",X"FB",X"01",X"22",X"6A",X"20",X"21",X"FB",X"FD",X"C3",X"89",
+		X"0E",X"CD",X"35",X"0E",X"C6",X"08",X"B8",X"D2",X"3D",X"0E",X"C9",X"06",X"03",X"CD",X"71",X"03",
+		X"C5",X"E5",X"1A",X"D3",X"04",X"DB",X"03",X"2F",X"A6",X"77",X"23",X"13",X"AF",X"D3",X"04",X"DB",
+		X"03",X"2F",X"A6",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"B0",X"0E",X"C9",X"06",
+		X"03",X"CD",X"71",X"03",X"C5",X"E5",X"1A",X"D3",X"04",X"DB",X"03",X"AE",X"77",X"23",X"13",X"AF",
+		X"D3",X"04",X"DB",X"03",X"AE",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"D4",X"0E",
+		X"C9",X"21",X"60",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"C2",X"FE",X"0E",X"35",X"C9",X"23",X"BE",
+		X"C2",X"0A",X"0F",X"34",X"CD",X"33",X"0F",X"22",X"65",X"20",X"CD",X"3B",X"0F",X"21",X"66",X"20",
+		X"7E",X"FE",X"30",X"DC",X"46",X"0F",X"FE",X"E8",X"D4",X"53",X"0F",X"2B",X"7E",X"FE",X"18",X"DA",
+		X"5E",X"0F",X"21",X"63",X"20",X"CD",X"A1",X"0D",X"2A",X"65",X"20",X"11",X"DA",X"0F",X"06",X"08",
+		X"C3",X"D1",X"0E",X"2A",X"5A",X"20",X"01",X"00",X"08",X"09",X"C9",X"2A",X"65",X"20",X"11",X"DA",
+		X"0F",X"06",X"08",X"C3",X"AD",X"0E",X"F5",X"E5",X"2A",X"65",X"20",X"CD",X"3E",X"0F",X"E1",X"36",
+		X"E0",X"F1",X"C9",X"E5",X"2A",X"65",X"20",X"CD",X"3E",X"0F",X"E1",X"36",X"34",X"C9",X"CD",X"3B",
+		X"0F",X"21",X"60",X"46",X"11",X"60",X"20",X"06",X"07",X"C3",X"8B",X"03",X"21",X"67",X"20",X"AF",
+		X"BE",X"C8",X"23",X"BE",X"CA",X"79",X"0F",X"35",X"C9",X"23",X"BE",X"C2",X"85",X"0F",X"34",X"CD",
+		X"33",X"0F",X"22",X"6C",X"20",X"2A",X"6C",X"20",X"CD",X"3E",X"0F",X"21",X"6D",X"20",X"7E",X"FE",
+		X"30",X"DC",X"BC",X"0F",X"FE",X"E8",X"D4",X"C4",X"0F",X"2B",X"7E",X"47",X"CD",X"52",X"1A",X"2E",
+		X"24",X"7E",X"FE",X"05",X"0E",X"13",X"D2",X"AB",X"0F",X"0E",X"18",X"78",X"B9",X"DA",X"CB",X"0F",
+		X"21",X"6A",X"20",X"CD",X"A1",X"0D",X"2A",X"6C",X"20",X"C3",X"2B",X"0F",X"F5",X"E5",X"2A",X"6C",
+		X"20",X"C3",X"57",X"0F",X"E5",X"2A",X"6C",X"20",X"C3",X"4B",X"0F",X"2A",X"6C",X"20",X"CD",X"3E",
+		X"0F",X"21",X"67",X"46",X"11",X"67",X"20",X"C3",X"67",X"0F",X"60",X"F0",X"F0",X"F0",X"F0",X"60",
+		X"90",X"90",X"21",X"6E",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"CA",X"EF",X"0F",X"35",X"C9",X"23",
+		X"BE",X"C2",X"FB",X"0F",X"34",X"CD",X"33",X"0F",X"22",X"73",X"20",X"2A",X"73",X"20",X"CD",X"3E");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn03 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn03
new file mode 100644
index 0000000000000000000000000000000000000000..e0ab28e6a5cb5e8be440d36bb172a55933488eca
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn03.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn03.vhd
new file mode 100644
index 00000000..d35cb0d4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn03.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity tn03 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of tn03 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"0F",X"21",X"74",X"20",X"7E",X"FE",X"30",X"DC",X"22",X"10",X"FE",X"E8",X"D4",X"2A",X"10",X"2B",
+		X"7E",X"FE",X"18",X"DA",X"31",X"10",X"21",X"71",X"20",X"CD",X"A1",X"0D",X"2A",X"73",X"20",X"C3",
+		X"2B",X"0F",X"F5",X"E5",X"2A",X"73",X"20",X"C3",X"4B",X"0F",X"E5",X"2A",X"73",X"20",X"C3",X"57",
+		X"0F",X"2A",X"73",X"20",X"CD",X"3E",X"0F",X"21",X"6E",X"46",X"11",X"6E",X"20",X"C3",X"67",X"0F",
+		X"21",X"11",X"20",X"AF",X"BE",X"C8",X"36",X"00",X"21",X"14",X"20",X"34",X"21",X"00",X"00",X"22",
+		X"16",X"20",X"2A",X"1A",X"20",X"CD",X"C3",X"08",X"21",X"60",X"20",X"AF",X"BE",X"CA",X"B0",X"10",
+		X"21",X"65",X"20",X"CD",X"8F",X"10",X"D4",X"6C",X"10",X"C3",X"B0",X"10",X"CD",X"96",X"10",X"DA",
+		X"73",X"10",X"C9",X"CD",X"9D",X"10",X"D2",X"7A",X"10",X"C9",X"CD",X"A9",X"10",X"DA",X"81",X"10",
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+		X"D3",X"02",X"CD",X"76",X"03",X"C5",X"E5",X"1A",X"D3",X"04",X"DB",X"03",X"B6",X"77",X"23",X"13",
+		X"AF",X"D3",X"04",X"DB",X"03",X"B6",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"65",
+		X"17",X"C9",X"2A",X"A8",X"20",X"EB",X"1A",X"2A",X"AF",X"20",X"2D",X"CA",X"BA",X"17",X"22",X"AF",
+		X"20",X"32",X"AE",X"20",X"13",X"1A",X"E6",X"0F",X"07",X"01",X"BF",X"17",X"26",X"00",X"6F",X"09",
+		X"E5",X"C1",X"21",X"A0",X"20",X"0A",X"77",X"03",X"23",X"0A",X"77",X"13",X"1A",X"6F",X"13",X"1A",
+		X"67",X"22",X"A2",X"20",X"EB",X"23",X"22",X"A8",X"20",X"C9",X"AF",X"32",X"AA",X"20",X"C9",X"00",
+		X"02",X"02",X"02",X"02",X"00",X"02",X"FE",X"00",X"FE",X"FE",X"FE",X"FE",X"00",X"FE",X"02",X"01",
+		X"02",X"02",X"01",X"02",X"FF",X"01",X"FE",X"FF",X"FE",X"FE",X"FF",X"FE",X"01",X"FF",X"02",X"FF",
+		X"FF",X"24",X"06",X"D7",X"30",X"10",X"00",X"D7",X"30",X"04",X"07",X"D7",X"50",X"0A",X"06",X"CF",
+		X"58",X"04",X"05",X"BC",X"58",X"04",X"07",X"B4",X"50",X"0A",X"06",X"AC",X"58",X"04",X"05",X"98");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn04 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn04
new file mode 100644
index 0000000000000000000000000000000000000000..2097c45c4a73bfbba52d9c0bcf036a18403f133a
GIT binary patch
literal 2048
zcmeHF!E4iC6#tSYX|i?gI=8h=ndDp9$|iJJw_39`4B41Pa6?2?6g}xh5HEHzjPtS`
z99RdUhv~sXyMx*x9(EX|O{_MB4?5?hSYcG0AQN<g2N`U>Y!m$xJoLfi_j|wh<$W)|
z<WxP1@3(QqFpqYUu@;Z8Tz-UM)5mx;AGUFG(3=Z0);Z8;L4O4LgRo7ApSIZ(mw;cW
z<r1ScC_V}p2aMae#B2>p%mOadqPU3}s55|Xp*FE(vqEx-?+9YrO)(Xh$&d@}h1h}!
zA@aekFl2-3JRp&47CXC|a~3_z9GzRG8fdaiDJ)rTtYlg3g?lkusnedgO?`?dS)?#J
zL*p(fgaVBrWXLWlsnFU61*+TvoYKF#Wj_$!BzJd-vO*YIS<zjz{7FjY<rC&f%}#?r
z?s-b&yp0Ui5|>AxZX%j>Te>BXbvrrg(H}RGGalS6sezm6(knh@Z1WrG;yd8vy64Y;
z8G)3W^~(;Kh2hLU!xsed(Lqku=`+ppnB*|XRZDJFTw=<WMB%ANp@L4SY<U**?Mdxu
z*}qzal8^vCJoFd{S;57_kWI8RdIx=DyZA-iBALz#PAhbW5TbE^w4Oz1oZ^LkE3zO8
zMd|1O8W(8PKgrXel<ChF?8iSRV(S5ad+P+e!+@wp^23;FbGG;AsCo*%K(<cn77cP-
z4EWV;Xj2WjEIHnv72C1V-fAc#K~2)9XjngMBBn-KcSwie3}KGbZ(DGeppS{TK}w~S
z`T|4u=o=LNBAIiFK7-sBQ|UZhfnQ2*o{NFkD%Uh$f@Qi%rwGjuf+s^G#^zR`&AYi-
z5WTn;hsJ#|-x@yWogC(np!zOe(SM0@FHYuh1ovdtIu)!Y&GTD@MsI^p<@hDa%4)pV
z*Q#Jc?!!NpL|8e3mGNLNHk7U110CL!S>r=kjl?qhRJcV=YEiGgCdwg93^5gyv5^WM
b#C;~=2WJLf4Vpi5HL4C&9jH3+-#PFbu86>U

literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn04.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn04.vhd
new file mode 100644
index 00000000..de61c21a
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn04.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity tn04 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of tn04 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"58",X"10",X"00",X"90",X"31",X"0C",X"06",X"D0",X"38",X"08",X"00",X"D0",X"38",X"08",X"00",X"D0",
+		X"38",X"04",X"07",X"D0",X"48",X"05",X"06",X"C8",X"50",X"04",X"05",X"BE",X"4E",X"08",X"00",X"B8",
+		X"38",X"0C",X"06",X"B0",X"38",X"08",X"00",X"B0",X"38",X"04",X"07",X"B0",X"48",X"05",X"06",X"A8",
+		X"50",X"04",X"05",X"9E",X"4E",X"08",X"00",X"98",X"38",X"0C",X"09",X"90",X"59",X"0C",X"0E",X"A6",
+		X"67",X"08",X"00",X"98",X"60",X"0B",X"06",X"A6",X"78",X"0A",X"00",X"90",X"78",X"0B",X"06",X"A6",
+		X"90",X"0A",X"00",X"90",X"90",X"0C",X"06",X"A6",X"A8",X"0A",X"00",X"A6",X"A8",X"0C",X"06",X"A6",
+		X"BC",X"0B",X"00",X"90",X"A8",X"0C",X"06",X"A6",X"C0",X"0A",X"00",X"A6",X"C0",X"0C",X"06",X"A6",
+		X"D4",X"0B",X"00",X"90",X"C0",X"0C",X"06",X"A6",X"D8",X"0C",X"07",X"A6",X"D8",X"0C",X"06",X"A6",
+		X"F0",X"00",X"00",X"00",X"00",X"92",X"18",X"01",X"04",X"E1",X"17",X"00",X"00",X"00",X"00",X"00",
+		X"17",X"00",X"1E",X"1E",X"1E",X"1E",X"FF",X"FF",X"FF",X"FF",X"36",X"00",X"CD",X"DC",X"18",X"3E",
+		X"04",X"CD",X"FB",X"01",X"2A",X"33",X"20",X"CD",X"76",X"03",X"0E",X"05",X"E5",X"C5",X"11",X"D0",
+		X"19",X"D5",X"06",X"02",X"C5",X"E5",X"01",X"12",X"02",X"CD",X"D5",X"01",X"3E",X"05",X"CD",X"D5",
+		X"14",X"E1",X"C1",X"05",X"C2",X"B4",X"18",X"D1",X"C1",X"E1",X"0D",X"C2",X"AC",X"18",X"01",X"12",
+		X"02",X"CD",X"8C",X"08",X"CD",X"C1",X"00",X"3E",X"04",X"C3",X"04",X"02",X"21",X"2F",X"20",X"36",
+		X"00",X"2E",X"14",X"36",X"00",X"C9",X"3A",X"17",X"20",X"A7",X"3E",X"02",X"C2",X"FB",X"01",X"C3",
+		X"04",X"02",X"3A",X"1D",X"20",X"A7",X"3E",X"01",X"C3",X"EC",X"18",X"3A",X"27",X"20",X"A7",X"3E",
+		X"08",X"C3",X"EC",X"18",X"3A",X"91",X"20",X"A7",X"3E",X"08",X"C3",X"EC",X"18",X"3E",X"DF",X"CD",
+		X"04",X"02",X"3E",X"DF",X"C3",X"17",X"02",X"3A",X"E4",X"20",X"A7",X"C8",X"3A",X"54",X"20",X"A7",
+		X"3E",X"01",X"C2",X"0E",X"02",X"C3",X"17",X"02",X"CD",X"95",X"19",X"D8",X"CD",X"5F",X"0C",X"CD",
+		X"47",X"0B",X"CD",X"17",X"19",X"C3",X"92",X"15",X"CD",X"C2",X"07",X"CD",X"95",X"19",X"D8",X"CD",
+		X"81",X"09",X"CD",X"F1",X"0E",X"CD",X"4B",X"19",X"C3",X"A2",X"14",X"CD",X"5A",X"19",X"21",X"34",
+		X"20",X"7E",X"2E",X"7F",X"BE",X"D8",X"C6",X"08",X"77",X"C9",X"21",X"34",X"20",X"7E",X"2E",X"7D",
+		X"BE",X"D0",X"D6",X"08",X"77",X"C9",X"CD",X"79",X"19",X"CD",X"95",X"19",X"D8",X"CD",X"5F",X"0C",
+		X"CD",X"9C",X"09",X"CD",X"DB",X"16",X"C3",X"6C",X"0F",X"3A",X"05",X"20",X"A7",X"3E",X"04",X"C2",
+		X"0E",X"02",X"C3",X"17",X"02",X"CD",X"95",X"19",X"D8",X"CD",X"BC",X"09",X"CD",X"E2",X"0F",X"CD",
+		X"56",X"0D",X"C3",X"9C",X"16",X"3A",X"7B",X"20",X"0F",X"C9",X"CD",X"71",X"03",X"C5",X"E5",X"1A",
+		X"D3",X"04",X"DB",X"03",X"A6",X"CA",X"AD",X"19",X"3E",X"01",X"32",X"11",X"20",X"DB",X"03",X"AE",
+		X"77",X"23",X"13",X"AF",X"D3",X"04",X"DB",X"03",X"A6",X"CA",X"C1",X"19",X"3E",X"01",X"32",X"11",
+		X"20",X"DB",X"03",X"AE",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"9D",X"19",X"C9",
+		X"00",X"00",X"07",X"00",X"00",X"00",X"42",X"00",X"00",X"00",X"15",X"02",X"11",X"49",X"8F",X"00",
+		X"EF",X"05",X"2F",X"08",X"D1",X"21",X"1D",X"20",X"00",X"00",X"17",X"00",X"09",X"11",X"07",X"00",
+		X"07",X"00",X"47",X"00",X"00",X"02",X"21",X"40",X"49",X"10",X"05",X"00",X"00",X"80",X"01",X"08",
+		X"09",X"40",X"07",X"00",X"03",X"00",X"01",X"00",X"49",X"02",X"49",X"44",X"00",X"80",X"09",X"02",
+		X"00",X"40",X"87",X"08",X"02",X"00",X"03",X"00",X"DB",X"02",X"E6",X"03",X"21",X"27",X"21",X"F5",
+		X"86",X"77",X"F1",X"2E",X"27",X"26",X"22",X"86",X"77",X"C9",X"CD",X"44",X"1A",X"7E",X"3D",X"C8",
+		X"4F",X"21",X"01",X"25",X"11",X"26",X"40",X"C5",X"01",X"10",X"01",X"CD",X"D5",X"01",X"C1",X"0D",
+		X"C2",X"34",X"1A",X"C9",X"CD",X"52",X"1A",X"2E",X"27",X"7E",X"C9",X"CD",X"52",X"1A",X"2E",X"25",
+		X"7E",X"C9",X"3A",X"DB",X"20",X"0F",X"DA",X"5C",X"1A",X"26",X"21",X"C9",X"26",X"22",X"C9",X"3E",
+		X"50",X"32",X"C2",X"20",X"C3",X"8C",X"02",X"3E",X"01",X"32",X"C1",X"20",X"C3",X"8C",X"02",X"21",
+		X"01",X"50",X"22",X"C1",X"20",X"C3",X"8C",X"02",X"21",X"29",X"09",X"11",X"36",X"21",X"06",X"06",
+		X"C3",X"8B",X"03",X"21",X"2F",X"09",X"C3",X"7B",X"1A",X"21",X"12",X"20",X"AF",X"BE",X"3E",X"10",
+		X"CA",X"04",X"02",X"35",X"C3",X"FB",X"01",X"21",X"E9",X"20",X"3A",X"DB",X"20",X"0F",X"D0",X"23",
+		X"C9",X"CD",X"97",X"1A",X"AF",X"BE",X"C8",X"CD",X"52",X"1A",X"21",X"C4",X"20",X"D2",X"B2",X"1A",
+		X"2E",X"C7",X"7E",X"06",X"15",X"B8",X"D8",X"CD",X"44",X"1A",X"34",X"CD",X"2A",X"1A",X"CD",X"97",
+		X"1A",X"36",X"00",X"21",X"12",X"20",X"36",X"50",X"C9",X"FE",X"FF",X"CA",X"25",X"1B",X"FE",X"FE",
+		X"CA",X"1A",X"1B",X"21",X"3B",X"21",X"36",X"80",X"23",X"77",X"23",X"EB",X"21",X"5D",X"1B",X"87",
+		X"4F",X"06",X"00",X"09",X"7E",X"23",X"66",X"6F",X"C3",X"F9",X"1A",X"3A",X"3B",X"21",X"A7",X"C8",
+		X"21",X"3D",X"21",X"35",X"C0",X"EB",X"2A",X"3E",X"21",X"7E",X"A7",X"CA",X"25",X"1B",X"FE",X"FF",
+		X"CA",X"14",X"1B",X"12",X"23",X"7E",X"06",X"08",X"D3",X"01",X"07",X"05",X"C2",X"08",X"1B",X"23",
+		X"22",X"3E",X"21",X"C9",X"3A",X"3C",X"21",X"F2",X"D3",X"1A",X"3E",X"01",X"32",X"3D",X"21",X"3E",
+		X"80",X"32",X"3B",X"21",X"C9",X"3E",X"FF",X"06",X"08",X"D3",X"01",X"07",X"05",X"C2",X"29",X"1B",
+		X"AF",X"32",X"3B",X"21",X"C9",X"21",X"39",X"21",X"7E",X"3D",X"77",X"C0",X"2B",X"7E",X"23",X"77",
+		X"23",X"7E",X"A7",X"C2",X"49",X"1B",X"C3",X"EB",X"1A",X"3A",X"36",X"21",X"CD",X"C9",X"1A",X"AF",
+		X"32",X"3A",X"21",X"C9",X"AF",X"32",X"37",X"21",X"3C",X"32",X"3A",X"21",X"C9",X"08",X"45",X"9C",
+		X"45",X"C6",X"45",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
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+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
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+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
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+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn05-1 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn05-1
new file mode 100644
index 0000000000000000000000000000000000000000..a52cdde55931b1d23ed2b5c06b7b38b64e5bd67d
GIT binary patch
literal 2048
zcmds2y=xpt6#vb~?Jl{?efTWAWbalhTaj@g`+{Ap!FZPh2a_s=Ni9f`l<s_mVAn|_
zunPYH!B*kca4y}L(H$`gs1Rx#fpl2~5mG9y1R;#y?A~1vD1wWP3%@tB@6Ej5y!U4I
z?JQ#e=M0P!0gQ&Qs#P%~8?NV-oR4MGDK`Pz=B)?!9<;b^6JkUm4sjP9xH-3A_$FQ;
z!%v3Oo_eZw@rc-mL^xiS%c<6;ViHl3FY>5%)zh?B#G!aEC~gtI$fZMh9Zn+B^8d4J
zobM87kEsWxp}vDE1J1bBebgg7OpxhOGa!vL0U}VUQxQW-%?9Or2y_{`+z(|Gt|Zuc
z7yie|#6ZlU7!>>%(c%51`%-s*)nTT?x5<C(zmW65HTc&M-AI!gO1nxQY28wqbeahf
z)u%n5<Noszop5AMJ5M{v^gQk2rS9ENmJns|GazH8(PmRq+tbo9|D#vDrQ?+(mQl?8
zBXSP&zUZx?XwyYF$$zFzMNwT*b>)?omH?_c3yR9>Z<yjJXa=*y7G7gf4U=KAs9w{^
z%*|jJ4VRaf&+uwPw&py~c3QdadBxOuKy*Z>z0khYzEZl-UH}qV6F<f*Y*gqzU}Dw&
zq!!nL#}!TfYQaU?UsDS6WOgu%gg8PC3}VDKjUt-Oi4OaTM1A8<=4E1)1!qv{GzwEi
z*?-j<-{6Ni=hjD9`?mLa%p|IJzv_z5%8G8GoKmbcH)O`Xw%2?`(<}9n0feYOY=yVy
z<Z9r?jx&#-b@ul6!Fh(V^94{V!<7xs_hvl{73o#!G8?eI9F+RjfcJ$aTIZ^?ZYj1d
zlr&?$$25DzH}mH)ool|&wMG3uG26yQnCGWp$e#N-Ao&N^?11gFJ+{MNQN-;$?k{|^
zu!&7eYuc<VtUGL*X}Lpa&3>c4PyKi52aG(~Ig%Op`yw|zC6YPI!o0CXe-@AQf6Q1G
z!YM?7pj-9Nk#?$h_GO*#pUWYaAjJ4zaKf7Qr|qzP*%*Fan0)Q=3Bbve$#=lqi+$-X
b4odFTzU5vYa5w4;_tw9Afe0omJ}l)8E8A7m

literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn05-1.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn05-1.vhd
new file mode 100644
index 00000000..0efc0ad1
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn05-1.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity tn05_1 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of tn05_1 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"01",X"01",X"00",X"00",X"02",X"02",X"01",X"00",X"01",X"02",X"02",X"02",X"02",X"00",X"00",X"01",
+		X"01",X"00",X"00",X"00",X"06",X"0E",X"0E",X"03",X"15",X"04",X"11",X"18",X"1B",X"1B",X"05",X"08",
+		X"0D",X"04",X"13",X"08",X"0B",X"13",X"00",X"00",X"07",X"07",X"02",X"1C",X"8B",X"77",X"8B",X"1C",
+		X"02",X"07",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",X"00",X"F0",
+		X"00",X"70",X"00",X"30",X"00",X"18",X"00",X"18",X"00",X"18",X"00",X"1C",X"00",X"1C",X"00",X"1C",
+		X"00",X"3E",X"00",X"BE",X"00",X"E0",X"00",X"9C",X"00",X"9C",X"00",X"9C",X"80",X"B0",X"C0",X"AD",
+		X"C0",X"DC",X"00",X"9E",X"00",X"9E",X"00",X"1E",X"00",X"04",X"00",X"38",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",X"00",X"F0",X"00",X"70",X"00",X"30",
+		X"00",X"18",X"00",X"18",X"00",X"18",X"00",X"1C",X"00",X"1C",X"00",X"1C",X"00",X"3E",X"00",X"BE",
+		X"00",X"E0",X"00",X"9C",X"00",X"9C",X"00",X"9C",X"80",X"B0",X"C0",X"AD",X"C0",X"DC",X"00",X"9E",
+		X"00",X"9E",X"00",X"1E",X"00",X"04",X"80",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",
+		X"00",X"04",X"00",X"1E",X"00",X"9E",X"00",X"9E",X"C0",X"DC",X"C0",X"AD",X"80",X"B0",X"00",X"9C",
+		X"00",X"9C",X"00",X"9C",X"00",X"E0",X"00",X"BE",X"00",X"3E",X"00",X"1C",X"00",X"1C",X"00",X"1C",
+		X"00",X"18",X"00",X"18",X"00",X"18",X"00",X"30",X"00",X"70",X"00",X"F0",X"00",X"38",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"80",X"03",X"00",X"04",X"00",X"1E",X"00",X"9E",X"00",X"9E",X"C0",
+		X"DC",X"C0",X"AD",X"80",X"B0",X"00",X"9C",X"00",X"9C",X"00",X"9C",X"00",X"E0",X"00",X"BE",X"00",
+		X"3E",X"00",X"1C",X"00",X"1C",X"00",X"1C",X"00",X"18",X"00",X"18",X"00",X"18",X"00",X"30",X"00",
+		X"70",X"00",X"F0",X"00",X"38",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"60",X"00",X"00",X"30",X"00",X"80",X"1B",X"00",X"C0",X"FF",X"00",X"C0",
+		X"67",X"00",X"C0",X"0B",X"00",X"00",X"08",X"00",X"00",X"08",X"00",X"00",X"08",X"00",X"00",X"10",
+		X"1E",X"00",X"10",X"3F",X"00",X"90",X"7F",X"00",X"E0",X"FF",X"00",X"E0",X"FF",X"00",X"E0",X"FF",
+		X"00",X"C0",X"FF",X"00",X"C0",X"FF",X"00",X"80",X"7F",X"00",X"00",X"3F",X"00",X"00",X"1E",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"80",
+		X"01",X"00",X"80",X"07",X"00",X"80",X"03",X"00",X"F0",X"00",X"00",X"78",X"01",X"00",X"78",X"02",
+		X"1E",X"38",X"04",X"3F",X"38",X"88",X"7F",X"00",X"D0",X"FF",X"00",X"E0",X"FF",X"00",X"E0",X"FF",
+		X"00",X"C0",X"FF",X"00",X"C0",X"FF",X"00",X"80",X"7F",X"00",X"00",X"3F",X"00",X"00",X"1E",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"40",X"02",X"00",X"C0",X"01",X"00",X"C0",X"00",
+		X"1E",X"40",X"00",X"3F",X"F0",X"81",X"7F",X"78",X"C6",X"FF",X"78",X"D8",X"FF",X"38",X"E0",X"FF",
+		X"38",X"C0",X"FF",X"00",X"C0",X"FF",X"00",X"80",X"7F",X"00",X"00",X"3F",X"00",X"00",X"1E",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"24",X"00",X"00",X"34",X"00",
+		X"1E",X"34",X"00",X"3F",X"3C",X"80",X"7F",X"3C",X"C0",X"FF",X"18",X"C0",X"FF",X"F8",X"FF",X"FF",
+		X"1C",X"C0",X"FF",X"3C",X"C0",X"FF",X"3C",X"80",X"7F",X"38",X"00",X"3F",X"10",X"00",X"1E",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"1E",X"00",X"00",X"3F",X"00",X"80",X"7F",X"00",X"C0",X"FF",X"00",X"C0",X"FF",X"20",X"E0",X"FF",
+		X"24",X"D8",X"FF",X"38",X"C6",X"FF",X"B0",X"81",X"7F",X"60",X"00",X"3F",X"E0",X"00",X"1E",X"E0",
+		X"00",X"00",X"E0",X"01",X"00",X"E0",X"01",X"00",X"C0",X"01",X"00",X"80",X"01",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"1E",X"00",X"00",X"3F",X"00",X"80",X"7F",X"00",X"C0",X"FF",X"00",X"C0",X"FF",X"00",X"E0",X"FF",
+		X"00",X"E0",X"FF",X"00",X"D0",X"FF",X"40",X"88",X"7F",X"40",X"04",X"3F",X"40",X"02",X"1E",X"F8",
+		X"01",X"00",X"E0",X"00",X"00",X"80",X"03",X"00",X"80",X"07",X"00",X"00",X"07",X"00",X"00",X"07",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"1E",X"00",X"00",X"3F",X"00",X"80",X"7F",X"00",X"C0",X"FF",X"00",X"C0",X"FF",X"00",X"E0",X"FF",
+		X"00",X"E0",X"FF",X"00",X"E0",X"FF",X"00",X"90",X"7F",X"00",X"10",X"3F",X"00",X"10",X"1E",X"00",
+		X"08",X"00",X"00",X"08",X"00",X"80",X"05",X"00",X"00",X"0B",X"00",X"00",X"06",X"00",X"C0",X"7F",
+		X"00",X"00",X"FB",X"00",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"15",X"00",
+		X"1F",X"00",X"1F",X"00",X"06",X"00",X"F2",X"00",X"2D",X"C0",X"DE",X"7F",X"DE",X"7F",X"2D",X"C0",
+		X"F2",X"00",X"06",X"00",X"1F",X"00",X"1F",X"00",X"15",X"00",X"DE",X"3F",X"DE",X"7C",X"7C",X"7C",
+		X"12",X"02",X"0E",X"11",X"04",X"1C",X"21",X"1B",X"1B",X"07",X"08",X"1C",X"12",X"02",X"0E",X"11",
+		X"04",X"1B",X"1B",X"12",X"02",X"0E",X"11",X"04",X"1C",X"22",X"00",X"00",X"03",X"30",X"03",X"30",
+		X"1D",X"26",X"1D",X"29",X"1D",X"2F",X"05",X"23",X"1D",X"26",X"00",X"00",X"7F",X"04",X"0F",X"03",
+		X"83",X"40",X"01",X"38",X"11",X"0C",X"01",X"00",X"01",X"01",X"03",X"8C",X"07",X"1A",X"0F",X"40",
+		X"0F",X"20",X"9F",X"0C",X"FF",X"00",X"1F",X"00",X"0F",X"20",X"27",X"00",X"07",X"00",X"13",X"04",
+		X"03",X"00",X"07",X"00",X"13",X"01",X"07",X"20",X"1F",X"00",X"7F",X"00",X"7F",X"00",X"3F",X"00",
+		X"0F",X"00",X"01",X"00",X"03",X"00",X"03",X"00",X"03",X"00",X"03",X"00",X"07",X"00",X"0F",X"00",
+		X"3F",X"00",X"7F",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"A4",X"04",X"00",X"10",
+		X"C8",X"54",X"E0",X"1B",X"E0",X"03",X"8C",X"01",X"20",X"12",X"00",X"0C",X"30",X"11",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"0C",X"C0",X"07",X"F1",X"0F",X"11",X"56",X"00",X"82",X"21",X"08",X"45",
+		X"0A",X"00",X"A0",X"63",X"B0",X"42",X"40",X"01",X"04",X"00",X"0E",X"70",X"4A",X"78",X"03",X"31",
+		X"0B",X"C0",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"A0",X"13",X"C8",X"04",
+		X"E0",X"01",X"50",X"07",X"A0",X"1E",X"C0",X"0B",X"C0",X"02",X"88",X"10",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"10",X"90",X"1C",X"38",X"48",X"21",X"04",X"8C",X"20",
+		X"18",X"40",X"08",X"08",X"24",X"00",X"20",X"1C",X"14",X"48",X"68",X"20",X"22",X"01",X"00",X"0B",
+		X"08",X"43",X"00",X"00",X"0F",X"0B",X"00",X"18",X"04",X"11",X"1B",X"1E",X"1B",X"1F",X"1B",X"06",
+		X"00",X"0C",X"04",X"1B",X"0E",X"15",X"04",X"11",X"C3",X"01",X"C2",X"04",X"C3",X"05",X"C2",X"06",
+		X"C3",X"02",X"C2",X"03",X"FF",X"FF",X"FF",X"FF",X"C1",X"02",X"C0",X"05",X"C1",X"06",X"C0",X"01",
+		X"C1",X"03",X"C0",X"04",X"FF",X"FF",X"FF",X"FF",X"02",X"DD",X"01",X"FF",X"01",X"D7",X"02",X"CC",
+		X"01",X"FF",X"01",X"D7",X"02",X"DD",X"01",X"FF",X"01",X"D7",X"02",X"CC",X"01",X"FF",X"01",X"D7",
+		X"02",X"DD",X"02",X"FF",X"02",X"E1",X"02",X"FF",X"06",X"E1",X"02",X"FF",X"02",X"DD",X"01",X"FF",
+		X"01",X"D7",X"02",X"CC",X"01",X"FF",X"01",X"D7",X"02",X"DD",X"01",X"FF",X"01",X"D7",X"02",X"CC",
+		X"01",X"FF",X"01",X"D7",X"02",X"D2",X"02",X"FF",X"02",X"DD",X"02",X"FF",X"06",X"B9",X"02",X"FF",
+		X"02",X"DD",X"01",X"FF",X"01",X"D7",X"02",X"CC",X"01",X"FF",X"01",X"D7",X"02",X"DD",X"01",X"FF",
+		X"01",X"D7",X"02",X"CC",X"01",X"FF",X"01",X"D7",X"02",X"DD",X"02",X"FF",X"02",X"E1",X"02",X"FF",
+		X"06",X"E4",X"02",X"FF",X"02",X"E6",X"02",X"FF",X"01",X"E4",X"01",X"E1",X"01",X"DD",X"01",X"D9",
+		X"02",X"D7",X"01",X"FF",X"01",X"D2",X"02",X"CC",X"01",X"FF",X"01",X"C9",X"02",X"CC",X"02",X"FF",
+		X"02",X"E6",X"02",X"FF",X"03",X"CC",X"06",X"FF",X"FF",X"00",X"00",X"00",X"04",X"D9",X"02",X"D7",
+		X"01",X"FF",X"01",X"D9",X"01",X"D2",X"01",X"FF",X"04",X"D9",X"01",X"DD",X"01",X"FF",X"01",X"DF",
+		X"01",X"FF",X"01",X"E1",X"01",X"FF",X"01",X"E2",X"01",X"FF",X"01",X"E4",X"01",X"FF",X"02",X"E6",
+		X"07",X"FF",X"FF",X"00",X"00",X"00",X"01",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"18",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"C8",X"D0",X"00",X"00",X"02",X"1B",
+		X"00",X"00",X"00",X"FD",X"00",X"00",X"00",X"00",X"04",X"00",X"FD",X"00",X"00",X"00",X"00",X"08",
+		X"00",X"FD",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"00",X"E8",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"B1",X"46",X"10",X"02",X"E1",X"17",X"00",X"00",X"00",X"00",X"00",X"29",
+		X"00",X"03",X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1D",X"25",
+		X"1D",X"38",X"1D",X"2E",X"00",X"00",X"00",X"00",X"C5",X"26",X"01",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"C3",X"01",X"18",X"27",X"C2",X"04",X"18",X"2D",X"C3",X"05",X"18",X"33",
+		X"C2",X"06",X"18",X"39",X"C3",X"02",X"18",X"3F",X"C2",X"03",X"18",X"45",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06
new file mode 100644
index 00000000..2000072a
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06	
@@ -0,0 +1 @@
+
				





	
				





	
				





	
				





	
				





	
				





	
				





	
				





	
				





	
				





			
				





			
				





			
				





			
				





			
				





			
				





			
				





			
				





			
				





			
				





	


				





	


				





	


				





	


				





	


				





	


				





	


				





	


				





	

\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06.vhd
new file mode 100644
index 00000000..0715686a
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06.vhd	
@@ -0,0 +1,86 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity tn06 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(9 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of tn06 is
+	type rom is array(0 to  1023) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0E",X"0E",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0E",X"0E",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0E",X"0E",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0E",X"0E",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0E",X"0E",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0F",X"0F",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0F",X"0F",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0F",X"0F",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07
new file mode 100644
index 00000000..7d88e647
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07	
@@ -0,0 +1 @@
+



				





	



				





	



				





	



				





	



				





	

				





	

				





	

				





	

				





	

				





			

				





			

				





			

				





			

				





			

				





			

				





			

				





			

				





			

				





			

				





	



				





	



				





	



				





	



				





	



				





	



				





	



				





	



				





	

\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07.vhd
new file mode 100644
index 00000000..580a92a7
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07.vhd	
@@ -0,0 +1,86 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity tn07 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(9 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of tn07 is
+	type rom is array(0 to  1023) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0D",X"0D",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0D",X"0D",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0D",X"0D",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0D",X"0D",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0D",X"0D",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0F",X"0F",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0F",X"0F",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0F",X"0F",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qpf
new file mode 100644
index 00000000..9f69ea50
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:27:39  November 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:27:39  November 20, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "BlueShark"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qsf
new file mode 100644
index 00000000..981a7773
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qsf	
@@ -0,0 +1,172 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 15:17:52  June 06, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		BlueShark_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/BlueShark_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/BlueShark_memory.sv
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/BlueShark_Overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY BlueShark_mist
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ----------------------------
+# start ENTITY(BlueShark_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(BlueShark_mist)
+# --------------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.sdc
new file mode 100644
index 00000000..f91c127c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/README.txt
new file mode 100644
index 00000000..07c9cf12
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/README.txt	
@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: Blue Shark port to MiST by Gehstock 
+-- 05 June 2019
+-- 
+---------------------------------------------------------------------------------
+-- 
+-- Midway 8080 Hardware
+-- Audio based on work by Paul Walsh.
+-- Audio and scan converter by MikeJ.
+---------------------------------------------------------------------------------
+-- 
+-- 
+-- Keyboard inputs :
+--
+--   F1          : Start
+--   SPACE       : Fire
+--   RIGHT/LEFT  : Movement
+--
+-- Joystick support.
+-- 
+-- 
+---------------------------------------------------------------------------------
+ToDo: Color Prom
+      Controls + DIP
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/Snapshot/BlueShark.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/Snapshot/BlueShark.rbf
new file mode 100644
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/clean.bat
new file mode 100644
index 00000000..83fb0c47
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/doc/Blue_Shark_-_1978_-_Midway_Games.pdf b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/doc/Blue_Shark_-_1978_-_Midway_Games.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..efc34017048fb9085f060aa6794231c68af43df2
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_Overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_Overlay.vhd
new file mode 100644
index 00000000..627256ff
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_Overlay.vhd	
@@ -0,0 +1,112 @@
+--Blue Shark Color Overlay Gehstock 2019
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+entity BlueShark_Overlay is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		AD                : in    std_logic_vector(15 downto 0);
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end BlueShark_Overlay;
+
+architecture rtl of BlueShark_Overlay is
+
+		signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_B1      : boolean;
+	signal Overlay_B1_VCnt : boolean;
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+	signal col_data        : std_logic_vector(3 downto 0);
+	signal col_addr        : std_logic_vector(9 downto 0);
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  Overlay_B1_VCnt <= false;
+	  Overlay_B1 <= false;
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt>= x"28") and (Vcnt <= x"35") then--Top Start
+		  Overlay_B1_VCnt <= true;
+		else
+		  Overlay_B1_VCnt <= false;
+		end if;
+	  end if;
+
+	  if (HCnt <= x"0") and Overlay_B1_VCnt then--Left Start
+		Overlay_B1 <= true;
+	  elsif (HCnt >= x"228") then--Right End
+		Overlay_B1 <= false;
+	  end if;
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video, Overlay_B1)
+  begin
+	if (Video = '0') then
+	  VideoRGB  <= "000";
+	else
+	  if Overlay_B1 then
+		VideoRGB  <= "001";
+	  else
+		VideoRGB  <= "111";
+	  end if;
+	end if;
+  end process;
+
+  
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_HSYNC   <= HSync;
+  O_VSYNC   <= VSync;
+
+
+end;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_memory.sv
new file mode 100644
index 00000000..59940ca0
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_memory.sv	
@@ -0,0 +1,68 @@
+module BlueShark_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+
+
+sprom #(
+	.init_file("./roms/blueshrk_h.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_0)
+	);
+
+sprom #(
+	.init_file("./roms/blueshrk_g.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_1)
+	);
+	
+sprom #(
+	.init_file("./roms/blueshrk_f.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_2)
+	);
+
+
+always @(Addr, rom_data_0, rom_data_1, rom_data_2) begin
+	Rom_out = 8'b00000000;
+		case (Addr[15:11])
+			5'b00000 : Rom_out = rom_data_0;
+			5'b00001 : Rom_out = rom_data_1;
+			5'b00010 : Rom_out = rom_data_2;
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_mist.sv
new file mode 100644
index 00000000..14647137
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_mist.sv	
@@ -0,0 +1,214 @@
+module BlueShark_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"BlueShark;;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Overlay, On, Off;",
+	"T6,Reset;",
+	"V,v0.00.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_core, clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+/*Dip Switch:SW
+1		2		3		4		5		6		7		8		Function	Option
+Unused
+				Off*
+				On
+Unused				
+								Off*
+								On
+Replay								
+										Off	On	 			14000
+										On		Off*	 		18000*
+										Off	Off	 		22000
+										On		On	 			None
+*/
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+	.DIP("00000000"),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(HSync),
+	.VSync(VSync)
+	);
+		
+BlueShark_memory BlueShark_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_core),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);		
+	  
+BlueShark_Overlay BlueShark_Overlay (
+	.Video(Video),
+	.Overlay(~status[5]),
+	.CLK(clk_core),
+	.Rst_n_s(Rst_n_s),
+	.HSync(HSync),
+	.VSync(VSync),
+	.AD(AD),
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({r,r,r}),
+	.G({g,g,g}),
+	.B({b,b,b}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ce_divider(0),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_left   = btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_fire1 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T8080se.vhd
new file mode 100644
index 00000000..65b92d54
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T8080se.vhd	
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..e09def1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..1c0f2638
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..e362f4b0
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders.vhd	
@@ -0,0 +1,243 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		DIP             : in  std_logic_vector(7 downto 0);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: entity work.mw8080
+		port map(
+			Rst_n => Rst_n,--Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+
+	GDB0(0) <= '1';             -- Unused
+	GDB0(1) <= '1';             -- Unused
+	GDB0(2) <= '1';             -- Unused
+	GDB0(3) <= '1';             -- Unused
+	GDB0(4) <= '1';             -- Unused
+	GDB0(5) <= '1';             -- Unused
+	GDB0(6) <= '1';             -- Unused
+	GDB0(7) <= '1';             -- Unused
+
+	GDB1(0) <= '1';	-- PADDLE
+	GDB1(1) <= '1';	-- PADDLE
+	GDB1(2) <= '1';	-- PADDLE
+	GDB1(3) <= '1';	-- PADDLE
+	GDB1(4) <= '1';	-- PADDLE
+	GDB1(5) <= '1';	-- PADDLE
+	GDB1(6) <= '1';	-- PADDLE
+	GDB1(7) <= '0';	-- PADDLE
+
+	GDB2(0) <= not Fire;
+	GDB2(1) <= not Coin;
+	GDB2(2) <= '1';	-- unknown
+	GDB2(3) <= '1';	-- TILT
+	GDB2(4) <= '1';	-- unknown
+	GDB2(5) <= '1';	-- Replay
+	GDB2(6) <= '1';	-- Replay
+	GDB2(7) <= '1';	-- TEST
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..f16cf379
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..1d9ad578
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,335 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..f8d0b139
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.vhd	
@@ -0,0 +1,382 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 20,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_f.hex
new file mode 100644
index 00000000..557f06b1
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_f.hex	
@@ -0,0 +1,129 @@
+:1000000066667E3C181C1818181818183C3C3C7E74
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_g.hex
new file mode 100644
index 00000000..8923d41f
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_g.hex	
@@ -0,0 +1,129 @@
+:10000000A7F2050837171213230605CD7D0F21022D
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_h.hex
new file mode 100644
index 00000000..212503d2
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_h.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qpf
new file mode 100644
index 00000000..56216d46
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 16:15:41  June 05, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:15:41  June 05, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "Boothill"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qsf
new file mode 100644
index 00000000..b07599dd
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qsf	
@@ -0,0 +1,176 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 20:29:53  August 09, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Boothill_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/SpaceWalk_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/invaders_memory.sv
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/romh.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/romg.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/romf.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/rome.vhd
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+set_global_assignment -name QIP_FILE "D:/Github/Mist_FPGA/common/mist/mist.qip"
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY SpaceWalk_mist
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ----------------------------
+# start ENTITY(SpaceWalk_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(SpaceWalk_mist)
+# --------------------------
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/README.txt
new file mode 100644
index 00000000..f5cc3629
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/README.txt	
@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: Booth Hill port to MiST by Gehstock 
+-- 05 June 2019
+-- 
+---------------------------------------------------------------------------------
+-- 
+-- Midway 8080 Hardware
+-- Audio based on work by Paul Walsh.
+-- Audio and scan converter by MikeJ.
+---------------------------------------------------------------------------------
+-- 
+-- 
+-- Keyboard inputs :
+--
+--   F1          : Start
+--   SPACE       : Fire
+--   RIGHT/LEFT  : Movement
+--
+-- Joystick support.
+-- 
+-- 
+---------------------------------------------------------------------------------
+
+Work in Progress
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/clean.bat
new file mode 100644
index 00000000..83fb0c47
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/SpaceWalk_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/SpaceWalk_mist.sv
new file mode 100644
index 00000000..b828472b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/SpaceWalk_mist.sv	
@@ -0,0 +1,198 @@
+module SpaceWalk_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"Boot Hill;;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_core, clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire [5:0]SoundCtrl6;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(btn_one_player),
+	.Sel2Player(btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+	.MoveUp(~m_up),
+	.MoveDown(~m_down),	
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.SoundCtrl6(SoundCtrl6),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(hs),
+	.VSync(vs)
+	);
+		
+invaders_memory invaders_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_core),
+	.S0(SoundCtrl3 | SoundCtrl4),
+	.S1(SoundCtrl4),
+	.S2(SoundCtrl5 | SoundCtrl6),//hi
+	.S3(SoundCtrl6),//lo
+	.Aud(audio)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({Video,Video,Video}),
+	.G({Video,Video,Video}),
+	.B({Video,Video,Video}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.ce_divider(0),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_up     = btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_fire2 = 0;
+reg btn_fire3 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h14: btn_fire3       <= key_pressed; // ctrl
+			'h11: btn_fire2       <= key_pressed; // alt
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T8080se.vhd
new file mode 100644
index 00000000..65b92d54
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T8080se.vhd	
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..e09def1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..1c0f2638
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..f3c51b25
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders.vhd	
@@ -0,0 +1,283 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		MoveUp          : in  std_logic;
+		MoveDown        : in  std_logic;
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);--audio1
+		SoundCtrl4      : out std_logic_vector(5 downto 0);--audio2
+		SoundCtrl5      : out std_logic_vector(5 downto 0);--low
+		SoundCtrl6      : out std_logic_vector(5 downto 0);--hi
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+	component mw8080
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+	end component;
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(7 downto 0);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(4) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: mw8080
+		port map(
+			Rst_n => Rst_n,--Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+
+	GDB0(0) <= not MoveUp;--active low
+	GDB0(1) <= not MoveDown;--active low
+	GDB0(2) <= not MoveLeft;--active low
+	GDB0(3) <= not MoveRight;--active low
+	GDB0(4) <= '0';--active low
+	GDB0(5) <= '1';--active low
+	GDB0(6) <= '0';--active low
+	GDB0(7) <= not Fire;
+	
+	GDB1(0) <= not MoveUp;--active low
+	GDB1(1) <= not MoveDown;--active low
+	GDB1(2) <= not MoveLeft;--active low
+	GDB1(3) <= not MoveRight;--active low
+	GDB1(4) <= '0';--active low
+	GDB1(5) <= '1';--active low
+	GDB1(6) <= '0';--active low
+	GDB1(7) <= not Fire;--active low
+
+	GDB2(0) <= '1';--coin
+	GDB2(1) <= '0';--coin
+	GDB2(2) <= '1';--time
+	GDB2(3) <= '1';--time
+	GDB2(4) <= '0';--DIPLOCK --active high
+	GDB2(5) <= not Sel1Player;--active low
+	GDB2(6) <= not Coin;--active low
+	GDB2(7) <= not Sel2Player;--active low
+
+--	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+---	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+---	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+--	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+--	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl4 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			SoundCtrl6 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);--audio_1_w
+			end if;
+--			if PortWr(4) = '1' and OldSample = '0' then
+--				D5(15 downto 8) <= DB;
+--				D5(7 downto 0) <= D5(15 downto 8);
+--			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);--tone_generator_lo_w
+			end if;
+			if PortWr(6) = '1' then
+				SoundCtrl6 <= DB(5 downto 0);--tone_generator_hi_w
+			end if;
+			if PortWr(7) = '1' then
+				SoundCtrl4 <= DB(5 downto 0);--audio_2_w
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..d48ec86a
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,498 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S0  : in  std_logic_vector(5 downto 0);
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  S3  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S0)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s0_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s0_t1 <= S0;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S0(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S0(3) = '1') and (s0_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S0(2) = '1') and (s0_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S0(1) = '1') and (s0_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_memory.sv
new file mode 100644
index 00000000..382edd1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_memory.sv	
@@ -0,0 +1,66 @@
+
+module invaders_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+
+
+
+romh romh (
+	.clk(Clock),
+	.addr(Addr[10:0]),
+	.data(rom_data_0)
+);
+
+romg romg (
+	.clk(Clock),
+	.addr(Addr[10:0]),
+	.data(rom_data_1)
+);
+
+romf romf (
+	.clk(Clock),
+	.addr(Addr[10:0]),
+	.data(rom_data_2)
+);
+
+rome rome (
+	.clk(Clock),
+	.addr(Addr[10:0]),
+	.data(rom_data_3)
+);
+
+	
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3) begin
+	Rom_out = 8'b00000000;
+		case (Addr[13:11])
+			3'b000 : Rom_out = rom_data_0;
+			3'b001 : Rom_out = rom_data_1;
+			3'b010 : Rom_out = rom_data_2;
+			3'b011 : Rom_out = rom_data_3;
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_video.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_video.vhd
new file mode 100644
index 00000000..77ac2478
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_video.vhd	
@@ -0,0 +1,127 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+entity invaders_video is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end invaders_video;
+
+architecture rtl of invaders_video is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_G1      : boolean;
+	signal Overlay_G2      : boolean;
+	signal Overlay_R1      : boolean;
+	signal Overlay_G1_VCnt : boolean;
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  Overlay_G1_VCnt <= false;
+	  Overlay_G1 <= false;
+	  Overlay_G2 <= false;
+	  Overlay_R1 <= false;
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt = x"1F") then
+		  Overlay_G1_VCnt <= true;
+		elsif (Vcnt = x"95") then
+		  Overlay_G1_VCnt <= false;
+		end if;
+	  end if;
+
+	  if (HCnt = x"027") and Overlay_G1_VCnt then
+		Overlay_G1 <= true;
+	  elsif (HCnt = x"046") then
+		Overlay_G1 <= false;
+	  end if;
+
+	  if (HCnt = x"046") then
+		Overlay_G2 <= true;
+	  elsif (HCnt = x"0B6") then
+		Overlay_G2 <= false;
+	  end if;
+
+	  if (HCnt = x"1A6") then
+		Overlay_R1 <= true;
+	  elsif (HCnt = x"1E6") then
+		Overlay_R1 <= false;
+	  end if;
+
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1)
+  begin
+	if (Video = '0') then
+	  VideoRGB  <= "000";
+	else
+	  if Overlay_G1 or Overlay_G2 then
+		VideoRGB  <= "010";
+	  elsif Overlay_R1 then
+		VideoRGB  <= "100";
+	  else
+		VideoRGB  <= "111";
+	  end if;
+	end if;
+  end process;
+
+
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_HSYNC   <= not HSync;
+  O_VSYNC   <= not VSync;
+
+
+end;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..b9a88f96
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,336 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..f8d0b139
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/pll.vhd	
@@ -0,0 +1,382 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 20,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/rome.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/rome.vhd
new file mode 100644
index 00000000..de22ea71
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/rome.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity rome is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of rome is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"A7",X"32",X"48",X"20",X"FC",X"41",X"18",X"78",X"91",X"C8",X"44",X"4D",X"6F",X"9F",X"67",X"CD",
+		X"41",X"18",X"EB",X"3E",X"11",X"21",X"00",X"00",X"E5",X"19",X"D2",X"1E",X"18",X"E3",X"E1",X"F5",
+		X"79",X"17",X"4F",X"78",X"17",X"47",X"7D",X"17",X"6F",X"7C",X"17",X"67",X"F1",X"3D",X"C2",X"18",
+		X"18",X"AF",X"7C",X"1F",X"57",X"7D",X"1F",X"5F",X"3A",X"48",X"20",X"A7",X"79",X"F0",X"2F",X"3C",
+		X"C9",X"7C",X"2F",X"67",X"7D",X"2F",X"6F",X"23",X"C9",X"11",X"4A",X"20",X"1A",X"3D",X"CA",X"66",
+		X"18",X"12",X"F6",X"30",X"21",X"29",X"20",X"77",X"11",X"B0",X"3E",X"3E",X"01",X"CD",X"30",X"01",
+		X"3E",X"1E",X"32",X"25",X"20",X"C9",X"AF",X"32",X"57",X"20",X"32",X"58",X"20",X"32",X"27",X"20",
+		X"CD",X"79",X"18",X"FA",X"60",X"18",X"C3",X"10",X"19",X"21",X"86",X"20",X"11",X"0B",X"00",X"19",
+		X"7E",X"A7",X"F8",X"7D",X"FE",X"B2",X"C2",X"7F",X"18",X"C9",X"21",X"55",X"20",X"7E",X"A7",X"11",
+		X"5E",X"20",X"C2",X"98",X"18",X"11",X"70",X"20",X"23",X"34",X"4E",X"06",X"00",X"21",X"7C",X"19",
+		X"09",X"7E",X"EB",X"56",X"2B",X"5E",X"2B",X"77",X"2B",X"1F",X"3E",X"47",X"DA",X"B0",X"18",X"3D",
+		X"B6",X"77",X"21",X"22",X"1A",X"09",X"09",X"7E",X"23",X"66",X"6F",X"E9",X"3E",X"0F",X"32",X"24",
+		X"20",X"CD",X"D9",X"11",X"D6",X"04",X"FE",X"25",X"D2",X"CD",X"18",X"C6",X"07",X"57",X"EB",X"22",
+		X"4E",X"20",X"EB",X"3A",X"09",X"20",X"E6",X"1C",X"4F",X"06",X"00",X"21",X"2E",X"1E",X"09",X"3E",
+		X"04",X"C3",X"30",X"01",X"21",X"C8",X"1D",X"3A",X"55",X"20",X"A7",X"CA",X"F1",X"18",X"21",X"E0",
+		X"1D",X"CD",X"82",X"1C",X"3E",X"0A",X"32",X"24",X"20",X"2A",X"4E",X"20",X"EB",X"3E",X"0F",X"C3",
+		X"6E",X"1B",X"3E",X"0F",X"32",X"24",X"20",X"2A",X"4E",X"20",X"EB",X"3E",X"10",X"C3",X"6E",X"1B",
+		X"AF",X"32",X"23",X"20",X"2A",X"0F",X"20",X"22",X"06",X"20",X"C9",X"2A",X"06",X"20",X"23",X"22",
+		X"06",X"20",X"C9",X"AF",X"32",X"57",X"20",X"32",X"58",X"20",X"32",X"27",X"20",X"32",X"25",X"20",
+		X"CD",X"79",X"18",X"FA",X"4D",X"19",X"3A",X"06",X"20",X"D6",X"67",X"C2",X"4D",X"19",X"32",X"0A",
+		X"20",X"21",X"91",X"1A",X"22",X"06",X"20",X"21",X"F6",X"1D",X"C3",X"87",X"1C",X"3E",X"01",X"32",
+		X"08",X"20",X"C9",X"8A",X"1B",X"68",X"1B",X"81",X"1B",X"8B",X"1B",X"9D",X"1B",X"A6",X"1B",X"B2",
+		X"1B",X"49",X"12",X"11",X"1C",X"24",X"1C",X"5C",X"1C",X"6F",X"1C",X"2B",X"1D",X"48",X"1D",X"7B",
+		X"1C",X"7F",X"1C",X"A0",X"80",X"60",X"30",X"0E",X"74",X"74",X"78",X"78",X"7A",X"B0",X"C0",X"D0",
+		X"D1",X"58",X"71",X"8F",X"A8",X"FF",X"80",X"50",X"0E",X"9E",X"5E",X"2E",X"0D",X"2A",X"0C",X"30",
+		X"0B",X"38",X"12",X"2A",X"13",X"30",X"14",X"38",X"15",X"00",X"12",X"00",X"11",X"00",X"0F",X"00",
+		X"0E",X"00",X"00",X"00",X"15",X"01",X"12",X"01",X"11",X"00",X"0F",X"00",X"0E",X"01",X"00",X"00",
+		X"BC",X"15",X"BC",X"15",X"BC",X"15",X"BC",X"15",X"BC",X"15",X"BC",X"15",X"BC",X"15",X"D5",X"15",
+		X"C5",X"15",X"C5",X"15",X"C5",X"15",X"C5",X"15",X"C5",X"15",X"C5",X"15",X"C5",X"15",X"61",X"16",
+		X"06",X"06",X"1A",X"15",X"06",X"FE",X"1A",X"04",X"06",X"00",X"1A",X"09",X"06",X"FA",X"1A",X"FE",
+		X"06",X"04",X"1A",X"11",X"06",X"FC",X"1A",X"02",X"06",X"02",X"1A",X"0E",X"FA",X"06",X"FC",X"15",
+		X"FA",X"FE",X"FC",X"04",X"FA",X"00",X"FC",X"09",X"FA",X"FA",X"FC",X"FE",X"FA",X"04",X"FC",X"11",
+		X"FA",X"FC",X"FC",X"02",X"FA",X"02",X"FC",X"0E",X"E4",X"0A",X"0B",X"38",X"00",X"0B",X"0C",X"30",
+		X"17",X"0B",X"0D",X"2A",X"E4",X"0A",X"14",X"38",X"00",X"0B",X"13",X"30",X"17",X"0B",X"12",X"2A",
+		X"08",X"09",X"0A",X"09",X"BC",X"18",X"E4",X"18",X"02",X"19",X"8A",X"1B",X"00",X"00",X"00",X"01",
+		X"01",X"00",X"01",X"01",X"01",X"02",X"02",X"01",X"02",X"02",X"02",X"03",X"03",X"02",X"03",X"03",
+		X"03",X"04",X"04",X"03",X"04",X"04",X"00",X"02",X"FE",X"00",X"02",X"FE",X"00",X"01",X"FF",X"00",
+		X"01",X"FF",X"00",X"00",X"FE",X"02",X"00",X"06",X"FA",X"00",X"FF",X"01",X"00",X"FF",X"01",X"00",
+		X"01",X"40",X"03",X"42",X"05",X"44",X"06",X"45",X"07",X"46",X"A8",X"E8",X"AA",X"E8",X"AC",X"E8",
+		X"AD",X"E8",X"AE",X"E8",X"05",X"02",X"05",X"06",X"09",X"06",X"01",X"0A",X"19",X"01",X"04",X"17",
+		X"05",X"06",X"15",X"07",X"02",X"13",X"03",X"03",X"11",X"02",X"07",X"0F",X"06",X"05",X"01",X"04",
+		X"01",X"06",X"01",X"11",X"20",X"06",X"00",X"44",X"20",X"04",X"0A",X"AE",X"1A",X"02",X"0E",X"00",
+		X"24",X"03",X"1E",X"00",X"02",X"07",X"00",X"24",X"03",X"1E",X"00",X"05",X"9D",X"1A",X"0E",X"08",
+		X"0A",X"02",X"09",X"00",X"28",X"03",X"3C",X"00",X"02",X"11",X"00",X"30",X"03",X"3C",X"00",X"02",
+		X"0A",X"00",X"3C",X"03",X"3C",X"00",X"08",X"0A",X"09",X"5F",X"20",X"00",X"10",X"08",X"32",X"80",
+		X"09",X"71",X"20",X"00",X"10",X"DE",X"36",X"88",X"04",X"00",X"AE",X"1A",X"06",X"01",X"28",X"20",
+		X"03",X"5A",X"00",X"0D",X"05",X"E0",X"1A",X"08",X"0F",X"95",X"1C",X"08",X"10",X"9C",X"1D",X"0B",
+		X"11",X"20",X"FB",X"1A",X"02",X"12",X"00",X"2C",X"05",X"FF",X"1A",X"02",X"13",X"00",X"30",X"03",
+		X"69",X"00",X"08",X"06",X"01",X"44",X"20",X"0A",X"07",X"09",X"5F",X"20",X"01",X"B0",X"01",X"38",
+		X"80",X"0B",X"11",X"20",X"26",X"1B",X"06",X"84",X"5B",X"20",X"06",X"35",X"5C",X"20",X"06",X"1E",
+		X"28",X"20",X"06",X"50",X"27",X"20",X"09",X"71",X"20",X"01",X"B0",X"DE",X"34",X"88",X"02",X"0B",
+		X"A0",X"34",X"03",X"1E",X"00",X"02",X"0C",X"A0",X"34",X"03",X"0F",X"00",X"02",X"08",X"A0",X"34",
+		X"02",X"0D",X"A2",X"3E",X"0B",X"47",X"20",X"52",X"1B",X"0C",X"09",X"83",X"20",X"00",X"B0",X"74",
+		X"01",X"80",X"06",X"01",X"58",X"20",X"06",X"01",X"57",X"20",X"0B",X"11",X"20",X"63",X"1B",X"06",
+		X"00",X"57",X"20",X"04",X"00",X"02",X"1B",X"00",X"1A",X"13",X"CD",X"8B",X"1C",X"EB",X"4F",X"21",
+		X"4E",X"1E",X"7E",X"23",X"A7",X"F2",X"72",X"1B",X"0D",X"C2",X"72",X"1B",X"E6",X"7F",X"C3",X"30",
+		X"01",X"EB",X"7E",X"32",X"23",X"20",X"23",X"22",X"06",X"20",X"C9",X"EB",X"7E",X"32",X"22",X"20",
+		X"23",X"5E",X"23",X"56",X"23",X"22",X"06",X"20",X"EB",X"22",X"0F",X"20",X"C9",X"EB",X"5E",X"23",
+		X"56",X"EB",X"22",X"06",X"20",X"C9",X"EB",X"7E",X"23",X"5E",X"23",X"56",X"23",X"22",X"06",X"20",
+		X"12",X"C9",X"21",X"0D",X"20",X"7E",X"23",X"B6",X"FE",X"04",X"F2",X"BE",X"1B",X"AF",X"32",X"47",
+		X"20",X"21",X"AF",X"0D",X"11",X"0D",X"3A",X"CD",X"F7",X"1B",X"21",X"14",X"1A",X"3A",X"0D",X"20",
+		X"CD",X"D9",X"1B",X"21",X"08",X"1A",X"3A",X"0E",X"20",X"A7",X"C8",X"FE",X"03",X"FA",X"E2",X"1B",
+		X"3E",X"03",X"F5",X"5E",X"23",X"56",X"23",X"D5",X"5E",X"23",X"56",X"23",X"E3",X"CD",X"F7",X"1B",
+		X"E1",X"F1",X"3D",X"C2",X"E2",X"1B",X"C9",X"4E",X"23",X"46",X"23",X"EB",X"C5",X"E5",X"1A",X"13",
+		X"77",X"23",X"0D",X"C2",X"FE",X"1B",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"FC",X"1B",
+		X"C9",X"EB",X"5E",X"23",X"56",X"23",X"0E",X"05",X"7E",X"23",X"12",X"1B",X"0D",X"C2",X"18",X"1C",
+		X"22",X"06",X"20",X"C9",X"11",X"0D",X"20",X"01",X"29",X"20",X"CD",X"44",X"1C",X"13",X"CD",X"44",
+		X"1C",X"11",X"00",X"24",X"21",X"29",X"20",X"3E",X"02",X"CD",X"30",X"01",X"11",X"1E",X"24",X"3E",
+		X"02",X"C3",X"30",X"01",X"1A",X"1F",X"1F",X"1F",X"1F",X"E6",X"0F",X"C2",X"50",X"1C",X"3E",X"10",
+		X"C6",X"30",X"02",X"03",X"1A",X"E6",X"0F",X"C6",X"30",X"02",X"03",X"C9",X"EB",X"4E",X"23",X"46",
+		X"23",X"5E",X"23",X"56",X"23",X"0A",X"A7",X"C2",X"6B",X"1C",X"EB",X"22",X"06",X"20",X"C9",X"21",
+		X"0D",X"3A",X"11",X"BD",X"20",X"01",X"06",X"24",X"C3",X"FC",X"1B",X"CD",X"8B",X"1C",X"E9",X"CD",
+		X"8B",X"1C",X"3A",X"0A",X"20",X"A7",X"C8",X"22",X"00",X"20",X"C9",X"EB",X"5E",X"23",X"56",X"23",
+		X"22",X"06",X"20",X"EB",X"C9",X"3A",X"12",X"20",X"0E",X"05",X"FE",X"04",X"D2",X"B0",X"1C",X"3D",
+		X"07",X"07",X"47",X"DB",X"02",X"E6",X"03",X"B0",X"4F",X"06",X"00",X"21",X"17",X"1D",X"09",X"4E",
+		X"11",X"00",X"28",X"11",X"00",X"28",X"04",X"79",X"A7",X"1F",X"4F",X"D2",X"CE",X"1C",X"C5",X"D5",
+		X"78",X"CD",X"6E",X"1B",X"E1",X"11",X"00",X"02",X"19",X"EB",X"C1",X"C3",X"B6",X"1C",X"C2",X"B6",
+		X"1C",X"D3",X"04",X"DB",X"02",X"2F",X"E6",X"A0",X"CA",X"D1",X"1C",X"07",X"E6",X"01",X"4F",X"DB",
+		X"02",X"07",X"E6",X"06",X"B1",X"4F",X"06",X"00",X"21",X"23",X"1D",X"09",X"46",X"21",X"12",X"20",
+		X"7E",X"90",X"FA",X"D1",X"1C",X"F3",X"7E",X"90",X"77",X"79",X"E6",X"01",X"3D",X"32",X"11",X"20",
+		X"3D",X"32",X"0A",X"20",X"DB",X"02",X"E6",X"0C",X"07",X"07",X"C6",X"64",X"32",X"08",X"20",X"AF",
+		X"32",X"0D",X"20",X"32",X"0E",X"20",X"C9",X"2B",X"05",X"08",X"08",X"05",X"05",X"33",X"05",X"05",
+		X"05",X"2B",X"05",X"01",X"02",X"01",X"01",X"02",X"04",X"02",X"02",X"3A",X"49",X"20",X"A7",X"C0",
+		X"3E",X"01",X"CD",X"C2",X"17",X"32",X"71",X"20",X"21",X"6E",X"20",X"7E",X"E6",X"0F",X"B0",X"77",
+		X"2B",X"7E",X"F6",X"42",X"77",X"C3",X"61",X"16",X"3A",X"12",X"20",X"A7",X"C2",X"D1",X"16",X"C9",
+		X"00",X"00",X"3F",X"13",X"1D",X"16",X"33",X"18",X"3F",X"1A",X"05",X"1D",X"01",X"1F",X"39",X"20",
+		X"27",X"22",X"11",X"24",X"35",X"25",X"13",X"27",X"2B",X"28",X"3F",X"29",X"0F",X"2B",X"19",X"2C",
+		X"1F",X"2D",X"21",X"2E",X"21",X"2F",X"1D",X"30",X"15",X"31",X"09",X"32",X"3B",X"32",X"29",X"33",
+		X"17",X"34",X"3F",X"34",X"27",X"35",X"0D",X"36",X"31",X"36",X"11",X"37",X"31",X"37",X"0F",X"38",
+		X"2B",X"38",X"05",X"39",X"1D",X"39",X"35",X"39",X"0B",X"3A",X"21",X"3A",X"84",X"06",X"14",X"02",
+		X"12",X"03",X"11",X"01",X"0F",X"0A",X"11",X"01",X"08",X"01",X"08",X"04",X"0D",X"01",X"0D",X"01",
+		X"0D",X"03",X"0D",X"01",X"0C",X"02",X"0D",X"0A",X"0F",X"00",X"84",X"01",X"15",X"02",X"00",X"02",
+		X"0E",X"01",X"11",X"03",X"10",X"03",X"0C",X"00",X"84",X"04",X"0F",X"03",X"0F",X"01",X"0F",X"04",
+		X"0F",X"03",X"12",X"01",X"11",X"03",X"11",X"01",X"0F",X"03",X"0F",X"01",X"0E",X"08",X"0F",X"00",
+		X"84",X"02",X"08",X"01",X"0D",X"01",X"0D",X"02",X"11",X"0A",X"14",X"01",X"14",X"01",X"14",X"02",
+		X"11",X"02",X"0D",X"0A",X"11",X"00",X"86",X"03",X"0A",X"01",X"0A",X"06",X"0F",X"03",X"0A",X"01",
+		X"0F",X"06",X"13",X"03",X"0A",X"01",X"0F",X"02",X"13",X"03",X"0A",X"01",X"0F",X"02",X"13",X"03",
+		X"0A",X"01",X"0F",X"06",X"13",X"03",X"0F",X"01",X"13",X"04",X"16",X"02",X"13",X"02",X"0F",X"06",
+		X"0A",X"03",X"0A",X"01",X"0A",X"06",X"0F",X"00",X"40",X"40",X"40",X"40",X"40",X"40",X"55",X"47",
+		X"48",X"5B",X"50",X"4F",X"57",X"5B",X"5A",X"41",X"50",X"5B",X"57",X"41",X"4D",X"5B",X"42",X"41",
+		X"4D",X"5B",X"54",X"48",X"55",X"44",X"55",X"4D",X"46",X"5B",X"41",X"52",X"47",X"5B",X"8D",X"27",
+		X"54",X"4F",X"40",X"53",X"54",X"41",X"52",X"54",X"40",X"47",X"41",X"4D",X"45",X"95",X"2B",X"50",
+		X"52",X"45",X"53",X"53",X"40",X"31",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"40",X"42",X"55",
+		X"54",X"54",X"4F",X"4E",X"9A",X"2D",X"50",X"52",X"45",X"53",X"53",X"40",X"31",X"40",X"4F",X"52",
+		X"40",X"32",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"40",X"42",X"55",X"54",X"54",X"4F",X"4E",
+		X"92",X"29",X"49",X"4E",X"53",X"45",X"52",X"54",X"40",X"31",X"40",X"4D",X"4F",X"52",X"45",X"40",
+		X"43",X"4F",X"49",X"4E",X"93",X"2A",X"49",X"4E",X"53",X"45",X"52",X"54",X"40",X"32",X"40",X"4D",
+		X"4F",X"52",X"45",X"40",X"43",X"4F",X"49",X"4E",X"53",X"93",X"2A",X"46",X"4F",X"52",X"40",X"54",
+		X"57",X"4F",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"40",X"47",X"41",X"4D",X"45",X"89",X"89",
+		X"24",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"89",X"25",X"42",X"4F",X"4F",X"54",
+		X"40",X"48",X"49",X"4C",X"4C",X"8B",X"26",X"49",X"4E",X"53",X"45",X"52",X"54",X"40",X"43",X"4F",
+		X"49",X"4E",X"40",X"89",X"24",X"47",X"45",X"54",X"40",X"52",X"45",X"41",X"44",X"59",X"89",X"24",
+		X"40",X"40",X"44",X"52",X"41",X"57",X"5B",X"40",X"40",X"8C",X"5C",X"5C",X"5C",X"5C",X"5C",X"5C",
+		X"20",X"5C",X"5C",X"5C",X"5C",X"5C",X"5C",X"89",X"24",X"47",X"41",X"4D",X"45",X"40",X"4F",X"56",
+		X"45",X"52",X"87",X"53",X"48",X"4F",X"54",X"13",X"4D",X"45",X"5B",X"87",X"40",X"40",X"40",X"40",
+		X"13",X"40",X"40",X"40",X"9A",X"27",X"54",X"57",X"4F",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",
+		X"40",X"4F",X"52",X"1D",X"53",X"49",X"4E",X"47",X"4C",X"45",X"40",X"50",X"4C",X"41",X"59",X"45",
+		X"52",X"B2",X"2A",X"55",X"53",X"45",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"40",X"31",X"40",
+		X"48",X"41",X"4E",X"44",X"4C",X"45",X"53",X"28",X"43",X"4F",X"4D",X"50",X"55",X"54",X"45",X"52",
+		X"40",X"43",X"4F",X"4E",X"54",X"52",X"4F",X"4C",X"53",X"40",X"4F",X"54",X"48",X"45",X"52",X"40",
+		X"43",X"4F",X"57",X"42",X"4F",X"59",X"99",X"2D",X"4D",X"41",X"59",X"40",X"54",X"48",X"45",X"40",
+		X"42",X"45",X"54",X"54",X"45",X"52",X"40",X"43",X"4F",X"57",X"42",X"4F",X"59",X"40",X"57",X"49",
+		X"4E",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romf.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romf.vhd
new file mode 100644
index 00000000..032ba6d3
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romf.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity romf is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of romf is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"7E",X"A7",X"CA",X"0E",X"10",X"C6",X"99",X"27",X"77",X"C2",X"0E",X"10",X"06",X"01",X"21",X"22",
+		X"20",X"CD",X"32",X"10",X"21",X"23",X"20",X"CD",X"32",X"10",X"23",X"CD",X"32",X"10",X"23",X"CD",
+		X"32",X"10",X"23",X"CD",X"32",X"10",X"23",X"CD",X"32",X"10",X"23",X"CD",X"32",X"10",X"32",X"4B",
+		X"20",X"C9",X"7E",X"A7",X"CA",X"3C",X"10",X"35",X"C2",X"3C",X"10",X"37",X"78",X"17",X"47",X"C9",
+		X"21",X"86",X"20",X"11",X"0B",X"00",X"19",X"E5",X"E5",X"CD",X"A6",X"10",X"E1",X"7D",X"FE",X"B2",
+		X"C2",X"43",X"10",X"E1",X"CD",X"0D",X"12",X"E1",X"CD",X"0D",X"12",X"E1",X"CD",X"0D",X"12",X"E1",
+		X"C3",X"0D",X"12",X"11",X"54",X"20",X"1A",X"3C",X"FE",X"03",X"C2",X"6E",X"10",X"AF",X"12",X"21",
+		X"49",X"20",X"11",X"12",X"00",X"19",X"3D",X"F2",X"75",X"10",X"C9",X"7E",X"E6",X"20",X"C8",X"7E",
+		X"E6",X"9F",X"77",X"01",X"06",X"00",X"09",X"11",X"33",X"20",X"CD",X"91",X"10",X"23",X"23",X"23",
+		X"23",X"1A",X"13",X"77",X"23",X"1A",X"13",X"77",X"23",X"13",X"13",X"13",X"1A",X"13",X"3C",X"77",
+		X"23",X"1A",X"13",X"77",X"23",X"C9",X"3A",X"0B",X"20",X"AE",X"E6",X"10",X"C0",X"7E",X"E6",X"20",
+		X"C8",X"7E",X"E6",X"40",X"C2",X"B9",X"10",X"36",X"00",X"01",X"05",X"00",X"09",X"5E",X"23",X"56",
+		X"23",X"EB",X"CD",X"C8",X"10",X"0E",X"1F",X"09",X"1A",X"13",X"77",X"23",X"1A",X"13",X"77",X"C9",
+		X"7E",X"E6",X"20",X"C8",X"23",X"01",X"05",X"00",X"09",X"5E",X"23",X"56",X"23",X"7B",X"B2",X"C8",
+		X"D5",X"5E",X"23",X"56",X"09",X"E3",X"CD",X"F6",X"10",X"E1",X"5E",X"23",X"56",X"23",X"7B",X"B2",
+		X"C8",X"D5",X"5E",X"23",X"56",X"E1",X"01",X"20",X"00",X"E5",X"7B",X"36",X"00",X"23",X"3D",X"C2",
+		X"FB",X"10",X"E1",X"09",X"15",X"C2",X"F9",X"10",X"C9",X"21",X"33",X"20",X"5E",X"23",X"56",X"23",
+		X"7A",X"B3",X"C8",X"D5",X"7E",X"23",X"D3",X"01",X"5E",X"23",X"56",X"23",X"4E",X"23",X"46",X"23",
+		X"E3",X"E6",X"08",X"CC",X"94",X"11",X"C4",X"EB",X"11",X"E1",X"C3",X"0C",X"11",X"7E",X"E6",X"40",
+		X"C8",X"7E",X"E6",X"BF",X"F6",X"20",X"77",X"E6",X"08",X"47",X"23",X"23",X"5E",X"23",X"7B",X"E6",
+		X"07",X"05",X"FA",X"46",X"11",X"2F",X"32",X"35",X"20",X"32",X"3C",X"20",X"56",X"23",X"CD",X"D9",
+		X"11",X"EB",X"22",X"33",X"20",X"EB",X"D5",X"CD",X"B3",X"11",X"23",X"23",X"23",X"23",X"E5",X"21",
+		X"36",X"20",X"CD",X"87",X"11",X"E1",X"C1",X"5E",X"23",X"7B",X"A7",X"C8",X"16",X"00",X"3E",X"05",
+		X"EB",X"29",X"3D",X"C2",X"71",X"11",X"09",X"EB",X"7E",X"23",X"83",X"5F",X"EB",X"22",X"3A",X"20",
+		X"EB",X"CD",X"B3",X"11",X"21",X"3D",X"20",X"73",X"23",X"72",X"23",X"71",X"23",X"70",X"23",X"AF",
+		X"77",X"23",X"77",X"C9",X"C5",X"E5",X"1A",X"13",X"D3",X"02",X"DB",X"03",X"77",X"23",X"0D",X"C2",
+		X"96",X"11",X"AF",X"D3",X"02",X"DB",X"03",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",
+		X"94",X"11",X"C9",X"5E",X"23",X"E5",X"16",X"00",X"21",X"01",X"03",X"19",X"19",X"5E",X"23",X"56",
+		X"EB",X"E3",X"5E",X"23",X"E3",X"16",X"00",X"19",X"19",X"5E",X"23",X"56",X"E1",X"EB",X"4E",X"23",
+		X"46",X"23",X"EB",X"C9",X"7B",X"E6",X"07",X"D3",X"01",X"06",X"03",X"AF",X"7A",X"1F",X"57",X"7B",
+		X"1F",X"5F",X"05",X"C2",X"DB",X"11",X"7A",X"C6",X"24",X"57",X"C9",X"79",X"85",X"6F",X"C5",X"E5",
+		X"1A",X"13",X"D3",X"02",X"DB",X"03",X"77",X"2B",X"0D",X"C2",X"F0",X"11",X"AF",X"D3",X"02",X"DB",
+		X"03",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"EE",X"11",X"C9",X"3A",X"0B",X"20",
+		X"AE",X"E6",X"10",X"C0",X"7E",X"E6",X"40",X"C8",X"7E",X"F6",X"20",X"77",X"23",X"23",X"5E",X"23",
+		X"23",X"56",X"23",X"CD",X"D4",X"11",X"73",X"23",X"72",X"23",X"EB",X"CD",X"32",X"12",X"01",X"1F",
+		X"00",X"09",X"7E",X"12",X"13",X"3E",X"03",X"D3",X"02",X"DB",X"03",X"B6",X"77",X"23",X"7E",X"12",
+		X"13",X"AF",X"D3",X"02",X"DB",X"03",X"B6",X"77",X"C9",X"F3",X"E1",X"01",X"00",X"00",X"11",X"00",
+		X"00",X"31",X"20",X"40",X"3E",X"10",X"C5",X"13",X"BA",X"C2",X"56",X"12",X"31",X"00",X"24",X"E9",
+		X"7E",X"A7",X"F0",X"E6",X"04",X"01",X"00",X"00",X"11",X"04",X"FC",X"CA",X"71",X"12",X"11",X"06",
+		X"FA",X"23",X"7E",X"E6",X"0F",X"CA",X"A9",X"12",X"1F",X"D2",X"7D",X"12",X"42",X"1F",X"D2",X"82",
+		X"12",X"43",X"1F",X"D2",X"87",X"12",X"4A",X"1F",X"D2",X"8C",X"12",X"4B",X"79",X"0E",X"00",X"23",
+		X"A7",X"C4",X"D0",X"12",X"23",X"78",X"A7",X"C4",X"C6",X"12",X"2B",X"2B",X"79",X"A7",X"CA",X"A9",
+		X"12",X"2B",X"7E",X"E6",X"ED",X"F6",X"60",X"77",X"C9",X"2B",X"7E",X"E6",X"02",X"C2",X"A2",X"12",
+		X"54",X"5D",X"01",X"0C",X"00",X"09",X"7E",X"FE",X"08",X"C8",X"36",X"08",X"EB",X"7E",X"E6",X"10",
+		X"C0",X"7E",X"F6",X"70",X"77",X"C9",X"86",X"FE",X"11",X"D8",X"FE",X"B4",X"D0",X"77",X"0C",X"C9",
+		X"86",X"E5",X"F5",X"23",X"23",X"23",X"5E",X"16",X"00",X"7D",X"FE",X"60",X"21",X"60",X"1A",X"CA",
+		X"E5",X"12",X"21",X"6A",X"1A",X"19",X"19",X"5E",X"23",X"56",X"F1",X"E1",X"BB",X"D8",X"BA",X"D0",
+		X"77",X"0C",X"C9",X"21",X"5B",X"20",X"7E",X"A7",X"F2",X"10",X"13",X"CD",X"39",X"13",X"11",X"46",
+		X"1A",X"3A",X"5C",X"20",X"CD",X"50",X"13",X"21",X"98",X"19",X"CD",X"99",X"13",X"22",X"65",X"20",
+		X"21",X"6D",X"20",X"7E",X"A7",X"F2",X"2D",X"13",X"CD",X"39",X"13",X"11",X"53",X"1A",X"3A",X"6E",
+		X"20",X"CD",X"50",X"13",X"21",X"A4",X"19",X"CD",X"99",X"13",X"22",X"77",X"20",X"21",X"7F",X"20",
+		X"7E",X"A7",X"F0",X"CD",X"39",X"13",X"23",X"71",X"C9",X"23",X"23",X"22",X"50",X"20",X"23",X"7E",
+		X"23",X"EB",X"21",X"73",X"19",X"01",X"FF",X"00",X"0C",X"BE",X"23",X"DA",X"48",X"13",X"EB",X"C9",
+		X"1F",X"1F",X"1F",X"1F",X"E6",X"0F",X"C2",X"5B",X"13",X"3E",X"01",X"77",X"23",X"F5",X"E5",X"46",
+		X"71",X"CD",X"7A",X"13",X"E1",X"F1",X"11",X"08",X"00",X"42",X"19",X"71",X"FE",X"0B",X"FA",X"73",
+		X"13",X"0E",X"05",X"2B",X"7E",X"A7",X"C0",X"36",X"08",X"C9",X"21",X"2C",X"1A",X"78",X"BE",X"C2",
+		X"8F",X"13",X"23",X"79",X"BE",X"C2",X"90",X"13",X"1A",X"2A",X"50",X"20",X"86",X"77",X"C9",X"23",
+		X"23",X"13",X"7D",X"FE",X"06",X"C2",X"7D",X"13",X"C9",X"09",X"09",X"5E",X"23",X"56",X"EB",X"C9",
+		X"3A",X"43",X"20",X"A7",X"C0",X"21",X"91",X"20",X"CD",X"BD",X"13",X"21",X"9C",X"20",X"CD",X"BD",
+		X"13",X"21",X"A7",X"20",X"CD",X"F0",X"13",X"21",X"B2",X"20",X"C3",X"F0",X"13",X"7E",X"A7",X"F0",
+		X"CD",X"95",X"14",X"C8",X"CD",X"6C",X"14",X"FE",X"07",X"F8",X"CD",X"5A",X"14",X"FE",X"0A",X"F8",
+		X"D6",X"09",X"21",X"90",X"19",X"FE",X"04",X"FA",X"A0",X"14",X"21",X"6E",X"20",X"3E",X"30",X"77",
+		X"32",X"5C",X"20",X"23",X"7E",X"FE",X"DE",X"DA",X"EC",X"13",X"36",X"DE",X"AF",X"C3",X"1F",X"14",
+		X"7E",X"A7",X"F0",X"CD",X"95",X"14",X"C8",X"CD",X"6C",X"14",X"FE",X"0A",X"F0",X"CD",X"5A",X"14",
+		X"FE",X"07",X"F0",X"D6",X"03",X"FE",X"01",X"21",X"8A",X"19",X"F2",X"A0",X"14",X"21",X"5C",X"20",
+		X"3E",X"30",X"77",X"32",X"6E",X"20",X"23",X"7E",X"FE",X"30",X"DA",X"1F",X"14",X"36",X"30",X"32",
+		X"55",X"20",X"AF",X"32",X"25",X"20",X"32",X"27",X"20",X"32",X"28",X"20",X"32",X"57",X"20",X"32",
+		X"58",X"20",X"32",X"22",X"20",X"3C",X"32",X"49",X"20",X"32",X"45",X"20",X"32",X"24",X"20",X"32",
+		X"43",X"20",X"3A",X"0A",X"20",X"A7",X"C8",X"3E",X"04",X"32",X"26",X"20",X"3A",X"55",X"20",X"A7",
+		X"3E",X"48",X"CA",X"57",X"14",X"3E",X"88",X"D3",X"03",X"C9",X"7E",X"E6",X"BF",X"77",X"11",X"07",
+		X"00",X"19",X"AF",X"77",X"23",X"77",X"23",X"77",X"23",X"77",X"78",X"C9",X"E5",X"23",X"23",X"7E",
+		X"E5",X"21",X"81",X"19",X"06",X"01",X"04",X"04",X"04",X"BE",X"23",X"D2",X"76",X"14",X"E1",X"23",
+		X"23",X"7E",X"21",X"85",X"19",X"11",X"88",X"19",X"05",X"13",X"23",X"BE",X"DA",X"88",X"14",X"EB",
+		X"96",X"4F",X"78",X"E1",X"C9",X"E5",X"11",X"07",X"00",X"19",X"7E",X"23",X"23",X"B6",X"E1",X"C9",
+		X"23",X"23",X"3D",X"C2",X"A0",X"14",X"5E",X"23",X"56",X"2E",X"01",X"61",X"EB",X"C3",X"F6",X"10",
+		X"21",X"86",X"20",X"11",X"0B",X"00",X"19",X"E5",X"CD",X"C3",X"14",X"E1",X"7D",X"FE",X"B2",X"C2",
+		X"B3",X"14",X"C9",X"7E",X"A7",X"F0",X"23",X"23",X"7E",X"FE",X"08",X"DA",X"E4",X"14",X"FE",X"F8",
+		X"D2",X"E4",X"14",X"23",X"23",X"7E",X"FE",X"10",X"DA",X"DE",X"14",X"FE",X"CC",X"D8",X"2B",X"7E",
+		X"2F",X"3C",X"77",X"C9",X"2B",X"2B",X"7E",X"E6",X"BF",X"77",X"C9",X"21",X"6D",X"20",X"11",X"0D",
+		X"20",X"CD",X"FA",X"14",X"21",X"5B",X"20",X"11",X"0E",X"20",X"7E",X"A7",X"F0",X"E6",X"01",X"C8",
+		X"23",X"23",X"23",X"7E",X"FE",X"17",X"D0",X"AF",X"32",X"45",X"20",X"2B",X"2B",X"7E",X"E6",X"0F",
+		X"F6",X"E0",X"77",X"2B",X"7E",X"E6",X"FE",X"77",X"3E",X"02",X"32",X"22",X"20",X"3A",X"0A",X"20",
+		X"A7",X"C8",X"1A",X"3C",X"27",X"12",X"C3",X"24",X"1C",X"3A",X"09",X"20",X"D6",X"05",X"F8",X"C2",
+		X"2C",X"15",X"2A",X"4C",X"20",X"7D",X"FE",X"20",X"D2",X"3E",X"15",X"21",X"23",X"1A",X"46",X"2B",
+		X"22",X"4C",X"20",X"3A",X"5C",X"20",X"E6",X"0F",X"CA",X"4F",X"15",X"78",X"32",X"67",X"20",X"3A",
+		X"6E",X"20",X"E6",X"0F",X"C8",X"78",X"32",X"79",X"20",X"C9",X"3A",X"57",X"20",X"A7",X"CA",X"70",
+		X"15",X"DB",X"00",X"47",X"DB",X"00",X"21",X"20",X"20",X"11",X"B0",X"19",X"B8",X"CC",X"82",X"15",
+		X"3A",X"58",X"20",X"A7",X"C8",X"DB",X"01",X"47",X"DB",X"01",X"21",X"21",X"20",X"11",X"C0",X"19",
+		X"B8",X"C0",X"E5",X"2F",X"F5",X"0F",X"0F",X"0F",X"0F",X"E6",X"07",X"4F",X"06",X"00",X"21",X"B4",
+		X"15",X"09",X"F1",X"E6",X"8F",X"B6",X"E1",X"AE",X"C8",X"4F",X"06",X"01",X"79",X"0F",X"DA",X"AA",
+		X"15",X"4F",X"78",X"07",X"47",X"13",X"13",X"C3",X"9C",X"15",X"78",X"AE",X"77",X"A0",X"EB",X"4E",
+		X"23",X"66",X"69",X"E9",X"30",X"70",X"40",X"50",X"20",X"50",X"60",X"10",X"21",X"5B",X"20",X"11",
+		X"20",X"20",X"C3",X"CB",X"15",X"21",X"6D",X"20",X"11",X"21",X"20",X"7E",X"F6",X"02",X"77",X"1A",
+		X"E6",X"7F",X"23",X"77",X"C9",X"C8",X"21",X"91",X"20",X"7E",X"A7",X"F2",X"E4",X"15",X"21",X"9C",
+		X"20",X"7E",X"A7",X"F8",X"11",X"59",X"20",X"1A",X"FE",X"07",X"F0",X"D5",X"3C",X"12",X"11",X"04",
+		X"00",X"19",X"E5",X"21",X"28",X"1E",X"11",X"A2",X"3E",X"CD",X"30",X"01",X"21",X"5F",X"20",X"5E",
+		X"16",X"00",X"2B",X"E5",X"21",X"CC",X"19",X"06",X"18",X"3A",X"0A",X"20",X"A7",X"CA",X"18",X"16",
+		X"78",X"D3",X"03",X"3E",X"04",X"32",X"26",X"20",X"19",X"19",X"19",X"19",X"5E",X"23",X"56",X"23",
+		X"4E",X"23",X"46",X"E1",X"7E",X"80",X"47",X"2B",X"7E",X"81",X"4F",X"E1",X"70",X"2B",X"72",X"2B",
+		X"71",X"2B",X"73",X"2B",X"36",X"C0",X"D1",X"1A",X"FE",X"06",X"C0",X"3C",X"12",X"13",X"7B",X"FE",
+		X"5A",X"CA",X"46",X"16",X"1B",X"1B",X"06",X"0A",X"3A",X"11",X"20",X"A7",X"CA",X"51",X"16",X"06",
+		X"05",X"1A",X"FE",X"06",X"FA",X"59",X"16",X"06",X"02",X"78",X"32",X"25",X"20",X"32",X"4A",X"20",
+		X"C9",X"C8",X"21",X"A7",X"20",X"7E",X"A7",X"F2",X"70",X"16",X"21",X"B2",X"20",X"7E",X"A7",X"F8",
+		X"11",X"5A",X"20",X"1A",X"FE",X"07",X"F0",X"D5",X"3C",X"12",X"11",X"04",X"00",X"19",X"E5",X"21",
+		X"28",X"1E",X"11",X"B8",X"3E",X"CD",X"30",X"01",X"21",X"71",X"20",X"5E",X"16",X"00",X"2B",X"E5",
+		X"21",X"E8",X"19",X"06",X"28",X"C3",X"09",X"16",X"21",X"0C",X"20",X"DB",X"02",X"2F",X"47",X"DB",
+		X"02",X"2F",X"B8",X"C0",X"E6",X"40",X"47",X"AE",X"C8",X"70",X"78",X"A7",X"C8",X"3E",X"0C",X"D3",
+		X"03",X"01",X"64",X"00",X"D3",X"04",X"05",X"C2",X"B4",X"16",X"0D",X"C2",X"B4",X"16",X"3E",X"08",
+		X"D3",X"03",X"21",X"12",X"20",X"34",X"21",X"BA",X"1D",X"CD",X"87",X"1C",X"3A",X"0A",X"20",X"A7",
+		X"C0",X"21",X"E7",X"1A",X"22",X"06",X"20",X"31",X"00",X"24",X"C3",X"7E",X"0F",X"3A",X"44",X"20",
+		X"A7",X"C8",X"11",X"08",X"20",X"01",X"29",X"20",X"CD",X"44",X"1C",X"21",X"29",X"20",X"11",X"0F",
+		X"24",X"3E",X"02",X"C3",X"30",X"01",X"21",X"7F",X"20",X"7E",X"A7",X"F0",X"23",X"23",X"23",X"7E",
+		X"FE",X"17",X"D2",X"08",X"17",X"3E",X"B6",X"77",X"EB",X"21",X"72",X"19",X"01",X"77",X"19",X"23",
+		X"03",X"BE",X"DA",X"0F",X"17",X"EB",X"0A",X"2B",X"77",X"C9",X"21",X"4B",X"20",X"7E",X"A7",X"C8",
+		X"36",X"00",X"1F",X"F5",X"DC",X"54",X"17",X"F1",X"1F",X"F5",X"DC",X"A8",X"17",X"F1",X"1F",X"F5",
+		X"DC",X"4F",X"17",X"F1",X"1F",X"F5",X"DC",X"49",X"18",X"F1",X"1F",X"F5",X"DC",X"8A",X"18",X"F1",
+		X"1F",X"DC",X"1B",X"19",X"1F",X"F5",X"DC",X"10",X"19",X"F1",X"1F",X"DC",X"23",X"19",X"C9",X"3E",
+		X"08",X"D3",X"03",X"C9",X"21",X"13",X"20",X"06",X"08",X"7E",X"07",X"07",X"07",X"AE",X"17",X"17",
+		X"21",X"13",X"20",X"7E",X"17",X"77",X"23",X"7E",X"17",X"77",X"05",X"C2",X"59",X"17",X"F6",X"02",
+		X"E6",X"1F",X"32",X"28",X"20",X"E6",X"07",X"4F",X"06",X"00",X"21",X"74",X"1A",X"09",X"46",X"21",
+		X"5E",X"20",X"7E",X"FE",X"A0",X"DA",X"8A",X"17",X"06",X"01",X"FE",X"18",X"D2",X"91",X"17",X"06",
+		X"02",X"2B",X"7E",X"FE",X"38",X"DA",X"9A",X"17",X"06",X"04",X"FE",X"10",X"D2",X"A1",X"17",X"06",
+		X"08",X"2B",X"7E",X"E6",X"F0",X"B0",X"77",X"C9",X"3A",X"09",X"20",X"F6",X"20",X"32",X"27",X"20",
+		X"AF",X"CD",X"C2",X"17",X"32",X"5F",X"20",X"21",X"5C",X"20",X"7E",X"E6",X"0F",X"B0",X"77",X"C3",
+		X"D5",X"15",X"F5",X"21",X"5D",X"20",X"4E",X"23",X"5E",X"21",X"6F",X"20",X"46",X"23",X"56",X"CD",
+		X"EF",X"17",X"C6",X"14",X"21",X"7A",X"1A",X"23",X"23",X"BE",X"23",X"DA",X"D7",X"17",X"F1",X"A7",
+		X"CA",X"E4",X"17",X"23",X"7E",X"4F",X"17",X"17",X"17",X"17",X"E6",X"F0",X"47",X"79",X"C9",X"7A",
+		X"93",X"C8",X"5F",X"9F",X"57",X"21",X"00",X"00",X"3E",X"06",X"19",X"3D",X"C2",X"FA",X"17",X"7C");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romg.vhd
new file mode 100644
index 00000000..1c8074d2
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romg.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity romg is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of romg is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"D8",X"00",X"F8",X"00",X"FE",X"03",X"B8",X"00",X"F8",X"01",X"F8",X"00",X"60",X"00",X"F0",
+		X"00",X"FC",X"07",X"FE",X"7F",X"FF",X"00",X"F9",X"00",X"F9",X"00",X"F9",X"00",X"FE",X"01",X"FE",
+		X"01",X"02",X"11",X"50",X"00",X"D8",X"00",X"F8",X"00",X"FE",X"03",X"B8",X"00",X"F8",X"01",X"F8",
+		X"00",X"60",X"00",X"F0",X"E0",X"FC",X"3F",X"FE",X"03",X"FF",X"00",X"F9",X"00",X"F9",X"00",X"F9",
+		X"00",X"FE",X"01",X"FE",X"01",X"02",X"11",X"50",X"00",X"D8",X"00",X"F8",X"00",X"FE",X"03",X"B8",
+		X"00",X"F8",X"01",X"F8",X"00",X"60",X"00",X"F0",X"70",X"FC",X"1F",X"FE",X"07",X"FF",X"00",X"F9",
+		X"00",X"F9",X"00",X"F9",X"00",X"FE",X"01",X"FE",X"01",X"02",X"11",X"50",X"00",X"D8",X"00",X"F8",
+		X"00",X"FE",X"03",X"B8",X"00",X"F8",X"01",X"F8",X"00",X"60",X"E0",X"F0",X"1C",X"FC",X"07",X"FE",
+		X"03",X"FF",X"00",X"F9",X"00",X"F9",X"00",X"F9",X"00",X"FE",X"01",X"FE",X"01",X"02",X"11",X"50",
+		X"00",X"D8",X"00",X"F8",X"00",X"FE",X"03",X"B8",X"40",X"F8",X"61",X"F8",X"30",X"60",X"18",X"F0",
+		X"0C",X"FC",X"07",X"FE",X"03",X"FF",X"00",X"F9",X"00",X"F9",X"00",X"F9",X"00",X"FE",X"01",X"FE",
+		X"01",X"02",X"09",X"FC",X"01",X"F8",X"03",X"98",X"03",X"18",X"07",X"1C",X"07",X"8E",X"03",X"86",
+		X"01",X"C7",X"01",X"9E",X"07",X"02",X"09",X"FC",X"01",X"F8",X"01",X"F8",X"01",X"F0",X"01",X"E0",
+		X"01",X"E0",X"00",X"C0",X"00",X"E0",X"00",X"C0",X"03",X"02",X"09",X"FC",X"00",X"F8",X"01",X"F0",
+		X"03",X"C8",X"07",X"9C",X"07",X"0E",X"03",X"06",X"03",X"87",X"03",X"3E",X"0F",X"02",X"0F",X"28",
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+		X"77",X"7D",X"FE",X"B2",X"C2",X"BA",X"0F",X"C9",X"7E",X"A7",X"F0",X"23",X"7E",X"23",X"86",X"77",
+		X"23",X"7E",X"23",X"86",X"77",X"C9",X"21",X"4B",X"20",X"7E",X"A7",X"C0",X"47",X"21",X"09",X"20",
+		X"35",X"C2",X"14",X"10",X"36",X"1E",X"3A",X"45",X"20",X"A7",X"C2",X"0E",X"10",X"21",X"08",X"20");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romh.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romh.vhd
new file mode 100644
index 00000000..d1853f40
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romh.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity romh is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of romh is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"00",X"AF",X"D3",X"03",X"C3",X"17",X"00",X"F5",X"C5",X"D5",X"E5",X"C3",X"9A",X"0E",X"00",
+		X"F5",X"C5",X"D5",X"E5",X"C3",X"B0",X"0E",X"DB",X"02",X"E6",X"10",X"CA",X"62",X"0F",X"06",X"01",
+		X"11",X"00",X"00",X"21",X"00",X"20",X"D3",X"04",X"70",X"7E",X"A8",X"CA",X"3D",X"00",X"4F",X"7D",
+		X"E6",X"01",X"79",X"C2",X"3B",X"00",X"B2",X"57",X"C3",X"3D",X"00",X"B3",X"5F",X"23",X"7C",X"FE",
+		X"40",X"C2",X"26",X"00",X"D3",X"04",X"2B",X"7C",X"FE",X"1F",X"CA",X"7A",X"00",X"7E",X"A8",X"CA",
+		X"61",X"00",X"4F",X"7D",X"E6",X"01",X"79",X"C2",X"5F",X"00",X"B2",X"57",X"C3",X"61",X"00",X"B3",
+		X"5F",X"78",X"2F",X"77",X"AE",X"CA",X"44",X"00",X"4F",X"7D",X"E6",X"01",X"79",X"C2",X"75",X"00",
+		X"B2",X"57",X"C3",X"77",X"00",X"B3",X"5F",X"C3",X"44",X"00",X"D3",X"04",X"23",X"7C",X"FE",X"40",
+		X"CA",X"9D",X"00",X"78",X"2F",X"AE",X"CA",X"98",X"00",X"4F",X"7D",X"E6",X"01",X"79",X"C2",X"96",
+		X"00",X"B2",X"57",X"C3",X"98",X"00",X"B3",X"5F",X"AF",X"77",X"C3",X"7A",X"00",X"78",X"07",X"47",
+		X"D2",X"23",X"00",X"7A",X"B3",X"CA",X"CC",X"00",X"EB",X"F9",X"11",X"00",X"20",X"06",X"00",X"21",
+		X"00",X"00",X"39",X"0E",X"10",X"AF",X"29",X"DA",X"BB",X"00",X"2F",X"12",X"13",X"3E",X"08",X"12",
+		X"13",X"0D",X"C2",X"B5",X"00",X"05",X"C2",X"AF",X"00",X"C3",X"1A",X"01",X"31",X"00",X"24",X"21",
+		X"00",X"00",X"11",X"00",X"00",X"0E",X"04",X"AF",X"86",X"D3",X"04",X"23",X"47",X"79",X"BC",X"78",
+		X"C2",X"D8",X"00",X"E5",X"21",X"1F",X"01",X"19",X"BE",X"3E",X"40",X"CA",X"F7",X"00",X"21",X"00",
+		X"20",X"34",X"21",X"28",X"01",X"19",X"7E",X"21",X"29",X"20",X"19",X"77",X"E1",X"13",X"0C",X"0C",
+		X"0C",X"0C",X"3E",X"24",X"B9",X"C2",X"D7",X"00",X"21",X"29",X"20",X"3A",X"00",X"20",X"A7",X"CA",
+		X"00",X"00",X"11",X"08",X"30",X"3E",X"08",X"CD",X"30",X"01",X"D3",X"04",X"C3",X"1A",X"01",X"00",
+		X"CA",X"40",X"19",X"47",X"E8",X"B8",X"00",X"BC",X"48",X"48",X"47",X"47",X"46",X"46",X"45",X"44",
+		X"F5",X"7E",X"23",X"A7",X"FA",X"31",X"01",X"D6",X"30",X"F2",X"4D",X"01",X"47",X"13",X"7B",X"E6",
+		X"1F",X"C2",X"46",X"01",X"14",X"14",X"04",X"C2",X"3D",X"01",X"C3",X"31",X"01",X"E5",X"D5",X"3C",
+		X"FE",X"0B",X"FA",X"57",X"01",X"D6",X"06",X"21",X"71",X"01",X"01",X"0A",X"00",X"09",X"3D",X"C2",
+		X"5D",X"01",X"EB",X"01",X"20",X"00",X"3E",X"0A",X"F5",X"1A",X"13",X"77",X"09",X"F1",X"3D",X"C2",
+		X"68",X"01",X"D1",X"E1",X"13",X"F1",X"3D",X"C2",X"30",X"01",X"C9",X"3C",X"7E",X"66",X"66",X"66",
+		X"66",X"66",X"66",X"7E",X"3C",X"18",X"1C",X"18",X"18",X"18",X"18",X"18",X"18",X"3C",X"3C",X"3C",
+		X"7E",X"66",X"60",X"7C",X"3E",X"06",X"06",X"7E",X"7E",X"3C",X"7E",X"66",X"60",X"38",X"78",X"60",
+		X"66",X"7E",X"3C",X"66",X"66",X"66",X"66",X"7E",X"7E",X"60",X"60",X"60",X"60",X"3E",X"3E",X"06",
+		X"06",X"3E",X"7E",X"60",X"66",X"7E",X"3C",X"3C",X"3E",X"06",X"06",X"3E",X"7E",X"66",X"66",X"7E",
+		X"3C",X"7E",X"7E",X"60",X"70",X"30",X"38",X"18",X"1C",X"0C",X"0C",X"3C",X"7E",X"66",X"66",X"3C",
+		X"7E",X"66",X"66",X"7E",X"3C",X"3C",X"7E",X"66",X"66",X"7E",X"7C",X"60",X"60",X"7C",X"3C",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"18",X"3C",X"7E",X"66",X"66",X"66",X"7E",
+		X"7E",X"66",X"66",X"3E",X"7E",X"66",X"66",X"3E",X"7E",X"66",X"66",X"7E",X"3E",X"3C",X"7E",X"66",
+		X"06",X"06",X"06",X"06",X"66",X"7E",X"3C",X"3E",X"7E",X"66",X"66",X"66",X"66",X"66",X"66",X"7E",
+		X"3E",X"7E",X"7E",X"06",X"06",X"3E",X"3E",X"06",X"06",X"7E",X"7E",X"7E",X"7E",X"06",X"06",X"3E",
+		X"3E",X"06",X"06",X"06",X"06",X"3C",X"7E",X"66",X"06",X"06",X"76",X"76",X"66",X"7E",X"3C",X"66",
+		X"66",X"66",X"66",X"7E",X"7E",X"66",X"66",X"66",X"66",X"3C",X"3C",X"18",X"18",X"18",X"18",X"18",
+		X"18",X"3C",X"3C",X"60",X"60",X"60",X"60",X"60",X"60",X"60",X"66",X"7E",X"3C",X"66",X"66",X"76",
+		X"3E",X"1E",X"1E",X"3E",X"76",X"66",X"66",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"7E",
+		X"7E",X"C3",X"C3",X"E7",X"E7",X"FF",X"FF",X"DB",X"C3",X"C3",X"C3",X"66",X"66",X"6E",X"6E",X"7E",
+		X"7E",X"76",X"76",X"66",X"66",X"3C",X"7E",X"66",X"66",X"66",X"66",X"66",X"66",X"7E",X"3C",X"3E",
+		X"7E",X"66",X"66",X"7E",X"3E",X"06",X"06",X"06",X"06",X"3C",X"7E",X"66",X"66",X"66",X"66",X"66",
+		X"66",X"7E",X"5C",X"3E",X"7E",X"66",X"66",X"7E",X"3E",X"76",X"66",X"66",X"66",X"3C",X"7E",X"66",
+		X"06",X"3E",X"7C",X"60",X"66",X"7E",X"3C",X"7E",X"7E",X"18",X"18",X"18",X"18",X"18",X"18",X"18",
+		X"18",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"7E",X"3C",X"66",X"66",X"66",X"66",X"66",
+		X"7E",X"3C",X"3C",X"18",X"18",X"C3",X"C3",X"C3",X"DB",X"FF",X"FF",X"E7",X"E7",X"C3",X"C3",X"66",
+		X"66",X"7E",X"3C",X"18",X"18",X"3C",X"7E",X"66",X"66",X"66",X"66",X"7E",X"3C",X"18",X"18",X"18",
+		X"18",X"18",X"18",X"7E",X"7E",X"60",X"70",X"38",X"1C",X"0E",X"06",X"7E",X"7E",X"C0",X"C0",X"C0",
+		X"C0",X"C0",X"C0",X"00",X"00",X"C0",X"C0",X"10",X"38",X"38",X"38",X"38",X"38",X"38",X"38",X"38",
+		X"7C",X"47",X"03",X"51",X"03",X"79",X"03",X"6F",X"03",X"8D",X"03",X"5B",X"03",X"83",X"03",X"65",
+		X"03",X"97",X"03",X"A1",X"03",X"AB",X"03",X"29",X"03",X"33",X"03",X"3D",X"03",X"1F",X"03",X"89",
+		X"0E",X"89",X"0E",X"89",X"0E",X"89",X"0E",X"89",X"0E",X"81",X"0D",X"81",X"0D",X"81",X"0D",X"81",
+		X"0D",X"81",X"0D",X"2B",X"0C",X"2B",X"0C",X"8D",X"0C",X"8D",X"0C",X"C1",X"0C",X"E9",X"0C",X"17",
+		X"0D",X"3D",X"0D",X"57",X"0D",X"71",X"0D",X"28",X"0B",X"7E",X"0B",X"CB",X"0B",X"F3",X"0B",X"13",
+		X"0C",X"C1",X"03",X"D6",X"05",X"B5",X"07",X"ED",X"08",X"FD",X"09",X"02",X"04",X"11",X"06",X"D9",
+		X"07",X"0D",X"09",X"1B",X"0A",X"43",X"04",X"4C",X"06",X"FD",X"07",X"2D",X"09",X"39",X"0A",X"84",
+		X"04",X"87",X"06",X"21",X"08",X"4D",X"09",X"57",X"0A",X"C5",X"04",X"C2",X"06",X"45",X"08",X"6D",
+		X"09",X"75",X"0A",X"06",X"05",X"FD",X"06",X"69",X"08",X"8D",X"09",X"93",X"0A",X"47",X"05",X"38",
+		X"07",X"8D",X"08",X"AD",X"09",X"B1",X"0A",X"88",X"05",X"73",X"07",X"B1",X"08",X"CD",X"09",X"CF",
+		X"0A",X"A2",X"05",X"89",X"07",X"C5",X"08",X"DD",X"09",X"D6",X"0A",X"BC",X"05",X"9F",X"07",X"D9",
+		X"08",X"ED",X"09",X"DD",X"0A",X"CD",X"09",X"DD",X"09",X"ED",X"09",X"CF",X"0A",X"D6",X"0A",X"DD",
+		X"0A",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",X"00",X"80",X"0F",X"00",X"C8",
+		X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",X"C0",X"7F",X"00",X"C0",X"1F",
+		X"00",X"80",X"1F",X"00",X"00",X"07",X"00",X"80",X"0F",X"00",X"F8",X"3F",X"00",X"FC",X"7F",X"00",
+		X"CE",X"FF",X"01",X"C6",X"FF",X"03",X"C6",X"1F",X"17",X"C6",X"1F",X"0E",X"C6",X"1F",X"14",X"FA",
+		X"3F",X"20",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",X"00",X"80",X"0F",X"00",
+		X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",X"C0",X"7F",X"00",X"C0",
+		X"1F",X"00",X"80",X"1F",X"00",X"00",X"07",X"00",X"80",X"0F",X"00",X"F8",X"3F",X"00",X"FC",X"7F",
+		X"00",X"CE",X"FF",X"01",X"C6",X"FF",X"07",X"C6",X"1F",X"1E",X"C6",X"1F",X"70",X"C6",X"1F",X"00",
+		X"FA",X"3F",X"00",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",X"00",X"80",X"0F",
+		X"00",X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",X"C0",X"7F",X"00",
+		X"C0",X"1F",X"00",X"80",X"1F",X"00",X"00",X"07",X"00",X"80",X"0F",X"00",X"F8",X"3F",X"00",X"FC",
+		X"FF",X"01",X"CE",X"FF",X"0F",X"C6",X"1F",X"7F",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6",X"1F",
+		X"00",X"FA",X"3F",X"00",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",X"00",X"80",
+		X"0F",X"00",X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",X"C0",X"7F",
+		X"00",X"C0",X"1F",X"00",X"80",X"1F",X"00",X"00",X"07",X"08",X"80",X"0F",X"F0",X"F8",X"FF",X"1F",
+		X"FC",X"FF",X"0F",X"CE",X"FF",X"00",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6",
+		X"1F",X"00",X"FA",X"3F",X"00",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",X"00",
+		X"80",X"0F",X"00",X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",X"C0",
+		X"7F",X"00",X"C0",X"1F",X"00",X"80",X"1F",X"C0",X"00",X"07",X"38",X"80",X"0F",X"0C",X"F8",X"FF",
+		X"0F",X"FC",X"FF",X"03",X"CE",X"FF",X"00",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6",X"1F",X"00",
+		X"C6",X"1F",X"00",X"FA",X"3F",X"00",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",
+		X"00",X"80",X"0F",X"00",X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",
+		X"C0",X"7F",X"00",X"C0",X"1F",X"C0",X"80",X"1F",X"70",X"00",X"07",X"3C",X"80",X"0F",X"0F",X"F8",
+		X"FF",X"03",X"FC",X"FF",X"01",X"CE",X"FF",X"00",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6",X"1F",
+		X"00",X"C6",X"1F",X"00",X"FA",X"3F",X"00",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",
+		X"0D",X"00",X"80",X"0F",X"00",X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"80",X"C0",X"3F",
+		X"50",X"C0",X"7F",X"60",X"C0",X"1F",X"30",X"80",X"1F",X"38",X"00",X"07",X"1C",X"80",X"0F",X"0E",
+		X"F8",X"FF",X"07",X"FC",X"FF",X"03",X"CE",X"FF",X"01",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6",
+		X"1F",X"00",X"C6",X"1F",X"00",X"FA",X"3F",X"00",X"02",X"0C",X"F0",X"3F",X"F0",X"3F",X"E0",X"3D",
+		X"C0",X"79",X"C0",X"71",X"C0",X"E1",X"C0",X"E1",X"E0",X"60",X"70",X"70",X"34",X"34",X"38",X"38",
+		X"F0",X"F0",X"02",X"0C",X"F0",X"3F",X"E0",X"3F",X"C0",X"1F",X"C0",X"1F",X"C0",X"1F",X"00",X"1F",
+		X"00",X"1E",X"00",X"1C",X"00",X"0C",X"00",X"0D",X"00",X"0E",X"00",X"3C",X"02",X"0C",X"F0",X"3F",
+		X"F0",X"3F",X"E0",X"1F",X"C0",X"0F",X"80",X"1F",X"00",X"3E",X"C0",X"7D",X"E0",X"78",X"70",X"30",
+		X"34",X"34",X"38",X"38",X"F0",X"F0",X"03",X"13",X"40",X"01",X"00",X"60",X"03",X"00",X"E0",X"03",
+		X"00",X"F4",X"17",X"00",X"FC",X"1F",X"00",X"E0",X"02",X"00",X"E0",X"0F",X"00",X"E0",X"03",X"00",
+		X"E0",X"03",X"00",X"C0",X"01",X"00",X"E0",X"03",X"00",X"FC",X"0F",X"00",X"FE",X"3F",X"00",X"F3",
+		X"7F",X"00",X"F3",X"E3",X"02",X"F3",X"C3",X"01",X"F1",X"83",X"02",X"FE",X"03",X"04",X"FC",X"07",
+		X"00",X"03",X"13",X"40",X"01",X"00",X"60",X"03",X"00",X"E0",X"03",X"00",X"F4",X"17",X"00",X"FC",
+		X"1F",X"00",X"E0",X"02",X"00",X"E0",X"0F",X"00",X"E0",X"03",X"00",X"E0",X"03",X"00",X"C0",X"01",
+		X"00",X"E0",X"03",X"00",X"FC",X"0F",X"00",X"FE",X"1F",X"00",X"F3",X"7F",X"00",X"F3",X"E3",X"01",
+		X"F3",X"03",X"07",X"F1",X"03",X"00",X"FE",X"03",X"00",X"FC",X"07",X"00",X"03",X"13",X"40",X"01",
+		X"00",X"60",X"03",X"00",X"E0",X"03",X"00",X"F4",X"17",X"00",X"FC",X"1F",X"00",X"E0",X"02",X"00",
+		X"E0",X"0F",X"00",X"E0",X"03",X"00",X"E0",X"03",X"00",X"C0",X"01",X"00",X"E0",X"03",X"00",X"FC",
+		X"1F",X"00",X"FE",X"FF",X"00",X"F3",X"FF",X"07",X"F3",X"03",X"00",X"F3",X"03",X"00",X"F1",X"03",
+		X"00",X"FE",X"03",X"00",X"FC",X"07",X"00",X"03",X"13",X"40",X"01",X"00",X"60",X"03",X"00",X"E0",
+		X"03",X"00",X"F4",X"17",X"00",X"FC",X"1F",X"00",X"E0",X"02",X"00",X"E0",X"0F",X"00",X"E0",X"03",
+		X"00",X"E0",X"03",X"00",X"C0",X"01",X"01",X"E0",X"03",X"1E",X"FC",X"FF",X"03",X"FE",X"FF",X"03",
+		X"F3",X"0F",X"00",X"F3",X"03",X"00",X"F3",X"03",X"00",X"F1",X"03",X"00",X"FE",X"03",X"00",X"FC",
+		X"07",X"00",X"03",X"13",X"40",X"01",X"00",X"60",X"03",X"00",X"E0",X"03",X"00",X"F4",X"17",X"00",
+		X"FC",X"1F",X"00",X"E0",X"02",X"00",X"E0",X"0F",X"00",X"E0",X"03",X"00",X"E0",X"03",X"0C",X"C0",
+		X"81",X"03",X"E0",X"C3",X"00",X"FC",X"FF",X"00",X"FE",X"3F",X"00",X"F3",X"0F",X"00",X"F3",X"03",
+		X"00",X"F3",X"03",X"00",X"F1",X"03",X"00",X"FE",X"03",X"00",X"FC",X"07",X"00",X"03",X"13",X"40",
+		X"01",X"00",X"60",X"03",X"00",X"E0",X"03",X"00",X"F4",X"17",X"00",X"FC",X"1F",X"00",X"E0",X"02",
+		X"00",X"E0",X"0F",X"00",X"E0",X"03",X"00",X"E0",X"03",X"06",X"C0",X"C1",X"03",X"E0",X"F3",X"00",
+		X"FC",X"3F",X"00",X"FE",X"1F",X"00",X"F3",X"0F",X"00",X"F3",X"03",X"00",X"F3",X"03",X"00",X"F1",
+		X"03",X"00",X"FE",X"03",X"00",X"FC",X"07",X"00",X"03",X"13",X"40",X"01",X"00",X"60",X"03",X"00",
+		X"E0",X"03",X"00",X"F4",X"17",X"00",X"FC",X"1F",X"00",X"E0",X"02",X"04",X"E0",X"8F",X"06",X"E0",
+		X"03",X"03",X"E0",X"83",X"03",X"C0",X"C1",X"01",X"E0",X"E3",X"00",X"FC",X"7F",X"00",X"FE",X"3F",
+		X"00",X"F3",X"1F",X"00",X"F3",X"03",X"00",X"F3",X"03",X"00",X"F1",X"03",X"00",X"FE",X"03",X"00",
+		X"FC",X"07",X"00",X"02",X"0A",X"F8",X"07",X"70",X"0F",X"70",X"0E",X"70",X"1C",X"30",X"1C",X"38",
+		X"0C",X"1C",X"0E",X"0C",X"06",X"0E",X"07",X"3C",X"1E",X"02",X"0A",X"FC",X"03",X"F8",X"03",X"F0",
+		X"03",X"F0",X"03",X"C0",X"03",X"C0",X"03",X"80",X"03",X"80",X"01",X"C0",X"01",X"80",X"07",X"02",
+		X"0A",X"FC",X"03",X"F8",X"01",X"F0",X"00",X"E0",X"01",X"C8",X"03",X"9C",X"07",X"0E",X"07",X"06",
+		X"03",X"87",X"03",X"1E",X"0F",X"02",X"11",X"50",X"00",X"D8",X"00",X"F8",X"00",X"FE",X"03",X"B8",
+		X"00",X"F8",X"01",X"F8",X"00",X"60",X"00",X"F0",X"00",X"FC",X"03",X"FE",X"07",X"FF",X"06",X"F9",
+		X"0C",X"F9",X"18",X"F9",X"20",X"FE",X"01",X"FE",X"01",X"02",X"11",X"50",X"00",X"D8",X"00",X"F8",
+		X"00",X"FE",X"03",X"B8",X"00",X"F8",X"01",X"F8",X"00",X"60",X"00",X"F0",X"00",X"FC",X"03",X"FE",
+		X"0F",X"FF",X"3C",X"F9",X"60",X"F9",X"00",X"F9",X"00",X"FE",X"01",X"FE",X"01",X"02",X"11",X"50");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qpf
new file mode 100644
index 00000000..e03e4c0b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 16:15:41  June 05, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:15:41  June 05, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "BowlingAlley"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qsf
new file mode 100644
index 00000000..872504f6
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qsf	
@@ -0,0 +1,171 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 13:13:10  June 05, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Invaders_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/BowlingAlley_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/BowlingAlley_memory.sv
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY BowlingAlley_mist
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ---------------------------
+# start ENTITY(Invaders_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(Invaders_mist)
+# -------------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.sdc
new file mode 100644
index 00000000..f91c127c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/README.txt
new file mode 100644
index 00000000..7f6452b7
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/README.txt	
@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: Bowling Alley port to MiST by Gehstock 
+-- 05 June 2019
+-- 
+---------------------------------------------------------------------------------
+-- 
+-- Midway 8080 Hardware
+-- Audio based on work by Paul Walsh.
+-- Audio and scan converter by MikeJ.
+---------------------------------------------------------------------------------
+-- 
+-- 
+-- Keyboard inputs :
+--
+--   F1          : Start
+--   SPACE       : Fire
+--   RIGHT/LEFT  : Movement
+--
+-- Joystick support.
+-- 
+-- 
+---------------------------------------------------------------------------------
+ToDo: Color Prom
+      Controls + DIP
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/Snapshot/BowlingAlley.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/Snapshot/BowlingAlley.rbf
new file mode 100644
index 0000000000000000000000000000000000000000..23ba85871cf31c3a3a5d296a6712db686cd6f2af
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fm<z$bSO;Au3=VWQ<-%;z&T-@3j~;!dZ{hy|cgj;6

literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/clean.bat
new file mode 100644
index 00000000..83fb0c47
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_memory.sv
new file mode 100644
index 00000000..57bd1c17
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_memory.sv	
@@ -0,0 +1,92 @@
+
+module BowlingAlley_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+wire [7:0]rom_data_4;
+
+
+sprom #(
+	.init_file("./roms/h.cpu.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_0)
+	);
+
+sprom #(
+	.init_file("./roms/g.cpu.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_1)
+	);
+	
+sprom #(
+	.init_file("./roms/f.cpu.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_2)
+	);
+	
+sprom #(
+	.init_file("./roms/e.cpu.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_e (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_3)
+	);
+
+sprom #(
+	.init_file("./roms/d.cpu.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_d (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_4)
+	);
+	
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4) begin
+	Rom_out = 8'b00000000;
+		case (Addr[15:11])
+			5'b00000 : Rom_out = rom_data_0;
+			5'b00001 : Rom_out = rom_data_1;
+			5'b00010 : Rom_out = rom_data_2;
+			5'b00011 : Rom_out = rom_data_3;
+			5'b01000 : Rom_out = rom_data_4;
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_mist.sv
new file mode 100644
index 00000000..a04fbd65
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_mist.sv	
@@ -0,0 +1,196 @@
+module BowlingAlley_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"Bow.Alley;;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_core, clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			Video;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(btn_one_player),
+	.Sel2Player(btn_two_players),
+	.Fire(m_fire),
+	.Fire2(m_bomb),
+	.MoveLeft(m_left),
+	.MoveRight(m_right),
+	.DIP("00000000"),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(hs),
+	.VSync(vs)
+	);
+		
+BowlingAlley_memory BowlingAlley_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_core),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);		
+	  
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({Video,Video,Video}),
+	.G({Video,Video,Video}),
+	.B({Video,Video,Video}),
+	.HSync(~hs),
+	.VSync(~vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.rotate({1'b1,status[2]}),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ce_divider(0),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_fire2 = 0;
+reg btn_fire3 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h14: btn_fire3       <= key_pressed; // ctrl
+			'h11: btn_fire2       <= key_pressed; // alt
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T8080se.vhd
new file mode 100644
index 00000000..65b92d54
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T8080se.vhd	
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..e09def1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..1c0f2638
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/dac.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/dac.vhd
new file mode 100644
index 00000000..db58d70b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/dac.vhd	
@@ -0,0 +1,48 @@
+-------------------------------------------------------------------------------
+--
+-- Delta-Sigma DAC
+--
+-- Refer to Xilinx Application Note XAPP154.
+--
+-- This DAC requires an external RC low-pass filter:
+--
+--   dac_o 0---XXXXX---+---0 analog audio
+--              3k3    |
+--                    === 4n7
+--                     |
+--                    GND
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.numeric_std.all;
+
+entity dac is
+	generic (
+		C_bits  : integer := 8
+	);
+	port (
+		clk_i   : in  std_logic;
+		res_n_i : in  std_logic;
+		dac_i   : in  std_logic_vector(C_bits-1 downto 0);
+		dac_o   : out std_logic
+	);
+end dac;
+
+architecture rtl of dac is
+	signal sig_in: unsigned(C_bits downto 0);
+begin
+	seq: process(clk_i, res_n_i)
+	begin
+		if res_n_i = '0' then
+			sig_in <= to_unsigned(2**C_bits, sig_in'length);
+			dac_o  <= '0';
+		elsif rising_edge(clk_i) then
+		        -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
+			--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
+			sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
+			dac_o  <= sig_in(C_bits);
+		end if;
+	end process seq;
+end rtl;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..0a4a7814
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders.vhd	
@@ -0,0 +1,283 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		Fire2           : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		DIP             : in  std_logic_vector(7 downto 0);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+	component mw8080
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+	end component;
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal GDB3         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: mw8080
+		port map(
+			Rst_n => Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				GDB3 when "11";
+--				S when others;
+				
+	GDB0(0) <= '0';  -- Language
+	GDB0(1) <= '0';  -- Language
+	GDB0(2) <= '0';  -- Demo_Sounds
+	GDB0(3) <= '0';  -- Game_Time 
+	GDB0(4) <= '0';  -- Coinage
+	GDB0(5) <= '0';  -- Difficulty
+	GDB0(6) <= '1';  -- Cabinet
+	GDB0(7) <= '1';  -- Unused
+
+	GDB1(0) <= not Coin;-- Active High !
+	GDB1(1) <= not Fire;
+	GDB1(2) <= not Sel1Player;
+	GDB1(3) <= not Fire2;
+	GDB1(4) <= '1';  --
+	GDB1(5) <= '1';  --
+	GDB1(6) <= '1';  --
+	GDB1(7) <= '1';  -- Unused ?
+
+	GDB2(0) <= '1';  -- TRACKBALL Y
+	GDB2(1) <= '1';  -- TRACKBALL Y
+	GDB2(2) <= '1';  -- TRACKBALL Y
+	GDB2(3) <= '1';  -- TRACKBALL Y
+	GDB2(4) <= '0';  -- TRACKBALL Y
+	GDB2(5) <= '0';  -- TRACKBALL Y
+	GDB2(6) <= '0';  -- TRACKBALL Y
+	GDB2(7) <= '0';  -- TRACKBALL Y
+	
+	GDB3(0) <= '1';  -- TRACKBALL X
+	GDB3(1) <= '1';  -- TRACKBALL X
+	GDB3(2) <= '1';  -- TRACKBALL X
+	GDB3(3) <= '1';  -- TRACKBALL X
+	GDB3(4) <= '0';  -- TRACKBALL X
+	GDB3(5) <= '0';  -- TRACKBALL X
+	GDB3(6) <= '0';  -- TRACKBALL X
+	GDB3(7) <= '0';  -- TRACKBALL X	
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..f16cf379
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..b9a88f96
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,336 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..f8d0b139
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.vhd	
@@ -0,0 +1,382 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 20,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/d.cpu.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/d.cpu.hex
new file mode 100644
index 00000000..3bf22e70
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/d.cpu.hex	
@@ -0,0 +1,129 @@
+:10000000C03AAC22B7CAA7402139222200223A19AD
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/e.cpu.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/e.cpu.hex
new file mode 100644
index 00000000..2d1a15fc
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/e.cpu.hex	
@@ -0,0 +1,129 @@
+:10000000CA051816043E09856F7EFEFECA3518B76C
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/f.cpu.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/f.cpu.hex
new file mode 100644
index 00000000..952f245b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/f.cpu.hex	
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/g.cpu.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/g.cpu.hex
new file mode 100644
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--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/g.cpu.hex	
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+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/h.cpu.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/h.cpu.hex
new file mode 100644
index 00000000..94b01ac2
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/h.cpu.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qpf
new file mode 100644
index 00000000..f68bb246
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:27:39  November 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:27:39  November 20, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "GunFight"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qsf
new file mode 100644
index 00000000..03524a57
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qsf	
@@ -0,0 +1,178 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 22:12:52  July 17, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		GunFight_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/GunFight_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/GunFight_memory.sv
+set_global_assignment -name VHDL_FILE rtl/GunFight_overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY GunFight_mist
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ---------------------------
+# start ENTITY(GunFight_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(GunFight_mist)
+# -------------------------
+
+# --------------------------------
+# start ENTITY(spaceinvaders_mist)
+
+# end ENTITY(spaceinvaders_mist)
+# ------------------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.sdc
new file mode 100644
index 00000000..f91c127c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/README GunFight.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Midway-Taito 8080 Hardware/README GunFight.txt
rename to Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/README.txt
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/clean.bat
new file mode 100644
index 00000000..83fb0c47
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_memory.sv
new file mode 100644
index 00000000..3e64a989
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_memory.sv	
@@ -0,0 +1,129 @@
+
+module GunFight_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+wire [7:0]rom_data_4;
+wire [7:0]rom_data_5;
+wire [7:0]rom_data_6;
+wire [7:0]rom_data_7;
+
+
+sprom #(
+	.init_file("./roms/gf-h.hex"),
+	.widthad_a(9),
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[8:0]),
+	.q(rom_data_0)
+	);
+
+sprom #(
+	.init_file("./roms/gf-g.hex"),
+	.widthad_a(9),
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[8:0]),
+	.q(rom_data_1)
+	);
+	
+sprom #(
+	.init_file("./roms/gf-f.hex"),
+	.widthad_a(9),
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[8:0]),
+	.q(rom_data_2)
+	);
+	
+sprom #(
+	.init_file("./roms/gf-e.hex"),
+	.widthad_a(9),
+	.width_a(8))
+u_rom_e (
+	.clock(Clock),
+	.Address(Addr[8:0]),
+	.q(rom_data_3)
+	);
+
+	sprom #(
+	.init_file("./roms/gf-d.hex"),
+	.widthad_a(9),
+	.width_a(8))
+u_rom_d (
+	.clock(Clock),
+	.Address(Addr[8:0]),
+	.q(rom_data_4)
+	);
+
+sprom #(
+	.init_file("./roms/gf-c.hex"),
+	.widthad_a(9),
+	.width_a(8))
+u_rom_c (
+	.clock(Clock),
+	.Address(Addr[8:0]),
+	.q(rom_data_5)
+	);
+	
+sprom #(
+	.init_file("./roms/gf-b.hex"),
+	.widthad_a(9),
+	.width_a(8))
+u_rom_b (
+	.clock(Clock),
+	.Address(Addr[8:0]),
+	.q(rom_data_6)
+	);
+	
+sprom #(
+	.init_file("./roms/gf-a.hex"),
+	.widthad_a(9),
+	.width_a(8))
+u_rom_a (
+	.clock(Clock),
+	.Address(Addr[8:0]),
+	.q(rom_data_7)
+	);
+	
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5, rom_data_6, rom_data_7) begin
+	Rom_out = 8'b00000000;
+		case (Addr[12:9])
+			4'b0000 : Rom_out = rom_data_0;
+			4'b0001 : Rom_out = rom_data_1;
+			4'b0010 : Rom_out = rom_data_2;
+			4'b0011 : Rom_out = rom_data_3;
+			
+			4'b0100 : Rom_out = rom_data_4;
+			4'b0101 : Rom_out = rom_data_5;
+			4'b0110 : Rom_out = rom_data_6;
+			4'b0111 : Rom_out = rom_data_7;
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_mist.sv
new file mode 100644
index 00000000..220eef32
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_mist.sv	
@@ -0,0 +1,197 @@
+module GunFight_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"Gun Fight;;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+//	"O5,Overlay, On, Off;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_sys),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(btn_one_player),
+	.Fire1(~joystick_0[4]),
+	.Fire2(~joystick_1[4]),
+	.GunUp1(gun1_up),
+	.GunDown1(gun1_dw),
+	.MoveLeft1(~joystick_0[1]),
+	.MoveRight1(~joystick_0[0]),
+	.MoveUp1(~joystick_0[3]),
+	.MoveDown1(~joystick_0[2]),
+	.GunUp2(gun2_up),
+	.GunDown2(gun2_dw),
+	.MoveLeft2(~joystick_1[1]),
+	.MoveRight2(~joystick_1[0]),
+	.MoveUp2(~joystick_1[3]),
+	.MoveDown2(~joystick_1[2]),
+//	.DIP(dip),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(hs),
+	.VSync(vs)
+	);
+		
+GunFight_memory GunFight_memory (
+	.Clock(clk_sys),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_sys),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({Video,Video,Video}),
+	.G({Video,Video,Video}),
+	.B(3'b000),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.scandoubler_disable(scandoublerD),
+	.ce_divider(1),
+	.scanlines(status[4:3]),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac #(
+	.c_bits(8))
+dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_coin  = 0;
+
+reg gun1_up  = 0;
+reg gun1_dw  = 0;
+reg gun2_up  = 0;
+reg gun2_dw  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h15: gun1_up       <= key_pressed; // Q
+			'h35: gun1_dw       <= key_pressed; // Y
+			'h75: gun2_up       <= key_pressed; // Arrow up
+			'h72: gun2_dw       <= key_pressed; // Arrow down
+		endcase
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_overlay.vhd
new file mode 100644
index 00000000..0bbba7ca
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_overlay.vhd	
@@ -0,0 +1,127 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+entity GunFight_overlay is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end GunFight_overlay;
+
+architecture rtl of GunFight_overlay is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_G1      : boolean;
+	signal Overlay_G2      : boolean;
+	signal Overlay_R1      : boolean;
+	signal Overlay_G1_VCnt : boolean;
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  Overlay_G1_VCnt <= false;
+	  Overlay_G1 <= false;
+	  Overlay_G2 <= false;
+	  Overlay_R1 <= false;
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt = x"1F") then
+		  Overlay_G1_VCnt <= true;
+		elsif (Vcnt = x"95") then
+		  Overlay_G1_VCnt <= false;
+		end if;
+	  end if;
+
+	  if (HCnt = x"027") and Overlay_G1_VCnt then
+		Overlay_G1 <= true;
+	  elsif (HCnt = x"046") then
+		Overlay_G1 <= false;
+	  end if;
+
+	  if (HCnt = x"046") then
+		Overlay_G2 <= true;
+	  elsif (HCnt = x"0B6") then
+		Overlay_G2 <= false;
+	  end if;
+
+	  if (HCnt = x"1A6") then
+		Overlay_R1 <= true;
+	  elsif (HCnt = x"1E6") then
+		Overlay_R1 <= false;
+	  end if;
+
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1)
+  begin
+	if (Video = '0') then
+	  VideoRGB  <= "000";
+	else
+	  if Overlay_G1 or Overlay_G2 then
+		VideoRGB  <= "010";
+	  elsif Overlay_R1 then
+		VideoRGB  <= "100";
+	  else
+		VideoRGB  <= "111";
+	  end if;
+	end if;
+  end process;
+
+
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_HSYNC   <= HSync;
+  O_VSYNC   <= VSync;
+
+
+end;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T8080se.vhd
new file mode 100644
index 00000000..65b92d54
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T8080se.vhd	
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..e09def1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..1c0f2638
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/gun.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/gun.sv
new file mode 100644
index 00000000..507462e5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/gun.sv	
@@ -0,0 +1,13 @@
+module gun(
+input	clk,
+input gun1up,
+input gun1dw,
+input gun2up,
+input gun2dw,
+output [2:0] gun1out,
+output [2:0] gun2out
+);
+
+//0x06, 0x02, 0x00, 0x04, 0x05, 0x01, 0x03
+wire [6:0]gun[6:0]gun = ()
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..e29e4774
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders.vhd	
@@ -0,0 +1,307 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.NUMERIC_STD.ALL;
+
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire1           : in  std_logic;
+		Fire2           : in  std_logic;
+		GunUp1        	 : in  std_logic;	
+		GunDown1        : in  std_logic;	
+		MoveLeft1       : in  std_logic;	
+		MoveRight1      : in  std_logic;	
+		MoveUp1         : in  std_logic;	
+		MoveDown1       : in  std_logic;	
+		GunUp2          : in  std_logic;	
+		GunDown2        : in  std_logic;	
+		MoveLeft2       : in  std_logic;	
+		MoveRight2      : in  std_logic;	
+		MoveUp2         : in  std_logic;	
+		MoveDown2       : in  std_logic;	
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+	component mw8080
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+	end component;
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+	signal gun1           : std_logic_vector(3 downto 0);
+	signal gun2           : std_logic_vector(3 downto 0);
+
+signal state1 : unsigned(2 downto 0);
+signal state2 : unsigned(2 downto 0);
+
+type gun_array is array(0 to  6) of std_logic_vector(3 downto 0);
+signal gun: gun_array := (
+		X"6",X"2",X"0",X"4",X"5",X"1",X"3");
+	
+begin
+
+process (Clk, GunUp1, GunUp2, GunDown1, GunDown2)
+begin
+if Clk = '1' then
+ if GunUp1 = '1' and not (state1 = 6) then state1 <= state1 + 1; elsif
+	 GunDown1 = '1' and not (state1 = 0)  then state1 <= state1 - 1; elsif
+	 GunUp2 = '1'  and not (state2 = 6) then state2 <= state2 + 1; elsif
+	 GunDown2 = '1'  and not (state2 = 0) then state2 <= state2 - 1; end if;	
+	end if; 
+end process;
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+-- no Watchdog
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+--			if WD_Cnt = 255 then
+--				Rst_n_s_i <= '0';
+--			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+--			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+--			if Sounds(0) = '1' and Old_S0 = '0' then
+--				WD_Cnt <= WD_Cnt + 1;
+--			end if;
+--			if PortWr(6) = '1' then
+--				WD_Cnt <= (others => '0');
+--			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: mw8080
+		port map(
+			Rst_n => Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+with AD_i(9 downto 8) select
+		GDB <= 	GDB0 when "00",
+					GDB1 when "01",
+					GDB2 when "10",
+						S when others;
+				
+--GDB <= GDB0 and GDB1 and GDB2 and S;--todo
+
+	GDB0(0) <= not MoveUp1;
+	GDB0(1) <= not MoveDown1;
+	GDB0(2) <= not MoveLeft1;
+	GDB0(3) <= not MoveRight1;
+	GDB0(4) <= not Gun1(0);--todo
+	GDB0(5) <= not Gun1(1);--todo
+	GDB0(6) <= not Gun1(2);--todo
+	GDB0(7) <= not Fire1;
+
+	GDB1(0) <= not MoveUp2;
+	GDB1(1) <= not MoveDown2;
+	GDB1(2) <= not MoveLeft2;
+	GDB1(3) <= not MoveRight2;
+	GDB1(4) <= Gun2(0);--todo
+	GDB1(5) <= Gun2(1);--todo
+	GDB1(6) <= Gun2(2);--todo
+	GDB1(7) <= not Fire2;
+
+	GDB2(0) <= '0';--Coinage
+	GDB2(1) <= '0';--Coinage
+	GDB2(2) <= '0';--Coinage
+	GDB2(3) <= '0';--Coinage
+	GDB2(4) <= '0';--Game_Time
+	GDB2(5) <= '0';--Game_Time
+	GDB2(6) <= Coin;
+	GDB2(7) <= Sel1Player;
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+			gun1 <= gun(to_integer(state1));
+			gun2 <= gun(to_integer(state2));
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..f16cf379
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..b9a88f96
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,336 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..d65b9f9b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.vhd	
@@ -0,0 +1,350 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire4_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire4_bv(0 DOWNTO 0) <= "0";
+	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	sub_wire2    <= inclk0;
+	sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire3,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-a.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-a.hex
new file mode 100644
index 00000000..c83404c4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-a.hex	
@@ -0,0 +1,18 @@
+:020000040000FA
+:2000000000001902007A0100FC00007E0500FE0380FC0340FE0738F9033EF0FF0FA0FF03F4
+:2000200080FF0080FF00C0FF00E0FF00E0FF0170FF0330FE0730FC0F30FE0F30FE0F30F8C0
+:200040000F20F00700F00700F00700C00700800700000700000300400300800300000F045B
+:200060000BA0000000B0010000B0013C00B0017E00F913FF00FF9FFF81F8C7FF9FFCFFFF88
+:20008000FFFEFFFFFF0000FF400000002000031C007E0080FF01E0FF07F0FF0FF0FF0FF810
+:2000A000FF1FF8FF1FF8FF1FF8E71FF0C30FF0810FE08107C0810380C301F0FF0FE0FF07E2
+:2000C000E0FF07F4FF2F843C21048120048120068160F7FFEF0681600400200400200400EE
+:2000E000200400204A0D460C870CC40B090D050CC80C86228221C321002145224121042277
+:20010000061AFF08000CFAFE0316FD0201141328740B3336740B1230740B32368C0B1228EB
+:200120008C0B0C38740B0C2A740B0D30740B0C2A8C0B0C388C0B0F30740B1111115265990B
+:20014000999911111153759999991111115485999999C400747020FFA00AB400008E0E000F
+:200160000047414B45404040404D53454F4040404040404040404040404040404040404073
+:200180004040404040404040404040404000002547524C404649474851494C50454F51405C
+:2001A000434D494C4040404040404040404040474551404F454144553A3A3A3A3A3A203A19
+:2001C0003A3A3A3A3A4040444F41543B4040474D51404B453B484555404E414F444C454F86
+:2001E0003B2E554D52404841534540434F454449513C00001A4E52504840425251514D4CAF
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-b.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-b.hex
new file mode 100644
index 00000000..e9efe4ee
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-b.hex	
@@ -0,0 +1,18 @@
+:020000040000FA
+:200000001F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01700C03F00C0CE
+:200020007F00C01FC0801F7000073C800F0FF8FF03FCFF01CEFF00C61F00C61F00C61F0040
+:20004000C61F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01700C03F0088
+:20006000C07F00C01F00801FC0000738800F0CF8FF0FFCFF03CE7F00C61F00C61F00C61F29
+:2000800000C61F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01700C03F48
+:2000A00000C07F00C01F00801F00000708800FF0F8FF1FFCFF0FCEFF00C61F00C61F00C678
+:2000C0001F00C61F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01700C028
+:2000E0003F00C07F00C01F00801F00000700800F00F83F00FCFF01CEFF0FC61F7FC61F0016
+:20010000C61F00C61F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01700E1
+:20012000C03F00C07F00C01F00801F00000700800F00F83F00FCFF00CEFF01C6FF07C61FBC
+:200140001EC61F70C61F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01713
+:2001600000C03F00C07F00C01F00801F00000700800F00F83F00FC7F00CEFF01C6FF03C61F
+:200180001F17C61F0EC61F14FA3F20030CF03F00F03F00E03D00C07900C07100C0E100C08F
+:2001A000E100E06000707000343400383800F0F000030CF03F00E03F00C01F00C01F00C0AB
+:2001C0001F00C01F00001E00001C00000C00000D00000E00003C00030CF03F00F03F00E037
+:2001E0001F00C00F00801F00003E00C07C00E07800703000343400383800F0F00003200421
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-c.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-c.hex
new file mode 100644
index 00000000..73d416cb
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-c.hex	
@@ -0,0 +1,18 @@
+:020000040000FA
+:200000007E3C181C1818181818183C3C3C7E66607C3E06067E7E3C7E6660387860667E3CF8
+:20002000666666667E7E606060603E3E06063E7E60667E3C3C3E06063E7E66667E3C7E7E24
+:2000400060703038181C0C0C3C7E66663C7E66667E3C3C7E66667E7C60607C3C10383838A6
+:2000600038383838387CC0C0C0C0C0C00000C0C00000000000000000C0C00000002040FF0D
+:2000800040200000F0C0A09008040201000078FCCCE07030300030300000000000000000C1
+:2000A0000000183C7E6666667E7E66663E7E66663E7E66667E3E3C7E6606060606667E3C50
+:2000C0003E7E6666666666667E3E7E7E06063E3E06067E7E7E7E06063E3E060606063C7E62
+:2000E0006606067676667E3C666666667E7E666666663C3C1818181818183C3C06060606BE
+:20010000060606067E7EC3C3E7E7FFFFDBC3C3C366666E6E7E7E767666663C7E66666666A7
+:2001200066667E3C3E7E66667E3E060606063E7E66667E3E766666663C7E66063E7C60664B
+:200140007E3C7E7E181818181818181866666666666666667E3C66666666667E3C3C18181B
+:20016000C3C3C3DBFFFFE7E7C3C366667E3C1818181818180116101818181858781B1A1E49
+:200180001E9898783818181818181818021B000100038003C007C007601D00318007E01F53
+:2001A000F03D383904418003C007E00FF81F3E2907E90001000900050005081F381B3829C6
+:2001C000CC37FE5D0315000500800D00800D00800F00C89F00F8FF00C01780C03F50C07FB8
+:2001E00060C01F30801F3800071C800F0EF8FF07FCFF03CEFF01C61F00C61F00C61F00C6BA
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-d.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-d.hex
new file mode 100644
index 00000000..f5711b67
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-d.hex	
@@ -0,0 +1,18 @@
+:020000040000FA
+:20000000CE0F3E07C3FB053A0820A7C8218208220020C921C52034C8352A00202B22002086
+:20002000C90413010C610F0A24100F035A0001296D0F0026035A00010B990F143D052A203C
+:20004000C30100004000660BAA8B0D4A0D8B0D035A00066320C6035400FE027800C8034B69
+:2000600000010BA40F143D033C00053D20C2FF400060006627A0C7220021C7220340000902
+:2000800021080127D50F012A052A20C30200004000A00BAA8B0D4A0D8B0D0004130F0A019F
+:2000A00009AF0F0C2E010CB80FA23E052A20C0010000480066139A8B0D870C8B0D053D20FB
+:2000C000C0FFE7A0480066139AC722C321C72206632006000004F800000AC80675200600CB
+:2000E0000004F800000AC806872006000004F800000AC806992006000004F800000AC8031B
+:200100001E000109C50F0C2E030A072A20073D20000105A40F0E2E14099B080C05202A20B7
+:2001200020FD0D0DC202030F000B2A20105F0E12032D00099B080E6010095D090E6050093E
+:200140005D090E6090095D090E7810095D090E9010095D090E9050095D090E90900DB2025E
+:200160000917090C02203D20D039230DB202030A000B3D20D09B2311032D00099B08610489
+:200180007304780487042A042A042A04B0048C0499049E04AB043E043E043E0417058407B8
+:2001A0008407840784078407840749056C051308E9053D06490655068D069D067006AD0674
+:2001C0008206BC064907380775078507AB070708E907EF07A305C9031B0936093C09420930
+:2001E00048094E0954095A09630900020000000000000000440000003C7E666666666666C7
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-e.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-e.hex
new file mode 100644
index 00000000..4372dd3e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-e.hex	
@@ -0,0 +1,18 @@
+:020000040000FA
+:20000000F21406471C7BE61FC20D06141404C20406C3FC05E5D521F809CA2406010A00097C
+:200020003DC21F06EB0120003E0AF51A137709F13DC22A06D1E113F13DC2FB05C92A0020BE
+:200040007E23220020320320C92A00207E23220020321520C9F3E10100001100003E1031DD
+:200060000F40C513BAC26206AFD301310024FBE92A00205E2356232200201AE6BF1213AFA0
+:2000800012C92A00205E2356EB220020C92A00205E2356230E0FCD7203220020C92A002076
+:2000A0005E2356230E09CD7203220020C92A00205E2356232200201AEE6012C9210E0FAF2C
+:2000C000D3023A02203DFAEB06FE02F41907FE05FAD5063E045E235623D55E2356230600CA
+:2000E000E3F5CD2D02F1E13DF2D5063A162047E680C2030778F68032162021220F3A052060
+:20010000C3C5063A1620E640C0F6403216203E04D302AF21360FC3D506E5F52150207EE6C4
+:2001200080C22D07EB0E0F21520FCD72033A1620F640321620F1E1C92A00205E235623226E
+:2001400000201A3C2712CDA3052A00205E235623F33E801213137E2312131313131AC60867
+:20016000124E234623220020131313EB71237023AF772377C92A00207ED301237E232200FB
+:2001800020321420C92A00203A1D205E235623220020922E0267CD5903EBE54B70230DC244
+:2001A0009C07E10E200915C29A07C921002111C40B1AA7C87723134F1A13477723C578064B
+:2001C0000009472B1A13D5571E0006087A1F577B175F05C2CC0773D10DC2C307C178060088
+:2001E000094705C2BD07C3B107213F20C3F207212C205E0104000956CD59031B151515219A
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-f.hex
new file mode 100644
index 00000000..e3ba8b5d
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-f.hex	
@@ -0,0 +1,18 @@
+:020000040000FA
+:20000000220020C93A0920FE22F4A705C9AEC84F0601790FDA20044F7807471313C3120483
+:2000200078AE77A0EB4E236669E91AE6700F0F0FA7C8321A2021E20E112A20C34F041AE675
+:20004000700F0F0FA7C8321B2021F00E113D204F0600094E2346EB36C0110B00197123706B
+:20006000C906FEC268040600212A2036C01105001970C90602C3630406FFC27F0406002113
+:200080002A2036C02370C90601C37A0406FEC293040600213D20C36B040602C38E0406FF07
+:2000A000C2A5040600213D20C382040601C3A004C82163207EE680CAC1042175207EE68021
+:2000C000C01112201AA7C0E5EB11A23E011020CDFA043EE2D301112C2001081A3A1A2021D6
+:2000E000FE0ECD7C03E1F336C623712373232323702372FB3E02321420C90A3C02FE06FA90
+:20010000110577472103207E3611A7CA100536027821A40FC3FB05C82187207EE680CA28CF
+:20012000052199207EE680C01113201AA7C0E5EB11B83E011120CDFA043ED2D301113F204F
+:2001400001F8F63A1B20C3DF04C83E04321420D301210720343A06204FE603BED036007900
+:200160001F1FE6033C21082086E60777C83A0420A7C03A0820A7C83D32082006603A06202E
+:20018000E630CA90054F78C6104779D610C285057832042021C62035210220AF772377232B
+:2001A0002377C9AF3203200E04211E201102201A1F1F1F1FE60FC2BB053E10C63077231A2F
+:2001C000E60FF63077062B79FE03C2D605062C1AA7C2D6053640132370230DC2AF053E08AD
+:2001E000211E20110524C3FB052A00207E235E235623D55E235623220020E1F57E23D63030
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-g.hex
new file mode 100644
index 00000000..f925841c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-g.hex	
@@ -0,0 +1,18 @@
+:020000040000FA
+:200000002777C21802C314022115207EA7CA180235C2180221C52035DB0247DB02B8210602
+:2000200020119E09CC0D04F1C1D1E1FBC97AB3C81A134F1A8032BC201A1347C5E51A13D3AC
+:2000400004DB0377230DC23D02AFD304DB0377E101200009C105C23B023ABC2047C9E57EE2
+:2000600023CD80025AE3AE771F1FE3232323CD80022B46E1AE77237EB02BC03EBFA677C93D
+:20008000E603477E23864F239623DA970296D297022B2B7156AFC92B2B05C2A7022BAF969F
+:2000A00077233E10C3BA022B36002305C2B4023E60C3BA0205C294023E4056A7C9AF5E7796
+:2000C00023567723477AB3EBC9E5010F0009444D2F32BD203E60BA21AB20D2E00221B2202D
+:2000E00071237023CD5903732372237123E37EEB210B0019EBE3732372EB1717DA14031769
+:20010000DA3E032B562B5E0104003E8009732372E1AE77C9E13E50BDC8E53E2ABD214903AC
+:20012000CA26032151033A0920E60C0F856FD23203245E2356E1E5010D00AFC30C03AF7782
+:20014000237723772377E177C98B0DB10DD70DB10DC722ED221323ED227BE6074F0603AF0C
+:200160007A1F577B1F5F05C25F03E521002419EBE1C9F37E2312130DC27303C9D55F160084
+:200180001978462356E1865F232323237E8257C93E08210220060070233DC29703CD5506BA
+:2001A000212108220020FB2A00203AC620A7CAB403219B085E23220020160021AE0919197F
+:2001C0005E2356EB11A603D5E9CD1308DB0047DB00B8211720117E09CC0D04DB0147DB017C
+:2001E000B8211820118E09CC0D04211C207EA7CA04043600075F160021D609195E2356EB88
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-h.hex
new file mode 100644
index 00000000..45ba5324
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-h.hex	
@@ -0,0 +1,18 @@
+:020000040000FA
+:200000000000310024C39003E5D5C5F5C3870077E5D5C5F521B9207E2F77A7FAEA00216F53
+:2000200020E5CDBD02CA38001A1377231A1377780E1F0905A7CA2800E1111200197DFEB727
+:20004000C2210021A220E5CDBD02CA76001A13EB73237223EBD3027E12133E03D304DB038D
+:20006000B677237E1213AFD304DB03B677780E1F0905A7CA5700E111EEFF197DFE5AC246AC
+:200080000021B220C391003AB920A7FA180221AB20CDBD02D5CAB400CDBD02EBD5CDBD02A8
+:2000A000D1CAB400E54B70230DC2A600E10E200915C2A400E1CDBD02CA18021A13D302D5FE
+:2000C000E3CDBD025E235623E322BA200600CD2D02E35E235623E3CD2D022ABA20E30C71B6
+:2000E000237023D1732372C318022163207EA7E5F25101237EA7237EFA0301FE70D2080172
+:20010000C35101FE90D25101110C00197EA7CA510111F8FF197ED610FEC0D25101E1E5363E
+:20012000A023237E1F1F1F1FE60F4F232323237E321D20D6101F1FE630B11F5F1600213A48
+:200140000F19791F7ED24C011F1F1F1FE60F321C20E1111200193EABBDC2ED002163207ECF
+:20016000A7F283013EFF32C420CD5E027E17F67FA677F28301E501090009CD59037323721C
+:200180002371E1011200093EABBDC25F012ABE207DB4C29801212A2022C020AF32BD207EC9
+:2001A000A7F2B101CD5E023ABD20A7CCC90222BE20111300193E63BDC2BE01212A203AC0F1
+:2001C00020BDC29F012114207EA7CAD40135C2D401AFD30121092035F20802362221042060
+:2001E0007EA7CAF601C6992777C2F601EB21C42034C29D03EB342103207EA7CA0802C69922
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.qpf
new file mode 100644
index 00000000..76b4c91f
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:27:39  November 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:27:39  November 20, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "LunarRescue"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.qsf
new file mode 100644
index 00000000..51170b9a
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.qsf	
@@ -0,0 +1,168 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 19:49:43  June 08, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		LunarRescue_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY LunarRescue_mist
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ------------------------------
+# start ENTITY(LunarRescue_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(LunarRescue_mist)
+# ----------------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/LunarRescue_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/LunarRescue_memory.sv
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/LunarRescue_Overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/col.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.sdc
new file mode 100644
index 00000000..f91c127c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/README LunarRescue.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Midway-Taito 8080 Hardware/README LunarRescue.txt
rename to Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/README.txt
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/clean.bat
new file mode 100644
index 00000000..83fb0c47
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_Overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_Overlay.vhd
new file mode 100644
index 00000000..8ec20801
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_Overlay.vhd	
@@ -0,0 +1,366 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+
+--Not Cleaned, iam to lazy for this
+
+
+entity LunarRescue_Overlay is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		CAB               : in    std_logic_vector(9 downto 0);
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end LunarRescue_Overlay;
+
+architecture rtl of LunarRescue_Overlay is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_A1      : boolean;
+	signal Overlay_A1_VCnt : boolean;
+	signal Overlay_A2      : boolean;
+	signal Overlay_A3      : boolean;
+	signal Overlay_A3_VCnt : boolean;	
+	signal Overlay_A4      : boolean;
+	signal Overlay_A4_VCnt : boolean;	
+	
+	signal Overlay_R1      : boolean;
+	signal Overlay_R1_VCnt : boolean;
+	signal Overlay_R2      : boolean;
+	signal Overlay_R3      : boolean;
+
+	signal Overlay_Y1      : boolean;
+	signal Overlay_Y1_VCnt : boolean;
+	signal Overlay_Y2      : boolean;
+	signal Overlay_Y3      : boolean;
+	signal Overlay_Y4      : boolean;
+	signal Overlay_Y4_VCnt : boolean;	
+	signal Overlay_Y5      : boolean;	
+	signal Overlay_Y5_VCnt : boolean;
+
+	signal Overlay_G1      : boolean;
+	signal Overlay_G1_VCnt : boolean;	
+	signal Overlay_G2      : boolean;
+   signal Overlay_G3      : boolean;
+	signal Overlay_G4      : boolean;
+	signal Overlay_G4_VCnt : boolean;	
+
+   signal Overlay_P1      : boolean;
+	signal Overlay_P2      : boolean;
+	signal Overlay_P2_VCnt : boolean;	
+	signal Overlay_P3      : boolean;
+	signal Overlay_P3_VCnt : boolean;
+	signal Overlay_P4      : boolean;
+	signal Overlay_P4_VCnt : boolean;
+	
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+	signal COLOR        : std_logic_vector(3 downto 0);
+
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  
+	  Overlay_G1 <= false;
+	  Overlay_G1_VCnt <= false;
+	  Overlay_G2 <= false;
+	  Overlay_G3 <= false;
+	  Overlay_G4 <= false;
+	  Overlay_G4_VCnt <= false;
+	  
+	  Overlay_A1 <= false;
+	  Overlay_A1_VCnt <= false;
+	  Overlay_A2 <= false;
+	  Overlay_A3 <= false;
+	  Overlay_A3_VCnt <= false;
+	  Overlay_A4 <= false;
+	  Overlay_A4_VCnt <= false;
+	  
+	  Overlay_R1 <= false;
+	  Overlay_R1_VCnt <= false;	  
+	  Overlay_R2 <= false;
+	  Overlay_R3 <= false;
+	  
+	  Overlay_Y1 <= false;
+	  Overlay_Y1_VCnt <= false;	  
+	  Overlay_Y2 <= false;
+	  Overlay_Y3 <= false;
+	  Overlay_Y4 <= false;
+	  Overlay_Y4_VCnt <= false;	  
+	  Overlay_Y5 <= false;
+	  Overlay_Y5_VCnt <= false;
+	  
+	  Overlay_P1 <= false;
+	  Overlay_P3 <= false;
+	  Overlay_P3_VCnt <= false;
+	  Overlay_P4 <= false;
+	  Overlay_P4_VCnt <= false;
+	  
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt >= 0) and (Vcnt <= 99) then
+		  Overlay_A1_VCnt <= true;
+		else
+		  Overlay_A1_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 100) and (Vcnt <= 149 ) then
+		  Overlay_R1_VCnt <= true;
+		else
+		  Overlay_R1_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 150) and (Vcnt <= 240) then
+		  Overlay_Y1_VCnt <= true;
+		else
+		  Overlay_Y1_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 236) and (Vcnt <= 16) then
+		  Overlay_G1_VCnt <= true;
+		else
+		  Overlay_G1_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 0) and (Vcnt <= 72) then
+		  Overlay_G4_VCnt <= true;
+		  Overlay_Y5_VCnt <= true;
+		else
+		  Overlay_G4_VCnt <= false;
+		  Overlay_Y5_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 73) and (Vcnt <= 200) then
+		  Overlay_P3_VCnt <= true;
+		else
+		  Overlay_P3_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 224) and (Vcnt <= 230) then
+		  Overlay_P4_VCnt <= true;
+		else
+		  Overlay_P4_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 160) and (Vcnt <= 166 ) then
+		  Overlay_A3_VCnt <= true;
+		else
+		  Overlay_A3_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 24 ) and (Vcnt <= 230 ) then
+		  Overlay_A4_VCnt <= true;
+		else
+		  Overlay_A4_VCnt <= false;
+		end if;
+	  
+	  	if (Vcnt >= 32 ) and (Vcnt <= 222 ) then
+		  Overlay_P2_VCnt <= true;
+		else
+		  Overlay_P2_VCnt <= false;
+		end if;
+	  end if;
+	  
+	  	if (Vcnt >= 42 ) and (Vcnt <= 216 ) then------------------------------------
+		  Overlay_Y4_VCnt <= true;
+		else
+		  Overlay_Y4_VCnt <= false;
+		end if;
+	  
+	  if (HCnt = 518)then--ok
+		if  Overlay_A1_VCnt then Overlay_A1 <= true; end if;
+		if  Overlay_R1_VCnt then Overlay_R1 <= true; end if;
+		if  Overlay_Y1_VCnt then Overlay_Y1 <= true; end if;
+	  elsif (HCnt >= 540) then
+		if  Overlay_A1_VCnt then Overlay_A1 <= false; end if;
+		if  Overlay_R1_VCnt then Overlay_R1 <= false; end if;
+		if  Overlay_Y1_VCnt then Overlay_Y1 <= false; end if;
+	  end if;
+	  
+	  if (HCnt = 528)then--check
+		if  Overlay_G1_VCnt then Overlay_G1 <= true; end if;
+	  elsif (HCnt >= 540) then
+		if  Overlay_G1_VCnt then Overlay_G1 <= false; end if;
+	  end if;
+	    
+	  if (HCnt = 486) then--ok
+		Overlay_R2 <= true;
+	  elsif (HCnt = 502) then
+		Overlay_R2 <= false;
+	  end if;
+
+	  if (HCnt = 438) then--ok
+		Overlay_Y2 <= true;
+	  elsif (HCnt = 470) then
+		Overlay_Y2 <= false;	
+	  end if;
+	  
+	  if (HCnt = 373) then--ok
+		Overlay_G2 <= true;
+	  elsif (HCnt = 445) then
+		Overlay_G2 <= false;
+	  end if;
+	  
+	  if (HCnt = 324) then--ok
+		Overlay_P1 <= true;
+	  elsif (HCnt = 380) then
+		Overlay_P1 <= false;
+	  end if;
+	  
+	  if (HCnt = 275) then--ok
+		Overlay_A2 <= true;
+	  elsif (HCnt = 327) then
+		Overlay_A2 <= false;
+	  end if;
+
+	  if (HCnt = 210) then--ok
+		Overlay_Y3 <= true;
+	  elsif (HCnt = 274) then
+		Overlay_Y3 <= false;
+	  end if;
+	  
+	  if (HCnt = 166) then--ok
+		Overlay_R3 <= true;
+	  elsif (HCnt = 214) then
+		Overlay_R3 <= false;
+	  end if;	  
+
+	  if (HCnt = 70) then--ok
+		Overlay_G3 <= true;
+	  elsif (HCnt = 170) then
+		Overlay_G3 <= false;
+	  end if;
+	  
+	  if (HCnt = 70) then--check
+		if  Overlay_P4_VCnt then Overlay_P4 <= true; end if;
+	  elsif (HCnt = 86) then
+		if  Overlay_P4_VCnt then Overlay_P4 <= false; end if;
+	  end if;
+	  
+	  if (HCnt = 0) then--ok
+		if  Overlay_Y5_VCnt then Overlay_Y5 <= true; end if;
+		if  Overlay_P3_VCnt then Overlay_P3 <= true; end if;
+	  elsif (HCnt = 70) then
+		if  Overlay_Y5_VCnt then Overlay_Y5 <= false; end if;
+		if  Overlay_P3_VCnt then Overlay_P3 <= false; end if;
+	  end if;
+	  
+	  if (HCnt = 164) then--check
+		if  Overlay_A3_VCnt then Overlay_A3 <= true; end if;
+	  elsif (HCnt = 172) then
+		if  Overlay_A3_VCnt then Overlay_A3 <= false; end if;
+	  end if;
+	  
+	  if (HCnt = 118) then--check
+		if  Overlay_A4_VCnt then Overlay_A4 <= true; end if;
+	  elsif (HCnt = 134) then
+		if  Overlay_A4_VCnt then Overlay_A4 <= false; end if;
+	  end if;
+	 
+	  if (HCnt = 102) then--check
+		if  Overlay_P2_VCnt then Overlay_P2 <= true; end if;
+	  elsif (HCnt = 118) then
+		if  Overlay_P2_VCnt then Overlay_P2 <= false; end if;
+	  end if;
+	  
+	  if (HCnt = 86) then--check
+		if  Overlay_Y4_VCnt then Overlay_Y4 <= true; end if;
+	  elsif (HCnt = 102) then
+		if  Overlay_Y4_VCnt then Overlay_Y4 <= false; end if;
+	  end if; 
+	  
+	  if (HCnt = 486) then--ok
+		if  Overlay_G4_VCnt then Overlay_G4 <= true; end if;
+	  elsif (HCnt = 470) then
+		if  Overlay_G4_VCnt then Overlay_G4 <= false; end if;
+	  end if;
+
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video)
+  begin
+	if (Video = '0') then
+		VideoRGB  <= "000";
+	elsif Overlay_R1 or Overlay_R2 or (Overlay_R3 and not Overlay_A3) then--Red      
+		VideoRGB  <= "100";
+	elsif Overlay_A1 or Overlay_A2 or Overlay_A3 or Overlay_A4 then--Aqua
+		VideoRGB  <= "011";
+	elsif (Overlay_Y1 and not Overlay_G1) or Overlay_Y2 or Overlay_Y3 or Overlay_Y4 or Overlay_Y5 then--Yellow
+		VideoRGB  <= "110";	
+	elsif Overlay_G1 or Overlay_G2 or (Overlay_G3 and not (Overlay_P4 or Overlay_A4 or Overlay_P2 or Overlay_Y4))-- or Overlay_G4 
+	then
+		VideoRGB  <= "010";	
+	elsif Overlay_P1 or Overlay_P2 or Overlay_P3 or Overlay_P4 then--Purple
+		VideoRGB  <= "101";		
+--	elsif not (Overlay_G4) then--white 
+	else
+		VideoRGB  <= "111";-- end if;
+	end if;
+  end process;
+  
+colPROM: entity work.col
+port map(
+	clk  => Clk,
+	addr => CAB, --should be Video Counters 
+	data => COLOR
+);
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  
+--  O_VIDEO_R <= COLOR(2);
+--  O_VIDEO_G <= COLOR(1);
+--  O_VIDEO_B <= COLOR(0);
+  O_HSYNC   <= HSync;
+  O_VSYNC   <= VSync;
+
+
+end;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_memory.sv
new file mode 100644
index 00000000..3f7ca5bf
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_memory.sv	
@@ -0,0 +1,103 @@
+module LunarRescue_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+wire [7:0]rom_data_4;
+wire [7:0]rom_data_5;
+
+
+sprom #(
+	.init_file("./roms/lrescue_1.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_0)
+	);
+
+sprom #(
+	.init_file("./roms/lrescue_2.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_1)
+	);
+	
+sprom #(
+	.init_file("./roms/lrescue_3.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_2)
+	);
+	
+sprom #(
+	.init_file("./roms/lrescue_4.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_e (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_3)
+	);
+	
+sprom #(
+	.init_file("./roms/lrescue_5.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_i (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_4)
+	);
+
+sprom #(
+	.init_file("./roms/lrescue_6.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_j (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_5)
+	);	
+
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5) begin
+	Rom_out = 8'b00000000;
+		case (Addr[15:11])
+			5'b00000 : Rom_out = rom_data_0;
+			5'b00001 : Rom_out = rom_data_1;
+			5'b00010 : Rom_out = rom_data_2;
+			5'b00011 : Rom_out = rom_data_3;
+			5'b01000 : Rom_out = rom_data_4;
+			5'b01001 : Rom_out = rom_data_5;
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_mist.sv
new file mode 100644
index 00000000..e09110e2
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_mist.sv	
@@ -0,0 +1,209 @@
+module LunarRescue_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"Lunar Resc.;;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Overlay, On, Off;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [9:0]CAB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_sys),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+	.DIP(dip),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.CAB(CAB),
+	.HSync(HSync),
+	.VSync(VSync)
+	);
+		
+LunarRescue_memory LunarRescue_memory (
+	.Clock(clk_sys),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+	
+invaders_audio invaders_audio (
+	.Clk(clk_sys),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);		
+	  
+LunarRescue_Overlay LunarRescue_Overlay (
+	.Video(Video),
+	.Overlay(~status[5]),
+	.CLK(clk_sys),
+	.Rst_n_s(Rst_n_s),
+	.HSync(HSync),
+	.VSync(VSync),
+	.CAB(CAB),
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({r,r,r}),
+	.G({g,g,g}),
+	.B({b,b,b}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.rotate({1'b0,status[2]}),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ce_divider(1),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..ed759c73
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/invaders.vhd	
@@ -0,0 +1,245 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		DIP             : in  std_logic_vector(7 downto 0);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		CAB             : out std_logic_vector(9 downto 0);
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: entity work.mw8080
+		port map(
+			Rst_n => Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			CAB => CAB,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+
+	GDB0(0) <= DIP(7);
+	GDB0(1) <= DIP(6);
+	GDB0(2) <= DIP(5);
+	GDB0(3) <= '1';
+	GDB0(4) <= not Fire;
+	GDB0(5) <= not MoveLeft;
+	GDB0(6) <= not MoveRight;
+	GDB0(7) <= DIP(4);
+
+	GDB1(0) <= not Coin;
+	GDB1(1) <= not Sel2Player;
+	GDB1(2) <= not Sel1Player;
+	GDB1(3) <= '1';
+	GDB1(4) <= not Fire;
+	GDB1(5) <= not MoveLeft;
+	GDB1(6) <= not MoveRight;
+	GDB1(7) <= '1';
+
+	GDB2(0) <= DIP(3);
+	GDB2(1) <= DIP(2);
+	GDB2(2) <= '0';--TILT
+	GDB2(3) <= DIP(1);
+	GDB2(4) <= not Fire;
+	GDB2(5) <= not MoveLeft;
+	GDB2(6) <= not MoveRight;
+	GDB2(7) <= '1';
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..f16cf379
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..7a8f0d58
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,337 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		CAB             : out std_logic_vector(9 downto 0);
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+   CAB <= std_logic_vector(CntE7(4 downto 0)) & std_logic_vector(CntE5(4 downto 0));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA, 
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..d65b9f9b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.vhd	
@@ -0,0 +1,350 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire4_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire4_bv(0 DOWNTO 0) <= "0";
+	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	sub_wire2    <= inclk0;
+	sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire3,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/col.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/col.bin
new file mode 100644
index 00000000..e65c5a07
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/col.bin	
@@ -0,0 +1 @@
+

			





	

			





	

			





	


			





	


			





	


			





	


			





	
			





	
			





	
			





			
			





			
			





			
			





			
			





			
			





			
			





			
			





			
			





			
		





			
			





	


			





	


			





	


			





	


			





	


			





	

			





	

			





	

			





	

\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/col.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/col.vhd
new file mode 100644
index 00000000..f798fd72
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/col.vhd	
@@ -0,0 +1,86 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity col is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(9 downto 0);
+	data : out std_logic_vector(3 downto 0)
+);
+end entity;
+
+architecture prom of col is
+	type rom is array(0 to  1023) of std_logic_vector(3 downto 0);
+	signal rom_data: rom := (
+		"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
+		"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
+		"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
+		"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
+		"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
+		"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
+		"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
+		"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
+		"1101","1101","1100","1100","1100","1100","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1100","1001","1111","1110","1110",
+		"1101","1101","1100","1100","1100","1110","1111","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1100","1001","1111","1110","1110",
+		"1101","1101","1100","1100","1011","1110","1111","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1100","1001","1111","1110","1110",
+		"1101","1101","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1100","1001","1111","1110","1110",
+		"1101","1101","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1100","1001","1111","1110","1110",
+		"1101","1101","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1100","1001","1111","1110","1110",
+		"1101","1101","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1100","1001","1111","1110","1110",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1110","1110",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1110","1110",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1110","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101",
+		"1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101",
+		"1111","1111","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101",
+		"1111","1111","1100","1100","1011","1110","1111","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101",
+		"1111","1111","1011","1100","1100","1110","1111","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101",
+		"1111","1111","1100","1100","1100","1100","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110",
+		"1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1100");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_1.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_1.hex
new file mode 100644
index 00000000..5ff2d9cd
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_1.hex	
@@ -0,0 +1,129 @@
+:10000000000000C34B160000F5C5D5E5C3E70500A9
+:10001000F5C5D5E53E8032BE2021C02035CD4B0A46
+:10002000DB010FDA66003AEA20A7CA42003AEB2069
+:10003000FE09D23E00C6012732EB20CDAC0AAF321A
+:10004000EA203AE920A7C260003AEF20A7C2E60EF4
+:100050003AEB20A7C26B003ABF21A7C2E60E000010
+:10006000E1D1C1F1FBC93E01C33F003A5820A7C20C
+:1000700060003E01CDDC08310024FBCDA401CDBDE4
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+:1000A000DB01E604CA8E000699AF32EE203AEB205F
+:1000B000802732EB20CDAC0ACD184C22F82022FC50
+:1000C00020CDD402CDDF02CDEA02CDC5480620CD39
+:1000D0000049CDA401CD9805CDAC4C21010122E50C
+:1000E00020CDB447CD4C4CCD8F02CDE349CDD402C9
+:1000F0000000000000CDF202CDCA01CD6102CD7931
+:1001000002CD4602CDA901CD781F3A2720A7D306FC
+:10011000CA0A01CD1210C223013A2820FE02D306DA
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+:1007F0000B08CD3B08C616CD4208C3A006CD3B086A
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_2.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_2.hex
new file mode 100644
index 00000000..c79ee941
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_2.hex	
@@ -0,0 +1,129 @@
+:10000000C32306CD3B08C60BC32306FE35D27808B2
+:100010003ADB20A7CA31082ADF202522DF203E1B39
+:10002000CD360521DB203521CF203ADB20856F3608
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+:1000E00032BF21C93AEF20A7C83AC620C3440A3A12
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+:10010000000000E5D5110004193E1CCD3605D1E1F3
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_3.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_3.hex
new file mode 100644
index 00000000..e4e4a765
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_3.hex	
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_4.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_4.hex
new file mode 100644
index 00000000..871ee3ed
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_4.hex	
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_5.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_5.hex
new file mode 100644
index 00000000..4176ee6a
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_5.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_6.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_6.hex
new file mode 100644
index 00000000..08e0316e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_6.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.qpf
new file mode 100644
index 00000000..7344eeb5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 16:15:41  June 05, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:15:41  June 05, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "OzmaWars"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.qsf
new file mode 100644
index 00000000..567324b3
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.qsf	
@@ -0,0 +1,178 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 02:57:11  June 09, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		OzmaWars_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name TOP_LEVEL_ENTITY OzmaWars_mist
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ---------------------------
+# start ENTITY(OzmaWars_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(OzmaWars_mist)
+# -------------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/OzmaWars_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/OzmaWars_memory.sv
+set_global_assignment -name VHDL_FILE rtl/OzmaWars_overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+set_global_assignment -name VHDL_FILE rtl/roms/mw01.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/mw02.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/mw03.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/mw04.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/mw05.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/mw06.vhd
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.sdc
new file mode 100644
index 00000000..f91c127c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/README OzmaWars.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Midway-Taito 8080 Hardware/README OzmaWars.txt
rename to Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/README.txt
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/clean.bat
new file mode 100644
index 00000000..83fb0c47
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_memory.sv
new file mode 100644
index 00000000..795f9949
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_memory.sv	
@@ -0,0 +1,80 @@
+
+module OzmaWars_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+wire [7:0]rom_data_4;
+wire [7:0]rom_data_5;
+
+
+mw01 mw01 (
+	.clk(Clock),
+	.addr(Addr[10:0]),
+	.data(rom_data_0)
+);
+
+mw02 mw02 (
+	.clk(Clock),
+	.addr(Addr[10:0]),
+	.data(rom_data_1)
+);
+
+mw03 mw03 (
+	.clk(Clock),
+	.addr(Addr[10:0]),
+	.data(rom_data_2)
+);
+
+mw04 mw04 (
+	.clk(Clock),
+	.addr(Addr[10:0]),
+	.data(rom_data_3)
+);
+
+mw05 mw05 (
+	.clk(Clock),
+	.addr(Addr[10:0]),
+	.data(rom_data_4)
+);
+
+mw06 mw06 (
+	.clk(Clock),
+	.addr(Addr[10:0]),
+	.data(rom_data_5)
+);
+	
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5) begin
+	Rom_out = 8'b00000000;
+		case (Addr[15:11])
+			5'b00000 : Rom_out = rom_data_0;
+			5'b00001 : Rom_out = rom_data_1;
+			5'b00010 : Rom_out = rom_data_2;
+			5'b00011 : Rom_out = rom_data_3;
+			5'b01000 : Rom_out = rom_data_4;
+			5'b01001 : Rom_out = rom_data_5;
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_mist.sv
new file mode 100644
index 00000000..bc82fcec
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_mist.sv	
@@ -0,0 +1,210 @@
+module OzmaWars_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"Ozma Wars;;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Overlay, On, Off;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_core, clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+	.MoveUp(~m_up),
+	.MoveDown(~m_down),	
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(HSync),
+	.VSync(VSync)
+	);
+		
+OzmaWars_memory OzmaWars_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_core),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);
+	
+OzmaWars_overlay OzmaWars_overlay (
+	.Video(Video),
+	.Overlay(~status[5]),
+	.CLK(clk_core),
+	.Rst_n_s(Rst_n_s),
+	.HSync(HSync),
+	.VSync(VSync),
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({r,r,r}),
+	.G({g,g,g}),
+	.B({b,b,b}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.rotate({1'b0,status[2]}),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ce_divider(0),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+
+
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd
new file mode 100644
index 00000000..b0188292
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd	
@@ -0,0 +1,225 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity OzmaWars_overlay is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		CAB               : in    std_logic_vector(7 downto 0);
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end OzmaWars_overlay;
+
+architecture rtl of OzmaWars_overlay is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	
+	signal Overlay_A1      : boolean;
+	signal Overlay_A2      : boolean;
+	signal Overlay_A3      : boolean;
+	signal Overlay_A3_VCnt : boolean;
+	
+	signal Overlay_B1      : boolean;
+	signal Overlay_B2      : boolean;
+	signal Overlay_B2_VCnt : boolean;
+	
+	signal Overlay_G1      : boolean;
+	
+	signal Overlay_P1      : boolean;
+	
+	signal Overlay_R1      : boolean;
+	signal Overlay_R2      : boolean;
+	
+	signal Overlay_Y1      : boolean;
+	signal Overlay_Y2      : boolean;
+	signal Overlay_Y2_VCnt : boolean;
+
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+	signal col_data        : std_logic_vector(3 downto 0);
+
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+
+	  Overlay_A1 <= false;
+	  Overlay_A2 <= false;
+	  Overlay_A3 <= false;
+	  Overlay_A3_VCnt <= false;
+	  
+	  Overlay_B1 <= false;
+	  Overlay_B2 <= false;
+	  Overlay_B2_VCnt <= false;
+	  
+	  Overlay_G1 <= false;
+	  
+	  Overlay_P1 <= false;
+	  
+	  Overlay_R1 <= false;
+	  Overlay_R2 <= false;
+	  
+	  Overlay_Y1 <= false;
+	  Overlay_Y2 <= false;
+	  Overlay_Y2_VCnt <= false;
+
+	  
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt = 0) then
+		  Overlay_A3_VCnt <= true;
+		elsif (Vcnt = 86) then
+		  Overlay_B2_VCnt <= true;
+		  Overlay_A3_VCnt <= false;
+		elsif (Vcnt = 168) then
+		  Overlay_Y2_VCnt <= true;
+		  Overlay_B2_VCnt <= false;
+		elsif (Vcnt = 232) then
+		  Overlay_Y2_VCnt <= false;
+		end if;
+	  end if;  
+	  
+	  if (HCnt = 500) and Overlay_A3_VCnt then
+		Overlay_A3 <= true;
+	  elsif (HCnt = 540) then
+		Overlay_A3 <= false;
+	  end if;
+	  
+	  if (HCnt = 486) and Overlay_B2_VCnt then
+		Overlay_B2 <= true;
+	  elsif (HCnt = 540) then
+		Overlay_B2 <= false;
+	  end if;
+
+	  if (HCnt = 486) and Overlay_Y2_VCnt then
+		Overlay_Y2 <= true;
+	  elsif (HCnt = 540) then
+		Overlay_Y2 <= false;
+	  end if;
+
+	  if (HCnt = 64) then
+		Overlay_R2 <= true;
+	  elsif (HCnt = 96) then
+		Overlay_A2 <= true;
+		Overlay_R2 <= false;
+	  elsif (HCnt = 120) then
+		Overlay_A2 <= false;
+		Overlay_R1 <= true;
+	  elsif (HCnt = 166) then
+		Overlay_R1 <= false;
+		Overlay_Y1 <= true;
+	  elsif (HCnt = 228) then
+	   Overlay_Y1 <= false;
+		Overlay_P1 <= true;
+	  elsif (HCnt = 292) then
+		Overlay_P1 <= false;
+		Overlay_A1 <= true;
+	  elsif (HCnt = 358) then
+		Overlay_G1 <= true;
+		Overlay_A1 <= false;
+	  elsif (HCnt = 430) then
+		Overlay_G1 <= false;
+		Overlay_B1 <= true;
+	  elsif (HCnt = 486) then
+		Overlay_B1 <= false;
+--		if Overlay_A3_VCnt then 
+--			Overlay_A2 <= true;
+--		if Overlay_B2_VCnt then 
+--			Overlay_B2 <= true;
+--		if Overlay_Y2_VCnt then 
+--			Overlay_Y2 <= true;
+--	   elsif (HCnt = 500) then
+--			Overlay_A3 <= false;	
+--	   elsif (HCnt = 540) then
+--			Overlay_B2 <= false;
+--			Overlay_Y2 <= false;
+	  end if; 
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video, Overlay_G1, Overlay_B1, Overlay_B2, Overlay_A1, Overlay_A2, Overlay_A3, Overlay_P1, Overlay_Y1, Overlay_Y2, Overlay_R1, Overlay_R2)
+  begin
+	if (Video = '0') then
+	  VideoRGB  <= "000";
+	else
+	  if Overlay_A1 or Overlay_A2 or Overlay_A3 then--AQUA
+		VideoRGB  <= "011";
+		elsif Overlay_B1 or Overlay_B2 then--BLUE
+		VideoRGB  <= "001";
+	  elsif Overlay_G1 then--GREEN
+		VideoRGB  <= "010";
+	  elsif Overlay_P1 then--PINK
+		VideoRGB  <= "101";
+	  elsif Overlay_R1 or Overlay_R2 then--RED
+		VideoRGB  <= "100";			
+	  elsif Overlay_Y1 or Overlay_Y2 then--YELLOW
+		VideoRGB  <= "110";	
+	  else	  
+		VideoRGB  <= "111";--WHITE
+	  end if;
+	end if;
+  end process;
+  
+--  colPROM: entity work.clr
+--port map(
+--	clk  => Clk,
+--	addr => CAB, --should be Video Counters 
+--	data => col_data
+--);
+
+--  O_VIDEO_R <= col_data(2);
+--  O_VIDEO_G <= col_data(1);
+--  O_VIDEO_B <= col_data(0);
+  
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_HSYNC   <= HSync;
+  O_VSYNC   <= VSync;
+
+
+end;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T8080se.vhd
new file mode 100644
index 00000000..65b92d54
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T8080se.vhd	
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..e09def1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..1c0f2638
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/dac.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/dac.vhd
new file mode 100644
index 00000000..db58d70b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/dac.vhd	
@@ -0,0 +1,48 @@
+-------------------------------------------------------------------------------
+--
+-- Delta-Sigma DAC
+--
+-- Refer to Xilinx Application Note XAPP154.
+--
+-- This DAC requires an external RC low-pass filter:
+--
+--   dac_o 0---XXXXX---+---0 analog audio
+--              3k3    |
+--                    === 4n7
+--                     |
+--                    GND
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.numeric_std.all;
+
+entity dac is
+	generic (
+		C_bits  : integer := 8
+	);
+	port (
+		clk_i   : in  std_logic;
+		res_n_i : in  std_logic;
+		dac_i   : in  std_logic_vector(C_bits-1 downto 0);
+		dac_o   : out std_logic
+	);
+end dac;
+
+architecture rtl of dac is
+	signal sig_in: unsigned(C_bits downto 0);
+begin
+	seq: process(clk_i, res_n_i)
+	begin
+		if res_n_i = '0' then
+			sig_in <= to_unsigned(2**C_bits, sig_in'length);
+			dac_o  <= '0';
+		elsif rising_edge(clk_i) then
+		        -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
+			--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
+			sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
+			dac_o  <= sig_in(C_bits);
+		end if;
+	end process seq;
+end rtl;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..e35bdc82
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/invaders.vhd	
@@ -0,0 +1,273 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		MoveUp          : in  std_logic;
+		MoveDown        : in  std_logic;
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+	component mw8080
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+	end component;
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: mw8080
+		port map(
+			Rst_n => Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+
+	GDB0(0) <= '1';--
+	GDB0(1) <= '1';--
+	GDB0(2) <= '1';--
+	GDB0(3) <= '1';--
+	GDB0(4) <= '1';--
+	GDB0(5) <= '1';--
+	GDB0(6) <= '1';--
+	GDB0(7) <= '1';--
+	
+	GDB1(0) <= Coin;
+	GDB1(1) <= not Sel2Player;
+	GDB1(2) <= not Sel1Player;
+	GDB1(3) <= '1';
+	GDB1(4) <= not Fire;--controller
+	GDB1(5) <= not MoveLeft;--controller
+	GDB1(6) <= not MoveRight;--controller
+	GDB1(7) <= '1';
+
+	GDB2(0) <= '0';--active high
+	GDB2(1) <= '0';--active high
+	GDB2(2) <= '0';--active high
+	GDB2(3) <= '0';--active high
+	GDB2(4) <= '0';--DIPLOCK --active high
+	GDB2(5) <= not Sel1Player;--active low
+	GDB2(6) <= not Coin;--active low
+	GDB2(7) <= not Sel2Player;--active low
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..f16cf379
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..b9a88f96
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,336 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..f8d0b139
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/pll.vhd	
@@ -0,0 +1,382 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 20,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw01.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw01.vhd
new file mode 100644
index 00000000..1e6a8db4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw01.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity mw01 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of mw01 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"F3",X"31",X"7C",X"02",X"C3",X"36",X"02",X"C7",X"F5",X"AF",X"32",X"05",X"20",X"C3",X"49",X"00",
+		X"F5",X"3E",X"80",X"C3",X"0A",X"00",X"C7",X"C7",X"F3",X"E5",X"D5",X"C5",X"F5",X"C3",X"2B",X"01",
+		X"F3",X"CD",X"0F",X"02",X"47",X"C3",X"D4",X"01",X"F3",X"CD",X"0F",X"02",X"47",X"C3",X"F3",X"01",
+		X"F3",X"CD",X"0F",X"02",X"2F",X"C3",X"FB",X"01",X"F3",X"CD",X"0F",X"02",X"79",X"C3",X"04",X"02",
+		X"AF",X"77",X"23",X"05",X"C2",X"41",X"00",X"C9",X"C7",X"AF",X"32",X"0B",X"20",X"22",X"26",X"20",
+		X"21",X"00",X"00",X"39",X"22",X"28",X"20",X"F1",X"2A",X"26",X"20",X"E5",X"2A",X"0C",X"20",X"F9",
+		X"2A",X"28",X"20",X"E5",X"D5",X"C5",X"F5",X"3A",X"06",X"20",X"F5",X"21",X"00",X"00",X"39",X"22",
+		X"0C",X"20",X"EB",X"2A",X"9E",X"02",X"EB",X"7A",X"2F",X"57",X"7B",X"2F",X"5F",X"19",X"D2",X"BA",
+		X"00",X"3A",X"0B",X"20",X"A7",X"C2",X"7B",X"01",X"CD",X"B6",X"02",X"21",X"07",X"20",X"7E",X"23",
+		X"A6",X"CA",X"05",X"01",X"47",X"23",X"4E",X"21",X"1E",X"20",X"16",X"80",X"7A",X"A0",X"CA",X"AC",
+		X"00",X"35",X"C2",X"AC",X"00",X"A1",X"C2",X"BA",X"00",X"7A",X"B1",X"4F",X"23",X"7A",X"2F",X"A0",
+		X"47",X"CA",X"BE",X"00",X"7A",X"1F",X"57",X"C3",X"9D",X"00",X"2A",X"A2",X"02",X"E9",X"21",X"09",
+		X"20",X"71",X"7E",X"2F",X"2B",X"A6",X"77",X"2A",X"0C",X"20",X"F9",X"0E",X"80",X"3A",X"09",X"20",
+		X"47",X"3A",X"0A",X"20",X"2F",X"A0",X"5F",X"3A",X"07",X"20",X"A3",X"CA",X"05",X"01",X"11",X"0E",
+		X"20",X"78",X"A1",X"C2",X"EE",X"00",X"79",X"1F",X"4F",X"13",X"13",X"C3",X"E1",X"00",X"2F",X"A0",
+		X"32",X"09",X"20",X"79",X"32",X"06",X"20",X"1A",X"6F",X"13",X"1A",X"67",X"F9",X"F1",X"C1",X"D1",
+		X"E1",X"D3",X"06",X"FB",X"C9",X"F3",X"2A",X"0C",X"20",X"F9",X"01",X"0A",X"00",X"09",X"22",X"0C",
+		X"20",X"F1",X"A7",X"CA",X"1E",X"01",X"47",X"3A",X"07",X"20",X"A0",X"CA",X"05",X"01",X"32",X"06",
+		X"20",X"F1",X"C1",X"D1",X"E1",X"F9",X"E1",X"D3",X"06",X"FB",X"C9",X"21",X"06",X"20",X"7E",X"47",
+		X"23",X"A6",X"CA",X"05",X"01",X"23",X"B6",X"77",X"21",X"1E",X"20",X"11",X"0E",X"20",X"78",X"17",
+		X"DA",X"49",X"01",X"23",X"13",X"13",X"C3",X"3F",X"01",X"44",X"4D",X"21",X"00",X"00",X"39",X"7D",
+		X"12",X"13",X"7C",X"12",X"11",X"08",X"00",X"19",X"F9",X"E3",X"7E",X"23",X"E3",X"02",X"C3",X"C7",
+		X"00",X"F3",X"A7",X"CA",X"70",X"01",X"C5",X"47",X"3A",X"07",X"20",X"A0",X"CA",X"72",X"01",X"C1",
+		X"FB",X"C9",X"78",X"C1",X"F5",X"32",X"0B",X"20",X"C3",X"4D",X"00",X"47",X"21",X"06",X"20",X"77",
+		X"23",X"B6",X"77",X"31",X"7C",X"02",X"78",X"33",X"33",X"33",X"33",X"17",X"D2",X"87",X"01",X"D1",
+		X"E1",X"F9",X"EB",X"FB",X"E9",X"F3",X"F5",X"A7",X"C4",X"9E",X"01",X"F1",X"FB",X"C9",X"C5",X"E5",
+		X"2F",X"47",X"0E",X"03",X"21",X"07",X"20",X"7E",X"A0",X"77",X"23",X"0D",X"C2",X"A7",X"01",X"36",
+		X"00",X"21",X"2A",X"20",X"78",X"2F",X"23",X"17",X"D2",X"B6",X"01",X"36",X"00",X"E1",X"C1",X"C9",
+		X"F3",X"3A",X"06",X"20",X"CD",X"9E",X"01",X"C3",X"C7",X"00",X"F1",X"C1",X"D1",X"E1",X"3A",X"00",
+		X"20",X"FB",X"A7",X"C9",X"CD",X"27",X"02",X"70",X"3E",X"D3",X"32",X"01",X"20",X"EB",X"3E",X"C9",
+		X"32",X"03",X"20",X"21",X"CC",X"4F",X"CD",X"2A",X"02",X"32",X"02",X"20",X"1A",X"CD",X"01",X"20",
+		X"C3",X"CA",X"01",X"CD",X"27",X"02",X"B0",X"77",X"C3",X"D8",X"01",X"47",X"CD",X"27",X"02",X"A0",
+		X"77",X"C3",X"D8",X"01",X"2F",X"4F",X"CD",X"27",X"02",X"B0",X"A1",X"77",X"C3",X"D8",X"01",X"32",
+		X"00",X"20",X"E3",X"33",X"33",X"EB",X"E3",X"7E",X"23",X"E3",X"3B",X"3B",X"E5",X"C5",X"32",X"04",
+		X"20",X"3A",X"00",X"20",X"F5",X"D5",X"C9",X"21",X"2A",X"20",X"3A",X"04",X"20",X"85",X"6F",X"7C",
+		X"CE",X"00",X"67",X"7E",X"A7",X"C9",X"D1",X"E1",X"F9",X"EB",X"CD",X"3E",X"02",X"E9",X"F3",X"F5",
+		X"C5",X"E5",X"AF",X"06",X"2D",X"21",X"06",X"20",X"CD",X"41",X"00",X"21",X"00",X"24",X"22",X"0C",
+		X"20",X"E1",X"C1",X"F1",X"D3",X"06",X"FB",X"C9",X"F3",X"F5",X"C5",X"E5",X"21",X"00",X"00",X"06",
+		X"00",X"7E",X"80",X"47",X"23",X"7C",X"FE",X"20",X"C2",X"61",X"02",X"78",X"C6",X"1B",X"C2",X"78",
+		X"02",X"E1",X"C1",X"F1",X"D3",X"06",X"FB",X"C9",X"2A",X"A0",X"02",X"E9",X"EE",X"02",X"8D",X"21",
+		X"8E",X"07",X"AD",X"21",X"A3",X"0A",X"C3",X"21",X"30",X"0D",X"DF",X"21",X"B1",X"11",X"F7",X"21",
+		X"5B",X"13",X"0D",X"22",X"C3",X"13",X"23",X"22",X"A4",X"02",X"24",X"22",X"A7",X"02",X"25",X"22",
+		X"AE",X"02",X"B2",X"02",X"C3",X"AA",X"02",X"C3",X"AA",X"02",X"F3",X"C3",X"AA",X"02",X"F3",X"C3",
+		X"AE",X"02",X"F3",X"C3",X"B2",X"02",X"2A",X"59",X"20",X"2B",X"22",X"59",X"20",X"DB",X"01",X"0F",
+		X"DA",X"C8",X"02",X"AF",X"32",X"47",X"20",X"C9",X"3A",X"46",X"20",X"FE",X"09",X"D0",X"3A",X"47",
+		X"20",X"A7",X"C0",X"3E",X"01",X"32",X"47",X"20",X"DB",X"02",X"07",X"3A",X"46",X"20",X"D2",X"E3",
+		X"02",X"C6",X"01",X"C6",X"01",X"27",X"E6",X"0F",X"32",X"46",X"20",X"D3",X"06",X"C9",X"CD",X"A4",
+		X"04",X"CD",X"16",X"07",X"21",X"26",X"22",X"11",X"B6",X"23",X"CD",X"24",X"07",X"21",X"39",X"20",
+		X"11",X"6E",X"21",X"CD",X"24",X"07",X"CD",X"16",X"07",X"3E",X"01",X"32",X"58",X"20",X"CD",X"A4",
+		X"04",X"CD",X"6F",X"03",X"3E",X"04",X"CD",X"61",X"01",X"CD",X"0A",X"06",X"3A",X"46",X"20",X"A7",
+		X"C2",X"78",X"03",X"3A",X"58",X"20",X"0F",X"DA",X"1C",X"03",X"CD",X"6F",X"03",X"CD",X"EC",X"06",
+		X"CD",X"0A",X"06",X"3E",X"01",X"32",X"30",X"20",X"3A",X"30",X"20",X"A7",X"C2",X"38",X"03",X"3E",
+		X"20",X"CD",X"61",X"01",X"3A",X"46",X"20",X"A7",X"C2",X"78",X"03",X"CD",X"0A",X"06",X"3A",X"2E",
+		X"20",X"A7",X"CA",X"5F",X"03",X"3E",X"80",X"CD",X"95",X"01",X"3E",X"80",X"CD",X"61",X"01",X"3A",
+		X"58",X"20",X"0F",X"D2",X"44",X"03",X"CD",X"3E",X"02",X"CD",X"16",X"07",X"C3",X"11",X"03",X"CD",
+		X"B2",X"05",X"CD",X"1E",X"05",X"C3",X"DC",X"05",X"CD",X"3E",X"02",X"CD",X"16",X"07",X"AF",X"32",
+		X"58",X"20",X"32",X"48",X"20",X"CD",X"A4",X"04",X"3E",X"04",X"CD",X"61",X"01",X"CD",X"DC",X"05",
+		X"CD",X"0A",X"06",X"DB",X"01",X"E6",X"06",X"CA",X"90",X"03",X"EE",X"04",X"CA",X"AE",X"04",X"EE",
+		X"06",X"C2",X"90",X"03",X"3A",X"46",X"20",X"3D",X"CA",X"90",X"03",X"3D",X"32",X"46",X"20",X"3E",
+		X"81",X"32",X"48",X"20",X"CD",X"A4",X"05",X"CD",X"1E",X"05",X"AF",X"32",X"40",X"20",X"CD",X"75",
+		X"07",X"CD",X"EC",X"06",X"3E",X"20",X"CD",X"61",X"01",X"3E",X"08",X"32",X"40",X"20",X"CD",X"0A",
+		X"06",X"3A",X"2E",X"20",X"A7",X"CA",X"E9",X"03",X"3E",X"80",X"CD",X"95",X"01",X"3E",X"80",X"CD",
+		X"61",X"01",X"3A",X"2E",X"20",X"A7",X"C2",X"E2",X"03",X"3A",X"2A",X"20",X"0F",X"D2",X"CE",X"03",
+		X"0F",X"DA",X"48",X"04",X"CD",X"EE",X"1F",X"CD",X"3E",X"02",X"3A",X"48",X"20",X"3C",X"E6",X"81",
+		X"32",X"48",X"20",X"3A",X"57",X"20",X"A7",X"3E",X"01",X"32",X"57",X"20",X"CA",X"B7",X"03",X"CD",
+		X"1E",X"05",X"3A",X"3C",X"20",X"A7",X"FA",X"F7",X"03",X"3A",X"29",X"22",X"47",X"3A",X"31",X"22",
+		X"B0",X"F4",X"75",X"07",X"3E",X"08",X"CD",X"61",X"01",X"CD",X"DC",X"05",X"3E",X"40",X"CD",X"61",
+		X"01",X"3E",X"01",X"32",X"2D",X"20",X"3E",X"20",X"CD",X"61",X"01",X"3E",X"80",X"CD",X"61",X"01",
+		X"3E",X"10",X"CD",X"61",X"01",X"C3",X"CE",X"03",X"3A",X"2A",X"20",X"A7",X"F5",X"CD",X"3E",X"02",
+		X"AF",X"E7",X"09",X"E7",X"0A",X"E7",X"0B",X"3E",X"1F",X"F7",X"0C",X"CD",X"4A",X"07",X"CD",X"0A",
+		X"06",X"F1",X"F2",X"6B",X"04",X"21",X"DA",X"4F",X"CD",X"F4",X"14",X"21",X"E2",X"1C",X"3A",X"48",
+		X"20",X"0F",X"DA",X"78",X"04",X"21",X"F9",X"1C",X"CD",X"F4",X"14",X"CD",X"01",X"07",X"3A",X"48",
+		X"20",X"A7",X"F2",X"93",X"04",X"3A",X"29",X"22",X"A7",X"F2",X"FA",X"03",X"3A",X"31",X"22",X"A7",
+		X"F2",X"FA",X"03",X"AF",X"32",X"48",X"20",X"CD",X"F6",X"04",X"3A",X"46",X"20",X"A7",X"CA",X"06",
+		X"03",X"C3",X"78",X"03",X"AF",X"E7",X"09",X"E7",X"0A",X"E7",X"0B",X"E7",X"0C",X"C9",X"3E",X"01",
+		X"32",X"48",X"20",X"21",X"46",X"20",X"35",X"CD",X"A4",X"05",X"CD",X"1E",X"05",X"AF",X"32",X"40",
+		X"20",X"CD",X"75",X"07",X"CD",X"EC",X"06",X"3E",X"20",X"CD",X"61",X"01",X"3E",X"08",X"32",X"40",
+		X"20",X"CD",X"0A",X"06",X"3A",X"2E",X"20",X"A7",X"CA",X"EC",X"04",X"3E",X"80",X"CD",X"95",X"01",
+		X"3E",X"80",X"CD",X"61",X"01",X"3A",X"2E",X"20",X"A7",X"C2",X"E5",X"04",X"3A",X"2A",X"20",X"0F",
+		X"D2",X"D1",X"04",X"C3",X"48",X"04",X"2A",X"26",X"22",X"EB",X"2A",X"2E",X"22",X"7C",X"BA",X"DA",
+		X"0B",X"05",X"C2",X"0A",X"05",X"7D",X"BB",X"DA",X"0B",X"05",X"EB",X"2A",X"43",X"20",X"7A",X"BC",
+		X"D8",X"C2",X"17",X"05",X"7B",X"BD",X"D8",X"EB",X"22",X"43",X"20",X"C3",X"0A",X"06",X"3A",X"48",
+		X"20",X"0F",X"21",X"39",X"20",X"11",X"26",X"22",X"06",X"08",X"DA",X"30",X"05",X"11",X"2E",X"22",
+		X"CD",X"34",X"16",X"21",X"68",X"20",X"11",X"36",X"22",X"06",X"D8",X"3A",X"48",X"20",X"0F",X"DA",
+		X"45",X"05",X"11",X"F6",X"22",X"CD",X"34",X"16",X"CD",X"16",X"07",X"3A",X"48",X"20",X"A7",X"C8",
+		X"3E",X"20",X"E7",X"0A",X"3A",X"48",X"20",X"0F",X"3E",X"20",X"D2",X"5E",X"05",X"AF",X"E7",X"0C",
+		X"06",X"10",X"CD",X"D3",X"07",X"7E",X"FE",X"38",X"C2",X"70",X"05",X"3E",X"01",X"EF",X"0A",X"C9",
+		X"7E",X"FE",X"33",X"C2",X"7B",X"05",X"3E",X"01",X"C3",X"DA",X"07",X"7E",X"FE",X"70",X"C2",X"86",
+		X"05",X"3E",X"10",X"EF",X"0C",X"C9",X"7E",X"FE",X"50",X"C2",X"95",X"05",X"3E",X"01",X"EF",X"0A",
+		X"3E",X"1F",X"C3",X"DA",X"07",X"7E",X"FE",X"3F",X"CA",X"90",X"05",X"23",X"23",X"23",X"23",X"05",
+		X"C2",X"65",X"05",X"C9",X"3E",X"04",X"CD",X"95",X"01",X"21",X"26",X"22",X"11",X"B6",X"23",X"CD",
+		X"24",X"07",X"DB",X"02",X"E6",X"03",X"87",X"21",X"D4",X"05",X"CD",X"2D",X"02",X"5F",X"23",X"56",
+		X"EB",X"22",X"28",X"22",X"22",X"30",X"22",X"3E",X"01",X"32",X"2D",X"22",X"32",X"35",X"22",X"AF",
+		X"32",X"57",X"20",X"C9",X"DC",X"05",X"D0",X"07",X"C4",X"09",X"AC",X"0D",X"21",X"34",X"1D",X"CD",
+		X"F4",X"14",X"21",X"5D",X"1D",X"CD",X"F4",X"14",X"21",X"68",X"1D",X"CD",X"F4",X"14",X"2A",X"43",
+		X"20",X"11",X"1D",X"30",X"CD",X"BE",X"06",X"2A",X"26",X"22",X"11",X"1D",X"27",X"CD",X"BE",X"06",
+		X"2A",X"2E",X"22",X"11",X"1D",X"39",X"CD",X"BE",X"06",X"C9",X"3A",X"46",X"20",X"21",X"01",X"3D",
+		X"CD",X"D9",X"06",X"CD",X"7B",X"06",X"60",X"69",X"11",X"01",X"2C",X"CD",X"BE",X"06",X"3A",X"59",
+		X"20",X"A7",X"CA",X"70",X"06",X"F3",X"2A",X"41",X"20",X"7C",X"B5",X"CA",X"59",X"06",X"EB",X"21",
+		X"00",X"00",X"22",X"41",X"20",X"2A",X"39",X"20",X"FB",X"7D",X"83",X"27",X"6F",X"7C",X"8A",X"27",
+		X"67",X"22",X"39",X"20",X"7B",X"21",X"1C",X"33",X"CD",X"D0",X"06",X"CD",X"C9",X"06",X"3E",X"40",
+		X"32",X"59",X"20",X"21",X"53",X"1D",X"CD",X"F4",X"14",X"FB",X"3A",X"48",X"20",X"A7",X"C8",X"2A",
+		X"39",X"20",X"0F",X"11",X"1D",X"27",X"DA",X"6C",X"06",X"11",X"1D",X"39",X"CD",X"BE",X"06",X"C9",
+		X"2A",X"53",X"1D",X"06",X"48",X"CD",X"E1",X"06",X"C3",X"59",X"06",X"2A",X"3B",X"20",X"11",X"A2",
+		X"06",X"01",X"00",X"00",X"7C",X"A7",X"F8",X"29",X"29",X"29",X"DA",X"95",X"06",X"7C",X"B5",X"C8",
+		X"13",X"13",X"C3",X"89",X"06",X"1A",X"81",X"27",X"4F",X"13",X"1A",X"88",X"27",X"47",X"13",X"C3",
+		X"89",X"06",X"92",X"81",X"96",X"40",X"48",X"20",X"24",X"10",X"12",X"05",X"56",X"02",X"28",X"01",
+		X"64",X"00",X"32",X"00",X"16",X"00",X"08",X"00",X"04",X"00",X"02",X"00",X"01",X"00",X"EB",X"D5",
+		X"7A",X"CD",X"D0",X"06",X"D1",X"7B",X"CD",X"D0",X"06",X"06",X"00",X"0E",X"08",X"C3",X"3D",X"16",
+		X"F5",X"0F",X"0F",X"0F",X"0F",X"CD",X"D9",X"06",X"F1",X"E6",X"0F",X"47",X"0E",X"08",X"C3",X"3D",
+		X"16",X"AF",X"11",X"20",X"00",X"77",X"19",X"05",X"C2",X"E5",X"06",X"C9",X"3E",X"80",X"CD",X"61",
+		X"01",X"3E",X"40",X"CD",X"61",X"01",X"3E",X"10",X"CD",X"61",X"01",X"3E",X"08",X"CD",X"61",X"01",
+		X"C9",X"21",X"F4",X"01",X"22",X"59",X"20",X"CD",X"DF",X"07",X"A7",X"F2",X"07",X"07",X"CD",X"E7",
+		X"07",X"06",X"68",X"C3",X"E1",X"06",X"21",X"00",X"24",X"06",X"00",X"70",X"23",X"7C",X"FE",X"40",
+		X"DA",X"19",X"07",X"C9",X"06",X"00",X"70",X"23",X"7C",X"BA",X"C2",X"26",X"07",X"7D",X"BB",X"C2",
+		X"26",X"07",X"C9",X"21",X"62",X"09",X"06",X"1A",X"36",X"00",X"23",X"05",X"C2",X"38",X"07",X"01",
+		X"06",X"00",X"09",X"7C",X"FE",X"40",X"DA",X"36",X"07",X"C9",X"3A",X"48",X"20",X"0F",X"11",X"39",
+		X"20",X"21",X"26",X"22",X"06",X"08",X"DA",X"5C",X"07",X"21",X"2E",X"22",X"CD",X"34",X"16",X"21",
+		X"36",X"22",X"11",X"68",X"20",X"06",X"C0",X"3A",X"48",X"20",X"0F",X"DA",X"71",X"07",X"21",X"F6",
+		X"22",X"CD",X"34",X"16",X"C9",X"CD",X"DC",X"05",X"CD",X"0A",X"06",X"3A",X"48",X"20",X"0F",X"21",
+		X"10",X"1D",X"DA",X"88",X"07",X"21",X"22",X"1D",X"CD",X"F4",X"14",X"C3",X"01",X"07",X"3A",X"2E",
+		X"20",X"E6",X"01",X"C2",X"89",X"09",X"21",X"18",X"8A",X"22",X"49",X"20",X"AF",X"32",X"4F",X"20",
+		X"21",X"8F",X"1B",X"22",X"4D",X"20",X"21",X"02",X"0F",X"22",X"4B",X"20",X"CD",X"1C",X"0A",X"DF",
+		X"01",X"2A",X"49",X"20",X"7C",X"C6",X"F8",X"67",X"3A",X"05",X"20",X"AC",X"47",X"3A",X"48",X"20",
+		X"FE",X"80",X"78",X"07",X"CA",X"CD",X"07",X"D2",X"AF",X"07",X"C3",X"D0",X"07",X"DA",X"AF",X"07",
+		X"C3",X"EF",X"07",X"CD",X"4F",X"0D",X"21",X"E8",X"20",X"C9",X"E7",X"0B",X"F7",X"0A",X"C9",X"3E",
+		X"00",X"D3",X"03",X"3A",X"5A",X"20",X"C9",X"3E",X"20",X"EF",X"0A",X"2A",X"10",X"1D",X"C9",X"21",
+		X"3D",X"20",X"34",X"CD",X"50",X"0A",X"3A",X"3C",X"20",X"A7",X"FA",X"84",X"09",X"3A",X"51",X"20");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw02.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw02.vhd
new file mode 100644
index 00000000..ef4b42fa
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw02.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity mw02 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of mw02 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"3D",X"32",X"51",X"20",X"F2",X"18",X"08",X"E6",X"0F",X"32",X"51",X"20",X"F3",X"2A",X"3B",X"20",
+		X"2B",X"22",X"3B",X"20",X"FB",X"C3",X"18",X"08",X"CD",X"79",X"0A",X"E6",X"F0",X"CA",X"4E",X"08",
+		X"21",X"51",X"20",X"35",X"EE",X"10",X"CA",X"2E",X"08",X"EE",X"30",X"CA",X"3E",X"08",X"2A",X"49",
+		X"20",X"7C",X"FE",X"28",X"DA",X"4E",X"08",X"25",X"22",X"49",X"20",X"C3",X"4E",X"08",X"2A",X"49",
+		X"20",X"7C",X"FE",X"E0",X"D2",X"4E",X"08",X"24",X"22",X"49",X"20",X"C3",X"4E",X"08",X"AF",X"32",
+		X"4F",X"20",X"CD",X"1C",X"0A",X"DF",X"01",X"3A",X"52",X"20",X"A7",X"CA",X"AF",X"07",X"01",X"00",
+		X"10",X"21",X"E8",X"20",X"7E",X"A7",X"CA",X"6C",X"08",X"F2",X"78",X"08",X"23",X"23",X"23",X"23",
+		X"0C",X"05",X"C2",X"64",X"08",X"C3",X"AF",X"07",X"E5",X"C5",X"57",X"79",X"21",X"68",X"20",X"87",
+		X"87",X"87",X"CD",X"2D",X"02",X"7E",X"FE",X"28",X"D2",X"A1",X"08",X"23",X"5E",X"3A",X"4A",X"20",
+		X"C6",X"02",X"47",X"C6",X"0A",X"BB",X"DA",X"A1",X"08",X"23",X"23",X"7B",X"86",X"B8",X"D2",X"A6",
+		X"08",X"C1",X"E1",X"C3",X"6C",X"08",X"7A",X"FE",X"40",X"CA",X"98",X"09",X"E6",X"F0",X"87",X"B1",
+		X"3C",X"32",X"2C",X"20",X"3E",X"3F",X"32",X"0A",X"20",X"7A",X"FE",X"40",X"C1",X"E1",X"36",X"00",
+		X"11",X"24",X"FA",X"FA",X"D1",X"08",X"FE",X"70",X"11",X"E0",X"FC",X"DA",X"D1",X"08",X"11",X"30",
+		X"F8",X"2A",X"3B",X"20",X"19",X"7C",X"A7",X"FA",X"4A",X"09",X"3E",X"04",X"EF",X"0A",X"3E",X"20",
+		X"EF",X"0B",X"DF",X"03",X"AF",X"32",X"66",X"20",X"D5",X"CD",X"50",X"0A",X"2A",X"49",X"20",X"3A",
+		X"51",X"20",X"3D",X"32",X"51",X"20",X"0F",X"DA",X"FF",X"08",X"25",X"25",X"C3",X"01",X"09",X"24",
+		X"24",X"22",X"49",X"20",X"CD",X"1C",X"0A",X"D1",X"2A",X"3B",X"20",X"2B",X"2B",X"2B",X"2B",X"2B",
+		X"2B",X"00",X"00",X"22",X"3B",X"20",X"13",X"13",X"13",X"13",X"13",X"13",X"00",X"00",X"7A",X"A7",
+		X"FA",X"E2",X"08",X"06",X"01",X"3E",X"04",X"F7",X"0A",X"3E",X"20",X"F7",X"0B",X"3E",X"01",X"32",
+		X"30",X"20",X"AF",X"32",X"0A",X"20",X"78",X"E6",X"02",X"C2",X"43",X"09",X"3A",X"48",X"20",X"A7",
+		X"F2",X"AF",X"07",X"78",X"32",X"2A",X"20",X"CD",X"C0",X"01",X"22",X"3B",X"20",X"3E",X"04",X"EF",
+		X"0A",X"3E",X"20",X"EF",X"0B",X"2A",X"49",X"20",X"11",X"FE",X"FD",X"19",X"22",X"49",X"20",X"21",
+		X"05",X"17",X"22",X"4B",X"20",X"21",X"54",X"1C",X"22",X"4D",X"20",X"CD",X"1C",X"0A",X"3E",X"64",
+		X"32",X"51",X"20",X"21",X"51",X"20",X"35",X"CA",X"7F",X"09",X"DF",X"01",X"C3",X"73",X"09",X"06",
+		X"03",X"C3",X"25",X"09",X"06",X"83",X"C3",X"25",X"09",X"3E",X"7F",X"32",X"0A",X"20",X"AF",X"32",
+		X"2E",X"20",X"11",X"18",X"FC",X"C3",X"D1",X"08",X"C1",X"E1",X"CD",X"FC",X"09",X"DF",X"01",X"CD",
+		X"50",X"0A",X"21",X"18",X"8A",X"22",X"49",X"20",X"CD",X"1C",X"0A",X"DF",X"01",X"3E",X"02",X"32",
+		X"2D",X"20",X"3E",X"10",X"EF",X"0A",X"11",X"DC",X"05",X"DB",X"02",X"E6",X"08",X"CA",X"C3",X"09",
+		X"11",X"E8",X"03",X"2A",X"3B",X"20",X"23",X"23",X"23",X"23",X"23",X"23",X"22",X"3B",X"20",X"E5",
+		X"D5",X"CD",X"1C",X"0A",X"D1",X"E1",X"DF",X"02",X"1B",X"1B",X"1B",X"1B",X"1B",X"1B",X"7A",X"A7",
+		X"F2",X"C3",X"09",X"3E",X"10",X"F7",X"0A",X"3E",X"80",X"32",X"2D",X"20",X"3C",X"32",X"30",X"20",
+		X"DF",X"01",X"3A",X"2D",X"20",X"A7",X"C2",X"F0",X"09",X"C3",X"AF",X"07",X"21",X"8F",X"19",X"11",
+		X"AD",X"1B",X"3A",X"FC",X"1F",X"86",X"23",X"47",X"7D",X"AB",X"C2",X"12",X"0A",X"7C",X"AA",X"CA",
+		X"16",X"0A",X"78",X"C3",X"05",X"0A",X"78",X"A7",X"C8",X"C3",X"30",X"0A",X"2A",X"49",X"20",X"CD",
+		X"70",X"15",X"EB",X"2A",X"4B",X"20",X"E5",X"2A",X"4D",X"20",X"C1",X"EB",X"AF",X"32",X"52",X"20",
+		X"E5",X"C5",X"1A",X"A6",X"CA",X"3A",X"0A",X"32",X"52",X"20",X"1A",X"B6",X"77",X"13",X"23",X"0D",
+		X"C2",X"32",X"0A",X"C1",X"05",X"E1",X"C8",X"D5",X"11",X"20",X"00",X"19",X"D1",X"C3",X"30",X"0A",
+		X"2A",X"49",X"20",X"CD",X"70",X"15",X"EB",X"2A",X"4B",X"20",X"E5",X"2A",X"4D",X"20",X"C1",X"EB",
+		X"E5",X"C5",X"00",X"1A",X"AE",X"77",X"23",X"13",X"0D",X"C2",X"62",X"0A",X"C1",X"E1",X"05",X"C8",
+		X"D5",X"11",X"20",X"00",X"19",X"D1",X"C3",X"60",X"0A",X"3A",X"48",X"20",X"A7",X"CA",X"9A",X"0A",
+		X"F2",X"91",X"0A",X"0F",X"DA",X"91",X"0A",X"DB",X"00",X"07",X"07",X"47",X"DB",X"02",X"C3",X"96",
+		X"0A",X"DB",X"00",X"47",X"DB",X"01",X"0F",X"E6",X"38",X"C9",X"3A",X"5B",X"20",X"C6",X"10",X"07",
+		X"E6",X"38",X"C9",X"AF",X"32",X"5C",X"20",X"32",X"64",X"20",X"3E",X"64",X"32",X"66",X"20",X"3E",
+		X"20",X"32",X"65",X"20",X"3E",X"01",X"32",X"5F",X"20",X"3A",X"2C",X"20",X"A7",X"C2",X"8D",X"0C",
+		X"3A",X"E8",X"20",X"FE",X"40",X"CA",X"9F",X"0C",X"3E",X"0F",X"F7",X"0C",X"3A",X"58",X"20",X"A7",
+		X"CA",X"FA",X"0A",X"21",X"66",X"20",X"35",X"C2",X"DF",X"0A",X"36",X"64",X"C3",X"14",X"0B",X"CD",
+		X"DC",X"0C",X"DF",X"01",X"C3",X"B9",X"0A",X"CD",X"79",X"0A",X"E6",X"08",X"C2",X"3E",X"0B",X"3A",
+		X"5C",X"20",X"E6",X"01",X"32",X"5C",X"20",X"C3",X"3E",X"0B",X"CD",X"79",X"0A",X"E6",X"08",X"C2",
+		X"0D",X"0B",X"3A",X"5C",X"20",X"E6",X"01",X"32",X"5C",X"20",X"C3",X"DF",X"0A",X"3A",X"5C",X"20",
+		X"A7",X"C2",X"DF",X"0A",X"3A",X"0A",X"20",X"E6",X"FF",X"C2",X"DF",X"0A",X"3E",X"03",X"32",X"5C",
+		X"20",X"3E",X"02",X"EF",X"0A",X"3E",X"08",X"32",X"67",X"20",X"F3",X"2A",X"3B",X"20",X"2B",X"2B",
+		X"22",X"3B",X"20",X"FB",X"2A",X"49",X"20",X"11",X"10",X"07",X"19",X"C3",X"66",X"0B",X"CD",X"DC",
+		X"0C",X"DF",X"01",X"11",X"05",X"0D",X"06",X"01",X"2A",X"5D",X"20",X"CD",X"DD",X"15",X"21",X"67",
+		X"20",X"35",X"C2",X"59",X"0B",X"3E",X"02",X"F7",X"0A",X"2A",X"5D",X"20",X"2C",X"2C",X"2C",X"2C",
+		X"7D",X"FE",X"D8",X"D2",X"D7",X"0B",X"22",X"5D",X"20",X"11",X"05",X"0D",X"06",X"01",X"CD",X"A0",
+		X"15",X"DF",X"01",X"79",X"A7",X"CA",X"E7",X"0A",X"01",X"00",X"10",X"21",X"E8",X"20",X"7E",X"A7",
+		X"CA",X"86",X"0B",X"F2",X"94",X"0B",X"23",X"23",X"23",X"23",X"0C",X"05",X"C2",X"7E",X"0B",X"DF",
+		X"01",X"C3",X"E7",X"0A",X"FE",X"40",X"CA",X"E7",X"0A",X"E5",X"C5",X"57",X"79",X"21",X"68",X"20",
+		X"87",X"87",X"87",X"CD",X"2D",X"02",X"D5",X"EB",X"2A",X"5D",X"20",X"EB",X"1C",X"1C",X"1C",X"7B",
+		X"4E",X"B9",X"DA",X"D1",X"0B",X"23",X"7A",X"46",X"B8",X"DA",X"D1",X"0B",X"23",X"23",X"23",X"7E",
+		X"87",X"87",X"87",X"81",X"BB",X"DA",X"D1",X"0B",X"23",X"7E",X"E6",X"1F",X"80",X"BA",X"D2",X"E2",
+		X"0B",X"D1",X"C1",X"E1",X"C3",X"86",X"0B",X"3A",X"5C",X"20",X"E6",X"FE",X"32",X"5C",X"20",X"C3",
+		X"E2",X"0A",X"D1",X"C1",X"E1",X"7A",X"FE",X"40",X"06",X"00",X"D2",X"F8",X"0B",X"3A",X"3D",X"20",
+		X"E6",X"07",X"47",X"3A",X"3F",X"20",X"80",X"47",X"7A",X"0F",X"0F",X"0F",X"0F",X"E6",X"0F",X"57",
+		X"59",X"21",X"08",X"0D",X"CD",X"2D",X"02",X"80",X"4F",X"06",X"00",X"2A",X"41",X"20",X"09",X"22",
+		X"41",X"20",X"3A",X"64",X"20",X"A7",X"CA",X"26",X"0C",X"D5",X"2A",X"63",X"20",X"44",X"4D",X"2A",
+		X"5F",X"20",X"CD",X"7F",X"15",X"D1",X"7B",X"21",X"E8",X"20",X"87",X"87",X"CD",X"2D",X"02",X"36",
+		X"00",X"7A",X"FE",X"04",X"D2",X"81",X"0C",X"3E",X"08",X"EF",X"0A",X"7B",X"87",X"87",X"87",X"21",
+		X"68",X"20",X"CD",X"2D",X"02",X"D6",X"02",X"4F",X"23",X"7E",X"D6",X"02",X"47",X"C5",X"7A",X"87",
+		X"87",X"21",X"10",X"0D",X"CD",X"2D",X"02",X"5F",X"23",X"56",X"23",X"4E",X"23",X"46",X"21",X"64",
+		X"20",X"70",X"2B",X"71",X"2B",X"72",X"2B",X"73",X"E1",X"22",X"5F",X"20",X"3A",X"5C",X"20",X"E6",
+		X"FE",X"32",X"5C",X"20",X"DF",X"01",X"CD",X"25",X"15",X"3E",X"32",X"32",X"65",X"20",X"C3",X"E2",
+		X"0A",X"FE",X"05",X"C2",X"3B",X"0C",X"3E",X"17",X"E7",X"0B",X"C3",X"3B",X"0C",X"3D",X"57",X"E6",
+		X"1F",X"4F",X"7A",X"1F",X"57",X"AF",X"32",X"2C",X"20",X"32",X"66",X"20",X"C3",X"E5",X"0B",X"21",
+		X"65",X"20",X"35",X"F2",X"D0",X"0C",X"36",X"20",X"3A",X"64",X"20",X"3C",X"FE",X"04",X"C2",X"B3",
+		X"0C",X"3E",X"00",X"32",X"64",X"20",X"3E",X"0F",X"F7",X"0C",X"3A",X"2D",X"20",X"E6",X"02",X"C2",
+		X"D0",X"0C",X"21",X"D8",X"0C",X"3A",X"64",X"20",X"3D",X"E6",X"03",X"CD",X"2D",X"02",X"EF",X"0C",
+		X"CD",X"DC",X"0C",X"DF",X"01",X"C3",X"B9",X"0A",X"01",X"04",X"02",X"08",X"3A",X"64",X"20",X"A7",
+		X"C8",X"21",X"65",X"20",X"35",X"C0",X"2B",X"46",X"36",X"00",X"2B",X"4E",X"2B",X"2B",X"2B",X"7E",
+		X"2B",X"6E",X"67",X"CD",X"7F",X"15",X"3E",X"08",X"F7",X"0A",X"3A",X"35",X"20",X"FE",X"17",X"C0",
+		X"3E",X"1F",X"E7",X"0B",X"C9",X"0F",X"00",X"00",X"10",X"20",X"30",X"40",X"05",X"06",X"00",X"80",
+		X"19",X"1C",X"02",X"13",X"19",X"1C",X"02",X"13",X"19",X"1C",X"02",X"13",X"19",X"1C",X"02",X"13",
+		X"3F",X"1C",X"01",X"0C",X"3F",X"1C",X"01",X"0C",X"4A",X"1C",X"02",X"07",X"02",X"4F",X"05",X"28",
+		X"21",X"2D",X"20",X"7E",X"A7",X"36",X"00",X"C2",X"5C",X"0E",X"3A",X"48",X"20",X"A7",X"C4",X"37",
+		X"0F",X"21",X"E8",X"20",X"06",X"40",X"CD",X"40",X"00",X"CD",X"4F",X"0D",X"C3",X"66",X"0D",X"3E",
+		X"DF",X"F7",X"0A",X"F7",X"0B",X"F7",X"0C",X"3A",X"40",X"20",X"E6",X"07",X"C8",X"FE",X"06",X"F0",
+		X"3E",X"15",X"C3",X"DA",X"0F",X"0A",X"DF",X"01",X"3A",X"40",X"20",X"87",X"87",X"21",X"7F",X"0D",
+		X"CD",X"2D",X"02",X"5F",X"23",X"56",X"23",X"7E",X"23",X"66",X"6F",X"E9",X"06",X"06",X"08",X"49",
+		X"0D",X"49",X"0D",X"03",X"0F",X"58",X"0E",X"19",X"0F",X"58",X"0E",X"20",X"0F",X"58",X"0E",X"0C",
+		X"0F",X"58",X"0E",X"30",X"0F",X"58",X"0E",X"FA",X"0E",X"58",X"0E",X"FD",X"0E",X"58",X"0E",X"00",
+		X"0F",X"6C",X"0E",X"CF",X"0E",X"58",X"0E",X"D8",X"0E",X"58",X"0E",X"DF",X"0E",X"58",X"0E",X"EA",
+		X"0E",X"58",X"0E",X"F3",X"0E",X"58",X"0E",X"FA",X"0E",X"58",X"0E",X"FD",X"0E",X"58",X"0E",X"00",
+		X"0F",X"6C",X"0E",X"03",X"0F",X"58",X"0E",X"0C",X"0F",X"58",X"0E",X"10",X"0F",X"58",X"0E",X"19",
+		X"0F",X"58",X"0E",X"20",X"0F",X"58",X"0E",X"FA",X"0E",X"58",X"0E",X"FD",X"0E",X"58",X"0E",X"00",
+		X"0F",X"6C",X"0E",X"29",X"0F",X"58",X"0E",X"20",X"0F",X"58",X"0E",X"EA",X"0E",X"58",X"0E",X"03",
+		X"0F",X"58",X"0E",X"0C",X"0F",X"58",X"0E",X"FA",X"0E",X"58",X"0E",X"FD",X"0E",X"58",X"0E",X"00",
+		X"0F",X"6C",X"0E",X"7E",X"3C",X"C8",X"3D",X"23",X"32",X"2A",X"21",X"7E",X"23",X"E5",X"CD",X"43",
+		X"0F",X"E1",X"C3",X"03",X"0E",X"AF",X"32",X"29",X"21",X"3D",X"32",X"2A",X"21",X"3E",X"06",X"C3",
+		X"26",X"0E",X"0D",X"CD",X"2D",X"02",X"32",X"28",X"21",X"CD",X"ED",X"0F",X"3A",X"2A",X"21",X"FE",
+		X"10",X"F0",X"21",X"28",X"21",X"35",X"C2",X"29",X"0E",X"DF",X"01",X"C3",X"1D",X"0E",X"DF",X"01",
+		X"3A",X"29",X"21",X"A7",X"C0",X"3A",X"40",X"20",X"3C",X"32",X"40",X"20",X"FE",X"21",X"DA",X"56",
+		X"0E",X"3E",X"01",X"32",X"40",X"20",X"AF",X"C9",X"EB",X"CD",X"03",X"0E",X"CD",X"15",X"0E",X"CD",
+		X"3E",X"0E",X"C2",X"5C",X"0E",X"AF",X"32",X"2D",X"20",X"C3",X"49",X"0D",X"EB",X"3E",X"80",X"32",
+		X"2B",X"21",X"CD",X"03",X"0E",X"CD",X"15",X"0E",X"3A",X"2D",X"20",X"E6",X"02",X"C2",X"90",X"0E",
+		X"21",X"2B",X"21",X"35",X"CA",X"BD",X"0E",X"CD",X"3E",X"0E",X"C2",X"75",X"0E",X"C3",X"49",X"0D",
+		X"DF",X"01",X"CD",X"15",X"0E",X"21",X"26",X"32",X"06",X"08",X"3E",X"AA",X"CD",X"41",X"00",X"DF",
+		X"01",X"CD",X"15",X"0E",X"21",X"26",X"32",X"06",X"08",X"3E",X"55",X"CD",X"41",X"00",X"3A",X"2D",
+		X"20",X"A7",X"F2",X"90",X"0E",X"21",X"26",X"32",X"06",X"08",X"CD",X"40",X"00",X"21",X"E9",X"20",
+		X"06",X"08",X"36",X"00",X"23",X"23",X"23",X"23",X"05",X"C2",X"C2",X"0E",X"C3",X"5C",X"0E",X"00",
+		X"00",X"01",X"01",X"02",X"02",X"03",X"03",X"FF",X"00",X"04",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",
+		X"05",X"01",X"06",X"02",X"07",X"03",X"08",X"04",X"09",X"FF",X"00",X"0B",X"01",X"0C",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"00",X"0D",X"01",X"0E",X"02",X"0F",X"FF",X"00",X"0A",X"FF",X"00",X"13",X"FF",
+		X"00",X"12",X"FF",X"00",X"10",X"01",X"11",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"18",X"FF",X"FF",
+		X"00",X"16",X"01",X"17",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"19",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"14",X"01",X"15",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"1A",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"1B",X"FF",X"FF",X"FF",X"FF",X"FF",X"21",X"DB",X"17",X"11",X"8F",X"19",X"3A",X"FD",X"1F",
+		X"C3",X"05",X"0A",X"87",X"21",X"00",X"40",X"CD",X"2D",X"02",X"5F",X"23",X"56",X"3A",X"2A",X"21",
+		X"21",X"68",X"20",X"87",X"87",X"87",X"CD",X"2D",X"02",X"06",X"06",X"3A",X"40",X"20",X"EE",X"07",
+		X"4F",X"E6",X"07",X"C2",X"77",X"0F",X"79",X"D6",X"08",X"F2",X"6E",X"0F",X"3E",X"18",X"4F",X"05",
+		X"1A",X"91",X"91",X"00",X"77",X"13",X"23",X"CD",X"34",X"16",X"21",X"E8",X"20",X"3A",X"2A",X"21",
+		X"87",X"87",X"CD",X"2D",X"02",X"1A",X"13",X"77",X"47",X"78",X"FE",X"38",X"C2",X"96",X"0F",X"3E",
+		X"01",X"EF",X"0A",X"C3",X"E3",X"0F",X"78",X"FE",X"33",X"C2",X"A3",X"0F",X"3E",X"01",X"E7",X"0B",
+		X"C3",X"12",X"4D",X"78",X"FE",X"70",X"C2",X"BC",X"0F",X"3E",X"10",X"EF",X"0C",X"D5",X"E5",X"21",
+		X"AD",X"1B",X"11",X"E0",X"1F",X"3E",X"A3",X"C3",X"EB",X"4F",X"19",X"4D",X"78",X"FE",X"50",X"C2",
+		X"CD",X"0F",X"3E",X"01",X"EF",X"0A",X"3E",X"1F",X"E7",X"0B",X"C3",X"E3",X"0F",X"78",X"FE",X"3F",
+		X"C2",X"E5",X"0F",X"3E",X"1F",X"E7",X"0B",X"C3",X"12",X"4D",X"E7",X"0B",X"3E",X"01",X"EF",X"0A",
+		X"C9",X"4F",X"4F",X"DF",X"01",X"23",X"36",X"00",X"23",X"73",X"23",X"72",X"C9",X"3A",X"2A",X"21",
+		X"3C",X"32",X"2A",X"21",X"FE",X"10",X"F0",X"21",X"E8",X"20",X"87",X"87",X"F3",X"CD",X"2D",X"02");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw03.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw03.vhd
new file mode 100644
index 00000000..cee80385
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw03.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity mw03 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of mw03 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"FB",X"CA",X"ED",X"0F",X"47",X"3A",X"29",X"21",X"3C",X"32",X"29",X"21",X"23",X"7E",X"A7",X"CA",
+		X"7D",X"10",X"35",X"21",X"68",X"20",X"3A",X"2A",X"21",X"87",X"87",X"87",X"CD",X"2D",X"02",X"FE",
+		X"20",X"DA",X"E2",X"10",X"5E",X"23",X"56",X"78",X"78",X"FE",X"50",X"DA",X"48",X"10",X"DB",X"02",
+		X"E6",X"04",X"CA",X"36",X"10",X"1D",X"78",X"FE",X"66",X"C2",X"48",X"10",X"3A",X"4A",X"20",X"C6",
+		X"04",X"92",X"14",X"D2",X"48",X"10",X"15",X"15",X"C5",X"4B",X"42",X"23",X"5E",X"23",X"56",X"1A",
+		X"2B",X"77",X"23",X"13",X"1A",X"77",X"13",X"D5",X"23",X"5E",X"23",X"56",X"D5",X"E5",X"23",X"7E",
+		X"23",X"66",X"81",X"6F",X"7C",X"80",X"67",X"EB",X"E1",X"2B",X"2B",X"2B",X"2B",X"72",X"2B",X"73",
+		X"EB",X"C1",X"D1",X"F1",X"A7",X"F8",X"C3",X"25",X"15",X"13",X"C3",X"81",X"10",X"23",X"5E",X"23",
+		X"56",X"1A",X"A7",X"CA",X"79",X"10",X"FE",X"CD",X"CA",X"63",X"11",X"FE",X"EB",X"CA",X"9A",X"11",
+		X"FE",X"01",X"CA",X"2E",X"11",X"FE",X"C3",X"CA",X"23",X"11",X"FE",X"AF",X"CA",X"F0",X"10",X"21",
+		X"E8",X"20",X"3A",X"2A",X"21",X"87",X"87",X"CD",X"2D",X"02",X"7E",X"FE",X"70",X"01",X"D4",X"FE",
+		X"CA",X"BC",X"10",X"01",X"F6",X"FF",X"7E",X"FE",X"40",X"D2",X"C7",X"10",X"EB",X"F3",X"2A",X"3B",
+		X"20",X"09",X"22",X"3B",X"20",X"FB",X"EB",X"36",X"00",X"21",X"68",X"20",X"3A",X"2A",X"21",X"87",
+		X"87",X"87",X"CD",X"2D",X"02",X"5E",X"23",X"56",X"23",X"23",X"23",X"4E",X"23",X"46",X"EB",X"C3",
+		X"7F",X"15",X"3A",X"2A",X"21",X"21",X"E8",X"20",X"87",X"87",X"CD",X"2D",X"02",X"C3",X"AA",X"10",
+		X"3A",X"2A",X"21",X"21",X"E8",X"20",X"87",X"87",X"CD",X"2D",X"02",X"F6",X"80",X"77",X"13",X"1A",
+		X"4F",X"13",X"1A",X"47",X"13",X"23",X"1A",X"77",X"13",X"23",X"73",X"23",X"72",X"21",X"68",X"20",
+		X"3A",X"2A",X"21",X"87",X"87",X"87",X"CD",X"2D",X"02",X"11",X"06",X"00",X"19",X"71",X"23",X"70",
+		X"C3",X"AA",X"10",X"13",X"1A",X"4F",X"13",X"1A",X"47",X"C5",X"D1",X"C3",X"81",X"10",X"21",X"E8",
+		X"20",X"3A",X"2A",X"21",X"87",X"87",X"CD",X"2D",X"02",X"E6",X"7F",X"77",X"23",X"13",X"1A",X"4F",
+		X"13",X"1A",X"47",X"13",X"1A",X"13",X"77",X"23",X"73",X"23",X"72",X"21",X"68",X"20",X"3A",X"2A",
+		X"21",X"87",X"87",X"87",X"CD",X"2D",X"02",X"11",X"06",X"00",X"19",X"71",X"23",X"70",X"06",X"01",
+		X"C3",X"13",X"10",X"3A",X"2A",X"21",X"F5",X"06",X"10",X"0E",X"00",X"21",X"E8",X"20",X"7E",X"A7",
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+		X"08",X"00",X"00",X"00",X"08",X"08",X"08",X"08",X"08",X"00",X"00",X"00",X"04",X"08",X"08",X"08",
+		X"10",X"00",X"00",X"00",X"00",X"00",X"7B",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"40",X"00",X"00",X"00",X"FB",X"17",X"00",X"00",X"B0",
+		X"01",X"B8",X"03",X"5C",X"07",X"EE",X"0E",X"13",X"19",X"4F",X"1E",X"E8",X"02",X"4F",X"1E",X"13",
+		X"19",X"EE",X"0E",X"5C",X"07",X"B8",X"03",X"B0",X"01",X"00",X"00",X"DB",X"17",X"00",X"00",X"B0");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw04.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw04.vhd
new file mode 100644
index 00000000..3b6861b8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw04.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity mw04 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of mw04 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"01",X"B8",X"03",X"5C",X"07",X"EE",X"0E",X"F3",X"19",X"FF",X"1F",X"F8",X"03",X"FF",X"1F",X"F3",
+		X"19",X"EE",X"0E",X"5C",X"07",X"B8",X"03",X"B0",X"01",X"00",X"00",X"3B",X"18",X"00",X"00",X"80",
+		X"07",X"80",X"0F",X"C0",X"1D",X"E0",X"3B",X"F8",X"67",X"5E",X"7C",X"C7",X"08",X"5E",X"7C",X"F8",
+		X"67",X"E0",X"3B",X"C0",X"1D",X"80",X"0F",X"80",X"07",X"00",X"00",X"1B",X"18",X"00",X"00",X"80",
+		X"07",X"80",X"0F",X"C0",X"1D",X"E0",X"3B",X"F8",X"7F",X"5E",X"7C",X"FF",X"08",X"5E",X"7C",X"F8",
+		X"7F",X"E0",X"3B",X"C0",X"1D",X"80",X"0F",X"80",X"07",X"00",X"00",X"7B",X"18",X"00",X"00",X"F0",
+		X"0F",X"80",X"1F",X"80",X"34",X"E0",X"6F",X"38",X"79",X"9E",X"30",X"BF",X"1F",X"9E",X"30",X"38",
+		X"79",X"E0",X"6F",X"80",X"34",X"80",X"1F",X"F0",X"0F",X"00",X"00",X"5B",X"18",X"00",X"00",X"F0",
+		X"0F",X"80",X"1F",X"80",X"34",X"E0",X"6F",X"38",X"7F",X"9E",X"36",X"B1",X"1F",X"9E",X"36",X"38",
+		X"7F",X"E0",X"6F",X"80",X"34",X"80",X"1F",X"F0",X"0F",X"00",X"00",X"BB",X"18",X"00",X"00",X"F0",
+		X"0F",X"C8",X"13",X"40",X"02",X"E0",X"07",X"70",X"5F",X"BF",X"7B",X"58",X"70",X"BF",X"7B",X"70",
+		X"5F",X"E0",X"07",X"40",X"02",X"C8",X"13",X"F0",X"0F",X"00",X"00",X"9B",X"18",X"00",X"00",X"F0",
+		X"0F",X"C8",X"13",X"40",X"02",X"E0",X"07",X"70",X"5F",X"BF",X"7B",X"5E",X"7C",X"BF",X"7B",X"70",
+		X"5F",X"E0",X"07",X"40",X"02",X"C8",X"13",X"F0",X"0F",X"00",X"00",X"FB",X"18",X"00",X"00",X"F0",
+		X"01",X"F8",X"03",X"0C",X"06",X"06",X"0C",X"E3",X"18",X"BF",X"1F",X"1F",X"1F",X"BF",X"1F",X"E3",
+		X"18",X"06",X"0C",X"0C",X"06",X"F8",X"03",X"F0",X"01",X"00",X"00",X"1B",X"19",X"00",X"00",X"F0",
+		X"01",X"F8",X"03",X"0C",X"07",X"06",X"0F",X"E3",X"1F",X"B3",X"19",X"13",X"19",X"B3",X"19",X"FF",
+		X"18",X"1E",X"0C",X"1C",X"06",X"F8",X"03",X"F0",X"01",X"00",X"00",X"3B",X"19",X"00",X"00",X"F0",
+		X"01",X"F8",X"03",X"EC",X"06",X"E6",X"0C",X"E3",X"18",X"B3",X"19",X"13",X"19",X"B3",X"19",X"E3",
+		X"18",X"E6",X"0C",X"EC",X"06",X"F8",X"03",X"F0",X"01",X"00",X"00",X"DB",X"18",X"00",X"00",X"F0",
+		X"01",X"F8",X"03",X"1C",X"06",X"1E",X"0C",X"FF",X"18",X"B3",X"19",X"13",X"19",X"B3",X"19",X"E3",
+		X"1F",X"06",X"0F",X"0C",X"07",X"F8",X"03",X"F0",X"01",X"00",X"00",X"68",X"19",X"00",X"1C",X"2A",
+		X"75",X"6B",X"75",X"3D",X"2F",X"1E",X"0C",X"00",X"75",X"19",X"00",X"0C",X"1E",X"2F",X"3B",X"65",
+		X"7B",X"7D",X"32",X"1C",X"00",X"82",X"19",X"00",X"18",X"3C",X"7E",X"5A",X"5F",X"6B",X"57",X"2A",
+		X"1C",X"00",X"5B",X"19",X"00",X"1C",X"26",X"5B",X"6F",X"5D",X"72",X"7E",X"3C",X"18",X"00",X"59",
+		X"1A",X"03",X"00",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"1F",X"00",X"00",X"00",X"00",
+		X"3E",X"00",X"00",X"00",X"00",X"7C",X"00",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"00",X"F0",
+		X"01",X"00",X"00",X"00",X"E0",X"03",X"00",X"00",X"00",X"C0",X"0F",X"00",X"00",X"00",X"80",X"1F",
+		X"00",X"00",X"00",X"00",X"2F",X"00",X"00",X"10",X"00",X"7E",X"00",X"00",X"00",X"00",X"7E",X"00",
+		X"00",X"00",X"00",X"FC",X"00",X"00",X"00",X"00",X"E8",X"03",X"00",X"00",X"00",X"D0",X"0B",X"00",
+		X"00",X"00",X"F0",X"15",X"00",X"00",X"00",X"A0",X"2B",X"00",X"00",X"00",X"40",X"55",X"00",X"00",
+		X"00",X"80",X"EA",X"00",X"00",X"00",X"00",X"DD",X"03",X"00",X"00",X"00",X"36",X"05",X"00",X"00",
+		X"00",X"AA",X"08",X"00",X"00",X"00",X"1C",X"1B",X"00",X"00",X"00",X"58",X"36",X"00",X"00",X"00",
+		X"A0",X"59",X"00",X"00",X"00",X"40",X"67",X"00",X"00",X"00",X"C0",X"CC",X"01",X"00",X"00",X"80",
+		X"45",X"01",X"00",X"00",X"00",X"AB",X"03",X"00",X"00",X"00",X"50",X"06",X"00",X"00",X"00",X"A4",
+		X"0C",X"00",X"00",X"00",X"8C",X"05",X"00",X"00",X"00",X"18",X"09",X"00",X"00",X"00",X"30",X"11",
+		X"00",X"00",X"00",X"40",X"02",X"00",X"00",X"00",X"80",X"04",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"8F",X"19",X"03",X"00",X"00",X"00",X"00",
+		X"0F",X"00",X"00",X"00",X"00",X"1F",X"00",X"00",X"00",X"00",X"3E",X"00",X"00",X"00",X"00",X"7C",
+		X"00",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"00",X"F0",X"01",X"00",X"00",X"00",X"E0",X"07",
+		X"00",X"00",X"00",X"C0",X"0F",X"00",X"00",X"00",X"80",X"1F",X"00",X"00",X"00",X"00",X"2F",X"00",
+		X"00",X"00",X"00",X"6E",X"00",X"00",X"00",X"00",X"DA",X"00",X"00",X"00",X"00",X"EC",X"01",X"00",
+		X"00",X"00",X"A8",X"03",X"00",X"00",X"00",X"5C",X"0B",X"00",X"00",X"00",X"E0",X"16",X"00",X"00",
+		X"00",X"A0",X"2D",X"00",X"00",X"00",X"C0",X"71",X"00",X"00",X"00",X"80",X"E5",X"00",X"00",X"00",
+		X"00",X"CB",X"01",X"00",X"00",X"00",X"36",X"05",X"00",X"00",X"00",X"68",X"02",X"00",X"00",X"00",
+		X"94",X"0C",X"00",X"00",X"00",X"48",X"39",X"00",X"00",X"00",X"90",X"52",X"00",X"00",X"00",X"20",
+		X"A5",X"00",X"00",X"00",X"C0",X"48",X"01",X"00",X"00",X"80",X"05",X"02",X"00",X"00",X"00",X"2B",
+		X"05",X"00",X"00",X"00",X"54",X"0A",X"00",X"00",X"00",X"A8",X"14",X"00",X"00",X"00",X"94",X"01",
+		X"00",X"00",X"00",X"08",X"01",X"00",X"00",X"00",X"10",X"02",X"00",X"00",X"00",X"20",X"04",X"00",
+		X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"23",X"1B",X"00",X"00",X"20",X"00",X"30",X"00",X"30",X"00",X"30",X"00",X"34",
+		X"00",X"3C",X"00",X"2C",X"00",X"7C",X"00",X"7C",X"00",X"3C",X"00",X"3C",X"00",X"3C",X"00",X"3C",
+		X"00",X"3C",X"00",X"BC",X"00",X"7C",X"00",X"7C",X"00",X"7C",X"01",X"FE",X"00",X"7E",X"00",X"FE",
+		X"00",X"FE",X"01",X"7E",X"03",X"FE",X"0F",X"7E",X"0F",X"FC",X"01",X"FC",X"03",X"FC",X"00",X"7C",
+		X"01",X"7C",X"02",X"7C",X"04",X"3C",X"00",X"38",X"00",X"3C",X"00",X"7A",X"00",X"B8",X"00",X"38",
+		X"00",X"10",X"00",X"00",X"00",X"75",X"1B",X"40",X"A0",X"00",X"60",X"FF",X"F0",X"FF",X"60",X"00",
+		X"A0",X"40",X"82",X"1B",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",
+		X"00",X"6C",X"00",X"FE",X"03",X"6C",X"00",X"38",X"00",X"F7",X"01",X"7F",X"1F",X"1E",X"FE",X"7F",
+		X"1F",X"F7",X"01",X"38",X"00",X"6C",X"00",X"FE",X"03",X"6C",X"00",X"00",X"00",X"B9",X"1B",X"00",
+		X"00",X"1C",X"0E",X"3B",X"3B",X"0E",X"1C",X"00",X"00",X"AD",X"1B",X"00",X"00",X"1C",X"0E",X"3F",
+		X"3F",X"0E",X"1C",X"00",X"00",X"E3",X"1B",X"3E",X"7C",X"63",X"C6",X"DD",X"BB",X"DD",X"BB",X"63",
+		X"C6",X"3E",X"7C",X"00",X"00",X"00",X"00",X"3E",X"7C",X"63",X"C6",X"DD",X"BB",X"DD",X"BB",X"63",
+		X"C6",X"3E",X"7C",X"C5",X"1B",X"3E",X"7C",X"6B",X"B6",X"D5",X"AB",X"D5",X"AB",X"6B",X"D6",X"BE",
+		X"7D",X"C0",X"03",X"C0",X"03",X"BE",X"7D",X"6B",X"D6",X"D5",X"AB",X"D5",X"AB",X"6B",X"D6",X"3E",
+		X"7C",X"0D",X"1C",X"00",X"00",X"3C",X"05",X"FF",X"1F",X"3C",X"05",X"00",X"00",X"01",X"1C",X"00",
+		X"00",X"3C",X"05",X"F7",X"1F",X"3C",X"05",X"00",X"00",X"80",X"00",X"80",X"02",X"50",X"48",X"54",
+		X"21",X"2A",X"04",X"40",X"0B",X"A8",X"24",X"D2",X"0D",X"E0",X"0A",X"F8",X"C7",X"F0",X"24",X"61",
+		X"04",X"D8",X"1A",X"54",X"25",X"00",X"02",X"88",X"15",X"A4",X"22",X"00",X"00",X"80",X"00",X"54",
+		X"2A",X"BB",X"56",X"30",X"E8",X"30",X"56",X"B3",X"2A",X"94",X"80",X"B4",X"28",X"1D",X"80",X"43",
+		X"52",X"24",X"80",X"5C",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"10",X"20",X"00",X"40",X"20",
+		X"39",X"12",X"2A",X"80",X"C8",X"46",X"09",X"04",X"10",X"95",X"8F",X"A7",X"02",X"00",X"88",X"F1",
+		X"5E",X"04",X"00",X"55",X"34",X"29",X"22",X"90",X"B2",X"D2",X"76",X"11",X"24",X"F5",X"6F",X"4B",
+		X"08",X"40",X"FF",X"FF",X"BB",X"02",X"C0",X"FF",X"FF",X"7F",X"02",X"BB",X"FF",X"FF",X"FF",X"DD",
+		X"C0",X"FF",X"FF",X"7F",X"00",X"20",X"DF",X"FF",X"1F",X"03",X"00",X"F5",X"EF",X"C9",X"20",X"92",
+		X"EC",X"52",X"76",X"49",X"48",X"CA",X"7C",X"77",X"10",X"04",X"A5",X"97",X"0D",X"00",X"10",X"52",
+		X"6A",X"55",X"09",X"08",X"28",X"D5",X"22",X"13",X"00",X"94",X"38",X"05",X"00",X"00",X"04",X"10",
+		X"08",X"00",X"00",X"20",X"10",X"00",X"00",X"1A",X"2C",X"0C",X"03",X"0D",X"18",X"0C",X"14",X"12",
+		X"17",X"10",X"2E",X"1D",X"12",X"16",X"0E",X"00",X"18",X"28",X"05",X"03",X"1B",X"0E",X"0A",X"0D",
+		X"22",X"00",X"10",X"29",X"12",X"00",X"10",X"0A",X"16",X"0E",X"2E",X"18",X"1F",X"0E",X"1B",X"2E",
+		X"19",X"15",X"0A",X"22",X"0E",X"1B",X"2E",X"01",X"00",X"10",X"29",X"12",X"00",X"10",X"0A",X"16",
+		X"0E",X"2E",X"18",X"1F",X"0E",X"1B",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"2E",X"02",X"00",
+		X"10",X"2B",X"0D",X"00",X"1D",X"1B",X"22",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"24",X"01",
+		X"25",X"00",X"10",X"2B",X"0D",X"00",X"1D",X"1B",X"22",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",
+		X"24",X"02",X"25",X"00",X"1E",X"25",X"1A",X"00",X"1C",X"0C",X"18",X"1B",X"0E",X"24",X"01",X"25",
+		X"2E",X"11",X"12",X"2B",X"1C",X"0C",X"18",X"1B",X"0E",X"2E",X"1C",X"0C",X"18",X"1B",X"0E",X"24",
+		X"02",X"25",X"00",X"1C",X"2D",X"05",X"00",X"19",X"18",X"12",X"17",X"1D",X"00",X"01",X"36",X"06",
+		X"00",X"0C",X"1B",X"0E",X"0D",X"12",X"1D",X"00",X"01",X"25",X"06",X"00",X"0E",X"17",X"0E",X"1B",
+		X"10",X"22",X"00",X"14",X"30",X"04",X"0F",X"19",X"1E",X"1C",X"11",X"01",X"12",X"2A",X"0F",X"0F",
+		X"01",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"2E",X"0B",X"1E",X"1D",X"1D",X"18",X"17",X"00",
+		X"10",X"2A",X"10",X"0F",X"02",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"1C",X"2E",X"0B",X"1E",
+		X"1D",X"1D",X"18",X"17",X"00",X"03",X"27",X"15",X"00",X"27",X"2E",X"1C",X"11",X"12",X"17",X"2E",
+		X"17",X"12",X"11",X"18",X"17",X"2E",X"14",X"12",X"14",X"0A",X"14",X"1E",X"2E",X"27",X"00",X"1A",
+		X"2C",X"0A",X"1F",X"18",X"23",X"16",X"0A",X"2E",X"2E",X"20",X"0A",X"1B",X"1C",X"01",X"18",X"2F",
+		X"05",X"1F",X"15",X"0E",X"1D",X"2F",X"1C",X"01",X"16",X"2B",X"0C",X"1F",X"1D",X"1B",X"0A",X"1F",
+		X"0E",X"15",X"29",X"0F",X"12",X"10",X"11",X"1D",X"01",X"14",X"2B",X"0B",X"1F",X"1C",X"19",X"0A",
+		X"0C",X"0E",X"2E",X"20",X"18",X"1B",X"15",X"0D",X"00",X"10",X"2E",X"07",X"00",X"27",X"1C",X"0C",
+		X"18",X"1B",X"0E",X"27",X"01",X"0E",X"2B",X"0E",X"00",X"1E",X"0F",X"18",X"2E",X"2E",X"2E",X"2E",
+		X"01",X"00",X"00",X"2C",X"05",X"00",X"00",X"01",X"0C",X"2B",X"0C",X"00",X"16",X"0E",X"1D",X"0E",
+		X"18",X"2E",X"2E",X"05",X"00",X"2C",X"07",X"00",X"01",X"0A",X"2B",X"0A",X"00",X"0C",X"18",X"16",
+		X"0E",X"1D",X"2E",X"2E",X"08",X"00",X"00",X"00",X"12",X"2A",X"0F",X"00",X"27",X"0C",X"11",X"0A",
+		X"1B",X"10",X"0E",X"2E",X"0E",X"17",X"0E",X"1B",X"10",X"22",X"27",X"01",X"10",X"2B",X"0F",X"00",
+		X"0D",X"18",X"0C",X"14",X"12",X"17",X"10",X"2E",X"2E",X"2A",X"01",X"05",X"00",X"00",X"00",X"01",
+		X"0E",X"29",X"13",X"00",X"27",X"0C",X"1B",X"0A",X"1C",X"11",X"2E",X"15",X"18",X"1C",X"1D",X"2E",
+		X"0E",X"17",X"0E",X"1B",X"10",X"22",X"27",X"01",X"0C",X"2B",X"0F",X"00",X"1E",X"0F",X"18",X"2E",
+		X"2E",X"2E",X"2E",X"2E",X"2E",X"2B",X"01",X"05",X"00",X"00",X"00",X"01",X"0A",X"2B",X"0E",X"00",
+		X"16",X"0E",X"1D",X"0E",X"18",X"2E",X"2E",X"2E",X"2E",X"2B",X"08",X"00",X"00",X"00",X"01",X"08",
+		X"2B",X"0F",X"00",X"0C",X"18",X"16",X"0E",X"1D",X"2E",X"2E",X"2E",X"2E",X"2B",X"02",X"00",X"00",
+		X"00",X"00",X"01",X"06",X"2B",X"0F",X"00",X"16",X"12",X"1C",X"1C",X"12",X"15",X"0E",X"2E",X"2E",
+		X"2B",X"01",X"00",X"00",X"00",X"00",X"00",X"14",X"2D",X"0B",X"00",X"12",X"17",X"1C",X"0E",X"1B",
+		X"1D",X"2E",X"0C",X"18",X"12",X"17",X"01",X"12",X"2B",X"0E",X"00",X"01",X"2E",X"18",X"1B",X"2E",
+		X"02",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"1C",X"01",X"10",X"2B",X"0F",X"00",X"01",X"2E",
+		X"19",X"15",X"0A",X"22",X"0E",X"1B",X"2E",X"01",X"2E",X"0C",X"18",X"12",X"17",X"01",X"0E",X"2A",
+		X"11",X"00",X"02",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"1C",X"2E",X"02",X"2E",X"0C",X"18",
+		X"12",X"17",X"1C",X"00",X"DE",X"88",X"D0",X"B8",X"C2",X"26",X"B6",X"CC",X"B0",X"60",X"A8",X"44",
+		X"A6",X"9C",X"9A",X"FC",X"8B",X"C8",X"7C",X"90",X"76",X"24",X"7C",X"90",X"68",X"C0",X"60",X"60",
+		X"4C",X"DC",X"48",X"84",X"3E",X"30",X"34",X"F8",X"2C",X"48",X"18",X"30",X"07",X"07",X"07",X"07",
+		X"45",X"1F",X"0A",X"15",X"0A",X"40",X"1F",X"15",X"0A",X"15",X"51",X"1F",X"00",X"0A",X"07",X"0A",
+		X"00",X"58",X"1F",X"00",X"05",X"0E",X"05",X"00",X"5F",X"1F",X"00",X"0A",X"0D",X"0A",X"00",X"4A",
+		X"1F",X"00",X"05",X"0B",X"05",X"00",X"66",X"1F",X"FF",X"0F",X"6A",X"1F",X"00",X"00",X"80",X"07",
+		X"E0",X"1B",X"F8",X"77",X"47",X"5C",X"FC",X"77",X"F0",X"3B",X"E0",X"1D",X"C0",X"0F",X"80",X"07",
+		X"00",X"00",X"A6",X"1F",X"00",X"00",X"00",X"00",X"D8",X"00",X"DC",X"01",X"FE",X"03",X"73",X"06",
+		X"FD",X"05",X"FF",X"07",X"FF",X"07",X"FF",X"07",X"FD",X"05",X"73",X"06",X"FE",X"03",X"DC",X"01",
+		X"D8",X"00",X"00",X"00",X"00",X"00",X"CA",X"1F",X"00",X"00",X"00",X"00",X"F8",X"00",X"DC",X"01",
+		X"DE",X"03",X"53",X"06",X"DD",X"05",X"DF",X"07",X"DF",X"07",X"DF",X"07",X"FD",X"05",X"73",X"06",
+		X"FE",X"03",X"FC",X"01",X"F8",X"00",X"00",X"00",X"00",X"00",X"82",X"1F",X"00",X"00",X"00",X"00",
+		X"F8",X"00",X"FC",X"01",X"FE",X"03",X"73",X"06",X"FD",X"05",X"DF",X"07",X"DF",X"07",X"DF",X"07",
+		X"DD",X"05",X"53",X"06",X"DE",X"03",X"DC",X"01",X"F8",X"00",X"00",X"00",X"00",X"00",X"3A",X"2A",
+		X"21",X"FE",X"10",X"E2",X"EE",X"1F",X"C3",X"4A",X"07",X"FF",X"85",X"78",X"E9",X"01",X"6C",X"FF");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw05.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw05.vhd
new file mode 100644
index 00000000..02127e5a
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw05.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity mw05 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of mw05 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"40",X"40",X"6D",X"40",X"B0",X"40",X"EB",X"40",X"1C",X"41",X"A4",X"41",X"DF",X"41",X"12",X"42",
+		X"45",X"42",X"78",X"42",X"21",X"46",X"A4",X"42",X"85",X"43",X"62",X"44",X"CA",X"44",X"F6",X"44",
+		X"22",X"45",X"A3",X"45",X"E4",X"45",X"2D",X"46",X"34",X"49",X"99",X"49",X"FD",X"49",X"27",X"4B",
+		X"4F",X"4C",X"49",X"4D",X"41",X"4E",X"69",X"4E",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"D0",X"70",X"DB",X"17",X"02",X"0F",X"20",X"01",X"FE",X"00",X"28",X"CD",X"53",X"40",X"01",X"FD",
+		X"01",X"30",X"76",X"D0",X"70",X"1B",X"18",X"02",X"0F",X"02",X"01",X"FE",X"00",X"20",X"01",X"FE",
+		X"01",X"00",X"F8",X"00",X"01",X"FE",X"01",X"18",X"01",X"FF",X"FF",X"20",X"76",X"D0",X"30",X"DB",
+		X"17",X"02",X"0F",X"20",X"01",X"FE",X"00",X"10",X"CD",X"90",X"40",X"01",X"FE",X"01",X"08",X"01",
+		X"FE",X"FF",X"08",X"01",X"FD",X"01",X"10",X"AF",X"FE",X"FF",X"06",X"01",X"FE",X"01",X"10",X"76",
+		X"D0",X"30",X"1B",X"18",X"02",X"0F",X"02",X"01",X"FE",X"01",X"18",X"01",X"FE",X"FF",X"10",X"01",
+		X"FE",X"00",X"10",X"AF",X"FE",X"FF",X"08",X"01",X"FE",X"FF",X"08",X"01",X"FE",X"01",X"10",X"76",
+		X"D0",X"A0",X"DB",X"17",X"02",X"0F",X"20",X"01",X"FE",X"00",X"18",X"CD",X"C7",X"40",X"01",X"FD",
+		X"00",X"08",X"01",X"FD",X"FF",X"18",X"76",X"D0",X"A0",X"1B",X"18",X"02",X"0F",X"02",X"01",X"FE",
+		X"00",X"18",X"01",X"FE",X"01",X"08",X"01",X"FE",X"FF",X"08",X"01",X"FE",X"00",X"10",X"AF",X"FE",
+		X"FF",X"08",X"01",X"FE",X"01",X"10",X"01",X"FE",X"FF",X"10",X"76",X"D0",X"D0",X"DB",X"17",X"02",
+		X"0F",X"20",X"01",X"FE",X"00",X"10",X"CD",X"0E",X"41",X"01",X"FE",X"00",X"10",X"AF",X"FF",X"FF",
+		X"10",X"01",X"FE",X"FF",X"08",X"01",X"FE",X"01",X"10",X"01",X"FD",X"00",X"18",X"76",X"D0",X"D0",
+		X"1B",X"18",X"02",X"0F",X"02",X"01",X"FE",X"00",X"20",X"C3",X"5E",X"40",X"D0",X"88",X"5B",X"18",
+		X"02",X"0F",X"10",X"CD",X"3C",X"41",X"CD",X"51",X"41",X"01",X"FE",X"FF",X"0A",X"AF",X"FE",X"FF",
+		X"02",X"01",X"FE",X"01",X"0A",X"AF",X"FE",X"01",X"02",X"C3",X"29",X"41",X"D0",X"76",X"5B",X"18",
+		X"02",X"0F",X"10",X"AF",X"00",X"00",X"12",X"CD",X"66",X"41",X"01",X"FF",X"FF",X"10",X"C3",X"29",
+		X"41",X"D0",X"9A",X"5B",X"18",X"02",X"0F",X"10",X"AF",X"00",X"00",X"12",X"CD",X"77",X"41",X"01",
+		X"FF",X"01",X"10",X"C3",X"29",X"41",X"D0",X"5C",X"5B",X"18",X"02",X"0F",X"10",X"AF",X"00",X"00",
+		X"12",X"CD",X"88",X"41",X"C3",X"4A",X"41",X"D0",X"B4",X"5B",X"18",X"02",X"0F",X"10",X"AF",X"00",
+		X"00",X"12",X"CD",X"96",X"41",X"C3",X"5F",X"41",X"D0",X"40",X"5B",X"18",X"02",X"0F",X"10",X"AF",
+		X"00",X"00",X"12",X"C3",X"4A",X"41",X"D0",X"CE",X"5B",X"18",X"02",X"0F",X"10",X"AF",X"00",X"00",
+		X"12",X"C3",X"5F",X"41",X"D0",X"30",X"5B",X"19",X"01",X"0B",X"50",X"CD",X"B9",X"41",X"01",X"FE",
+		X"01",X"14",X"01",X"FE",X"FF",X"14",X"C3",X"AE",X"41",X"D0",X"40",X"75",X"19",X"01",X"0B",X"50",
+		X"AF",X"00",X"00",X"10",X"CD",X"CA",X"41",X"C3",X"AE",X"41",X"D0",X"40",X"68",X"19",X"01",X"0B",
+		X"50",X"AF",X"00",X"00",X"10",X"01",X"FE",X"00",X"28",X"CD",X"40",X"40",X"C3",X"AE",X"41",X"D0",
+		X"50",X"82",X"19",X"01",X"0B",X"50",X"CD",X"EC",X"41",X"C3",X"AE",X"41",X"D0",X"60",X"75",X"19",
+		X"01",X"0B",X"50",X"AF",X"00",X"00",X"18",X"CD",X"FD",X"41",X"C3",X"AE",X"41",X"D0",X"50",X"68",
+		X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",X"01",X"FE",X"00",X"28",X"CD",X"6D",X"40",X"C3",
+		X"AE",X"41",X"D0",X"70",X"5B",X"19",X"01",X"0B",X"50",X"CD",X"1F",X"42",X"C3",X"AE",X"41",X"D0",
+		X"80",X"68",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",X"CD",X"30",X"42",X"C3",X"AE",X"41",
+		X"D0",X"70",X"75",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",X"01",X"FE",X"00",X"28",X"CD",
+		X"B0",X"40",X"C3",X"AE",X"41",X"D0",X"90",X"82",X"19",X"01",X"0B",X"50",X"CD",X"52",X"42",X"C3",
+		X"AE",X"41",X"D0",X"A0",X"68",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",X"CD",X"63",X"42",
+		X"C3",X"AE",X"41",X"D0",X"90",X"75",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",X"01",X"FE",
+		X"00",X"20",X"CD",X"EB",X"40",X"C3",X"AE",X"41",X"D0",X"B0",X"5B",X"19",X"01",X"0B",X"50",X"CD",
+		X"85",X"42",X"C3",X"AE",X"41",X"D0",X"C0",X"5B",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",
+		X"CD",X"96",X"42",X"C3",X"AE",X"41",X"D0",X"B0",X"5B",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",
+		X"18",X"C3",X"AE",X"41",X"D0",X"80",X"9B",X"18",X"02",X"0F",X"30",X"CD",X"E9",X"42",X"01",X"FF",
+		X"FF",X"10",X"01",X"FF",X"01",X"10",X"CD",X"1F",X"43",X"01",X"FF",X"00",X"10",X"CD",X"2B",X"43",
+		X"01",X"FF",X"00",X"10",X"AF",X"FF",X"FF",X"10",X"01",X"FF",X"FF",X"10",X"CD",X"35",X"43",X"01",
+		X"FF",X"FF",X"10",X"CD",X"3F",X"43",X"01",X"FF",X"FF",X"10",X"CD",X"49",X"43",X"01",X"FF",X"00",
+		X"10",X"CD",X"53",X"43",X"01",X"FF",X"00",X"30",X"76",X"D0",X"60",X"9B",X"18",X"02",X"0F",X"30",
+		X"AF",X"00",X"00",X"60",X"01",X"FF",X"FF",X"10",X"01",X"FF",X"01",X"10",X"CD",X"5D",X"43",X"01",
+		X"FF",X"00",X"10",X"CD",X"67",X"43",X"01",X"FF",X"00",X"20",X"AF",X"FF",X"01",X"10",X"01",X"FF",
+		X"01",X"10",X"CD",X"71",X"43",X"01",X"FF",X"00",X"10",X"CD",X"7B",X"43",X"C3",X"E4",X"42",X"A0",
+		X"80",X"01",X"1C",X"02",X"05",X"66",X"01",X"FD",X"00",X"30",X"76",X"90",X"8A",X"01",X"1C",X"02",
+		X"05",X"66",X"C3",X"26",X"43",X"60",X"60",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"50",
+		X"58",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"40",X"40",X"01",X"1C",X"02",X"05",X"66",
+		X"C3",X"26",X"43",X"30",X"4A",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"A0",X"60",X"01",
+		X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"90",X"6A",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",
+		X"43",X"50",X"80",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"38",X"70",X"01",X"1C",X"02",
+		X"05",X"66",X"C3",X"26",X"43",X"D0",X"A0",X"9B",X"18",X"02",X"0F",X"30",X"CD",X"C8",X"43",X"01",
+		X"FF",X"00",X"10",X"CD",X"FE",X"43",X"01",X"FF",X"00",X"10",X"CD",X"08",X"44",X"01",X"FF",X"00",
+		X"10",X"AF",X"FF",X"00",X"10",X"01",X"FF",X"01",X"10",X"CD",X"12",X"44",X"01",X"FF",X"01",X"10",
+		X"CD",X"1C",X"44",X"01",X"FF",X"01",X"08",X"AF",X"FF",X"01",X"10",X"01",X"FF",X"01",X"08",X"CD",
+		X"26",X"44",X"CD",X"30",X"44",X"C3",X"E4",X"42",X"D0",X"C0",X"9B",X"18",X"02",X"0F",X"30",X"AF",
+		X"00",X"00",X"50",X"01",X"FF",X"00",X"10",X"CD",X"3A",X"44",X"01",X"FF",X"00",X"10",X"CD",X"44",
+		X"44",X"01",X"FF",X"FF",X"10",X"AF",X"FF",X"00",X"10",X"01",X"FF",X"01",X"10",X"01",X"FF",X"FF",
+		X"10",X"CD",X"4E",X"44",X"01",X"FF",X"FF",X"10",X"CD",X"58",X"44",X"C3",X"E4",X"42",X"A0",X"A0",
+		X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"A0",X"AA",X"01",X"1C",X"02",X"05",X"66",X"C3",
+		X"26",X"43",X"60",X"C0",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"60",X"CA",X"01",X"1C",
+		X"02",X"05",X"66",X"C3",X"26",X"43",X"40",X"E0",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",
+		X"40",X"EA",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"A0",X"C0",X"01",X"1C",X"02",X"05",
+		X"66",X"C3",X"26",X"43",X"A0",X"CA",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"50",X"A0",
+		X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"50",X"AA",X"01",X"1C",X"02",X"05",X"66",X"C3",
+		X"26",X"43",X"D0",X"40",X"1B",X"18",X"02",X"0F",X"02",X"CD",X"AB",X"44",X"01",X"FE",X"00",X"12",
+		X"01",X"FE",X"01",X"04",X"EB",X"6A",X"1F",X"02",X"0B",X"10",X"01",X"FE",X"01",X"04",X"01",X"FE",
+		X"01",X"04",X"EB",X"7E",X"4E",X"02",X"07",X"20",X"01",X"FE",X"01",X"04",X"AF",X"00",X"04",X"01",
+		X"EB",X"8E",X"4E",X"02",X"07",X"30",X"01",X"FE",X"02",X"03",X"01",X"FE",X"01",X"03",X"01",X"FE",
+		X"00",X"08",X"01",X"FE",X"FF",X"08",X"01",X"FE",X"FE",X"30",X"76",X"D0",X"44",X"1B",X"18",X"02",
+		X"0F",X"02",X"AF",X"00",X"00",X"20",X"CD",X"BC",X"44",X"C3",X"6C",X"44",X"D0",X"38",X"1B",X"18",
+		X"02",X"0F",X"02",X"AF",X"00",X"00",X"20",X"C3",X"6C",X"44",X"D0",X"80",X"1B",X"18",X"02",X"0F",
+		X"02",X"CD",X"D7",X"44",X"C3",X"6C",X"44",X"D0",X"84",X"1B",X"18",X"02",X"0F",X"02",X"AF",X"00",
+		X"00",X"20",X"CD",X"E8",X"44",X"C3",X"6C",X"44",X"D0",X"78",X"1B",X"18",X"02",X"0F",X"02",X"AF",
+		X"00",X"00",X"20",X"C3",X"6C",X"44",X"D0",X"C0",X"1B",X"18",X"02",X"0F",X"02",X"CD",X"03",X"45",
+		X"C3",X"6C",X"44",X"D0",X"C4",X"1B",X"18",X"02",X"0F",X"02",X"AF",X"00",X"00",X"20",X"CD",X"14",
+		X"45",X"C3",X"6C",X"44",X"D0",X"B8",X"1B",X"18",X"02",X"0F",X"02",X"AF",X"00",X"00",X"20",X"C3",
+		X"6C",X"44",X"D0",X"30",X"9E",X"4E",X"02",X"05",X"20",X"CD",X"79",X"45",X"CD",X"87",X"45",X"CD",
+		X"95",X"45",X"01",X"FF",X"01",X"10",X"EB",X"AA",X"4E",X"02",X"07",X"20",X"01",X"FF",X"01",X"08",
+		X"EB",X"BA",X"4E",X"02",X"09",X"20",X"01",X"FE",X"01",X"08",X"EB",X"CE",X"4E",X"02",X"0B",X"20",
+		X"01",X"FE",X"01",X"04",X"EB",X"E6",X"4E",X"02",X"0D",X"20",X"01",X"FE",X"01",X"02",X"EB",X"DB",
+		X"17",X"02",X"0F",X"20",X"01",X"FE",X"00",X"08",X"AF",X"FE",X"FF",X"08",X"01",X"FD",X"FF",X"08",
+		X"01",X"FE",X"01",X"10",X"01",X"FD",X"01",X"16",X"76",X"D0",X"50",X"9E",X"4E",X"02",X"05",X"20",
+		X"01",X"00",X"00",X"08",X"C3",X"32",X"45",X"D0",X"70",X"9E",X"4E",X"02",X"05",X"20",X"01",X"00",
+		X"00",X"10",X"C3",X"32",X"45",X"D0",X"90",X"9E",X"4E",X"02",X"05",X"20",X"01",X"00",X"00",X"18",
+		X"C3",X"32",X"45",X"D0",X"30",X"9E",X"4E",X"02",X"05",X"20",X"CD",X"BA",X"45",X"CD",X"C8",X"45",
+		X"CD",X"D6",X"45",X"AF",X"00",X"00",X"20",X"C3",X"32",X"45",X"D0",X"50",X"9E",X"4E",X"02",X"05",
+		X"20",X"AF",X"00",X"00",X"28",X"C3",X"32",X"45",X"D0",X"70",X"9E",X"4E",X"02",X"05",X"20",X"AF",
+		X"00",X"00",X"30",X"C3",X"32",X"45",X"D0",X"90",X"9E",X"4E",X"02",X"05",X"20",X"AF",X"00",X"00",
+		X"38",X"C3",X"32",X"45",X"C0",X"BD",X"23",X"1B",X"02",X"28",X"40",X"01",X"FF",X"FF",X"41",X"CD",
+		X"F7",X"45",X"01",X"00",X"00",X"FF",X"76",X"77",X"8C",X"75",X"1B",X"01",X"0B",X"40",X"CD",X"06",
+		X"46",X"01",X"00",X"00",X"FF",X"76",X"23",X"90",X"82",X"1B",X"0B",X"01",X"40",X"CD",X"15",X"46",
+		X"01",X"00",X"00",X"FF",X"76",X"23",X"92",X"82",X"1B",X"0B",X"01",X"40",X"01",X"00",X"00",X"FF",
+		X"76",X"C0",X"F0",X"8F",X"19",X"05",X"28",X"70",X"01",X"FD",X"FD",X"40",X"76",X"80",X"B0",X"82",
+		X"1F",X"02",X"11",X"38",X"01",X"00",X"00",X"01",X"CD",X"82",X"47",X"CD",X"8E",X"47",X"CD",X"98",
+		X"47",X"CD",X"A4",X"47",X"CD",X"AE",X"47",X"AF",X"00",X"FE",X"04",X"CD",X"B8",X"47",X"01",X"00",
+		X"FE",X"04",X"CD",X"C2",X"47",X"01",X"00",X"FE",X"04",X"CD",X"CC",X"47",X"AF",X"00",X"FE",X"04",
+		X"CD",X"D6",X"47",X"01",X"00",X"FE",X"04",X"CD",X"E0",X"47",X"01",X"00",X"FE",X"04",X"CD",X"EA",
+		X"47",X"AF",X"00",X"FF",X"08",X"CD",X"F4",X"47",X"01",X"00",X"FE",X"04",X"CD",X"FE",X"47",X"01",
+		X"00",X"FE",X"04",X"CD",X"08",X"48",X"01",X"00",X"FF",X"08",X"CD",X"12",X"48",X"CD",X"1C",X"48",
+		X"AF",X"00",X"FE",X"04",X"CD",X"26",X"48",X"01",X"00",X"FE",X"04",X"CD",X"30",X"48",X"01",X"00",
+		X"FE",X"04",X"CD",X"3A",X"48",X"01",X"00",X"FE",X"04",X"CD",X"44",X"48",X"01",X"00",X"FE",X"04",
+		X"CD",X"4E",X"48",X"01",X"00",X"FE",X"04",X"CD",X"58",X"48",X"01",X"00",X"FE",X"04",X"CD",X"62",
+		X"48",X"01",X"00",X"02",X"04",X"CD",X"6C",X"48",X"AF",X"00",X"02",X"04",X"CD",X"76",X"48",X"01",
+		X"00",X"02",X"04",X"CD",X"80",X"48",X"AF",X"00",X"02",X"04",X"CD",X"30",X"48",X"01",X"00",X"02",
+		X"04",X"CD",X"8A",X"48",X"01",X"00",X"01",X"08",X"CD",X"94",X"48",X"AF",X"00",X"01",X"08",X"CD",
+		X"1C",X"48",X"01",X"00",X"02",X"04",X"CD",X"9E",X"48",X"01",X"00",X"02",X"04",X"CD",X"F4",X"47",
+		X"AF",X"00",X"02",X"04",X"CD",X"A8",X"48",X"01",X"00",X"02",X"04",X"CD",X"B2",X"48",X"01",X"00",
+		X"02",X"04",X"CD",X"D6",X"47",X"01",X"00",X"02",X"04",X"CD",X"BC",X"48",X"01",X"00",X"02",X"04",
+		X"CD",X"C6",X"48",X"AF",X"00",X"02",X"04",X"CD",X"D0",X"48",X"01",X"00",X"02",X"04",X"CD",X"8E",
+		X"47",X"01",X"00",X"02",X"04",X"CD",X"DA",X"48",X"01",X"00",X"02",X"04",X"CD",X"AE",X"47",X"AF",
+		X"00",X"02",X"04",X"CD",X"E4",X"48",X"01",X"00",X"02",X"04",X"CD",X"EE",X"48",X"01",X"00",X"02",
+		X"04",X"CD",X"F8",X"48",X"01",X"00",X"01",X"08",X"CD",X"02",X"49",X"01",X"00",X"02",X"08",X"CD",
+		X"0C",X"49",X"01",X"00",X"FE",X"08",X"CD",X"16",X"49",X"01",X"00",X"FE",X"04",X"CD",X"20",X"49",
+		X"01",X"00",X"FE",X"04",X"CD",X"2A",X"49",X"AF",X"00",X"FE",X"0C",X"01",X"00",X"FE",X"04",X"C3",
+		X"34",X"46",X"70",X"AC",X"66",X"1F",X"02",X"01",X"64",X"01",X"FC",X"00",X"18",X"76",X"70",X"B2",
+		X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"B6",X"01",X"1C",X"02",X"05",X"66",X"01",
+		X"FD",X"00",X"20",X"76",X"70",X"BE",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"C4",
+		X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"AA",X"01",X"1C",X"02",X"05",X"66",X"C3",
+		X"9F",X"47",X"70",X"A2",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"9A",X"01",X"1C",
+		X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"94",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",
+		X"70",X"8A",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"82",X"01",X"1C",X"02",X"05",
+		X"66",X"C3",X"9F",X"47",X"70",X"7C",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"72");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw06.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw06.vhd
new file mode 100644
index 00000000..dc5691b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw06.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity mw06 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of mw06 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"6A",X"01",X"1C",X"02",X"05",X"66",X"C3",
+		X"9F",X"47",X"70",X"60",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"6C",X"66",X"1F",
+		X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"5A",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",
+		X"70",X"54",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"4A",X"01",X"1C",X"02",X"05",
+		X"66",X"C3",X"9F",X"47",X"70",X"42",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"3A",
+		X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"32",X"01",X"1C",X"02",X"05",X"66",X"C3",
+		X"9F",X"47",X"70",X"2C",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"3B",X"01",X"1C",
+		X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"43",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",
+		X"70",X"4B",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"5B",X"01",X"1C",X"02",X"05",
+		X"66",X"C3",X"9F",X"47",X"70",X"63",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"73",
+		X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"83",X"01",X"1C",X"02",X"05",X"66",X"C3",
+		X"9F",X"47",X"70",X"8B",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"9B",X"01",X"1C",
+		X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"A3",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",
+		X"70",X"AB",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"BB",X"01",X"1C",X"02",X"05",
+		X"66",X"C3",X"9F",X"47",X"70",X"CB",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"D3",
+		X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"DB",X"01",X"1C",X"02",X"05",X"66",X"C3",
+		X"9F",X"47",X"70",X"E3",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"E8",X"66",X"1F",
+		X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"CA",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",
+		X"70",X"C2",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"BA",X"01",X"1C",X"02",X"05",
+		X"66",X"C3",X"9F",X"47",X"D0",X"60",X"1B",X"18",X"02",X"0F",X"02",X"CD",X"62",X"44",X"01",X"FE",
+		X"00",X"10",X"AF",X"00",X"04",X"01",X"EB",X"6A",X"1F",X"02",X"0B",X"10",X"01",X"FE",X"01",X"08",
+		X"AF",X"00",X"04",X"01",X"EB",X"7E",X"4E",X"02",X"07",X"20",X"01",X"FE",X"01",X"04",X"AF",X"00",
+		X"04",X"01",X"EB",X"8E",X"4E",X"02",X"07",X"30",X"01",X"FE",X"02",X"04",X"01",X"FE",X"01",X"03",
+		X"CD",X"83",X"49",X"01",X"FE",X"00",X"08",X"01",X"FE",X"FF",X"04",X"CD",X"8F",X"49",X"01",X"FE",
+		X"FE",X"20",X"76",X"7A",X"78",X"4A",X"1F",X"01",X"05",X"66",X"01",X"FD",X"00",X"20",X"76",X"62",
+		X"74",X"4A",X"1F",X"01",X"05",X"66",X"C3",X"8A",X"49",X"D0",X"A0",X"1B",X"18",X"02",X"0F",X"02",
+		X"CD",X"CA",X"44",X"CD",X"F6",X"44",X"01",X"FE",X"00",X"10",X"AF",X"00",X"04",X"01",X"EB",X"6A",
+		X"1F",X"02",X"0B",X"10",X"01",X"FE",X"01",X"08",X"AF",X"00",X"04",X"01",X"EB",X"7E",X"4E",X"02",
+		X"07",X"20",X"01",X"FE",X"01",X"04",X"AF",X"00",X"04",X"01",X"EB",X"8E",X"4E",X"02",X"07",X"30",
+		X"01",X"FE",X"02",X"03",X"CD",X"E9",X"49",X"01",X"FE",X"01",X"04",X"01",X"FE",X"00",X"04",X"CD",
+		X"F3",X"49",X"01",X"FE",X"00",X"04",X"C3",X"A2",X"44",X"82",X"73",X"4A",X"1F",X"01",X"05",X"66",
+		X"C3",X"8A",X"49",X"72",X"67",X"4A",X"1F",X"01",X"05",X"66",X"C3",X"8A",X"49",X"D0",X"78",X"DB",
+		X"18",X"02",X"0F",X"33",X"CD",X"61",X"4A",X"01",X"FF",X"00",X"10",X"CD",X"3F",X"4A",X"01",X"FF",
+		X"00",X"10",X"01",X"FF",X"01",X"11",X"01",X"FE",X"FF",X"08",X"01",X"FD",X"FF",X"05",X"AF",X"F0",
+		X"FF",X"02",X"01",X"00",X"00",X"04",X"CD",X"4B",X"4A",X"CD",X"57",X"4A",X"01",X"00",X"00",X"12",
+		X"CD",X"4B",X"4A",X"CD",X"57",X"4A",X"01",X"FE",X"00",X"10",X"01",X"FD",X"FF",X"10",X"76",X"B8",
+		X"7F",X"4A",X"1F",X"01",X"05",X"66",X"01",X"FD",X"00",X"40",X"76",X"50",X"7A",X"66",X"1F",X"02",
+		X"01",X"64",X"01",X"FC",X"00",X"10",X"76",X"50",X"84",X"66",X"1F",X"02",X"01",X"64",X"C3",X"52",
+		X"4A",X"D0",X"48",X"1B",X"19",X"02",X"0F",X"33",X"AF",X"00",X"00",X"10",X"CD",X"DF",X"4A",X"01",
+		X"FF",X"00",X"10",X"CD",X"AB",X"4A",X"01",X"FF",X"00",X"11",X"01",X"FE",X"00",X"08",X"01",X"FD",
+		X"00",X"05",X"AF",X"F0",X"00",X"02",X"01",X"00",X"00",X"06",X"CD",X"B5",X"4A",X"CD",X"C1",X"4A",
+		X"01",X"00",X"00",X"06",X"CD",X"B5",X"4A",X"CD",X"C1",X"4A",X"01",X"FE",X"00",X"08",X"CD",X"CB",
+		X"4A",X"CD",X"D5",X"4A",X"01",X"00",X"00",X"10",X"C3",X"9E",X"4A",X"B8",X"4F",X"4A",X"1F",X"01",
+		X"05",X"66",X"C3",X"46",X"4A",X"60",X"48",X"40",X"1F",X"01",X"03",X"64",X"01",X"FE",X"00",X"30",
+		X"76",X"60",X"54",X"40",X"1F",X"01",X"03",X"64",X"C3",X"BC",X"4A",X"50",X"48",X"40",X"1F",X"01",
+		X"03",X"64",X"C3",X"BC",X"4A",X"50",X"54",X"40",X"1F",X"01",X"03",X"64",X"C3",X"BC",X"4A",X"D0",
+		X"78",X"DB",X"18",X"02",X"0F",X"33",X"AF",X"00",X"00",X"10",X"01",X"FF",X"00",X"11",X"01",X"FE",
+		X"00",X"08",X"01",X"FD",X"00",X"05",X"AF",X"F0",X"00",X"02",X"01",X"00",X"00",X"10",X"01",X"FE",
+		X"00",X"09",X"01",X"FD",X"00",X"06",X"CD",X"13",X"4B",X"CD",X"1D",X"4B",X"01",X"00",X"00",X"10",
+		X"C3",X"06",X"4B",X"40",X"79",X"66",X"1F",X"02",X"01",X"64",X"C3",X"52",X"4A",X"40",X"83",X"66",
+		X"1F",X"02",X"01",X"64",X"C3",X"52",X"4A",X"D0",X"A8",X"FB",X"18",X"02",X"0F",X"33",X"CD",X"87",
+		X"4B",X"01",X"FF",X"00",X"18",X"CD",X"69",X"4B",X"01",X"FF",X"00",X"08",X"01",X"FF",X"01",X"11",
+		X"01",X"FE",X"FF",X"08",X"01",X"FD",X"FF",X"05",X"AF",X"F0",X"FF",X"02",X"01",X"00",X"00",X"02",
+		X"CD",X"73",X"4B",X"CD",X"7D",X"4B",X"01",X"00",X"00",X"0E",X"CD",X"73",X"4B",X"CD",X"7D",X"4B",
+		X"01",X"FE",X"00",X"10",X"01",X"FD",X"01",X"10",X"76",X"B0",X"AF",X"4A",X"1F",X"01",X"05",X"66",
+		X"C3",X"46",X"4A",X"50",X"AA",X"66",X"1F",X"02",X"01",X"64",X"C3",X"52",X"4A",X"50",X"B4",X"66",
+		X"1F",X"02",X"01",X"64",X"C3",X"52",X"4A",X"D0",X"D8",X"DB",X"18",X"02",X"0F",X"33",X"AF",X"00",
+		X"00",X"10",X"CD",X"03",X"4C",X"01",X"FF",X"00",X"18",X"CD",X"D1",X"4B",X"01",X"FF",X"00",X"09",
+		X"01",X"FE",X"00",X"08",X"01",X"FD",X"00",X"05",X"AF",X"F0",X"00",X"02",X"01",X"00",X"00",X"04",
+		X"CD",X"DB",X"4B",X"CD",X"E5",X"4B",X"01",X"00",X"00",X"08",X"CD",X"DB",X"4B",X"CD",X"E5",X"4B",
+		X"01",X"FE",X"00",X"08",X"CD",X"EF",X"4B",X"CD",X"F9",X"4B",X"01",X"00",X"00",X"10",X"C3",X"C4",
+		X"4B",X"B0",X"DF",X"4A",X"1F",X"01",X"05",X"66",X"C3",X"46",X"4A",X"60",X"D8",X"40",X"1F",X"01",
+		X"03",X"64",X"C3",X"BC",X"4A",X"60",X"E4",X"40",X"1F",X"01",X"03",X"64",X"C3",X"BC",X"4A",X"50",
+		X"D8",X"40",X"1F",X"01",X"03",X"64",X"C3",X"BC",X"4A",X"50",X"E4",X"40",X"1F",X"01",X"03",X"64",
+		X"C3",X"BC",X"4A",X"D0",X"A8",X"FB",X"18",X"02",X"0F",X"33",X"AF",X"00",X"00",X"10",X"01",X"FF",
+		X"00",X"11",X"01",X"FE",X"00",X"08",X"01",X"FD",X"00",X"05",X"AF",X"F0",X"00",X"02",X"01",X"00",
+		X"00",X"10",X"01",X"FE",X"00",X"09",X"01",X"FD",X"00",X"06",X"01",X"00",X"00",X"04",X"CD",X"3B",
+		X"4C",X"CD",X"45",X"4C",X"01",X"00",X"00",X"10",X"C3",X"2A",X"4C",X"40",X"A9",X"66",X"1F",X"02",
+		X"01",X"64",X"C3",X"52",X"4A",X"40",X"B3",X"66",X"1F",X"03",X"01",X"64",X"C3",X"52",X"4A",X"C0",
+		X"8C",X"C5",X"1B",X"02",X"0E",X"3F",X"00",X"00",X"00",X"CD",X"6C",X"4C",X"CD",X"88",X"4C",X"CD",
+		X"9A",X"4C",X"CD",X"B0",X"4C",X"01",X"00",X"00",X"20",X"C3",X"56",X"4C",X"AA",X"8A",X"AD",X"1B",
+		X"01",X"0A",X"08",X"01",X"FE",X"00",X"08",X"01",X"FE",X"00",X"18",X"01",X"FE",X"01",X"10",X"01",
+		X"FD",X"FE",X"10",X"01",X"FC",X"02",X"10",X"76",X"AA",X"92",X"AD",X"1B",X"01",X"0A",X"08",X"01",
+		X"FE",X"00",X"08",X"01",X"FE",X"00",X"18",X"C3",X"7B",X"4C",X"B4",X"8A",X"AD",X"1B",X"01",X"0A",
+		X"08",X"01",X"FE",X"00",X"08",X"01",X"FE",X"FE",X"0C",X"01",X"FE",X"01",X"04",X"C3",X"7B",X"4C",
+		X"B4",X"92",X"AD",X"1B",X"01",X"0A",X"08",X"01",X"FE",X"00",X"08",X"CD",X"D2",X"4C",X"CD",X"E4",
+		X"4C",X"CD",X"F6",X"4C",X"CD",X"04",X"4D",X"01",X"FE",X"02",X"14",X"01",X"FE",X"00",X"04",X"C3",
+		X"7B",X"4C",X"AE",X"8A",X"AD",X"1B",X"01",X"0A",X"08",X"01",X"FE",X"FE",X"11",X"01",X"FE",X"01",
+		X"0E",X"C3",X"7B",X"4C",X"AE",X"92",X"AD",X"1B",X"01",X"0A",X"08",X"01",X"FE",X"02",X"18",X"01",
+		X"FE",X"01",X"08",X"C3",X"7B",X"4C",X"B8",X"8A",X"AD",X"1B",X"01",X"0A",X"08",X"01",X"FE",X"FE",
+		X"24",X"C3",X"7B",X"4C",X"B8",X"92",X"AD",X"1B",X"01",X"0A",X"08",X"01",X"FE",X"02",X"24",X"C3",
+		X"7B",X"4C",X"3E",X"01",X"F7",X"0A",X"C3",X"E3",X"0F",X"E1",X"C3",X"E3",X"0F",X"76",X"1E",X"4D",
+		X"00",X"00",X"1E",X"0C",X"3F",X"0C",X"1E",X"00",X"00",X"29",X"4D",X"00",X"00",X"00",X"00",X"F0",
+		X"00",X"60",X"00",X"F8",X"01",X"7E",X"00",X"FC",X"00",X"3F",X"00",X"FC",X"00",X"7E",X"00",X"F8",
+		X"01",X"60",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"D0",X"48",X"29",X"4D",X"02",X"0F",X"12",
+		X"CD",X"9C",X"4D",X"CD",X"D3",X"4D",X"CD",X"0A",X"4E",X"01",X"FE",X"FE",X"10",X"01",X"FE",X"02",
+		X"10",X"CD",X"76",X"4D",X"CD",X"80",X"4D",X"CD",X"8E",X"4D",X"76",X"01",X"FE",X"FE",X"10",X"01",
+		X"FE",X"02",X"10",X"C3",X"6B",X"4D",X"90",X"4B",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"6B",X"4D",
+		X"93",X"48",X"1E",X"4D",X"01",X"09",X"22",X"01",X"FF",X"FE",X"10",X"C3",X"6B",X"4D",X"93",X"4E",
+		X"1E",X"4D",X"01",X"09",X"22",X"01",X"FF",X"02",X"08",X"C3",X"6B",X"4D",X"D0",X"78",X"29",X"4D",
+		X"02",X"0F",X"12",X"01",X"FE",X"FE",X"10",X"01",X"FE",X"02",X"10",X"CD",X"B5",X"4D",X"CD",X"BF",
+		X"4D",X"CD",X"C9",X"4D",X"76",X"90",X"7B",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"6B",X"4D",X"93",
+		X"78",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"87",X"4D",X"93",X"7E",X"1E",X"4D",X"01",X"09",X"22",
+		X"C3",X"95",X"4D",X"D0",X"B8",X"29",X"4D",X"02",X"0F",X"12",X"01",X"FE",X"FE",X"10",X"01",X"FE",
+		X"02",X"10",X"CD",X"EC",X"4D",X"CD",X"F6",X"4D",X"CD",X"00",X"4E",X"76",X"90",X"BB",X"1E",X"4D",
+		X"01",X"09",X"22",X"C3",X"6B",X"4D",X"93",X"B8",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"87",X"4D",
+		X"93",X"BE",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"95",X"4D",X"D0",X"E8",X"29",X"4D",X"02",X"0F",
+		X"12",X"01",X"FE",X"FE",X"10",X"01",X"FF",X"02",X"10",X"CD",X"23",X"4E",X"CD",X"2D",X"4E",X"CD",
+		X"37",X"4E",X"76",X"90",X"EB",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"6B",X"4D",X"93",X"E8",X"1E",
+		X"4D",X"01",X"09",X"22",X"C3",X"87",X"4D",X"93",X"EE",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"95",
+		X"4D",X"D0",X"88",X"DB",X"18",X"02",X"0F",X"33",X"CD",X"49",X"4D",X"AF",X"00",X"00",X"20",X"CD",
+		X"49",X"4D",X"01",X"00",X"00",X"04",X"AF",X"00",X"04",X"02",X"01",X"00",X"00",X"04",X"AF",X"00",
+		X"FC",X"02",X"01",X"00",X"00",X"04",X"C3",X"4F",X"4E",X"D0",X"10",X"AD",X"1B",X"01",X"0A",X"08",
+		X"CD",X"49",X"4D",X"AF",X"00",X"00",X"10",X"CD",X"FD",X"49",X"CD",X"27",X"4B",X"76",X"7E",X"4E",
+		X"00",X"00",X"E0",X"1F",X"78",X"7C",X"FF",X"7F",X"FC",X"3F",X"F0",X"1F",X"00",X"00",X"8E",X"4E",
+		X"00",X"00",X"00",X"00",X"C0",X"0F",X"FE",X"7F",X"E0",X"0F",X"00",X"00",X"00",X"00",X"9E",X"4E",
+		X"00",X"00",X"40",X"00",X"E0",X"00",X"40",X"00",X"00",X"00",X"AA",X"4E",X"00",X"00",X"E0",X"00",
+		X"F0",X"01",X"B0",X"01",X"F0",X"01",X"E0",X"00",X"00",X"00",X"BA",X"4E",X"00",X"00",X"E0",X"00",
+		X"50",X"01",X"E8",X"02",X"B8",X"03",X"E8",X"02",X"50",X"01",X"E0",X"00",X"00",X"00",X"CE",X"4E",
+		X"00",X"00",X"B0",X"01",X"F8",X"03",X"EC",X"06",X"B4",X"05",X"58",X"03",X"B4",X"05",X"EC",X"06",
+		X"F8",X"03",X"B0",X"01",X"00",X"00",X"E6",X"4E",X"00",X"00",X"B0",X"01",X"F8",X"03",X"5C",X"07",
+		X"AE",X"0E",X"56",X"0D",X"F8",X"03",X"56",X"0D",X"AE",X"0E",X"5C",X"07",X"F8",X"03",X"B0",X"01",
+		X"00",X"00",X"C0",X"04",X"00",X"00",X"00",X"10",X"C6",X"00",X"00",X"00",X"6C",X"29",X"10",X"01",
+		X"00",X"16",X"04",X"06",X"11",X"00",X"6E",X"C9",X"00",X"00",X"00",X"34",X"C2",X"05",X"90",X"00",
+		X"DF",X"08",X"02",X"00",X"00",X"CC",X"25",X"08",X"02",X"10",X"BA",X"43",X"92",X"80",X"00",X"A1",
+		X"4C",X"08",X"21",X"02",X"2F",X"2B",X"31",X"04",X"10",X"D0",X"6A",X"04",X"81",X"20",X"0A",X"95",
+		X"02",X"10",X"02",X"A0",X"A8",X"45",X"01",X"04",X"10",X"51",X"00",X"92",X"00",X"01",X"44",X"06",
+		X"20",X"01",X"36",X"92",X"44",X"42",X"00",X"C2",X"A0",X"91",X"04",X"00",X"00",X"10",X"03",X"01",
+		X"02",X"28",X"08",X"0C",X"20",X"00",X"80",X"92",X"02",X"41",X"08",X"04",X"00",X"25",X"90",X"00",
+		X"50",X"05",X"4A",X"24",X"00",X"00",X"20",X"D4",X"48",X"00",X"8A",X"42",X"80",X"81",X"42",X"02",
+		X"10",X"00",X"21",X"04",X"40",X"01",X"20",X"02",X"08",X"04",X"48",X"44",X"00",X"00",X"20",X"10",
+		X"88",X"00",X"00",X"00",X"04",X"10",X"10",X"01",X"10",X"01",X"21",X"00",X"20",X"28",X"08",X"00",
+		X"40",X"44",X"80",X"00",X"04",X"02",X"00",X"00",X"14",X"00",X"04",X"00",X"20",X"20",X"01",X"09",
+		X"00",X"00",X"02",X"02",X"00",X"08",X"00",X"01",X"20",X"00",X"00",X"40",X"80",X"00",X"00",X"20",
+		X"00",X"10",X"80",X"00",X"40",X"00",X"20",X"00",X"00",X"80",X"FF",X"FF",X"07",X"07",X"07",X"07",
+		X"07",X"07",X"07",X"07",X"07",X"02",X"03",X"04",X"05",X"06",X"12",X"2D",X"0A",X"00",X"0E",X"17",
+		X"0E",X"1B",X"10",X"22",X"2E",X"18",X"1E",X"1D",X"00",X"3E",X"09",X"CD",X"05",X"0A",X"E1",X"D1",
+		X"C3",X"12",X"4D",X"3E",X"E1",X"C3",X"EB",X"4F",X"F7",X"0A",X"F7",X"0C",X"AF",X"E7",X"0B",X"C9");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/README.txt
new file mode 100644
index 00000000..6c0eccf4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/README.txt	
@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: Shuffleboard port to MiST by Gehstock 
+-- 05 June 2019
+-- 
+---------------------------------------------------------------------------------
+-- 
+-- Midway 8080 Hardware
+-- Audio based on work by Paul Walsh.
+-- Audio and scan converter by MikeJ.
+---------------------------------------------------------------------------------
+-- 
+-- 
+-- Keyboard inputs :
+--
+--   F1          : Start
+--   SPACE       : Fire
+--   RIGHT/LEFT  : Movement
+--
+-- Joystick support.
+-- 
+-- 
+---------------------------------------------------------------------------------
+ToDo: Color Prom
+      Controls + DIP
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.qpf
new file mode 100644
index 00000000..d253de0b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:27:39  November 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:27:39  November 20, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "Shuffleboard"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.qsf
new file mode 100644
index 00000000..03efe657
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.qsf	
@@ -0,0 +1,173 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 13:57:20  June 05, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		LunarRescue_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Shuffleboard_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Shuffleboard_memory.sv
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_video.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY Shuffleboard_mist
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ------------------------------
+# start ENTITY(LunarRescue_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(LunarRescue_mist)
+# ----------------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.sdc
new file mode 100644
index 00000000..f91c127c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Snapshot/Shuffleboard.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Snapshot/Shuffleboard.rbf
new file mode 100644
index 0000000000000000000000000000000000000000..4b320709609677405d899cb7c5e54e8c78d73e09
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/clean.bat
new file mode 100644
index 00000000..83fb0c47
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/Shuffleboard_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/Shuffleboard_memory.sv
new file mode 100644
index 00000000..135c4b18
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/Shuffleboard_memory.sv	
@@ -0,0 +1,80 @@
+module Shuffleboard_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+
+
+sprom #(
+	.init_file("./roms/shuffle.h.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_0)
+	);
+
+sprom #(
+	.init_file("./roms/shuffle.g.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_1)
+	);
+	
+sprom #(
+	.init_file("./roms/shuffle.f.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_2)
+	);
+	
+sprom #(
+	.init_file("./roms/shuffle.e.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_e (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_3)
+	);
+
+
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3) begin
+	Rom_out = 8'b00000000;
+		case (Addr[15:11])
+			5'b00000 : Rom_out = rom_data_0;
+			5'b00001 : Rom_out = rom_data_1;
+			5'b00010 : Rom_out = rom_data_2;
+			5'b00011 : Rom_out = rom_data_3;
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/Shuffleboard_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/Shuffleboard_mist.sv
new file mode 100644
index 00000000..b88aaae3
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/Shuffleboard_mist.sv	
@@ -0,0 +1,196 @@
+module Shuffleboard_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"Shuffleb.;;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_sys),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+	.DIP(dip),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(hs),
+	.VSync(vs)
+	);
+		
+Shuffleboard_memory Shuffleboard_memory (
+	.Clock(clk_sys),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_sys),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);		
+	  
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({Video,Video,Video}),
+	.G({Video,Video,Video}),
+	.B({Video,Video,Video}),
+	.HSync(~hs),
+	.VSync(~vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.rotate({1'b0,status[2]}),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ce_divider(1),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_fire2 = 0;
+reg btn_fire3 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h14: btn_fire3       <= key_pressed; // ctrl
+			'h11: btn_fire2       <= key_pressed; // alt
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T8080se.vhd
new file mode 100644
index 00000000..65b92d54
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T8080se.vhd	
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..e09def1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..1c0f2638
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/dac.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/dac.vhd
new file mode 100644
index 00000000..db58d70b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/dac.vhd	
@@ -0,0 +1,48 @@
+-------------------------------------------------------------------------------
+--
+-- Delta-Sigma DAC
+--
+-- Refer to Xilinx Application Note XAPP154.
+--
+-- This DAC requires an external RC low-pass filter:
+--
+--   dac_o 0---XXXXX---+---0 analog audio
+--              3k3    |
+--                    === 4n7
+--                     |
+--                    GND
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.numeric_std.all;
+
+entity dac is
+	generic (
+		C_bits  : integer := 8
+	);
+	port (
+		clk_i   : in  std_logic;
+		res_n_i : in  std_logic;
+		dac_i   : in  std_logic_vector(C_bits-1 downto 0);
+		dac_o   : out std_logic
+	);
+end dac;
+
+architecture rtl of dac is
+	signal sig_in: unsigned(C_bits downto 0);
+begin
+	seq: process(clk_i, res_n_i)
+	begin
+		if res_n_i = '0' then
+			sig_in <= to_unsigned(2**C_bits, sig_in'length);
+			dac_o  <= '0';
+		elsif rising_edge(clk_i) then
+		        -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
+			--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
+			sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
+			dac_o  <= sig_in(C_bits);
+		end if;
+	end process seq;
+end rtl;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..f089f1f2
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/invaders.vhd	
@@ -0,0 +1,243 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: entity work.mw8080
+		port map(
+			Rst_n => Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+
+	GDB0(0) <= DIP(8);  -- Unused ?
+	GDB0(1) <= DIP(7);
+	GDB0(2) <= DIP(6);  -- Unused ?
+	GDB0(3) <= '1';             -- Unused ?
+	GDB0(4) <= not Fire;
+	GDB0(5) <= not MoveLeft;
+	GDB0(6) <= not MoveRight;
+	GDB0(7) <= DIP(5);  -- Unused ?
+
+	GDB1(0) <= not Coin;-- Active High !
+	GDB1(1) <= not Sel2Player;
+	GDB1(2) <= not Sel1Player;
+	GDB1(3) <= '1';-- Unused ?
+	GDB1(4) <= not Fire;
+	GDB1(5) <= not MoveLeft;
+	GDB1(6) <= not MoveRight;
+	GDB1(7) <= '1';-- Unused ?
+
+	GDB2(0) <= DIP(4);  -- LSB Lives 3-6
+	GDB2(1) <= DIP(3);  -- MSB Lives 3-6
+	GDB2(2) <= '0';-- Tilt ?
+	GDB2(3) <= '0';--DIP(2);  -- Bonus life at 1000 or 1500
+	GDB2(4) <= not Fire;
+	GDB2(5) <= not MoveLeft;
+	GDB2(6) <= not MoveRight;
+	GDB2(7) <= '1';--DIP(1);  -- Coin info
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..f16cf379
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..1d9ad578
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,335 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..d65b9f9b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/pll.vhd	
@@ -0,0 +1,350 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire4_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire4_bv(0 DOWNTO 0) <= "0";
+	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	sub_wire2    <= inclk0;
+	sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire3,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.e.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.e.bin
new file mode 100644
index 0000000000000000000000000000000000000000..f94474737f88a568a5f18f479af7e2ae5a816d00
GIT binary patch
literal 2048
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.e.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.e.hex
new file mode 100644
index 00000000..bf312566
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.e.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.f.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.f.bin
new file mode 100644
index 0000000000000000000000000000000000000000..ba6856a466aa5b2a587fe6f8b0a555be4f43842a
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.f.hex
new file mode 100644
index 00000000..4fcca38e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.f.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.g.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.g.bin
new file mode 100644
index 0000000000000000000000000000000000000000..d20308fb883140e69b29adb95803b6274ea6fc87
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.g.hex
new file mode 100644
index 00000000..154a3344
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.g.hex	
@@ -0,0 +1,129 @@
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new file mode 100644
index 0000000000000000000000000000000000000000..cf6b9c11d08235f504b14278ec54b439a4d7d10e
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.h.hex
new file mode 100644
index 00000000..620300a5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.h.hex	
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qpf
new file mode 100644
index 00000000..215a8d81
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:27:39  November 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:27:39  November 20, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "Invaders2"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qsf
new file mode 100644
index 00000000..f7c9eea1
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qsf	
@@ -0,0 +1,173 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 13:13:10  June 05, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Invaders_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Invaders2_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/invaders_memory.sv
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_video.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY Invaders2_mist
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ---------------------------
+# start ENTITY(Invaders_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(Invaders_mist)
+# -------------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.sdc
new file mode 100644
index 00000000..f91c127c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/README SpaceInvaders2.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Midway-Taito 8080 Hardware/README SpaceInvaders2.txt
rename to Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/README.txt
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/clean.bat
new file mode 100644
index 00000000..83fb0c47
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/Invaders2_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/Invaders2_mist.sv
new file mode 100644
index 00000000..8cf901c0
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/Invaders2_mist.sv	
@@ -0,0 +1,211 @@
+module Invaders2_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"Space Inv.2;;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Overlay, On, Off;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_sys),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+	.DIP(dip),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(HSync),
+	.VSync(VSync)
+	);
+		
+invaders_memory invaders_memory (
+	.Clock(clk_sys),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_sys),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);		
+	  
+invaders_video invaders_video (
+	.Video(Video),
+	.Overlay(~status[5]),
+	.CLK(clk_sys),
+	.Rst_n_s(Rst_n_s),
+	.HSync(HSync),
+	.VSync(VSync),
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({r,r,r}),
+	.G({g,g,g}),
+	.B({b,b,b}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.rotate({1'b0,status[2]}),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ce_divider(1),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_fire2 = 0;
+reg btn_fire3 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h14: btn_fire3       <= key_pressed; // ctrl
+			'h11: btn_fire2       <= key_pressed; // alt
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T8080se.vhd
new file mode 100644
index 00000000..65b92d54
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T8080se.vhd	
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..e09def1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..1c0f2638
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/dac.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/dac.vhd
new file mode 100644
index 00000000..db58d70b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/dac.vhd	
@@ -0,0 +1,48 @@
+-------------------------------------------------------------------------------
+--
+-- Delta-Sigma DAC
+--
+-- Refer to Xilinx Application Note XAPP154.
+--
+-- This DAC requires an external RC low-pass filter:
+--
+--   dac_o 0---XXXXX---+---0 analog audio
+--              3k3    |
+--                    === 4n7
+--                     |
+--                    GND
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.numeric_std.all;
+
+entity dac is
+	generic (
+		C_bits  : integer := 8
+	);
+	port (
+		clk_i   : in  std_logic;
+		res_n_i : in  std_logic;
+		dac_i   : in  std_logic_vector(C_bits-1 downto 0);
+		dac_o   : out std_logic
+	);
+end dac;
+
+architecture rtl of dac is
+	signal sig_in: unsigned(C_bits downto 0);
+begin
+	seq: process(clk_i, res_n_i)
+	begin
+		if res_n_i = '0' then
+			sig_in <= to_unsigned(2**C_bits, sig_in'length);
+			dac_o  <= '0';
+		elsif rising_edge(clk_i) then
+		        -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
+			--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
+			sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
+			dac_o  <= sig_in(C_bits);
+		end if;
+	end process seq;
+end rtl;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..a509baa4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders.vhd	
@@ -0,0 +1,271 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+	component mw8080
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+	end component;
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: mw8080
+		port map(
+			Rst_n => Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+
+	GDB0(0) <= '1';--DIP(8);  -- Unused ?
+	GDB0(1) <= '1';--DIP(7);
+	GDB0(2) <= '1';--DIP(6);  -- Unused ?
+	GDB0(3) <= '1';             -- Unused ?
+	GDB0(4) <= not Fire;
+	GDB0(5) <= not MoveLeft;
+	GDB0(6) <= not MoveRight;
+	GDB0(7) <= '1';--DIP(5);  -- Unused ?
+
+	GDB1(0) <= not Coin;-- Active High !
+	GDB1(1) <= not Sel2Player;
+	GDB1(2) <= not Sel1Player;
+	GDB1(3) <= '1';-- Unused ?
+	GDB1(4) <= not Fire;
+	GDB1(5) <= not MoveLeft;
+	GDB1(6) <= not MoveRight;
+	GDB1(7) <= '1';-- Unused ?
+
+	GDB2(0) <= '1';--DIP(4);  -- LSB Lives 3-6
+	GDB2(1) <= '1';--DIP(3);  -- MSB Lives 3-6
+	GDB2(2) <= '0';-- Tilt ?
+	GDB2(3) <= '0';--DIP(2);  -- Bonus life at 1000 or 1500
+	GDB2(4) <= not Fire;
+	GDB2(5) <= not MoveLeft;
+	GDB2(6) <= not MoveRight;
+	GDB2(7) <= '1';--DIP(1);  -- Coin info
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..f16cf379
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_memory.sv
new file mode 100644
index 00000000..9ad7fe2a
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_memory.sv	
@@ -0,0 +1,104 @@
+
+module invaders_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+wire [7:0]rom_data_4;
+wire [7:0]rom_data_5;
+
+sprom #(
+	.init_file("./roms/invad2ct.h.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_0)
+	);
+
+sprom #(
+	.init_file("./roms/invad2ct.g.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_1)
+	);
+	
+sprom #(
+	.init_file("./roms/invad2ct.f.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_2)
+	);
+	
+sprom #(
+	.init_file("./roms/invad2ct.e.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_e (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_3)
+	);
+
+sprom #(
+	.init_file("./roms/invad2ct.b.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_b (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_4)
+	);
+
+sprom #(
+	.init_file("./roms/invad2ct.a.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_a (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_5)
+	);	
+	
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5) begin
+	Rom_out = 8'b00000000;
+		case (Addr[15:11])
+			5'b00000 : Rom_out = rom_data_0;
+			5'b00001 : Rom_out = rom_data_1;
+			5'b00010 : Rom_out = rom_data_2;
+			5'b00011 : Rom_out = rom_data_3;
+			
+			5'b01010 : Rom_out = rom_data_4;
+			5'b01011 : Rom_out = rom_data_5;
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_video.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_video.vhd
new file mode 100644
index 00000000..77ac2478
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_video.vhd	
@@ -0,0 +1,127 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+entity invaders_video is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end invaders_video;
+
+architecture rtl of invaders_video is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_G1      : boolean;
+	signal Overlay_G2      : boolean;
+	signal Overlay_R1      : boolean;
+	signal Overlay_G1_VCnt : boolean;
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  Overlay_G1_VCnt <= false;
+	  Overlay_G1 <= false;
+	  Overlay_G2 <= false;
+	  Overlay_R1 <= false;
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt = x"1F") then
+		  Overlay_G1_VCnt <= true;
+		elsif (Vcnt = x"95") then
+		  Overlay_G1_VCnt <= false;
+		end if;
+	  end if;
+
+	  if (HCnt = x"027") and Overlay_G1_VCnt then
+		Overlay_G1 <= true;
+	  elsif (HCnt = x"046") then
+		Overlay_G1 <= false;
+	  end if;
+
+	  if (HCnt = x"046") then
+		Overlay_G2 <= true;
+	  elsif (HCnt = x"0B6") then
+		Overlay_G2 <= false;
+	  end if;
+
+	  if (HCnt = x"1A6") then
+		Overlay_R1 <= true;
+	  elsif (HCnt = x"1E6") then
+		Overlay_R1 <= false;
+	  end if;
+
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1)
+  begin
+	if (Video = '0') then
+	  VideoRGB  <= "000";
+	else
+	  if Overlay_G1 or Overlay_G2 then
+		VideoRGB  <= "010";
+	  elsif Overlay_R1 then
+		VideoRGB  <= "100";
+	  else
+		VideoRGB  <= "111";
+	  end if;
+	end if;
+  end process;
+
+
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_HSYNC   <= not HSync;
+  O_VSYNC   <= not VSync;
+
+
+end;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..b9a88f96
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,336 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..d65b9f9b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.vhd	
@@ -0,0 +1,350 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire4_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire4_bv(0 DOWNTO 0) <= "0";
+	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	sub_wire2    <= inclk0;
+	sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire3,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.a.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.a.hex
new file mode 100644
index 00000000..38fd57d7
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.a.hex	
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.b.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.b.hex
new file mode 100644
index 00000000..ec483fdc
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.b.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.e.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.e.hex
new file mode 100644
index 00000000..84ee5864
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.e.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.f.hex
new file mode 100644
index 00000000..cf20ae03
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.f.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.g.hex
new file mode 100644
index 00000000..63b4648e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.g.hex	
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.h.hex
new file mode 100644
index 00000000..1ffa200a
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.h.hex	
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/README SpaceInvaders.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Midway-Taito 8080 Hardware/README SpaceInvaders.txt
rename to Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/README.txt
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qpf
new file mode 100644
index 00000000..4195da4c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:27:39  November 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:27:39  November 20, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "SpaceInvaders"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qsf
new file mode 100644
index 00000000..6c2d87d6
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qsf	
@@ -0,0 +1,173 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 19:10:47  June 08, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		SpaceInvaders_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/spaceinvaders_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/spaceinvaders_memory.sv
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/spaceinvaders_overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY spaceinvaders_mist
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# --------------------------------
+# start ENTITY(spaceinvaders_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(spaceinvaders_mist)
+# ------------------------------
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.sdc
new file mode 100644
index 00000000..f91c127c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/clean.bat
new file mode 100644
index 00000000..83fb0c47
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T8080se.vhd
new file mode 100644
index 00000000..65b92d54
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T8080se.vhd	
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..e09def1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..1c0f2638
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/dac.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/dac.vhd
new file mode 100644
index 00000000..db58d70b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/dac.vhd	
@@ -0,0 +1,48 @@
+-------------------------------------------------------------------------------
+--
+-- Delta-Sigma DAC
+--
+-- Refer to Xilinx Application Note XAPP154.
+--
+-- This DAC requires an external RC low-pass filter:
+--
+--   dac_o 0---XXXXX---+---0 analog audio
+--              3k3    |
+--                    === 4n7
+--                     |
+--                    GND
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.numeric_std.all;
+
+entity dac is
+	generic (
+		C_bits  : integer := 8
+	);
+	port (
+		clk_i   : in  std_logic;
+		res_n_i : in  std_logic;
+		dac_i   : in  std_logic_vector(C_bits-1 downto 0);
+		dac_o   : out std_logic
+	);
+end dac;
+
+architecture rtl of dac is
+	signal sig_in: unsigned(C_bits downto 0);
+begin
+	seq: process(clk_i, res_n_i)
+	begin
+		if res_n_i = '0' then
+			sig_in <= to_unsigned(2**C_bits, sig_in'length);
+			dac_o  <= '0';
+		elsif rising_edge(clk_i) then
+		        -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
+			--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
+			sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
+			dac_o  <= sig_in(C_bits);
+		end if;
+	end process seq;
+end rtl;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..21326c26
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/invaders.vhd	
@@ -0,0 +1,271 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+	component mw8080
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+	end component;
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: mw8080
+		port map(
+			Rst_n => Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+
+	GDB0(0) <= DIP(8);  -- Unused ?
+	GDB0(1) <= DIP(7);
+	GDB0(2) <= DIP(6);  -- Unused ?
+	GDB0(3) <= '1';             -- Unused ?
+	GDB0(4) <= not Fire;
+	GDB0(5) <= not MoveLeft;
+	GDB0(6) <= not MoveRight;
+	GDB0(7) <= DIP(5);  -- Unused ?
+
+	GDB1(0) <= not Coin;-- Active High !
+	GDB1(1) <= not Sel2Player;
+	GDB1(2) <= not Sel1Player;
+	GDB1(3) <= '1';-- Unused ?
+	GDB1(4) <= not Fire;
+	GDB1(5) <= not MoveLeft;
+	GDB1(6) <= not MoveRight;
+	GDB1(7) <= '1';-- Unused ?
+
+	GDB2(0) <= DIP(4);  -- LSB Lives 3-6
+	GDB2(1) <= DIP(3);  -- MSB Lives 3-6
+	GDB2(2) <= '0';-- Tilt ?
+	GDB2(3) <= '0';--DIP(2);  -- Bonus life at 1000 or 1500
+	GDB2(4) <= not Fire;
+	GDB2(5) <= not MoveLeft;
+	GDB2(6) <= not MoveRight;
+	GDB2(7) <= '1';--DIP(1);  -- Coin info
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..f16cf379
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..b9a88f96
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,336 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..d65b9f9b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.vhd	
@@ -0,0 +1,350 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire4_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire4_bv(0 DOWNTO 0) <= "0";
+	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	sub_wire2    <= inclk0;
+	sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire3,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_e.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_e.hex
new file mode 100644
index 00000000..5ff2818c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_e.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_f.hex
new file mode 100644
index 00000000..4f7acccc
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_f.hex	
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_g.hex
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_h.hex
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_memory.sv
new file mode 100644
index 00000000..cb74d5cf
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_memory.sv	
@@ -0,0 +1,82 @@
+
+module spaceinvaders_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+
+
+
+sprom #(
+	.init_file("./roms/invaders_h.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_0)
+	);
+
+sprom #(
+	.init_file("./roms/invaders_g.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_1)
+	);
+	
+sprom #(
+	.init_file("./roms/invaders_f.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_2)
+	);
+	
+sprom #(
+	.init_file("./roms/invaders_e.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_e (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_3)
+	);
+
+	
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3) begin
+	Rom_out = 8'b00000000;
+		case (Addr[13:11])
+			3'b000 : Rom_out = rom_data_0;
+			3'b001 : Rom_out = rom_data_1;
+			3'b010 : Rom_out = rom_data_2;
+			3'b011 : Rom_out = rom_data_3;
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_mist.sv
new file mode 100644
index 00000000..ad18ca58
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_mist.sv	
@@ -0,0 +1,211 @@
+module spaceinvaders_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"Space Inv.;;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Overlay, On, Off;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_sys),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+//	.DIP(dip),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(HSync),
+	.VSync(VSync)
+	);
+		
+spaceinvaders_memory spaceinvaders_memory (
+	.Clock(clk_sys),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_sys),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);		
+	  
+spaceinvaders_overlay spaceinvaders_overlay (
+	.Video(Video),
+	.Overlay(~status[5]),
+	.CLK(clk_sys),
+	.Rst_n_s(Rst_n_s),
+	.HSync(HSync),
+	.VSync(VSync),
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({r,r,r}),
+	.G({g,g,g}),
+	.B({b,b,b}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.rotate({1'b0,status[2]}),
+	.scandoubler_disable(scandoublerD),
+	.ce_divider(1),
+	.scanlines(status[4:3]),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_fire2 = 0;
+reg btn_fire3 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h14: btn_fire3       <= key_pressed; // ctrl
+			'h11: btn_fire2       <= key_pressed; // alt
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_overlay.vhd
new file mode 100644
index 00000000..5188f6f0
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_overlay.vhd	
@@ -0,0 +1,127 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+entity spaceinvaders_overlay is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end spaceinvaders_overlay;
+
+architecture rtl of spaceinvaders_overlay is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_G1      : boolean;
+	signal Overlay_G2      : boolean;
+	signal Overlay_R1      : boolean;
+	signal Overlay_G1_VCnt : boolean;
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  Overlay_G1_VCnt <= false;
+	  Overlay_G1 <= false;
+	  Overlay_G2 <= false;
+	  Overlay_R1 <= false;
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt = x"1F") then
+		  Overlay_G1_VCnt <= true;
+		elsif (Vcnt = x"95") then
+		  Overlay_G1_VCnt <= false;
+		end if;
+	  end if;
+
+	  if (HCnt = x"027") and Overlay_G1_VCnt then
+		Overlay_G1 <= true;
+	  elsif (HCnt = x"046") then
+		Overlay_G1 <= false;
+	  end if;
+
+	  if (HCnt = x"046") then
+		Overlay_G2 <= true;
+	  elsif (HCnt = x"0B6") then
+		Overlay_G2 <= false;
+	  end if;
+
+	  if (HCnt = x"1A6") then
+		Overlay_R1 <= true;
+	  elsif (HCnt = x"1E6") then
+		Overlay_R1 <= false;
+	  end if;
+
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1)
+  begin
+	if (Video = '0') then
+	  VideoRGB  <= "000";
+	else
+	  if Overlay_G1 or Overlay_G2 then
+		VideoRGB  <= "010";
+	  elsif Overlay_R1 then
+		VideoRGB  <= "100";
+	  else
+		VideoRGB  <= "111";
+	  end if;
+	end if;
+  end process;
+
+
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_HSYNC   <= HSync;
+  O_VSYNC   <= VSync;
+
+
+end;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/README SpaceLaser.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Midway-Taito 8080 Hardware/README SpaceLaser.txt
rename to Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/README.txt
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.qpf
new file mode 100644
index 00000000..2dd6eff6
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:27:39  November 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:27:39  November 20, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "SpaceLaser"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.qsf
new file mode 100644
index 00000000..97a90f38
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.qsf	
@@ -0,0 +1,173 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 13:58:36  June 09, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		SpaceLaser_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/spacelaser_mist.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/spacelaser_memory.sv
+set_global_assignment -name VHDL_FILE rtl/spacelaser_overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/clr.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY SpaceLaser_mist
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# -----------------------------
+# start ENTITY(SpaceLaser_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(SpaceLaser_mist)
+# ---------------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.sdc
new file mode 100644
index 00000000..f91c127c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/clean.bat
new file mode 100644
index 00000000..83fb0c47
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T8080se.vhd
new file mode 100644
index 00000000..65b92d54
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T8080se.vhd	
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..e09def1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..1c0f2638
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..d37537f9
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/invaders.vhd	
@@ -0,0 +1,245 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		CAB             : out std_logic_vector(7 downto 0);
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: entity work.mw8080
+		port map(
+			Rst_n => Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			CAB => CAB,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+
+	GDB0(0) <= '1';--unknown
+	GDB0(1) <= '1';--unknown
+	GDB0(2) <= '1';--unknown
+	GDB0(3) <= '1';--unknown
+	GDB0(4) <= '1';--unknown
+	GDB0(5) <= '1';--unknown
+	GDB0(6) <= '1';--unknown
+	GDB0(7) <= '1';--unknown
+
+	GDB1(0) <= not Coin;
+	GDB1(1) <= not Sel2Player;
+	GDB1(2) <= not Sel1Player;
+	GDB1(3) <= '1';--unknown
+	GDB1(4) <= not Fire;
+	GDB1(5) <= not MoveLeft;
+	GDB1(6) <= not MoveRight;
+	GDB1(7) <= '1';--unknown
+
+	GDB2(0) <= '0';--unknown
+	GDB2(1) <= '0';--unknown
+	GDB2(2) <= '0';--unknown
+	GDB2(3) <= '0';--unknown
+	GDB2(4) <= not Fire;--player2
+	GDB2(5) <= not MoveLeft;--player2
+	GDB2(6) <= not MoveRight;--player2
+	GDB2(7) <= '1';-- Coinage
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..f16cf379
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..536bb064
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,336 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		CAB             : out std_logic_vector(7 downto 0);
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+	CAB <= std_logic_vector(CntE7(3 downto 0)) & std_logic_vector(CntE5(3 downto 0));
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..f8d0b139
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/pll.vhd	
@@ -0,0 +1,382 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 20,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/clr.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/clr.vhd
new file mode 100644
index 00000000..1ebf53de
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/clr.vhd	
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity clr is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(7 downto 0);
+	data : out std_logic_vector(3 downto 0)
+);
+end entity;
+
+architecture prom of clr is
+	type rom is array(0 to  255) of std_logic_vector(3 downto 0);
+	signal rom_data: rom := (
+		"0101","0111","0001","0011","0100","0110","0110","0010","0010","0101","0101","0010","0010","0001","0011","0010",
+		"0101","0111","0001","0011","0100","0110","0110","0010","0010","0101","0101","0010","0010","0001","0011","0010",
+		"0101","0111","0001","0011","0100","0110","0110","0010","0010","0101","0101","0110","0110","0001","0011","0010",
+		"0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0110","0110","0001","0011","0010",
+		"0101","0111","0001","0011","0100","0110","0110","0010","0010","0101","0101","0010","0010","0001","0011","0010",
+		"0101","0111","0001","0011","0100","0110","0110","0010","0010","0101","0101","0010","0010","0001","0011","0010",
+		"0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0110","0110","0001","0011","0010",
+		"0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0110","0110","0001","0011","0010",
+		"0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0011","0011","0001","0011","0110",
+		"0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0011","0011","0001","0011","0110",
+		"0110","0110","0001","0011","0100","0110","0110","0010","0010","0101","0101","0101","0101","0001","0011","0110",
+		"0110","0110","0001","0011","0100","0110","0110","0010","0010","0101","0101","0101","0101","0001","0011","0110",
+		"0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0011","0011","0001","0011","0110",
+		"0110","0110","0001","0011","0100","0110","0110","0010","0010","0101","0101","0101","0101","0001","0011","0110",
+		"0110","0110","0001","0011","0100","0110","0110","0010","0010","0101","0101","0101","0101","0001","0011","0110",
+		"0110","0110","0001","0011","0100","0110","0110","0010","0010","0101","0101","0101","0101","0001","0011","0110");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la01.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la01.hex
new file mode 100644
index 00000000..761aac36
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la01.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la02.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la02.hex
new file mode 100644
index 00000000..37b1d86a
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la02.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la03.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la03.hex
new file mode 100644
index 00000000..3d5b3e4a
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la03.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la04.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la04.hex
new file mode 100644
index 00000000..acef86ea
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la04.hex	
@@ -0,0 +1,129 @@
+:1000000025070024191812171D1CFE2E0A010000D6
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_memory.sv
new file mode 100644
index 00000000..eb503e87
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_memory.sv	
@@ -0,0 +1,81 @@
+module spacelaser_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+wire [7:0]rom_data_4;
+wire [7:0]rom_data_5;
+
+
+sprom #(
+	.init_file("./roms/la01.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_0)
+	);
+
+sprom #(
+	.init_file("./roms/la02.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_1)
+	);
+	
+sprom #(
+	.init_file("./roms/la03.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_2)
+	);
+	
+sprom #(
+	.init_file("./roms/la04.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_e (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_3)
+	);
+
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3) begin
+	Rom_out = 8'b00000000;
+		case (Addr[15:11])
+			5'b00000 : Rom_out = rom_data_0;
+			5'b00001 : Rom_out = rom_data_1;
+			5'b00010 : Rom_out = rom_data_2;
+			5'b00011 : Rom_out = rom_data_3;
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_mist.sv
new file mode 100644
index 00000000..2f80be68
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_mist.sv	
@@ -0,0 +1,208 @@
+module SpaceLaser_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"SpaceLaser;;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Overlay, On, Off;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_core, clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]CAB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.CAB(CAB),
+	.HSync(HSync),
+	.VSync(VSync)
+	);
+		
+spacelaser_memory spacelaser_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_core),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);		
+	  
+spacelaser_overlay spacelaser_overlay (
+	.Video(Video),
+	.Overlay(~status[5]),
+	.CLK(clk_core),
+	.Rst_n_s(Rst_n_s),
+	.HSync(HSync),
+	.VSync(VSync),
+	.CAB(CAB),
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({r,r,r}),
+	.G({g,g,g}),
+	.B({b,b,b}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.rotate({1'b0,status[2]}),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ce_divider(0),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+
+wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_overlay.vhd
new file mode 100644
index 00000000..05c20798
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_overlay.vhd	
@@ -0,0 +1,228 @@
+-- 2019 by Gehstock
+-- needs some cleanup i´m to Lazy for this
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+entity spacelaser_overlay is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		CAB               : in    std_logic_vector(7 downto 0);
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end spacelaser_overlay;
+
+architecture rtl of spacelaser_overlay is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	
+	signal Overlay_A1      : boolean;
+	signal Overlay_A2      : boolean;
+	signal Overlay_A3      : boolean;
+	signal Overlay_A3_VCnt : boolean;
+	
+	signal Overlay_B1      : boolean;
+	signal Overlay_B2      : boolean;
+	signal Overlay_B2_VCnt : boolean;
+	
+	signal Overlay_G1      : boolean;
+	
+	signal Overlay_P1      : boolean;
+	
+	signal Overlay_R1      : boolean;
+	signal Overlay_R2      : boolean;
+	
+	signal Overlay_Y1      : boolean;
+	signal Overlay_Y2      : boolean;
+	signal Overlay_Y2_VCnt : boolean;
+
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+	signal col_data        : std_logic_vector(3 downto 0);
+
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+
+	  Overlay_A1 <= false;
+	  Overlay_A2 <= false;
+	  Overlay_A3 <= false;
+	  Overlay_A3_VCnt <= false;
+	  
+	  Overlay_B1 <= false;
+	  Overlay_B2 <= false;
+	  Overlay_B2_VCnt <= false;
+	  
+	  Overlay_G1 <= false;
+	  
+	  Overlay_P1 <= false;
+	  
+	  Overlay_R1 <= false;
+	  Overlay_R2 <= false;
+	  
+	  Overlay_Y1 <= false;
+	  Overlay_Y2 <= false;
+	  Overlay_Y2_VCnt <= false;
+
+	  
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt = 0) then
+		  Overlay_A3_VCnt <= true;
+		elsif (Vcnt = 98) then
+		  Overlay_B2_VCnt <= true;
+		  Overlay_A3_VCnt <= false;
+		elsif (Vcnt = 140) then
+		  Overlay_Y2_VCnt <= true;
+		  Overlay_B2_VCnt <= false;
+		elsif (Vcnt = 232) then
+		  Overlay_Y2_VCnt <= false;
+		end if;
+	  end if;  
+	  
+	  if (HCnt = 500) and Overlay_A3_VCnt then
+		Overlay_A3 <= true;
+	  elsif (HCnt = 540) then
+		Overlay_A3 <= false;
+	  end if;
+	  
+	  if (HCnt = 486) and Overlay_B2_VCnt then
+		Overlay_B2 <= true;
+	  elsif (HCnt = 540) then
+		Overlay_B2 <= false;
+	  end if;
+
+	  if (HCnt = 486) and Overlay_Y2_VCnt then
+		Overlay_Y2 <= true;
+	  elsif (HCnt = 540) then
+		Overlay_Y2 <= false;
+	  end if;
+
+	  if (HCnt = 64) then
+		Overlay_R2 <= true;
+	  elsif (HCnt = 96) then
+		Overlay_A2 <= true;
+		Overlay_R2 <= false;
+	  elsif (HCnt = 120) then
+		Overlay_A2 <= false;
+		Overlay_R1 <= true;
+	  elsif (HCnt = 166) then
+		Overlay_R1 <= false;
+		Overlay_Y1 <= true;
+	  elsif (HCnt = 228) then
+	   Overlay_Y1 <= false;
+		Overlay_P1 <= true;
+	  elsif (HCnt = 292) then
+		Overlay_P1 <= false;
+		Overlay_A1 <= true;
+	  elsif (HCnt = 358) then
+		Overlay_G1 <= true;
+		Overlay_A1 <= false;
+	  elsif (HCnt = 430) then
+		Overlay_G1 <= false;
+		Overlay_B1 <= true;
+	  elsif (HCnt = 486) then
+		Overlay_B1 <= false;
+--		if Overlay_A3_VCnt then 
+--			Overlay_A2 <= true;
+--		if Overlay_B2_VCnt then 
+--			Overlay_B2 <= true;
+--		if Overlay_Y2_VCnt then 
+--			Overlay_Y2 <= true;
+--	   elsif (HCnt = 500) then
+--			Overlay_A3 <= false;	
+--	   elsif (HCnt = 540) then
+--			Overlay_B2 <= false;
+--			Overlay_Y2 <= false;
+	  end if; 
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video, Overlay_G1, Overlay_B1, Overlay_B2, Overlay_A1, Overlay_A2, Overlay_A3, Overlay_P1, Overlay_Y1, Overlay_Y2, Overlay_R1, Overlay_R2)
+  begin
+	if (Video = '0') then
+	  VideoRGB  <= "000";
+	else
+	  if Overlay_A1 or Overlay_A2 or Overlay_A3 then--AQUA
+		VideoRGB  <= "011";
+		elsif Overlay_B1 or Overlay_B2 then--BLUE
+		VideoRGB  <= "001";
+	  elsif Overlay_G1 then--GREEN
+		VideoRGB  <= "010";
+	  elsif Overlay_P1 then--PINK
+		VideoRGB  <= "101";
+	  elsif Overlay_R1 or Overlay_R2 then--RED
+		VideoRGB  <= "100";			
+	  elsif Overlay_Y1 or Overlay_Y2 then--YELLOW
+		VideoRGB  <= "110";	
+	  else	  
+		VideoRGB  <= "111";--WHITE
+	  end if;
+	end if;
+  end process;
+  
+  colPROM: entity work.clr
+port map(
+	clk  => Clk,
+	addr => CAB, --should be Video Counters 
+	data => col_data
+);
+
+--  O_VIDEO_R <= col_data(2);
+--  O_VIDEO_G <= col_data(1);
+--  O_VIDEO_B <= col_data(0);
+  
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_HSYNC   <= HSync;
+  O_VSYNC   <= VSync;
+
+
+end;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/README.txt
new file mode 100644
index 00000000..ffd0e157
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/README.txt	
@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: Space Walk port to MiST by Gehstock 
+-- 05 June 2019
+-- 
+---------------------------------------------------------------------------------
+-- 
+-- Midway 8080 Hardware
+-- Audio based on work by Paul Walsh.
+-- Audio and scan converter by MikeJ.
+---------------------------------------------------------------------------------
+-- 
+-- 
+-- Keyboard inputs :
+--
+--   F1          : Start
+--   SPACE       : Fire
+--   RIGHT/LEFT  : Movement
+--
+-- Joystick support.
+-- 
+-- 
+---------------------------------------------------------------------------------
+ToDo: Color Prom
+      Controls + DIP
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qpf
new file mode 100644
index 00000000..31bfde3e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 16:15:41  June 05, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:15:41  June 05, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "SpaceWalk"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qsf
new file mode 100644
index 00000000..224648a1
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qsf	
@@ -0,0 +1,172 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 20:00:37  August 10, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		SpaceWalk_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/SpaceWalk.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Spacewalk_memory.sv
+set_global_assignment -name VHDL_FILE rtl/Spacewalk_overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY SpaceWalk
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# -----------------------
+# start ENTITY(SpaceWalk)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(SpaceWalk)
+# ---------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.sdc
new file mode 100644
index 00000000..f91c127c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/clean.bat
new file mode 100644
index 00000000..83fb0c47
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/SpaceWalk.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/SpaceWalk.sv
new file mode 100644
index 00000000..708187bd
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/SpaceWalk.sv	
@@ -0,0 +1,187 @@
+module SpaceWalk(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"Spacewalk;;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+//	"O5,Overlay, On, Off;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_core, clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+
+invaders invaders(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(btn_one_player),
+	.Fire(~joystick_0[4]),
+	.MoveLeft(~joystick_0[1]),
+	.MoveRight(~joystick_0[0]),
+//	.DIP(dip),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(hs),
+	.VSync(vs)
+	);
+		
+Spacewalk_memory Spacewalk_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_core),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({Video,Video,Video}),
+	.G({Video,Video,Video}),
+	.B({Video,Video,Video}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.scandoubler_disable(scandoublerD),
+	.ce_divider(0),
+	.scanlines(status[4:3]),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac #(
+	.c_bits(8))
+dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_coin  = 0;
+
+reg gun1_up  = 0;
+reg gun1_dw  = 0;
+reg gun2_up  = 0;
+reg gun2_dw  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h15: gun1_up       <= key_pressed; // Q
+			'h35: gun1_dw       <= key_pressed; // Y
+			'h75: gun2_up       <= key_pressed; // Arrow up
+			'h72: gun2_dw       <= key_pressed; // Arrow down
+		endcase
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_memory.sv
new file mode 100644
index 00000000..0d77837a
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_memory.sv	
@@ -0,0 +1,132 @@
+
+module Spacewalk_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+wire [7:0]rom_data_4;
+wire [7:0]rom_data_5;
+wire [7:0]rom_data_6;
+wire [7:0]rom_data_7;
+
+
+sprom #(
+	.init_file("./roms/sw.h.hex"),
+	.widthad_a(10),
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_0)
+	);
+
+sprom #(
+	.init_file("./roms/sw.g.hex"),
+	.widthad_a(10),
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_1)
+	);
+	
+sprom #(
+	.init_file("./roms/sw.f.hex"),
+	.widthad_a(10),
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_2)
+	);
+	
+sprom #(
+	.init_file("./roms/sw.e.hex"),
+	.widthad_a(10),
+	.width_a(8))
+u_rom_e (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_3)
+	);
+
+	
+	
+	
+	sprom #(
+	.init_file("./roms/sw.d.hex"),
+	.widthad_a(10),
+	.width_a(8))
+u_rom_d (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_4)
+	);
+
+sprom #(
+	.init_file("./roms/sw.c.hex"),
+	.widthad_a(10),
+	.width_a(8))
+u_rom_c (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_5)
+	);
+	
+sprom #(
+	.init_file("./roms/sw.b.hex"),
+	.widthad_a(10),
+	.width_a(8))
+u_rom_b (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_6)
+	);
+	
+sprom #(
+	.init_file("./roms/sw.a.hex"),
+	.widthad_a(10),
+	.width_a(8))
+u_rom_a (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_7)
+	);
+	
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5, rom_data_6, rom_data_7) begin
+	Rom_out = 8'b00000000;
+		case (Addr[13:10])
+			4'b0000 : Rom_out = rom_data_0;
+			4'b0001 : Rom_out = rom_data_1;// 0100 0000 0000
+			4'b0010 : Rom_out = rom_data_2;// 1000 0000 0000
+			4'b0011 : Rom_out = rom_data_3;
+			
+			4'b0100 : Rom_out = rom_data_4;
+			4'b0101 : Rom_out = rom_data_5;
+			4'b0110 : Rom_out = rom_data_6;
+			4'b0111 : Rom_out = rom_data_7;
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_overlay.vhd
new file mode 100644
index 00000000..c45739e0
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_overlay.vhd	
@@ -0,0 +1,127 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+entity Spacewalk_overlay is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end Spacewalk_overlay;
+
+architecture rtl of Spacewalk_overlay is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_G1      : boolean;
+	signal Overlay_G2      : boolean;
+	signal Overlay_R1      : boolean;
+	signal Overlay_G1_VCnt : boolean;
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  Overlay_G1_VCnt <= false;
+	  Overlay_G1 <= false;
+	  Overlay_G2 <= false;
+	  Overlay_R1 <= false;
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt = x"1F") then
+		  Overlay_G1_VCnt <= true;
+		elsif (Vcnt = x"95") then
+		  Overlay_G1_VCnt <= false;
+		end if;
+	  end if;
+
+	  if (HCnt = x"027") and Overlay_G1_VCnt then
+		Overlay_G1 <= true;
+	  elsif (HCnt = x"046") then
+		Overlay_G1 <= false;
+	  end if;
+
+	  if (HCnt = x"046") then
+		Overlay_G2 <= true;
+	  elsif (HCnt = x"0B6") then
+		Overlay_G2 <= false;
+	  end if;
+
+	  if (HCnt = x"1A6") then
+		Overlay_R1 <= true;
+	  elsif (HCnt = x"1E6") then
+		Overlay_R1 <= false;
+	  end if;
+
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1)
+  begin
+	if (Video = '0') then
+	  VideoRGB  <= "000";
+	else
+	  if Overlay_G1 or Overlay_G2 then
+		VideoRGB  <= "010";
+	  elsif Overlay_R1 then
+		VideoRGB  <= "100";
+	  else
+		VideoRGB  <= "111";
+	  end if;
+	end if;
+  end process;
+
+
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_HSYNC   <= not HSync;
+  O_VSYNC   <= not VSync;
+
+
+end;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T8080se.vhd
new file mode 100644
index 00000000..65b92d54
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T8080se.vhd	
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..e09def1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..1c0f2638
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..5c95d579
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders.vhd	
@@ -0,0 +1,281 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaders is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl4      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		SoundCtrl6      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaders;
+
+architecture rtl of invaders is
+
+	component mw8080
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+	end component;
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(7 downto 0);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: mw8080
+		port map(
+			Rst_n => Rst_n,--Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+
+	GDB0(0) <= '0';--
+	GDB0(1) <= '0';--
+	GDB0(2) <= '0';--
+	GDB0(3) <= '0';--
+	GDB0(4) <= '0';--
+	GDB0(5) <= '0';--
+	GDB0(6) <= '0';--
+	GDB0(7) <= '0';--
+
+	GDB1(0) <= '1';-- Unused ?
+	GDB1(1) <= '1';-- Unused ?
+	GDB1(2) <= '1';-- Unused ?
+	GDB1(2) <= '1';-- Unused ?
+	GDB1(4) <= not Sel2Player;
+	GDB1(5) <= not Sel1Player;
+	GDB1(6) <= not Coin;
+	GDB1(7) <= '1';-- Unused ?
+
+	GDB2(0) <= '0';--Game_Time
+	GDB2(1) <= '0';--Game_Time
+	GDB2(2) <= '0';--Coinage
+	GDB2(3) <= '0';--Coinage
+	GDB2(4) <= '0';--Extended Time At
+	GDB2(5) <= '0';--Extended Time At
+	GDB2(6) <= '0';--Springboard Alignment
+	GDB2(7) <= '0';--unused
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl4 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			SoundCtrl6 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);--audio_1_w
+			end if;
+			--if PortWr(4) = '1' and OldSample = '0' then
+				--D5(15 downto 8) <= DB;
+				--D5(7 downto 0) <= D5(15 downto 8);
+			--end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);--tone_generator_lo_w
+			end if;
+			if PortWr(6) = '1' then
+				SoundCtrl6 <= DB(5 downto 0);--midway_tone_generator_hi_w
+			end if;	
+			if PortWr(7) = '1' then
+				SoundCtrl4 <= DB(5 downto 0);--audio_2_w
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..f16cf379
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..b9a88f96
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,336 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..f8d0b139
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.vhd	
@@ -0,0 +1,382 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 20,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.a.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.a.bin
new file mode 100644
index 0000000000000000000000000000000000000000..bd675deceba1cad7515df8db2da07f7993aafd0c
GIT binary patch
literal 1024
zcmeH@F%H5&3<P--64Xx4tDGg`J)NBZ|9=P|I`ROjn|`JkbD3OQM}%aB&>`(MJ<(;}
zGU@D!#;}yLs}$Nn$UA=pJQA+Z)gp}kN$<ujq}oy?3Ofqd*&Hh7fu7&!<$8Jz#({C*
GzX#s8?3vsE

literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.a.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.a.hex
new file mode 100644
index 00000000..c3bcceac
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.a.hex	
@@ -0,0 +1,65 @@
+:10000000494E40414E445052455353405448454058
+:100010004F4E4540504C4159455240425554544F23
+:100020004E4F524445504F53495440324E44404342
+:100030004F494E40414E4450524553534054484519
+:100040004054574F40504C415945524042555454EA
+:100050004F4E455854454E4445444D495353494FDE
+:100060004E50524556494F555340484947484053D2
+:10007000434F5245434F4D42494E454440494E53EC
+:1000800045525440434F494E353600FFFFFFFFFFB6
+:10009000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF70
+:1000A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF60
+:1000B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF50
+:1000C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF40
+:1000D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF30
+:1000E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF20
+:1000F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF10
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+:10018000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7F
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+:1001A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5F
+:1001B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4F
+:1001C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3F
+:1001D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2F
+:1001E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1F
+:1001F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0F
+:10020000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE
+:10021000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEE
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+:10025000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAE
+:10026000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9E
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+:10029000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6E
+:1002A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5E
+:1002B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4E
+:1002C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3E
+:1002D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2E
+:1002E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1E
+:1002F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0E
+:10030000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD
+:10031000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFED
+:10032000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDD
+:10033000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCD
+:10034000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBD
+:10035000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAD
+:10036000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9D
+:10037000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8D
+:10038000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7D
+:10039000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6D
+:1003A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5D
+:1003B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4D
+:1003C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3D
+:1003D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2D
+:1003E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1D
+:1003F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0D
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.b.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.b.bin
new file mode 100644
index 0000000000000000000000000000000000000000..5d164292d9b6d556749ac575483ec9fffb328b2d
GIT binary patch
literal 1024
zcmZuvO^91n6u$4hn>&-2J8zQABfan5XL4>brfoWlG@Tz9+9AP-q3SfHQ(Hu_Y29?!
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.b.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.b.hex
new file mode 100644
index 00000000..93134886
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.b.hex	
@@ -0,0 +1,65 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.c.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.c.bin
new file mode 100644
index 0000000000000000000000000000000000000000..1cfd2e879f8aba465600f5bd3a4b2e9c03c539b8
GIT binary patch
literal 1024
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DN+Lg0

literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.c.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.c.hex
new file mode 100644
index 00000000..88bf7240
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.c.hex	
@@ -0,0 +1,65 @@
+:1000000023732372233A6020773E02325220C93E86
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.d.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.d.bin
new file mode 100644
index 0000000000000000000000000000000000000000..3bd482c3dee9d9ff6003f532d7a72b7f224f2372
GIT binary patch
literal 1024
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.d.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.d.hex
new file mode 100644
index 00000000..d7cdf5e2
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.d.hex	
@@ -0,0 +1,65 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.e.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.e.bin
new file mode 100644
index 0000000000000000000000000000000000000000..efcc5800950c0f936aad5d3f37b29d1cf5c2c8c9
GIT binary patch
literal 1024
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.e.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.e.hex
new file mode 100644
index 00000000..107eddf5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.e.hex	
@@ -0,0 +1,65 @@
+:1000000000003F0000000000001800000080FF0119
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.f.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.f.bin
new file mode 100644
index 0000000000000000000000000000000000000000..07a82f8c7a3a0418f11f788be96b95ebc7b00317
GIT binary patch
literal 1024
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.f.hex
new file mode 100644
index 00000000..7339ab28
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.f.hex	
@@ -0,0 +1,65 @@
+:1000000023702370093DC2FF07C94E237E5FD301D1
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.g.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.g.bin
new file mode 100644
index 0000000000000000000000000000000000000000..6f921f660a89c57d5282227f6d42983c814e8b35
GIT binary patch
literal 1024
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.g.hex
new file mode 100644
index 00000000..65a5a680
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.g.hex	
@@ -0,0 +1,65 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.h.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.h.bin
new file mode 100644
index 0000000000000000000000000000000000000000..4172f1bc951de761390a27529e800828537f0f13
GIT binary patch
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H-vIpwK7(%$

literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.h.hex
new file mode 100644
index 00000000..18ba68e5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.h.hex	
@@ -0,0 +1,65 @@
+:100000000000310024C31700FBC9000000000000FD
+:10001000F5C5D5E5C34C03DB0217DA2000C3660C37
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/README SuperEarthInvasion.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Midway-Taito 8080 Hardware/README SuperEarthInvasion.txt
rename to Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/README.txt
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qpf
new file mode 100644
index 00000000..8c553b65
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:27:39  November 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:27:39  November 20, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "SuperEarthInvasion"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qsf
new file mode 100644
index 00000000..0ebe06ab
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qsf	
@@ -0,0 +1,172 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 19:20:51  August 08, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		SuperEarthInvasion_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/SuperEarthInvasion_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/SuperEarthInvasion_memory.sv
+set_global_assignment -name VHDL_FILE rtl/SuperEarthInvasion_overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY SuperEarthInvasion_mist
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# -------------------------------------
+# start ENTITY(SuperEarthInvasion_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(SuperEarthInvasion_mist)
+# -----------------------------------
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.sdc
new file mode 100644
index 00000000..f91c127c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/clean.bat
new file mode 100644
index 00000000..83fb0c47
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_memory.sv
new file mode 100644
index 00000000..04687a33
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_memory.sv	
@@ -0,0 +1,81 @@
+module SuperEarthInvasion_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+wire [7:0]rom_data_4;
+wire [7:0]rom_data_5;
+
+
+sprom #(
+	.init_file("./roms/earthinv_h.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_0)
+	);
+
+sprom #(
+	.init_file("./roms/earthinv_g.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_1)
+	);
+	
+sprom #(
+	.init_file("./roms/earthinv_f.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_2)
+	);
+	
+sprom #(
+	.init_file("./roms/earthinv_e.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_e (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_3)
+	);
+
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3) begin
+	Rom_out = 8'b00000000;
+		case (Addr[15:11])
+			5'b00000 : Rom_out = rom_data_0;
+			5'b00001 : Rom_out = rom_data_1;
+			5'b00010 : Rom_out = rom_data_2;
+			5'b00011 : Rom_out = rom_data_3;
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_mist.sv
new file mode 100644
index 00000000..0c0853d6
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_mist.sv	
@@ -0,0 +1,212 @@
+module SuperEarthInvasion_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"SEarthInv.;;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Overlay, On, Off;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_core, clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+	.DIP(dip),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(HSync),
+	.VSync(VSync)
+	);
+		
+SuperEarthInvasion_memory SuperEarthInvasion_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_core),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);		
+	  
+SuperEarthInvasion_overlay SuperEarthInvasion_overlay (
+	.Video(Video),
+	.Overlay(~status[5]),
+	.CLK(clk_core),
+	.Rst_n_s(Rst_n_s),
+	.HSync(HSync),
+	.VSync(VSync),
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({r,r,r}),
+	.G({g,g,g}),
+	.B({b,b,b}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.rotate({1'b0,status[2]}),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ce_divider(0),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_fire2 = 0;
+reg btn_fire3 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h14: btn_fire3       <= key_pressed; // ctrl
+			'h11: btn_fire2       <= key_pressed; // alt
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_overlay.vhd
new file mode 100644
index 00000000..adbf653b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_overlay.vhd	
@@ -0,0 +1,128 @@
+--2019 by Gehstock
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+entity SuperEarthInvasion_overlay is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end SuperEarthInvasion_overlay;
+
+architecture rtl of SuperEarthInvasion_overlay is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_G1      : boolean;
+	signal Overlay_G2      : boolean;
+	signal Overlay_R1      : boolean;
+	signal Overlay_G1_VCnt : boolean;
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  Overlay_G1_VCnt <= false;
+	  Overlay_G1 <= false;
+	  Overlay_G2 <= false;
+	  Overlay_R1 <= false;
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt = x"1F") then
+		  Overlay_G1_VCnt <= true;
+		elsif (Vcnt = x"95") then
+		  Overlay_G1_VCnt <= false;
+		end if;
+	  end if;
+
+	  if (HCnt = x"027") and Overlay_G1_VCnt then
+		Overlay_G1 <= true;
+	  elsif (HCnt = x"046") then
+		Overlay_G1 <= false;
+	  end if;
+
+	  if (HCnt = x"046") then
+		Overlay_G2 <= true;
+	  elsif (HCnt = x"0B6") then
+		Overlay_G2 <= false;
+	  end if;
+
+	  if (HCnt = x"1A6") then
+		Overlay_R1 <= true;
+	  elsif (HCnt = x"1E6") then
+		Overlay_R1 <= false;
+	  end if;
+
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1)
+  begin
+	if (Video = '0') then
+	  VideoRGB  <= "000";
+	else
+	  if Overlay_G1 or Overlay_G2 then
+		VideoRGB  <= "010";
+	  elsif Overlay_R1 then
+		VideoRGB  <= "100";
+	  else
+		VideoRGB  <= "111";
+	  end if;
+	end if;
+  end process;
+
+
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_HSYNC   <= HSync;
+  O_VSYNC   <= VSync;
+
+
+end;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T8080se.vhd
new file mode 100644
index 00000000..65b92d54
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T8080se.vhd	
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..e09def1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..1c0f2638
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/dac.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/dac.vhd
new file mode 100644
index 00000000..db58d70b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/dac.vhd	
@@ -0,0 +1,48 @@
+-------------------------------------------------------------------------------
+--
+-- Delta-Sigma DAC
+--
+-- Refer to Xilinx Application Note XAPP154.
+--
+-- This DAC requires an external RC low-pass filter:
+--
+--   dac_o 0---XXXXX---+---0 analog audio
+--              3k3    |
+--                    === 4n7
+--                     |
+--                    GND
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.numeric_std.all;
+
+entity dac is
+	generic (
+		C_bits  : integer := 8
+	);
+	port (
+		clk_i   : in  std_logic;
+		res_n_i : in  std_logic;
+		dac_i   : in  std_logic_vector(C_bits-1 downto 0);
+		dac_o   : out std_logic
+	);
+end dac;
+
+architecture rtl of dac is
+	signal sig_in: unsigned(C_bits downto 0);
+begin
+	seq: process(clk_i, res_n_i)
+	begin
+		if res_n_i = '0' then
+			sig_in <= to_unsigned(2**C_bits, sig_in'length);
+			dac_o  <= '0';
+		elsif rising_edge(clk_i) then
+		        -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
+			--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
+			sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
+			dac_o  <= sig_in(C_bits);
+		end if;
+	end process seq;
+end rtl;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..f089f1f2
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/invaders.vhd	
@@ -0,0 +1,243 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: entity work.mw8080
+		port map(
+			Rst_n => Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+
+	GDB0(0) <= DIP(8);  -- Unused ?
+	GDB0(1) <= DIP(7);
+	GDB0(2) <= DIP(6);  -- Unused ?
+	GDB0(3) <= '1';             -- Unused ?
+	GDB0(4) <= not Fire;
+	GDB0(5) <= not MoveLeft;
+	GDB0(6) <= not MoveRight;
+	GDB0(7) <= DIP(5);  -- Unused ?
+
+	GDB1(0) <= not Coin;-- Active High !
+	GDB1(1) <= not Sel2Player;
+	GDB1(2) <= not Sel1Player;
+	GDB1(3) <= '1';-- Unused ?
+	GDB1(4) <= not Fire;
+	GDB1(5) <= not MoveLeft;
+	GDB1(6) <= not MoveRight;
+	GDB1(7) <= '1';-- Unused ?
+
+	GDB2(0) <= DIP(4);  -- LSB Lives 3-6
+	GDB2(1) <= DIP(3);  -- MSB Lives 3-6
+	GDB2(2) <= '0';-- Tilt ?
+	GDB2(3) <= '0';--DIP(2);  -- Bonus life at 1000 or 1500
+	GDB2(4) <= not Fire;
+	GDB2(5) <= not MoveLeft;
+	GDB2(6) <= not MoveRight;
+	GDB2(7) <= '1';--DIP(1);  -- Coin info
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..f16cf379
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..1d9ad578
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,335 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..f8d0b139
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.vhd	
@@ -0,0 +1,382 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 20,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_e.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_e.hex
new file mode 100644
index 00000000..9d3a7323
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_e.hex	
@@ -0,0 +1,129 @@
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+:1007F00003040E05110E0C0000080808080800008C
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_f.hex
new file mode 100644
index 00000000..a6308ac3
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_f.hex	
@@ -0,0 +1,129 @@
+:10000000131226050E112626262612020E1104268C
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_g.hex
new file mode 100644
index 00000000..cf7f462f
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_g.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_h.hex
new file mode 100644
index 00000000..d334786f
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_h.hex	
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+:10052000327120CD63053A7620FE15DA34053A584B
+:100530001B3276203A7820A7215520C25B05115046
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+:10055000327F20217320060BC3321A117320060B41
+:10056000C3321A2173207EE680C2C1053AC120FE43
+:10057000043A6920CAB705A7C82336003A7020A7F5
+:10058000CA8905473ACF20B8D03A7120A7CA960544
+:10059000473ACF20B8D0237EA7CA1B062A76204E22
+:1005A0002300227620CD2F06D0CD7A0179C60767A9
+:1005B0007DD60A6F227B202173207EF6807723343C
+:1005C000C9117C20CD061AD0237EE601C244062341
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+:1005E000D60C3279203A7B20473A7E2080327B201D
+:1005F000CD6C063A7B20FE15DA12063A6120A7C8B8
+:100600003A7B20FE1EDA1206FE2700D2120697322F
+:1006100015203A7320F601327320C93A1B20C60810
+:1006200067CD6F1579FE0CDAA5050E0BC3A5050D78
+:100630003A6720676916057EA737C07DC60B6F1520
+:10064000C23706C9217820357EFE03C26706CD7504
+:100650000621DC1C227920217C2035352B35353EC6
+:1006600006327D20C36C06A7C0C37506217920CD54
+:100670003B1AC3EE13217920CD3B1AC3AA1422489A
+:1006800020C9E13A8020FE02C02183207EA7CA0F44
+:10069000053A5620A7C20F05237EA7C2AB063A82B1
+:1006A00020FE02DA0F053601CD3C07118A20CD0667
+:1006B0001AD02185207EA7C2D606218A207E232338
+:1006C00086328A20CD1012218A207EFE28DAF90691
+:1006D000FEE1D2F906C906FECDDC1923357EFE1FE8
+:1006E000CA4B07FE18CA0C07A7C006EF2198207E48
+:1006F000A077E620D305000000CDD212CDCB142187
+:100700008320060ACD5F0706FEC3DC193E0132F1E5
+:10071000202A8D20460E0421501D114C1D1AB8CAE6
+:10072000280723130DC21D077E3287202600682963
+:1007300029292922F220CDD212C3F108CD4207C3C4
+:100740003914218720CD3B1AC3471A06102198205F
+:100750007EB077CD7017217C1D228720C33C071106
+:10076000831BC3321A3E01329320310024FBCD7922
+:1007700019CDF6172113301104000E04CDF3083AF9
+:10078000EB203D2110280E14C2570811CF1ACDF3CB
+:1007900008DB01E604CA7F070699AF32CE203AEBA8
+:1007A00020802732EB20CD471921000022F820229B
+:1007B000FC20CD2519CD2B19CDD7192101017C3273
+:1007C000EF2022E72022E520CDD912CDEF01CDF593
+:1007D00001CDD10832FF2132FF22CDD700AF32FE4A
+:1007E0002132FE22CDC001CD041921783822FC210E
+:1007F00022FC22CDE401CD7F1ACD8D08CDD6090093
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/README.txt
new file mode 100644
index 00000000..04cbfbca
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/README.txt	
@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: Vortex port to MiST by Gehstock 
+-- 08 June 2019
+-- 
+---------------------------------------------------------------------------------
+-- 
+-- Midway 8080 Hardware
+-- Audio based on work by Paul Walsh.
+-- Audio and scan converter by MikeJ.
+---------------------------------------------------------------------------------
+-- 
+-- 
+-- Keyboard inputs :
+--
+--   F1          : Start
+--   SPACE       : Fire
+--   RIGHT/LEFT  : Movement
+--
+-- Joystick support.
+-- 
+-- 
+---------------------------------------------------------------------------------
+
+ToDo  	Sound
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qpf
new file mode 100644
index 00000000..8bec1592
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 16:15:41  June 05, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:15:41  June 05, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "Vortex"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qsf
new file mode 100644
index 00000000..b86690cb
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qsf	
@@ -0,0 +1,176 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 18:00:39  August 08, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Vortex_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Vortex_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Vortex_memory.sv
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/1.t36.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/2.t35.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/3.t34.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/4.t33.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/5.t32.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/6.t31.vhd
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY Vortex_mist
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# -------------------------
+# start ENTITY(Vortex_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(Vortex_mist)
+# -----------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/clean.bat
new file mode 100644
index 00000000..ac9bf0a8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/clean.bat	
@@ -0,0 +1,16 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s build_id.v
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T8080se.vhd
new file mode 100644
index 00000000..65b92d54
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T8080se.vhd	
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..e09def1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..1c0f2638
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_memory.sv
new file mode 100644
index 00000000..46ef1be8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_memory.sv	
@@ -0,0 +1,80 @@
+
+module Vortex_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+wire [7:0]rom_data_4;
+wire [7:0]rom_data_5;
+wire [10:0]rom_addr = {Addr[11:10],~Addr[9],Addr[8:4],~Addr[3],Addr[2:1],~Addr[0]};
+
+rom1t36 rom1t36 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_0)
+);
+
+rom2t35 rom2t35 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_1)
+);
+
+rom3t34 rom3t34 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_2)
+);
+
+rom4t33 rom4t33 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_3)
+);
+
+rom5t32 rom5t32 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_4)
+);
+
+rom6t31 rom6t31 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_5)
+);
+	
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5) begin
+	Rom_out = 8'b00000000;
+		case (Addr[15:11])
+			5'b00000 : Rom_out = rom_data_0;
+			5'b00001 : Rom_out = rom_data_1;
+			5'b00010 : Rom_out = rom_data_2;
+			5'b00011 : Rom_out = rom_data_3;
+			5'b01000 : Rom_out = rom_data_4;
+			5'b01001 : Rom_out = rom_data_5;
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_mist.sv
new file mode 100644
index 00000000..a2b52c05
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_mist.sv	
@@ -0,0 +1,191 @@
+module Vortex_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"Vortex;;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_core, clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hs, vs;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+	.MoveUp(~m_up),
+	.MoveDown(~m_down),	
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(hs),
+	.VSync(vs)
+	);
+		
+Vortex_memory Vortex_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_core),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({Video,Video,Video}),
+	.G({Video,Video,Video}),
+	.B({Video,Video,Video}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.rotate({1'b0,status[2]}),
+	.scandoubler_disable(scandoublerD),
+	.ce_divider(0),
+	.scanlines(status[4:3]),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_up     = status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+
+
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..40003ea4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders.vhd	
@@ -0,0 +1,283 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		MoveUp          : in  std_logic;
+		MoveDown        : in  std_logic;
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+	component mw8080
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+	end component;
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+	signal GDB_A        : unsigned(1 downto 0);
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: mw8080
+		port map(
+			Rst_n => Rst_n,--Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+--	with AD_i(9 downto 8) select
+--		GDB <= GDB0 when "00",
+--				GDB1 when "01",
+--				GDB2 when "10",
+--				S when others;
+				
+			GDB_A <= not AD_i(9) & AD_i(8);
+
+	with GDB_A select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+
+
+	GDB0(0) <= '1';--IPT_UNKNOWN
+	GDB0(1) <= '1';--IPT_UNKNOWN
+	GDB0(2) <= '1';--IPT_UNKNOWN
+	GDB0(3) <= '1';--IPT_UNKNOWN
+	GDB0(4) <= '1';--IPT_UNKNOWN
+	GDB0(5) <= '1';--IPT_UNKNOWN
+	GDB0(6) <= '1';--IPT_UNKNOWN
+	GDB0(7) <= '1';--IPT_UNKNOWN
+	
+	GDB1(0) <= Coin;
+	GDB1(1) <= not Sel2Player;
+	GDB1(2) <= not Sel1Player;
+	GDB1(3) <= '1';
+	GDB1(4) <= not Fire;--controller
+	GDB1(5) <= not MoveLeft;--controller
+	GDB1(6) <= not MoveRight;--controller
+	GDB1(7) <= '1';
+
+	GDB2(0) <= '0';--active high
+	GDB2(1) <= '0';--active high
+	GDB2(2) <= '0';--active high
+	GDB2(3) <= '0';--active high
+	GDB2(4) <= not Fire;--controller 2
+	GDB2(5) <= not MoveLeft;--controller 2
+	GDB2(6) <= not MoveRight;--controller 2
+	GDB2(7) <= '0';--active low
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..f16cf379
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..b9a88f96
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,336 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..97a42db7
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.vhd	
@@ -0,0 +1,382 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 20,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/1.t36.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/1.t36.vhd
new file mode 100644
index 00000000..5cd19142
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/1.t36.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity rom1t36 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of rom1t36 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"C2",X"27",X"19",X"2A",X"A7",X"7D",X"2A",X"C2",X"41",X"CD",X"C3",X"40",X"01",X"81",X"FE",X"7C",
+		X"13",X"20",X"44",X"23",X"E1",X"4D",X"00",X"C9",X"C3",X"19",X"1B",X"C6",X"01",X"3E",X"D6",X"32",
+		X"23",X"13",X"C2",X"0D",X"02",X"22",X"F3",X"C9",X"00",X"00",X"47",X"7E",X"77",X"1A",X"12",X"78",
+		X"20",X"F5",X"CA",X"A7",X"17",X"E4",X"A6",X"C3",X"CA",X"76",X"03",X"3D",X"93",X"C3",X"3A",X"02",
+		X"ED",X"C2",X"CD",X"1E",X"1F",X"92",X"1E",X"C3",X"C2",X"40",X"1F",X"54",X"92",X"CD",X"C9",X"1F",
+		X"20",X"E6",X"32",X"3C",X"20",X"E6",X"51",X"C3",X"CD",X"1F",X"15",X"D2",X"D2",X"C3",X"3A",X"1D",
+		X"51",X"C3",X"3A",X"02",X"20",X"E4",X"32",X"3C",X"3A",X"02",X"20",X"E5",X"32",X"3C",X"20",X"E5",
+		X"32",X"3C",X"20",X"E3",X"51",X"C3",X"21",X"02",X"20",X"E4",X"51",X"C3",X"3A",X"02",X"20",X"E3",
+		X"E4",X"32",X"21",X"20",X"21",X"C0",X"00",X"C9",X"21",X"00",X"32",X"97",X"20",X"E3",X"97",X"C9",
+		X"E5",X"20",X"CD",X"D5",X"15",X"B4",X"E1",X"D1",X"00",X"00",X"11",X"00",X"20",X"B0",X"D3",X"2A",
+		X"15",X"96",X"DE",X"C3",X"3A",X"15",X"20",X"E1",X"D6",X"3A",X"A7",X"20",X"D9",X"C2",X"CD",X"03",
+		X"20",X"E0",X"CA",X"A7",X"04",X"EE",X"CC",X"C3",X"CA",X"A7",X"04",X"EE",X"A1",X"C3",X"3A",X"01",
+		X"11",X"06",X"14",X"00",X"06",X"CD",X"11",X"15",X"3A",X"01",X"20",X"F6",X"0A",X"FE",X"D6",X"DA",
+		X"B4",X"CD",X"3A",X"15",X"20",X"D6",X"01",X"FE",X"20",X"B0",X"F0",X"21",X"22",X"32",X"20",X"D3",
+		X"15",X"96",X"32",X"97",X"20",X"D1",X"DA",X"32",X"1C",X"CA",X"C3",X"03",X"03",X"78",X"CD",X"00",
+		X"20",X"E8",X"02",X"3E",X"32",X"00",X"20",X"F5",X"32",X"20",X"20",X"D7",X"D9",X"32",X"32",X"20",
+		X"20",X"D2",X"02",X"3E",X"DD",X"32",X"32",X"20",X"05",X"3E",X"00",X"32",X"3E",X"20",X"32",X"10",
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+		X"01",X"0E",X"22",X"CD",X"C9",X"02",X"17",X"21",X"02",X"22",X"CE",X"21",X"11",X"20",X"22",X"CE",
+		X"C3",X"09",X"05",X"F7",X"17",X"21",X"11",X"2F",X"11",X"2F",X"0B",X"90",X"08",X"0E",X"F1",X"CD",
+		X"2E",X"15",X"03",X"11",X"0E",X"06",X"C3",X"09",X"0B",X"98",X"08",X"0E",X"F1",X"CD",X"21",X"09");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/2.t35.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/2.t35.vhd
new file mode 100644
index 00000000..4b813941
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/2.t35.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity rom2t35 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of rom2t35 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"49",X"7F",X"49",X"49",X"00",X"36",X"00",X"00",X"24",X"1F",X"24",X"44",X"00",X"1F",X"00",X"00",
+		X"41",X"7F",X"41",X"41",X"00",X"3E",X"00",X"00",X"41",X"3E",X"41",X"41",X"00",X"22",X"00",X"00",
+		X"70",X"C3",X"FF",X"4A",X"FF",X"FF",X"01",X"FF",X"49",X"7F",X"49",X"49",X"00",X"41",X"00",X"00",
+		X"08",X"7F",X"08",X"08",X"00",X"7F",X"00",X"00",X"41",X"3E",X"45",X"41",X"00",X"47",X"00",X"00",
+		X"9C",X"CD",X"57",X"01",X"3D",X"84",X"67",X"3D",X"41",X"00",X"41",X"7F",X"00",X"00",X"00",X"00",
+		X"01",X"7F",X"01",X"01",X"00",X"01",X"00",X"00",X"3D",X"3D",X"87",X"5F",X"C3",X"87",X"1D",X"FC",
+		X"10",X"7F",X"04",X"08",X"00",X"7F",X"00",X"00",X"20",X"7F",X"20",X"18",X"00",X"7F",X"00",X"00",
+		X"48",X"7F",X"48",X"48",X"00",X"30",X"00",X"00",X"41",X"3E",X"41",X"41",X"00",X"3E",X"00",X"00",
+		X"48",X"7F",X"4A",X"4C",X"00",X"31",X"00",X"00",X"07",X"00",X"7E",X"1E",X"07",X"1E",X"00",X"00",
+		X"40",X"40",X"40",X"7F",X"00",X"40",X"00",X"00",X"49",X"32",X"49",X"49",X"00",X"26",X"00",X"00",
+		X"06",X"78",X"06",X"01",X"00",X"78",X"00",X"00",X"01",X"7E",X"01",X"01",X"00",X"7E",X"00",X"00",
+		X"14",X"63",X"14",X"08",X"00",X"63",X"00",X"00",X"F1",X"CD",X"CD",X"09",X"09",X"CE",X"14",X"C9",
+		X"45",X"43",X"51",X"49",X"00",X"61",X"00",X"00",X"10",X"60",X"10",X"0F",X"00",X"60",X"00",X"00",
+		X"00",X"00",X"7F",X"21",X"00",X"01",X"00",X"00",X"3E",X"00",X"49",X"45",X"3E",X"51",X"00",X"00",
+		X"42",X"00",X"49",X"41",X"66",X"59",X"00",X"00",X"23",X"00",X"49",X"45",X"31",X"49",X"00",X"00",
+		X"72",X"00",X"51",X"51",X"4E",X"51",X"00",X"00",X"0C",X"00",X"24",X"14",X"04",X"7F",X"00",X"00",
+		X"40",X"00",X"48",X"47",X"60",X"50",X"00",X"00",X"1E",X"00",X"49",X"29",X"46",X"49",X"00",X"00",
+		X"31",X"00",X"49",X"49",X"3C",X"4A",X"00",X"00",X"36",X"00",X"49",X"49",X"36",X"49",X"00",X"00",
+		X"5F",X"20",X"01",X"21",X"C3",X"3C",X"0B",X"D2",X"A1",X"21",X"C3",X"20",X"40",X"FE",X"AD",X"3A",
+		X"7E",X"23",X"00",X"BB",X"00",X"00",X"E9",X"E1",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"A9",X"21",X"C3",X"20",X"40",X"FE",X"00",X"00",X"A5",X"21",X"C3",X"20",X"40",X"FE",X"00",X"00",
+		X"26",X"26",X"08",X"07",X"12",X"26",X"0E",X"02",X"12",X"26",X"0E",X"02",X"04",X"11",X"1B",X"26",
+		X"26",X"04",X"26",X"1C",X"0B",X"0F",X"18",X"00",X"04",X"11",X"26",X"26",X"02",X"12",X"11",X"0E",
+		X"1C",X"26",X"0F",X"26",X"00",X"0B",X"04",X"18",X"14",X"0F",X"07",X"12",X"26",X"1B",X"11",X"0E",
+		X"02",X"0D",X"04",X"11",X"08",X"03",X"26",X"13",X"12",X"11",X"01",X"26",X"13",X"14",X"0E",X"13",
+		X"0B",X"0F",X"18",X"00",X"11",X"04",X"1C",X"26",X"0B",X"0F",X"18",X"00",X"11",X"04",X"1B",X"26",
+		X"0A",X"00",X"26",X"E5",X"6F",X"00",X"29",X"29",X"0F",X"26",X"08",X"0E",X"13",X"0D",X"11",X"12",
+		X"1A",X"C5",X"13",X"77",X"20",X"01",X"09",X"00",X"19",X"29",X"E1",X"EB",X"08",X"06",X"04",X"D3",
+		X"23",X"56",X"23",X"7E",X"6F",X"66",X"CD",X"7A",X"05",X"C1",X"B8",X"C2",X"C9",X"0B",X"23",X"5E",
+		X"E6",X"0F",X"CD",X"0F",X"0B",X"E6",X"E6",X"F1",X"0B",X"D3",X"D5",X"7B",X"0F",X"F5",X"0F",X"0F",
+		X"3C",X"C3",X"AF",X"09",X"81",X"7D",X"6F",X"27",X"CD",X"0F",X"0B",X"E6",X"C9",X"D1",X"1A",X"C6",
+		X"11",X"0E",X"04",X"13",X"26",X"17",X"76",X"F3",X"88",X"7C",X"C3",X"27",X"41",X"1B",X"15",X"26",
+		X"30",X"17",X"70",X"11",X"CD",X"0B",X"0A",X"B0",X"3F",X"FE",X"F8",X"C2",X"0E",X"17",X"21",X"04",
+		X"01",X"06",X"05",X"FB",X"1A",X"C2",X"CD",X"08",X"0F",X"0E",X"15",X"21",X"C3",X"2A",X"09",X"0D",
+		X"20",X"AD",X"0E",X"6F",X"CD",X"01",X"0B",X"EB",X"0A",X"28",X"18",X"C2",X"26",X"08",X"3A",X"00",
+		X"20",X"AD",X"99",X"FE",X"53",X"D2",X"CD",X"08",X"32",X"7D",X"20",X"AD",X"26",X"CD",X"3A",X"0B",
+		X"0B",X"74",X"13",X"21",X"CD",X"28",X"09",X"F1",X"0A",X"28",X"53",X"CA",X"0E",X"08",X"11",X"15",
+		X"62",X"DA",X"DB",X"08",X"E6",X"03",X"C2",X"02",X"18",X"C3",X"3A",X"08",X"20",X"AD",X"02",X"FE",
+		X"3E",X"09",X"C3",X"01",X"08",X"7B",X"16",X"CD",X"08",X"6E",X"03",X"DB",X"04",X"E6",X"08",X"CA",
+		X"3E",X"20",X"32",X"02",X"20",X"F1",X"16",X"CD",X"DB",X"09",X"E6",X"02",X"3C",X"03",X"E1",X"32",
+		X"32",X"3C",X"20",X"E0",X"C6",X"CD",X"00",X"03",X"CD",X"09",X"0B",X"26",X"02",X"DB",X"03",X"E6",
+		X"08",X"0E",X"17",X"21",X"11",X"2F",X"0B",X"90",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"7D",X"E5",X"DD",X"C6",X"24",X"6F",X"B8",X"7E",X"F1",X"CD",X"C3",X"09",X"08",X"BC",X"44",X"4D",
+		X"FE",X"81",X"C9",X"81",X"AF",X"CD",X"21",X"03",X"7E",X"23",X"C3",X"B9",X"04",X"B2",X"E6",X"F3",
+		X"08",X"06",X"21",X"EF",X"23",X"80",X"08",X"06",X"23",X"00",X"08",X"06",X"21",X"EF",X"23",X"40",
+		X"DF",X"09",X"C2",X"05",X"08",X"D9",X"F6",X"21",X"21",X"EF",X"23",X"C0",X"08",X"06",X"06",X"EF",
+		X"EF",X"22",X"CD",X"97",X"1C",X"00",X"9F",X"31",X"06",X"22",X"EF",X"05",X"08",X"06",X"ED",X"21",
+		X"B4",X"7D",X"B2",X"B3",X"C2",X"A7",X"01",X"5C",X"2A",X"20",X"20",X"A5",X"2A",X"EB",X"20",X"A9",
+		X"04",X"D3",X"37",X"C3",X"11",X"08",X"09",X"2D",X"4E",X"21",X"22",X"00",X"20",X"9F",X"C9",X"FB",
+		X"3D",X"20",X"E6",X"47",X"FE",X"0F",X"C2",X"0F",X"F1",X"CD",X"C3",X"09",X"08",X"18",X"AD",X"3A",
+		X"32",X"78",X"20",X"AD",X"1B",X"C9",X"0F",X"26",X"09",X"28",X"E6",X"78",X"F6",X"F0",X"47",X"09",
+		X"13",X"13",X"0D",X"0E",X"CD",X"00",X"0B",X"A7",X"00",X"0B",X"04",X"18",X"26",X"11",X"14",X"01",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"CD",X"C9",X"4A",X"C4",X"00",X"00",
+		X"DF",X"00",X"21",X"DF",X"28",X"10",X"F7",X"CD",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"D2",X"CD",X"DF",X"0B",X"10",X"21",X"0E",X"35",X"DF",X"0C",X"10",X"21",X"1E",X"33",X"00",X"20",
+		X"28",X"0C",X"F5",X"CD",X"DF",X"10",X"0C",X"21",X"11",X"07",X"0B",X"A0",X"BB",X"CD",X"21",X"09",
+		X"00",X"00",X"0C",X"21",X"0E",X"35",X"11",X"07",X"1E",X"33",X"00",X"50",X"D2",X"CD",X"DF",X"0B",
+		X"F5",X"CD",X"DF",X"07",X"08",X"21",X"11",X"31",X"0B",X"A0",X"BB",X"CD",X"21",X"09",X"28",X"08",
+		X"08",X"21",X"0E",X"35",X"11",X"07",X"0B",X"A0",X"C1",X"00",X"CE",X"CD",X"DF",X"0B",X"00",X"00",
+		X"FF",X"FF",X"1A",X"FF",X"00",X"D5",X"A7",X"CD",X"BB",X"CD",X"CD",X"09",X"40",X"4C",X"FF",X"C9",
+		X"09",X"BB",X"CD",X"C9",X"1C",X"F3",X"1C",X"0E",X"00",X"0B",X"DF",X"D1",X"00",X"13",X"C2",X"0D",
+		X"CD",X"09",X"0B",X"40",X"20",X"CD",X"CD",X"0B",X"1E",X"21",X"11",X"24",X"0B",X"50",X"F1",X"CD",
+		X"0B",X"89",X"F1",X"CD",X"C3",X"09",X"0D",X"DB",X"0B",X"48",X"07",X"0E",X"01",X"21",X"11",X"35",
+		X"00",X"D1",X"0D",X"13",X"F1",X"C2",X"C9",X"09",X"1A",X"C9",X"00",X"D5",X"A7",X"CD",X"00",X"0B",
+		X"0C",X"E2",X"0D",X"10",X"0D",X"25",X"0D",X"3A",X"0C",X"8E",X"0C",X"A3",X"0C",X"B8",X"0C",X"CD",
+		X"FF",X"7F",X"80",X"00",X"E3",X"7F",X"80",X"FF",X"00",X"00",X"3E",X"3E",X"00",X"FF",X"3E",X"00",
+		X"80",X"C1",X"01",X"01",X"C0",X"FF",X"80",X"20",X"E3",X"C0",X"00",X"C1",X"FF",X"01",X"C0",X"C0",
+		X"00",X"02",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"01",X"00",X"FF",X"02",X"00",X"20",X"00",X"00",
+		X"00",X"FF",X"38",X"00",X"FF",X"7C",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"01",X"C6",X"01",X"00",X"00",X"FF",X"EE",X"7C",X"00",X"FF",X"EE",X"00",X"FF",X"C6",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"01",X"00",X"01",X"00",X"FF",X"00",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"FF",X"F8",X"00",X"FF",X"F8",X"00",X"00",X"FF",X"FF",X"00",X"00",X"F8",X"FC",X"00",X"01",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20",X"F8",X"00",X"FF",X"20",X"00",X"FF",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"00",X"FF",X"FC",X"00",X"07",X"F0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"FF",X"F0",X"00",X"01",X"40",X"FF",X"00",X"FF",X"01",X"00",X"00",X"F0",X"F0",X"01",X"01",
+		X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"40",X"40",X"00",X"FF",X"40",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"0C",X"86",X"10",X"21",X"C3",X"2E",X"0F",X"F5",X"FF",X"FF",X"FF",X"FF",X"A6",X"11",X"CD",X"10",
+		X"0C",X"3A",X"0C",X"4F",X"0C",X"64",X"0C",X"79",X"06",X"EB",X"0C",X"10",X"0C",X"25",X"07",X"E0",
+		X"DC",X"00",X"0F",X"F4",X"FF",X"0F",X"00",X"00",X"00",X"00",X"EC",X"EC",X"0F",X"0F",X"00",X"FF",
+		X"12",X"F2",X"FF",X"03",X"00",X"00",X"E3",X"E0",X"FA",X"38",X"07",X"17",X"00",X"FF",X"F0",X"00",
+		X"FF",X"00",X"00",X"00",X"07",X"00",X"00",X"38",X"01",X"31",X"00",X"FF",X"00",X"00",X"3E",X"1F",
+		X"00",X"FF",X"EE",X"00",X"06",X"FA",X"FF",X"07",X"FF",X"FF",X"00",X"00",X"F6",X"F6",X"05",X"05",
+		X"78",X"00",X"09",X"F9",X"FF",X"01",X"80",X"00",X"00",X"00",X"FD",X"9C",X"03",X"0B",X"00",X"FF",
+		X"1F",X"0F",X"FF",X"00",X"80",X"00",X"03",X"00",X"F1",X"F0",X"00",X"18",X"00",X"FF",X"00",X"80",
+		X"02",X"02",X"00",X"FF",X"37",X"00",X"03",X"3D",X"00",X"1C",X"FF",X"FF",X"00",X"00",X"1B",X"1B",
+		X"00",X"FF",X"BC",X"80",X"04",X"FC",X"FF",X"00",X"FF",X"03",X"80",X"00",X"FE",X"CE",X"01",X"05",
+		X"80",X"C0",X"0F",X"07",X"FF",X"00",X"C0",X"00",X"C0",X"00",X"78",X"78",X"00",X"0C",X"00",X"FF",
+		X"05",X"0D",X"01",X"01",X"80",X"FF",X"9B",X"80",X"01",X"00",X"00",X"0E",X"FF",X"FF",X"80",X"80",
+		X"00",X"02",X"00",X"FF",X"5E",X"40",X"02",X"7E",X"01",X"86",X"FF",X"01",X"40",X"00",X"CF",X"E7",
+		X"00",X"FF",X"C0",X"E0",X"07",X"03",X"FF",X"00",X"FF",X"00",X"60",X"00",X"3C",X"3C",X"00",X"06",
+		X"80",X"80",X"3F",X"2F",X"80",X"FF",X"3F",X"80",X"E0",X"00",X"00",X"00",X"00",X"07",X"FF",X"FF",
+		X"0D",X"00",X"FF",X"07",X"00",X"00",X"02",X"07",X"FF",X"0D",X"80",X"80",X"0F",X"0F",X"80",X"FF",
+		X"86",X"CD",X"C9",X"0C",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"00",X"11",X"FF",X"11",X"10",
+		X"07",X"20",X"07",X"30",X"07",X"40",X"07",X"50",X"1E",X"7A",X"1E",X"8A",X"1E",X"9A",X"07",X"10",
+		X"FF",X"09",X"00",X"00",X"10",X"02",X"00",X"FF",X"80",X"80",X"4E",X"5C",X"00",X"FF",X"24",X"00",
+		X"FF",X"27",X"00",X"40",X"24",X"02",X"00",X"FF",X"0C",X"00",X"FF",X"0C",X"40",X"FF",X"1E",X"80",
+		X"FF",X"FF",X"80",X"C0",X"03",X"01",X"20",X"FF",X"02",X"00",X"FF",X"04",X"00",X"00",X"03",X"0C",
+		X"40",X"FF",X"00",X"00",X"FF",X"02",X"C8",X"FF",X"09",X"90",X"FF",X"04",X"60",X"20",X"04",X"06",
+		X"20",X"FF",X"00",X"00",X"FF",X"01",X"C0",X"C0",X"05",X"E8",X"FF",X"04",X"90",X"40",X"00",X"02",
+		X"12",X"FF",X"00",X"20",X"FF",X"01",X"20",X"10",X"FF",X"FF",X"FF",X"FF",X"3C",X"F2",X"01",X"00",
+		X"3A",X"FF",X"FF",X"5C",X"90",X"09",X"91",X"FF",X"60",X"FF",X"FF",X"18",X"FF",X"FF",X"FF",X"FF",
+		X"DF",X"1D",X"C9",X"DF",X"FF",X"FF",X"30",X"30",X"FF",X"89",X"46",X"62",X"FF",X"FF",X"AA",X"CD",
+		X"C3",X"F1",X"00",X"08",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"3E",X"F5",X"32",X"AA",X"22",X"48",
+		X"FF",X"FF",X"EB",X"CD",X"84",X"19",X"C3",X"67",X"FF",X"FF",X"F0",X"FF",X"FF",X"F0",X"60",X"60",
+		X"F0",X"F0",X"03",X"03",X"E0",X"FF",X"01",X"E0",X"0A",X"48",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"F0",X"FF",X"0F",X"F0",X"FF",X"01",X"C0",X"C0",X"FF",X"FF",X"FF",X"FF",
+		X"07",X"E0",X"FF",X"07",X"C0",X"C0",X"03",X"03",X"FF",X"0F",X"F0",X"F0",X"0F",X"0F",X"E0",X"FF",
+		X"1F",X"E0",X"FF",X"1F",X"C0",X"C0",X"0F",X"0F",X"FF",X"FF",X"E0",X"E0",X"1F",X"1F",X"E0",X"FF",
+		X"1E",X"41",X"86",X"CD",X"C3",X"0C",X"0D",X"FA",X"80",X"FF",X"07",X"80",X"FF",X"07",X"11",X"FF",
+		X"1D",X"21",X"1D",X"31",X"1D",X"41",X"1E",X"31",X"1C",X"B9",X"1C",X"C9",X"1C",X"D9",X"1D",X"11",
+		X"FF",X"0F",X"00",X"00",X"06",X"06",X"FF",X"FF",X"80",X"80",X"1F",X"1F",X"00",X"FF",X"0F",X"00",
+		X"FF",X"1E",X"00",X"00",X"0C",X"0C",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"1E",X"00",
+		X"FF",X"FF",X"00",X"00",X"18",X"18",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"C0",X"FF",X"07",X"00",X"00",X"01",X"FF",X"00",X"1F",X"C0",X"FF",X"07",X"C0",X"C0",X"07",X"07",
+		X"FF",X"00",X"D2",X"FF",X"08",X"53",X"C5",X"F5",X"00",X"00",X"01",X"01",X"00",X"FF",X"01",X"00",
+		X"86",X"41",X"47",X"23",X"A7",X"7D",X"9D",X"CA",X"26",X"E5",X"2E",X"0B",X"6E",X"DE",X"F3",X"3A",
+		X"80",X"C0",X"0F",X"1F",X"80",X"FF",X"0F",X"80",X"78",X"0D",X"79",X"C3",X"FF",X"0D",X"FF",X"FF",
+		X"02",X"00",X"FF",X"00",X"78",X"FF",X"C0",X"A7",X"FF",X"0F",X"00",X"80",X"02",X"0F",X"00",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"C1",X"E1",X"C3",X"F1",X"08",X"3F",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"AA",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"3B",X"1F",X"80",X"FF",X"3B",X"80",X"FF",X"31",X"00",X"FF",X"0E",X"00",X"FF",X"1F",X"80",X"00",
+		X"FF",X"00",X"CD",X"FF",X"0B",X"26",X"03",X"0E",X"40",X"80",X"40",X"31",X"40",X"FF",X"40",X"00",
+		X"C9",X"48",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"9C",X"21",X"11",X"30",X"22",X"51",X"2C",X"CD",
+		X"FF",X"FF",X"10",X"21",X"C3",X"2B",X"0E",X"F4",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/3.t34.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/3.t34.vhd
new file mode 100644
index 00000000..40698213
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/3.t34.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity rom3t34 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of rom3t34 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"10",X"10",X"10",X"42",X"10",X"74",X"10",X"A6",X"0F",X"10",X"0F",X"42",X"0F",X"74",X"0F",X"A6",
+		X"E3",X"F0",X"07",X"E3",X"FF",X"07",X"E0",X"E0",X"30",X"30",X"7F",X"7F",X"06",X"06",X"F0",X"FF",
+		X"70",X"2A",X"3E",X"12",X"86",X"00",X"CA",X"A7",X"C1",X"C1",X"03",X"03",X"FF",X"FF",X"E5",X"F5",
+		X"C2",X"C3",X"16",X"41",X"F1",X"E1",X"DC",X"C3",X"12",X"36",X"C3",X"23",X"12",X"2D",X"FE",X"7D",
+		X"00",X"FF",X"1F",X"00",X"00",X"E0",X"FF",X"03",X"FF",X"13",X"00",X"00",X"F0",X"1E",X"01",X"00",
+		X"19",X"00",X"00",X"60",X"FF",X"06",X"00",X"00",X"00",X"80",X"60",X"19",X"06",X"00",X"80",X"FF",
+		X"00",X"80",X"FF",X"01",X"FF",X"FF",X"FF",X"FF",X"C0",X"0F",X"03",X"00",X"00",X"FF",X"06",X"00",
+		X"00",X"FF",X"18",X"00",X"FF",X"3C",X"00",X"00",X"40",X"8E",X"FF",X"FF",X"00",X"00",X"18",X"18",
+		X"00",X"00",X"66",X"66",X"00",X"FF",X"66",X"00",X"7E",X"3C",X"00",X"FF",X"7E",X"00",X"FF",X"66",
+		X"3C",X"00",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"7E",X"00",X"00",X"3C",X"7E",X"00",X"FF",
+		X"3E",X"F0",X"00",X"01",X"00",X"FF",X"E0",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",
+		X"00",X"06",X"00",X"FF",X"60",X"80",X"06",X"19",X"03",X"1F",X"FF",X"00",X"80",X"00",X"19",X"60",
+		X"00",X"FF",X"80",X"00",X"01",X"06",X"FF",X"00",X"FF",X"00",X"00",X"00",X"0F",X"C0",X"00",X"03",
+		X"E0",X"60",X"0F",X"0B",X"E0",X"FF",X"0F",X"60",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"03",X"C0",X"FF",X"01",X"80",X"C0",X"00",X"01",X"FF",X"03",X"E0",X"60",X"03",X"03",X"E0",X"FF",
+		X"0B",X"21",X"C3",X"2E",X"13",X"10",X"00",X"00",X"80",X"FF",X"FF",X"00",X"CD",X"FF",X"0C",X"86",
+		X"0E",X"10",X"0E",X"49",X"0E",X"82",X"0E",X"BB",X"1E",X"41",X"0D",X"4F",X"0D",X"88",X"0D",X"C1",
+		X"2B",X"08",X"50",X"11",X"CD",X"07",X"0C",X"86",X"10",X"11",X"CD",X"0D",X"0C",X"86",X"21",X"C9",
+		X"C9",X"0C",X"EB",X"CD",X"3A",X"0B",X"20",X"E2",X"08",X"21",X"11",X"2E",X"07",X"60",X"86",X"CD",
+		X"97",X"23",X"C3",X"77",X"19",X"67",X"FE",X"78",X"D3",X"C9",X"05",X"01",X"05",X"05",X"C9",X"78",
+		X"CD",X"20",X"19",X"72",X"77",X"78",X"FE",X"3D",X"C3",X"40",X"11",X"61",X"FF",X"FF",X"FA",X"3A",
+		X"7B",X"23",X"FA",X"32",X"C3",X"20",X"1F",X"41",X"C2",X"0B",X"13",X"56",X"07",X"3E",X"13",X"12",
+		X"11",X"26",X"13",X"86",X"E2",X"3A",X"A7",X"20",X"97",X"23",X"C3",X"77",X"1F",X"3E",X"01",X"21",
+		X"3A",X"12",X"20",X"E0",X"DC",X"C3",X"CD",X"13",X"79",X"CA",X"3A",X"13",X"20",X"E1",X"26",X"C3",
+		X"10",X"10",X"10",X"10",X"26",X"10",X"26",X"26",X"09",X"F1",X"D1",X"C1",X"C9",X"E1",X"10",X"10",
+		X"2A",X"13",X"20",X"D3",X"CD",X"2B",X"1D",X"58",X"26",X"26",X"26",X"26",X"26",X"26",X"C7",X"11",
+		X"F1",X"CD",X"C3",X"09",X"03",X"EC",X"01",X"E6",X"01",X"21",X"0E",X"26",X"11",X"09",X"13",X"8D",
+		X"C1",X"CA",X"CD",X"13",X"1D",X"58",X"7D",X"C3",X"D3",X"2A",X"2B",X"20",X"C7",X"11",X"A7",X"13",
+		X"15",X"AA",X"FF",X"2B",X"B4",X"54",X"56",X"6B",X"CD",X"16",X"1D",X"AA",X"7D",X"C3",X"D8",X"16",
+		X"04",X"01",X"FF",X"FF",X"CA",X"A7",X"13",X"82",X"A8",X"FF",X"14",X"28",X"FF",X"09",X"80",X"10",
+		X"3E",X"13",X"C3",X"02",X"1F",X"71",X"E2",X"CA",X"A7",X"00",X"82",X"CA",X"4F",X"13",X"7F",X"C3",
+		X"A7",X"20",X"E2",X"CA",X"C3",X"18",X"04",X"33",X"FE",X"18",X"C2",X"02",X"18",X"57",X"F5",X"3A",
+		X"1C",X"65",X"1C",X"7A",X"1C",X"8F",X"1C",X"A4",X"1C",X"11",X"1C",X"26",X"1C",X"3B",X"1C",X"50",
+		X"FF",X"C1",X"A0",X"80",X"61",X"73",X"00",X"01",X"C0",X"C0",X"82",X"86",X"C0",X"FF",X"CD",X"40",
+		X"30",X"00",X"1E",X"1E",X"00",X"03",X"00",X"FF",X"00",X"FF",X"2F",X"20",X"01",X"33",X"FF",X"00",
+		X"00",X"80",X"00",X"03",X"FF",X"FF",X"FF",X"FF",X"E0",X"F0",X"03",X"01",X"FF",X"00",X"70",X"00",
+		X"7E",X"A0",X"FF",X"60",X"D0",X"C0",X"30",X"B9",X"FF",X"FF",X"60",X"60",X"61",X"73",X"E0",X"FF",
+		X"0F",X"8F",X"00",X"01",X"00",X"FF",X"F0",X"F8",X"80",X"FF",X"97",X"90",X"FF",X"19",X"18",X"00",
+		X"00",X"01",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"01",X"00",X"FF",X"00",X"38",X"00",X"00",X"C0",
+		X"70",X"FF",X"3F",X"50",X"FF",X"3C",X"68",X"E0",X"FF",X"FF",X"FF",X"FF",X"B0",X"B0",X"3E",X"3F",
+		X"8C",X"80",X"07",X"C7",X"00",X"FF",X"F8",X"7C",X"18",X"5C",X"C0",X"FF",X"4B",X"C8",X"FF",X"0C",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"1C",X"00",X"00",X"E0",X"FF",X"FF",
+		X"1F",X"1F",X"B8",X"FF",X"1F",X"E8",X"FF",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"D8",X"D8",
+		X"FF",X"06",X"C6",X"C0",X"03",X"63",X"00",X"FF",X"B4",X"70",X"0F",X"2E",X"E0",X"FF",X"25",X"64",
+		X"FF",X"FF",X"E0",X"07",X"FF",X"00",X"FF",X"FF",X"7C",X"3E",X"FF",X"00",X"0E",X"00",X"00",X"70",
+		X"C0",X"C0",X"1F",X"17",X"C0",X"FF",X"1E",X"C0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"07",X"80",X"FF",X"03",X"00",X"80",X"01",X"03",X"FF",X"07",X"C0",X"C0",X"06",X"07",X"C0",X"FF",
+		X"86",X"CD",X"C3",X"0C",X"11",X"F6",X"00",X"00",X"FF",X"FF",X"FF",X"00",X"11",X"FF",X"1C",X"11",
+		X"12",X"10",X"12",X"42",X"12",X"74",X"12",X"A6",X"11",X"10",X"11",X"42",X"11",X"74",X"11",X"A6",
+		X"FF",X"7E",X"1E",X"1E",X"3C",X"3C",X"FF",X"FF",X"F3",X"F3",X"67",X"67",X"3F",X"FF",X"7E",X"3F",
+		X"32",X"3D",X"22",X"43",X"C3",X"F1",X"03",X"66",X"3A",X"F5",X"22",X"43",X"CA",X"A7",X"11",X"2C",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"FF",X"1F",X"00",X"CC",X"33",X"00",X"FF",X"FF",X"80",X"F0",X"0F",X"01",X"F8",X"FF",
+		X"1E",X"00",X"30",X"FF",X"00",X"00",X"FF",X"0C",X"CC",X"FF",X"00",X"00",X"FF",X"33",X"00",X"78",
+		X"FE",X"00",X"DA",X"0C",X"13",X"60",X"46",X"C3",X"DA",X"FF",X"11",X"66",X"0C",X"06",X"BC",X"CD",
+		X"00",X"FF",X"06",X"00",X"FF",X"0F",X"80",X"00",X"FF",X"13",X"FF",X"FF",X"00",X"00",X"06",X"06",
+		X"80",X"80",X"19",X"19",X"80",X"FF",X"19",X"80",X"1F",X"0F",X"80",X"FF",X"1F",X"80",X"FF",X"19",
+		X"0F",X"00",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"1F",X"00",X"80",X"0F",X"1F",X"00",X"FF",
+		X"0F",X"7C",X"00",X"FF",X"F8",X"C0",X"FF",X"07",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"80",X"00",
+		X"98",X"60",X"01",X"06",X"FF",X"00",X"C0",X"00",X"60",X"00",X"06",X"98",X"00",X"01",X"00",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"03",X"F0",X"00",X"FF",X"60",X"80",X"FF",X"01",
+		X"00",X"00",X"7B",X"5F",X"00",X"FF",X"7F",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"1F",X"00",X"FF",X"0E",X"00",X"00",X"04",X"0E",X"FF",X"1F",X"00",X"00",X"1F",X"1B",X"00",X"FF",
+		X"11",X"2B",X"0C",X"79",X"F5",X"C3",X"00",X"12",X"FF",X"FF",X"FF",X"00",X"00",X"FF",X"0C",X"21",
+		X"E6",X"3D",X"32",X"1F",X"20",X"D1",X"01",X"3E",X"32",X"10",X"20",X"D0",X"D1",X"3A",X"3D",X"20",
+		X"E5",X"20",X"CD",X"D5",X"15",X"B4",X"00",X"CD",X"D8",X"32",X"11",X"20",X"20",X"B0",X"D3",X"2A",
+		X"00",X"00",X"96",X"CD",X"3A",X"15",X"20",X"DA",X"D1",X"15",X"3A",X"E1",X"20",X"D6",X"00",X"A7",
+		X"CA",X"A7",X"16",X"7D",X"03",X"3E",X"20",X"C3",X"C2",X"A7",X"16",X"87",X"ED",X"CD",X"00",X"40",
+		X"16",X"5F",X"1A",X"17",X"02",X"32",X"13",X"20",X"97",X"11",X"05",X"32",X"3A",X"20",X"20",X"D1",
+		X"03",X"32",X"7D",X"20",X"04",X"32",X"CD",X"20",X"32",X"1A",X"20",X"01",X"D3",X"2A",X"7C",X"20",
+		X"32",X"97",X"20",X"DF",X"00",X"3A",X"6F",X"22",X"17",X"88",X"20",X"26",X"DF",X"3A",X"F5",X"20",
+		X"17",X"88",X"5E",X"C3",X"3A",X"05",X"20",X"CF",X"8D",X"CD",X"F1",X"18",X"DF",X"32",X"CD",X"20",
+		X"40",X"ED",X"A7",X"00",X"7D",X"C2",X"21",X"16",X"C2",X"A7",X"1B",X"87",X"12",X"C3",X"CD",X"1B",
+		X"16",X"AA",X"D0",X"3A",X"C6",X"20",X"32",X"10",X"20",X"DA",X"C3",X"35",X"16",X"7D",X"D2",X"07",
+		X"16",X"09",X"DD",X"3A",X"47",X"20",X"D5",X"3A",X"20",X"D0",X"D1",X"3A",X"3C",X"20",X"C3",X"3C",
+		X"20",X"D5",X"ED",X"CD",X"00",X"40",X"C3",X"A7",X"90",X"20",X"96",X"D2",X"3E",X"1B",X"32",X"50",
+		X"3A",X"17",X"20",X"DD",X"50",X"FE",X"D5",X"D2",X"42",X"20",X"D8",X"3A",X"A7",X"20",X"6F",X"C2",
+		X"D3",X"2A",X"E5",X"20",X"B4",X"CD",X"00",X"15",X"3C",X"16",X"DD",X"32",X"11",X"20",X"20",X"B0",
+		X"20",X"D9",X"16",X"5F",X"1A",X"17",X"B7",X"4F",X"33",X"C3",X"00",X"18",X"00",X"00",X"3A",X"E1",
+		X"17",X"17",X"5F",X"17",X"C3",X"9F",X"03",X"F7",X"13",X"17",X"CE",X"1A",X"B7",X"00",X"17",X"17",
+		X"FF",X"FE",X"00",X"FE",X"00",X"FF",X"01",X"FF",X"FF",X"00",X"FD",X"FF",X"FE",X"FF",X"FE",X"FE",
+		X"00",X"02",X"FF",X"02",X"FF",X"01",X"FE",X"01",X"01",X"00",X"02",X"01",X"01",X"01",X"01",X"02",
+		X"DA",X"03",X"17",X"49",X"3C",X"2F",X"A7",X"4F",X"7B",X"57",X"E0",X"E6",X"3E",X"26",X"FE",X"79",
+		X"3C",X"20",X"07",X"E6",X"D7",X"32",X"3E",X"20",X"63",X"CA",X"CD",X"17",X"1B",X"9C",X"D7",X"3A",
+		X"A7",X"17",X"63",X"CA",X"CD",X"17",X"15",X"14",X"32",X"01",X"20",X"D2",X"79",X"0D",X"2F",X"C3",
+		X"3E",X"20",X"32",X"01",X"20",X"D2",X"79",X"0D",X"D7",X"3A",X"3C",X"20",X"07",X"E6",X"D7",X"32",
+		X"CD",X"20",X"15",X"96",X"7D",X"C3",X"3A",X"1B",X"49",X"C3",X"22",X"17",X"20",X"D3",X"B0",X"11",
+		X"D2",X"C3",X"3A",X"16",X"20",X"D7",X"C2",X"A7",X"20",X"DD",X"03",X"FE",X"7B",X"C3",X"3D",X"17",
+		X"00",X"3A",X"47",X"22",X"00",X"3A",X"32",X"20",X"16",X"D5",X"D1",X"3A",X"C3",X"20",X"1B",X"73",
+		X"EB",X"20",X"DB",X"2A",X"22",X"20",X"20",X"EB",X"22",X"00",X"32",X"78",X"20",X"00",X"EB",X"2A",
+		X"AE",X"3A",X"32",X"20",X"20",X"EE",X"32",X"78",X"22",X"EB",X"20",X"DB",X"EE",X"3A",X"47",X"20",
+		X"7C",X"19",X"25",X"FE",X"24",X"DA",X"FE",X"17",X"20",X"AE",X"79",X"C9",X"C2",X"A7",X"17",X"B9",
+		X"C3",X"27",X"17",X"26",X"21",X"E5",X"20",X"B1",X"DA",X"3E",X"17",X"26",X"26",X"CA",X"26",X"17",
+		X"13",X"13",X"23",X"23",X"FE",X"7D",X"C2",X"C1",X"B0",X"11",X"1A",X"20",X"7E",X"47",X"70",X"12",
+		X"17",X"F0",X"E1",X"F1",X"C1",X"D1",X"C9",X"FB",X"17",X"D3",X"C9",X"E1",X"F0",X"C3",X"C2",X"1A",
+		X"00",X"00",X"00",X"00",X"05",X"C3",X"00",X"08",X"01",X"3E",X"F5",X"32",X"CD",X"20",X"03",X"C6",
+		X"C0",X"07",X"00",X"01",X"40",X"04",X"00",X"01",X"80",X"03",X"80",X"03",X"C0",X"07",X"80",X"03",
+		X"C0",X"00",X"C0",X"00",X"40",X"00",X"40",X"00",X"C0",X"07",X"C0",X"03",X"C0",X"0F",X"C0",X"01",
+		X"80",X"01",X"60",X"00",X"00",X"01",X"00",X"00",X"C0",X"0F",X"C0",X"07",X"80",X"01",X"E0",X"01",
+		X"00",X"03",X"00",X"00",X"00",X"02",X"00",X"00",X"C0",X"03",X"E0",X"07",X"80",X"03",X"F0",X"0F",
+		X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"F8",X"03",X"E0",X"03",X"E0",X"03",X"00",X"07",
+		X"F8",X"07",X"00",X"01",X"00",X"00",X"00",X"00",X"E0",X"01",X"C0",X"01",X"F0",X"03",X"80",X"01",
+		X"F0",X"00",X"80",X"00",X"30",X"00",X"00",X"00",X"E0",X"07",X"C0",X"00",X"E0",X"03",X"C0",X"00",
+		X"60",X"00",X"60",X"00",X"20",X"00",X"20",X"00",X"E0",X"01",X"E0",X"03",X"E0",X"00",X"E0",X"07",
+		X"80",X"00",X"E0",X"03",X"80",X"00",X"20",X"02",X"C0",X"01",X"C0",X"01",X"C0",X"01",X"E0",X"03",
+		X"00",X"03",X"00",X"03",X"00",X"02",X"00",X"02",X"C0",X"03",X"E0",X"03",X"80",X"03",X"F0",X"03",
+		X"00",X"06",X"80",X"01",X"00",X"00",X"80",X"00",X"E0",X"03",X"F0",X"03",X"80",X"07",X"80",X"01",
+		X"00",X"00",X"C0",X"00",X"00",X"00",X"40",X"00",X"E0",X"07",X"C0",X"03",X"F0",X"0F",X"C0",X"01",
+		X"00",X"00",X"E0",X"00",X"00",X"00",X"00",X"00",X"C0",X"07",X"C0",X"1F",X"E0",X"00",X"C0",X"07",
+		X"20",X"00",X"F8",X"07",X"00",X"00",X"00",X"00",X"E0",X"00",X"E0",X"01",X"60",X"00",X"F0",X"03",
+		X"40",X"00",X"C0",X"03",X"00",X"00",X"00",X"03",X"C0",X"00",X"F8",X"01",X"C0",X"00",X"F0",X"01",
+		X"00",X"03",X"00",X"03",X"00",X"02",X"00",X"02",X"E0",X"03",X"C0",X"03",X"F0",X"03",X"80",X"03",
+		X"1A",X"20",X"7D",X"77",X"BF",X"FE",X"13",X"C8",X"D0",X"3A",X"5F",X"20",X"14",X"16",X"B0",X"21",
+		X"20",X"B1",X"1A",X"B7",X"12",X"17",X"1B",X"4F",X"C3",X"23",X"15",X"09",X"06",X"C5",X"11",X"00",
+		X"CA",X"BE",X"15",X"32",X"13",X"13",X"C3",X"13",X"17",X"1A",X"79",X"12",X"47",X"B0",X"FE",X"7B",
+		X"17",X"CC",X"00",X"00",X"B6",X"1A",X"13",X"77",X"15",X"1A",X"C1",X"78",X"C0",X"A7",X"C3",X"23",
+		X"69",X"60",X"77",X"B6",X"2B",X"13",X"B6",X"1A",X"1A",X"2B",X"77",X"B6",X"23",X"13",X"E5",X"1A",
+		X"A6",X"2F",X"E6",X"77",X"CA",X"07",X"15",X"65",X"23",X"77",X"44",X"13",X"E1",X"4D",X"1A",X"C9",
+		X"A6",X"2F",X"E6",X"77",X"CA",X"E0",X"15",X"75",X"01",X"3E",X"D6",X"32",X"13",X"20",X"1A",X"2B",
+		X"E5",X"2F",X"69",X"60",X"77",X"A6",X"07",X"E6",X"01",X"3E",X"D6",X"32",X"13",X"20",X"1A",X"23",
+		X"2B",X"13",X"2F",X"1A",X"77",X"A6",X"E0",X"E6",X"88",X"CA",X"3E",X"15",X"32",X"01",X"20",X"D6",
+		X"4F",X"20",X"DE",X"7C",X"47",X"00",X"3C",X"CD",X"19",X"CA",X"C3",X"02",X"02",X"14",X"D6",X"7D",
+		X"1D",X"82",X"3C",X"CD",X"CD",X"15",X"1D",X"82",X"CD",X"15",X"1D",X"82",X"3C",X"CD",X"CD",X"15",
+		X"DE",X"7C",X"47",X"00",X"57",X"CD",X"CD",X"15",X"3C",X"CD",X"C9",X"15",X"D6",X"7D",X"4F",X"20",
+		X"57",X"CD",X"CD",X"15",X"1D",X"82",X"57",X"CD",X"1D",X"82",X"57",X"CD",X"CD",X"15",X"1D",X"82",
+		X"E5",X"01",X"31",X"C3",X"00",X"02",X"D2",X"3A",X"C9",X"15",X"F5",X"3A",X"A7",X"20",X"FE",X"C8",
+		X"3A",X"16",X"20",X"D7",X"C2",X"A7",X"16",X"AA",X"3D",X"20",X"D2",X"32",X"A7",X"20",X"AA",X"C2",
+		X"D2",X"00",X"16",X"96",X"D0",X"3A",X"D6",X"20",X"10",X"3E",X"D2",X"32",X"C3",X"20",X"40",X"DA");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/4.t33.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/4.t33.vhd
new file mode 100644
index 00000000..f19c46b3
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/4.t33.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity rom4t33 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of rom4t33 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"41",X"9F",X"41",X"BE",X"41",X"DD",X"41",X"FC",X"1A",X"A5",X"1A",X"B8",X"1A",X"D3",X"41",X"80",
+		X"3A",X"1A",X"20",X"DB",X"A7",X"CD",X"D2",X"06",X"DC",X"3A",X"CD",X"20",X"06",X"9D",X"29",X"D2",
+		X"3A",X"19",X"20",X"FB",X"E6",X"C3",X"00",X"1D",X"1A",X"29",X"1F",X"E6",X"03",X"FE",X"F0",X"DA",
+		X"01",X"07",X"F0",X"FF",X"01",X"F0",X"FF",X"01",X"F0",X"00",X"05",X"B0",X"FF",X"07",X"F0",X"F0",
+		X"00",X"40",X"FF",X"FF",X"FF",X"FF",X"F8",X"D8",X"E0",X"B0",X"00",X"01",X"E0",X"FF",X"FF",X"40",
+		X"F8",X"F8",X"F8",X"FF",X"FF",X"50",X"20",X"70",X"03",X"02",X"F8",X"FF",X"03",X"F8",X"FF",X"00",
+		X"FF",X"00",X"7C",X"FF",X"01",X"FC",X"FF",X"01",X"20",X"FF",X"FF",X"00",X"7F",X"FF",X"00",X"00",
+		X"38",X"6C",X"38",X"FF",X"FF",X"10",X"00",X"10",X"7C",X"FC",X"00",X"01",X"7C",X"FF",X"FF",X"7C",
+		X"FE",X"BE",X"FE",X"FF",X"FF",X"36",X"3E",X"36",X"FF",X"FF",X"00",X"3F",X"00",X"00",X"FF",X"FF",
+		X"FF",X"00",X"00",X"FF",X"F8",X"FE",X"1F",X"00",X"3E",X"FF",X"FF",X"1C",X"08",X"1C",X"08",X"FF",
+		X"BD",X"EF",X"BF",X"FF",X"FF",X"EA",X"6C",X"AE",X"00",X"00",X"FF",X"00",X"EF",X"FF",X"FF",X"EF",
+		X"D2",X"DE",X"01",X"01",X"DE",X"FF",X"01",X"7E",X"6C",X"FF",X"FF",X"28",X"00",X"28",X"FF",X"FF",
+		X"01",X"D8",X"FF",X"00",X"50",X"D8",X"50",X"FF",X"FF",X"01",X"DC",X"7E",X"01",X"01",X"DC",X"FF",
+		X"FC",X"A4",X"02",X"02",X"FC",X"FF",X"02",X"B8",X"FF",X"00",X"BC",X"FF",X"03",X"BC",X"FF",X"03",
+		X"01",X"A0",X"FF",X"00",X"00",X"A0",X"FF",X"FF",X"FF",X"03",X"B0",X"B8",X"01",X"03",X"B0",X"FF",
+		X"28",X"CD",X"C3",X"0A",X"17",X"E7",X"FF",X"FF",X"A3",X"3A",X"FE",X"20",X"D2",X"01",X"1E",X"5F",
+		X"32",X"F1",X"20",X"DF",X"88",X"CD",X"C3",X"17",X"FF",X"FF",X"FF",X"FF",X"CD",X"FF",X"18",X"8D",
+		X"FE",X"1B",X"CA",X"80",X"1B",X"C0",X"8E",X"C3",X"16",X"E6",X"D1",X"3A",X"A7",X"20",X"C0",X"CA",
+		X"A7",X"E1",X"10",X"CA",X"FE",X"19",X"CA",X"01",X"E5",X"1B",X"7E",X"24",X"B6",X"23",X"B6",X"23",
+		X"67",X"00",X"49",X"C3",X"EB",X"18",X"C3",X"2B",X"19",X"10",X"D6",X"7D",X"6F",X"20",X"DE",X"7C",
+		X"18",X"49",X"15",X"FE",X"5C",X"D2",X"FE",X"1B",X"1B",X"DD",X"E6",X"7D",X"FE",X"1F",X"D2",X"19",
+		X"C3",X"1B",X"18",X"49",X"25",X"E5",X"23",X"7E",X"D2",X"10",X"18",X"49",X"09",X"FE",X"21",X"DA",
+		X"D6",X"7D",X"6F",X"20",X"DE",X"7C",X"67",X"00",X"23",X"B6",X"E1",X"B6",X"C2",X"A7",X"18",X"81",
+		X"20",X"D8",X"2D",X"C3",X"3A",X"16",X"20",X"D7",X"49",X"C3",X"32",X"18",X"20",X"D9",X"32",X"97",
+		X"CF",X"32",X"C3",X"20",X"05",X"5E",X"0F",X"3E",X"CA",X"A7",X"16",X"2D",X"7D",X"C3",X"3D",X"16",
+		X"C3",X"20",X"1B",X"7D",X"06",X"C5",X"11",X"00",X"CF",X"32",X"C3",X"20",X"16",X"5F",X"D5",X"32",
+		X"1F",X"1A",X"79",X"12",X"47",X"B0",X"FE",X"7B",X"20",X"B0",X"1A",X"B7",X"12",X"1F",X"13",X"4F",
+		X"C1",X"78",X"C0",X"A7",X"C3",X"2B",X"17",X"CC",X"CA",X"BF",X"1B",X"B8",X"C3",X"13",X"1B",X"A2",
+		X"EB",X"77",X"23",X"23",X"23",X"23",X"3C",X"7E",X"08",X"3E",X"90",X"C3",X"00",X"1B",X"03",X"3E",
+		X"77",X"23",X"D6",X"7D",X"6F",X"0A",X"00",X"00",X"70",X"23",X"71",X"23",X"72",X"23",X"73",X"23",
+		X"32",X"05",X"22",X"00",X"81",X"C9",X"0F",X"E6",X"C2",X"A7",X"19",X"26",X"00",X"3A",X"C6",X"22",
+		X"32",X"0F",X"20",X"ED",X"21",X"C3",X"00",X"1B",X"12",X"4F",X"ED",X"3A",X"3C",X"20",X"E6",X"3C",
+		X"12",X"D8",X"10",X"D8",X"0F",X"D8",X"11",X"D8",X"1A",X"88",X"1A",X"6B",X"1A",X"4E",X"1A",X"31",
+		X"42",X"C2",X"3A",X"1B",X"20",X"F4",X"00",X"85",X"E6",X"81",X"4F",X"0F",X"1B",X"D1",X"A7",X"12",
+		X"3D",X"20",X"ED",X"C3",X"D1",X"1B",X"24",X"24",X"3A",X"6F",X"20",X"F3",X"67",X"8C",X"F4",X"3A",
+		X"DF",X"3A",X"F5",X"20",X"32",X"97",X"20",X"DF",X"D2",X"C3",X"CD",X"1F",X"17",X"88",X"20",X"26",
+		X"1B",X"00",X"12",X"7C",X"7D",X"1B",X"3A",X"12",X"00",X"3A",X"6F",X"22",X"05",X"C3",X"00",X"1B",
+		X"1D",X"A5",X"EE",X"3A",X"A7",X"20",X"C5",X"C2",X"20",X"DF",X"01",X"FE",X"EE",X"C3",X"CD",X"13",
+		X"22",X"05",X"ED",X"3A",X"5F",X"20",X"19",X"16",X"3E",X"06",X"32",X"0C",X"20",X"EE",X"32",X"97",
+		X"FE",X"22",X"D2",X"02",X"19",X"1B",X"54",X"C3",X"32",X"1A",X"22",X"02",X"1A",X"13",X"01",X"32",
+		X"00",X"18",X"26",X"6F",X"7E",X"22",X"FE",X"2B",X"FE",X"19",X"CA",X"01",X"1B",X"68",X"49",X"C3",
+		X"F9",X"CA",X"57",X"1F",X"77",X"97",X"4E",X"2B",X"CA",X"0C",X"1F",X"7A",X"2B",X"5E",X"A7",X"7E",
+		X"A7",X"00",X"F8",X"C2",X"09",X"18",X"FE",X"7C",X"46",X"2B",X"95",X"C3",X"3A",X"06",X"20",X"DF",
+		X"26",X"18",X"7E",X"27",X"C2",X"A7",X"02",X"06",X"DA",X"25",X"18",X"C3",X"3E",X"FE",X"BB",X"DA",
+		X"01",X"3E",X"DF",X"32",X"3A",X"20",X"20",X"EF",X"98",X"C3",X"26",X"04",X"C3",X"3E",X"18",X"BB",
+		X"01",X"3E",X"F4",X"32",X"3E",X"20",X"32",X"02",X"32",X"3C",X"20",X"EF",X"32",X"97",X"20",X"F3",
+		X"18",X"ED",X"8A",X"CD",X"97",X"18",X"F6",X"32",X"20",X"F0",X"00",X"3A",X"FE",X"22",X"CA",X"05",
+		X"2B",X"EB",X"C3",X"7D",X"1B",X"E0",X"00",X"00",X"32",X"20",X"20",X"DF",X"C2",X"C3",X"C9",X"04",
+		X"00",X"01",X"FF",X"01",X"FF",X"00",X"FE",X"FF",X"FF",X"FF",X"FF",X"00",X"01",X"00",X"01",X"01",
+		X"49",X"C3",X"79",X"18",X"04",X"32",X"78",X"22",X"C6",X"7D",X"6F",X"20",X"CE",X"7C",X"67",X"00",
+		X"18",X"94",X"EB",X"22",X"C3",X"20",X"1B",X"C6",X"03",X"32",X"C3",X"22",X"19",X"5C",X"C3",X"2B",
+		X"06",X"9D",X"10",X"D2",X"3A",X"1A",X"20",X"EB",X"32",X"97",X"20",X"DF",X"EC",X"3A",X"CD",X"20",
+		X"03",X"FE",X"F0",X"DA",X"00",X"19",X"10",X"C3",X"A7",X"CD",X"D2",X"06",X"1A",X"10",X"1F",X"E6",
+		X"32",X"7C",X"22",X"03",X"00",X"3A",X"CD",X"22",X"C3",X"1A",X"1D",X"E6",X"32",X"7D",X"22",X"04",
+		X"23",X"23",X"F9",X"3A",X"BD",X"20",X"41",X"C3",X"18",X"8A",X"CA",X"C9",X"19",X"D0",X"23",X"23",
+		X"7E",X"23",X"13",X"12",X"7E",X"23",X"13",X"12",X"00",X"02",X"16",X"5F",X"7E",X"21",X"13",X"12",
+		X"19",X"9D",X"F9",X"3A",X"CD",X"20",X"19",X"72",X"C9",X"23",X"BC",X"CD",X"FE",X"00",X"DA",X"0D",
+		X"20",X"F9",X"D9",X"C3",X"23",X"1E",X"77",X"97",X"77",X"78",X"12",X"3D",X"23",X"13",X"32",X"7B",
+		X"CA",X"DA",X"3A",X"19",X"20",X"F8",X"72",X"CD",X"D6",X"C3",X"CD",X"1E",X"00",X"BC",X"07",X"FE",
+		X"43",X"60",X"FF",X"FF",X"FF",X"FF",X"3C",X"77",X"78",X"19",X"0B",X"FE",X"BE",X"C2",X"C3",X"19",
+		X"1F",X"17",X"97",X"23",X"C3",X"77",X"1F",X"14",X"13",X"12",X"7B",X"23",X"F8",X"32",X"C3",X"20",
+		X"F7",X"3A",X"CD",X"20",X"19",X"72",X"77",X"78",X"BC",X"CD",X"FE",X"00",X"DA",X"0C",X"13",X"38",
+		X"6A",X"C3",X"3E",X"19",X"C3",X"30",X"04",X"8F",X"12",X"3C",X"23",X"13",X"32",X"7B",X"20",X"F7",
+		X"DB",X"32",X"32",X"20",X"20",X"DC",X"00",X"C9",X"57",X"97",X"EB",X"32",X"32",X"20",X"20",X"EC",
+		X"20",X"FE",X"67",X"8C",X"25",X"FE",X"25",X"DA",X"1C",X"0A",X"FF",X"3A",X"85",X"20",X"3A",X"6F",
+		X"26",X"1E",X"1B",X"25",X"12",X"7C",X"7D",X"1B",X"FE",X"1E",X"DA",X"3E",X"1E",X"1B",X"1B",X"CA",
+		X"1E",X"1B",X"5F",X"1A",X"B3",X"0A",X"BC",X"C3",X"CD",X"12",X"1D",X"A5",X"26",X"C9",X"C3",X"3E",
+		X"0F",X"07",X"00",X"FF",X"00",X"00",X"FF",X"07",X"80",X"1D",X"09",X"80",X"FF",X"0B",X"80",X"00",
+		X"01",X"07",X"C0",X"FF",X"01",X"C0",X"FF",X"01",X"FE",X"FF",X"3F",X"F0",X"FF",X"07",X"C0",X"F0",
+		X"80",X"80",X"80",X"FF",X"FF",X"00",X"21",X"FF",X"80",X"C0",X"00",X"01",X"80",X"FF",X"FF",X"80",
+		X"C2",X"19",X"18",X"49",X"23",X"23",X"FE",X"7E",X"40",X"7F",X"11",X"3E",X"6F",X"85",X"FE",X"7E",
+		X"FF",X"FF",X"00",X"00",X"02",X"05",X"80",X"FF",X"C2",X"08",X"06",X"A7",X"F8",X"C3",X"FF",X"1A",
+		X"FF",X"FF",X"C0",X"00",X"07",X"01",X"00",X"FF",X"08",X"00",X"FF",X"05",X"80",X"00",X"08",X"00",
+		X"FF",X"FF",X"80",X"40",X"00",X"01",X"20",X"FF",X"01",X"00",X"FF",X"01",X"00",X"00",X"01",X"00",
+		X"FF",X"FF",X"EB",X"97",X"00",X"E9",X"02",X"3E",X"02",X"40",X"FF",X"01",X"20",X"00",X"02",X"00",
+		X"21",X"20",X"E0",X"FF",X"FE",X"22",X"CD",X"20",X"FB",X"32",X"21",X"20",X"01",X"00",X"FC",X"22",
+		X"00",X"1E",X"E5",X"2B",X"75",X"CD",X"E1",X"02",X"02",X"7F",X"23",X"00",X"A7",X"7E",X"D6",X"CA",
+		X"3A",X"23",X"20",X"F7",X"C2",X"BD",X"1E",X"C2",X"A7",X"7A",X"82",X"CA",X"23",X"19",X"23",X"23",
+		X"20",X"FE",X"87",X"CD",X"23",X"02",X"A7",X"7E",X"CD",X"00",X"1F",X"92",X"00",X"21",X"22",X"20",
+		X"7A",X"E1",X"C3",X"A7",X"1F",X"10",X"00",X"00",X"14",X"CA",X"2B",X"1F",X"CD",X"E5",X"02",X"6B",
+		X"FF",X"01",X"00",X"00",X"00",X"01",X"FF",X"FF",X"80",X"80",X"03",X"07",X"80",X"FF",X"03",X"00",
+		X"20",X"FA",X"C3",X"BD",X"02",X"48",X"02",X"3E",X"A3",X"CA",X"23",X"19",X"23",X"23",X"3A",X"23",
+		X"CD",X"20",X"05",X"A2",X"7E",X"23",X"CA",X"A7",X"FB",X"32",X"21",X"20",X"FF",X"FF",X"FC",X"22",
+		X"A7",X"7A",X"3E",X"CA",X"23",X"13",X"23",X"23",X"1F",X"3E",X"E5",X"2B",X"61",X"CD",X"E1",X"02",
+		X"92",X"CD",X"21",X"1F",X"E0",X"FF",X"FE",X"22",X"3A",X"23",X"20",X"F8",X"C2",X"BD",X"1F",X"2C",
+		X"19",X"67",X"E5",X"2B",X"57",X"CD",X"E1",X"02",X"CD",X"20",X"05",X"AA",X"7E",X"23",X"CA",X"A7",
+		X"1F",X"74",X"03",X"FE",X"E9",X"CA",X"3E",X"13",X"A7",X"7A",X"63",X"C3",X"00",X"19",X"CA",X"A7",
+		X"1D",X"70",X"2B",X"5E",X"97",X"56",X"CA",X"BA",X"32",X"01",X"20",X"DF",X"13",X"03",X"C3",X"23",
+		X"03",X"AA",X"2B",X"1C",X"2B",X"2B",X"C3",X"7D",X"1F",X"8B",X"77",X"12",X"8B",X"C3",X"1E",X"1F",
+		X"3A",X"04",X"20",X"F6",X"06",X"C3",X"3A",X"04",X"1F",X"EA",X"F5",X"3A",X"A7",X"20",X"10",X"C2",
+		X"CA",X"02",X"1F",X"B8",X"C8",X"21",X"C3",X"20",X"20",X"EF",X"01",X"FE",X"B2",X"CA",X"FE",X"1F",
+		X"C4",X"21",X"5E",X"20",X"56",X"23",X"4E",X"23",X"1F",X"BB",X"C0",X"21",X"C3",X"20",X"1F",X"BB",
+		X"E1",X"1D",X"C1",X"D1",X"E6",X"7D",X"CA",X"1F",X"46",X"23",X"C5",X"EB",X"E5",X"D5",X"53",X"CD",
+		X"5F",X"8B",X"F3",X"3A",X"8A",X"20",X"1A",X"57",X"04",X"2A",X"54",X"D5",X"3A",X"5D",X"20",X"F4",
+		X"18",X"10",X"00",X"32",X"C3",X"22",X"1B",X"DE",X"C2",X"A7",X"18",X"2D",X"F0",X"3A",X"C3",X"20",
+		X"2B",X"1D",X"2B",X"2B",X"C3",X"7D",X"1B",X"DE",X"FE",X"79",X"DA",X"20",X"1D",X"A1",X"97",X"C3",
+		X"C9",X"09",X"00",X"D3",X"02",X"D3",X"A6",X"C3",X"00",X"CD",X"CD",X"40",X"05",X"B2",X"CB",X"CD",
+		X"FF",X"0F",X"0F",X"F0",X"FF",X"FF",X"FF",X"FF",X"F0",X"08",X"FF",X"0F",X"0F",X"F0",X"F0",X"FF",
+		X"60",X"FF",X"FF",X"18",X"18",X"60",X"60",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"18",X"60",
+		X"FF",X"FF",X"30",X"FF",X"FF",X"C0",X"C0",X"30",X"FF",X"18",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"30",X"FF",X"FF",X"C0",X"C0",X"30",X"FF",X"FF",
+		X"FF",X"07",X"80",X"78",X"07",X"00",X"78",X"FF",X"80",X"78",X"07",X"00",X"78",X"FF",X"00",X"80",
+		X"FF",X"0F",X"00",X"F0",X"0F",X"00",X"F0",X"FF",X"00",X"80",X"FF",X"07",X"F0",X"FF",X"00",X"00",
+		X"FF",X"FF",X"00",X"E0",X"1E",X"01",X"E0",X"FF",X"00",X"00",X"FF",X"0F",X"00",X"F0",X"0F",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"01",X"00",X"FF",X"1E",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"3C",X"C0",X"FF",X"03",X"C0",X"00",X"03",X"3C",
+		X"00",X"FF",X"78",X"80",X"FF",X"07",X"80",X"00",X"FF",X"FF",X"FF",X"FF",X"80",X"00",X"07",X"78",
+		X"11",X"FF",X"FF",X"1F",X"1F",X"0E",X"00",X"FF",X"07",X"78",X"00",X"FF",X"78",X"80",X"FF",X"07",
+		X"32",X"FF",X"FF",X"3A",X"3E",X"1C",X"00",X"FF",X"FF",X"0E",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"74",X"FF",X"FF",X"74",X"74",X"38",X"00",X"FF",X"FF",X"1C",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"02",X"FF",X"D1",X"B6",X"66",X"C3",X"00",X"1F",X"FF",X"38",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"7C",X"23",X"40",X"FE",X"F6",X"C2",X"C9",X"1C",X"00",X"00",X"21",X"00",X"24",X"00",X"00",X"36",
+		X"FF",X"00",X"00",X"80",X"FF",X"FF",X"FF",X"FF",X"C0",X"C0",X"01",X"03",X"C0",X"FF",X"01",X"80",
+		X"FF",X"70",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F8",X"00",X"FF",X"E8",X"C8",X"70",X"00",X"FF",
+		X"01",X"00",X"00",X"FF",X"FF",X"E0",X"FF",X"FF",X"F0",X"FF",X"01",X"F0",X"FF",X"01",X"10",X"E0",
+		X"02",X"01",X"00",X"FF",X"00",X"C0",X"FF",X"01",X"E0",X"FF",X"03",X"E0",X"FF",X"02",X"60",X"C0",
+		X"05",X"03",X"00",X"FF",X"00",X"80",X"FF",X"03",X"C0",X"FF",X"05",X"C0",X"FF",X"05",X"C0",X"80",
+		X"D6",X"7D",X"4F",X"20",X"DE",X"7C",X"47",X"00",X"00",X"FF",X"0A",X"00",X"03",X"5F",X"57",X"0A",
+		X"2F",X"1A",X"0A",X"5F",X"C3",X"A3",X"1C",X"E9",X"C5",X"E5",X"2F",X"1A",X"77",X"A6",X"D5",X"13",
+		X"81",X"CD",X"FE",X"1D",X"C2",X"FF",X"1D",X"60",X"FE",X"1A",X"C2",X"FF",X"1D",X"63",X"E1",X"C1",
+		X"67",X"00",X"D6",X"79",X"4F",X"20",X"DE",X"78",X"13",X"C9",X"C6",X"7D",X"6F",X"20",X"CE",X"7C",
+		X"40",X"FE",X"9F",X"DA",X"26",X"1D",X"1A",X"25",X"47",X"00",X"25",X"FE",X"F0",X"DA",X"7C",X"1F",
+		X"57",X"0A",X"D6",X"7D",X"4F",X"20",X"DE",X"7C",X"06",X"C9",X"1A",X"3E",X"0A",X"C9",X"03",X"5F",
+		X"C3",X"D5",X"1E",X"2A",X"D1",X"02",X"13",X"03",X"47",X"00",X"C5",X"E5",X"B6",X"1A",X"13",X"77",
+		X"CD",X"E1",X"1D",X"81",X"FF",X"FE",X"B2",X"C2",X"1A",X"23",X"FF",X"FE",X"B5",X"C2",X"C1",X"1D",
+		X"EB",X"46",X"D5",X"C5",X"CD",X"E5",X"1D",X"53",X"C9",X"1D",X"23",X"5E",X"23",X"56",X"23",X"4E",
+		X"1B",X"0F",X"4F",X"12",X"02",X"C2",X"3A",X"1E",X"D1",X"E1",X"C3",X"C1",X"19",X"30",X"E6",X"81",
+		X"C3",X"67",X"1E",X"02",X"3A",X"C6",X"C3",X"6F",X"20",X"FD",X"6F",X"85",X"FC",X"3A",X"8C",X"20");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/5.t32.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/5.t32.vhd
new file mode 100644
index 00000000..db8a803b
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/5.t32.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity rom5t32 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of rom5t32 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"77",X"5E",X"00",X"FF",X"75",X"00",X"FF",X"36",X"80",X"FF",X"77",X"80",X"FF",X"5F",X"00",X"80",
+		X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"14",X"36",X"00",X"FF",X"14",X"00",
+		X"16",X"C2",X"32",X"3D",X"22",X"42",X"6F",X"C3",X"31",X"CA",X"3A",X"42",X"22",X"42",X"CA",X"A7",
+		X"DD",X"32",X"C3",X"20",X"17",X"6F",X"FF",X"FF",X"3E",X"17",X"32",X"05",X"22",X"42",X"06",X"3E",
+		X"26",X"1D",X"CA",X"A7",X"42",X"55",X"43",X"3A",X"43",X"3A",X"A7",X"22",X"F2",X"CA",X"3A",X"45",
+		X"33",X"FE",X"65",X"DA",X"3E",X"42",X"32",X"01",X"3D",X"22",X"43",X"32",X"3A",X"22",X"20",X"D4",
+		X"00",X"22",X"00",X"00",X"D3",X"2A",X"3E",X"20",X"22",X"49",X"7B",X"C3",X"AF",X"42",X"49",X"32",
+		X"86",X"C3",X"2A",X"42",X"20",X"D3",X"26",X"7C",X"94",X"3D",X"D6",X"85",X"6F",X"01",X"3D",X"26",
+		X"3E",X"22",X"32",X"00",X"22",X"46",X"3A",X"C9",X"94",X"25",X"D6",X"85",X"6F",X"02",X"44",X"22",
+		X"A7",X"42",X"B2",X"CA",X"AF",X"42",X"48",X"32",X"20",X"E2",X"3A",X"A7",X"22",X"48",X"AA",X"CA",
+		X"C9",X"42",X"CA",X"A7",X"42",X"A1",X"32",X"AF",X"3A",X"22",X"22",X"45",X"33",X"FE",X"BB",X"D2",
+		X"42",X"BB",X"3A",X"C9",X"22",X"47",X"CA",X"A7",X"22",X"48",X"45",X"3A",X"FE",X"22",X"DA",X"33",
+		X"32",X"01",X"22",X"47",X"49",X"3A",X"A7",X"22",X"42",X"C7",X"32",X"3D",X"22",X"47",X"3E",X"C9",
+		X"17",X"D2",X"CD",X"43",X"42",X"E9",X"58",X"CD",X"78",X"C2",X"3A",X"47",X"22",X"45",X"26",X"FE",
+		X"2A",X"47",X"22",X"44",X"43",X"06",X"46",X"3A",X"3E",X"1D",X"32",X"A0",X"22",X"43",X"F2",X"C3",
+		X"57",X"0A",X"FF",X"C9",X"FF",X"FF",X"FF",X"FF",X"E6",X"22",X"87",X"03",X"0A",X"4F",X"03",X"5F",
+		X"44",X"2A",X"06",X"22",X"C3",X"47",X"42",X"EE",X"45",X"05",X"44",X"4F",X"44",X"AC",X"44",X"00",
+		X"42",X"E9",X"58",X"CD",X"3A",X"1D",X"22",X"46",X"49",X"3A",X"A7",X"22",X"8E",X"C2",X"CD",X"47",
+		X"22",X"44",X"D6",X"7D",X"6F",X"40",X"DE",X"7C",X"32",X"3C",X"22",X"46",X"03",X"E6",X"2A",X"F5",
+		X"2A",X"43",X"22",X"44",X"C6",X"7D",X"6F",X"1F",X"67",X"00",X"44",X"22",X"F1",X"22",X"47",X"C2",
+		X"42",X"E9",X"AA",X"CD",X"C9",X"1D",X"40",X"CD",X"CE",X"7C",X"67",X"00",X"44",X"22",X"CD",X"22",
+		X"40",X"A9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"CD",X"42",X"46",X"D6",X"28",X"CD",X"C3",X"0A",
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+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/6.t31.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/6.t31.vhd
new file mode 100644
index 00000000..bf2ef75f
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/6.t31.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity rom6t31 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of rom6t31 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"10",X"13",X"03",X"01",X"00",X"05",X"05",X"06",X"08",X"14",X"00",X"05",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"04",X"01",X"12",X"09",X"14",X"0E",X"0F",
+		X"57",X"21",X"36",X"22",X"21",X"00",X"2E",X"88",X"00",X"1B",X"00",X"1B",X"00",X"1B",X"00",X"00",
+		X"32",X"00",X"22",X"5B",X"1C",X"C2",X"C3",X"49",X"13",X"C3",X"21",X"49",X"22",X"57",X"3E",X"34",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"05",X"18",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"C2",X"0D",X"4A",X"55",X"18",X"11",X"19",X"00",X"0C",X"21",X"0E",X"2E",X"36",X"08",X"23",X"00",
+		X"FF",X"04",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FE",X"7C",X"C2",X"37",X"4A",X"53",X"D3",X"C3",
+		X"CA",X"81",X"4A",X"83",X"01",X"3E",X"59",X"32",X"03",X"DB",X"7F",X"EE",X"E6",X"F3",X"FE",X"81",
+		X"32",X"AF",X"22",X"59",X"00",X"DB",X"80",X"E6",X"AF",X"22",X"3A",X"C9",X"22",X"59",X"C8",X"A7",
+		X"22",X"5A",X"CA",X"A7",X"4A",X"A5",X"32",X"AF",X"97",X"CA",X"3E",X"4A",X"A7",X"01",X"3A",X"C9",
+		X"22",X"5A",X"C9",X"AF",X"18",X"01",X"1A",X"04",X"22",X"5A",X"93",X"C3",X"3E",X"4A",X"32",X"01",
+		X"06",X"C8",X"D5",X"04",X"1C",X"11",X"19",X"00",X"13",X"77",X"05",X"23",X"AF",X"C2",X"0D",X"4A",
+		X"4B",X"E0",X"AC",X"CD",X"21",X"4A",X"2A",X"16",X"C3",X"D1",X"4A",X"AF",X"16",X"21",X"11",X"26",
+		X"11",X"2E",X"4D",X"00",X"AC",X"CD",X"21",X"4A",X"A0",X"11",X"CD",X"4C",X"4A",X"AC",X"16",X"21",
+		X"60",X"11",X"21",X"4D",X"36",X"16",X"AC",X"CD",X"32",X"16",X"40",X"11",X"CD",X"4C",X"4A",X"AC",
+		X"4A",X"AC",X"DF",X"DF",X"DF",X"DF",X"C9",X"DF",X"11",X"4A",X"4D",X"C0",X"16",X"21",X"CD",X"3A",
+		X"1F",X"00",X"44",X"24",X"1F",X"24",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"3E",X"00",X"41",X"41",X"22",X"41",X"00",X"00",X"7F",X"00",X"49",X"49",X"36",X"49",X"00",X"00",
+		X"7F",X"00",X"49",X"49",X"41",X"49",X"00",X"00",X"7F",X"00",X"41",X"41",X"3E",X"41",X"00",X"00",
+		X"3E",X"00",X"41",X"41",X"47",X"45",X"00",X"00",X"7F",X"00",X"48",X"48",X"40",X"48",X"00",X"00",
+		X"00",X"00",X"7F",X"41",X"00",X"41",X"00",X"00",X"7F",X"00",X"08",X"08",X"7F",X"08",X"00",X"00",
+		X"7F",X"00",X"14",X"08",X"41",X"22",X"00",X"00",X"02",X"00",X"01",X"01",X"7E",X"01",X"00",X"00",
+		X"7F",X"00",X"18",X"20",X"7F",X"20",X"00",X"00",X"7F",X"00",X"01",X"01",X"01",X"01",X"00",X"00",
+		X"3E",X"00",X"41",X"41",X"3E",X"41",X"00",X"00",X"7F",X"00",X"08",X"10",X"7F",X"04",X"00",X"00",
+		X"3E",X"00",X"45",X"41",X"3D",X"42",X"00",X"00",X"7F",X"00",X"48",X"48",X"30",X"48",X"00",X"00",
+		X"32",X"00",X"49",X"49",X"26",X"49",X"00",X"00",X"7F",X"00",X"4C",X"48",X"31",X"4A",X"00",X"00",
+		X"7E",X"00",X"01",X"01",X"7E",X"01",X"00",X"00",X"40",X"00",X"7F",X"40",X"40",X"40",X"00",X"00",
+		X"7F",X"00",X"0C",X"02",X"7F",X"02",X"00",X"00",X"7C",X"00",X"01",X"02",X"7C",X"02",X"00",X"00",
+		X"60",X"00",X"0F",X"10",X"60",X"10",X"00",X"00",X"63",X"00",X"08",X"14",X"63",X"14",X"00",X"00",
+		X"08",X"00",X"08",X"08",X"08",X"08",X"00",X"00",X"43",X"00",X"49",X"45",X"61",X"51",X"00",X"00",
+		X"00",X"00",X"FF",X"C0",X"00",X"00",X"FF",X"F8",X"00",X"00",X"F8",X"00",X"00",X"00",X"FF",X"00",
+		X"FC",X"00",X"00",X"FF",X"FF",X"80",X"00",X"1F",X"00",X"00",X"FF",X"FF",X"F0",X"00",X"07",X"FF",
+		X"C2",X"23",X"48",X"03",X"A0",X"3E",X"43",X"32",X"00",X"21",X"36",X"00",X"23",X"00",X"FE",X"7C",
+		X"32",X"3D",X"22",X"4C",X"CA",X"A7",X"48",X"22",X"C3",X"22",X"40",X"CD",X"3A",X"F5",X"22",X"4C",
+		X"C3",X"33",X"1F",X"9F",X"D5",X"1A",X"11",X"E5",X"C9",X"F1",X"03",X"3E",X"4C",X"32",X"33",X"22",
+		X"0D",X"13",X"2C",X"C2",X"C9",X"48",X"FF",X"FF",X"4B",X"00",X"AA",X"CD",X"E1",X"0B",X"24",X"D1",
+		X"46",X"1A",X"DA",X"B8",X"48",X"57",X"7E",X"C2",X"AB",X"11",X"21",X"20",X"20",X"A7",X"03",X"0E",
+		X"50",X"32",X"11",X"22",X"20",X"A5",X"4D",X"21",X"1B",X"48",X"0D",X"2B",X"48",X"C2",X"AF",X"48",
+		X"22",X"4F",X"03",X"0E",X"46",X"1A",X"DA",X"B8",X"06",X"22",X"EF",X"03",X"A3",X"11",X"21",X"20",
+		X"6C",X"C2",X"C3",X"48",X"05",X"18",X"20",X"3E",X"48",X"89",X"18",X"C2",X"1B",X"05",X"0D",X"2B",
+		X"21",X"48",X"20",X"A1",X"4D",X"11",X"06",X"22",X"50",X"32",X"11",X"22",X"20",X"A9",X"5E",X"C3",
+		X"07",X"D3",X"51",X"21",X"3E",X"22",X"77",X"01",X"EF",X"03",X"80",X"C3",X"3A",X"49",X"22",X"50",
+		X"49",X"A0",X"0F",X"0E",X"2C",X"CD",X"3A",X"48",X"77",X"23",X"77",X"23",X"99",X"21",X"11",X"29",
+		X"11",X"49",X"0B",X"90",X"08",X"0E",X"F1",X"CD",X"22",X"50",X"21",X"A7",X"2D",X"17",X"76",X"C2",
+		X"CD",X"11",X"48",X"2C",X"93",X"21",X"11",X"29",X"21",X"09",X"28",X"95",X"B0",X"11",X"0E",X"49",
+		X"29",X"91",X"D8",X"11",X"0E",X"49",X"CD",X"0F",X"49",X"C8",X"0F",X"0E",X"2C",X"CD",X"21",X"48",
+		X"12",X"0E",X"2C",X"CD",X"21",X"48",X"2F",X"8D",X"48",X"2C",X"0F",X"21",X"11",X"28",X"49",X"E8",
+		X"0B",X"21",X"11",X"29",X"4A",X"08",X"10",X"0E",X"00",X"11",X"0E",X"4A",X"CD",X"03",X"48",X"2C",
+		X"0E",X"4A",X"CD",X"05",X"48",X"2C",X"03",X"3E",X"2C",X"CD",X"21",X"48",X"2E",X"88",X"20",X"11",
+		X"22",X"22",X"22",X"55",X"55",X"2A",X"0E",X"22",X"28",X"C3",X"11",X"4A",X"22",X"51",X"54",X"32",
+		X"22",X"50",X"C2",X"A7",X"49",X"4F",X"03",X"DB",X"D5",X"01",X"2C",X"CD",X"DF",X"48",X"3A",X"D1",
+		X"C4",X"20",X"49",X"6D",X"03",X"DB",X"10",X"E6",X"40",X"E6",X"64",X"C4",X"DB",X"49",X"E6",X"03",
+		X"C2",X"00",X"49",X"16",X"92",X"C3",X"DB",X"49",X"33",X"CA",X"C3",X"4A",X"4E",X"50",X"22",X"54",
+		X"20",X"E6",X"6D",X"C4",X"DB",X"49",X"E6",X"00",X"E6",X"00",X"C4",X"40",X"49",X"64",X"00",X"DB",
+		X"C0",X"1B",X"12",X"AF",X"1A",X"C9",X"12",X"3D",X"C3",X"10",X"49",X"40",X"3C",X"1A",X"FE",X"12",
+		X"C3",X"0B",X"48",X"BC",X"FF",X"FF",X"FF",X"FF",X"F0",X"A7",X"1A",X"3E",X"C9",X"12",X"98",X"11",
+		X"48",X"94",X"01",X"3E",X"E2",X"32",X"C3",X"20",X"11",X"CD",X"3A",X"40",X"22",X"50",X"CA",X"A7",
+		X"FF",X"05",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"48",X"95",X"32",X"AF",X"20",X"E2",X"18",X"C3",
+		X"01",X"0C",X"09",X"14",X"0E",X"0F",X"00",X"13",X"0F",X"03",X"07",X"0E",X"01",X"12",X"15",X"14",
+		X"01",X"00",X"08",X"03",X"09",X"05",X"05",X"16",X"0F",X"19",X"00",X"15",X"01",X"08",X"05",X"16",
+		X"0F",X"14",X"01",X"04",X"13",X"19",X"08",X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"0C",X"10",X"01",X"05",X"05",X"13",X"12",X"00",X"1B",X"09",X"03",X"13",X"12",X"0F",X"00",X"05",
+		X"0F",X"19",X"12",X"15",X"09",X"00",X"09",X"0E",X"07",X"05",X"13",X"09",X"05",X"14",X"00",X"12",
+		X"08",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"09",X"14",X"0C",X"01",X"00",X"13",X"09",X"17",
+		X"07",X"E0",X"07",X"E0",X"03",X"FF",X"FF",X"C0",X"1F",X"80",X"01",X"F8",X"0F",X"C0",X"03",X"F0",
+		X"00",X"7F",X"FE",X"00",X"00",X"3F",X"FC",X"00",X"01",X"FF",X"FF",X"80",X"00",X"FF",X"FF",X"00",
+		X"06",X"06",X"EE",X"7E",X"77",X"FF",X"05",X"23",X"0F",X"0E",X"15",X"21",X"11",X"25",X"00",X"1A",
+		X"19",X"4E",X"28",X"C3",X"0D",X"4E",X"C5",X"F5",X"2A",X"C2",X"7C",X"4E",X"3E",X"FE",X"3D",X"CA",
+		X"FF",X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DF",X"DF",X"C1",X"00",X"C2",X"F1",X"4E",X"22",
+		X"3A",X"24",X"22",X"54",X"CA",X"3D",X"49",X"92",X"5B",X"3A",X"A7",X"22",X"1C",X"C2",X"13",X"49",
+		X"C3",X"3D",X"49",X"16",X"FF",X"FF",X"FF",X"FF",X"01",X"3E",X"5B",X"32",X"3A",X"22",X"22",X"54",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
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+		X"3F",X"FF",X"00",X"00",X"0F",X"FF",X"00",X"00",X"FF",X"F0",X"00",X"03",X"FF",X"FC",X"00",X"00",
+		X"FF",X"FC",X"00",X"00",X"FF",X"F0",X"00",X"03",X"0F",X"FF",X"00",X"00",X"3F",X"FF",X"00",X"00",
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+		X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",
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+		X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"F8",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",
+		X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",
+		X"FF",X"FC",X"3F",X"FF",X"FF",X"FE",X"7F",X"FF",X"FF",X"F0",X"0F",X"FF",X"FF",X"F8",X"1F",X"FF",
+		X"00",X"3F",X"FC",X"00",X"00",X"1F",X"F8",X"00",X"FF",X"FF",X"FF",X"FF",X"00",X"7F",X"FE",X"00",
+		X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00",
+		X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00",
+		X"00",X"7F",X"FE",X"00",X"FF",X"FF",X"FF",X"FF",X"00",X"1F",X"F8",X"00",X"00",X"3F",X"FC",X"00",
+		X"FF",X"F8",X"1F",X"FF",X"FF",X"F0",X"0F",X"FF",X"FF",X"FE",X"7F",X"FF",X"FF",X"FC",X"3F",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"E0",X"00",X"F8",X"03",X"E0",X"00",X"F8",X"03",X"FF",X"FF",X"FF",X"FF",X"E0",X"00",X"F8",X"03",
+		X"FE",X"00",X"F8",X"03",X"FF",X"80",X"F8",X"03",X"F0",X"00",X"F8",X"03",X"FC",X"00",X"F8",X"03",
+		X"EF",X"F8",X"F8",X"03",X"E3",X"FC",X"F8",X"03",X"FF",X"C0",X"F8",X"03",X"FF",X"E0",X"F8",X"03",
+		X"C0",X"3F",X"7F",X"FF",X"80",X"0F",X"7F",X"FF",X"E1",X"FF",X"FC",X"07",X"C0",X"FF",X"FE",X"0F",
+		X"00",X"01",X"07",X"F8",X"00",X"00",X"00",X"00",X"00",X"07",X"3F",X"FF",X"00",X"03",X"1F",X"FE",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03",X"FF",X"FF",X"FF",X"FF",X"E0",X"1F",X"F8",X"03",
+		X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03",
+		X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03",
+		X"E0",X"1F",X"F8",X"03",X"00",X"1F",X"F8",X"00",X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03",
+		X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00",
+		X"00",X"FF",X"FF",X"00",X"01",X"FF",X"FF",X"80",X"00",X"3F",X"FC",X"00",X"00",X"7F",X"FE",X"00",
+		X"0F",X"C0",X"03",X"F0",X"1F",X"80",X"01",X"F8",X"03",X"FF",X"FF",X"C0",X"07",X"E0",X"07",X"E0",
+		X"FC",X"00",X"00",X"3F",X"F8",X"00",X"00",X"1F",X"3F",X"00",X"00",X"FC",X"FE",X"00",X"00",X"7F",
+		X"FE",X"00",X"00",X"7F",X"3F",X"00",X"00",X"FC",X"F8",X"00",X"00",X"1F",X"FC",X"00",X"00",X"3F");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/README.txt
new file mode 100644
index 00000000..871b6a6a
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/README.txt	
@@ -0,0 +1,27 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: Western Gun Part II port to MiST by Gehstock 
+-- 05 June 2019
+-- 
+---------------------------------------------------------------------------------
+-- 
+-- Midway 8080 Hardware
+-- Audio based on work by Paul Walsh.
+-- Audio and scan converter by MikeJ.
+---------------------------------------------------------------------------------
+-- 
+-- 
+-- Keyboard inputs :
+--
+--   F1          : Start
+--   SPACE       : Fire
+--   RIGHT/LEFT  : Movement
+--
+-- Joystick support.
+-- 
+-- 
+---------------------------------------------------------------------------------
+
+ToDo: Color Prom
+      Controls + DIP
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.qpf
new file mode 100644
index 00000000..b277111e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.qpf	
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 18:00:31  July 15, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "18:00:31  July 15, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "WesternGunPtII"
+PROJECT_REVISION = "SpaceInvaders"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.qsf
new file mode 100644
index 00000000..2a568027
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.qsf	
@@ -0,0 +1,172 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 19:48:57  August 10, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		WesternGunPtII_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/westerngun_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/westerngun_memory.sv
+set_global_assignment -name VHDL_FILE rtl/westerngun_overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY westerngun_mist
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# --------------------------------
+# start ENTITY(spaceinvaders_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(spaceinvaders_mist)
+# ------------------------------
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.sdc
new file mode 100644
index 00000000..f91c127c
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/clean.bat
new file mode 100644
index 00000000..83fb0c47
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T8080se.vhd
new file mode 100644
index 00000000..65b92d54
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T8080se.vhd	
@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..e09def1e
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..1c0f2638
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/invaders.vhd
new file mode 100644
index 00000000..876ed1fc
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/invaders.vhd	
@@ -0,0 +1,277 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft1        : in  std_logic;
+		MoveRight1       : in  std_logic;
+		MoveUp1        	 : in  std_logic;
+		MoveDown1        : in  std_logic;
+		MoveLeft2        : in  std_logic;
+		MoveRight2       : in  std_logic;
+		MoveUp2        	 : in  std_logic;
+		MoveDown2        : in  std_logic;
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+	component mw8080
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+	end component;
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: mw8080
+		port map(
+			Rst_n => Rst_n,--Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+
+	GDB0(0) <= '0';
+	GDB0(1) <= '0';
+	GDB0(2) <= '0';
+	GDB0(3) <= '0';
+	GDB0(4) <= '0';
+	GDB0(5) <= '0';
+	GDB0(6) <= '0';
+	GDB0(7) <= '0';
+
+	GDB1(0) <= not MoveRight1;
+	GDB1(1) <= not MoveLeft1;
+	GDB1(2) <= not MoveUp1;
+	GDB1(3) <= not MoveDown1;
+	GDB1(4) <= not MoveRight2;
+	GDB1(5) <= not MoveLeft2;
+	GDB1(6) <= not MoveUp2;
+	GDB1(7) <= not MoveDown2;
+
+	GDB2(0) <= not Fire;
+	GDB2(1) <= not Fire;
+	GDB2(2) <= not Sel1Player;
+	GDB2(3) <= not Sel2Player;
+	GDB2(4) <= '1';--Lives
+	GDB2(5) <= '1';--Cabinet
+	GDB2(6) <= '1';--unused
+	GDB2(7) <= not Coin;
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/invaders_audio.vhd
new file mode 100644
index 00000000..f16cf379
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/invaders_audio.vhd	
@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/mw8080.vhd
new file mode 100644
index 00000000..b9a88f96
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/mw8080.vhd	
@@ -0,0 +1,336 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/pll.qip
new file mode 100644
index 00000000..48665362
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/pll.vhd
new file mode 100644
index 00000000..97a42db7
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/pll.vhd	
@@ -0,0 +1,382 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 20,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic32.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic32.hex
new file mode 100644
index 00000000..251ad2c5
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic32.hex	
@@ -0,0 +1,66 @@
+:020000040000FA
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+:2000200020218272010209CD64213E0132FD67214D7211EE1A010B03C5CD5921C111561C00
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+:200060000609C3332108492214814242811422490800008080F0F8B0BC3A3A3A1818080884
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+:2000C000E0E07632341800D0600609F8F671416040404040C0C0C0E0F0FFF9010000000123
+:2000E00003060C0F0F0704050505050504070F3F7F7FFFFFF8E0F0FC3EFC01030703070F32
+:2001000003050400000200C001002000401000401011C1DC0FFFFE0DE09F0FD0C10FCAE0B1
+:200120000606600000000000000080C8F8C1FFC04000001A77CD3D2105C23321C93AFD6715
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+:2004A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5C
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+:2004E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1C
+:20050000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB
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+:20054000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBB
+:20056000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9B
+:20058000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7B
+:2005A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5B
+:2005C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3B
+:2005E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1B
+:20060000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA
+:20062000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDA
+:20064000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBA
+:20066000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9A
+:20068000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7A
+:2006A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5A
+:2006C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3A
+:2006E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1A
+:20070000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9
+:20072000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD9
+:20074000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB9
+:20076000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF99
+:20078000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF79
+:2007A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF59
+:2007C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF39
+:2007E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF19
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic33.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic33.hex
new file mode 100644
index 00000000..c763f525
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic33.hex	
@@ -0,0 +1,66 @@
+:020000040000FA
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic34.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic34.hex
new file mode 100644
index 00000000..3e90c4b8
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic34.hex	
@@ -0,0 +1,66 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic35.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic35.hex
new file mode 100644
index 00000000..25cd8543
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic35.hex	
@@ -0,0 +1,66 @@
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic35sound.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic35sound.hex
new file mode 100644
index 00000000..8c4fdccf
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic35sound.hex	
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+:2005A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5B
+:2005C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3B
+:2005E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1B
+:20060000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA
+:20062000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDA
+:20064000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBA
+:20066000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9A
+:20068000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7A
+:2006A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5A
+:2006C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3A
+:2006E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1A
+:20070000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9
+:20072000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD9
+:20074000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB9
+:20076000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF99
+:20078000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF79
+:2007A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF59
+:2007C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF39
+:2007E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF19
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic36.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic36.hex
new file mode 100644
index 00000000..2ff5aef2
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic36.hex	
@@ -0,0 +1,66 @@
+:020000040000FA
+:20000000C3DB000000FF0000F5C5D5E5C3B00100F5C5D5E5C3D602EE1A1B1B481B751BA279
+:200020001BCF1BFC1B291C561C831CB01CDD1C0A1D371D641D911D0000FA06FA06000000DF
+:2000400000FB05FB0500000000FC04FC0400000000FD03FD030000030302060208010A0776
+:2000600002020203030408010F0100080403030202020701020C0C080F08000C0C020106DD
+:200080000E00050F0E03030E0904000FFD03FD06FD00FBFEFDFDFDFE03FC00FE0EFD030007
+:2000A00004080C10140105090D111502060A0E121603070B0F1317FF000300FD000003002A
+:2000C000020202FE0000FD00FE02FEFE010505030204040708060102060807310080DB0250
+:2000E000E640CA0024CDEF05CD860DAF32826032866032C36032E160CDA423CDB9232F328A
+:20010000C2603E613280603E0ACD9023DB02CD1A243E1532D960CD1A08AF32C160FB3E2054
+:20012000CDD90F118506CD810FCDBA063EFF32C36021014B1118100E0ACDBE0D21154A0E0E
+:200140000CCDBE0D2110480E10CDE40F210E480E11CDE40F3ED0CDD90FAF32C360211A51FB
+:20016000CDD7233E40CDD90FCD930DAFCD9023CD3F08CDBA06CDD206CD4007CD040D3E0172
+:2001800032C160CD7508CDF608CD030A3A3560A7C27E01CDF6083A3560A7CA9301AF32C125
+:2001A0006032DF6032C360FB3E20CDD90FC3E800AF3283603AC260A7CA96023ADF60A7C255
+:2001C000C9013AC1600FD27302213060CD53131108602E0F0610CDC6101213A7C2ED012FA6
+:2001E0001312320C60011160AF0203021B2E170618CDC61012A7C202022F3282603E0FC321
+:2002000037023ADF60A7CA58023A3560A7CA37023A0160A7FA6E02C23D021E0A1A1BA70631
+:200220000ACA31020601FA31021A3D0FE6073C3C473A8B60E620B0CDB923C34702FE08CA11
+:2002400047020610CDB3233A2F60473A7F60B0473A8A60E6EDCDA3233A3560A7CA6502CD7E
+:20026000D910CD0D12CD431AE1D1C1F1FBC9060DC331023AC360A7CA680221906035C268A6
+:2002800002360C0E03CDB602212472DA90022EA4229160C368023AC460A7F26802219060DD
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+:2002C0007DC6066F7E2B35FAD1024E2B8277790FC9AF32C460C93E8032836021C06035DB06
+:2002E0000207DA020321DA607EA7CA0703237EFE99CAFE02C6012777211F5ACDC00FAFC3B3
+:2003000004033EFF32DA603AC260A7CAB7033ADF60A7C223033ADB60A7C2CD033AC1600F86
+:20032000D27C03212060CD53132130607EFEFD3EFEC23503AF773A8660A7C24303CD6A12FA
+:20034000C36802217160357EFA630323CA6803CDB40F0E01CDA412EB2272600604CD962382
+:20036000C3680236FFC36802CDD012AF3286603E0432256006FBCD9623C368023AC360A7C7
+:20038000CA680221986035C26802CD8612CDA111210660CD9E12C6FE772E9836050E02CDAE
+:2003A000B602212473DAAA032E54229960219D60CD9E1277C368023AC460A7CA6802F283BC
+:2003C0000321986035C268023605C39D03310080AF328860CDB92332C46032C2603C32DFE8
+:2003E00060CDA423FBCD930D0600CD8A23CD1A080E0421124E115510CDBE0D210A4D0E0605
+:20040000CDBE0D210E490E0E3ADB603DCA2D04116D10CDBE0D0698DB020F0F0F0FDA280420
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+:2004600011B006060ACD6D0FCD910FCD970F3A8160A7C27D042AFE600630CDAC0DCDBA06A6
+:20048000CDD206CDD8063E61328060CD930D0600CD8A233A8960A7FABF053E40F5CDDB05C6
+:2004A000117B1021104B0E0ACDBE0DF1CDD90FCD930DCDBD06AF328260328660CD40073AA8
+:2004C0008160A7CAD3043E30CD0623CD930D0600CD8A23CD3F08CD040D3A8060672E373E8C
+:2004E0000F320360F5562B5E2BE5EB220560CD6F12E1F13DF2E104AFCD700D1A32376006EC
+:2005000010C5CD431AC105C201053A3B60323F600E10C5790FDA1E05CD1A16C32105CD2667
+:20052000163E03CDD90FC10DC2120521000022FE6721011022FC67010204210763C5E53A33
+:200540000B60A7113F00FACC05FE04D265051E4FFE01D257051E47CD642121040019EBE1D5
+:2005600023C1CD6421211F45E50660CDAC0D2EFFCD0C08F5CD1208F1E13DCA87054F3E0A09
+:20058000CDD80D0DC27E057C32D8603EFF32C260CD7508CDF608CD030ACD75213A8260A7CB
+:2005A000CA90053E60CDD90F3A3560A7CAAC05AF32C260310080CD7521CDE721C3B2043AF9
+:2005C0008160A7C4BF233EA0F5C3A004FEFCD25505FEECD257051E37C357053A80600F3E9A
+:2005E00020D2E505AF473A8860E61FB0C39023CDBA062EC01103000603CD6D0F2EDA11A53D
+:20060000060606CD6D0F2EF111AB06060FC36D0F000000FF01B8A800101000070319320075
+:200620000050407901000000941300100000040000000000000010048214FF68790004EF78
+:20064000010100000100100032160000000000000000000000001000AA180000009F00A529
+:2006600000AB00B10000400046196C14000032EF1D18E01004FFFF006814000020B06C14EB
+:2006800000000005000C2472203038800305247310B89880FE05D0710E38302202052473B2
+:2006A0001038BF22FE000000D608000000001D4D0000001D440000001D56CD760F21206004
+:2006C0001125060651CD6D0F2E71117606060FC36D0F210061C3E306210062C3E3062E0033
+:2006E000CD0C08064811F806CD6D0FCD9F072EE41110060615C36D0F05050505070707073D
+:200700000101010103030303F1F3F5F7F8F2F4F6CCDACCA8CC76CC44CC129A12681236126D
+:2007200004120444047604A804DA36DA68DA9ADA9A44364436A89AA8CC12041204DACCDAA1
+:20074000210063CD890FCD890F21010822FC672142630608C3332100FF00C91706FF00FECF
+:200760000000C91706FF0000FF01D017061200020101D01706121000FF02D717FF09FE008D
+:200780000202D717FF092000FF03DE170F0902000303DE170F093004040505060607072E91
+:2007A000480E0411EA07D5061ECD6D0FD10DC2A607AFD3033E04D30247110808C51A6F13E9
+:2007C000D5780F0E0ED2E0073A0B602FE607C61BCDCA0D010701CD881ED1C105C2BC07C941
+:2007E0003600230DC2E007C3D907AEEAFEFFFEFFF83FF83FF83FF83FF83FF83FF83FF83FFD
+:00000001FF
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/spram.vhd	
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_memory.sv
new file mode 100644
index 00000000..684014b4
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_memory.sv	
@@ -0,0 +1,93 @@
+
+module westerngun_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+wire [7:0]rom_data_4;
+
+
+sprom #(
+	.init_file("./roms/ic36.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_0)
+	);
+
+sprom #(
+	.init_file("./roms/ic35.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_1)
+	);
+	
+sprom #(
+	.init_file("./roms/ic34.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_2)
+	);
+	
+sprom #(
+	.init_file("./roms/ic33.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_e (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_3)
+	);
+
+sprom #(
+	.init_file("./roms/ic32.hex"),
+	.widthad_a(11),
+	.width_a(8))
+u_rom_d (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_4)
+	);	
+	
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4) begin
+	Rom_out = 8'b00000000;
+		case (Addr[15:11])
+			5'b00000 : Rom_out = rom_data_0;
+			5'b00001 : Rom_out = rom_data_1;
+			5'b00010 : Rom_out = rom_data_2;
+			5'b00011 : Rom_out = rom_data_3;
+			5'b01000 : Rom_out = rom_data_4;
+			default : Rom_out = 8'b00000000;
+		endcase
+
+end
+		
+spram #(
+	.addr_width_g(14),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[13:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_mist.sv
new file mode 100644
index 00000000..83286f52
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_mist.sv	
@@ -0,0 +1,218 @@
+module westerngun_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"WesternGunPtII;;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Overlay, On, Off;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_core, clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft1(~m_left),
+	.MoveRight1(~m_right),
+	.MoveUp1(~m_up),
+	.MoveDown1(~m_down),
+	.MoveLeft2(~m_left),
+	.MoveRight2(~m_right),
+	.MoveUp2(~m_up),
+	.MoveDown2(~m_down),
+//	.DIP(dip),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(HSync),
+	.VSync(VSync)
+	);
+		
+westerngun_memory westerngun_memory (
+	.Clock(clk_sys),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_sys),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);		
+	  
+westerngun_overlay westerngun_overlay (
+	.Video(Video),
+	.Overlay(~status[5]),
+	.CLK(clk_sys),
+	.Rst_n_s(Rst_n_s),
+	.HSync(HSync),
+	.VSync(VSync),
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({r,r,r}),
+	.G({g,g,g}),
+	.B({b,b,b}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.rotate({1'b0,status[2]}),
+	.scandoubler_disable(scandoublerD),
+	.ce_divider(0),
+	.scanlines(status[4:3]),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_fire2 = 0;
+reg btn_fire3 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h14: btn_fire3       <= key_pressed; // ctrl
+			'h11: btn_fire2       <= key_pressed; // alt
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_overlay.vhd
new file mode 100644
index 00000000..ffa6ec94
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_overlay.vhd	
@@ -0,0 +1,127 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+entity westerngun_overlay is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end westerngun_overlay;
+
+architecture rtl of westerngun_overlay is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_G1      : boolean;
+	signal Overlay_G2      : boolean;
+	signal Overlay_R1      : boolean;
+	signal Overlay_G1_VCnt : boolean;
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  Overlay_G1_VCnt <= false;
+	  Overlay_G1 <= false;
+	  Overlay_G2 <= false;
+	  Overlay_R1 <= false;
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt = x"1F") then
+		  Overlay_G1_VCnt <= true;
+		elsif (Vcnt = x"95") then
+		  Overlay_G1_VCnt <= false;
+		end if;
+	  end if;
+
+	  if (HCnt = x"027") and Overlay_G1_VCnt then
+		Overlay_G1 <= true;
+	  elsif (HCnt = x"046") then
+		Overlay_G1 <= false;
+	  end if;
+
+	  if (HCnt = x"046") then
+		Overlay_G2 <= true;
+	  elsif (HCnt = x"0B6") then
+		Overlay_G2 <= false;
+	  end if;
+
+	  if (HCnt = x"1A6") then
+		Overlay_R1 <= true;
+	  elsif (HCnt = x"1E6") then
+		Overlay_R1 <= false;
+	  end if;
+
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1)
+  begin
+	if (Video = '0') then
+	  VideoRGB  <= "000";
+	else
+	  if Overlay_G1 or Overlay_G2 then
+		VideoRGB  <= "010";
+	  elsif Overlay_R1 then
+		VideoRGB  <= "100";
+	  else
+		VideoRGB  <= "111";
+	  end if;
+	end if;
+  end process;
+
+
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_HSYNC   <= HSync;
+  O_VSYNC   <= VSync;
+
+
+end;
\ No newline at end of file