From c525056fb3c06e1c06ebda9335ad476be3968fd6 Mon Sep 17 00:00:00 2001 From: Marcel Date: Mon, 1 Jun 2020 16:45:14 +0200 Subject: [PATCH] Use Common Components --- .../Centipede_MiST/Centipede.qsf | 9 +- .../Centipede_MiST/rtl/Centipede.sv | 149 ++- .../Centipede_MiST/rtl/Pokey/POKEY.sv | 505 -------- .../Centipede_MiST/rtl/Pokey/matoro.sv | 129 -- .../Centipede_MiST/rtl/t65/T65.vhd | 564 --------- .../Centipede_MiST/rtl/t65/T65_ALU.vhd | 260 ---- .../Centipede_MiST/rtl/t65/T65_MCode.vhd | 1052 ----------------- .../Centipede_MiST/rtl/t65/T65_Pack.vhd | 117 -- 8 files changed, 70 insertions(+), 2715 deletions(-) delete mode 100644 Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Pokey/POKEY.sv delete mode 100644 Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Pokey/matoro.sv delete mode 100644 Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65.vhd delete mode 100644 Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65_ALU.vhd delete mode 100644 Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65_MCode.vhd delete mode 100644 Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65_Pack.vhd diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.qsf b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.qsf index 5d0bdef1..90f08935 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.qsf +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.qsf @@ -148,12 +148,6 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name SYSTEMVERILOG_FILE rtl/Centipede.sv set_global_assignment -name VERILOG_FILE rtl/centipede.v set_global_assignment -name VERILOG_FILE rtl/pf_ram.v -set_global_assignment -name VHDL_FILE rtl/t65/T65_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/t65/T65_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/t65/T65_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/t65/T65.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Pokey/POKEY.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Pokey/matoro.sv set_global_assignment -name VHDL_FILE rtl/roms/F7.vhd set_global_assignment -name VHDL_FILE rtl/roms/HJ7.vhd set_global_assignment -name VHDL_FILE rtl/roms/PROG.vhd @@ -162,4 +156,7 @@ set_global_assignment -name VHDL_FILE rtl/spram.vhd set_global_assignment -name VHDL_FILE rtl/dpram.vhd set_global_assignment -name VHDL_FILE rtl/pll.vhd set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip +set_global_assignment -name SYSTEMVERILOG_FILE ../../../common/Sound/Pokey/POKEY.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../../../common/Sound/Pokey/matoro.sv +set_global_assignment -name QIP_FILE ../../../common/CPU/T65/T65.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede.sv b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede.sv index 9874a587..671846ed 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede.sv +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede.sv @@ -1,8 +1,7 @@ //============================================================================ // Arcade: Centipede // -// Port to MiST -// Copyright (C) 2018 Gehstock +// Port to MiST 2018 Gehstock // // This program is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License as published by the Free @@ -42,13 +41,20 @@ module Centipede localparam CONF_STR = { "Centipede;;", - "O1,Test,Off,On;", "O2,Rotate Controls,Off,On;", "O34,Scanlines,Off,25%,50%,75%;", - "T7,Reset;", - "V,v1.40.",`BUILD_DATE + "O5,Blend,Off,On;", + "O7,Test,Off,On;", + "T0,Reset;", + "V,v1.50.",`BUILD_DATE }; +wire rotate = status[2]; +wire [1:0] scanlines = status[4:3]; +wire blend = status[5]; +wire joyswap = status[6]; +wire service = status[7]; + assign LED = 1; assign AUDIO_R = AUDIO_L; @@ -65,24 +71,26 @@ pll pll( wire [31:0] status; wire [1:0] buttons; wire [1:0] switches; -wire [7:0] joystick_0, joystick_1; +wire [7:0] joystick_0; +wire [7:0] joystick_1; wire scandoublerD; wire ypbpr; -wire [10:0] ps2_key; -wire [6:0] audio1, audio2; +wire no_csync; +wire key_pressed; +wire [7:0] key_code; +wire key_strobe; wire [7:0] RGB; -wire vb, hb; +wire hs, vs, vb, hb; wire blankn = ~(hb | vb); -wire hs, vs; wire [3:0] audio; centipede centipede( .clk_100mhz(clk_100mhz), .clk_12mhz(clk_12), - .reset(status[0] | status[7] | buttons[1]), - .playerinput_i({ r_coin, c_coin, l_coin, m_test, m_cocktail, m_slam, m_start2, m_start1, m_fire2, m_fire1 }), + .reset(status[0] | buttons[1]), + .playerinput_i(~{ 1'b0, 1'b0, m_coin1, service, 1'b0, 1'b0, m_two_players, m_one_player, m_fireB, m_fireA }), .trakball_i(), - .joystick_i({m_right , m_left, m_down, m_up, m_right , m_left, m_down, m_up}), + .joystick_i(~{m_right , m_left, m_down, m_up, m_right , m_left, m_down, m_up}), .sw1_i("01010100"), .sw2_i("00000000"), .rgb_o(RGB), @@ -92,28 +100,30 @@ centipede centipede( .vblank_o(vb), .audio_o(audio) ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_24), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? RGB[2:0] : 0), - .G(blankn ? RGB[5:3] : 0), - .B(blankn ? RGB[7:6] : 0), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}),//(left/right,on/off) - .scandoubler_disable(scandoublerD), - .scanlines(status[4:3]), - .ypbpr(ypbpr) - ); - + +mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( + .clk_sys ( clk_24 ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R (blankn ? RGB[2:0] : 0), + .G (blankn ? RGB[5:3] : 0), + .B (blankn ? RGB[7:6] : 0), + .HSync ( hs ), + .VSync ( vs ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ), + .rotate ( { 1'b0, rotate } ), + .ce_divider ( 1'b1 ), + .blend ( blend ), + .scandoubler_disable(scandoublerD ), + .no_csync ( 1'b1 ), + .ypbpr ( ypbpr ) + ); + user_io #( .STRLEN(($size(CONF_STR)>>3))) user_io( @@ -127,67 +137,42 @@ user_io( .switches (switches ), .scandoubler_disable (scandoublerD ), .ypbpr (ypbpr ), + .no_csync (no_csync ), .key_strobe (key_strobe ), .key_pressed (key_pressed ), .key_code (key_code ), .joystick_0 (joystick_0 ), .joystick_1 (joystick_1 ), .status (status ) - ); + ); dac #( .C_bits(15)) dac ( .clk_i(clk_24), .res_n_i(1), - .dac_i({2{2'b0,audio,audio}}), + .dac_i({2{audio,audio}}), .dac_o(AUDIO_L) ); + +wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF; +wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F; +wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players; -wire m_up = status[2] ? ~btn_up & ~joystick_0[3] & ~joystick_1[3] : ~btn_right & ~joystick_0[0] & ~joystick_1[0]; -wire m_down = status[2] ? ~btn_down & ~joystick_0[2] & ~joystick_1[2] : ~btn_left & ~joystick_0[1] & ~joystick_1[1]; -wire m_left = status[2] ? ~btn_left & ~joystick_0[1] & ~joystick_1[1] : ~btn_up & ~joystick_0[3] & ~joystick_1[3]; -wire m_right = status[2] ? ~btn_right & ~joystick_0[0] & ~joystick_1[0] : ~btn_down & ~joystick_0[2] & ~joystick_1[2]; - -wire m_start1 = ~btn_one_player; -wire m_start2 = 1'b1; -wire m_fire1 = ~btn_fire1 & ~joystick_0[4] & ~joystick_1[4]; -wire m_fire2 = 1'b1; -wire c_coin = ~btn_coin; -wire l_coin, r_coin = 1'b1; -wire m_test = ~status[1]; -wire m_slam = 1'b1;//generate Noise -wire m_cocktail = 1'b1; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; - -always @(posedge clk_24) begin - if(key_strobe) begin - case(key_code) - 'h75: btn_up <= key_pressed; // up - 'h72: btn_down <= key_pressed; // down - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h14: btn_fire3 <= key_pressed; // ctrl - 'h11: btn_fire2 <= key_pressed; // alt - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end +arcade_inputs inputs ( + .clk ( clk_24 ), + .key_strobe ( key_strobe ), + .key_pressed ( key_pressed ), + .key_code ( key_code ), + .joystick_0 ( joystick_0 ), + .joystick_1 ( joystick_1 ), + .rotate ( rotate ), + .orientation ( 2'b01 ), + .joyswap ( joyswap ), + .oneplayer ( 1'b1 ), + .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ), + .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ), + .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} ) +); endmodule diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Pokey/POKEY.sv b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Pokey/POKEY.sv deleted file mode 100644 index 6cbbac04..00000000 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Pokey/POKEY.sv +++ /dev/null @@ -1,505 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: M-x Butterfly -// Engineer: Peter Pearson -// -// Create Date: 10/29/2015 03:59:30 PM -// Design Name: -// Module Name: POKEY -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - - - -module POKEY - ( - input logic [7:0] Din, - output logic [7:0] Dout, - input logic [3:0] A, - input logic [7:0] P, - input logic phi2, - input logic readHighWriteLow, - input logic cs0Bar, - output logic aud, - output logic [3:0] audio, - //This clk is the 100 MHz clock, and is not a pin on the POKEY DIP - input logic clk - ); - - - logic [7:0] audf1, audf2, audf3, audf4, audc1, audc2, audc3, audc4, audCtl, allPot, skCtl; - logic [7:0] dataIn, dataOut; - logic clr; - logic baseClkWave; - logic wave15k, pulse15k, wave64k, pulse64k, wave179m, pulse179m; - logic rand4, rand5, rand17, reduce9; - logic [7:0] rngRead; - logic phi2Rising; - logic [3:0] bypassMask1, bypassMask2, bypassMask3, bypassMask4; - - //Outputs of the divide-by-N blocks for each channel - logic [3:0] divOut; - - //Base clock fed to each channel - logic [3:0] baseClks; - - //High pass filter clocks fed to each channel - logic [3:0] hpfClks; - - //Output waveform of each channel - logic [3:0] rawWave; - - assign clr = (skCtl[1:0] == 2'b00); - - -// tristateDriver #(8) triDrv(.i(dataOut), .o(D), .en(readHighWriteLow)); - assign dataIn = Din; - assign Dout = dataOut; - - - wave15kGen w15k(.clk(clk), .clr(clr), .wave(wave15k), .pulse(pulse15k)); - wave64kGen w64k(.clk(clk), .clr(clr), .wave(wave64k), .pulse(pulse64k)); - wave179mGen w179m(.clk(clk), .clr(clr), .wave(wave179m), .pulse(pulse179m)); - - polyCounter4 pc4(.clk(clk), .pulse179m(pulse179m), .rand4(rand4), .clr(clr)); - polyCounter5 pc5(.clk(clk), .pulse179m(pulse179m), .rand5(rand5), .clr(clr)); - polyCounter17 pc17(.clk(clk), .pulse179m(pulse179m), .reduce9(reduce9), .rand17(rand17), .rngVal(rngRead), .clr(clr)); - - - risingDetector risingPhi(.clk(clk), .clr(clr), .signalIn(phi2), .risingEdge(phi2Rising)); - - - audioChannelDigital channel1(.clk(clk), .clr(clr), .baseClkWave(baseClks[0]), .audf(audf1), .audc(audc1), .rand4(rand4), .rand5(rand5), .rand17(rand17), .hpfClk(hpfClks[0]), .bypassMask(bypassMask1), .rawWave(rawWave[0]), .divOut(divOut[0])); - audioChannelDigital channel2(.clk(clk), .clr(clr), .baseClkWave(baseClks[1]), .audf(audf2), .audc(audc2), .rand4(rand4), .rand5(rand5), .rand17(rand17), .hpfClk(hpfClks[1]), .bypassMask(bypassMask2), .rawWave(rawWave[1]), .divOut(divOut[1])); - audioChannelDigital channel3(.clk(clk), .clr(clr), .baseClkWave(baseClks[2]), .audf(audf3), .audc(audc3), .rand4(rand4), .rand5(rand5), .rand17(rand17), .hpfClk(hpfClks[2]), .bypassMask(bypassMask3), .rawWave(rawWave[2]), .divOut(divOut[2])); - audioChannelDigital channel4(.clk(clk), .clr(clr), .baseClkWave(baseClks[3]), .audf(audf4), .audc(audc4), .rand4(rand4), .rand5(rand5), .rand17(rand17), .hpfClk(hpfClks[3]), .bypassMask(bypassMask4), .rawWave(rawWave[3]), .divOut(divOut[3])); - - assign audio = {4{aud}}; - volumeMixer finalMix(.clk(clk), .clr(clr), .audc1(audc1), .audc2(audc2), .audc3(audc3), .audc4(audc4), .digitalWave(rawWave), .pwmWave(aud)); - - - assign hpfClks = {{divOut[2]},{divOut[3]},{2'b00}}; - - - //AUDCTL and bypass mask logic - always_comb - begin - reduce9 = audCtl[7]; - - baseClks[0] = (audCtl[6] ? wave179m : baseClkWave); - baseClks[2] = (audCtl[5] ? wave179m : baseClkWave); - baseClks[1] = (audCtl[4] ? divOut[0] : baseClkWave); - baseClks[3] = (audCtl[3] ? divOut[2] : baseClkWave); - - bypassMask1 = {{audCtl[2]},{3'b000}}; - bypassMask2 = {{audCtl[1]},{3'b000}}; - bypassMask3 = 4'h8; - bypassMask4 = 4'h8; - - baseClkWave = (audCtl[0] ? wave15k : wave64k); - end - - - always_ff@(posedge clk) - begin - if(phi2Rising & !cs0Bar) - begin - if(clr) - begin - audf1 <= 8'd0; - audf2 <= 8'd0; - audf3 <= 8'd0; - audf4 <= 8'd0; - audc1 <= 8'd0; - audc2 <= 8'd0; - audc3 <= 8'd0; - audc4 <= 8'd0; - audCtl <= 8'd0; - allPot <= 8'd0; - dataOut <= 8'd0; - if(!readHighWriteLow & (A == 4'hF)) - begin - skCtl <= dataIn; - end - end - else - begin - if(readHighWriteLow) - begin - case(A) - 4'h8: dataOut <= allPot; - 4'hA: dataOut <= rngRead; - endcase - end - else - begin - case(A) - 4'h0: audf1 <= dataIn; - 4'h1: audc1 <= dataIn; - 4'h2: audf2 <= dataIn; - 4'h3: audc2 <= dataIn; - 4'h4: audf3 <= dataIn; - 4'h5: audc3 <= dataIn; - 4'h6: audf4 <= dataIn; - 4'h7: audc4 <= dataIn; - 4'h8: audCtl <= dataIn; - 4'hB: allPot <= P; - 4'hF: skCtl <= dataIn; - endcase // case (A) - end // else: !if(readHighWriteLow) - end - end - end - - -endmodule: POKEY - -module tristateDriver - #(parameter WIDTH = 8) - ( - input logic [WIDTH-1:0] i, - output logic [WIDTH-1:0] o, - input logic en - ); - - assign o = (en) ? i : ({WIDTH{1'bz}}); - -endmodule: tristateDriver - -module volumeMixer - ( - input logic clk, clr, - input logic [7:0] audc1, audc2, audc3, audc4, - input logic [3:0] digitalWave, - output logic pwmWave - ); - - logic [5:0] volume; - logic [5:0] pwmCnt; - - assign volume = - ((digitalWave[3] | audc4[4]) ? audc4[3:0] : 0) + - ((digitalWave[2] | audc3[4]) ? audc3[3:0] : 0) + - ((digitalWave[1] | audc2[4]) ? audc2[3:0] : 0) + - ((digitalWave[0] | audc1[4]) ? audc1[3:0] : 0); - - m_counter #(6) pwmClk(.Q(pwmCnt), .D(6'd0), .clk(clk), .clr(clr), .load(1'b0), .en(1'b1), .up(1'b1)); - - assign pwmWave = (pwmCnt < volume); - -endmodule: volumeMixer - -module audioChannelDigital - ( - input logic clk, clr, - input logic baseClkWave, - input logic [7:0] audf, audc, - input logic rand4, rand5, rand17, - input logic hpfClk, - input logic [3:0] bypassMask, - output logic rawWave, divOut, noiseOut, arbDiv2Out - ); - - - logic noise; - - logic [3:0] sigIn, sigOut; - - divideByN stage1(.signalIn(sigIn[0]), .clk(clk), .clr(clr), .N(audf), .signalOut(sigOut[0])); - noiseGen rng(.rand4(rand4), .rand5(rand5), .rand17(rand17), .noise(noise), .randSel(audc[7:5])); - randomMixer randMix(.clk(clk), .clr(clr), .randomIn(noise), .signalIn(sigIn[1]), .signalOut(sigOut[1])); - arbDivBy2 adb2(.clk(clk), .clr(clr), .signalIn(sigIn[2]), .signalOut(sigOut[2])); - highPassFilter hpf(.hpfClk(hpfClk), .clk(clk), .clr(clr), .inputSignal(sigIn[3]), .outputSignal(sigOut[3])); - - - assign sigIn[0] = baseClkWave; - assign sigIn[1] = bypassMask[0] ? sigIn[0] : sigOut[0]; - assign sigIn[2] = bypassMask[1] ? sigIn[1] : sigOut[1]; - assign sigIn[3] = bypassMask[2] ? sigIn[2] : sigOut[2]; - assign rawWave = bypassMask[3] ? sigIn[3] : sigOut[3]; - assign divOut = sigOut[0]; - assign noiseOut = sigOut[1]; - assign arbDiv2Out = sigOut[2]; - -endmodule: audioChannelDigital - -module highPassFilter - ( - input logic clk, clr, - input logic hpfClk, - input logic inputSignal, - output logic outputSignal - ); - - logic ffOut; - - m_register #(1) filterReg(.Q(ffOut), .D(inputSignal), .clr(clr), .clk(clk), .en(hpfClk)); - assign outputSignal = (inputSignal ^ ffOut); - -endmodule: highPassFilter - - -module noiseGen - ( - input logic rand4, rand5, rand17, - input logic [2:0] randSel, - output logic noise - ); - - always_comb - begin - casex(randSel) - 3'b000: - begin - noise = rand5 & rand17; - end - 3'b0?1: - begin - noise = rand5; - end - 3'b010: - begin - noise = rand4 & rand5; - end - 3'b100: - begin - noise = rand17; - end - 3'b1?1: - begin - noise = 1'b1; - end - 3'b110: - begin - noise = rand4; - end - default: - begin - noise = 1'b1; - end - endcase // casex (randSel) - - end - - -endmodule: noiseGen - -module edgeDetector - ( - input logic clk, clr, - input logic signal, - output logic edgeFound - ); - - logic prevSignal; - - m_register #(1) edgeRegister(.Q(prevSignal), .D(signal), .clk(clk), .clr(clr), .en(1'b1)); - - assign edgeFound = signal ^ prevSignal; - -endmodule: edgeDetector - - -module divideByN - ( - input logic signalIn, clk, clr, - input logic [7:0] N, - output logic signalOut - ); - - logic [7:0] countOut; - logic rollover, edgeFound; - - edgeDetector edgeChecker(.clk(clk), .clr(clr), .signal(signalIn), .edgeFound(edgeFound)); - m_counter #(8) divCounter(.D(8'd0), .Q(countOut), .clk(clk), .en(edgeFound), .up(1'b1), .clr(clr), .load(rollover)); - m_register #(1) waveTracker(.Q(signalOut), .D(!signalOut), .clk(clk), .en(rollover), .clr(clr)); - - assign rollover = (countOut >= N) & edgeFound; - -endmodule: divideByN - - -module wave15kGen - ( - input logic clk, clr, - output logic wave, pulse - ); - - logic [11:0] parallel15k; - - m_counter #(12) counter15k(.D(12'd0), .Q(parallel15k), .clk(clk), .en(1'b1), .up(1'b1), .clr(clr), .load(pulse)); - m_register #(1) waveTracker(.D(!wave), .Q(wave), .clk(clk), .en(pulse), .clr(clr)); - - assign pulse = (parallel15k == 12'd3333); - -endmodule: wave15kGen - -module wave64kGen - ( - input logic clk, clr, - output logic wave, pulse - ); - - logic [9:0] parallel64k; - - m_counter #(10) counter64k(.D(10'd0), .Q(parallel64k), .clk(clk), .en(1'b1), .up(1'b1), .clr(clr), .load(pulse)); - m_register #(1) waveTracker(.D(!wave), .Q(wave), .clk(clk), .en(pulse), .clr(clr)); - - assign pulse = (parallel64k == 10'd781); - -endmodule: wave64kGen - -module wave179mGen - ( - input logic clk, clr, - output logic wave, pulse - ); - - logic [4:0] parallel179m; - - m_counter #(5) counter64k(.D(5'd0), .Q(parallel179m), .clk(clk), .en(1'b1), .up(1'b1), .clr(clr), .load(pulse)); - m_register #(1) waveTracker(.D(!wave), .Q(wave), .clk(clk), .en(pulse), .clr(clr)); - - assign pulse = (parallel179m == 5'd28); - -endmodule: wave179mGen - - -module polyCounter4 - ( - input logic clk, pulse179m, clr, - output logic rand4 - ); - - logic [3:0] regValue; - logic feedbackVal; - - m_shift_register #(4) polyShifter(.Q(regValue), .clk(clk), .en(pulse179m), .left(1'b0), .s_in(feedbackVal), .clr(clr)); - - assign feedbackVal = !(regValue[3] ^ regValue[2]); - assign rand4 = regValue[3]; - -endmodule: polyCounter4 - - -module polyCounter5 - ( - input logic clk, pulse179m, clr, - output logic rand5 - ); - - logic [4:0] regValue; - logic feedbackVal; - - m_shift_register #(5) polyShifter(.Q(regValue), .clk(clk), .en(pulse179m), .left(1'b1), .s_in(feedbackVal), .clr(clr)); - - assign feedbackVal = !(regValue[4] ^ regValue[2]); - assign rand5 = regValue[4]; - -endmodule: polyCounter5 - - -module polyCounter17 - ( - input logic clk, pulse179m, clr, - input logic reduce9, - output logic rand17, - output logic [7:0] rngVal - ); - - logic [16:0] regValue; - logic feedbackVal; - - m_shift_register #(9) polyShifterUpper(.Q(regValue[16:8]), .clk(clk), .en(pulse179m), .left(1'b1), .s_in(reduce9 ? feedbackVal : regValue[7]), .clr(clr)); - m_shift_register #(8) polyShifterLower(.Q(regValue[7:0]), .clk(clk), .en(pulse179m), .left(1'b1), .s_in(feedbackVal), .clr(clr)); - - assign feedbackVal = !(regValue[16] ^ regValue[11]); - assign rand17 = regValue[16]; - assign rngVal = regValue[16:9]; - -endmodule: polyCounter17 - -module volumeControl - ( - input logic clk, clr, - input logic signalIn, - input logic [3:0] volume, - input logic dcVolume, - output logic signalOut - ); - - logic [3:0] pwmCount; - logic pwmOn; - - m_counter #(4) pwmTimer(.Q(pwmCount), .D(4'h0), .clk(clk), .clr(clr), .load(1'b0), .en(1'b1), .up(1'b1)); - - assign pwmOn = (pwmCount <= volume); - - assign signalOut = dcVolume ? pwmOn : (pwmOn & signalIn); - - -endmodule: volumeControl - -module risingDetector - ( - input logic clk, clr, - input logic signalIn, - output logic risingEdge - ); - - logic prevSignal; - - m_register #(1) risingRegister(.Q(prevSignal), .D(signalIn), .en(1'b1), .clk(clk), .clr(clr)); - assign risingEdge = signalIn & ~prevSignal; - -endmodule: risingDetector - -module randomMixer - ( - input logic clk, clr, - input logic signalIn, - input logic randomIn, - output logic signalOut - ); - - logic risingEdge; - - logic waveWideRandom; - - //This instance name made sense at 4AM when I typed it - risingDetector rayfall(.clk(clk), .clr(clr), .signalIn(signalIn), .risingEdge(risingEdge)); - - m_register #(1) randomCapture(.Q(waveWideRandom), .D(randomIn), .en(risingEdge), .clk(clk), .clr(clr)); - - assign signalOut = signalIn & waveWideRandom; - -endmodule: randomMixer - -module arbDivBy2 - ( - input logic clk, clr, - input logic signalIn, - output logic signalOut - ); - - logic risingEdge; - - risingDetector risingCheck(.clk(clk), .clr(clr), .signalIn(signalIn), .risingEdge(risingEdge)); - - m_register #(1) waveTracker(.Q(signalOut), .D(~signalOut), .en(risingEdge), .clk(clk), .clr(clr)); - -endmodule: arbDivBy2 - - - diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Pokey/matoro.sv b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Pokey/matoro.sv deleted file mode 100644 index c647dc1f..00000000 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Pokey/matoro.sv +++ /dev/null @@ -1,129 +0,0 @@ -`timescale 1ns / 1ps -module m_range_check - #(parameter WIDTH = 6) - (input logic [WIDTH-1:0] val, low, high, - output logic is_between); - - logic smallEnough, largeEnough; - - m_comparator #(WIDTH) lc(,,largeEnough, low, val); - m_comparator #(WIDTH) hc(,,smallEnough, val, high); - - assign is_between = ~smallEnough & ~largeEnough; - -endmodule: m_range_check - -module m_offset_check - #(parameter WIDTH = 6) - (input logic [WIDTH-1:0] val, low, delta, - output logic is_between); - - logic [WIDTH-1:0] high; - - m_adder #(WIDTH) add(high,, low, delta, 1'b0); - m_range_check #(WIDTH) rc(.*); - -endmodule: m_offset_check - -module m_comparator - #(parameter WIDTH = 6) - (output logic AltB, AeqB, AgtB, - input logic [WIDTH-1:0] A, B); - - assign AltB = (A < B); - assign AeqB = (A == B); - assign AgtB = (A > B); - -endmodule: m_comparator - -module m_adder - #(parameter WIDTH = 6) - (output logic [WIDTH-1:0] Sum, - output logic Cout, - input logic [WIDTH-1:0] A, B, - input logic Cin); - - assign {Cout, Sum} = A + B + Cin; - -endmodule: m_adder - -module m_mux - #(parameter WIDTH = 6) - (output logic Y, - input logic [WIDTH-1:0] I, - input logic [$clog2(WIDTH)-1:0] Sel); - - assign Y = I[Sel]; - -endmodule: m_mux - -module m_mux2to1 - #(parameter WIDTH = 6) - (output logic [WIDTH-1:0] Y, - input logic [WIDTH-1:0] I0, I1, - input logic Sel); - - assign Y = (Sel ? I1 : I0); - -endmodule: m_mux2to1 - -module m_decoder - #(parameter WIDTH = 6) - (output logic [(1 << WIDTH)-1:0] D, - input logic [WIDTH-1:0] I, - input logic en); - - assign D = en << I; - -endmodule: m_decoder - -module m_register - #(parameter WIDTH = 6) - (output logic [WIDTH-1:0] Q, - input logic [WIDTH-1:0] D, - input logic clr, en, clk); - - always_ff @(posedge clk) - if(clr) - Q <= 0; - else if(en) - Q <= D; - -endmodule: m_register - -module m_counter - #(parameter WIDTH = 6) - (output logic [WIDTH-1:0] Q, - input logic [WIDTH-1:0] D, - input logic clk, clr, load, en, up); - - always_ff @(posedge clk) begin - if(clr) - Q <= 0; - else if(load) - Q <= D; - else if(en) - Q <= (up ? Q + 1 : Q - 1); - end -endmodule: m_counter - -module m_shift_register - #(parameter WIDTH = 6) - (output logic [WIDTH-1:0] Q, - input logic clk, en, left, s_in, clr); - - always_ff @(posedge clk) - if (clr) begin - Q <= 'd0; - end - else if(en) begin - if(left) begin - Q <= (Q << 1); - Q[0] <= s_in; - end - else begin - Q <= (Q >> 1); - Q[WIDTH-1] <= s_in; - end - end -endmodule: m_shift_register diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65.vhd b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65.vhd deleted file mode 100644 index 09253fe0..00000000 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65.vhd +++ /dev/null @@ -1,564 +0,0 @@ --- **** --- T65(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 more merging --- Ver 300 Bugfixes by ehenciak added, started tidyup *bust* --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 65xx compatible microprocessor core --- --- Version : 0246 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t65/ --- --- Limitations : --- --- 65C02 and 65C816 modes are incomplete --- Undocumented instructions are not supported --- Some interface signals behaves incorrect --- --- File history : --- --- 0246 : First release --- - -library IEEE; - use IEEE.std_logic_1164.all; - use IEEE.numeric_std.all; - use work.T65_Pack.all; - --- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use --- the ready signal to limit the CPU. -entity T65 is - port( - Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 - Res_n : in std_logic; - Enable : in std_logic; - Clk : in std_logic; - Rdy : in std_logic; - Abort_n : in std_logic; - IRQ_n : in std_logic; - NMI_n : in std_logic; - SO_n : in std_logic; - R_W_n : out std_logic; - Sync : out std_logic; - EF : out std_logic; - MF : out std_logic; - XF : out std_logic; - ML_n : out std_logic; - VP_n : out std_logic; - VDA : out std_logic; - VPA : out std_logic; - A : out std_logic_vector(23 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T65; - -architecture rtl of T65 is - - -- Registers - signal ABC, X, Y, D : std_logic_vector(15 downto 0); - signal P, AD, DL : std_logic_vector(7 downto 0) := x"00"; - signal BAH : std_logic_vector(7 downto 0); - signal BAL : std_logic_vector(8 downto 0); - signal PBR : std_logic_vector(7 downto 0); - signal DBR : std_logic_vector(7 downto 0); - signal PC : unsigned(15 downto 0); - signal S : unsigned(15 downto 0); - signal EF_i : std_logic; - signal MF_i : std_logic; - signal XF_i : std_logic; - - signal IR : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - - signal Mode_r : std_logic_vector(1 downto 0); - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Write_Data_r : std_logic_vector(2 downto 0); - signal Set_Addr_To_r : std_logic_vector(1 downto 0); - signal PCAdder : unsigned(8 downto 0); - - signal RstCycle : std_logic; - signal IRQCycle : std_logic; - signal NMICycle : std_logic; - - signal B_o : std_logic; - signal SO_n_o : std_logic; - signal IRQ_n_o : std_logic; - signal NMI_n_o : std_logic; - signal NMIAct : std_logic; - - signal Break : std_logic; - - -- ALU signals - signal BusA : std_logic_vector(7 downto 0); - signal BusA_r : std_logic_vector(7 downto 0); - signal BusB : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal P_Out : std_logic_vector(7 downto 0); - - -- Micro code outputs - signal LCycle : std_logic_vector(2 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(2 downto 0); - signal Set_Addr_To : std_logic_vector(1 downto 0); - signal Write_Data : std_logic_vector(2 downto 0); - signal Jump : std_logic_vector(1 downto 0); - signal BAAdd : std_logic_vector(1 downto 0); - signal BreakAtNA : std_logic; - signal ADAdd : std_logic; - signal AddY : std_logic; - signal PCAdd : std_logic; - signal Inc_S : std_logic; - signal Dec_S : std_logic; - signal LDA : std_logic; - signal LDP : std_logic; - signal LDX : std_logic; - signal LDY : std_logic; - signal LDS : std_logic; - signal LDDI : std_logic; - signal LDALU : std_logic; - signal LDAD : std_logic; - signal LDBAL : std_logic; - signal LDBAH : std_logic; - signal SaveP : std_logic; - signal Write : std_logic; - - signal really_rdy : std_logic; - signal R_W_n_i : std_logic; - -begin - -- ehenciak : gate Rdy with read/write to make an "OK, it's - -- really OK to stop the processor now if Rdy is - -- deasserted" signal - really_rdy <= Rdy or not(R_W_n_i); - - -- ehenciak : Drive R_W_n_i off chip. - R_W_n <= R_W_n_i; - - Sync <= '1' when MCycle = "000" else '0'; - EF <= EF_i; - MF <= MF_i; - XF <= XF_i; - ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1'; - VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1'; - VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!! - VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!! - - mcode : T65_MCode - port map( - Mode => Mode_r, - IR => IR, - MCycle => MCycle, - P => P, - LCycle => LCycle, - ALU_Op => ALU_Op, - Set_BusA_To => Set_BusA_To, - Set_Addr_To => Set_Addr_To, - Write_Data => Write_Data, - Jump => Jump, - BAAdd => BAAdd, - BreakAtNA => BreakAtNA, - ADAdd => ADAdd, - AddY => AddY, - PCAdd => PCAdd, - Inc_S => Inc_S, - Dec_S => Dec_S, - LDA => LDA, - LDP => LDP, - LDX => LDX, - LDY => LDY, - LDS => LDS, - LDDI => LDDI, - LDALU => LDALU, - LDAD => LDAD, - LDBAL => LDBAL, - LDBAH => LDBAH, - SaveP => SaveP, - Write => Write - ); - - alu : T65_ALU - port map( - Mode => Mode_r, - Op => ALU_Op_r, - BusA => BusA_r, - BusB => BusB, - P_In => P, - P_Out => P_Out, - Q => ALU_Q - ); - - process (Res_n, Clk) - begin - if Res_n = '0' then - PC <= (others => '0'); -- Program Counter - IR <= "00000000"; - S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!! - D <= (others => '0'); - PBR <= (others => '0'); - DBR <= (others => '0'); - - Mode_r <= (others => '0'); - ALU_Op_r <= "1100"; - Write_Data_r <= "000"; - Set_Addr_To_r <= "00"; - - R_W_n_i <= '1'; - EF_i <= '1'; - MF_i <= '1'; - XF_i <= '1'; - - elsif Clk'event and Clk = '1' then - if (Enable = '1') then - if (really_rdy = '1') then - R_W_n_i <= not Write or RstCycle; - - D <= (others => '1'); -- Dummy - PBR <= (others => '1'); -- Dummy - DBR <= (others => '1'); -- Dummy - EF_i <= '0'; -- Dummy - MF_i <= '0'; -- Dummy - XF_i <= '0'; -- Dummy - - if MCycle = "000" then - Mode_r <= Mode; - - if IRQCycle = '0' and NMICycle = '0' then - PC <= PC + 1; - end if; - - if IRQCycle = '1' or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DI; - end if; - end if; - - ALU_Op_r <= ALU_Op; - Write_Data_r <= Write_Data; - if Break = '1' then - Set_Addr_To_r <= "00"; - else - Set_Addr_To_r <= Set_Addr_To; - end if; - - if Inc_S = '1' then - S <= S + 1; - end if; - if Dec_S = '1' and RstCycle = '0' then - S <= S - 1; - end if; - if LDS = '1' then - S(7 downto 0) <= unsigned(ALU_Q); - end if; - - if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then - PC <= PC + 1; - end if; - -- - -- jump control logic - -- - case Jump is - when "01" => - PC <= PC + 1; - - when "10" => - PC <= unsigned(DI & DL); - - when "11" => - if PCAdder(8) = '1' then - if DL(7) = '0' then - PC(15 downto 8) <= PC(15 downto 8) + 1; - else - PC(15 downto 8) <= PC(15 downto 8) - 1; - end if; - end if; - PC(7 downto 0) <= PCAdder(7 downto 0); - - when others => null; - end case; - end if; - end if; - end if; - end process; - - PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1' - else "0" & PC(7 downto 0); - - process (Clk) - begin - if Clk'event and Clk = '1' then - if (Enable = '1') then - if (really_rdy = '1') then - if MCycle = "000" then - if LDA = '1' then - ABC(7 downto 0) <= ALU_Q; - end if; - if LDX = '1' then - X(7 downto 0) <= ALU_Q; - end if; - if LDY = '1' then - Y(7 downto 0) <= ALU_Q; - end if; - if (LDA or LDX or LDY) = '1' then - P <= P_Out; - end if; - end if; - if SaveP = '1' then - P <= P_Out; - end if; - if LDP = '1' then - P <= ALU_Q; - end if; - if IR(4 downto 0) = "11000" then - case IR(7 downto 5) is - when "000" => - P(Flag_C) <= '0'; - when "001" => - P(Flag_C) <= '1'; - when "010" => - P(Flag_I) <= '0'; - when "011" => - P(Flag_I) <= '1'; - when "101" => - P(Flag_V) <= '0'; - when "110" => - P(Flag_D) <= '0'; - when "111" => - P(Flag_D) <= '1'; - when others => - end case; - end if; - - --if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then - -- P(Flag_B) <= '1'; - --end if; - --if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then - -- P(Flag_I) <= '1'; - -- P(Flag_B) <= B_o; - --end if; - - -- B=1 always on the 6502 - P(Flag_B) <= '1'; - if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then - if MCycle = "011" then - -- B=0 in *copy* of P pushed onto the stack - P(Flag_B) <= '0'; - elsif MCycle = "100" then - P(Flag_I) <= '1'; - end if; - end if; - - if SO_n_o = '1' and SO_n = '0' then - P(Flag_V) <= '1'; - end if; - if RstCycle = '1' and Mode_r /= "00" then - P(Flag_1) <= '1'; - P(Flag_D) <= '0'; - P(Flag_I) <= '1'; - end if; - P(Flag_1) <= '1'; - - B_o <= P(Flag_B); - SO_n_o <= SO_n; - IRQ_n_o <= IRQ_n; - NMI_n_o <= NMI_n; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - - process (Res_n, Clk) - begin - if Res_n = '0' then - BusA_r <= (others => '0'); - BusB <= (others => '0'); - AD <= (others => '0'); - BAL <= (others => '0'); - BAH <= (others => '0'); - DL <= (others => '0'); - elsif Clk'event and Clk = '1' then - if (Enable = '1') then - if (Rdy = '1') then - BusA_r <= BusA; - BusB <= DI; - - case BAAdd is - when "01" => - -- BA Inc - AD <= std_logic_vector(unsigned(AD) + 1); - BAL <= std_logic_vector(unsigned(BAL) + 1); - when "10" => - -- BA Add - BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9)); - when "11" => - -- BA Adj - if BAL(8) = '1' then - BAH <= std_logic_vector(unsigned(BAH) + 1); - end if; - when others => - end case; - - -- ehenciak : modified to use Y register as well (bugfix) - if ADAdd = '1' then - if (AddY = '1') then - AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0))); - else - AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0))); - end if; - end if; - - if IR = "00000000" then - BAL <= (others => '1'); - BAH <= (others => '1'); - if RstCycle = '1' then - BAL(2 downto 0) <= "100"; - elsif NMICycle = '1' then - BAL(2 downto 0) <= "010"; - else - BAL(2 downto 0) <= "110"; - end if; - if Set_addr_To_r = "11" then - BAL(0) <= '1'; - end if; - end if; - - - if LDDI = '1' then - DL <= DI; - end if; - if LDALU = '1' then - DL <= ALU_Q; - end if; - if LDAD = '1' then - AD <= DI; - end if; - if LDBAL = '1' then - BAL(7 downto 0) <= DI; - end if; - if LDBAH = '1' then - BAH <= DI; - end if; - end if; - end if; - end if; - end process; - - Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8)); - - - with Set_BusA_To select - BusA <= DI when "000", - ABC(7 downto 0) when "001", - X(7 downto 0) when "010", - Y(7 downto 0) when "011", - std_logic_vector(S(7 downto 0)) when "100", - P when "101", - (others => '-') when others; - - with Set_Addr_To_r select - A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01", - DBR & "00000000" & AD when "10", - "00000000" & BAH & BAL(7 downto 0) when "11", - PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others; - - with Write_Data_r select - DO <= DL when "000", - ABC(7 downto 0) when "001", - X(7 downto 0) when "010", - Y(7 downto 0) when "011", - std_logic_vector(S(7 downto 0)) when "100", - P when "101", - std_logic_vector(PC(7 downto 0)) when "110", - std_logic_vector(PC(15 downto 8)) when others; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - - process (Res_n, Clk) - begin - if Res_n = '0' then - MCycle <= "001"; - RstCycle <= '1'; - IRQCycle <= '0'; - NMICycle <= '0'; - NMIAct <= '0'; - elsif Clk'event and Clk = '1' then - if (Enable = '1') then - if (really_rdy = '1') then - if MCycle = LCycle or Break = '1' then - MCycle <= "000"; - RstCycle <= '0'; - IRQCycle <= '0'; - NMICycle <= '0'; - if NMIAct = '1' then - NMICycle <= '1'; - elsif IRQ_n_o = '0' and P(Flag_I) = '0' then - IRQCycle <= '1'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - - if NMICycle = '1' then - NMIAct <= '0'; - end if; - if NMI_n_o = '1' and NMI_n = '0' then - NMIAct <= '1'; - end if; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65_ALU.vhd b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65_ALU.vhd deleted file mode 100644 index b1f6d632..00000000 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65_ALU.vhd +++ /dev/null @@ -1,260 +0,0 @@ --- **** --- T65(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 Bugfixes by ehenciak added --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 6502 compatible microprocessor core --- --- Version : 0245 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t65/ --- --- Limitations : --- --- File history : --- --- 0245 : First version --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T65_Pack.all; - -entity T65_ALU is - port( - Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 - Op : in std_logic_vector(3 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - P_In : in std_logic_vector(7 downto 0); - P_Out : out std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0) - ); -end T65_ALU; - -architecture rtl of T65_ALU is - - -- AddSub variables (temporary signals) - signal ADC_Z : std_logic; - signal ADC_C : std_logic; - signal ADC_V : std_logic; - signal ADC_N : std_logic; - signal ADC_Q : std_logic_vector(7 downto 0); - signal SBC_Z : std_logic; - signal SBC_C : std_logic; - signal SBC_V : std_logic; - signal SBC_N : std_logic; - signal SBC_Q : std_logic_vector(7 downto 0); - -begin - - process (P_In, BusA, BusB) - variable AL : unsigned(6 downto 0); - variable AH : unsigned(6 downto 0); - variable C : std_logic; - begin - AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7); - AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); - --- pragma translate_off - if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; - if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; --- pragma translate_on - - if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then - ADC_Z <= '1'; - else - ADC_Z <= '0'; - end if; - - if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then - AL(6 downto 1) := AL(6 downto 1) + 6; - end if; - - C := AL(6) or AL(5); - AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); - - ADC_N <= AH(4); - ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7)); - --- pragma translate_off - if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; --- pragma translate_on - - if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then - AH(6 downto 1) := AH(6 downto 1) + 6; - end if; - - ADC_C <= AH(6) or AH(5); - - ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); - end process; - - process (Op, P_In, BusA, BusB) - variable AL : unsigned(6 downto 0); - variable AH : unsigned(5 downto 0); - variable C : std_logic; - begin - C := P_In(Flag_C) or not Op(0); - AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6); - AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6); - --- pragma translate_off - if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; - if is_x(std_logic_vector(AH)) then AH := "000000"; end if; --- pragma translate_on - - if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then - SBC_Z <= '1'; - else - SBC_Z <= '0'; - end if; - - SBC_C <= not AH(5); - SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7)); - SBC_N <= AH(4); - - if P_In(Flag_D) = '1' then - if AL(5) = '1' then - AL(5 downto 1) := AL(5 downto 1) - 6; - end if; - AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6); - if AH(5) = '1' then - AH(5 downto 1) := AH(5 downto 1) - 6; - end if; - end if; - - SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); - end process; - - process (Op, P_In, BusA, BusB, - ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q, - SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q) - variable Q_t : std_logic_vector(7 downto 0); - begin - -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC - -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC - P_Out <= P_In; - Q_t := BusA; - case Op(3 downto 0) is - when "0000" => - -- ORA - Q_t := BusA or BusB; - when "0001" => - -- AND - Q_t := BusA and BusB; - when "0010" => - -- EOR - Q_t := BusA xor BusB; - when "0011" => - -- ADC - P_Out(Flag_V) <= ADC_V; - P_Out(Flag_C) <= ADC_C; - Q_t := ADC_Q; - when "0101" | "1101" => - -- LDA - when "0110" => - -- CMP - P_Out(Flag_C) <= SBC_C; - when "0111" => - -- SBC - P_Out(Flag_V) <= SBC_V; - P_Out(Flag_C) <= SBC_C; - Q_t := SBC_Q; - when "1000" => - -- ASL - Q_t := BusA(6 downto 0) & "0"; - P_Out(Flag_C) <= BusA(7); - when "1001" => - -- ROL - Q_t := BusA(6 downto 0) & P_In(Flag_C); - P_Out(Flag_C) <= BusA(7); - when "1010" => - -- LSR - Q_t := "0" & BusA(7 downto 1); - P_Out(Flag_C) <= BusA(0); - when "1011" => - -- ROR - Q_t := P_In(Flag_C) & BusA(7 downto 1); - P_Out(Flag_C) <= BusA(0); - when "1100" => - -- BIT - P_Out(Flag_V) <= BusB(6); - when "1110" => - -- DEC - Q_t := std_logic_vector(unsigned(BusA) - 1); - when "1111" => - -- INC - Q_t := std_logic_vector(unsigned(BusA) + 1); - when others => - end case; - - case Op(3 downto 0) is - when "0011" => - P_Out(Flag_N) <= ADC_N; - P_Out(Flag_Z) <= ADC_Z; - when "0110" | "0111" => - P_Out(Flag_N) <= SBC_N; - P_Out(Flag_Z) <= SBC_Z; - when "0100" => - when "1100" => - P_Out(Flag_N) <= BusB(7); - if (BusA and BusB) = "00000000" then - P_Out(Flag_Z) <= '1'; - else - P_Out(Flag_Z) <= '0'; - end if; - when others => - P_Out(Flag_N) <= Q_t(7); - if Q_t = "00000000" then - P_Out(Flag_Z) <= '1'; - else - P_Out(Flag_Z) <= '0'; - end if; - end case; - - Q <= Q_t; - end process; - -end; diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65_MCode.vhd b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65_MCode.vhd deleted file mode 100644 index 6c6c864a..00000000 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65_MCode.vhd +++ /dev/null @@ -1,1052 +0,0 @@ --- **** --- T65(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 302 minor timing fixes --- Ver 301 Jump timing fixed --- Ver 300 Bugfixes by ehenciak added --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 65xx compatible microprocessor core --- --- Version : 0246 + fix --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t65/ --- --- Limitations : --- --- 65C02 --- supported : inc, dec, phx, plx, phy, ply --- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8 --- --- File history : --- --- 0246 : First release --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T65_Pack.all; - -entity T65_MCode is - port( - Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 - IR : in std_logic_vector(7 downto 0); - MCycle : in std_logic_vector(2 downto 0); - P : in std_logic_vector(7 downto 0); - LCycle : out std_logic_vector(2 downto 0); - ALU_Op : out std_logic_vector(3 downto 0); - Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P - Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA - Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH - Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel - BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj - BreakAtNA : out std_logic; - ADAdd : out std_logic; - AddY : out std_logic; - PCAdd : out std_logic; - Inc_S : out std_logic; - Dec_S : out std_logic; - LDA : out std_logic; - LDP : out std_logic; - LDX : out std_logic; - LDY : out std_logic; - LDS : out std_logic; - LDDI : out std_logic; - LDALU : out std_logic; - LDAD : out std_logic; - LDBAL : out std_logic; - LDBAH : out std_logic; - SaveP : out std_logic; - Write : out std_logic - ); -end T65_MCode; - -architecture rtl of T65_MCode is - - signal Branch : std_logic; - -begin - - with IR(7 downto 5) select - Branch <= not P(Flag_N) when "000", - P(Flag_N) when "001", - not P(Flag_V) when "010", - P(Flag_V) when "011", - not P(Flag_C) when "100", - P(Flag_C) when "101", - not P(Flag_Z) when "110", - P(Flag_Z) when others; - - process (IR, MCycle, P, Branch, Mode) - begin - LCycle <= "001"; - Set_BusA_To <= "001"; -- A - Set_Addr_To <= (others => '0'); - Write_Data <= (others => '0'); - Jump <= (others => '0'); - BAAdd <= "00"; - BreakAtNA <= '0'; - ADAdd <= '0'; - PCAdd <= '0'; - Inc_S <= '0'; - Dec_S <= '0'; - LDA <= '0'; - LDP <= '0'; - LDX <= '0'; - LDY <= '0'; - LDS <= '0'; - LDDI <= '0'; - LDALU <= '0'; - LDAD <= '0'; - LDBAL <= '0'; - LDBAH <= '0'; - SaveP <= '0'; - Write <= '0'; - AddY <= '0'; - - case IR(7 downto 5) is - when "100" => - --{{{ - case IR(1 downto 0) is - when "00" => - Set_BusA_To <= "011"; -- Y - Write_Data <= "011"; -- Y - when "10" => - Set_BusA_To <= "010"; -- X - Write_Data <= "010"; -- X - when others => - Write_Data <= "001"; -- A - end case; - --}}} - when "101" => - --{{{ - case IR(1 downto 0) is - when "00" => - if IR(4) /= '1' or IR(2) /= '0' then - LDY <= '1'; - end if; - when "10" => - LDX <= '1'; - when others => - LDA <= '1'; - end case; - Set_BusA_To <= "000"; -- DI - --}}} - when "110" => - --{{{ - case IR(1 downto 0) is - when "00" => - if IR(4) = '0' then - LDY <= '1'; - end if; - Set_BusA_To <= "011"; -- Y - when others => - Set_BusA_To <= "001"; -- A - end case; - --}}} - when "111" => - --{{{ - case IR(1 downto 0) is - when "00" => - if IR(4) = '0' then - LDX <= '1'; - end if; - Set_BusA_To <= "010"; -- X - when others => - Set_BusA_To <= "001"; -- A - end case; - --}}} - when others => - end case; - - if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then - Set_BusA_To <= "000"; -- DI - end if; - - case IR(4 downto 0) is - when "00000" | "01000" | "01010" | "11000" | "11010" => - --{{{ - -- Implied - case IR is - when "00000000" => - -- BRK - LCycle <= "110"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= "01"; -- S - Write_Data <= "111"; -- PCH - Write <= '1'; - when 2 => - Dec_S <= '1'; - Set_Addr_To <= "01"; -- S - Write_Data <= "110"; -- PCL - Write <= '1'; - when 3 => - Dec_S <= '1'; - Set_Addr_To <= "01"; -- S - Write_Data <= "101"; -- P - Write <= '1'; - when 4 => - Dec_S <= '1'; - Set_Addr_To <= "11"; -- BA - when 5 => - LDDI <= '1'; - Set_Addr_To <= "11"; -- BA - when 6 => - Jump <= "10"; -- DIDL - when others => - end case; - when "00100000" => - -- JSR - LCycle <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Jump <= "01"; - LDDI <= '1'; - Set_Addr_To <= "01"; -- S - when 2 => - Set_Addr_To <= "01"; -- S - Write_Data <= "111"; -- PCH - Write <= '1'; - when 3 => - Dec_S <= '1'; - Set_Addr_To <= "01"; -- S - Write_Data <= "110"; -- PCL - Write <= '1'; - when 4 => - Dec_S <= '1'; - when 5 => - Jump <= "10"; -- DIDL - when others => - end case; - when "01000000" => - -- RTI - LCycle <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= "01"; -- S - when 2 => - Inc_S <= '1'; - Set_Addr_To <= "01"; -- S - when 3 => - Inc_S <= '1'; - Set_Addr_To <= "01"; -- S - Set_BusA_To <= "000"; -- DI - when 4 => - LDP <= '1'; - Inc_S <= '1'; - LDDI <= '1'; - Set_Addr_To <= "01"; -- S - when 5 => - Jump <= "10"; -- DIDL - when others => - end case; - when "01100000" => - -- RTS - LCycle <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= "01"; -- S - when 2 => - Inc_S <= '1'; - Set_Addr_To <= "01"; -- S - when 3 => - Inc_S <= '1'; - LDDI <= '1'; - Set_Addr_To <= "01"; -- S - when 4 => - Jump <= "10"; -- DIDL - when 5 => - Jump <= "01"; - when others => - end case; - when "00001000" | "01001000" | "01011010" | "11011010" => - -- PHP, PHA, PHY*, PHX* - LCycle <= "010"; - if Mode = "00" and IR(1) = '1' then - LCycle <= "001"; - end if; - case to_integer(unsigned(MCycle)) is - when 1 => - case IR(7 downto 4) is - when "0000" => - Write_Data <= "101"; -- P - when "0100" => - Write_Data <= "001"; -- A - when "0101" => - Write_Data <= "011"; -- Y - when "1101" => - Write_Data <= "010"; -- X - when others => - end case; - Write <= '1'; - Set_Addr_To <= "01"; -- S - when 2 => - Dec_S <= '1'; - when others => - end case; - when "00101000" | "01101000" | "01111010" | "11111010" => - -- PLP, PLA, PLY*, PLX* - LCycle <= "011"; - if Mode = "00" and IR(1) = '1' then - LCycle <= "001"; - end if; - case IR(7 downto 4) is - when "0010" => - LDP <= '1'; - when "0110" => - LDA <= '1'; - when "0111" => - if Mode /= "00" then - LDY <= '1'; - end if; - when "1111" => - if Mode /= "00" then - LDX <= '1'; - end if; - when others => - end case; - case to_integer(unsigned(MCycle)) is - when 0 => - SaveP <= '1'; - when 1 => - Set_Addr_To <= "01"; -- S - when 2 => - Inc_S <= '1'; - Set_Addr_To <= "01"; -- S - when 3 => - Set_BusA_To <= "000"; -- DI - when others => - end case; - when "10100000" | "11000000" | "11100000" => - -- LDY, CPY, CPX - -- Immediate - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - Jump <= "01"; - when others => - end case; - when "10001000" => - -- DEY - LDY <= '1'; - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - Set_BusA_To <= "011"; -- Y - when others => - end case; - when "11001010" => - -- DEX - LDX <= '1'; - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - Set_BusA_To <= "010"; -- X - when others => - end case; - when "00011010" | "00111010" => - -- INC*, DEC* - if Mode /= "00" then - LDA <= '1'; -- A - end if; - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - Set_BusA_To <= "100"; -- S - when others => - end case; - when "00001010" | "00101010" | "01001010" | "01101010" => - -- ASL, ROL, LSR, ROR - LDA <= '1'; -- A - Set_BusA_To <= "001"; -- A - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - when others => - end case; - when "10001010" | "10011000" => - -- TYA, TXA - LDA <= '1'; -- A - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - when others => - end case; - when "10101010" | "10101000" => - -- TAX, TAY - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - Set_BusA_To <= "001"; -- A - when others => - end case; - when "10011010" => - -- TXS - case to_integer(unsigned(MCycle)) is - when 0 => - LDS <= '1'; - when 1 => - when others => - end case; - when "10111010" => - -- TSX - LDX <= '1'; - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - Set_BusA_To <= "100"; -- S - when others => - end case; - - -- when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" => - -- -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX - -- case to_integer(unsigned(MCycle)) is - -- when 1 => - -- when others => - -- end case; - when others => - case to_integer(unsigned(MCycle)) is - when 0 => - when others => - end case; - end case; - --}}} - - when "00001" | "00011" => - --{{{ - -- Zero Page Indexed Indirect (d,x) - LCycle <= "101"; - if IR(7 downto 6) /= "10" then - LDA <= '1'; - end if; - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - Jump <= "01"; - LDAD <= '1'; - Set_Addr_To <= "10"; -- AD - when 2 => - ADAdd <= '1'; - Set_Addr_To <= "10"; -- AD - when 3 => - BAAdd <= "01"; -- DB Inc - LDBAL <= '1'; - Set_Addr_To <= "10"; -- AD - when 4 => - LDBAH <= '1'; - if IR(7 downto 5) = "100" then - Write <= '1'; - end if; - Set_Addr_To <= "11"; -- BA - when 5 => - when others => - end case; - --}}} - - when "01001" | "01011" => - --{{{ - -- Immediate - LDA <= '1'; - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - Jump <= "01"; - when others => - end case; - - --}}} - - when "00010" | "10010" => - --{{{ - -- Immediate, KIL - LDX <= '1'; - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - if IR = "10100010" then - -- LDX - Jump <= "01"; - else - -- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!! - end if; - when others => - end case; - --}}} - - when "00100" => - --{{{ - -- Zero Page - LCycle <= "010"; - case to_integer(unsigned(MCycle)) is - when 0 => - if IR(7 downto 5) = "001" then - SaveP <= '1'; - end if; - when 1 => - Jump <= "01"; - LDAD <= '1'; - if IR(7 downto 5) = "100" then - Write <= '1'; - end if; - Set_Addr_To <= "10"; -- AD - when 2 => - when others => - end case; - --}}} - - when "00101" | "00110" | "00111" => - --{{{ - -- Zero Page - if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then - -- Read-Modify-Write - LCycle <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Jump <= "01"; - LDAD <= '1'; - Set_Addr_To <= "10"; -- AD - when 2 => - LDDI <= '1'; - Write <= '1'; - Set_Addr_To <= "10"; -- AD - when 3 => - LDALU <= '1'; - SaveP <= '1'; - Write <= '1'; - Set_Addr_To <= "10"; -- AD - when 4 => - when others => - end case; - else - LCycle <= "010"; - if IR(7 downto 6) /= "10" then - LDA <= '1'; - end if; - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - Jump <= "01"; - LDAD <= '1'; - if IR(7 downto 5) = "100" then - Write <= '1'; - end if; - Set_Addr_To <= "10"; -- AD - when 2 => - when others => - end case; - end if; - --}}} - - when "01100" => - --{{{ - -- Absolute - if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then - -- JMP - if IR(5) = '0' then - --LCycle <= "011"; - LCycle <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Jump <= "01"; - LDDI <= '1'; - when 2 => - Jump <= "10"; -- DIDL - when others => - end case; - else - --LCycle <= "101"; - LCycle <= "100"; -- mikej - case to_integer(unsigned(MCycle)) is - when 1 => - Jump <= "01"; - LDDI <= '1'; - LDBAL <= '1'; - when 2 => - LDBAH <= '1'; - if Mode /= "00" then - Jump <= "10"; -- DIDL - end if; - if Mode = "00" then - Set_Addr_To <= "11"; -- BA - end if; - when 3 => - LDDI <= '1'; - if Mode = "00" then - Set_Addr_To <= "11"; -- BA - BAAdd <= "01"; -- DB Inc - else - Jump <= "01"; - end if; - when 4 => - Jump <= "10"; -- DIDL - when others => - end case; - end if; - else - LCycle <= "011"; - case to_integer(unsigned(MCycle)) is - when 0 => - if IR(7 downto 5) = "001" then - SaveP <= '1'; - end if; - when 1 => - Jump <= "01"; - LDBAL <= '1'; - when 2 => - Jump <= "01"; - LDBAH <= '1'; - if IR(7 downto 5) = "100" then - Write <= '1'; - end if; - Set_Addr_To <= "11"; -- BA - when 3 => - when others => - end case; - end if; - --}}} - - when "01101" | "01110" | "01111" => - --{{{ - -- Absolute - if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then - -- Read-Modify-Write - LCycle <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Jump <= "01"; - LDBAL <= '1'; - when 2 => - Jump <= "01"; - LDBAH <= '1'; - Set_Addr_To <= "11"; -- BA - when 3 => - LDDI <= '1'; - Write <= '1'; - Set_Addr_To <= "11"; -- BA - when 4 => - Write <= '1'; - LDALU <= '1'; - SaveP <= '1'; - Set_Addr_To <= "11"; -- BA - when 5 => - SaveP <= '0'; -- MIKEJ was 1 - when others => - end case; - else - LCycle <= "011"; - if IR(7 downto 6) /= "10" then - LDA <= '1'; - end if; - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - Jump <= "01"; - LDBAL <= '1'; - when 2 => - Jump <= "01"; - LDBAH <= '1'; - if IR(7 downto 5) = "100" then - Write <= '1'; - end if; - Set_Addr_To <= "11"; -- BA - when 3 => - when others => - end case; - end if; - --}}} - - when "10000" => - --{{{ - -- Relative - - -- This circuit dictates when the last - -- microcycle occurs for the branch depending on - -- whether or not the branch is taken and if a page - -- is crossed... - if (Branch = '1') then - - LCycle <= "011"; -- We're done @ T3 if branching...upper - -- level logic will stop at T2 if no page cross - -- (See the Break signal) - else - - LCycle <= "001"; - - end if; - - -- This decodes the current microcycle and takes the - -- proper course of action... - case to_integer(unsigned(MCycle)) is - - -- On the T1 microcycle, increment the program counter - -- and instruct the upper level logic to fetch the offset - -- from the Din bus and store it in the data latches. This - -- will be the last microcycle if the branch isn't taken. - when 1 => - - Jump <= "01"; -- Increments the PC by one (PC will now be PC+2) - -- from microcycle T0. - - LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route - -- the Din bus to the memory data latch (DL) - -- so that the branch offset is fetched. - - -- In microcycle T2, tell the logic in the top level to - -- add the offset. If the most significant byte of the - -- program counter (i.e. the current "page") does not need - -- updating, we are done here...the Break signal at the - -- T65.vhd level takes care of that... - when 2 => - - Jump <= "11"; -- Tell the PC Jump logic to use relative mode. - - PCAdd <= '1'; -- This tells the PC adder to update itself with - -- the current offset recently fetched from - -- memory. - - -- The following is microcycle T3 : - -- The program counter should be completely updated - -- on this cycle after the page cross is detected. - -- We don't need to do anything here... - when 3 => - - - when others => null; -- Do nothing. - - end case; - --}}} - - when "10001" | "10011" => - --{{{ - -- Zero Page Indirect Indexed (d),y - LCycle <= "101"; - if IR(7 downto 6) /= "10" then - LDA <= '1'; - end if; - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - Jump <= "01"; - LDAD <= '1'; - Set_Addr_To <= "10"; -- AD - when 2 => - LDBAL <= '1'; - BAAdd <= "01"; -- DB Inc - Set_Addr_To <= "10"; -- AD - when 3 => - Set_BusA_To <= "011"; -- Y - BAAdd <= "10"; -- BA Add - LDBAH <= '1'; - Set_Addr_To <= "11"; -- BA - when 4 => - BAAdd <= "11"; -- BA Adj - if IR(7 downto 5) = "100" then - Write <= '1'; - else - BreakAtNA <= '1'; - end if; - Set_Addr_To <= "11"; -- BA - when 5 => - when others => - end case; - --}}} - - when "10100" | "10101" | "10110" | "10111" => - --{{{ - -- Zero Page, X - if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then - -- Read-Modify-Write - LCycle <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Jump <= "01"; - LDAD <= '1'; - Set_Addr_To <= "10"; -- AD - when 2 => - ADAdd <= '1'; - Set_Addr_To <= "10"; -- AD - when 3 => - LDDI <= '1'; - Write <= '1'; - Set_Addr_To <= "10"; -- AD - when 4 => - LDALU <= '1'; - SaveP <= '1'; - Write <= '1'; - Set_Addr_To <= "10"; -- AD - when 5 => - when others => - end case; - else - LCycle <= "011"; - if IR(7 downto 6) /= "10" then - LDA <= '1'; - end if; - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - Jump <= "01"; - LDAD <= '1'; - Set_Addr_To <= "10"; -- AD - when 2 => - ADAdd <= '1'; - -- Added this check for Y reg. use... - if (IR(3 downto 0) = "0110") then - AddY <= '1'; - end if; - - if IR(7 downto 5) = "100" then - Write <= '1'; - end if; - Set_Addr_To <= "10"; -- AD - when 3 => null; - when others => - end case; - end if; - --}}} - - when "11001" | "11011" => - --{{{ - -- Absolute Y - LCycle <= "100"; - if IR(7 downto 6) /= "10" then - LDA <= '1'; - end if; - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - Jump <= "01"; - LDBAL <= '1'; - when 2 => - Jump <= "01"; - Set_BusA_To <= "011"; -- Y - BAAdd <= "10"; -- BA Add - LDBAH <= '1'; - Set_Addr_To <= "11"; -- BA - when 3 => - BAAdd <= "11"; -- BA adj - if IR(7 downto 5) = "100" then - Write <= '1'; - else - BreakAtNA <= '1'; - end if; - Set_Addr_To <= "11"; -- BA - when 4 => - when others => - end case; - --}}} - - when "11100" | "11101" | "11110" | "11111" => - --{{{ - -- Absolute X - - if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then - -- Read-Modify-Write - LCycle <= "110"; - case to_integer(unsigned(MCycle)) is - when 1 => - Jump <= "01"; - LDBAL <= '1'; - when 2 => - Jump <= "01"; - Set_BusA_To <= "010"; -- X - BAAdd <= "10"; -- BA Add - LDBAH <= '1'; - Set_Addr_To <= "11"; -- BA - when 3 => - BAAdd <= "11"; -- BA adj - Set_Addr_To <= "11"; -- BA - when 4 => - LDDI <= '1'; - Write <= '1'; - Set_Addr_To <= "11"; -- BA - when 5 => - LDALU <= '1'; - SaveP <= '1'; - Write <= '1'; - Set_Addr_To <= "11"; -- BA - when 6 => - when others => - end case; - else - LCycle <= "100"; - if IR(7 downto 6) /= "10" then - LDA <= '1'; - end if; - case to_integer(unsigned(MCycle)) is - when 0 => - when 1 => - Jump <= "01"; - LDBAL <= '1'; - when 2 => - Jump <= "01"; - -- mikej - -- special case 0xBE which uses Y reg as index!! - if (IR = "10111110") then - Set_BusA_To <= "011"; -- Y - else - Set_BusA_To <= "010"; -- X - end if; - BAAdd <= "10"; -- BA Add - LDBAH <= '1'; - Set_Addr_To <= "11"; -- BA - when 3 => - BAAdd <= "11"; -- BA adj - if IR(7 downto 5) = "100" then - Write <= '1'; - else - BreakAtNA <= '1'; - end if; - Set_Addr_To <= "11"; -- BA - when 4 => - when others => - end case; - end if; - --}}} - when others => - end case; - end process; - - process (IR, MCycle) - begin - -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC - -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC - case IR(1 downto 0) is - when "00" => - --{{{ - case IR(4 downto 2) is - when "000" | "001" | "011" => - case IR(7 downto 5) is - when "110" | "111" => - -- CP - ALU_Op <= "0110"; - when "101" => - -- LD - ALU_Op <= "0101"; - when "001" => - -- BIT - ALU_Op <= "1100"; - when others => - -- NOP/ST - ALU_Op <= "0100"; - end case; - when "010" => - case IR(7 downto 5) is - when "111" | "110" => - -- IN - ALU_Op <= "1111"; - when "100" => - -- DEY - ALU_Op <= "1110"; - when others => - -- LD - ALU_Op <= "1101"; - end case; - when "110" => - case IR(7 downto 5) is - when "100" => - -- TYA - ALU_Op <= "1101"; - when others => - ALU_Op <= "----"; - end case; - when others => - case IR(7 downto 5) is - when "101" => - -- LD - ALU_Op <= "1101"; - when others => - ALU_Op <= "0100"; - end case; - end case; - --}}} - when "01" => -- OR - --{{{ - ALU_Op(3) <= '0'; - ALU_Op(2 downto 0) <= IR(7 downto 5); - --}}} - when "10" => - --{{{ - ALU_Op(3) <= '1'; - ALU_Op(2 downto 0) <= IR(7 downto 5); - case IR(7 downto 5) is - when "000" => - if IR(4 downto 2) = "110" then - -- INC - ALU_Op <= "1111"; - end if; - when "001" => - if IR(4 downto 2) = "110" then - -- DEC - ALU_Op <= "1110"; - end if; - when "100" => - if IR(4 downto 2) = "010" then - -- TXA - ALU_Op <= "0101"; - else - ALU_Op <= "0100"; - end if; - when others => - end case; - --}}} - when others => - --{{{ - case IR(7 downto 5) is - when "100" => - ALU_Op <= "0100"; - when others => - if MCycle = "000" then - ALU_Op(3) <= '0'; - ALU_Op(2 downto 0) <= IR(7 downto 5); - else - ALU_Op(3) <= '1'; - ALU_Op(2 downto 0) <= IR(7 downto 5); - end if; - end case; - --}}} - end case; - end process; - -end; diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65_Pack.vhd b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65_Pack.vhd deleted file mode 100644 index e025e1bf..00000000 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65_Pack.vhd +++ /dev/null @@ -1,117 +0,0 @@ --- **** --- T65(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 Bugfixes by ehenciak added --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 65xx compatible microprocessor core --- --- Version : 0246 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t65/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T65_Pack is - - constant Flag_C : integer := 0; - constant Flag_Z : integer := 1; - constant Flag_I : integer := 2; - constant Flag_D : integer := 3; - constant Flag_B : integer := 4; - constant Flag_1 : integer := 5; - constant Flag_V : integer := 6; - constant Flag_N : integer := 7; - - component T65_MCode - port( - Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 - IR : in std_logic_vector(7 downto 0); - MCycle : in std_logic_vector(2 downto 0); - P : in std_logic_vector(7 downto 0); - LCycle : out std_logic_vector(2 downto 0); - ALU_Op : out std_logic_vector(3 downto 0); - Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P - Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA - Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH - Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel - BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj - BreakAtNA : out std_logic; - ADAdd : out std_logic; - AddY : out std_logic; - PCAdd : out std_logic; - Inc_S : out std_logic; - Dec_S : out std_logic; - LDA : out std_logic; - LDP : out std_logic; - LDX : out std_logic; - LDY : out std_logic; - LDS : out std_logic; - LDDI : out std_logic; - LDALU : out std_logic; - LDAD : out std_logic; - LDBAL : out std_logic; - LDBAH : out std_logic; - SaveP : out std_logic; - Write : out std_logic - ); - end component; - - component T65_ALU - port( - Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 - Op : in std_logic_vector(3 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - P_In : in std_logic_vector(7 downto 0); - P_Out : out std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0) - ); - end component; - -end;