From ca0c6feb5f2b5cd671ee4a0d116ca28fcd82713a Mon Sep 17 00:00:00 2001 From: Marcel Date: Thu, 13 Jul 2023 12:03:28 +0200 Subject: [PATCH] Update dual_port_ram.vhd --- Arcade_MiST/Toaplan v1 Hardware/rtl/dual_port_ram.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/dual_port_ram.vhd b/Arcade_MiST/Toaplan v1 Hardware/rtl/dual_port_ram.vhd index e47fb4b2..7e87685c 100644 --- a/Arcade_MiST/Toaplan v1 Hardware/rtl/dual_port_ram.vhd +++ b/Arcade_MiST/Toaplan v1 Hardware/rtl/dual_port_ram.vhd @@ -80,7 +80,7 @@ begin clock_enable_output_a => "BYPASS", clock_enable_output_b => "BYPASS", indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", + intended_device_family => "Cyclone III", lpm_type => "altsyncram", numwords_a => LEN, numwords_b => LEN,