From cabcb08770697c4f747e83bba454fedc1609cb4c Mon Sep 17 00:00:00 2001
From: Gyorgy Szombathelyi <gyurco@freemail.hu>
Date: Tue, 18 Aug 2020 23:07:26 +0200
Subject: [PATCH] Midway8080: update + fix some games

They all work more or less, audio is usually wrong (need custom sound board)
---
 .../280ZZZAP_MiST/280ZZZAP.qsf                |   42 +-
 .../280ZZZAP_MiST/280ZZZAP.sdc                |    2 +-
 .../280ZZZAP_MiST/Snapshot/280ZZZAP.rbf       |  Bin 240973 -> 0 bytes
 .../280ZZZAP_MiST/rtl/D280ZZZAP_memory.sv     |    4 +-
 .../280ZZZAP_MiST/rtl/D280ZZZAP_mist.sv       |  176 +-
 .../280ZZZAP_MiST/rtl/T80/T80.vhd             | 1080 ---------
 .../280ZZZAP_MiST/rtl/T80/T8080se.vhd         |  194 --
 .../280ZZZAP_MiST/rtl/T80/T80_ALU.vhd         |  361 ---
 .../280ZZZAP_MiST/rtl/T80/T80_MCode.vhd       | 1944 -----------------
 .../280ZZZAP_MiST/rtl/T80/T80_Pack.vhd        |  217 --
 .../280ZZZAP_MiST/rtl/T80/T80_Reg.vhd         |  114 -
 .../280ZZZAP_MiST/rtl/invaders.vhd            |   36 +-
 .../280ZZZAP_MiST/rtl/invaders_audio.vhd      |  496 -----
 .../280ZZZAP_MiST/rtl/pll.vhd                 |   30 +-
 .../280ZZZAP_MiST/rtl/spy_hunter_control.vhd  |  160 ++
 .../BalloonBomber_MiST/BalloonBomber.qsf      |   20 +-
 .../BalloonBomber_MiST/BalloonBomber.sdc      |  126 ++
 .../rtl/BalloonBomber_memory.sv               |    2 +-
 .../rtl/BalloonBomber_mist.sv                 |  104 +-
 .../BalloonBomber_MiST/rtl/T80/T80.vhd        | 1080 ---------
 .../BalloonBomber_MiST/rtl/T80/T8080se.vhd    |  194 --
 .../BalloonBomber_MiST/rtl/T80/T80_ALU.vhd    |  361 ---
 .../BalloonBomber_MiST/rtl/T80/T80_MCode.vhd  | 1944 -----------------
 .../BalloonBomber_MiST/rtl/T80/T80_Pack.vhd   |  217 --
 .../BalloonBomber_MiST/rtl/T80/T80_Reg.vhd    |  114 -
 .../BalloonBomber_MiST/rtl/invaders.vhd       |   17 +-
 .../BalloonBomber_MiST/rtl/pll.vhd            |   30 +-
 .../BalloonBomber_MiST/rtl/roms/ballbomb.zip  |  Bin 7424 -> 0 bytes
 .../BalloonBomber_MiST/rtl/roms/tn01          |  Bin 2048 -> 0 bytes
 .../BalloonBomber_MiST/rtl/roms/tn02          |  Bin 2048 -> 0 bytes
 .../BalloonBomber_MiST/rtl/roms/tn03          |  Bin 2048 -> 0 bytes
 .../BalloonBomber_MiST/rtl/roms/tn04          |  Bin 2048 -> 0 bytes
 .../BalloonBomber_MiST/rtl/roms/tn05-1        |  Bin 2048 -> 0 bytes
 .../BalloonBomber_MiST/rtl/roms/tn06          |    1 -
 .../BalloonBomber_MiST/rtl/roms/tn07          |    1 -
 .../BlueShark_MiST/BlueShark.qsf              |   39 +-
 .../BlueShark_MiST/BlueShark.sdc              |    2 +-
 .../BlueShark_MiST/README.txt                 |    2 +-
 .../BlueShark_MiST/Snapshot/BlueShark.rbf     |  Bin 241979 -> 0 bytes
 .../BlueShark_MiST/rtl/BlueShark_mist.sv      |  102 +-
 .../BlueShark_MiST/rtl/T80/T80.vhd            | 1080 ---------
 .../BlueShark_MiST/rtl/T80/T8080se.vhd        |  194 --
 .../BlueShark_MiST/rtl/T80/T80_ALU.vhd        |  361 ---
 .../BlueShark_MiST/rtl/T80/T80_MCode.vhd      | 1944 -----------------
 .../BlueShark_MiST/rtl/T80/T80_Pack.vhd       |  217 --
 .../BlueShark_MiST/rtl/T80/T80_Reg.vhd        |  114 -
 .../BlueShark_MiST/rtl/invaders.vhd           |   35 +-
 .../BlueShark_MiST/rtl/pll.vhd                |   30 +-
 .../BlueShark_MiST/rtl/spinner.vhd            |   49 +
 .../BowlingAlley_MiST/BowlingAlley.qsf        |   33 +-
 .../BowlingAlley_MiST/BowlingAlley.sdc        |    2 +-
 .../Snapshot/BowlingAlley.rbf                 |  Bin 245721 -> 0 bytes
 .../rtl/BowlingAlley_mist.sv                  |  101 +-
 .../BowlingAlley_MiST/rtl/T80/T80.vhd         | 1080 ---------
 .../BowlingAlley_MiST/rtl/T80/T8080se.vhd     |  194 --
 .../BowlingAlley_MiST/rtl/T80/T80_ALU.vhd     |  361 ---
 .../BowlingAlley_MiST/rtl/T80/T80_MCode.vhd   | 1944 -----------------
 .../BowlingAlley_MiST/rtl/T80/T80_Pack.vhd    |  217 --
 .../BowlingAlley_MiST/rtl/T80/T80_Reg.vhd     |  114 -
 .../BowlingAlley_MiST/rtl/dac.vhd             |   48 -
 .../BowlingAlley_MiST/rtl/invaders.vhd        |   29 +-
 .../BowlingAlley_MiST/rtl/pll.vhd             |   30 +-
 .../GunFight_MiST/GunFight.qsf                |   94 +-
 .../GunFight_MiST/GunFight.sdc                |    2 +-
 .../GunFight_MiST/rtl/GunFight_mist.sv        |  110 +-
 .../GunFight_MiST/rtl/T80/T80.vhd             | 1080 ---------
 .../GunFight_MiST/rtl/T80/T8080se.vhd         |  194 --
 .../GunFight_MiST/rtl/T80/T80_ALU.vhd         |  361 ---
 .../GunFight_MiST/rtl/T80/T80_MCode.vhd       | 1944 -----------------
 .../GunFight_MiST/rtl/T80/T80_Pack.vhd        |  217 --
 .../GunFight_MiST/rtl/T80/T80_Reg.vhd         |  114 -
 .../GunFight_MiST/rtl/invaders.vhd            |   67 +-
 .../GunFight_MiST/rtl/pll.vhd                 |   68 +-
 .../Lunar Rescue_MiST/LunarRescue.sdc         |    2 +-
 .../Lunar Rescue_MiST/rtl/LunarRescue_mist.sv |   95 +-
 .../Lunar Rescue_MiST/rtl/pll.vhd             |   68 +-
 .../Space Invaders 2_MiST/Invaders2.qsf       |   32 +-
 .../Space Invaders 2_MiST/Invaders2.sdc       |    2 +-
 .../rtl/Invaders2_mist.sv                     |  110 +-
 .../Space Invaders 2_MiST/rtl/T80/T80.vhd     | 1080 ---------
 .../Space Invaders 2_MiST/rtl/T80/T8080se.vhd |  194 --
 .../Space Invaders 2_MiST/rtl/T80/T80_ALU.vhd |  361 ---
 .../rtl/T80/T80_MCode.vhd                     | 1944 -----------------
 .../rtl/T80/T80_Pack.vhd                      |  217 --
 .../Space Invaders 2_MiST/rtl/T80/T80_Reg.vhd |  114 -
 .../Space Invaders 2_MiST/rtl/dac.vhd         |   48 -
 .../Space Invaders 2_MiST/rtl/invaders.vhd    |   27 +-
 .../Space Invaders 2_MiST/rtl/pll.vhd         |   68 +-
 .../Space Invaders_MiST/SpaceInvaders.qsf     |   35 +-
 .../Space Invaders_MiST/SpaceInvaders.sdc     |    2 +-
 .../Space Invaders_MiST/rtl/T80/T80.vhd       | 1080 ---------
 .../Space Invaders_MiST/rtl/T80/T8080se.vhd   |  194 --
 .../Space Invaders_MiST/rtl/T80/T80_ALU.vhd   |  361 ---
 .../Space Invaders_MiST/rtl/T80/T80_MCode.vhd | 1944 -----------------
 .../Space Invaders_MiST/rtl/T80/T80_Pack.vhd  |  217 --
 .../Space Invaders_MiST/rtl/T80/T80_Reg.vhd   |  114 -
 .../Space Invaders_MiST/rtl/dac.vhd           |   48 -
 .../Space Invaders_MiST/rtl/pll.vhd           |   68 +-
 .../rtl/spaceinvaders_mist.sv                 |   97 +-
 .../SpaceWalk_MiST/SpaceWalk.qsf              |   36 +-
 .../SpaceWalk_MiST/SpaceWalk.sdc              |    2 +-
 .../SpaceWalk_MiST/rtl/SpaceWalk.sv           |  115 +-
 .../SpaceWalk_MiST/rtl/Spacewalk_overlay.vhd  |    4 +-
 .../SpaceWalk_MiST/rtl/T80/T80.vhd            | 1080 ---------
 .../SpaceWalk_MiST/rtl/T80/T8080se.vhd        |  194 --
 .../SpaceWalk_MiST/rtl/T80/T80_ALU.vhd        |  361 ---
 .../SpaceWalk_MiST/rtl/T80/T80_MCode.vhd      | 1944 -----------------
 .../SpaceWalk_MiST/rtl/T80/T80_Pack.vhd       |  217 --
 .../SpaceWalk_MiST/rtl/T80/T80_Reg.vhd        |  114 -
 .../SpaceWalk_MiST/rtl/invaders.vhd           |   28 +-
 .../SpaceWalk_MiST/rtl/pll.vhd                |   30 +-
 .../SpaceWalk_MiST/rtl/spinner.vhd            |   49 +
 .../SuperEarthInvasion.qsf                    |   45 +-
 .../SuperEarthInvasion.sdc                    |    2 +-
 .../rtl/SuperEarthInvasion_mist.sv            |  101 +-
 .../Super Earth Invasion_MiST/rtl/T80/T80.vhd | 1080 ---------
 .../rtl/T80/T8080se.vhd                       |  194 --
 .../rtl/T80/T80_ALU.vhd                       |  361 ---
 .../rtl/T80/T80_MCode.vhd                     | 1944 -----------------
 .../rtl/T80/T80_Pack.vhd                      |  217 --
 .../rtl/T80/T80_Reg.vhd                       |  114 -
 .../Super Earth Invasion_MiST/rtl/dac.vhd     |   48 -
 .../Super Earth Invasion_MiST/rtl/pll.vhd     |   30 +-
 .../Vortex_MiST/Vortex.qsf                    |   43 +-
 .../Vortex_MiST/Vortex.sdc                    |  126 ++
 .../Vortex_MiST/rtl/T80/T80.vhd               | 1080 ---------
 .../Vortex_MiST/rtl/T80/T8080se.vhd           |  194 --
 .../Vortex_MiST/rtl/T80/T80_ALU.vhd           |  361 ---
 .../Vortex_MiST/rtl/T80/T80_MCode.vhd         | 1944 -----------------
 .../Vortex_MiST/rtl/T80/T80_Pack.vhd          |  217 --
 .../Vortex_MiST/rtl/T80/T80_Reg.vhd           |  114 -
 .../Vortex_MiST/rtl/Vortex_mist.sv            |   98 +-
 .../Vortex_MiST/rtl/invaders.vhd              |   11 +-
 .../Vortex_MiST/rtl/pll.vhd                   |   30 +-
 134 files changed, 1801 insertions(+), 40889 deletions(-)
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/Snapshot/280ZZZAP.rbf
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T8080se.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders_audio.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/spy_hunter_control.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.sdc
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T8080se.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/ballbomb.zip
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn01
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn02
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn03
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn04
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn05-1
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/Snapshot/BlueShark.rbf
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T8080se.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Reg.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/spinner.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/Snapshot/BowlingAlley.rbf
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T8080se.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T8080se.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T8080se.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T8080se.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T8080se.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Reg.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/spinner.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T8080se.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/dac.vhd
 create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.sdc
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T8080se.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Reg.vhd

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qsf
index d88d2228..9517fc0c 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qsf	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qsf	
@@ -41,25 +41,9 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/D280ZZZAP_mist.sv
-set_global_assignment -name VHDL_FILE rtl/invaders.vhd
-set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
-set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/D280ZZZAP_memory.sv
-set_global_assignment -name VHDL_FILE rtl/D280ZZZAP_Overlay.vhd
-set_global_assignment -name VHDL_FILE rtl/sprom.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
 
 # Pin & Location Assignments
 # ==========================
@@ -123,7 +107,7 @@ set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
 
 # EDA Netlist Writer Assignments
 # ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
 
 # Assembler Assignments
 # =====================
@@ -147,7 +131,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 	# EDA Netlist Writer Assignments
 	# ==============================
-	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
 
 # end EDA_TOOL_SETTINGS(eda_simulation)
 # -------------------------------------
@@ -163,10 +147,26 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
 	# end DESIGN_PARTITION(Top)
 	# -------------------------
 
 # end ENTITY(D280ZZZAP_mist)
-# --------------------------
\ No newline at end of file
+# --------------------------
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/D280ZZZAP_mist.sv
+set_global_assignment -name VHDL_FILE rtl/spy_hunter_control.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/D280ZZZAP_memory.sv
+set_global_assignment -name VHDL_FILE rtl/D280ZZZAP_Overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.sdc
index f91c127c..11d2c7a9 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.sdc	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.sdc	
@@ -87,7 +87,7 @@ set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [g
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {VGA_*}]
 
 #**************************************************************
 # Set Clock Groups
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/Snapshot/280ZZZAP.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/Snapshot/280ZZZAP.rbf
deleted file mode 100644
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GIT binary patch
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zdGO#^WlQPY%z=Yj4n~Jd!N}#KE(sni1U2{I?mzu2@@~pDgZzdA8*B>lfPGsw<t8)1
zWG)!?k)5AYK~S<|i*u1gjq=NxR2j7X;~`I>s3Piw%H-!C8WT+Vb_cWLr%C3?4CS|M
zvig*rP~kq6O$T#CPHq^3=*r)^=+i!N5T7S&Or0=pYl!tr!i5w&*be|dj^|3W{^Fct
H0}KBjs+AYU

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_memory.sv
index fd2ac6a0..6529e8e1 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_memory.sv	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_memory.sv	
@@ -75,7 +75,7 @@ u_rom_c (
 	.Address(Addr[9:0]),
 	.q(rom_data_5)
 	);
-	
+
 always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5) begin
 	Rom_out = 8'b00000000;
 		case (Addr[15:10])
@@ -89,7 +89,7 @@ always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_d
 			default : Rom_out = 8'b00000000;
 		endcase
 end
-		
+
 spram #(
 	.addr_width_g(13),
 	.data_width_g(8)) 
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_mist.sv
index da613e03..358b10e6 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_mist.sv	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_mist.sv	
@@ -22,35 +22,84 @@ localparam CONF_STR = {
 	"280ZZZAP;;",
 	"O34,Scanlines,Off,25%,50%,75%;",
 	"O5,Overlay, On, Off;",
-	"T6,Reset;",
+	"T0,Reset;",
 	"V,v0.00.",`BUILD_DATE
 };
 
+wire  [1:0] scanlines = status[4:3];
+wire        rotate    = status[2];
+wire        overlay   = status[5];
+
 assign LED = 1;
-assign AUDIO_R = AUDIO_L;
 
-
-wire clk_core, clk_sys;
+wire clk_core, clk_vid;
 wire pll_locked;
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(),
 	.c0(clk_core),
-	.c1(clk_sys)
+	.c1(clk_vid)
 );
+wire        reset = status[0] | buttons[1];
 
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire  [7:0] kbjoy;
 wire  [7:0] joystick_0,joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
+wire        no_csync;
 wire        key_pressed;
 wire  [7:0] key_code;
 wire        key_strobe;
-wire  [7:0] audio;
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_core       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+wire signed [7:0] steering;
+wire signed [7:0] steering_adj = -(steering + 8'h10); // range adjust and negate: 30-b0 -> 40-c0
+wire [7:0] pedal;
+
+spy_hunter_control controls (
+	.clock_40(clk_core),
+	.reset(reset),
+	.vsync(vs),
+	.gas_plus(m_up),
+	.gas_minus(m_down),
+	.steering_plus(m_right),
+	.steering_minus(m_left),
+	.steering(steering),
+	.gas(pedal)
+);
+
+wire       gear;
+input_toggle gear_sw(
+	.clk(clk_core),
+	.reset(reset),
+	.btn(m_fireA),
+	.state(gear)
+);
+
 wire 			hsync,vsync;
 wire 			hs, vs;
 wire 			r,g,b;
@@ -67,6 +116,8 @@ wire RWE_n;
 wire Video;
 wire HSync;
 wire VSync;
+wire  [7:0] audio;
+
 /*
 Dip Switch:E3
 1		2		3		4		5		6		7		8		Function	Option
@@ -96,18 +147,19 @@ Language
 												Off	On		German
 												Off	Off	Spanish
 */
+wire  [8:1] dip = 8'b00111100;
 
 invaderst invaderst(
-	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Rst_n(~reset),
 	.Clk(clk_core),
 	.ENA(),
-	.Coin(btn_coin),
-	.Sel1Player(~btn_one_player),
-	.Sel2Player(~btn_two_players),
-	.Fire(~m_fire),
-	.MoveLeft(~m_left),
-	.MoveRight(~m_right),
-	.DIP("00000000"),
+	.Coin(m_coin1 | m_coin2),
+	.Sel1Player(m_one_player),
+	.Sel2Player(m_two_players),
+	.Fire(gear),
+	.Pedal(pedal[7:4]),
+	.Steering(steering_adj),
+	.DIP(dip),
 	.RDB(RDB),
 	.IB(IB),
 	.RWD(RWD),
@@ -121,7 +173,7 @@ invaderst invaderst(
 	.HSync(HSync),
 	.VSync(VSync)
 	);
-		
+
 D280ZZZAP_memory D280ZZZAP_memory (
 	.Clock(clk_core),
 	.RW_n(RWE_n),
@@ -131,17 +183,10 @@ D280ZZZAP_memory D280ZZZAP_memory (
 	.Ram_in(RWD),
 	.Rom_out(IB)
 	);
-		
-invaders_audio invaders_audio (
-	.Clk(clk_core),
-	.S1(SoundCtrl3),
-	.S2(SoundCtrl5),
-	.Aud(audio)
-	);		
-	  
+
 D280ZZZAP_Overlay D280ZZZAP_Overlay (
 	.Video(Video),
-	.Overlay(~status[5]),
+	.Overlay(~overlay),
 	.CLK(clk_core),
 	.Rst_n_s(Rst_n_s),
 	.HSync(HSync),
@@ -153,14 +198,14 @@ D280ZZZAP_Overlay D280ZZZAP_Overlay (
 	.O_VSYNC(vs)
 	);
 
-mist_video #(.COLOR_DEPTH(3)) mist_video(
-	.clk_sys(clk_sys),
+mist_video #(.COLOR_DEPTH(1)) mist_video(
+	.clk_sys(clk_vid),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({r,r,r}),
-	.G({g,g,g}),
-	.B({b,b,b}),
+	.R(r),
+	.G(g),
+	.B(b),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -169,60 +214,41 @@ mist_video #(.COLOR_DEPTH(3)) mist_video(
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
 	.scandoubler_disable(scandoublerD),
-	.scanlines(status[4:3]),
+	.scanlines(scanlines),
 	.ce_divider(0),
-	.ypbpr(ypbpr)
-	);
-
-user_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-user_io(
-	.clk_sys        (clk_sys       ),
-	.conf_str       (CONF_STR       ),
-	.SPI_CLK        (SPI_SCK        ),
-	.SPI_SS_IO      (CONF_DATA0     ),
-	.SPI_MISO       (SPI_DO         ),
-	.SPI_MOSI       (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches       (switches       ),
-	.scandoubler_disable (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.key_strobe     (key_strobe     ),
-	.key_pressed    (key_pressed    ),
-	.key_code       (key_code       ),
-	.joystick_0     (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
+	.ypbpr(ypbpr),
+	.no_csync(no_csync)
 	);
 
+assign AUDIO_L = 0;
+assign AUDIO_R = 0;
+/*
 dac dac (
-	.clk_i(clk_sys),
+	.clk_i(clk_core),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
+*/
 
-wire m_left   = btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_fire1 = 0;
-reg btn_coin  = 0;
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
 
-always @(posedge clk_sys) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h6B: btn_left        <= key_pressed; // left
-			'h74: btn_right       <= key_pressed; // right
-			'h76: btn_coin        <= key_pressed; // ESC
-			'h05: btn_one_player  <= key_pressed; // F1
-			'h06: btn_two_players <= key_pressed; // F2
-			'h29: btn_fire1       <= key_pressed; // Space
-		endcase
-	end
-end
+arcade_inputs inputs (
+	.clk         ( clk_core    ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b00       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index da01f6b4..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1080 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in  std_logic;
-		CLK_n           : in  std_logic;
-		CEN             : in  std_logic;
-		WAIT_n          : in  std_logic;
-		INT_n           : in  std_logic;
-		NMI_n           : in  std_logic;
-		BUSRQ_n         : in  std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A               : out std_logic_vector(15 downto 0);
-		DInst           : in  std_logic_vector(7 downto 0);
-		DI              : in  std_logic_vector(7 downto 0);
-		DO              : out std_logic_vector(7 downto 0);
-		MC              : out std_logic_vector(2 downto 0);
-		TS              : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone              : std_logic_vector(2 downto 0) := "111";
-	constant aBC                : std_logic_vector(2 downto 0) := "000";
-	constant aDE                : std_logic_vector(2 downto 0) := "001";
-	constant aXY                : std_logic_vector(2 downto 0) := "010";
-	constant aIOA               : std_logic_vector(2 downto 0) := "100";
-	constant aSP                : std_logic_vector(2 downto 0) := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR          => IR,
-			ISet        => ISet,
-			MCycle      => MCycle,
-			F           => F,
-			NMICycle    => NMICycle,
-			IntCycle    => IntCycle,
-			MCycles     => MCycles_d,
-			TStates     => TStates,
-			Prefix      => Prefix,
-			Inc_PC      => Inc_PC,
-			Inc_WZ      => Inc_WZ,
-			IncDec_16   => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op      => ALU_Op,
-			Save_ALU    => Save_ALU,
-			PreserveC   => PreserveC,
-			Arith16     => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ        => IORQ_i,
-			Jump        => Jump,
-			JumpE       => JumpE,
-			JumpXY      => JumpXY,
-			Call        => Call,
-			RstP        => RstP,
-			LDZ         => LDZ,
-			LDW         => LDW,
-			LDSPHL      => LDSPHL,
-			Special_LD  => Special_LD,
-			ExchangeDH  => ExchangeDH,
-			ExchangeRp  => ExchangeRp,
-			ExchangeAF  => ExchangeAF,
-			ExchangeRS  => ExchangeRS,
-			I_DJNZ      => I_DJNZ,
-			I_CPL       => I_CPL,
-			I_CCF       => I_CCF,
-			I_SCF       => I_SCF,
-			I_RETN      => I_RETN,
-			I_BT        => I_BT,
-			I_BC        => I_BC,
-			I_BTR       => I_BTR,
-			I_RLD       => I_RLD,
-			I_RRD       => I_RRD,
-			I_INRC      => I_INRC,
-			SetDI       => SetDI,
-			SetEI       => SetEI,
-			IMode       => IMode,
-			Halt        => Halt,
-			NoRead      => NoRead,
-			Write       => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16     => Z16_r,
-			ALU_Op  => ALU_Op_r,
-			IR      => IR(5 downto 0),
-			ISet    => ISet,
-			BusA    => BusA,
-			BusB    => BusB,
-			F_In    => F,
-			Q       => ALU_Q,
-			F_Out   => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T8080se.vhd
deleted file mode 100644
index 65b92d54..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T8080se.vhd	
+++ /dev/null
@@ -1,194 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- 8080 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original 8080
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---      STACK status output not supported
---
--- File history :
---
---      0237 : First version
---
---      0238 : Updated for T80 interface change
---
---      0240 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T8080se is
-	generic(
-		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK                     : in std_logic;
-		CLKEN           : in std_logic;
-		READY           : in std_logic;
-		HOLD            : in std_logic;
-		INT             : in std_logic;
-		INTE            : out std_logic;
-		DBIN            : out std_logic;
-		SYNC            : out std_logic;
-		VAIT            : out std_logic;
-		HLDA            : out std_logic;
-		WR_n            : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0)
-	);
-end T8080se;
-
-architecture rtl of T8080se is
-
-	signal IntCycle_n   : std_logic;
-	signal NoRead               : std_logic;
-	signal Write                : std_logic;
-	signal IORQ                 : std_logic;
-	signal INT_n                : std_logic;
-	signal HALT_n               : std_logic;
-	signal BUSRQ_n              : std_logic;
-	signal BUSAK_n              : std_logic;
-	signal DO_i                 : std_logic_vector(7 downto 0);
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal TState               : std_logic_vector(2 downto 0);
-	signal One                  : std_logic;
-
-begin
-
-	INT_n <= not INT;
-	BUSRQ_n <= HOLD;
-	HLDA <= not BUSAK_n;
-	SYNC <= '1' when TState = "001" else '0';
-	VAIT <= '1' when TState = "010" else '0';
-	One <= '1';
-
-	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
-	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
-	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
-	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
-	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
-	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
-	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
-	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 0)
-		port map(
-			CEN => CLKEN,
-			M1_n => open,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => open,
-			HALT_n => HALT_n,
-			WAIT_n => READY,
-			INT_n => INT_n,
-			NMI_n => One,
-			RESET_n => RESET_n,
-			BUSRQ_n => One,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO_i,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n,
-			IntE => INTE);
-
-	process (RESET_n, CLK)
-	begin
-		if RESET_n = '0' then
-			DBIN <= '0';
-			WR_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK'event and CLK = '1' then
-			if CLKEN = '1' then
-				DBIN <= '0';
-				WR_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and READY = '0') then
-						DBIN <= IntCycle_n;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
-						DBIN <= '1';
-					end if;
-					if T2Write = 0 then
-						if TState = "010" and Write = '1' then
-							WR_n <= '0';
-						end if;
-					else
-						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
-							WR_n <= '0';
-						end if;
-					end if;
-				end if;
-				if TState = "010" and READY = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index e09def1e..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,361 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 43cea1b5..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1944 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-				  ALU_Op <= "1000";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-				  ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-				  ALU_Op <= "1010";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index 42cf6105..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,217 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 1c0f2638..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---      0242 : Initial release
---
---      0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal      RegsH   : Register_Image(0 to 7);
-	signal      RegsL   : Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders.vhd
index ce639856..92fda62a 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders.vhd	
@@ -63,8 +63,8 @@ entity invaderst is
 		Sel1Player      : in  std_logic;
 		Sel2Player      : in  std_logic;
 		Fire            : in  std_logic;
-		MoveLeft        : in  std_logic;
-		MoveRight       : in  std_logic;
+		Pedal           : in  std_logic_vector(3 downto 0);
+		Steering        : in  std_logic_vector(7 downto 0);
 		DIP             : in  std_logic_vector(8 downto 1);
 		RDB             : in  std_logic_vector(7 downto 0);
 		IB              : in  std_logic_vector(7 downto 0);
@@ -169,35 +169,17 @@ begin
 				GDB1 when "01",
 				GDB2 when "10",
 				S when others;
+
 --IN0
-	GDB0(0) <= '0';	-- PEDAL
-	GDB0(1) <= '0';	-- PEDAL
-	GDB0(2) <= '0';	-- PEDAL
-	GDB0(3) <= '1';	-- PEDAL
+	GDB0(3 downto 0) <= Pedal;
 	GDB0(4) <= not Fire;	-- fire
 	GDB0(5) <= '1';	-- UNUSED
 	GDB0(6) <= not Coin;	-- coin
 	GDB0(7) <= not Sel1Player;	-- start
 --IN1
-	GDB1(0) <= '0';	-- steering wheel 
-	GDB1(1) <= '0';	-- steering wheel 
-	GDB1(2) <= '0';	-- steering wheel 
-	GDB1(3) <= '0';	-- steering wheel 
-	GDB1(4) <= '0';	-- steering wheel 
-	GDB1(5) <= '0';	-- steering wheel 
-	GDB1(6) <= '0';	-- steering wheel 
-	GDB1(7) <= '1';	-- steering wheel 
+	GDB1 <= Steering;
 --IN2
-	GDB2(0) <= '0';--Coinage
-	GDB2(1) <= '0';--Coinage
-	GDB2(2) <= '1';--Game_Time
-	GDB2(3) <= '1';--Game_Time
-	GDB2(4) <= '1';--Extended Time At
-	GDB2(5) <= '1';--Extended Time At
-	GDB2(6) <= '0';--Language
-	GDB2(7) <= '0';--Language
-	
-
+	GDB2 <= DIP;
 
 	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
 	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
@@ -215,13 +197,13 @@ begin
 			SoundCtrl5 <= (others => '0');
 			OldSample := '0';
 		elsif Clk'event and Clk = '1' then
-			if PortWr(2) = '1' then
+			if PortWr(4) = '1' then
 				EA <= DB(2 downto 0);
 			end if;
-			if PortWr(3) = '1' then
+			if PortWr(2) = '1' then
 				SoundCtrl3 <= DB(5 downto 0);
 			end if;
-			if PortWr(4) = '1' and OldSample = '0' then
+			if PortWr(3) = '1' and OldSample = '0' then
 				D5(15 downto 8) <= DB;
 				D5(7 downto 0) <= D5(15 downto 8);
 			end if;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders_audio.vhd
deleted file mode 100644
index f16cf379..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders_audio.vhd	
+++ /dev/null
@@ -1,496 +0,0 @@
-
--- Version : 0300
--- The latest version of this file can be found at:
---      http://www.fpgaarcade.com
--- minor tidy up by MikeJ
--------------------------------------------------------------------------------
--- Company:
--- Engineer:    PaulWalsh
---
--- Create Date:    08:45:29 11/04/05
--- Design Name:
--- Module Name:    Invaders Audio
--- Project Name:   Space Invaders
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-
-entity invaders_audio is
-	Port (
-	  Clk : in  std_logic;
-	  S1  : in  std_logic_vector(5 downto 0);
-	  S2  : in  std_logic_vector(5 downto 0);
-	  Aud : out std_logic_vector(7 downto 0)
-	  );
-end;
- --* Port 3: (S1)
- --* bit 0=UFO  (repeats)
- --* bit 1=Shot
- --* bit 2=Base hit
- --* bit 3=Invader hit
- --* bit 4=Bonus base
- --*
- --* Port 5: (S2)
- --* bit 0=Fleet movement 1
- --* bit 1=Fleet movement 2
- --* bit 2=Fleet movement 3
- --* bit 3=Fleet movement 4
- --* bit 4=UFO 2
-
-architecture Behavioral of invaders_audio is
-
-  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
-  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
-  signal Clk7680_ena  : std_logic;
-  signal Clk480_ena   : std_logic;
-  signal Clk240_ena   : std_logic;
-  signal Clk60_ena    : std_logic;
-
-  signal s1_t1        : std_logic_vector(5 downto 0);
-  signal s2_t1        : std_logic_vector(5 downto 0);
-  signal tempsum      : std_logic_vector(7 downto 0);
-
-  signal vco_cnt      : std_logic_vector(3 downto 0);
-
-  signal TriDir1      : std_logic;
-  signal Fnum         : std_logic_vector(3 downto 0);
-  signal comp         : std_logic;
-
-  signal SS           : std_logic;
-
-  signal TrigSH       : std_logic;
-  signal SHCnt        : std_logic_vector(8 downto 0);
-  signal SH           : std_logic_vector(7 downto 0);
-  signal SauHit       : std_logic_vector(8 downto 0);
-  signal SHitTri      : std_logic_vector(5 downto 0);
-
-  signal TrigIH       : std_logic;
-  signal IHDir        : std_logic;
-  signal IHDir1       : std_logic;
-  signal IHCnt        : std_logic_vector(8 downto 0);
-  signal IH           : std_logic_vector(7 downto 0);
-  signal InHit        : std_logic_vector(8 downto 0);
-  signal IHitTri      : std_logic_vector(5 downto 0);
-
-  signal TrigEx       : std_logic;
-  signal Excnt        : std_logic_vector(9 downto 0);
-  signal ExShift      : std_logic_vector(15 downto 0);
-  signal Ex           : std_logic_vector(2 downto 0);
-  signal Explo        : std_logic;
-
-  signal TrigMis      : std_logic;
-  signal MisShift     : std_logic_vector(15 downto 0);
-  signal MisCnt       : std_logic_vector(8 downto 0);
-  signal miscnt1      : unsigned(7 downto 0);
-  signal Mis          : std_logic_vector(2 downto 0);
-  signal Missile      : std_logic;
-
-  signal EnBG         : std_logic;
-  signal BGFnum       : std_logic_vector(7 downto 0);
-  signal BGCnum       : std_logic_vector(7 downto 0);
-  signal bg_cnt       : unsigned(7 downto 0);
-  signal BG           : std_logic;
-
-begin
-
-  -- do a crude addition of all sound samples
-	p_audio_mix : process
-	  variable IHVol : std_logic_vector(6 downto 0);
-	  variable SHVol : std_logic_vector(6 downto 0);
-	begin
-	  wait until rising_edge(Clk);
-
-	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
-	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
-
-	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
-
-	  Aud(7) <= tempsum (7);
-	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
-	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
-	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
-	  Aud(3 downto 0) <= tempsum (3 downto 0);
-
-	end process;
-
-	p_clkdiv : process
-	begin
-	  wait until rising_edge(Clk);
-	  Clk7680_ena <= '0';
-	  if ClkDiv =  1277 then
-		Clk7680_ena <= '1';
-		ClkDiv <= (others => '0');
-	  else
-		ClkDiv <= ClkDiv + 1;
-	  end if;
-	end process;
-
-	p_clkdiv2 : process
-	begin
-	  wait until rising_edge(Clk);
-	  Clk480_ena <= '0';
-	  Clk240_ena <= '0';
-	  Clk60_ena  <= '0';
-
-	  if (Clk7680_ena = '1') then
-		ClkDiv2 <= ClkDiv2 + 1;
-
-		if (ClkDiv2(3 downto 0) = "0000") then
-		  Clk480_ena <= '1';
-		end if;
-
-		if (ClkDiv2(4 downto 0) = "00000") then
-		  Clk240_ena <= '1';
-		end if;
-
-		if (ClkDiv2(7 downto 0) = "00000000") then
-		  Clk60_ena <= '1';
-		end if;
-
-	  end if;
-	end process;
-
-   p_delay : process
-   begin
-	 wait until rising_edge(Clk);
-	 s1_t1 <= S1;
-	 s2_t1 <= S2;
-   end process;
---*************************Saucer Sound***************************************
-
--- Implement a VCOscilator: frequency is set using counter end point(Fnum)
-	p_saucer_vco : process
-	  variable term : std_logic_vector(3 downto 0);
-	begin
-	  wait until rising_edge(Clk);
-	  term := 8 + Fnum;
-	  if (S1(0) = '1') and (Clk7680_ena = '1') then
-		if vco_cnt = term then
-
-		  vco_cnt <= (others => '0');
-		  SS <= not SS;
-		else
-		  vco_cnt <= vco_cnt + 1;
-		end if;
-	  end if;
-	end process;
-
--- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
-	-- this is 6Hz ?? 0123454321
-	p_saucer_lfo : process
-	begin
-	  wait until rising_edge(Clk);
-	  if (Clk60_ena = '1') then
-		if Fnum = 4 then -- 5 -1
-		  Comp <= '1';
-		elsif Fnum = 1 then -- 0 +1
-		  Comp <= '0';
-		end if;
-
-		if comp = '1' then
-		  Fnum <= Fnum - 1 ;
-		else
-		  Fnum <= Fnum + 1 ;
-		end if;
-	  end if;
-	end process;
-
---**********************SAUCER HIT Sound**************************
-
--- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
-	p_saucer_hit_vco : process
-	begin
-	  wait until rising_edge(Clk);
-	  if (Clk480_ena = '1') then
-		if SHitTri = 48 then
-		  SHitTri <= "000000";
-		else
-		  SHitTri <= SHitTri+1;
-		end if;
-	  end if;
-	end process;
-
--- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
-	p_saucer_hit_lfo : process
-	begin
-	 wait until rising_edge(Clk);
-	 if (Clk7680_ena = '1') then
-			if TriDir1 = '1' then
-				if (SauHit +58 - SHitTri) < 190 + 256 then
-					SauHit <= SauHit +58 - SHitTri;
-				else
-					SauHit <= "110111110";
-					TriDir1 <= '0';
-				end if;
-			else
-				if (SauHit -58 + SHitTri) > 256 then
-					SauHit <= SauHit -58 + SHitTri;
-				else
-					SauHit <= "100000000";
-					TriDir1 <= '1';
-				end if;
-			end if;
-	end if;
-  end process;
-
--- Implement the ADSR for Saucer Hit Sound
-	p_saucer_adsr : process
-	begin
-	  wait until rising_edge(Clk);
-	  if (Clk480_ena = '1') then
-		if (TrigSH = '1') then
-		  SHCnt <= "100000000";
-		  SH <= "11111111";
-		elsif (SHCnt(8) = '1') then
-		  SHCnt <= SHCnt + "1";
-		  if SHCnt(7 downto 0) = x"60" then -- 96
-			SH <= "01111111";
-		  elsif SHCnt(7 downto 0) = x"90" then -- 144
-			SH <= "00111111";
-		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
-			SH <= "00000000";
-		  end if;
-		end if;
-	  end if;
-	end process;
-
- -- Implement the trigger for The Saucer Hit Sound
-	p_saucer_hit : process
-	begin
-	  wait until rising_edge(Clk);
-	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
-		TrigSH <= '1';
-	  elsif (Clk480_ena = '1') then
-		TrigSH <= '0';
-	  end if;
-	end process;
-
---***********************Invader Hit Sound*****************************
--- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
-	p_invader_hit_lfo : process
-	begin
-	  wait until rising_edge(Clk);
-	  if (Clk480_ena = '1') then
-		if IHitTri = 48-2 then
-		  IHDir <= '0';
-		elsif IHitTri =0+2 then
-		  IHDir <= '1';
-		end if;
-
-		if IHDir ='1' then
-		  IHitTri <= IHitTri + 2;
-		else
-		  IHitTri <= IHitTri - 2;
-		end if;
-	  end if;
-	end process;
-
--- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
-	p_invader_hit_vco : process
-	begin
-	  wait until rising_edge(Clk);
-	  if (Clk7680_ena = '1') then
-		if IHDir1 = '1' then
-		  if (InHit +10 + IHitTri) < 110 + 256 then
-			 InHit <= InHit +10 + IHitTri;
-		   else
-			 InHit <= "101101110";
-			 IHDir1 <= '0';
-		   end if;
-		else
-		  if (InHit -10 - IHitTri) > 256 then
-			 InHit <= InHit -10 - IHitTri;
-		  else
-			 InHit <= "100000000";
-			 IHDir1 <= '1';
-		  end if;
-		end if;
-	  end if;
-	end process;
-
--- Implement the ADSR for Invader Hit Sound
-	p_invader_adsr : process
-	begin
-	  wait until rising_edge(Clk);
-	  if (Clk480_ena = '1') then
-		if (TrigIH = '1') then
-		  IHCnt <= "100000000";
-		  IH <= "11111111";
-		elsif (IHCnt(8) = '1') then
-		  IHCnt <= IHCnt + "1";
-		  if IHCnt(7 downto 0) = x"14" then -- 20
-			IH <= "01111111";
-		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
-			IH <= "11111111";
-		  elsif IHCnt(7 downto 0) = x"30" then -- 48
-			IH <= "00000000";
-		  end if;
-		end if;
-	  end if;
-	end process;
-
-  -- Implement the trigger for The Invader Hit Sound
-	p_invader_hit : process
-	begin
-	  wait until rising_edge(Clk);
-	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
-		TrigIH <= '1';
-	  elsif (Clk480_ena = '1') then
-		TrigIH <= '0';
-	  end if;
-	end process;
-
---***********************Explosion*****************************
--- Implement a Pseudo Random Noise Generator
-	p_explosion_pseudo : process
-	begin
-	  wait until rising_edge(Clk);
-	  if (Clk480_ena = '1') then
-		if (ExShift = x"0000") then
-		  ExShift <= "0000000010101001";
-		else
-		  ExShift(0) <= Exshift(14) xor ExShift(15);
-		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
-		end if;
-	  end if;
-	end process;
-	Explo <= ExShift(0);
-
-	p_explosion_adsr : process
-	begin
-	  wait until rising_edge(Clk);
-	  if (Clk480_ena = '1') then
-		if (TrigEx = '1') then
-		  ExCnt <= "1000000000";
-		  Ex <= "100";
-		elsif (ExCnt(9) = '1') then
-		  ExCnt <= ExCnt + "1";
-		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
-			Ex <= "010";
-		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
-			Ex <= "001";
-		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
-			Ex <= "000";
-		  end if;
-		end if;
-	  end if;
-	end process;
-
--- Implement the trigger for The Explosion Sound
-	p_explosion_trig : process
-	begin
-	  wait until rising_edge(Clk);
-	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
-		TrigEx <= '1';
-	  elsif (Clk480_ena = '1') then
-		TrigEx <= '0';
-	  end if;
-	end process;
-
---***********************Missile*****************************
--- Implement a Pseudo Random Noise Generator
-	p_missile_pseudo : process
-	begin
-	  wait until rising_edge(Clk);
-	  if (Clk7680_ena = '1') then
-		if (MisShift = x"0000") then
-		  MisShift <= "0000000010101001";
-		else
-		  MisShift(0) <= MisShift(14) xor MisShift(15);
-		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
-		end if;
-
-		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
-		if miscnt1 > 60 then
-		  miscnt1 <= "00000000";
-		  Missile <= not Missile;
-		end if;
-
-	  end if;
-	end process;
-
--- Implement the ADSR for The Missile Sound
-	p_missile_adsr : process
-	begin
-	  wait until rising_edge(Clk);
-	  if (Clk480_ena = '1') then
-		if (TrigMis = '1') then
-		  MisCnt <= "100000000";
-		  Mis <= "100";
-		elsif (MisCnt(8) = '1') then
-		  MisCnt <= MisCnt + "1";
-		  if MisCnt(7 downto 0) = x"4b" then -- 75
-			Mis <= "010";
-		  elsif MisCnt(7 downto 0) = x"70" then -- 112
-			Mis <= "001";
-		  elsif MisCnt(7 downto 0) = x"96" then -- 150
-			Mis <= "000";
-		  end if;
-		end if;
-	  end if;
-	end process;
-
--- Implement the trigger for The Missile Sound
-	p_missile_trig : process
-	begin
-	  wait until rising_edge(Clk);
-	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
-		TrigMis <= '1';
-	  elsif (Clk480_ena = '1') then
-		TrigMis <= '0';
-	  end if;
-	end process;
-
--- ******************************** Background invader moving tones **************************
-	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
-
-	with S2(3 downto 0) select
-		BGFnum <= x"66" when "0001",
-				  x"74" when "0010",
-				  x"7C" when "0100",
-				  x"87" when "1000",
-				  x"87" when others;
-
-	with S2(3 downto 0) select
-		BGCnum <= x"33" when "0001",
-				  x"3A" when "0010",
-				  x"3E" when "0100",
-				  x"43" when "1000",
-				  x"43" when others;
-
--- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
-
-	p_background : process
-	begin
-	  wait until rising_edge(Clk);
-	  if (Clk7680_ena = '1') then
-		if EnBG = '0' then
-		  bg_cnt <= x"00";
-		  BG <= '0';
-		else
-		  bg_cnt <= bg_cnt + 1;
-
-		  if bg_cnt = unsigned(BGfnum) then
-			bg_cnt <= x"00";
-			BG  <= '0';
-		  elsif bg_cnt=unsigned(BGCnum) then
-			BG <='1';
-		  end if;
-		end if;
-	  end if;
-	end process;
-
-end Behavioral;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.vhd
index f8d0b139..39c09b03 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.vhd	
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************
 
 
@@ -141,13 +141,13 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 27,
+		clk0_divide_by => 1125,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 10,
+		clk0_multiply_by => 416,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 27,
+		clk1_divide_by => 1125,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 20,
+		clk1_multiply_by => 832,
 		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -231,8 +231,8 @@ END SYN;
 -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "9.984000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "19.968000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -260,10 +260,10 @@ END SYN;
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
 -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "9.98400000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "19.96800000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -307,13 +307,13 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "416"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "832"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/spy_hunter_control.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/spy_hunter_control.vhd
new file mode 100644
index 00000000..7ca5b826
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/spy_hunter_control.vhd	
@@ -0,0 +1,160 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity spy_hunter_control is
+port(
+ clock_40     	: in std_logic;
+ reset        	: in std_logic;
+ vsync 			: in std_logic;
+ 
+ gas_plus     	: in std_logic;
+ gas_minus     : in std_logic;
+ steering_plus : in std_logic;
+ steering_minus: in std_logic;
+ steering      : out std_logic_vector(7 downto 0);
+ gas           : out std_logic_vector(7 downto 0)
+  );
+end spy_hunter_control;
+ 
+ 
+architecture struct of spy_hunter_control is
+ signal steering_r    : std_logic_vector(7 downto 0);
+ --signal steering_plus    : std_logic;
+ signal steering_plus_r  : std_logic;
+ --signal steering_minus   : std_logic;
+ signal steering_minus_r : std_logic;
+ signal steering_timer   : std_logic_vector(5 downto 0);
+ 
+ signal gas_r    : std_logic_vector(7 downto 0);
+ --signal gas_plus    : std_logic;
+ signal gas_plus_r  : std_logic;
+ --signal gas_minus   : std_logic;
+ signal gas_minus_r : std_logic;
+ signal gas_timer   : std_logic_vector(5 downto 0);
+ signal vsync_r : std_logic;
+ begin-- absolute position decoder simulation
+--
+--  steering :
+--       thresholds        median
+--   F5 <  left 8   < 34    30
+--   35 <  left 7   < 3C    38
+--   3D <  left 6   < 44    40
+--   45 <  left 5   < 4C    48     
+--   4D <  left 4   < 54    50
+--   45 <  left 3   < 5C    58
+--   5D <  left 2   < 64    60
+--   65 <  left 1   < 6C    68
+--   6D < centrered < 74    70
+--   75 <  right 1  < 7C    78
+--   7D <  right 2  < 84    80
+--   85 <  right 3  < 8C    88
+--   8D <  right 4  < 94    90
+--   95 <  right 5  < 9C    98
+--   9D <  right 6  < A4    A0
+--   A5 <  right 7  < AC    A8
+--   AD <  right 8  < F4    BO
+
+-- gas :
+--         threshold          median
+--    00 < gas pedal 00 < 3B   (39)  3E-5
+--    3C < gas pedal 01 < 40    3E
+--    41 < gas pedal 02 < 45    43
+--    46 < gas pedal 03 < 4A    48      
+--    4B < gas pedal 04 < 4F    4D
+--    50 < gas pedal 05 < 54    52
+--    55 < gas pedal 06 < 59    57
+--    5A < gas pedal 07 < 5E    5C
+--    5F < gas pedal 08 < 63    61
+--     ...
+--    FA < gas pedal 27 < FE    FC
+--    FF = gas pedal 28        (FF)  FC+4
+
+
+gas <= gas_r;
+steering <= steering_r;
+
+process (clock_40, reset)
+begin
+	if reset = '1' then 	
+		gas_r <= x"39";
+		steering_r <= x"70";
+	else
+
+		if rising_edge(clock_40) then
+			gas_plus_r       <= gas_plus;
+			gas_minus_r      <= gas_minus;
+			steering_plus_r  <= steering_plus;
+			steering_minus_r <= steering_minus;
+			vsync_r          <= vsync;
+			
+			-- gas increase/decrease as long as btn is pushed
+			-- keep current value when no btn is pushed
+			if gas_r < x"39" then
+				gas_r <= x"39";
+			else 		
+				if (gas_plus_r = not gas_plus)  or
+					(gas_minus_r = not gas_minus) then
+						gas_timer <= (others => '0');
+				else
+					if vsync_r ='0' and vsync = '1' then 
+						if (gas_timer >= 5 and (gas_minus_r = '1' or gas_plus_r = '1')) then --tune inc/dec rate
+							gas_timer <= (others => '0');
+						else
+							gas_timer <= gas_timer + 1;
+						end if;
+					end if;
+				end if;
+	
+				if vsync_r ='0' and vsync = '1' and gas_timer = 0 then	
+					if gas_plus = '1' then
+						if gas_r >= x"FC" then gas_r <= x"FF"; else gas_r <= gas_r + 5; end if;
+					elsif gas_minus = '1' then
+						if gas_r <= x"3E" then gas_r <= x"39"; else gas_r <= gas_r - 5; end if;
+					end if;
+				end if;
+				
+			end if;
+		
+			-- steering increase/decrease as long as btn is pushed
+			-- return to center value when no btn is pushed
+			if steering_r < x"30" then
+				steering_r <= x"30";
+			elsif steering_r > x"B0" then
+				steering_r <= x"B0"; 
+			else
+				if (steering_plus_r = not steering_plus)  or
+					(steering_minus_r = not steering_minus) then
+						steering_timer <= (others => '0');
+				else
+					if vsync_r ='0' and vsync = '1' then 
+						if (steering_timer >= 7 and (steering_minus_r = '1' or  steering_plus_r = '1')) or   -- tune btn pushed   rate
+						   (steering_timer >= 3 and (steering_minus_r = '0' and steering_plus_r = '0')) then -- tune btn released rate
+							steering_timer <= (others => '0');
+						else
+							steering_timer <= steering_timer + 1;
+						end if;
+					end if;
+				end if;
+				
+				if vsync_r ='0' and vsync = '1' and steering_timer = 0 then	
+					if steering_plus = '1' then 
+						if steering_r >= x"A8" then steering_r <= x"B0"; else steering_r <= steering_r + 8; end if;
+					elsif steering_minus = '1' then
+						if steering_r <= x"38" then steering_r <= x"30"; else steering_r <= steering_r - 8; end if;
+					else
+						if steering_r <= x"68" then steering_r <= steering_r + 8; end if;						
+						if steering_r >= x"78" then steering_r <= steering_r - 8; end if;
+						if (steering_r > x"68") and (steering_r < x"78") then steering_r <= x"70"; end if;						
+					end if;
+				end if;
+
+			end if;
+		
+		end if;
+		
+	end if;
+end process;	
+
+end struct;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qsf
index 37310fc8..6072b2b2 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qsf	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qsf	
@@ -41,7 +41,7 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
 # Pin & Location Assignments
@@ -106,7 +106,7 @@ set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
 
 # EDA Netlist Writer Assignments
 # ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
 
 # Assembler Assignments
 # =====================
@@ -130,7 +130,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 	# EDA Netlist Writer Assignments
 	# ==============================
-	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
 
 # end EDA_TOOL_SETTINGS(eda_simulation)
 # -------------------------------------
@@ -159,14 +159,7 @@ set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/BalloonBomber_memory.sv
 set_global_assignment -name VHDL_FILE rtl/BalloonBomber_Overlay.vhd
 set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
 set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
 set_global_assignment -name VHDL_FILE rtl/roms/tn07.vhd
 set_global_assignment -name VHDL_FILE rtl/roms/tn06.vhd
 set_global_assignment -name VHDL_FILE "rtl/roms/tn05-1.vhd"
@@ -174,4 +167,11 @@ set_global_assignment -name VHDL_FILE rtl/roms/tn04.vhd
 set_global_assignment -name VHDL_FILE rtl/roms/tn03.vhd
 set_global_assignment -name VHDL_FILE rtl/roms/tn02.vhd
 set_global_assignment -name VHDL_FILE rtl/roms/tn01.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp5.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/stp5.stp
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.sdc
new file mode 100644
index 00000000..11d2c7a9
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_memory.sv
index 2dda36ca..9d6f6628 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_memory.sv	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_memory.sv	
@@ -14,7 +14,7 @@ wire [7:0]rom_data_1;
 wire [7:0]rom_data_2;
 wire [7:0]rom_data_3;
 wire [7:0]rom_data_4;
-wire [10:0]rom_addr = {Addr[11:10],~Addr[9],Addr[8:4],~Addr[3],Addr[2:1],~Addr[0]};
+wire [10:0]rom_addr =	Addr[10:0];
 
 tn01 tn01 (
 	.clk(Clock),
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_mist.sv
index b596dae0..c721603d 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_mist.sv	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_mist.sv	
@@ -20,33 +20,37 @@ module BalloonBomber_mist(
 
 localparam CONF_STR = {
 	"BallBomb;;",
+	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-	"O5,Overlay, On, Off;",
-	"T6,Reset;",
+	"O5,Overlay,On,Off;",
+	"T0,Reset;",
 	"V,v1.20.",`BUILD_DATE
 };
 
+wire  [1:0] scanlines = status[4:3];
+wire        rotate    = status[2];
+wire        overlay   = status[5];
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
-
-wire clk_sys, clk_core;
+wire clk_core, clk_vid;
 wire pll_locked;
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(),
 	.c0(clk_core),
-	.c1(clk_sys)
+	.c1(clk_vid)
 );
 
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire  [7:0] kbjoy;
 wire  [7:0] joystick_0,joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
+wire        no_csync;
 wire        key_pressed;
 wire  [7:0] key_code;
 wire        key_strobe;
@@ -69,13 +73,13 @@ wire HSync;
 wire VSync;
 
 invaderst invaderst(
-	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Rst_n(~(status[0] | buttons[1])),
 	.Clk(clk_core),
 	.ENA(),
-	.Coin(btn_coin),
-	.Sel1Player(~btn_one_player),
-	.Sel2Player(~btn_two_players),
-	.Fire(~m_fire),
+	.Coin(m_coin1 | m_coin2),
+	.Sel1Player(~m_one_player),
+	.Sel2Player(~m_two_players),
+	.Fire(~m_fireA),
 	.MoveLeft(~m_left),
 	.MoveRight(~m_right),
 	.MoveUp(~m_up),
@@ -93,7 +97,7 @@ invaderst invaderst(
 	.HSync(HSync),
 	.VSync(VSync)
 	);
-		
+
 BalloonBomber_memory BalloonBomber_memory (
 	.Clock(clk_core),
 	.RW_n(RWE_n),
@@ -103,10 +107,10 @@ BalloonBomber_memory BalloonBomber_memory (
 	.Ram_in(RWD),
 	.Rom_out(IB)
 	);
-	
+
 BalloonBomber_Overlay BalloonBomber_Overlay (
 	.Video(Video),
-	.Overlay(~status[5]),
+	.Overlay(~overlay),
 	.CLK(clk_core),
 	.Rst_n_s(Rst_n_s),
 	.HSync(HSync),
@@ -117,7 +121,7 @@ BalloonBomber_Overlay BalloonBomber_Overlay (
 	.O_HSYNC(hs),
 	.O_VSYNC(vs)
 	);
-			
+
 invaders_audio invaders_audio (
 	.Clk(clk_core),
 	.S1(SoundCtrl3),
@@ -125,14 +129,14 @@ invaders_audio invaders_audio (
 	.Aud(audio)
 	);
 
-mist_video #(.COLOR_DEPTH(3)) mist_video(
-	.clk_sys(clk_sys),
+mist_video #(.COLOR_DEPTH(1)) mist_video(
+	.clk_sys(clk_vid),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({r,r,r}),
-	.G({g,g,g}),
-	.B({b,b,b}),
+	.R(r),
+	.G(g),
+	.B(b),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -140,16 +144,18 @@ mist_video #(.COLOR_DEPTH(3)) mist_video(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
+	.rotate({1'b0,rotate}),
 	.scandoubler_disable(scandoublerD),
-	.scanlines(status[4:3]),
-	.ce_divider(0),
-	.ypbpr(ypbpr)
+	.scanlines(scanlines),
+	.ce_divider(1'b0),
+	.ypbpr(ypbpr),
+	.no_csync(no_csync)
 	);
 
 user_io #(
 	.STRLEN(($size(CONF_STR)>>3)))
 user_io(
-	.clk_sys        (clk_sys        ),
+	.clk_sys        (clk_core       ),
 	.conf_str       (CONF_STR       ),
 	.SPI_CLK        (SPI_SCK        ),
 	.SPI_SS_IO      (CONF_DATA0     ),
@@ -159,6 +165,7 @@ user_io(
 	.switches       (switches       ),
 	.scandoubler_disable (scandoublerD	  ),
 	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
 	.key_strobe     (key_strobe     ),
 	.key_pressed    (key_pressed    ),
 	.key_code       (key_code       ),
@@ -168,41 +175,30 @@ user_io(
 	);
 
 dac dac (
-	.clk_i(clk_sys),
+	.clk_i(clk_core),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
 
-wire m_up     = status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
 
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_coin  = 0;
-
-always @(posedge clk_sys) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h75: btn_up          <= key_pressed; // up
-			'h72: btn_down        <= key_pressed; // down
-			'h6B: btn_left        <= key_pressed; // left
-			'h74: btn_right       <= key_pressed; // right
-			'h76: btn_coin        <= key_pressed; // ESC
-			'h05: btn_one_player  <= key_pressed; // F1
-			'h06: btn_two_players <= key_pressed; // F2
-			'h29: btn_fire1       <= key_pressed; // Space
-		endcase
-	end
-end
+arcade_inputs inputs (
+	.clk         ( clk_core    ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b01       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index da01f6b4..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1080 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in  std_logic;
-		CLK_n           : in  std_logic;
-		CEN             : in  std_logic;
-		WAIT_n          : in  std_logic;
-		INT_n           : in  std_logic;
-		NMI_n           : in  std_logic;
-		BUSRQ_n         : in  std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A               : out std_logic_vector(15 downto 0);
-		DInst           : in  std_logic_vector(7 downto 0);
-		DI              : in  std_logic_vector(7 downto 0);
-		DO              : out std_logic_vector(7 downto 0);
-		MC              : out std_logic_vector(2 downto 0);
-		TS              : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone              : std_logic_vector(2 downto 0) := "111";
-	constant aBC                : std_logic_vector(2 downto 0) := "000";
-	constant aDE                : std_logic_vector(2 downto 0) := "001";
-	constant aXY                : std_logic_vector(2 downto 0) := "010";
-	constant aIOA               : std_logic_vector(2 downto 0) := "100";
-	constant aSP                : std_logic_vector(2 downto 0) := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR          => IR,
-			ISet        => ISet,
-			MCycle      => MCycle,
-			F           => F,
-			NMICycle    => NMICycle,
-			IntCycle    => IntCycle,
-			MCycles     => MCycles_d,
-			TStates     => TStates,
-			Prefix      => Prefix,
-			Inc_PC      => Inc_PC,
-			Inc_WZ      => Inc_WZ,
-			IncDec_16   => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op      => ALU_Op,
-			Save_ALU    => Save_ALU,
-			PreserveC   => PreserveC,
-			Arith16     => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ        => IORQ_i,
-			Jump        => Jump,
-			JumpE       => JumpE,
-			JumpXY      => JumpXY,
-			Call        => Call,
-			RstP        => RstP,
-			LDZ         => LDZ,
-			LDW         => LDW,
-			LDSPHL      => LDSPHL,
-			Special_LD  => Special_LD,
-			ExchangeDH  => ExchangeDH,
-			ExchangeRp  => ExchangeRp,
-			ExchangeAF  => ExchangeAF,
-			ExchangeRS  => ExchangeRS,
-			I_DJNZ      => I_DJNZ,
-			I_CPL       => I_CPL,
-			I_CCF       => I_CCF,
-			I_SCF       => I_SCF,
-			I_RETN      => I_RETN,
-			I_BT        => I_BT,
-			I_BC        => I_BC,
-			I_BTR       => I_BTR,
-			I_RLD       => I_RLD,
-			I_RRD       => I_RRD,
-			I_INRC      => I_INRC,
-			SetDI       => SetDI,
-			SetEI       => SetEI,
-			IMode       => IMode,
-			Halt        => Halt,
-			NoRead      => NoRead,
-			Write       => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16     => Z16_r,
-			ALU_Op  => ALU_Op_r,
-			IR      => IR(5 downto 0),
-			ISet    => ISet,
-			BusA    => BusA,
-			BusB    => BusB,
-			F_In    => F,
-			Q       => ALU_Q,
-			F_Out   => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T8080se.vhd
deleted file mode 100644
index 65b92d54..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T8080se.vhd	
+++ /dev/null
@@ -1,194 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- 8080 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original 8080
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---      STACK status output not supported
---
--- File history :
---
---      0237 : First version
---
---      0238 : Updated for T80 interface change
---
---      0240 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T8080se is
-	generic(
-		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK                     : in std_logic;
-		CLKEN           : in std_logic;
-		READY           : in std_logic;
-		HOLD            : in std_logic;
-		INT             : in std_logic;
-		INTE            : out std_logic;
-		DBIN            : out std_logic;
-		SYNC            : out std_logic;
-		VAIT            : out std_logic;
-		HLDA            : out std_logic;
-		WR_n            : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0)
-	);
-end T8080se;
-
-architecture rtl of T8080se is
-
-	signal IntCycle_n   : std_logic;
-	signal NoRead               : std_logic;
-	signal Write                : std_logic;
-	signal IORQ                 : std_logic;
-	signal INT_n                : std_logic;
-	signal HALT_n               : std_logic;
-	signal BUSRQ_n              : std_logic;
-	signal BUSAK_n              : std_logic;
-	signal DO_i                 : std_logic_vector(7 downto 0);
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal TState               : std_logic_vector(2 downto 0);
-	signal One                  : std_logic;
-
-begin
-
-	INT_n <= not INT;
-	BUSRQ_n <= HOLD;
-	HLDA <= not BUSAK_n;
-	SYNC <= '1' when TState = "001" else '0';
-	VAIT <= '1' when TState = "010" else '0';
-	One <= '1';
-
-	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
-	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
-	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
-	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
-	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
-	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
-	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
-	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 0)
-		port map(
-			CEN => CLKEN,
-			M1_n => open,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => open,
-			HALT_n => HALT_n,
-			WAIT_n => READY,
-			INT_n => INT_n,
-			NMI_n => One,
-			RESET_n => RESET_n,
-			BUSRQ_n => One,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO_i,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n,
-			IntE => INTE);
-
-	process (RESET_n, CLK)
-	begin
-		if RESET_n = '0' then
-			DBIN <= '0';
-			WR_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK'event and CLK = '1' then
-			if CLKEN = '1' then
-				DBIN <= '0';
-				WR_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and READY = '0') then
-						DBIN <= IntCycle_n;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
-						DBIN <= '1';
-					end if;
-					if T2Write = 0 then
-						if TState = "010" and Write = '1' then
-							WR_n <= '0';
-						end if;
-					else
-						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
-							WR_n <= '0';
-						end if;
-					end if;
-				end if;
-				if TState = "010" and READY = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index e09def1e..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,361 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 43cea1b5..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1944 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-				  ALU_Op <= "1000";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-				  ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-				  ALU_Op <= "1010";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index 42cf6105..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,217 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 1c0f2638..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---      0242 : Initial release
---
---      0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal      RegsH   : Register_Image(0 to 7);
-	signal      RegsL   : Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders.vhd
index ca17b82c..7dfae135 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders.vhd	
@@ -195,26 +195,19 @@ begin
 			HSync => HSync,
 			VSync => VSync);
 
---	with AD_i(9 downto 8) select
---		GDB <= GDB0 when "00",
---				GDB1 when "01",
---				GDB2 when "10",
---				S when others;
-				
-			GDB_A <= not AD_i(9) & AD_i(8);
-
-	with GDB_A select
+	with AD_i(9 downto 8) select
 		GDB <= GDB0 when "00",
 				GDB1 when "01",
 				GDB2 when "10",
 				S when others;
+				
 	GDB0(0) <= '0';
 	GDB0(1) <= '0';
 	GDB0(2) <= '0';
 	GDB0(3) <= '0';
-	GDB0(4) <= not Fire;
-	GDB0(5) <= not MoveLeft;
-	GDB0(6) <= not MoveRight;
+	GDB0(4) <= '0';
+	GDB0(5) <= '0';
+	GDB0(6) <= '0';
 	GDB0(7) <= '0';
 	
 	GDB1(0) <= Coin;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.vhd
index f8d0b139..39c09b03 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.vhd	
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************
 
 
@@ -141,13 +141,13 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 27,
+		clk0_divide_by => 1125,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 10,
+		clk0_multiply_by => 416,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 27,
+		clk1_divide_by => 1125,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 20,
+		clk1_multiply_by => 832,
 		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -231,8 +231,8 @@ END SYN;
 -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "9.984000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "19.968000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -260,10 +260,10 @@ END SYN;
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
 -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "9.98400000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "19.96800000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -307,13 +307,13 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "416"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "832"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/ballbomb.zip b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/ballbomb.zip
deleted file mode 100644
index 02178e7f51e8d17d799287093b2e7ffbc81d32cd..0000000000000000000000000000000000000000
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literal 0
HcmV?d00001

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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06
deleted file mode 100644
index 2000072a..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06	
+++ /dev/null
@@ -1 +0,0 @@
-
				





	
				





	
				





	
				





	
				





	
				





	
				





	
				





	
				





	
				





			
				





			
				





			
				





			
				





			
				





			
				





			
				





			
				





			
				





			
				





	


				





	


				





	


				





	


				





	


				





	


				





	


				





	


				





	

\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07
deleted file mode 100644
index 7d88e647..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07	
+++ /dev/null
@@ -1 +0,0 @@
-



				





	



				





	



				





	



				





	



				





	

				





	

				





	

				





	

				





	

				





			

				





			

				





			

				





			

				





			

				





			

				





			

				





			

				





			

				





			

				





	



				





	



				





	



				





	



				





	



				





	



				





	



				





	



				





	

\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qsf
index 981a7773..21093dab 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qsf	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qsf	
@@ -41,25 +41,9 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/BlueShark_mist.sv
-set_global_assignment -name VHDL_FILE rtl/invaders.vhd
-set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
-set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/BlueShark_memory.sv
-set_global_assignment -name VHDL_FILE rtl/sprom.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/BlueShark_Overlay.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
 
 # Pin & Location Assignments
 # ==========================
@@ -123,7 +107,7 @@ set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
 
 # EDA Netlist Writer Assignments
 # ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
 
 # Assembler Assignments
 # =====================
@@ -147,7 +131,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 	# EDA Netlist Writer Assignments
 	# ==============================
-	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
 
 # end EDA_TOOL_SETTINGS(eda_simulation)
 # -------------------------------------
@@ -169,4 +153,21 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(BlueShark_mist)
 # --------------------------
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/BlueShark_mist.sv
+set_global_assignment -name VHDL_FILE rtl/spinner.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/BlueShark_memory.sv
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/BlueShark_Overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp4.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/stp4.stp
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.sdc
index f91c127c..11d2c7a9 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.sdc	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.sdc	
@@ -87,7 +87,7 @@ set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [g
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {VGA_*}]
 
 #**************************************************************
 # Set Clock Groups
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/README.txt
index 07c9cf12..822afd0c 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/README.txt	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/README.txt	
@@ -14,7 +14,7 @@
 -- Keyboard inputs :
 --
 --   F1          : Start
---   SPACE       : Fire
+--   RIGHT CTRL  : Fire
 --   RIGHT/LEFT  : Movement
 --
 -- Joystick support.
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/Snapshot/BlueShark.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/Snapshot/BlueShark.rbf
deleted file mode 100644
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A?f?J)

diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_mist.sv
index 14647137..fe0cdfd4 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_mist.sv	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_mist.sv	
@@ -21,32 +21,36 @@ module BlueShark_mist(
 localparam CONF_STR = {
 	"BlueShark;;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-	"O5,Overlay, On, Off;",
-	"T6,Reset;",
+	"O5,Overlay,On,Off;",
+	"T0,Reset;",
 	"V,v0.00.",`BUILD_DATE
 };
 
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
+wire        rotate = 0;
+wire        reset = status[0] | buttons[1];
+wire  [1:0] scanlines = status[4:3];
+wire        overlay = status[5];
 
-wire clk_core, clk_sys;
+wire clk_core, clk_vid;
 wire pll_locked;
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(),
 	.c0(clk_core),
-	.c1(clk_sys)
+	.c1(clk_vid)
 );
 
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire  [7:0] kbjoy;
 wire  [7:0] joystick_0,joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
+wire        no_csync;
 wire        key_pressed;
 wire  [7:0] key_code;
 wire        key_strobe;
@@ -82,16 +86,26 @@ Replay
 										On		On	 			None
 */
 
+wire  [7:0] paddle;
+
+spinner spinner(
+	.clock_40(clk_core),
+	.reset(reset),
+	.btn_left(m_right),
+	.btn_right(m_left),
+	.ctc_zc_to_2(vs),
+	.spin_angle(paddle)
+);
+
 invaderst invaderst(
-	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Rst_n(~reset),
 	.Clk(clk_core),
 	.ENA(),
-	.Coin(btn_coin),
-	.Sel1Player(~btn_one_player),
-	.Sel2Player(~btn_two_players),
-	.Fire(~m_fire),
-	.MoveLeft(~m_left),
-	.MoveRight(~m_right),
+	.Coin(m_coin1 | m_coin2),
+	.Sel1Player(~m_one_player),
+	.Sel2Player(~m_two_players),
+	.Fire(~m_fireA),
+	.Paddle(paddle),
 	.DIP("00000000"),
 	.RDB(RDB),
 	.IB(IB),
@@ -126,7 +140,7 @@ invaders_audio invaders_audio (
 	  
 BlueShark_Overlay BlueShark_Overlay (
 	.Video(Video),
-	.Overlay(~status[5]),
+	.Overlay(overlay),
 	.CLK(clk_core),
 	.Rst_n_s(Rst_n_s),
 	.HSync(HSync),
@@ -139,14 +153,14 @@ BlueShark_Overlay BlueShark_Overlay (
 	.O_VSYNC(vs)
 	);
 
-mist_video #(.COLOR_DEPTH(3)) mist_video(
-	.clk_sys(clk_sys),
+mist_video #(.COLOR_DEPTH(1)) mist_video(
+	.clk_sys(clk_vid),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({r,r,r}),
-	.G({g,g,g}),
-	.B({b,b,b}),
+	.R(r),
+	.G(g),
+	.B(b),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -154,16 +168,18 @@ mist_video #(.COLOR_DEPTH(3)) mist_video(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
+	.rotate({1'b0,rotate}),
 	.scandoubler_disable(scandoublerD),
-	.scanlines(status[4:3]),
-	.ce_divider(0),
-	.ypbpr(ypbpr)
+	.scanlines(scanlines),
+	.ce_divider(1'b0),
+	.ypbpr(ypbpr),
+	.no_csync(no_csync)
 	);
 
 user_io #(
 	.STRLEN(($size(CONF_STR)>>3)))
 user_io(
-	.clk_sys        (clk_sys       ),
+	.clk_sys        (clk_core       ),
 	.conf_str       (CONF_STR       ),
 	.SPI_CLK        (SPI_SCK        ),
 	.SPI_SS_IO      (CONF_DATA0     ),
@@ -173,6 +189,7 @@ user_io(
 	.switches       (switches       ),
 	.scandoubler_disable (scandoublerD	  ),
 	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
 	.key_strobe     (key_strobe     ),
 	.key_pressed    (key_pressed    ),
 	.key_code       (key_code       ),
@@ -182,33 +199,30 @@ user_io(
 	);
 
 dac dac (
-	.clk_i(clk_sys),
+	.clk_i(clk_core),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
 
-wire m_left   = btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_fire1 = 0;
-reg btn_coin  = 0;
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
 
-always @(posedge clk_sys) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h6B: btn_left        <= key_pressed; // left
-			'h74: btn_right       <= key_pressed; // right
-			'h76: btn_coin        <= key_pressed; // ESC
-			'h05: btn_one_player  <= key_pressed; // F1
-			'h06: btn_two_players <= key_pressed; // F2
-			'h29: btn_fire1       <= key_pressed; // Space
-		endcase
-	end
-end
+arcade_inputs inputs (
+	.clk         ( clk_core    ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b00       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index da01f6b4..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1080 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in  std_logic;
-		CLK_n           : in  std_logic;
-		CEN             : in  std_logic;
-		WAIT_n          : in  std_logic;
-		INT_n           : in  std_logic;
-		NMI_n           : in  std_logic;
-		BUSRQ_n         : in  std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A               : out std_logic_vector(15 downto 0);
-		DInst           : in  std_logic_vector(7 downto 0);
-		DI              : in  std_logic_vector(7 downto 0);
-		DO              : out std_logic_vector(7 downto 0);
-		MC              : out std_logic_vector(2 downto 0);
-		TS              : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone              : std_logic_vector(2 downto 0) := "111";
-	constant aBC                : std_logic_vector(2 downto 0) := "000";
-	constant aDE                : std_logic_vector(2 downto 0) := "001";
-	constant aXY                : std_logic_vector(2 downto 0) := "010";
-	constant aIOA               : std_logic_vector(2 downto 0) := "100";
-	constant aSP                : std_logic_vector(2 downto 0) := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR          => IR,
-			ISet        => ISet,
-			MCycle      => MCycle,
-			F           => F,
-			NMICycle    => NMICycle,
-			IntCycle    => IntCycle,
-			MCycles     => MCycles_d,
-			TStates     => TStates,
-			Prefix      => Prefix,
-			Inc_PC      => Inc_PC,
-			Inc_WZ      => Inc_WZ,
-			IncDec_16   => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op      => ALU_Op,
-			Save_ALU    => Save_ALU,
-			PreserveC   => PreserveC,
-			Arith16     => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ        => IORQ_i,
-			Jump        => Jump,
-			JumpE       => JumpE,
-			JumpXY      => JumpXY,
-			Call        => Call,
-			RstP        => RstP,
-			LDZ         => LDZ,
-			LDW         => LDW,
-			LDSPHL      => LDSPHL,
-			Special_LD  => Special_LD,
-			ExchangeDH  => ExchangeDH,
-			ExchangeRp  => ExchangeRp,
-			ExchangeAF  => ExchangeAF,
-			ExchangeRS  => ExchangeRS,
-			I_DJNZ      => I_DJNZ,
-			I_CPL       => I_CPL,
-			I_CCF       => I_CCF,
-			I_SCF       => I_SCF,
-			I_RETN      => I_RETN,
-			I_BT        => I_BT,
-			I_BC        => I_BC,
-			I_BTR       => I_BTR,
-			I_RLD       => I_RLD,
-			I_RRD       => I_RRD,
-			I_INRC      => I_INRC,
-			SetDI       => SetDI,
-			SetEI       => SetEI,
-			IMode       => IMode,
-			Halt        => Halt,
-			NoRead      => NoRead,
-			Write       => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16     => Z16_r,
-			ALU_Op  => ALU_Op_r,
-			IR      => IR(5 downto 0),
-			ISet    => ISet,
-			BusA    => BusA,
-			BusB    => BusB,
-			F_In    => F,
-			Q       => ALU_Q,
-			F_Out   => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T8080se.vhd
deleted file mode 100644
index 65b92d54..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T8080se.vhd	
+++ /dev/null
@@ -1,194 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- 8080 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original 8080
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---      STACK status output not supported
---
--- File history :
---
---      0237 : First version
---
---      0238 : Updated for T80 interface change
---
---      0240 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T8080se is
-	generic(
-		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK                     : in std_logic;
-		CLKEN           : in std_logic;
-		READY           : in std_logic;
-		HOLD            : in std_logic;
-		INT             : in std_logic;
-		INTE            : out std_logic;
-		DBIN            : out std_logic;
-		SYNC            : out std_logic;
-		VAIT            : out std_logic;
-		HLDA            : out std_logic;
-		WR_n            : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0)
-	);
-end T8080se;
-
-architecture rtl of T8080se is
-
-	signal IntCycle_n   : std_logic;
-	signal NoRead               : std_logic;
-	signal Write                : std_logic;
-	signal IORQ                 : std_logic;
-	signal INT_n                : std_logic;
-	signal HALT_n               : std_logic;
-	signal BUSRQ_n              : std_logic;
-	signal BUSAK_n              : std_logic;
-	signal DO_i                 : std_logic_vector(7 downto 0);
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal TState               : std_logic_vector(2 downto 0);
-	signal One                  : std_logic;
-
-begin
-
-	INT_n <= not INT;
-	BUSRQ_n <= HOLD;
-	HLDA <= not BUSAK_n;
-	SYNC <= '1' when TState = "001" else '0';
-	VAIT <= '1' when TState = "010" else '0';
-	One <= '1';
-
-	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
-	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
-	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
-	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
-	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
-	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
-	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
-	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 0)
-		port map(
-			CEN => CLKEN,
-			M1_n => open,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => open,
-			HALT_n => HALT_n,
-			WAIT_n => READY,
-			INT_n => INT_n,
-			NMI_n => One,
-			RESET_n => RESET_n,
-			BUSRQ_n => One,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO_i,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n,
-			IntE => INTE);
-
-	process (RESET_n, CLK)
-	begin
-		if RESET_n = '0' then
-			DBIN <= '0';
-			WR_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK'event and CLK = '1' then
-			if CLKEN = '1' then
-				DBIN <= '0';
-				WR_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and READY = '0') then
-						DBIN <= IntCycle_n;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
-						DBIN <= '1';
-					end if;
-					if T2Write = 0 then
-						if TState = "010" and Write = '1' then
-							WR_n <= '0';
-						end if;
-					else
-						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
-							WR_n <= '0';
-						end if;
-					end if;
-				end if;
-				if TState = "010" and READY = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index e09def1e..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,361 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 43cea1b5..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1944 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-				  ALU_Op <= "1000";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-				  ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-				  ALU_Op <= "1010";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index 42cf6105..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,217 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 1c0f2638..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---      0242 : Initial release
---
---      0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal      RegsH   : Register_Image(0 to 7);
-	signal      RegsL   : Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders.vhd
index e362f4b0..ea6f9ed2 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders.vhd	
@@ -62,9 +62,8 @@ entity invaderst is
 		Coin            : in  std_logic;
 		Sel1Player      : in  std_logic;
 		Sel2Player      : in  std_logic;
+		Paddle          : in  std_logic_vector(7 downto 0);
 		Fire            : in  std_logic;
-		MoveLeft        : in  std_logic;
-		MoveRight       : in  std_logic;
 		DIP             : in  std_logic_vector(7 downto 0);
 		RDB             : in  std_logic_vector(7 downto 0);
 		IB              : in  std_logic_vector(7 downto 0);
@@ -92,7 +91,7 @@ architecture rtl of invaderst is
 	signal DB           : std_logic_vector(7 downto 0);
 	signal Sounds       : std_logic_vector(7 downto 0);
 	signal AD_i         : std_logic_vector(15 downto 0);
-	signal PortWr       : std_logic_vector(6 downto 2);
+	signal PortWr       : std_logic_vector(6 downto 1);
 	signal EA           : std_logic_vector(2 downto 0);
 	signal D5           : std_logic_vector(15 downto 0);
 	signal WD_Cnt       : unsigned(7 downto 0);
@@ -170,23 +169,16 @@ begin
 				GDB2 when "10",
 				S when others;
 
-	GDB0(0) <= '1';             -- Unused
-	GDB0(1) <= '1';             -- Unused
-	GDB0(2) <= '1';             -- Unused
-	GDB0(3) <= '1';             -- Unused
-	GDB0(4) <= '1';             -- Unused
-	GDB0(5) <= '1';             -- Unused
-	GDB0(6) <= '1';             -- Unused
-	GDB0(7) <= '1';             -- Unused
+	GDB0(0) <= S(7);
+	GDB0(1) <= S(6);
+	GDB0(2) <= S(5);
+	GDB0(3) <= S(4);
+	GDB0(4) <= S(3);
+	GDB0(5) <= S(2);
+	GDB0(6) <= S(1);
+	GDB0(7) <= S(0);
 
-	GDB1(0) <= '1';	-- PADDLE
-	GDB1(1) <= '1';	-- PADDLE
-	GDB1(2) <= '1';	-- PADDLE
-	GDB1(3) <= '1';	-- PADDLE
-	GDB1(4) <= '1';	-- PADDLE
-	GDB1(5) <= '1';	-- PADDLE
-	GDB1(6) <= '1';	-- PADDLE
-	GDB1(7) <= '0';	-- PADDLE
+	GDB1 <= Paddle;
 
 	GDB2(0) <= not Fire;
 	GDB2(1) <= not Coin;
@@ -197,6 +189,7 @@ begin
 	GDB2(6) <= '1';	-- Replay
 	GDB2(7) <= '1';	-- TEST
 
+	PortWr(1) <= '1' when AD_i(10 downto 8) = "001" and Sample = '1' else '0';
 	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
 	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
 	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
@@ -213,13 +206,13 @@ begin
 			SoundCtrl5 <= (others => '0');
 			OldSample := '0';
 		elsif Clk'event and Clk = '1' then
-			if PortWr(2) = '1' then
+			if PortWr(1) = '1' then
 				EA <= DB(2 downto 0);
 			end if;
 			if PortWr(3) = '1' then
 				SoundCtrl3 <= DB(5 downto 0);
 			end if;
-			if PortWr(4) = '1' and OldSample = '0' then
+			if PortWr(2) = '1' and OldSample = '0' then
 				D5(15 downto 8) <= DB;
 				D5(7 downto 0) <= D5(15 downto 8);
 			end if;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.vhd
index f8d0b139..39c09b03 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.vhd	
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************
 
 
@@ -141,13 +141,13 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 27,
+		clk0_divide_by => 1125,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 10,
+		clk0_multiply_by => 416,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 27,
+		clk1_divide_by => 1125,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 20,
+		clk1_multiply_by => 832,
 		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -231,8 +231,8 @@ END SYN;
 -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "9.984000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "19.968000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -260,10 +260,10 @@ END SYN;
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
 -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "9.98400000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "19.96800000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -307,13 +307,13 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "416"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "832"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/spinner.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/spinner.vhd
new file mode 100644
index 00000000..88a56651
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/spinner.vhd	
@@ -0,0 +1,49 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity spinner is
+generic(
+	step          : integer := 40
+);
+port(
+ clock_40       : in std_logic;
+ reset          : in std_logic;
+ btn_left       : in std_logic;
+ btn_right      : in std_logic;
+ btn_acc        : in std_logic; -- speed up button
+ ctc_zc_to_2    : in std_logic;
+ spin_angle     : out std_logic_vector(6 downto 0)
+);
+end spinner;
+
+architecture rtl of spinner is
+
+signal ctc_zc_to_2_r : std_logic;
+signal spin_count    : std_logic_vector(9 downto 0);
+
+begin
+
+spin_angle <= spin_count(9 downto 3);
+
+process (clock_40, reset)
+begin
+	if reset = '1' then
+		spin_count <= (others => '0');
+	elsif rising_edge(clock_40) then
+		ctc_zc_to_2_r <= ctc_zc_to_2;
+
+		if ctc_zc_to_2_r ='0' and ctc_zc_to_2 = '1' then
+			if btn_acc = '0' then  -- space -- speed up
+				if btn_left = '1' then spin_count <= spin_count - step; end if; -- left
+				if btn_right = '1' then spin_count <= spin_count + step; end if; -- right
+			else
+				if btn_left = '1' then spin_count <= spin_count - 55; end if;
+				if btn_right = '1' then spin_count <= spin_count + 55; end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qsf
index 872504f6..cfe4c70b 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qsf	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qsf	
@@ -41,24 +41,9 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/BowlingAlley_mist.sv
-set_global_assignment -name VHDL_FILE rtl/invaders.vhd
-set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
-set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/BowlingAlley_memory.sv
-set_global_assignment -name VHDL_FILE rtl/sprom.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
 
 # Pin & Location Assignments
 # ==========================
@@ -122,7 +107,7 @@ set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
 
 # EDA Netlist Writer Assignments
 # ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
 
 # Assembler Assignments
 # =====================
@@ -146,7 +131,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 	# EDA Netlist Writer Assignments
 	# ==============================
-	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
 
 # end EDA_TOOL_SETTINGS(eda_simulation)
 # -------------------------------------
@@ -168,4 +153,16 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(Invaders_mist)
 # -------------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/BowlingAlley_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/BowlingAlley_memory.sv
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.sdc
index f91c127c..11d2c7a9 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.sdc	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.sdc	
@@ -87,7 +87,7 @@ set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [g
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {VGA_*}]
 
 #**************************************************************
 # Set Clock Groups
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/Snapshot/BowlingAlley.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/Snapshot/BowlingAlley.rbf
deleted file mode 100644
index 23ba85871cf31c3a3a5d296a6712db686cd6f2af..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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zK7MzfLciHR)fc*?%$k4xTdgh4O9omz`sqzFHOdn>G~E_A(z7Pmg?d2DyiSeu+5+a4
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z=NfcrgmP(cGD{L|ln?#G$v5>{{aA8+npb{z*<{Zwhjdv#Xndo8U5)8}gsD$~zV^a?
zn8QX+^TVICL8&jaJ%0J|t2g^nK>_KvdRiuIK^!=qN16pyWVX!9GBz7`x}`01tQ%Km
zi%U7SfSKdo;F_QPugms1PXb$hJX3EO>6!w^o?ZJKtV3F{T#B9F)jn@t_KapFpB>}B
zxw^b;pU-8VcNM5bMLrw-wr_e>HR_9v-aPeli{eh#LQ7y-JOkieJ66t!TWmx+t}UW`
z@_@)p$-B#a^R$*7hYVlmce#Y7oQYrw0y_iPGGQ}VGDpNR$L3(rjO2cE3}dCgv*cJl
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zIkpInt?QR}w7kJ(q1<0~Cl|yq+t+yQeSH&Hk0srSeo4Pq`rdn%r_XKryl)NkuScW&
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zgPsaHEc8rLLh}VL>aS{TVe3s&D@*SS&B3odtV6a73Nt5_)8cEt(zgL*hBYwnP4_7=
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zc7R{}?J{8t<z3%6CPmZy;C&0l-#dRlyLf5O>gQtlEKj0u^ZIj4K+D?a{)#(S-Mb0r
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diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_mist.sv
index a04fbd65..f5a5a754 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_mist.sv	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_mist.sv	
@@ -19,34 +19,37 @@ module BowlingAlley_mist(
 `include "rtl\build_id.v" 
 
 localparam CONF_STR = {
-	"Bow.Alley;;",
+	"BOWLER;;",
 	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
+	"T0,Reset;",
 	"V,v1.20.",`BUILD_DATE
 };
 
+wire  [1:0] scanlines = status[4:3];
+wire        rotate    = status[2];
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
 
-wire clk_core, clk_sys;
+wire clk_core, clk_vid;
 wire pll_locked;
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(),
 	.c0(clk_core),
-	.c1(clk_sys)
+	.c1(clk_vid)
 );
 
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire  [7:0] kbjoy;
 wire  [7:0] joystick_0,joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
+wire        no_csync;
 wire        key_pressed;
 wire  [7:0] key_code;
 wire        key_strobe;
@@ -67,14 +70,14 @@ wire RWE_n;
 
 
 invaderst invaderst(
-	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Rst_n(~(status[0] | buttons[1])),
 	.Clk(clk_core),
 	.ENA(),
-	.Coin(btn_coin),
-	.Sel1Player(btn_one_player),
-	.Sel2Player(btn_two_players),
-	.Fire(m_fire),
-	.Fire2(m_bomb),
+	.Coin(m_coin1 | m_coin2),
+	.Sel1Player(m_one_player),
+	.Sel2Player(m_two_players),
+	.Fire(m_fireA),
+	.Fire2(m_fireB),
 	.MoveLeft(m_left),
 	.MoveRight(m_right),
 	.DIP("00000000"),
@@ -109,32 +112,33 @@ invaders_audio invaders_audio (
 	.Aud(audio)
 	);		
 	  
-mist_video #(.COLOR_DEPTH(3)) mist_video(
-	.clk_sys(clk_sys),
+mist_video #(.COLOR_DEPTH(1)) mist_video(
+	.clk_sys(clk_vid),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({Video,Video,Video}),
-	.G({Video,Video,Video}),
-	.B({Video,Video,Video}),
-	.HSync(~hs),
-	.VSync(~vs),
+	.R(Video),
+	.G(Video),
+	.B(Video),
+	.HSync(hs),
+	.VSync(vs),
 	.VGA_R(VGA_R),
 	.VGA_G(VGA_G),
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
-	.rotate({1'b1,status[2]}),
+	.rotate({1'b1,rotate}),
 	.scandoubler_disable(scandoublerD),
-	.scanlines(status[4:3]),
+	.scanlines(scanlines),
 	.ce_divider(0),
-	.ypbpr(ypbpr)
+	.ypbpr(ypbpr),
+	.no_csync(no_csync)
 	);
 
 user_io #(
 	.STRLEN(($size(CONF_STR)>>3)))
 user_io(
-	.clk_sys        (clk_sys       ),
+	.clk_sys        (clk_core       ),
 	.conf_str       (CONF_STR       ),
 	.SPI_CLK        (SPI_SCK        ),
 	.SPI_SS_IO      (CONF_DATA0     ),
@@ -144,6 +148,7 @@ user_io(
 	.switches       (switches       ),
 	.scandoubler_disable (scandoublerD	  ),
 	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
 	.key_strobe     (key_strobe     ),
 	.key_pressed    (key_pressed    ),
 	.key_code       (key_code       ),
@@ -153,44 +158,30 @@ user_io(
 	);
 
 dac dac (
-	.clk_i(clk_sys),
+	.clk_i(clk_core),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
 
-wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
 
-always @(posedge clk_sys) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h75: btn_up          <= key_pressed; // up
-			'h72: btn_down        <= key_pressed; // down
-			'h6B: btn_left        <= key_pressed; // left
-			'h74: btn_right       <= key_pressed; // right
-			'h76: btn_coin        <= key_pressed; // ESC
-			'h05: btn_one_player  <= key_pressed; // F1
-			'h06: btn_two_players <= key_pressed; // F2
-			'h14: btn_fire3       <= key_pressed; // ctrl
-			'h11: btn_fire2       <= key_pressed; // alt
-			'h29: btn_fire1       <= key_pressed; // Space
-		endcase
-	end
-end
+arcade_inputs inputs (
+	.clk         ( clk_core    ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b01       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index da01f6b4..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1080 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in  std_logic;
-		CLK_n           : in  std_logic;
-		CEN             : in  std_logic;
-		WAIT_n          : in  std_logic;
-		INT_n           : in  std_logic;
-		NMI_n           : in  std_logic;
-		BUSRQ_n         : in  std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A               : out std_logic_vector(15 downto 0);
-		DInst           : in  std_logic_vector(7 downto 0);
-		DI              : in  std_logic_vector(7 downto 0);
-		DO              : out std_logic_vector(7 downto 0);
-		MC              : out std_logic_vector(2 downto 0);
-		TS              : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone              : std_logic_vector(2 downto 0) := "111";
-	constant aBC                : std_logic_vector(2 downto 0) := "000";
-	constant aDE                : std_logic_vector(2 downto 0) := "001";
-	constant aXY                : std_logic_vector(2 downto 0) := "010";
-	constant aIOA               : std_logic_vector(2 downto 0) := "100";
-	constant aSP                : std_logic_vector(2 downto 0) := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR          => IR,
-			ISet        => ISet,
-			MCycle      => MCycle,
-			F           => F,
-			NMICycle    => NMICycle,
-			IntCycle    => IntCycle,
-			MCycles     => MCycles_d,
-			TStates     => TStates,
-			Prefix      => Prefix,
-			Inc_PC      => Inc_PC,
-			Inc_WZ      => Inc_WZ,
-			IncDec_16   => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op      => ALU_Op,
-			Save_ALU    => Save_ALU,
-			PreserveC   => PreserveC,
-			Arith16     => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ        => IORQ_i,
-			Jump        => Jump,
-			JumpE       => JumpE,
-			JumpXY      => JumpXY,
-			Call        => Call,
-			RstP        => RstP,
-			LDZ         => LDZ,
-			LDW         => LDW,
-			LDSPHL      => LDSPHL,
-			Special_LD  => Special_LD,
-			ExchangeDH  => ExchangeDH,
-			ExchangeRp  => ExchangeRp,
-			ExchangeAF  => ExchangeAF,
-			ExchangeRS  => ExchangeRS,
-			I_DJNZ      => I_DJNZ,
-			I_CPL       => I_CPL,
-			I_CCF       => I_CCF,
-			I_SCF       => I_SCF,
-			I_RETN      => I_RETN,
-			I_BT        => I_BT,
-			I_BC        => I_BC,
-			I_BTR       => I_BTR,
-			I_RLD       => I_RLD,
-			I_RRD       => I_RRD,
-			I_INRC      => I_INRC,
-			SetDI       => SetDI,
-			SetEI       => SetEI,
-			IMode       => IMode,
-			Halt        => Halt,
-			NoRead      => NoRead,
-			Write       => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16     => Z16_r,
-			ALU_Op  => ALU_Op_r,
-			IR      => IR(5 downto 0),
-			ISet    => ISet,
-			BusA    => BusA,
-			BusB    => BusB,
-			F_In    => F,
-			Q       => ALU_Q,
-			F_Out   => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T8080se.vhd
deleted file mode 100644
index 65b92d54..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T8080se.vhd	
+++ /dev/null
@@ -1,194 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- 8080 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original 8080
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---      STACK status output not supported
---
--- File history :
---
---      0237 : First version
---
---      0238 : Updated for T80 interface change
---
---      0240 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T8080se is
-	generic(
-		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK                     : in std_logic;
-		CLKEN           : in std_logic;
-		READY           : in std_logic;
-		HOLD            : in std_logic;
-		INT             : in std_logic;
-		INTE            : out std_logic;
-		DBIN            : out std_logic;
-		SYNC            : out std_logic;
-		VAIT            : out std_logic;
-		HLDA            : out std_logic;
-		WR_n            : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0)
-	);
-end T8080se;
-
-architecture rtl of T8080se is
-
-	signal IntCycle_n   : std_logic;
-	signal NoRead               : std_logic;
-	signal Write                : std_logic;
-	signal IORQ                 : std_logic;
-	signal INT_n                : std_logic;
-	signal HALT_n               : std_logic;
-	signal BUSRQ_n              : std_logic;
-	signal BUSAK_n              : std_logic;
-	signal DO_i                 : std_logic_vector(7 downto 0);
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal TState               : std_logic_vector(2 downto 0);
-	signal One                  : std_logic;
-
-begin
-
-	INT_n <= not INT;
-	BUSRQ_n <= HOLD;
-	HLDA <= not BUSAK_n;
-	SYNC <= '1' when TState = "001" else '0';
-	VAIT <= '1' when TState = "010" else '0';
-	One <= '1';
-
-	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
-	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
-	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
-	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
-	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
-	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
-	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
-	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 0)
-		port map(
-			CEN => CLKEN,
-			M1_n => open,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => open,
-			HALT_n => HALT_n,
-			WAIT_n => READY,
-			INT_n => INT_n,
-			NMI_n => One,
-			RESET_n => RESET_n,
-			BUSRQ_n => One,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO_i,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n,
-			IntE => INTE);
-
-	process (RESET_n, CLK)
-	begin
-		if RESET_n = '0' then
-			DBIN <= '0';
-			WR_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK'event and CLK = '1' then
-			if CLKEN = '1' then
-				DBIN <= '0';
-				WR_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and READY = '0') then
-						DBIN <= IntCycle_n;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
-						DBIN <= '1';
-					end if;
-					if T2Write = 0 then
-						if TState = "010" and Write = '1' then
-							WR_n <= '0';
-						end if;
-					else
-						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
-							WR_n <= '0';
-						end if;
-					end if;
-				end if;
-				if TState = "010" and READY = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index e09def1e..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,361 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 43cea1b5..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1944 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-				  ALU_Op <= "1000";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-				  ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-				  ALU_Op <= "1010";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index 42cf6105..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,217 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 1c0f2638..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---      0242 : Initial release
---
---      0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal      RegsH   : Register_Image(0 to 7);
-	signal      RegsL   : Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/dac.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/dac.vhd
deleted file mode 100644
index db58d70b..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,48 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity dac is
-	generic (
-		C_bits  : integer := 8
-	);
-	port (
-		clk_i   : in  std_logic;
-		res_n_i : in  std_logic;
-		dac_i   : in  std_logic_vector(C_bits-1 downto 0);
-		dac_o   : out std_logic
-	);
-end dac;
-
-architecture rtl of dac is
-	signal sig_in: unsigned(C_bits downto 0);
-begin
-	seq: process(clk_i, res_n_i)
-	begin
-		if res_n_i = '0' then
-			sig_in <= to_unsigned(2**C_bits, sig_in'length);
-			dac_o  <= '0';
-		elsif rising_edge(clk_i) then
-		        -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
-			--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
-			sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
-			dac_o  <= sig_in(C_bits);
-		end if;
-	end process seq;
-end rtl;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders.vhd
index 0a4a7814..8c1f51aa 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders.vhd	
@@ -118,11 +118,12 @@ architecture rtl of invaderst is
 	signal GDB2         : std_logic_vector(7 downto 0);
 	signal GDB3         : std_logic_vector(7 downto 0);
 	signal S            : std_logic_vector(7 downto 0);
+	signal S_Rev        : std_logic_vector(7 downto 0);
 	signal GDB          : std_logic_vector(7 downto 0);
 	signal DB           : std_logic_vector(7 downto 0);
 	signal Sounds       : std_logic_vector(7 downto 0);
 	signal AD_i         : std_logic_vector(15 downto 0);
-	signal PortWr       : std_logic_vector(6 downto 2);
+	signal PortWr       : std_logic_vector(6 downto 1);
 	signal EA           : std_logic_vector(2 downto 0);
 	signal D5           : std_logic_vector(15 downto 0);
 	signal WD_Cnt       : unsigned(7 downto 0);
@@ -194,21 +195,23 @@ begin
 			HSync => HSync,
 			VSync => VSync);
 
-	with AD_i(9 downto 8) select
-		GDB <= GDB0 when "00",
-				GDB1 when "01",
-				GDB2 when "10",
-				GDB3 when "11";
---				S when others;
-				
+	with AD_i(10 downto 8) select
+		GDB <= GDB0 when "010",
+				GDB1 when "100",
+				GDB2 when "101",
+				GDB3 when "110",
+				not S when "001",
+				S_rev when "011",
+				(others=>'0') when others;
+
 	GDB0(0) <= '0';  -- Language
 	GDB0(1) <= '0';  -- Language
 	GDB0(2) <= '0';  -- Demo_Sounds
 	GDB0(3) <= '0';  -- Game_Time 
 	GDB0(4) <= '0';  -- Coinage
 	GDB0(5) <= '0';  -- Difficulty
-	GDB0(6) <= '1';  -- Cabinet
-	GDB0(7) <= '1';  -- Unused
+	GDB0(6) <= '0';  -- Cabinet
+	GDB0(7) <= '0';  -- Unused
 
 	GDB1(0) <= not Coin;-- Active High !
 	GDB1(1) <= not Fire;
@@ -237,6 +240,7 @@ begin
 	GDB3(6) <= '0';  -- TRACKBALL X
 	GDB3(7) <= '0';  -- TRACKBALL X	
 
+	PortWr(1) <= '1' when AD_i(10 downto 8) = "001" and Sample = '1' else '0';
 	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
 	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
 	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
@@ -253,13 +257,13 @@ begin
 			SoundCtrl5 <= (others => '0');
 			OldSample := '0';
 		elsif Clk'event and Clk = '1' then
-			if PortWr(2) = '1' then
+			if PortWr(1) = '1' then
 				EA <= DB(2 downto 0);
 			end if;
 			if PortWr(3) = '1' then
 				SoundCtrl3 <= DB(5 downto 0);
 			end if;
-			if PortWr(4) = '1' and OldSample = '0' then
+			if PortWr(2) = '1' and OldSample = '0' then
 				D5(15 downto 8) <= DB;
 				D5(7 downto 0) <= D5(15 downto 8);
 			end if;
@@ -280,4 +284,5 @@ begin
 			 D5( 9 downto 2) when "110",
 			 D5( 8 downto 1) when others;
 
+	 S_rev <= S(0)&S(1)&S(2)&S(3)&S(4)&S(5)&S(6)&S(7);
 end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.vhd
index f8d0b139..39c09b03 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.vhd	
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************
 
 
@@ -141,13 +141,13 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 27,
+		clk0_divide_by => 1125,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 10,
+		clk0_multiply_by => 416,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 27,
+		clk1_divide_by => 1125,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 20,
+		clk1_multiply_by => 832,
 		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -231,8 +231,8 @@ END SYN;
 -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "9.984000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "19.968000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -260,10 +260,10 @@ END SYN;
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
 -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "9.98400000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "19.96800000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -307,13 +307,13 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "416"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "832"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qsf
index 03524a57..9fea430b 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qsf	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qsf	
@@ -41,25 +41,9 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/GunFight_mist.sv
-set_global_assignment -name VHDL_FILE rtl/invaders.vhd
-set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
-set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/GunFight_memory.sv
-set_global_assignment -name VHDL_FILE rtl/GunFight_overlay.vhd
-set_global_assignment -name VHDL_FILE rtl/sprom.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 
 # Pin & Location Assignments
 # ==========================
@@ -123,7 +107,7 @@ set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
 
 # EDA Netlist Writer Assignments
 # ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
 
 # Assembler Assignments
 # =====================
@@ -147,7 +131,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 	# EDA Netlist Writer Assignments
 	# ==============================
-	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
 
 # end EDA_TOOL_SETTINGS(eda_simulation)
 # -------------------------------------
@@ -175,4 +159,74 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(spaceinvaders_mist)
 # ------------------------------
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/GunFight_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/GunFight_memory.sv
+set_global_assignment -name VHDL_FILE rtl/GunFight_overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp3.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/stp3.stp
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "invaderst:invaderst|Clk" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "invaderst:invaderst|Gun1[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "invaderst:invaderst|Gun1[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "invaderst:invaderst|Gun1[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "invaderst:invaderst|Gun1[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "invaderst:invaderst|Gun2[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "invaderst:invaderst|Gun2[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "invaderst:invaderst|Gun2[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "invaderst:invaderst|Gun2[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "invaderst:invaderst|state1[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "invaderst:invaderst|state1[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "invaderst:invaderst|state1[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "invaderst:invaderst|state2[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "invaderst:invaderst|state2[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "invaderst:invaderst|state2[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "invaderst:invaderst|Gun1[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "invaderst:invaderst|Gun1[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "invaderst:invaderst|Gun1[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "invaderst:invaderst|Gun1[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "invaderst:invaderst|Gun2[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "invaderst:invaderst|Gun2[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "invaderst:invaderst|Gun2[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "invaderst:invaderst|Gun2[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "invaderst:invaderst|state1[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "invaderst:invaderst|state1[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "invaderst:invaderst|state1[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "invaderst:invaderst|state2[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "invaderst:invaderst|state2[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "invaderst:invaderst|state2[2]" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=14" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=14" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=63" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=3917" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=53125" -section_id auto_signaltap_0
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name SLD_FILE db/stp3_auto_stripped.stp
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.sdc
index f91c127c..11d2c7a9 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.sdc	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.sdc	
@@ -87,7 +87,7 @@ set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [g
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {VGA_*}]
 
 #**************************************************************
 # Set Clock Groups
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_mist.sv
index 220eef32..520144a6 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_mist.sv	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_mist.sv	
@@ -19,33 +19,38 @@ module GunFight_mist(
 `include "rtl\build_id.v" 
 
 localparam CONF_STR = {
-	"Gun Fight;;",
+	"GUNFIGHT;;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-//	"O5,Overlay, On, Off;",
-	"T6,Reset;",
+	"O6,Joystick swap,Off,On;",
+	"T0,Reset;",
 	"V,v1.20.",`BUILD_DATE
 };
 
+wire  [1:0] scanlines = status[4:3];
+wire        rotate = 0;
+wire        joyswap = status[6];
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
 
-wire clk_sys;
+wire clk_sys, clk_vid;
 wire pll_locked;
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(),
-	.c0(clk_sys)
+	.c0(clk_sys),
+	.c1(clk_vid)
 );
 
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire  [7:0] kbjoy;
 wire  [7:0] joystick_0,joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
+wire        no_csync;
 wire        key_pressed;
 wire  [7:0] key_code;
 wire        key_strobe;
@@ -68,25 +73,25 @@ wire HSync;
 wire VSync;
 
 invaderst invaderst(
-	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Rst_n(~(status[0] | buttons[1])),
 	.Clk(clk_sys),
 	.ENA(),
-	.Coin(btn_coin),
-	.Sel1Player(btn_one_player),
-	.Fire1(~joystick_0[4]),
-	.Fire2(~joystick_1[4]),
-	.GunUp1(gun1_up),
-	.GunDown1(gun1_dw),
-	.MoveLeft1(~joystick_0[1]),
-	.MoveRight1(~joystick_0[0]),
-	.MoveUp1(~joystick_0[3]),
-	.MoveDown1(~joystick_0[2]),
-	.GunUp2(gun2_up),
-	.GunDown2(gun2_dw),
-	.MoveLeft2(~joystick_1[1]),
-	.MoveRight2(~joystick_1[0]),
-	.MoveUp2(~joystick_1[3]),
-	.MoveDown2(~joystick_1[2]),
+	.Coin(m_coin1 | m_coin2),
+	.Sel1Player(m_one_player),
+	.Fire1(~m_fireA),
+	.Fire2(~m_fire2A),
+	.GunUp1(m_fireB),
+	.GunDown1(m_fireC),
+	.MoveLeft1(~m_left),
+	.MoveRight1(~m_right),
+	.MoveUp1(~m_up),
+	.MoveDown1(~m_down),
+	.GunUp2(m_fire2B),
+	.GunDown2(m_fire2C),
+	.MoveLeft2(~m_left2),
+	.MoveRight2(~m_right2),
+	.MoveUp2(~m_up2),
+	.MoveDown2(~m_down2),
 //	.DIP(dip),
 	.RDB(RDB),
 	.IB(IB),
@@ -119,14 +124,14 @@ invaders_audio invaders_audio (
 	.Aud(audio)
 	);
 
-mist_video #(.COLOR_DEPTH(3)) mist_video(
-	.clk_sys(clk_sys),
+mist_video #(.COLOR_DEPTH(1)) mist_video(
+	.clk_sys(clk_vid),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({Video,Video,Video}),
-	.G({Video,Video,Video}),
-	.B(3'b000),
+	.R(Video),
+	.G(Video),
+	.B(1'b0),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -134,10 +139,12 @@ mist_video #(.COLOR_DEPTH(3)) mist_video(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
+	.rotate({1'b0,rotate}),
 	.scandoubler_disable(scandoublerD),
-	.ce_divider(1),
-	.scanlines(status[4:3]),
-	.ypbpr(ypbpr)
+	.scanlines(scanlines),
+	.ce_divider(1'b0),
+	.ypbpr(ypbpr),
+	.no_csync(no_csync)
 	);
 
 user_io #(
@@ -153,6 +160,7 @@ user_io(
 	.switches       (switches       ),
 	.scandoubler_disable (scandoublerD	  ),
 	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
 	.key_strobe     (key_strobe     ),
 	.key_pressed    (key_pressed    ),
 	.key_code       (key_code       ),
@@ -170,28 +178,24 @@ dac (
 	.dac_o(AUDIO_L)
 	);
 
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
 
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_coin  = 0;
-
-reg gun1_up  = 0;
-reg gun1_dw  = 0;
-reg gun2_up  = 0;
-reg gun2_dw  = 0;
-
-always @(posedge clk_sys) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h76: btn_coin        <= key_pressed; // ESC
-			'h05: btn_one_player  <= key_pressed; // F1
-			'h06: btn_two_players <= key_pressed; // F2
-			'h15: gun1_up       <= key_pressed; // Q
-			'h35: gun1_dw       <= key_pressed; // Y
-			'h75: gun2_up       <= key_pressed; // Arrow up
-			'h72: gun2_dw       <= key_pressed; // Arrow down
-		endcase
-	end
-end
+arcade_inputs inputs (
+	.clk         ( clk_sys     ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b00       ),
+	.joyswap     ( joyswap     ),
+	.oneplayer   ( 1'b0        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index da01f6b4..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1080 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in  std_logic;
-		CLK_n           : in  std_logic;
-		CEN             : in  std_logic;
-		WAIT_n          : in  std_logic;
-		INT_n           : in  std_logic;
-		NMI_n           : in  std_logic;
-		BUSRQ_n         : in  std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A               : out std_logic_vector(15 downto 0);
-		DInst           : in  std_logic_vector(7 downto 0);
-		DI              : in  std_logic_vector(7 downto 0);
-		DO              : out std_logic_vector(7 downto 0);
-		MC              : out std_logic_vector(2 downto 0);
-		TS              : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone              : std_logic_vector(2 downto 0) := "111";
-	constant aBC                : std_logic_vector(2 downto 0) := "000";
-	constant aDE                : std_logic_vector(2 downto 0) := "001";
-	constant aXY                : std_logic_vector(2 downto 0) := "010";
-	constant aIOA               : std_logic_vector(2 downto 0) := "100";
-	constant aSP                : std_logic_vector(2 downto 0) := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR          => IR,
-			ISet        => ISet,
-			MCycle      => MCycle,
-			F           => F,
-			NMICycle    => NMICycle,
-			IntCycle    => IntCycle,
-			MCycles     => MCycles_d,
-			TStates     => TStates,
-			Prefix      => Prefix,
-			Inc_PC      => Inc_PC,
-			Inc_WZ      => Inc_WZ,
-			IncDec_16   => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op      => ALU_Op,
-			Save_ALU    => Save_ALU,
-			PreserveC   => PreserveC,
-			Arith16     => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ        => IORQ_i,
-			Jump        => Jump,
-			JumpE       => JumpE,
-			JumpXY      => JumpXY,
-			Call        => Call,
-			RstP        => RstP,
-			LDZ         => LDZ,
-			LDW         => LDW,
-			LDSPHL      => LDSPHL,
-			Special_LD  => Special_LD,
-			ExchangeDH  => ExchangeDH,
-			ExchangeRp  => ExchangeRp,
-			ExchangeAF  => ExchangeAF,
-			ExchangeRS  => ExchangeRS,
-			I_DJNZ      => I_DJNZ,
-			I_CPL       => I_CPL,
-			I_CCF       => I_CCF,
-			I_SCF       => I_SCF,
-			I_RETN      => I_RETN,
-			I_BT        => I_BT,
-			I_BC        => I_BC,
-			I_BTR       => I_BTR,
-			I_RLD       => I_RLD,
-			I_RRD       => I_RRD,
-			I_INRC      => I_INRC,
-			SetDI       => SetDI,
-			SetEI       => SetEI,
-			IMode       => IMode,
-			Halt        => Halt,
-			NoRead      => NoRead,
-			Write       => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16     => Z16_r,
-			ALU_Op  => ALU_Op_r,
-			IR      => IR(5 downto 0),
-			ISet    => ISet,
-			BusA    => BusA,
-			BusB    => BusB,
-			F_In    => F,
-			Q       => ALU_Q,
-			F_Out   => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T8080se.vhd
deleted file mode 100644
index 65b92d54..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T8080se.vhd	
+++ /dev/null
@@ -1,194 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- 8080 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original 8080
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---      STACK status output not supported
---
--- File history :
---
---      0237 : First version
---
---      0238 : Updated for T80 interface change
---
---      0240 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T8080se is
-	generic(
-		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK                     : in std_logic;
-		CLKEN           : in std_logic;
-		READY           : in std_logic;
-		HOLD            : in std_logic;
-		INT             : in std_logic;
-		INTE            : out std_logic;
-		DBIN            : out std_logic;
-		SYNC            : out std_logic;
-		VAIT            : out std_logic;
-		HLDA            : out std_logic;
-		WR_n            : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0)
-	);
-end T8080se;
-
-architecture rtl of T8080se is
-
-	signal IntCycle_n   : std_logic;
-	signal NoRead               : std_logic;
-	signal Write                : std_logic;
-	signal IORQ                 : std_logic;
-	signal INT_n                : std_logic;
-	signal HALT_n               : std_logic;
-	signal BUSRQ_n              : std_logic;
-	signal BUSAK_n              : std_logic;
-	signal DO_i                 : std_logic_vector(7 downto 0);
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal TState               : std_logic_vector(2 downto 0);
-	signal One                  : std_logic;
-
-begin
-
-	INT_n <= not INT;
-	BUSRQ_n <= HOLD;
-	HLDA <= not BUSAK_n;
-	SYNC <= '1' when TState = "001" else '0';
-	VAIT <= '1' when TState = "010" else '0';
-	One <= '1';
-
-	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
-	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
-	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
-	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
-	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
-	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
-	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
-	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 0)
-		port map(
-			CEN => CLKEN,
-			M1_n => open,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => open,
-			HALT_n => HALT_n,
-			WAIT_n => READY,
-			INT_n => INT_n,
-			NMI_n => One,
-			RESET_n => RESET_n,
-			BUSRQ_n => One,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO_i,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n,
-			IntE => INTE);
-
-	process (RESET_n, CLK)
-	begin
-		if RESET_n = '0' then
-			DBIN <= '0';
-			WR_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK'event and CLK = '1' then
-			if CLKEN = '1' then
-				DBIN <= '0';
-				WR_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and READY = '0') then
-						DBIN <= IntCycle_n;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
-						DBIN <= '1';
-					end if;
-					if T2Write = 0 then
-						if TState = "010" and Write = '1' then
-							WR_n <= '0';
-						end if;
-					else
-						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
-							WR_n <= '0';
-						end if;
-					end if;
-				end if;
-				if TState = "010" and READY = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index e09def1e..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,361 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 43cea1b5..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1944 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-				  ALU_Op <= "1000";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-				  ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-				  ALU_Op <= "1010";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index 42cf6105..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,217 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 1c0f2638..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---      0242 : Initial release
---
---      0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal      RegsH   : Register_Image(0 to 7);
-	signal      RegsL   : Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders.vhd
index e29e4774..c7dc4e73 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders.vhd	
@@ -138,28 +138,49 @@ architecture rtl of invaderst is
 	signal WD_Cnt       : unsigned(7 downto 0);
 	signal Sample       : std_logic;
 	signal Rst_n_s_i    : std_logic;
-	signal gun1           : std_logic_vector(3 downto 0);
-	signal gun2           : std_logic_vector(3 downto 0);
+	signal Gun1         : std_logic_vector(3 downto 0);
+	signal Gun2         : std_logic_vector(3 downto 0);
+	signal GunUp1_d     : std_logic;
+	signal GunDown1_d   : std_logic;
+	signal GunUp2_d     : std_logic;
+	signal GunDown2_d   : std_logic;
 
 signal state1 : unsigned(2 downto 0);
 signal state2 : unsigned(2 downto 0);
 
 type gun_array is array(0 to  6) of std_logic_vector(3 downto 0);
-signal gun: gun_array := (
+signal gunstates1: gun_array := (
 		X"6",X"2",X"0",X"4",X"5",X"1",X"3");
+		--"110","010","000","100","101","001","011"
+signal gunstates2: gun_array := (
+		X"4",X"6",X"2",X"3",X"7",X"5",X"1");
+		--"100","110","010","011","111","101","001"
+begin
+
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			state1 <= "000";
+			state2 <= "000";
+		elsif Clk'event and Clk = '1' then
+			GunUp1_d <= GunUp1;
+			GunDown1_d <= GunDown1;
+			if GunUp1 = '1' and GunUp1_d = '0' and not (state1 = 6) then state1 <= state1 + 1;
+			elsif GunDown1 = '1' and GunDown1_d = '0' and not (state1 = 0)  then state1 <= state1 - 1;
+			end if;
+
+			GunUp2_d <= GunUp2;
+			GunDown2_d <= GunDown2;
+			if GunUp2 = '1' and GunUp2_d = '0' and not (state2 = 6) then state2 <= state2 + 1;
+			elsif GunDown2 = '1' and GunDown2_d = '0' and not (state2 = 0)  then state2 <= state2 - 1;
+			end if;
+
+			Gun1 <= gunstates1(to_integer(state1));
+			Gun2 <= gunstates2(to_integer(state2));
+
+		end if; 
+	end process;
 	
-begin
-
-process (Clk, GunUp1, GunUp2, GunDown1, GunDown2)
-begin
-if Clk = '1' then
- if GunUp1 = '1' and not (state1 = 6) then state1 <= state1 + 1; elsif
-	 GunDown1 = '1' and not (state1 = 0)  then state1 <= state1 - 1; elsif
-	 GunUp2 = '1'  and not (state2 = 6) then state2 <= state2 + 1; elsif
-	 GunDown2 = '1'  and not (state2 = 0) then state2 <= state2 - 1; end if;	
-	end if; 
-end process;
-
 	Rst_n_s <= Rst_n_s_i;
 	RWD <= DB;
 	AD <= AD_i;
@@ -230,24 +251,22 @@ with AD_i(9 downto 8) select
 					GDB2 when "10",
 						S when others;
 				
---GDB <= GDB0 and GDB1 and GDB2 and S;--todo
-
 	GDB0(0) <= not MoveUp1;
 	GDB0(1) <= not MoveDown1;
 	GDB0(2) <= not MoveLeft1;
 	GDB0(3) <= not MoveRight1;
-	GDB0(4) <= not Gun1(0);--todo
-	GDB0(5) <= not Gun1(1);--todo
-	GDB0(6) <= not Gun1(2);--todo
+	GDB0(4) <= not Gun1(0);
+	GDB0(5) <= not Gun1(1);
+	GDB0(6) <= not Gun1(2);
 	GDB0(7) <= not Fire1;
 
 	GDB1(0) <= not MoveUp2;
 	GDB1(1) <= not MoveDown2;
 	GDB1(2) <= not MoveLeft2;
 	GDB1(3) <= not MoveRight2;
-	GDB1(4) <= Gun2(0);--todo
-	GDB1(5) <= Gun2(1);--todo
-	GDB1(6) <= Gun2(2);--todo
+	GDB1(4) <= Gun2(0);
+	GDB1(5) <= Gun2(1);
+	GDB1(6) <= Gun2(2);
 	GDB1(7) <= not Fire2;
 
 	GDB2(0) <= '0';--Coinage
@@ -274,8 +293,6 @@ with AD_i(9 downto 8) select
 			SoundCtrl3 <= (others => '0');
 			SoundCtrl5 <= (others => '0');
 			OldSample := '0';
-			gun1 <= gun(to_integer(state1));
-			gun2 <= gun(to_integer(state2));
 		elsif Clk'event and Clk = '1' then
 			if PortWr(2) = '1' then
 				EA <= DB(2 downto 0);
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.vhd
index d65b9f9b..39c09b03 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.vhd	
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************
 
 
@@ -43,7 +43,8 @@ ENTITY pll IS
 	PORT
 	(
 		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC 
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
 	);
 END pll;
 
@@ -53,9 +54,10 @@ ARCHITECTURE SYN OF pll IS
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
 	SIGNAL sub_wire1	: STD_LOGIC ;
 	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire4_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 
 
@@ -66,6 +68,10 @@ ARCHITECTURE SYN OF pll IS
 		clk0_duty_cycle		: NATURAL;
 		clk0_multiply_by		: NATURAL;
 		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
 		compensate_clock		: STRING;
 		inclk0_input_frequency		: NATURAL;
 		intended_device_family		: STRING;
@@ -123,20 +129,26 @@ ARCHITECTURE SYN OF pll IS
 	END COMPONENT;
 
 BEGIN
-	sub_wire4_bv(0 DOWNTO 0) <= "0";
-	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
 	sub_wire1    <= sub_wire0(0);
 	c0    <= sub_wire1;
-	sub_wire2    <= inclk0;
-	sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
 
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 27,
+		clk0_divide_by => 1125,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 10,
+		clk0_multiply_by => 416,
 		clk0_phase_shift => "0",
+		clk1_divide_by => 1125,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 832,
+		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
 		intended_device_family => "Cyclone III",
@@ -170,7 +182,7 @@ BEGIN
 		port_scanread => "PORT_UNUSED",
 		port_scanwrite => "PORT_UNUSED",
 		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_UNUSED",
+		port_clk1 => "PORT_USED",
 		port_clk2 => "PORT_UNUSED",
 		port_clk3 => "PORT_UNUSED",
 		port_clk4 => "PORT_UNUSED",
@@ -188,7 +200,7 @@ BEGIN
 		width_clock => 5
 	)
 	PORT MAP (
-		inclk => sub_wire3,
+		inclk => sub_wire4,
 		clk => sub_wire0
 	);
 
@@ -216,8 +228,11 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "9.984000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "19.968000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -238,18 +253,26 @@ END SYN;
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
 -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "9.98400000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "19.96800000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -272,19 +295,26 @@ END SYN;
 -- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
 -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "416"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1125"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "832"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -317,7 +347,7 @@ END SYN;
 -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
 -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -336,10 +366,12 @@ END SYN;
 -- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
 -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
 -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.sdc
index f91c127c..11d2c7a9 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.sdc	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.sdc	
@@ -87,7 +87,7 @@ set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [g
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {VGA_*}]
 
 #**************************************************************
 # Set Clock Groups
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_mist.sv
index e09110e2..10dcf7c2 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_mist.sv	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_mist.sv	
@@ -19,34 +19,38 @@ module LunarRescue_mist(
 `include "rtl\build_id.v" 
 
 localparam CONF_STR = {
-	"Lunar Resc.;;",
+	"LRESCUE;;",
 	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-	"O5,Overlay, On, Off;",
-	"T6,Reset;",
+	"O5,Overlay,On,Off;",
+	"T0,Reset;",
 	"V,v1.20.",`BUILD_DATE
 };
 
+wire  [1:0] scanlines = status[4:3];
+wire        rotate    = status[2];
+wire        overlay   = status[5];
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
-
-wire clk_sys;
+wire clk_sys, clk_vid;
 wire pll_locked;
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(),
-	.c0(clk_sys)
+	.c0(clk_sys),
+	.c1(clk_vid)
 );
 
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire  [7:0] kbjoy;
 wire  [7:0] joystick_0,joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
+wire        no_csync;
 wire        key_pressed;
 wire  [7:0] key_code;
 wire        key_strobe;
@@ -70,13 +74,13 @@ wire HSync;
 wire VSync;
 
 invaderst invaderst(
-	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Rst_n(~(status[0] | buttons[1])),
 	.Clk(clk_sys),
 	.ENA(),
-	.Coin(btn_coin),
-	.Sel1Player(~btn_one_player),
-	.Sel2Player(~btn_two_players),
-	.Fire(~m_fire),
+	.Coin(m_coin1 | m_coin2),
+	.Sel1Player(~m_one_player),
+	.Sel2Player(~m_two_players),
+	.Fire(~m_fireA),
 	.MoveLeft(~m_left),
 	.MoveRight(~m_right),
 	.DIP(dip),
@@ -114,7 +118,7 @@ invaders_audio invaders_audio (
 	  
 LunarRescue_Overlay LunarRescue_Overlay (
 	.Video(Video),
-	.Overlay(~status[5]),
+	.Overlay(~overlay),
 	.CLK(clk_sys),
 	.Rst_n_s(Rst_n_s),
 	.HSync(HSync),
@@ -127,14 +131,14 @@ LunarRescue_Overlay LunarRescue_Overlay (
 	.O_VSYNC(vs)
 	);
 
-mist_video #(.COLOR_DEPTH(3)) mist_video(
-	.clk_sys(clk_sys),
+mist_video #(.COLOR_DEPTH(1)) mist_video(
+	.clk_sys(clk_vid),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({r,r,r}),
-	.G({g,g,g}),
-	.B({b,b,b}),
+	.R(r),
+	.G(g),
+	.B(b),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -142,11 +146,12 @@ mist_video #(.COLOR_DEPTH(3)) mist_video(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),
+	.rotate({1'b0,rotate}),
 	.scandoubler_disable(scandoublerD),
-	.scanlines(status[4:3]),
-	.ce_divider(1),
-	.ypbpr(ypbpr)
+	.scanlines(scanlines),
+	.ce_divider(1'b0),
+	.ypbpr(ypbpr),
+	.no_csync(no_csync)
 	);
 
 user_io #(
@@ -162,6 +167,7 @@ user_io(
 	.switches       (switches       ),
 	.scandoubler_disable (scandoublerD	  ),
 	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
 	.key_strobe     (key_strobe     ),
 	.key_pressed    (key_pressed    ),
 	.key_code       (key_code       ),
@@ -177,33 +183,24 @@ dac dac (
 	.dac_o(AUDIO_L)
 	);
 
-wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_coin  = 0;
-
-always @(posedge clk_sys) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h75: btn_up          <= key_pressed; // up
-			'h72: btn_down        <= key_pressed; // down
-			'h6B: btn_left        <= key_pressed; // left
-			'h74: btn_right       <= key_pressed; // right
-			'h76: btn_coin        <= key_pressed; // ESC
-			'h05: btn_one_player  <= key_pressed; // F1
-			'h06: btn_two_players <= key_pressed; // F2
-			'h29: btn_fire1       <= key_pressed; // Space
-		endcase
-	end
-end
-
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
 
+arcade_inputs inputs (
+	.clk         ( clk_sys     ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b01       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.vhd
index d65b9f9b..39c09b03 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.vhd	
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************
 
 
@@ -43,7 +43,8 @@ ENTITY pll IS
 	PORT
 	(
 		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC 
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
 	);
 END pll;
 
@@ -53,9 +54,10 @@ ARCHITECTURE SYN OF pll IS
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
 	SIGNAL sub_wire1	: STD_LOGIC ;
 	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire4_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 
 
@@ -66,6 +68,10 @@ ARCHITECTURE SYN OF pll IS
 		clk0_duty_cycle		: NATURAL;
 		clk0_multiply_by		: NATURAL;
 		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
 		compensate_clock		: STRING;
 		inclk0_input_frequency		: NATURAL;
 		intended_device_family		: STRING;
@@ -123,20 +129,26 @@ ARCHITECTURE SYN OF pll IS
 	END COMPONENT;
 
 BEGIN
-	sub_wire4_bv(0 DOWNTO 0) <= "0";
-	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
 	sub_wire1    <= sub_wire0(0);
 	c0    <= sub_wire1;
-	sub_wire2    <= inclk0;
-	sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
 
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 27,
+		clk0_divide_by => 1125,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 10,
+		clk0_multiply_by => 416,
 		clk0_phase_shift => "0",
+		clk1_divide_by => 1125,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 832,
+		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
 		intended_device_family => "Cyclone III",
@@ -170,7 +182,7 @@ BEGIN
 		port_scanread => "PORT_UNUSED",
 		port_scanwrite => "PORT_UNUSED",
 		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_UNUSED",
+		port_clk1 => "PORT_USED",
 		port_clk2 => "PORT_UNUSED",
 		port_clk3 => "PORT_UNUSED",
 		port_clk4 => "PORT_UNUSED",
@@ -188,7 +200,7 @@ BEGIN
 		width_clock => 5
 	)
 	PORT MAP (
-		inclk => sub_wire3,
+		inclk => sub_wire4,
 		clk => sub_wire0
 	);
 
@@ -216,8 +228,11 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "9.984000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "19.968000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -238,18 +253,26 @@ END SYN;
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
 -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "9.98400000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "19.96800000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -272,19 +295,26 @@ END SYN;
 -- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
 -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "416"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1125"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "832"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -317,7 +347,7 @@ END SYN;
 -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
 -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -336,10 +366,12 @@ END SYN;
 -- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
 -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
 -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qsf
index 448dd251..a64d0a95 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qsf	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qsf	
@@ -41,26 +41,10 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Invaders2_mist.sv
-set_global_assignment -name VHDL_FILE rtl/invaders.vhd
-set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
-set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/invaders_memory.sv
 #set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name VHDL_FILE rtl/sprom.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/invaders_video.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 
 # Pin & Location Assignments
 # ==========================
@@ -170,4 +154,18 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(Invaders_mist)
 # -------------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Invaders2_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/invaders_memory.sv
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_video.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name CDF_FILE output_files/Chain1.cdf
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.sdc
index f91c127c..11d2c7a9 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.sdc	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.sdc	
@@ -87,7 +87,7 @@ set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [g
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {VGA_*}]
 
 #**************************************************************
 # Set Clock Groups
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/Invaders2_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/Invaders2_mist.sv
index 8cf901c0..bab17a52 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/Invaders2_mist.sv	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/Invaders2_mist.sv	
@@ -19,34 +19,40 @@ module Invaders2_mist(
 `include "rtl\build_id.v" 
 
 localparam CONF_STR = {
-	"Space Inv.2;;",
+	"INVAD2CT;;",
 	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-	"O5,Overlay, On, Off;",
-	"T6,Reset;",
+	"O5,Overlay,On,Off;",
+	"O6,Joystick Swap,Off,On;",
+	"T0,Reset;",
 	"V,v1.20.",`BUILD_DATE
 };
 
+wire  [1:0] scanlines = status[4:3];
+wire        rotate    = status[2];
+wire        overlay   = status[5];
+wire        joyswap   = status[6];
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
-
-wire clk_sys;
+wire clk_sys, clk_vid;
 wire pll_locked;
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(),
-	.c0(clk_sys)
+	.c0(clk_sys),
+	.c1(clk_vid)
 );
 
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire  [7:0] kbjoy;
 wire  [7:0] joystick_0,joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
+wire        no_csync;
 wire        key_pressed;
 wire  [7:0] key_code;
 wire        key_strobe;
@@ -69,15 +75,18 @@ wire HSync;
 wire VSync;
 
 invaderst invaderst(
-	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Rst_n(~(status[0] | buttons[1])),
 	.Clk(clk_sys),
 	.ENA(),
-	.Coin(btn_coin),
-	.Sel1Player(~btn_one_player),
-	.Sel2Player(~btn_two_players),
-	.Fire(~m_fire),
-	.MoveLeft(~m_left),
-	.MoveRight(~m_right),
+	.Coin(m_coin1 | m_coin2),
+	.Sel1Player(~m_one_player),
+	.Sel2Player(~m_two_players),
+	.FireA(~m_fireA),
+	.MoveLeftA(~m_left),
+	.MoveRightA(~m_right),
+	.FireB(~m_fire2A),
+	.MoveLeftB(rotate ? ~m_right2 : ~m_left2),
+	.MoveRightB(rotate ? ~m_left2 : ~m_right2),
 	.DIP(dip),
 	.RDB(RDB),
 	.IB(IB),
@@ -124,14 +133,14 @@ invaders_video invaders_video (
 	.O_VSYNC(vs)
 	);
 
-mist_video #(.COLOR_DEPTH(3)) mist_video(
-	.clk_sys(clk_sys),
+mist_video #(.COLOR_DEPTH(1)) mist_video(
+	.clk_sys(clk_vid),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({r,r,r}),
-	.G({g,g,g}),
-	.B({b,b,b}),
+	.R(r),
+	.G(g),
+	.B(b),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -139,11 +148,12 @@ mist_video #(.COLOR_DEPTH(3)) mist_video(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),
+	.rotate({1'b1,rotate}),
 	.scandoubler_disable(scandoublerD),
-	.scanlines(status[4:3]),
-	.ce_divider(1),
-	.ypbpr(ypbpr)
+	.scanlines(scanlines),
+	.ce_divider(1'b0),
+	.ypbpr(ypbpr),
+	.no_csync(no_csync)
 	);
 
 user_io #(
@@ -159,6 +169,7 @@ user_io(
 	.switches       (switches       ),
 	.scandoubler_disable (scandoublerD	  ),
 	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
 	.key_strobe     (key_strobe     ),
 	.key_pressed    (key_pressed    ),
 	.key_code       (key_code       ),
@@ -167,45 +178,32 @@ user_io(
 	.status         (status         )
 	);
 
+
 dac dac (
 	.clk_i(clk_sys),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
+	
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
 
-wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-
-always @(posedge clk_sys) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h75: btn_up          <= key_pressed; // up
-			'h72: btn_down        <= key_pressed; // down
-			'h6B: btn_left        <= key_pressed; // left
-			'h74: btn_right       <= key_pressed; // right
-			'h76: btn_coin        <= key_pressed; // ESC
-			'h05: btn_one_player  <= key_pressed; // F1
-			'h06: btn_two_players <= key_pressed; // F2
-			'h14: btn_fire3       <= key_pressed; // ctrl
-			'h11: btn_fire2       <= key_pressed; // alt
-			'h29: btn_fire1       <= key_pressed; // Space
-		endcase
-	end
-end
+arcade_inputs inputs (
+	.clk         ( clk_sys     ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b11       ),
+	.joyswap     ( joyswap     ),
+	.oneplayer   ( 1'b0        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index da01f6b4..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1080 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in  std_logic;
-		CLK_n           : in  std_logic;
-		CEN             : in  std_logic;
-		WAIT_n          : in  std_logic;
-		INT_n           : in  std_logic;
-		NMI_n           : in  std_logic;
-		BUSRQ_n         : in  std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A               : out std_logic_vector(15 downto 0);
-		DInst           : in  std_logic_vector(7 downto 0);
-		DI              : in  std_logic_vector(7 downto 0);
-		DO              : out std_logic_vector(7 downto 0);
-		MC              : out std_logic_vector(2 downto 0);
-		TS              : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone              : std_logic_vector(2 downto 0) := "111";
-	constant aBC                : std_logic_vector(2 downto 0) := "000";
-	constant aDE                : std_logic_vector(2 downto 0) := "001";
-	constant aXY                : std_logic_vector(2 downto 0) := "010";
-	constant aIOA               : std_logic_vector(2 downto 0) := "100";
-	constant aSP                : std_logic_vector(2 downto 0) := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR          => IR,
-			ISet        => ISet,
-			MCycle      => MCycle,
-			F           => F,
-			NMICycle    => NMICycle,
-			IntCycle    => IntCycle,
-			MCycles     => MCycles_d,
-			TStates     => TStates,
-			Prefix      => Prefix,
-			Inc_PC      => Inc_PC,
-			Inc_WZ      => Inc_WZ,
-			IncDec_16   => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op      => ALU_Op,
-			Save_ALU    => Save_ALU,
-			PreserveC   => PreserveC,
-			Arith16     => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ        => IORQ_i,
-			Jump        => Jump,
-			JumpE       => JumpE,
-			JumpXY      => JumpXY,
-			Call        => Call,
-			RstP        => RstP,
-			LDZ         => LDZ,
-			LDW         => LDW,
-			LDSPHL      => LDSPHL,
-			Special_LD  => Special_LD,
-			ExchangeDH  => ExchangeDH,
-			ExchangeRp  => ExchangeRp,
-			ExchangeAF  => ExchangeAF,
-			ExchangeRS  => ExchangeRS,
-			I_DJNZ      => I_DJNZ,
-			I_CPL       => I_CPL,
-			I_CCF       => I_CCF,
-			I_SCF       => I_SCF,
-			I_RETN      => I_RETN,
-			I_BT        => I_BT,
-			I_BC        => I_BC,
-			I_BTR       => I_BTR,
-			I_RLD       => I_RLD,
-			I_RRD       => I_RRD,
-			I_INRC      => I_INRC,
-			SetDI       => SetDI,
-			SetEI       => SetEI,
-			IMode       => IMode,
-			Halt        => Halt,
-			NoRead      => NoRead,
-			Write       => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16     => Z16_r,
-			ALU_Op  => ALU_Op_r,
-			IR      => IR(5 downto 0),
-			ISet    => ISet,
-			BusA    => BusA,
-			BusB    => BusB,
-			F_In    => F,
-			Q       => ALU_Q,
-			F_Out   => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T8080se.vhd
deleted file mode 100644
index 65b92d54..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T8080se.vhd	
+++ /dev/null
@@ -1,194 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- 8080 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original 8080
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---      STACK status output not supported
---
--- File history :
---
---      0237 : First version
---
---      0238 : Updated for T80 interface change
---
---      0240 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T8080se is
-	generic(
-		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK                     : in std_logic;
-		CLKEN           : in std_logic;
-		READY           : in std_logic;
-		HOLD            : in std_logic;
-		INT             : in std_logic;
-		INTE            : out std_logic;
-		DBIN            : out std_logic;
-		SYNC            : out std_logic;
-		VAIT            : out std_logic;
-		HLDA            : out std_logic;
-		WR_n            : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0)
-	);
-end T8080se;
-
-architecture rtl of T8080se is
-
-	signal IntCycle_n   : std_logic;
-	signal NoRead               : std_logic;
-	signal Write                : std_logic;
-	signal IORQ                 : std_logic;
-	signal INT_n                : std_logic;
-	signal HALT_n               : std_logic;
-	signal BUSRQ_n              : std_logic;
-	signal BUSAK_n              : std_logic;
-	signal DO_i                 : std_logic_vector(7 downto 0);
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal TState               : std_logic_vector(2 downto 0);
-	signal One                  : std_logic;
-
-begin
-
-	INT_n <= not INT;
-	BUSRQ_n <= HOLD;
-	HLDA <= not BUSAK_n;
-	SYNC <= '1' when TState = "001" else '0';
-	VAIT <= '1' when TState = "010" else '0';
-	One <= '1';
-
-	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
-	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
-	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
-	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
-	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
-	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
-	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
-	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 0)
-		port map(
-			CEN => CLKEN,
-			M1_n => open,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => open,
-			HALT_n => HALT_n,
-			WAIT_n => READY,
-			INT_n => INT_n,
-			NMI_n => One,
-			RESET_n => RESET_n,
-			BUSRQ_n => One,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO_i,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n,
-			IntE => INTE);
-
-	process (RESET_n, CLK)
-	begin
-		if RESET_n = '0' then
-			DBIN <= '0';
-			WR_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK'event and CLK = '1' then
-			if CLKEN = '1' then
-				DBIN <= '0';
-				WR_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and READY = '0') then
-						DBIN <= IntCycle_n;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
-						DBIN <= '1';
-					end if;
-					if T2Write = 0 then
-						if TState = "010" and Write = '1' then
-							WR_n <= '0';
-						end if;
-					else
-						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
-							WR_n <= '0';
-						end if;
-					end if;
-				end if;
-				if TState = "010" and READY = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index e09def1e..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,361 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 43cea1b5..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1944 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-				  ALU_Op <= "1000";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-				  ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-				  ALU_Op <= "1010";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index 42cf6105..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,217 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 1c0f2638..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---      0242 : Initial release
---
---      0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal      RegsH   : Register_Image(0 to 7);
-	signal      RegsL   : Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/dac.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/dac.vhd
deleted file mode 100644
index db58d70b..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,48 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity dac is
-	generic (
-		C_bits  : integer := 8
-	);
-	port (
-		clk_i   : in  std_logic;
-		res_n_i : in  std_logic;
-		dac_i   : in  std_logic_vector(C_bits-1 downto 0);
-		dac_o   : out std_logic
-	);
-end dac;
-
-architecture rtl of dac is
-	signal sig_in: unsigned(C_bits downto 0);
-begin
-	seq: process(clk_i, res_n_i)
-	begin
-		if res_n_i = '0' then
-			sig_in <= to_unsigned(2**C_bits, sig_in'length);
-			dac_o  <= '0';
-		elsif rising_edge(clk_i) then
-		        -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
-			--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
-			sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
-			dac_o  <= sig_in(C_bits);
-		end if;
-	end process seq;
-end rtl;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders.vhd
index a509baa4..24356363 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders.vhd	
@@ -62,9 +62,12 @@ entity invaderst is
 		Coin            : in  std_logic;
 		Sel1Player      : in  std_logic;
 		Sel2Player      : in  std_logic;
-		Fire            : in  std_logic;
-		MoveLeft        : in  std_logic;
-		MoveRight       : in  std_logic;
+		FireA           : in  std_logic;
+		MoveLeftA       : in  std_logic;
+		MoveRightA      : in  std_logic;
+		FireB           : in  std_logic;
+		MoveLeftB       : in  std_logic;
+		MoveRightB      : in  std_logic;
 		DIP             : in  std_logic_vector(8 downto 1);
 		RDB             : in  std_logic_vector(7 downto 0);
 		IB              : in  std_logic_vector(7 downto 0);
@@ -202,27 +205,27 @@ begin
 	GDB0(1) <= '1';--DIP(7);
 	GDB0(2) <= '1';--DIP(6);  -- Unused ?
 	GDB0(3) <= '1';             -- Unused ?
-	GDB0(4) <= not Fire;
-	GDB0(5) <= not MoveLeft;
-	GDB0(6) <= not MoveRight;
+	GDB0(4) <= '1';
+	GDB0(5) <= '1';
+	GDB0(6) <= '1';
 	GDB0(7) <= '1';--DIP(5);  -- Unused ?
 
 	GDB1(0) <= not Coin;-- Active High !
 	GDB1(1) <= not Sel2Player;
 	GDB1(2) <= not Sel1Player;
 	GDB1(3) <= '1';-- Unused ?
-	GDB1(4) <= not Fire;
-	GDB1(5) <= not MoveLeft;
-	GDB1(6) <= not MoveRight;
+	GDB1(4) <= not FireA;
+	GDB1(5) <= not MoveRightA;
+	GDB1(6) <= not MoveLeftA;
 	GDB1(7) <= '1';-- Unused ?
 
 	GDB2(0) <= '1';--DIP(4);  -- LSB Lives 3-6
 	GDB2(1) <= '1';--DIP(3);  -- MSB Lives 3-6
 	GDB2(2) <= '0';-- Tilt ?
 	GDB2(3) <= '0';--DIP(2);  -- Bonus life at 1000 or 1500
-	GDB2(4) <= not Fire;
-	GDB2(5) <= not MoveLeft;
-	GDB2(6) <= not MoveRight;
+	GDB2(4) <= not FireB;
+	GDB2(5) <= not MoveRightB;
+	GDB2(6) <= not MoveLeftB;
 	GDB2(7) <= '1';--DIP(1);  -- Coin info
 
 	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.vhd
index d65b9f9b..39c09b03 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.vhd	
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************
 
 
@@ -43,7 +43,8 @@ ENTITY pll IS
 	PORT
 	(
 		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC 
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
 	);
 END pll;
 
@@ -53,9 +54,10 @@ ARCHITECTURE SYN OF pll IS
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
 	SIGNAL sub_wire1	: STD_LOGIC ;
 	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire4_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 
 
@@ -66,6 +68,10 @@ ARCHITECTURE SYN OF pll IS
 		clk0_duty_cycle		: NATURAL;
 		clk0_multiply_by		: NATURAL;
 		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
 		compensate_clock		: STRING;
 		inclk0_input_frequency		: NATURAL;
 		intended_device_family		: STRING;
@@ -123,20 +129,26 @@ ARCHITECTURE SYN OF pll IS
 	END COMPONENT;
 
 BEGIN
-	sub_wire4_bv(0 DOWNTO 0) <= "0";
-	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
 	sub_wire1    <= sub_wire0(0);
 	c0    <= sub_wire1;
-	sub_wire2    <= inclk0;
-	sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
 
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 27,
+		clk0_divide_by => 1125,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 10,
+		clk0_multiply_by => 416,
 		clk0_phase_shift => "0",
+		clk1_divide_by => 1125,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 832,
+		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
 		intended_device_family => "Cyclone III",
@@ -170,7 +182,7 @@ BEGIN
 		port_scanread => "PORT_UNUSED",
 		port_scanwrite => "PORT_UNUSED",
 		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_UNUSED",
+		port_clk1 => "PORT_USED",
 		port_clk2 => "PORT_UNUSED",
 		port_clk3 => "PORT_UNUSED",
 		port_clk4 => "PORT_UNUSED",
@@ -188,7 +200,7 @@ BEGIN
 		width_clock => 5
 	)
 	PORT MAP (
-		inclk => sub_wire3,
+		inclk => sub_wire4,
 		clk => sub_wire0
 	);
 
@@ -216,8 +228,11 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "9.984000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "19.968000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -238,18 +253,26 @@ END SYN;
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
 -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "9.98400000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "19.96800000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -272,19 +295,26 @@ END SYN;
 -- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
 -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "416"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1125"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "832"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -317,7 +347,7 @@ END SYN;
 -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
 -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -336,10 +366,12 @@ END SYN;
 -- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
 -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
 -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qsf
index cd1d8ca2..9fb947e5 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qsf	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qsf	
@@ -41,26 +41,10 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/spaceinvaders_mist.sv
-set_global_assignment -name VHDL_FILE rtl/invaders.vhd
-set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
-set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/spaceinvaders_memory.sv
 #set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name VHDL_FILE rtl/sprom.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/spaceinvaders_overlay.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 
 # Pin & Location Assignments
 # ==========================
@@ -164,10 +148,23 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
 	# end DESIGN_PARTITION(Top)
 	# -------------------------
 
 # end ENTITY(spaceinvaders_mist)
-# ------------------------------
\ No newline at end of file
+# ------------------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/spaceinvaders_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/spaceinvaders_memory.sv
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/spaceinvaders_overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.sdc
index f91c127c..11d2c7a9 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.sdc	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.sdc	
@@ -87,7 +87,7 @@ set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [g
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {VGA_*}]
 
 #**************************************************************
 # Set Clock Groups
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index da01f6b4..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1080 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in  std_logic;
-		CLK_n           : in  std_logic;
-		CEN             : in  std_logic;
-		WAIT_n          : in  std_logic;
-		INT_n           : in  std_logic;
-		NMI_n           : in  std_logic;
-		BUSRQ_n         : in  std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A               : out std_logic_vector(15 downto 0);
-		DInst           : in  std_logic_vector(7 downto 0);
-		DI              : in  std_logic_vector(7 downto 0);
-		DO              : out std_logic_vector(7 downto 0);
-		MC              : out std_logic_vector(2 downto 0);
-		TS              : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone              : std_logic_vector(2 downto 0) := "111";
-	constant aBC                : std_logic_vector(2 downto 0) := "000";
-	constant aDE                : std_logic_vector(2 downto 0) := "001";
-	constant aXY                : std_logic_vector(2 downto 0) := "010";
-	constant aIOA               : std_logic_vector(2 downto 0) := "100";
-	constant aSP                : std_logic_vector(2 downto 0) := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR          => IR,
-			ISet        => ISet,
-			MCycle      => MCycle,
-			F           => F,
-			NMICycle    => NMICycle,
-			IntCycle    => IntCycle,
-			MCycles     => MCycles_d,
-			TStates     => TStates,
-			Prefix      => Prefix,
-			Inc_PC      => Inc_PC,
-			Inc_WZ      => Inc_WZ,
-			IncDec_16   => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op      => ALU_Op,
-			Save_ALU    => Save_ALU,
-			PreserveC   => PreserveC,
-			Arith16     => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ        => IORQ_i,
-			Jump        => Jump,
-			JumpE       => JumpE,
-			JumpXY      => JumpXY,
-			Call        => Call,
-			RstP        => RstP,
-			LDZ         => LDZ,
-			LDW         => LDW,
-			LDSPHL      => LDSPHL,
-			Special_LD  => Special_LD,
-			ExchangeDH  => ExchangeDH,
-			ExchangeRp  => ExchangeRp,
-			ExchangeAF  => ExchangeAF,
-			ExchangeRS  => ExchangeRS,
-			I_DJNZ      => I_DJNZ,
-			I_CPL       => I_CPL,
-			I_CCF       => I_CCF,
-			I_SCF       => I_SCF,
-			I_RETN      => I_RETN,
-			I_BT        => I_BT,
-			I_BC        => I_BC,
-			I_BTR       => I_BTR,
-			I_RLD       => I_RLD,
-			I_RRD       => I_RRD,
-			I_INRC      => I_INRC,
-			SetDI       => SetDI,
-			SetEI       => SetEI,
-			IMode       => IMode,
-			Halt        => Halt,
-			NoRead      => NoRead,
-			Write       => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16     => Z16_r,
-			ALU_Op  => ALU_Op_r,
-			IR      => IR(5 downto 0),
-			ISet    => ISet,
-			BusA    => BusA,
-			BusB    => BusB,
-			F_In    => F,
-			Q       => ALU_Q,
-			F_Out   => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T8080se.vhd
deleted file mode 100644
index 65b92d54..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T8080se.vhd	
+++ /dev/null
@@ -1,194 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- 8080 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original 8080
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---      STACK status output not supported
---
--- File history :
---
---      0237 : First version
---
---      0238 : Updated for T80 interface change
---
---      0240 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T8080se is
-	generic(
-		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK                     : in std_logic;
-		CLKEN           : in std_logic;
-		READY           : in std_logic;
-		HOLD            : in std_logic;
-		INT             : in std_logic;
-		INTE            : out std_logic;
-		DBIN            : out std_logic;
-		SYNC            : out std_logic;
-		VAIT            : out std_logic;
-		HLDA            : out std_logic;
-		WR_n            : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0)
-	);
-end T8080se;
-
-architecture rtl of T8080se is
-
-	signal IntCycle_n   : std_logic;
-	signal NoRead               : std_logic;
-	signal Write                : std_logic;
-	signal IORQ                 : std_logic;
-	signal INT_n                : std_logic;
-	signal HALT_n               : std_logic;
-	signal BUSRQ_n              : std_logic;
-	signal BUSAK_n              : std_logic;
-	signal DO_i                 : std_logic_vector(7 downto 0);
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal TState               : std_logic_vector(2 downto 0);
-	signal One                  : std_logic;
-
-begin
-
-	INT_n <= not INT;
-	BUSRQ_n <= HOLD;
-	HLDA <= not BUSAK_n;
-	SYNC <= '1' when TState = "001" else '0';
-	VAIT <= '1' when TState = "010" else '0';
-	One <= '1';
-
-	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
-	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
-	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
-	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
-	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
-	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
-	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
-	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 0)
-		port map(
-			CEN => CLKEN,
-			M1_n => open,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => open,
-			HALT_n => HALT_n,
-			WAIT_n => READY,
-			INT_n => INT_n,
-			NMI_n => One,
-			RESET_n => RESET_n,
-			BUSRQ_n => One,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO_i,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n,
-			IntE => INTE);
-
-	process (RESET_n, CLK)
-	begin
-		if RESET_n = '0' then
-			DBIN <= '0';
-			WR_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK'event and CLK = '1' then
-			if CLKEN = '1' then
-				DBIN <= '0';
-				WR_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and READY = '0') then
-						DBIN <= IntCycle_n;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
-						DBIN <= '1';
-					end if;
-					if T2Write = 0 then
-						if TState = "010" and Write = '1' then
-							WR_n <= '0';
-						end if;
-					else
-						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
-							WR_n <= '0';
-						end if;
-					end if;
-				end if;
-				if TState = "010" and READY = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index e09def1e..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,361 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 43cea1b5..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1944 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-				  ALU_Op <= "1000";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-				  ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-				  ALU_Op <= "1010";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index 42cf6105..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,217 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 1c0f2638..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---      0242 : Initial release
---
---      0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal      RegsH   : Register_Image(0 to 7);
-	signal      RegsL   : Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/dac.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/dac.vhd
deleted file mode 100644
index db58d70b..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,48 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity dac is
-	generic (
-		C_bits  : integer := 8
-	);
-	port (
-		clk_i   : in  std_logic;
-		res_n_i : in  std_logic;
-		dac_i   : in  std_logic_vector(C_bits-1 downto 0);
-		dac_o   : out std_logic
-	);
-end dac;
-
-architecture rtl of dac is
-	signal sig_in: unsigned(C_bits downto 0);
-begin
-	seq: process(clk_i, res_n_i)
-	begin
-		if res_n_i = '0' then
-			sig_in <= to_unsigned(2**C_bits, sig_in'length);
-			dac_o  <= '0';
-		elsif rising_edge(clk_i) then
-		        -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
-			--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
-			sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
-			dac_o  <= sig_in(C_bits);
-		end if;
-	end process seq;
-end rtl;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.vhd
index d65b9f9b..39c09b03 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.vhd	
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************
 
 
@@ -43,7 +43,8 @@ ENTITY pll IS
 	PORT
 	(
 		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC 
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
 	);
 END pll;
 
@@ -53,9 +54,10 @@ ARCHITECTURE SYN OF pll IS
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
 	SIGNAL sub_wire1	: STD_LOGIC ;
 	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire4_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 
 
@@ -66,6 +68,10 @@ ARCHITECTURE SYN OF pll IS
 		clk0_duty_cycle		: NATURAL;
 		clk0_multiply_by		: NATURAL;
 		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
 		compensate_clock		: STRING;
 		inclk0_input_frequency		: NATURAL;
 		intended_device_family		: STRING;
@@ -123,20 +129,26 @@ ARCHITECTURE SYN OF pll IS
 	END COMPONENT;
 
 BEGIN
-	sub_wire4_bv(0 DOWNTO 0) <= "0";
-	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
 	sub_wire1    <= sub_wire0(0);
 	c0    <= sub_wire1;
-	sub_wire2    <= inclk0;
-	sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
 
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 27,
+		clk0_divide_by => 1125,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 10,
+		clk0_multiply_by => 416,
 		clk0_phase_shift => "0",
+		clk1_divide_by => 1125,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 832,
+		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
 		intended_device_family => "Cyclone III",
@@ -170,7 +182,7 @@ BEGIN
 		port_scanread => "PORT_UNUSED",
 		port_scanwrite => "PORT_UNUSED",
 		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_UNUSED",
+		port_clk1 => "PORT_USED",
 		port_clk2 => "PORT_UNUSED",
 		port_clk3 => "PORT_UNUSED",
 		port_clk4 => "PORT_UNUSED",
@@ -188,7 +200,7 @@ BEGIN
 		width_clock => 5
 	)
 	PORT MAP (
-		inclk => sub_wire3,
+		inclk => sub_wire4,
 		clk => sub_wire0
 	);
 
@@ -216,8 +228,11 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "9.984000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "19.968000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -238,18 +253,26 @@ END SYN;
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
 -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "9.98400000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "19.96800000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -272,19 +295,26 @@ END SYN;
 -- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
 -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "416"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1125"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "832"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -317,7 +347,7 @@ END SYN;
 -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
 -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -336,10 +366,12 @@ END SYN;
 -- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
 -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
 -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_mist.sv
index ad18ca58..8cf88618 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_mist.sv	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_mist.sv	
@@ -19,34 +19,38 @@ module spaceinvaders_mist(
 `include "rtl\build_id.v" 
 
 localparam CONF_STR = {
-	"Space Inv.;;",
+	"INVADERS;;",
 	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-	"O5,Overlay, On, Off;",
-	"T6,Reset;",
+	"O5,Overlay,On,Off;",
+	"T0,Reset;",
 	"V,v1.20.",`BUILD_DATE
 };
 
+wire  [1:0] scanlines = status[4:3];
+wire        rotate    = status[2];
+wire        overlay   = status[5];
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
-
-wire clk_sys;
+wire clk_sys, clk_vid;
 wire pll_locked;
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(),
-	.c0(clk_sys)
+	.c0(clk_sys),
+	.c1(clk_vid)
 );
 
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire  [7:0] kbjoy;
 wire  [7:0] joystick_0,joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
+wire        no_csync;
 wire        key_pressed;
 wire  [7:0] key_code;
 wire        key_strobe;
@@ -69,13 +73,13 @@ wire HSync;
 wire VSync;
 
 invaderst invaderst(
-	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Rst_n(~(status[0] | buttons[1])),
 	.Clk(clk_sys),
 	.ENA(),
-	.Coin(btn_coin),
-	.Sel1Player(~btn_one_player),
-	.Sel2Player(~btn_two_players),
-	.Fire(~m_fire),
+	.Coin(m_coin1 | m_coin2),
+	.Sel1Player(~m_one_player),
+	.Sel2Player(~m_two_players),
+	.Fire(~m_fireA),
 	.MoveLeft(~m_left),
 	.MoveRight(~m_right),
 //	.DIP(dip),
@@ -112,7 +116,7 @@ invaders_audio invaders_audio (
 	  
 spaceinvaders_overlay spaceinvaders_overlay (
 	.Video(Video),
-	.Overlay(~status[5]),
+	.Overlay(~overlay),
 	.CLK(clk_sys),
 	.Rst_n_s(Rst_n_s),
 	.HSync(HSync),
@@ -124,14 +128,14 @@ spaceinvaders_overlay spaceinvaders_overlay (
 	.O_VSYNC(vs)
 	);
 
-mist_video #(.COLOR_DEPTH(3)) mist_video(
-	.clk_sys(clk_sys),
+mist_video #(.COLOR_DEPTH(1)) mist_video(
+	.clk_sys(clk_vid),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({r,r,r}),
-	.G({g,g,g}),
-	.B({b,b,b}),
+	.R(r),
+	.G(g),
+	.B(b),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -139,10 +143,10 @@ mist_video #(.COLOR_DEPTH(3)) mist_video(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),
+	.rotate({1'b0,rotate}),
 	.scandoubler_disable(scandoublerD),
-	.ce_divider(1),
-	.scanlines(status[4:3]),
+	.ce_divider(1'b0),
+	.scanlines(scanlines),
 	.ypbpr(ypbpr)
 	);
 
@@ -159,6 +163,7 @@ user_io(
 	.switches       (switches       ),
 	.scandoubler_disable (scandoublerD	  ),
 	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
 	.key_strobe     (key_strobe     ),
 	.key_pressed    (key_pressed    ),
 	.key_code       (key_code       ),
@@ -174,38 +179,24 @@ dac dac (
 	.dac_o(AUDIO_L)
 	);
 
-wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
 
-always @(posedge clk_sys) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h75: btn_up          <= key_pressed; // up
-			'h72: btn_down        <= key_pressed; // down
-			'h6B: btn_left        <= key_pressed; // left
-			'h74: btn_right       <= key_pressed; // right
-			'h76: btn_coin        <= key_pressed; // ESC
-			'h05: btn_one_player  <= key_pressed; // F1
-			'h06: btn_two_players <= key_pressed; // F2
-			'h14: btn_fire3       <= key_pressed; // ctrl
-			'h11: btn_fire2       <= key_pressed; // alt
-			'h29: btn_fire1       <= key_pressed; // Space
-		endcase
-	end
-end
+arcade_inputs inputs (
+	.clk         ( clk_sys     ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b01       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qsf
index 224648a1..e6276551 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qsf	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qsf	
@@ -41,25 +41,9 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/SpaceWalk.sv
-set_global_assignment -name VHDL_FILE rtl/invaders.vhd
-set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
-set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Spacewalk_memory.sv
-set_global_assignment -name VHDL_FILE rtl/Spacewalk_overlay.vhd
-set_global_assignment -name VHDL_FILE rtl/sprom.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 
 # Pin & Location Assignments
 # ==========================
@@ -123,7 +107,7 @@ set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
 
 # EDA Netlist Writer Assignments
 # ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
 
 # Assembler Assignments
 # =====================
@@ -147,7 +131,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 	# EDA Netlist Writer Assignments
 	# ==============================
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
 
 # end EDA_TOOL_SETTINGS(eda_simulation)
 # -------------------------------------
@@ -169,4 +153,18 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
 # end ENTITY(SpaceWalk)
 # ---------------------
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/SpaceWalk.sv
+set_global_assignment -name VHDL_FILE rtl/spinner.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Spacewalk_memory.sv
+set_global_assignment -name VHDL_FILE rtl/Spacewalk_overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.sdc
index f91c127c..11d2c7a9 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.sdc	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.sdc	
@@ -87,7 +87,7 @@ set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [g
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {VGA_*}]
 
 #**************************************************************
 # Set Clock Groups
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/SpaceWalk.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/SpaceWalk.sv
index 708187bd..8cece0fb 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/SpaceWalk.sv	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/SpaceWalk.sv	
@@ -21,32 +21,37 @@ module SpaceWalk(
 localparam CONF_STR = {
 	"Spacewalk;;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-//	"O5,Overlay, On, Off;",
-	"T6,Reset;",
+//	"O5,Overlay,On,Off;",
+	"T0,Reset;",
 	"V,v1.20.",`BUILD_DATE
 };
 
+wire        reset = status[0] | buttons[1];
+wire  [1:0] scanlines = status[4:3];
+wire        overlay   = 0;
+wire        rotate    = 0;
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
 
-wire clk_core, clk_sys;
+wire clk_core, clk_vid;
 wire pll_locked;
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(),
 	.c0(clk_core),
-	.c1(clk_sys)
+	.c1(clk_vid)
 );
 
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire  [7:0] kbjoy;
 wire  [7:0] joystick_0,joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
+wire        no_csync;
 wire        key_pressed;
 wire  [7:0] key_code;
 wire        key_strobe;
@@ -67,16 +72,26 @@ wire RWE_n;
 wire Video;
 wire HSync;
 wire VSync;
+wire  [7:0] paddle;
+
+spinner spinner(
+	.clock_40(clk_core),
+	.reset(reset),
+	.btn_left(m_right),
+	.btn_right(m_left),
+	.ctc_zc_to_2(vs),
+	.spin_angle(paddle)
+);
 
 invaders invaders(
-	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Rst_n(~reset),
 	.Clk(clk_core),
 	.ENA(),
-	.Coin(btn_coin),
-	.Sel1Player(btn_one_player),
-	.Fire(~joystick_0[4]),
-	.MoveLeft(~joystick_0[1]),
-	.MoveRight(~joystick_0[0]),
+	.Coin(m_coin1 | m_coin2),
+	.Sel1Player(m_one_player),
+	.Sel2Player(m_two_players),
+	.Fire(~m_fireA),
+	.Paddle(paddle),
 //	.DIP(dip),
 	.RDB(RDB),
 	.IB(IB),
@@ -88,10 +103,24 @@ invaders invaders(
 	.Rst_n_s(Rst_n_s),
 	.RWE_n(RWE_n),
 	.Video(Video),
-	.HSync(hs),
-	.VSync(vs)
+	.HSync(HSync),
+	.VSync(VSync)
 	);
-		
+
+Spacewalk_Overlay Spacewalk_Overlay (
+	.Video(Video),
+	.Overlay(overlay),
+	.CLK(clk_core),
+	.Rst_n_s(Rst_n_s),
+	.HSync(HSync),
+	.VSync(VSync),
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs)
+	);
+
 Spacewalk_memory Spacewalk_memory (
 	.Clock(clk_core),
 	.RW_n(RWE_n),
@@ -109,14 +138,14 @@ invaders_audio invaders_audio (
 	.Aud(audio)
 	);
 
-mist_video #(.COLOR_DEPTH(3)) mist_video(
-	.clk_sys(clk_sys),
+mist_video #(.COLOR_DEPTH(1)) mist_video(
+	.clk_sys(clk_vid),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({Video,Video,Video}),
-	.G({Video,Video,Video}),
-	.B({Video,Video,Video}),
+	.R(r),
+	.G(g),
+	.B(b),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -125,15 +154,16 @@ mist_video #(.COLOR_DEPTH(3)) mist_video(
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
 	.scandoubler_disable(scandoublerD),
+	.no_csync(no_csync),
 	.ce_divider(0),
-	.scanlines(status[4:3]),
+	.scanlines(scanlines),
 	.ypbpr(ypbpr)
 	);
 
 user_io #(
 	.STRLEN(($size(CONF_STR)>>3)))
 user_io(
-	.clk_sys        (clk_sys       ),
+	.clk_sys        (clk_core       ),
 	.conf_str       (CONF_STR       ),
 	.SPI_CLK        (SPI_SCK        ),
 	.SPI_SS_IO      (CONF_DATA0     ),
@@ -143,6 +173,7 @@ user_io(
 	.switches       (switches       ),
 	.scandoubler_disable (scandoublerD	  ),
 	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
 	.key_strobe     (key_strobe     ),
 	.key_pressed    (key_pressed    ),
 	.key_code       (key_code       ),
@@ -154,34 +185,30 @@ user_io(
 dac #(
 	.c_bits(8))
 dac (
-	.clk_i(clk_sys),
+	.clk_i(clk_core),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
 
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
 
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_coin  = 0;
-
-reg gun1_up  = 0;
-reg gun1_dw  = 0;
-reg gun2_up  = 0;
-reg gun2_dw  = 0;
-
-always @(posedge clk_sys) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h76: btn_coin        <= key_pressed; // ESC
-			'h05: btn_one_player  <= key_pressed; // F1
-			'h06: btn_two_players <= key_pressed; // F2
-			'h15: gun1_up       <= key_pressed; // Q
-			'h35: gun1_dw       <= key_pressed; // Y
-			'h75: gun2_up       <= key_pressed; // Arrow up
-			'h72: gun2_dw       <= key_pressed; // Arrow down
-		endcase
-	end
-end
+arcade_inputs inputs (
+	.clk         ( clk_core    ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b00       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_overlay.vhd
index c45739e0..4aeb306f 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_overlay.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_overlay.vhd	
@@ -120,8 +120,8 @@ begin
   O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
   O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
   O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
-  O_HSYNC   <= not HSync;
-  O_VSYNC   <= not VSync;
+  O_HSYNC   <= HSync;
+  O_VSYNC   <= VSync;
 
 
 end;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index da01f6b4..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1080 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in  std_logic;
-		CLK_n           : in  std_logic;
-		CEN             : in  std_logic;
-		WAIT_n          : in  std_logic;
-		INT_n           : in  std_logic;
-		NMI_n           : in  std_logic;
-		BUSRQ_n         : in  std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A               : out std_logic_vector(15 downto 0);
-		DInst           : in  std_logic_vector(7 downto 0);
-		DI              : in  std_logic_vector(7 downto 0);
-		DO              : out std_logic_vector(7 downto 0);
-		MC              : out std_logic_vector(2 downto 0);
-		TS              : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone              : std_logic_vector(2 downto 0) := "111";
-	constant aBC                : std_logic_vector(2 downto 0) := "000";
-	constant aDE                : std_logic_vector(2 downto 0) := "001";
-	constant aXY                : std_logic_vector(2 downto 0) := "010";
-	constant aIOA               : std_logic_vector(2 downto 0) := "100";
-	constant aSP                : std_logic_vector(2 downto 0) := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR          => IR,
-			ISet        => ISet,
-			MCycle      => MCycle,
-			F           => F,
-			NMICycle    => NMICycle,
-			IntCycle    => IntCycle,
-			MCycles     => MCycles_d,
-			TStates     => TStates,
-			Prefix      => Prefix,
-			Inc_PC      => Inc_PC,
-			Inc_WZ      => Inc_WZ,
-			IncDec_16   => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op      => ALU_Op,
-			Save_ALU    => Save_ALU,
-			PreserveC   => PreserveC,
-			Arith16     => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ        => IORQ_i,
-			Jump        => Jump,
-			JumpE       => JumpE,
-			JumpXY      => JumpXY,
-			Call        => Call,
-			RstP        => RstP,
-			LDZ         => LDZ,
-			LDW         => LDW,
-			LDSPHL      => LDSPHL,
-			Special_LD  => Special_LD,
-			ExchangeDH  => ExchangeDH,
-			ExchangeRp  => ExchangeRp,
-			ExchangeAF  => ExchangeAF,
-			ExchangeRS  => ExchangeRS,
-			I_DJNZ      => I_DJNZ,
-			I_CPL       => I_CPL,
-			I_CCF       => I_CCF,
-			I_SCF       => I_SCF,
-			I_RETN      => I_RETN,
-			I_BT        => I_BT,
-			I_BC        => I_BC,
-			I_BTR       => I_BTR,
-			I_RLD       => I_RLD,
-			I_RRD       => I_RRD,
-			I_INRC      => I_INRC,
-			SetDI       => SetDI,
-			SetEI       => SetEI,
-			IMode       => IMode,
-			Halt        => Halt,
-			NoRead      => NoRead,
-			Write       => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16     => Z16_r,
-			ALU_Op  => ALU_Op_r,
-			IR      => IR(5 downto 0),
-			ISet    => ISet,
-			BusA    => BusA,
-			BusB    => BusB,
-			F_In    => F,
-			Q       => ALU_Q,
-			F_Out   => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T8080se.vhd
deleted file mode 100644
index 65b92d54..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T8080se.vhd	
+++ /dev/null
@@ -1,194 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- 8080 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original 8080
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---      STACK status output not supported
---
--- File history :
---
---      0237 : First version
---
---      0238 : Updated for T80 interface change
---
---      0240 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T8080se is
-	generic(
-		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK                     : in std_logic;
-		CLKEN           : in std_logic;
-		READY           : in std_logic;
-		HOLD            : in std_logic;
-		INT             : in std_logic;
-		INTE            : out std_logic;
-		DBIN            : out std_logic;
-		SYNC            : out std_logic;
-		VAIT            : out std_logic;
-		HLDA            : out std_logic;
-		WR_n            : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0)
-	);
-end T8080se;
-
-architecture rtl of T8080se is
-
-	signal IntCycle_n   : std_logic;
-	signal NoRead               : std_logic;
-	signal Write                : std_logic;
-	signal IORQ                 : std_logic;
-	signal INT_n                : std_logic;
-	signal HALT_n               : std_logic;
-	signal BUSRQ_n              : std_logic;
-	signal BUSAK_n              : std_logic;
-	signal DO_i                 : std_logic_vector(7 downto 0);
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal TState               : std_logic_vector(2 downto 0);
-	signal One                  : std_logic;
-
-begin
-
-	INT_n <= not INT;
-	BUSRQ_n <= HOLD;
-	HLDA <= not BUSAK_n;
-	SYNC <= '1' when TState = "001" else '0';
-	VAIT <= '1' when TState = "010" else '0';
-	One <= '1';
-
-	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
-	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
-	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
-	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
-	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
-	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
-	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
-	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 0)
-		port map(
-			CEN => CLKEN,
-			M1_n => open,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => open,
-			HALT_n => HALT_n,
-			WAIT_n => READY,
-			INT_n => INT_n,
-			NMI_n => One,
-			RESET_n => RESET_n,
-			BUSRQ_n => One,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO_i,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n,
-			IntE => INTE);
-
-	process (RESET_n, CLK)
-	begin
-		if RESET_n = '0' then
-			DBIN <= '0';
-			WR_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK'event and CLK = '1' then
-			if CLKEN = '1' then
-				DBIN <= '0';
-				WR_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and READY = '0') then
-						DBIN <= IntCycle_n;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
-						DBIN <= '1';
-					end if;
-					if T2Write = 0 then
-						if TState = "010" and Write = '1' then
-							WR_n <= '0';
-						end if;
-					else
-						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
-							WR_n <= '0';
-						end if;
-					end if;
-				end if;
-				if TState = "010" and READY = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index e09def1e..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,361 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 43cea1b5..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1944 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-				  ALU_Op <= "1000";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-				  ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-				  ALU_Op <= "1010";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index 42cf6105..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,217 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 1c0f2638..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---      0242 : Initial release
---
---      0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal      RegsH   : Register_Image(0 to 7);
-	signal      RegsL   : Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders.vhd
index 5c95d579..9421271d 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders.vhd	
@@ -63,8 +63,7 @@ entity invaders is
 		Sel1Player      : in  std_logic;
 		Sel2Player      : in  std_logic;
 		Fire            : in  std_logic;
-		MoveLeft        : in  std_logic;
-		MoveRight       : in  std_logic;
+		Paddle          : in  std_logic_vector(7 downto 0);
 		DIP             : in  std_logic_vector(8 downto 1);
 		RDB             : in  std_logic_vector(7 downto 0);
 		IB              : in  std_logic_vector(7 downto 0);
@@ -122,7 +121,7 @@ architecture rtl of invaders is
 	signal DB           : std_logic_vector(7 downto 0);
 	signal Sounds       : std_logic_vector(7 downto 0);
 	signal AD_i         : std_logic_vector(15 downto 0);
-	signal PortWr       : std_logic_vector(7 downto 0);
+	signal PortWr       : std_logic_vector(7 downto 1);
 	signal EA           : std_logic_vector(2 downto 0);
 	signal D5           : std_logic_vector(15 downto 0);
 	signal WD_Cnt       : unsigned(7 downto 0);
@@ -200,19 +199,12 @@ begin
 				GDB2 when "10",
 				S when others;
 
-	GDB0(0) <= '0';--
-	GDB0(1) <= '0';--
-	GDB0(2) <= '0';--
-	GDB0(3) <= '0';--
-	GDB0(4) <= '0';--
-	GDB0(5) <= '0';--
-	GDB0(6) <= '0';--
-	GDB0(7) <= '0';--
+	GDB0 <= Paddle;
 
 	GDB1(0) <= '1';-- Unused ?
 	GDB1(1) <= '1';-- Unused ?
 	GDB1(2) <= '1';-- Unused ?
-	GDB1(2) <= '1';-- Unused ?
+	GDB1(3) <= '1';-- Unused ?
 	GDB1(4) <= not Sel2Player;
 	GDB1(5) <= not Sel1Player;
 	GDB1(6) <= not Coin;
@@ -227,11 +219,13 @@ begin
 	GDB2(6) <= '0';--Springboard Alignment
 	GDB2(7) <= '0';--unused
 
+	PortWr(1) <= '1' when AD_i(10 downto 8) = "001" and Sample = '1' else '0';
 	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
 	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
 	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
 	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
 	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+	PortWr(7) <= '1' when AD_i(10 downto 8) = "111" and Sample = '1' else '0';
 
 	process (Rst_n_s_i, Clk)
 		variable OldSample : std_logic;
@@ -245,16 +239,16 @@ begin
 			SoundCtrl6 <= (others => '0');
 			OldSample := '0';
 		elsif Clk'event and Clk = '1' then
-			if PortWr(2) = '1' then
+			if PortWr(1) = '1' then
 				EA <= DB(2 downto 0);
 			end if;
 			if PortWr(3) = '1' then
 				SoundCtrl3 <= DB(5 downto 0);--audio_1_w
 			end if;
-			--if PortWr(4) = '1' and OldSample = '0' then
-				--D5(15 downto 8) <= DB;
-				--D5(7 downto 0) <= D5(15 downto 8);
-			--end if;
+			if PortWr(2) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
 			if PortWr(5) = '1' then
 				SoundCtrl5 <= DB(5 downto 0);--tone_generator_lo_w
 			end if;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.vhd
index f8d0b139..39c09b03 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.vhd	
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************
 
 
@@ -141,13 +141,13 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 27,
+		clk0_divide_by => 1125,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 10,
+		clk0_multiply_by => 416,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 27,
+		clk1_divide_by => 1125,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 20,
+		clk1_multiply_by => 832,
 		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -231,8 +231,8 @@ END SYN;
 -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "9.984000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "19.968000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -260,10 +260,10 @@ END SYN;
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
 -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "9.98400000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "19.96800000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -307,13 +307,13 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "416"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "832"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/spinner.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/spinner.vhd
new file mode 100644
index 00000000..88a56651
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/spinner.vhd	
@@ -0,0 +1,49 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity spinner is
+generic(
+	step          : integer := 40
+);
+port(
+ clock_40       : in std_logic;
+ reset          : in std_logic;
+ btn_left       : in std_logic;
+ btn_right      : in std_logic;
+ btn_acc        : in std_logic; -- speed up button
+ ctc_zc_to_2    : in std_logic;
+ spin_angle     : out std_logic_vector(6 downto 0)
+);
+end spinner;
+
+architecture rtl of spinner is
+
+signal ctc_zc_to_2_r : std_logic;
+signal spin_count    : std_logic_vector(9 downto 0);
+
+begin
+
+spin_angle <= spin_count(9 downto 3);
+
+process (clock_40, reset)
+begin
+	if reset = '1' then
+		spin_count <= (others => '0');
+	elsif rising_edge(clock_40) then
+		ctc_zc_to_2_r <= ctc_zc_to_2;
+
+		if ctc_zc_to_2_r ='0' and ctc_zc_to_2 = '1' then
+			if btn_acc = '0' then  -- space -- speed up
+				if btn_left = '1' then spin_count <= spin_count - step; end if; -- left
+				if btn_right = '1' then spin_count <= spin_count + step; end if; -- right
+			else
+				if btn_left = '1' then spin_count <= spin_count - 55; end if;
+				if btn_right = '1' then spin_count <= spin_count + 55; end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qsf
index 0ebe06ab..0d8a41ff 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qsf	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qsf	
@@ -41,25 +41,9 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/SuperEarthInvasion_mist.sv
-set_global_assignment -name VHDL_FILE rtl/invaders.vhd
-set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/SuperEarthInvasion_memory.sv
-set_global_assignment -name VHDL_FILE rtl/SuperEarthInvasion_overlay.vhd
-set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
-set_global_assignment -name VHDL_FILE rtl/sprom.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
 
 # Pin & Location Assignments
 # ==========================
@@ -123,7 +107,7 @@ set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
 
 # EDA Netlist Writer Assignments
 # ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
 
 # Assembler Assignments
 # =====================
@@ -147,7 +131,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 	# EDA Netlist Writer Assignments
 	# ==============================
-	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
 
 # end EDA_TOOL_SETTINGS(eda_simulation)
 # -------------------------------------
@@ -163,10 +147,29 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
 	# end DESIGN_PARTITION(Top)
 	# -------------------------
 
 # end ENTITY(SuperEarthInvasion_mist)
-# -----------------------------------
\ No newline at end of file
+# -----------------------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/SuperEarthInvasion_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/SuperEarthInvasion_memory.sv
+set_global_assignment -name VHDL_FILE rtl/SuperEarthInvasion_overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.sdc
index f91c127c..11d2c7a9 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.sdc	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.sdc	
@@ -87,7 +87,7 @@ set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [g
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
 set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {VGA_*}]
 
 #**************************************************************
 # Set Clock Groups
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_mist.sv
index 0c0853d6..bf7bbc01 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_mist.sv	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_mist.sv	
@@ -22,32 +22,37 @@ localparam CONF_STR = {
 	"SEarthInv.;;",
 	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-	"O5,Overlay, On, Off;",
-	"T6,Reset;",
+	"O5,Overlay,On,Off;",
+	"T0,Reset;",
 	"V,v1.20.",`BUILD_DATE
 };
 
+wire        reset = status[0] | buttons[1];
+wire        rotate = status[2];
+wire  [1:0] scanlines = status[4:3];
+wire        overlay = status[5];
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
 
-wire clk_core, clk_sys;
+wire clk_core, clk_vid;
 wire pll_locked;
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(),
 	.c0(clk_core),
-	.c1(clk_sys)
+	.c1(clk_vid)
 );
 
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire  [7:0] kbjoy;
 wire  [7:0] joystick_0,joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
+wire        no_csync;
 wire        key_pressed;
 wire  [7:0] key_code;
 wire        key_strobe;
@@ -70,13 +75,13 @@ wire HSync;
 wire VSync;
 
 invaderst invaderst(
-	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Rst_n(~reset),
 	.Clk(clk_core),
 	.ENA(),
-	.Coin(btn_coin),
-	.Sel1Player(~btn_one_player),
-	.Sel2Player(~btn_two_players),
-	.Fire(~m_fire),
+	.Coin(m_coin1 | m_coin2),
+	.Sel1Player(~m_one_player),
+	.Sel2Player(~m_two_players),
+	.Fire(~m_fireA),
 	.MoveLeft(~m_left),
 	.MoveRight(~m_right),
 	.DIP(dip),
@@ -113,7 +118,7 @@ invaders_audio invaders_audio (
 	  
 SuperEarthInvasion_overlay SuperEarthInvasion_overlay (
 	.Video(Video),
-	.Overlay(~status[5]),
+	.Overlay(~overlay),
 	.CLK(clk_core),
 	.Rst_n_s(Rst_n_s),
 	.HSync(HSync),
@@ -125,14 +130,14 @@ SuperEarthInvasion_overlay SuperEarthInvasion_overlay (
 	.O_VSYNC(vs)
 	);
 
-mist_video #(.COLOR_DEPTH(3)) mist_video(
-	.clk_sys(clk_sys),
+mist_video #(.COLOR_DEPTH(1)) mist_video(
+	.clk_sys(clk_vid),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({r,r,r}),
-	.G({g,g,g}),
-	.B({b,b,b}),
+	.R(r),
+	.G(g),
+	.B(b),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -140,17 +145,18 @@ mist_video #(.COLOR_DEPTH(3)) mist_video(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),
+	.rotate({1'b0,rotate}),
 	.scandoubler_disable(scandoublerD),
-	.scanlines(status[4:3]),
-	.ce_divider(0),
-	.ypbpr(ypbpr)
+	.scanlines(scanlines),
+	.ce_divider(1'b0),
+	.ypbpr(ypbpr),
+	.no_csync(no_csync)
 	);
 
 user_io #(
 	.STRLEN(($size(CONF_STR)>>3)))
 user_io(
-	.clk_sys        (clk_sys       ),
+	.clk_sys        (clk_core       ),
 	.conf_str       (CONF_STR       ),
 	.SPI_CLK        (SPI_SCK        ),
 	.SPI_SS_IO      (CONF_DATA0     ),
@@ -160,6 +166,7 @@ user_io(
 	.switches       (switches       ),
 	.scandoubler_disable (scandoublerD	  ),
 	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
 	.key_strobe     (key_strobe     ),
 	.key_pressed    (key_pressed    ),
 	.key_code       (key_code       ),
@@ -169,44 +176,30 @@ user_io(
 	);
 
 dac dac (
-	.clk_i(clk_sys),
+	.clk_i(clk_core),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
 
-wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
 
-always @(posedge clk_sys) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h75: btn_up          <= key_pressed; // up
-			'h72: btn_down        <= key_pressed; // down
-			'h6B: btn_left        <= key_pressed; // left
-			'h74: btn_right       <= key_pressed; // right
-			'h76: btn_coin        <= key_pressed; // ESC
-			'h05: btn_one_player  <= key_pressed; // F1
-			'h06: btn_two_players <= key_pressed; // F2
-			'h14: btn_fire3       <= key_pressed; // ctrl
-			'h11: btn_fire2       <= key_pressed; // alt
-			'h29: btn_fire1       <= key_pressed; // Space
-		endcase
-	end
-end
+arcade_inputs inputs (
+	.clk         ( clk_core    ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b01       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index da01f6b4..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1080 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in  std_logic;
-		CLK_n           : in  std_logic;
-		CEN             : in  std_logic;
-		WAIT_n          : in  std_logic;
-		INT_n           : in  std_logic;
-		NMI_n           : in  std_logic;
-		BUSRQ_n         : in  std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A               : out std_logic_vector(15 downto 0);
-		DInst           : in  std_logic_vector(7 downto 0);
-		DI              : in  std_logic_vector(7 downto 0);
-		DO              : out std_logic_vector(7 downto 0);
-		MC              : out std_logic_vector(2 downto 0);
-		TS              : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone              : std_logic_vector(2 downto 0) := "111";
-	constant aBC                : std_logic_vector(2 downto 0) := "000";
-	constant aDE                : std_logic_vector(2 downto 0) := "001";
-	constant aXY                : std_logic_vector(2 downto 0) := "010";
-	constant aIOA               : std_logic_vector(2 downto 0) := "100";
-	constant aSP                : std_logic_vector(2 downto 0) := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR          => IR,
-			ISet        => ISet,
-			MCycle      => MCycle,
-			F           => F,
-			NMICycle    => NMICycle,
-			IntCycle    => IntCycle,
-			MCycles     => MCycles_d,
-			TStates     => TStates,
-			Prefix      => Prefix,
-			Inc_PC      => Inc_PC,
-			Inc_WZ      => Inc_WZ,
-			IncDec_16   => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op      => ALU_Op,
-			Save_ALU    => Save_ALU,
-			PreserveC   => PreserveC,
-			Arith16     => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ        => IORQ_i,
-			Jump        => Jump,
-			JumpE       => JumpE,
-			JumpXY      => JumpXY,
-			Call        => Call,
-			RstP        => RstP,
-			LDZ         => LDZ,
-			LDW         => LDW,
-			LDSPHL      => LDSPHL,
-			Special_LD  => Special_LD,
-			ExchangeDH  => ExchangeDH,
-			ExchangeRp  => ExchangeRp,
-			ExchangeAF  => ExchangeAF,
-			ExchangeRS  => ExchangeRS,
-			I_DJNZ      => I_DJNZ,
-			I_CPL       => I_CPL,
-			I_CCF       => I_CCF,
-			I_SCF       => I_SCF,
-			I_RETN      => I_RETN,
-			I_BT        => I_BT,
-			I_BC        => I_BC,
-			I_BTR       => I_BTR,
-			I_RLD       => I_RLD,
-			I_RRD       => I_RRD,
-			I_INRC      => I_INRC,
-			SetDI       => SetDI,
-			SetEI       => SetEI,
-			IMode       => IMode,
-			Halt        => Halt,
-			NoRead      => NoRead,
-			Write       => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16     => Z16_r,
-			ALU_Op  => ALU_Op_r,
-			IR      => IR(5 downto 0),
-			ISet    => ISet,
-			BusA    => BusA,
-			BusB    => BusB,
-			F_In    => F,
-			Q       => ALU_Q,
-			F_Out   => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T8080se.vhd
deleted file mode 100644
index 65b92d54..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T8080se.vhd	
+++ /dev/null
@@ -1,194 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- 8080 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original 8080
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---      STACK status output not supported
---
--- File history :
---
---      0237 : First version
---
---      0238 : Updated for T80 interface change
---
---      0240 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T8080se is
-	generic(
-		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK                     : in std_logic;
-		CLKEN           : in std_logic;
-		READY           : in std_logic;
-		HOLD            : in std_logic;
-		INT             : in std_logic;
-		INTE            : out std_logic;
-		DBIN            : out std_logic;
-		SYNC            : out std_logic;
-		VAIT            : out std_logic;
-		HLDA            : out std_logic;
-		WR_n            : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0)
-	);
-end T8080se;
-
-architecture rtl of T8080se is
-
-	signal IntCycle_n   : std_logic;
-	signal NoRead               : std_logic;
-	signal Write                : std_logic;
-	signal IORQ                 : std_logic;
-	signal INT_n                : std_logic;
-	signal HALT_n               : std_logic;
-	signal BUSRQ_n              : std_logic;
-	signal BUSAK_n              : std_logic;
-	signal DO_i                 : std_logic_vector(7 downto 0);
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal TState               : std_logic_vector(2 downto 0);
-	signal One                  : std_logic;
-
-begin
-
-	INT_n <= not INT;
-	BUSRQ_n <= HOLD;
-	HLDA <= not BUSAK_n;
-	SYNC <= '1' when TState = "001" else '0';
-	VAIT <= '1' when TState = "010" else '0';
-	One <= '1';
-
-	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
-	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
-	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
-	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
-	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
-	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
-	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
-	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 0)
-		port map(
-			CEN => CLKEN,
-			M1_n => open,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => open,
-			HALT_n => HALT_n,
-			WAIT_n => READY,
-			INT_n => INT_n,
-			NMI_n => One,
-			RESET_n => RESET_n,
-			BUSRQ_n => One,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO_i,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n,
-			IntE => INTE);
-
-	process (RESET_n, CLK)
-	begin
-		if RESET_n = '0' then
-			DBIN <= '0';
-			WR_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK'event and CLK = '1' then
-			if CLKEN = '1' then
-				DBIN <= '0';
-				WR_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and READY = '0') then
-						DBIN <= IntCycle_n;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
-						DBIN <= '1';
-					end if;
-					if T2Write = 0 then
-						if TState = "010" and Write = '1' then
-							WR_n <= '0';
-						end if;
-					else
-						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
-							WR_n <= '0';
-						end if;
-					end if;
-				end if;
-				if TState = "010" and READY = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index e09def1e..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,361 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 43cea1b5..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1944 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-				  ALU_Op <= "1000";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-				  ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-				  ALU_Op <= "1010";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index 42cf6105..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,217 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 1c0f2638..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---      0242 : Initial release
---
---      0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal      RegsH   : Register_Image(0 to 7);
-	signal      RegsL   : Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/dac.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/dac.vhd
deleted file mode 100644
index db58d70b..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,48 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity dac is
-	generic (
-		C_bits  : integer := 8
-	);
-	port (
-		clk_i   : in  std_logic;
-		res_n_i : in  std_logic;
-		dac_i   : in  std_logic_vector(C_bits-1 downto 0);
-		dac_o   : out std_logic
-	);
-end dac;
-
-architecture rtl of dac is
-	signal sig_in: unsigned(C_bits downto 0);
-begin
-	seq: process(clk_i, res_n_i)
-	begin
-		if res_n_i = '0' then
-			sig_in <= to_unsigned(2**C_bits, sig_in'length);
-			dac_o  <= '0';
-		elsif rising_edge(clk_i) then
-		        -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
-			--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
-			sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
-			dac_o  <= sig_in(C_bits);
-		end if;
-	end process seq;
-end rtl;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.vhd
index f8d0b139..39c09b03 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.vhd	
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************
 
 
@@ -141,13 +141,13 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 27,
+		clk0_divide_by => 1125,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 10,
+		clk0_multiply_by => 416,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 27,
+		clk1_divide_by => 1125,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 20,
+		clk1_multiply_by => 832,
 		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -231,8 +231,8 @@ END SYN;
 -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "9.984000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "19.968000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -260,10 +260,10 @@ END SYN;
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
 -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "9.98400000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "19.96800000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -307,13 +307,13 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "416"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "832"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qsf
index b86690cb..dad54766 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qsf	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qsf	
@@ -41,29 +41,9 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Vortex_mist.sv
-set_global_assignment -name VHDL_FILE rtl/invaders.vhd
-set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
-set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Vortex_memory.sv
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/1.t36.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/2.t35.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/3.t34.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/4.t33.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/5.t32.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/6.t31.vhd
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 
 # Pin & Location Assignments
 # ==========================
@@ -127,7 +107,7 @@ set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
 
 # EDA Netlist Writer Assignments
 # ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
 
 # Assembler Assignments
 # =====================
@@ -151,7 +131,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 	# EDA Netlist Writer Assignments
 	# ==============================
-	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
 
 # end EDA_TOOL_SETTINGS(eda_simulation)
 # -------------------------------------
@@ -173,4 +153,21 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(Vortex_mist)
 # -----------------------
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Vortex_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Vortex_memory.sv
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/1.t36.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/2.t35.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/3.t34.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/4.t33.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/5.t32.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/6.t31.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.sdc
new file mode 100644
index 00000000..11d2c7a9
--- /dev/null
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index da01f6b4..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1080 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in  std_logic;
-		CLK_n           : in  std_logic;
-		CEN             : in  std_logic;
-		WAIT_n          : in  std_logic;
-		INT_n           : in  std_logic;
-		NMI_n           : in  std_logic;
-		BUSRQ_n         : in  std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A               : out std_logic_vector(15 downto 0);
-		DInst           : in  std_logic_vector(7 downto 0);
-		DI              : in  std_logic_vector(7 downto 0);
-		DO              : out std_logic_vector(7 downto 0);
-		MC              : out std_logic_vector(2 downto 0);
-		TS              : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone              : std_logic_vector(2 downto 0) := "111";
-	constant aBC                : std_logic_vector(2 downto 0) := "000";
-	constant aDE                : std_logic_vector(2 downto 0) := "001";
-	constant aXY                : std_logic_vector(2 downto 0) := "010";
-	constant aIOA               : std_logic_vector(2 downto 0) := "100";
-	constant aSP                : std_logic_vector(2 downto 0) := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR          => IR,
-			ISet        => ISet,
-			MCycle      => MCycle,
-			F           => F,
-			NMICycle    => NMICycle,
-			IntCycle    => IntCycle,
-			MCycles     => MCycles_d,
-			TStates     => TStates,
-			Prefix      => Prefix,
-			Inc_PC      => Inc_PC,
-			Inc_WZ      => Inc_WZ,
-			IncDec_16   => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op      => ALU_Op,
-			Save_ALU    => Save_ALU,
-			PreserveC   => PreserveC,
-			Arith16     => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ        => IORQ_i,
-			Jump        => Jump,
-			JumpE       => JumpE,
-			JumpXY      => JumpXY,
-			Call        => Call,
-			RstP        => RstP,
-			LDZ         => LDZ,
-			LDW         => LDW,
-			LDSPHL      => LDSPHL,
-			Special_LD  => Special_LD,
-			ExchangeDH  => ExchangeDH,
-			ExchangeRp  => ExchangeRp,
-			ExchangeAF  => ExchangeAF,
-			ExchangeRS  => ExchangeRS,
-			I_DJNZ      => I_DJNZ,
-			I_CPL       => I_CPL,
-			I_CCF       => I_CCF,
-			I_SCF       => I_SCF,
-			I_RETN      => I_RETN,
-			I_BT        => I_BT,
-			I_BC        => I_BC,
-			I_BTR       => I_BTR,
-			I_RLD       => I_RLD,
-			I_RRD       => I_RRD,
-			I_INRC      => I_INRC,
-			SetDI       => SetDI,
-			SetEI       => SetEI,
-			IMode       => IMode,
-			Halt        => Halt,
-			NoRead      => NoRead,
-			Write       => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16     => Z16_r,
-			ALU_Op  => ALU_Op_r,
-			IR      => IR(5 downto 0),
-			ISet    => ISet,
-			BusA    => BusA,
-			BusB    => BusB,
-			F_In    => F,
-			Q       => ALU_Q,
-			F_Out   => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T8080se.vhd
deleted file mode 100644
index 65b92d54..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T8080se.vhd	
+++ /dev/null
@@ -1,194 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- 8080 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original 8080
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---      STACK status output not supported
---
--- File history :
---
---      0237 : First version
---
---      0238 : Updated for T80 interface change
---
---      0240 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T8080se is
-	generic(
-		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK                     : in std_logic;
-		CLKEN           : in std_logic;
-		READY           : in std_logic;
-		HOLD            : in std_logic;
-		INT             : in std_logic;
-		INTE            : out std_logic;
-		DBIN            : out std_logic;
-		SYNC            : out std_logic;
-		VAIT            : out std_logic;
-		HLDA            : out std_logic;
-		WR_n            : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0)
-	);
-end T8080se;
-
-architecture rtl of T8080se is
-
-	signal IntCycle_n   : std_logic;
-	signal NoRead               : std_logic;
-	signal Write                : std_logic;
-	signal IORQ                 : std_logic;
-	signal INT_n                : std_logic;
-	signal HALT_n               : std_logic;
-	signal BUSRQ_n              : std_logic;
-	signal BUSAK_n              : std_logic;
-	signal DO_i                 : std_logic_vector(7 downto 0);
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal TState               : std_logic_vector(2 downto 0);
-	signal One                  : std_logic;
-
-begin
-
-	INT_n <= not INT;
-	BUSRQ_n <= HOLD;
-	HLDA <= not BUSAK_n;
-	SYNC <= '1' when TState = "001" else '0';
-	VAIT <= '1' when TState = "010" else '0';
-	One <= '1';
-
-	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
-	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
-	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
-	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
-	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
-	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
-	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
-	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 0)
-		port map(
-			CEN => CLKEN,
-			M1_n => open,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => open,
-			HALT_n => HALT_n,
-			WAIT_n => READY,
-			INT_n => INT_n,
-			NMI_n => One,
-			RESET_n => RESET_n,
-			BUSRQ_n => One,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO_i,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n,
-			IntE => INTE);
-
-	process (RESET_n, CLK)
-	begin
-		if RESET_n = '0' then
-			DBIN <= '0';
-			WR_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK'event and CLK = '1' then
-			if CLKEN = '1' then
-				DBIN <= '0';
-				WR_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and READY = '0') then
-						DBIN <= IntCycle_n;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
-						DBIN <= '1';
-					end if;
-					if T2Write = 0 then
-						if TState = "010" and Write = '1' then
-							WR_n <= '0';
-						end if;
-					else
-						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
-							WR_n <= '0';
-						end if;
-					end if;
-				end if;
-				if TState = "010" and READY = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index e09def1e..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,361 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 43cea1b5..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1944 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-				  ALU_Op <= "1000";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-				  ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-				  ALU_Op <= "1010";
-				  Read_To_Reg <= '1';
-				  Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index 42cf6105..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,217 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 1c0f2638..00000000
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---      0242 : Initial release
---
---      0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal      RegsH   : Register_Image(0 to 7);
-	signal      RegsL   : Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_mist.sv
index a2b52c05..f7b02880 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_mist.sv	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_mist.sv	
@@ -22,31 +22,33 @@ localparam CONF_STR = {
 	"Vortex;;",
 	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
+	"T0,Reset;",
 	"V,v1.20.",`BUILD_DATE
 };
 
+wire  [1:0] scanlines = status[4:3];
+wire        rotate    = status[2];
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
-
-wire clk_core, clk_sys;
+wire clk_core, clk_vid;
 wire pll_locked;
 pll pll
 (
 	.inclk0(CLOCK_27),
 	.areset(),
 	.c0(clk_core),
-	.c1(clk_sys)
+	.c1(clk_vid)
 );
 
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire  [7:0] kbjoy;
 wire  [7:0] joystick_0,joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
+wire        no_csync;
 wire        key_pressed;
 wire  [7:0] key_code;
 wire        key_strobe;
@@ -65,17 +67,18 @@ wire RWE_n;
 wire Video;
 
 invaderst invaderst(
-	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Rst_n(~(status[0] | buttons[1])),
 	.Clk(clk_core),
 	.ENA(),
-	.Coin(btn_coin),
-	.Sel1Player(~btn_one_player),
-	.Sel2Player(~btn_two_players),
-	.Fire(~m_fire),
+	.Coin(m_coin1 | m_coin2),
+	.Sel1Player(~m_one_player),
+	.Sel2Player(~m_two_players),
+	.Fire(~m_fireA),
+	.Fire2(~m_fire2A),
 	.MoveLeft(~m_left),
 	.MoveRight(~m_right),
-	.MoveUp(~m_up),
-	.MoveDown(~m_down),	
+	.MoveLeft2(~m_left2),
+	.MoveRight2(~m_right2),
 	.RDB(RDB),
 	.IB(IB),
 	.RWD(RWD),
@@ -107,14 +110,14 @@ invaders_audio invaders_audio (
 	.Aud(audio)
 	);
 
-mist_video #(.COLOR_DEPTH(3)) mist_video(
-	.clk_sys(clk_sys),
+mist_video #(.COLOR_DEPTH(1)) mist_video(
+	.clk_sys(clk_vid),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({Video,Video,Video}),
-	.G({Video,Video,Video}),
-	.B({Video,Video,Video}),
+	.R(Video),
+	.G(Video),
+	.B(Video),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -122,17 +125,18 @@ mist_video #(.COLOR_DEPTH(3)) mist_video(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),
+	.rotate({1'b0,rotate}),
 	.scandoubler_disable(scandoublerD),
-	.ce_divider(0),
-	.scanlines(status[4:3]),
-	.ypbpr(ypbpr)
+	.scanlines(scanlines),
+	.ce_divider(1'b0),
+	.ypbpr(ypbpr),
+	.no_csync(no_csync)
 	);
 
 user_io #(
 	.STRLEN(($size(CONF_STR)>>3)))
 user_io(
-	.clk_sys        (clk_sys       ),
+	.clk_sys        (clk_core       ),
 	.conf_str       (CONF_STR       ),
 	.SPI_CLK        (SPI_SCK        ),
 	.SPI_SS_IO      (CONF_DATA0     ),
@@ -142,6 +146,7 @@ user_io(
 	.switches       (switches       ),
 	.scandoubler_disable (scandoublerD	  ),
 	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
 	.key_strobe     (key_strobe     ),
 	.key_pressed    (key_pressed    ),
 	.key_code       (key_code       ),
@@ -151,41 +156,30 @@ user_io(
 	);
 
 dac dac (
-	.clk_i(clk_sys),
+	.clk_i(clk_core),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
 
-wire m_up     = status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
 
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_coin  = 0;
-
-always @(posedge clk_sys) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h75: btn_up          <= key_pressed; // up
-			'h72: btn_down        <= key_pressed; // down
-			'h6B: btn_left        <= key_pressed; // left
-			'h74: btn_right       <= key_pressed; // right
-			'h76: btn_coin        <= key_pressed; // ESC
-			'h05: btn_one_player  <= key_pressed; // F1
-			'h06: btn_two_players <= key_pressed; // F2
-			'h29: btn_fire1       <= key_pressed; // Space
-		endcase
-	end
-end
+arcade_inputs inputs (
+	.clk         ( clk_core    ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( 1'b0        ),
+	.orientation ( 2'b00       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders.vhd
index 40003ea4..487212d0 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders.vhd	
@@ -63,10 +63,11 @@ entity invaderst is
 		Sel1Player      : in  std_logic;
 		Sel2Player      : in  std_logic;
 		Fire            : in  std_logic;
+		Fire2           : in  std_logic;
 		MoveLeft        : in  std_logic;
 		MoveRight       : in  std_logic;
-		MoveUp          : in  std_logic;
-		MoveDown        : in  std_logic;
+		MoveLeft2       : in  std_logic;
+		MoveRight2      : in  std_logic;
 		DIP             : in  std_logic_vector(8 downto 1);
 		RDB             : in  std_logic_vector(7 downto 0);
 		IB              : in  std_logic_vector(7 downto 0);
@@ -232,9 +233,9 @@ begin
 	GDB2(1) <= '0';--active high
 	GDB2(2) <= '0';--active high
 	GDB2(3) <= '0';--active high
-	GDB2(4) <= not Fire;--controller 2
-	GDB2(5) <= not MoveLeft;--controller 2
-	GDB2(6) <= not MoveRight;--controller 2
+	GDB2(4) <= not Fire2;--controller 2
+	GDB2(5) <= not MoveLeft2;--controller 2
+	GDB2(6) <= not MoveRight2;--controller 2
 	GDB2(7) <= '0';--active low
 
 	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.vhd
index 97a42db7..39c09b03 100644
--- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.vhd	
+++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.vhd	
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************
 
 
@@ -141,13 +141,13 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 27,
+		clk0_divide_by => 1125,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 10,
+		clk0_multiply_by => 416,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 27,
+		clk1_divide_by => 1125,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 20,
+		clk1_multiply_by => 832,
 		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -231,8 +231,8 @@ END SYN;
 -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "9.984000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "19.968000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -258,11 +258,11 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "9.98400000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "19.96800000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
@@ -307,13 +307,13 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "416"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1125"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "832"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"