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Inferno Sound Workaround

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This commit is contained in:
Marcel
2022-09-14 14:46:07 +02:00
parent 6d8602b59a
commit ccdbfa2ae7
7 changed files with 1760 additions and 3 deletions
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7
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/tshoot_sound_board.vhd
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@@ -33,7 +33,7 @@ entity tshoot_sound_board is
port( port(
clock_12 : in std_logic; clock_12 : in std_logic;
reset : in std_logic; reset : in std_logic;
hwsel : in std_logic_vector(1 downto 0);
sound_select : in std_logic_vector(7 downto 0); sound_select : in std_logic_vector(7 downto 0);
sound_trig : in std_logic; sound_trig : in std_logic;
sound_ack : out std_logic; sound_ack : out std_logic;
@@ -46,6 +46,8 @@ end tshoot_sound_board;
architecture struct of tshoot_sound_board is architecture struct of tshoot_sound_board is
constant HW_INFERNO : std_logic_vector(1 downto 0) := "10";
-- signal reset_n : std_logic; -- signal reset_n : std_logic;
signal clock_div : std_logic_vector(3 downto 0); signal clock_div : std_logic_vector(3 downto 0);
@@ -131,7 +133,8 @@ pia_rw_n <= '0' when cpu_rw_n = '0' and pia_cs = '1' else '1';
-- mux cpu in data between roms/io/wram -- mux cpu in data between roms/io/wram
cpu_di <= cpu_di <=
wram_do when wram_cs = '1' else wram_do when wram_cs = '1' else
pia_do when pia_cs = '1' else sound_select when pia_cs = '1' and hwsel = HW_INFERNO else
pia_do when pia_cs = '1' and not hwsel = HW_INFERNO else
rom_do when rom_cs = '1' else X"55"; rom_do when rom_cs = '1' else X"55";
-- pia irqs to cpu -- pia irqs to cpu

2
Arcade_MiST/Williams 6809 rev.2 Hardware/rtl/williams2.vhd
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@@ -1171,7 +1171,7 @@ tshoot_sound_board : entity work.tshoot_sound_board
port map( port map(
clock_12 => clock_12, clock_12 => clock_12,
reset => reset, reset => reset,
hwsel => hwsel,
sound_select => sound_select, sound_select => sound_select,
sound_trig => sound_trig, sound_trig => sound_trig,
sound_ack => sound_ack, sound_ack => sound_ack,

2
common/CPU/bc6502/BC6502.qip Normal file
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@@ -0,0 +1,2 @@
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) bc6502.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) addsub.v ]

56
common/CPU/bc6502/addsub.v Normal file
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@@ -0,0 +1,56 @@
/* ===============================================================
(C) 2002 Bird Computer
All rights reserved.
addsub.v
Please read the Licensing Agreement (license.html file).
Use of this file is subject to the license agreement.
You are free to use and modify this code for non-commercial
or evaluation purposes.
If you do modify the code, please state the origin and
note that you have modified the code.
Adder / subtractor module with carry in, carry and overflow
outputs. Parameterized width with a default of 32 bits.
Note: we use a trick in the adder to get carry generated
and an adder / subtractor packed into 1 LUT per bit. The
'a' and 'b' inputs are specified with an extra unused bit
on the left (pass a zero for this bit).
Also note that the carry (borrow) input for a subtract has
to be inverted. IE. ci = 1 = no borrow in.
=============================================================== */
`timescale 1ps / 1ps
module addsub(op, ci, a, b, o, co, v);
parameter DBW = 32;
input op; // 0 = add, 1 = sub
input ci; // carry in
input [DBW:0] a, b; // operands input
output [DBW-1:0] o; // result
output co; // carry out
output v; // overflow
reg [DBW+1:0] sum;
// Note XST does not like assignments to bit group on LHS
// for subtract
always @(op or ci or a or b) begin
case(op)
1'd0: sum = {a,ci} + {b,1'b1};
1'd1: sum = {a,ci} - {b,1'b1};
endcase
end
assign o = sum[DBW:1];
assign co = sum[DBW+1];
// compute overflow
assign v = (op ^ o[DBW-1] ^ b[DBW-1]) & (~op ^ a[DBW-1] ^ b[DBW-1]);
endmodule

1571
common/CPU/bc6502/bc6502.v Normal file
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85
common/CPU/bc6502/license.html Normal file
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@@ -0,0 +1,85 @@
<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
<meta name="GENERATOR" content="Microsoft FrontPage 4.0">
<meta name="ProgId" content="FrontPage.Editor.Document">
<title>Sparrow License Agreement 9</title>
</head>
<body>
<p><font color="#000080" size="4">Bird Computer License Agreement</font><br>
2/06/2002<br>
(C) 2002 Bird Computer<br>
All Rights Reserved<br>
<br>
This is a legal agreement between You and Bird Computer (&quot;BC&quot;).
Carefully read the following terms and conditions before using this Work. Your
use, distribution, or installation of this copy of the Work indicates your
acceptance of this License. If you do not agree with any of the terms of this
Agreement, then you must not install, use or distribute this Work And you must
delete, remove or otherwise destroy your copy of this Work and any portion
thereof.</p>
<p><font size="4">Definitions</font></p>
<p>1. The &quot;Work&quot; is the collection of files or file associated with
the BC 6502 Verilog Source Archive and includes the &quot;Sources&quot;
(documentation, specifications, source code, scripts and schematics) in
conjunction with the&nbsp; &quot;Outputs&quot; (binaries, configuration data,
net lists) derived from the &quot;Sources&quot;, AND any derivative work based
on the foregoing.</p>
<p>2. &quot;You&quot; specifies your person, company, or educational
institution.<br>
</p>
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</body>
</html>

40
common/TTL/ls42.v Normal file
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@@ -0,0 +1,40 @@
/*============================================================================
74LS42 - BCD to decimal decoder
Copyright (C) 2022 - Jim Gregory - https://github.com/JimmyStones/
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program. If not, see <http://www.gnu.org/licenses/>.
===========================================================================*/
`timescale 1 ps / 1 ps
`default_nettype none
module ls42
(
input wire a, b, c, d,
output wire [9:0] o
);
assign o[0] = ~(~a && ~b && ~c && ~d);
assign o[1] = ~(a && ~b && ~c && ~d);
assign o[2] = ~(~a && b && ~c && ~d);
assign o[3] = ~(a && b && ~c && ~d);
assign o[4] = ~(~a && ~b && c && ~d);
assign o[5] = ~(a && ~b && c && ~d);
assign o[6] = ~(~a && b && c && ~d);
assign o[7] = ~(a && b && c && ~d);
assign o[8] = ~(~a && ~b && ~c && d);
assign o[9] = ~(a && ~b && ~c && d);
endmodule