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Noma TriPool

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Marcel
2023-05-17 14:22:33 +02:00
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Arcade_MiST/Noma Tri-Pool Hardware/Freeze.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 16:01:18 November 25, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "16:01:18 November 25, 2020"
# Revisions
PROJECT_REVISION = "Freeze"

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Arcade_MiST/Noma Tri-Pool Hardware/Freeze.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 13:36:27 May 16, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Freeze_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Freeze.sv
set_global_assignment -name VERILOG_FILE rtl/core.v
set_global_assignment -name VERILOG_FILE rtl/decode.v
set_global_assignment -name VERILOG_FILE rtl/mcpu.v
set_global_assignment -name VERILOG_FILE rtl/decrypt_mcpu.v
set_global_assignment -name VERILOG_FILE rtl/mcpu_rom1.v
set_global_assignment -name VERILOG_FILE rtl/mcpu_rom2.v
set_global_assignment -name VERILOG_FILE rtl/scpu.v
set_global_assignment -name VERILOG_FILE rtl/scpu_rom.v
set_global_assignment -name VERILOG_FILE rtl/video.v
set_global_assignment -name VERILOG_FILE rtl/dpram.v
set_global_assignment -name VERILOG_FILE rtl/vdata.v
set_global_assignment -name VERILOG_FILE rtl/hvgen.v
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VERILOG_FILE rtl/ram.v
set_global_assignment -name VERILOG_FILE rtl/clk_en.v
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/mist/mist.qip"
set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/CPU/T80/T80.qip"
set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/Sound/JT49/jt49.qip"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name TOP_LEVEL_ENTITY Freeze
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/dect.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# --------------------
# start ENTITY(Freeze)
# Pin & Location Assignments
# ==========================
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
# Fitter Assignments
# ==================
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(Freeze)
# ------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Arcade_MiST/Noma Tri-Pool Hardware/Readme.md Normal file
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# Jack the Giantkiller
## General description
This is a port of Jack the Giantkiller from Cinematronics. It includes:
- Jack the Giantkiller
- Freeze
- Zzyzzyxx
- SuperCasino
- Tri-Pool
### TODO
- Fix MRA names and information.
- Some of the H/V switches are not working. The CPU reads it but whatever the value is, it always clears the flip register. We need to check in the original games. Cocktail mode works on Jack.
- HS/VS timings are certainly wrong.
- Fix OSD options that are not working well: reset & aspect ratio.
Thanks to all my contributors as usual!

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Arcade_MiST/Noma Tri-Pool Hardware/clean.bat Normal file
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

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Arcade_MiST/Noma Tri-Pool Hardware/meta/freeze.mra Normal file
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<misterromdescription>
<name>Freeze</name>
<homebrew>no</homebrew>
<bootleg>no</bootleg>
<series></series>
<year>1984</year>
<manufacturer>Cinematronics</manufacturer>
<category>Platform</category>
<rbf>freeze</rbf>
<about></about>
<resolution>15kHz</resolution>
<rotation>vertical</rotation>
<flip></flip>
<players>2</players>
<joystick>2-way</joystick>
<special_controls></special_controls>
<num_buttons>1</num_buttons>
<buttons names="Button1,Button2,Start1P,Start2P,CoinA,CoinB" default="A,Start,Select,R1,L1"></buttons>
<switches default="00">
<dip bits="0" name="Flip Screen" ids="Off,On"/>
<dip bits="1" name="Service Mode" ids="Off,On"/>
<dip bits="2" name="Difficulty" ids="Easy,Hard"/>
<dip bits="3" name="Lives" ids="3,5"/>
<dip bits="4,5" name="Bonus Life" ids="10000,1000/40000,10000/60000,20000/100000"/>
<dip bits="6,7" name="Coinage" ids="1C_1C,1C_2C,2C_1C,Free_Play"/>
</switches>
<rom index="0" zip="freeze.zip" md5="none">
<!-- main cpu -->
<part name="freeze.f2" crc="0a431665"/>
<part name="freeze.f3" crc="1189b8ad"/>
<part name="freeze.f4" crc="10c4a5ea"/>
<part name="freeze.f5" crc="16024c53"/>
<part name="freeze.f7" crc="ea0b0765"/>
<part name="freeze.e7" crc="1155c00b"/>
<part name="freeze.e5" crc="95c18d75"/>
<part name="freeze.e4" crc="7e8f5afc"/>
<!-- audio cpu -->
<part name="freeze.a1" crc="7771f5b9"/>
<part repeat="4096">00</part>
<!-- gfx -->
<part name="freeze.5a" crc="6c8a98a0"/>
<part name="freeze.3a" crc="6d2125e4"/>
<part name="freeze.1a" crc="3a7f2fa9"/>
<part name="freeze.2a" crc="dd70ddd6"/>
</rom>
<rom index="1"><part>0</part></rom>
<rom index="2"></rom>
<rom_3></rom_3>
<rom_4></rom_4>
<nvram></nvram>
<remark></remark>
<!-- <mratimestamp></mratimestamp> -->
</misterromdescription>

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Arcade_MiST/Noma Tri-Pool Hardware/meta/jack.mra Normal file
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<misterromdescription>
<name>Jack the Giantkiller</name>
<homebrew>no</homebrew>
<bootleg>no</bootleg>
<series></series>
<year>1982</year>
<manufacturer>Cinematronics</manufacturer>
<category>Platform</category>
<rbf>freeze</rbf>
<about></about>
<resolution>15kHz</resolution>
<rotation>vertical</rotation>
<flip></flip>
<players>2</players>
<joystick>2-way</joystick>
<special_controls></special_controls>
<num_buttons>1</num_buttons>
<buttons names="Button1,Button2,Start1P,Start2P,CoinA,CoinB" default="A,Start,Select,R1,L1"></buttons>
<switches default="00,00">
<dip bits="0,1" name="CoinB" ids="2C_1C,4C_3C,1C_1C,1C_3C"/>
<dip bits="2,3" name="CoinA" ids="3C_1C,2C_1C,4C_3C,1C_1C"/>
<dip bits="4" name="Lives" ids="3,5"/>
<dip bits="5" name="Bonus Life" ids="10000,x10000"/>
<dip bits="6" name="Difficulty" ids="Level1,Level13"/>
<dip bits="7" name="Per Bean/Bullets" ids="1,2"/>
<dip bits="8" name="Cabinet" ids="Cocktail,Upright"/>
<dip bits="13" name="Service" ids="Off,On"/>
<dip bits="14" name="Invulnerability" ids="Off,On"/>
<dip bits="15" name="255 Lives" ids="Off,On"/>
</switches>
<rom index="0" zip="jack.zip" md5="none">
<!-- main cpu -->
<part name="j8" crc="c8e73998"/>
<part name="jgk.j6" crc="36d7810e"/>
<part name="jgk.j7" crc="b15ff3ee"/>
<part name="jgk.j5" crc="4a63d242"/>
<part name="jgk.j3" crc="605514a8"/>
<part name="jgk.j4" crc="bce489b7"/>
<part name="jgk.j2" crc="db21bd55"/>
<part name="jgk.j1" crc="49fffe31"/>
<!-- audio cpu -->
<part name="jgk.j9" crc="c2dc1e00"/>
<part repeat="4096">00</part>
<!-- gfx -->
<part name="jgk.j12" crc="ce726df0"/>
<part name="jgk.j13" crc="6aec2c8d"/>
<part name="jgk.j11" crc="fd14c525"/>
<part name="jgk.j10" crc="eab890b2"/>
</rom>
<rom index="1"><part>1</part></rom>
<rom index="2"></rom>
<rom_3></rom_3>
<rom_4></rom_4>
<nvram></nvram>
<remark></remark>
<!-- <mratimestamp></mratimestamp> -->
</misterromdescription>

50
Arcade_MiST/Noma Tri-Pool Hardware/meta/sucasino.mra Normal file
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<misterromdescription>
<name>Super Casino</name>
<homebrew>no</homebrew>
<bootleg>no</bootleg>
<series></series>
<year>1984</year>
<manufacturer>Data Amusement</manufacturer>
<category>Platform</category>
<rbf>freeze</rbf>
<about></about>
<resolution>15kHz</resolution>
<rotation>vertical</rotation>
<flip></flip>
<players>2</players>
<joystick>2-way</joystick>
<special_controls></special_controls>
<num_buttons>1</num_buttons>
<buttons names="Button1,Button2,Start1P,Start2P,CoinA,CoinB" default="A,Start,Select,R1,L1"></buttons>
<switches default="00">
<dip bits="0,1" name="Coinage" ids="1C_1C,1C_2C,1C_3C,1C_4C"/>
<dip bits="2" name="Cabinet" ids="Upright,Cocktail"/>
<dip bits="3" name="FlipScreen" ids="Off,On"/>
</switches>
<rom index="0" zip="sucasino.zip" md5="none">
<!-- main cpu -->
<part name="1" crc="e116e979"/>
<part name="2" crc="2a2635f5"/>
<part name="3" crc="69864d90"/>
<part name="4" crc="174c9373"/>
<part name="5" crc="115bcb1e"/>
<part name="6" crc="434caa17"/>
<part name="7" crc="67c68b82"/>
<part name=8" crc="f5b63006"/>
<!-- audio cpu -->
<part name="9" crc="67cf8aec"/>
<part repeat="4096">00</part>
<!-- gfx -->
<part name="11" crc="f92c4c5b"/>
<part repeat="4096">00</part>
<part name=10" crc="3b0783ce"/>
<part repeat="4096">00</part>
</rom>
<rom index="1"><part>3</part></rom>
<rom index="2"></rom>
<rom_3></rom_3>
<rom_4></rom_4>
<nvram></nvram>
<remark></remark>
<!-- <mratimestamp></mratimestamp> -->
</misterromdescription>

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<misterromdescription>
<name>Tri-pool</name>
<homebrew>no</homebrew>
<bootleg>no</bootleg>
<series></series>
<year>1984</year>
<manufacturer>Noma (Casino Tech license)</manufacturer>
<category></category>
<rbf>freeze</rbf>
<about></about>
<resolution>15kHz</resolution>
<rotation>vertical</rotation>
<flip></flip>
<players>2</players>
<joystick>2-way</joystick>
<special_controls></special_controls>
<num_buttons>1</num_buttons>
<buttons names="Button1,Button2,Button3,Button4,Button5,Start1P,Start2P,CoinA,CoinB" default="A,Start,Select,R1,L1"></buttons>
<switches default="00">
<dip bits="0,1" name="CoinB" ids="1C_1C,1C_2C,1C_3C,1C_5C"/>
<dip bits="2,3" name="CoinA" ids="4C_1C,3C_1C,2C_1C,1C_1C"/>
</switches>
<rom index="0" zip="tripool.zip" md5="none">
<!-- main cpu -->
<part name="tri73a.bin" crc="96893aa7"/>
<part repeat="4096">00</part>
<part name="tri62a.bin" crc="3299dc65"/>
<part name="tri52b.bin" crc="27ef765e"/>
<part name="tri33c.bin" crc="d7ef061d"/>
<part name="tri45c.bin" crc="51b813b1"/>
<part name="tri25d.bin" crc="8e64512d"/>
<part name="tri13d.bin" crc="ad268e9b"/>
<!-- audio cpu -->
<part name="trisnd.bin" crc="945c4b8b"/>
<part repeat="4096">00</part>
<!-- gfx -->
<part name="tri105a.bin" crc="366a753c"/>
<part repeat="4096">00</part>
<part name="tri93a.bin" crc="35213782"/>
<part repeat="4096">00</part>
</rom>
<!-- decryption scheme - 0 = no encryption, 1 = treahunt, 2 = striv -->
<rom index="1"><part>4</part></rom>
<rom index="2"></rom>
<rom_3></rom_3>
<rom_4></rom_4>
<nvram></nvram>
<remark></remark>
<!-- <mratimestamp></mratimestamp> -->
</misterromdescription>

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<misterromdescription>
<name>Zzyzzyxx</name>
<homebrew>no</homebrew>
<bootleg>no</bootleg>
<series></series>
<year>1984</year>
<manufacturer>Cinematronics</manufacturer>
<category>Platform</category>
<rbf>freeze</rbf>
<about></about>
<resolution>15kHz</resolution>
<rotation>vertical</rotation>
<flip></flip>
<players>2</players>
<joystick>2-way</joystick>
<special_controls></special_controls>
<num_buttons>1</num_buttons>
<buttons names="Button1,Button2,Start1P,Start2P,CoinA,CoinB" default="A,Start,Select,R1,L1"></buttons>
<switches default="00">
<dip bits="0" name="Flip Screen" ids="Off,On"/>
<dip bits="1" name="Service Mode" ids="Off,On"/>
<dip bits="2" name="Difficulty" ids="Easy,Hard"/>
<dip bits="3" name="Lives" ids="3,5"/>
<dip bits="4,5" name="Bonus Life" ids="10000,1000/40000,10000/60000,20000/100000"/>
<dip bits="6,7" name="Coinage" ids="1C_1C,1C_2C,2C_1C,Free_Play"/>
</switches>
<rom index="0" zip="zzyzzyxx.zip" md5="none">
<!-- main cpu -->
<part name="a.2f" crc="a9102e34"/>
<part name="zzyzzyxx.b" crc="efa9d4c6"/>
<part name="zzyzzyxx.c" crc="b0a365b1"/>
<part name="zzyzzyxx.d" crc="5ed6dd9a"/>
<part name="zzyzzyxx.e" crc="5966fdbf"/>
<part name="f.7e" crc="12f24c68"/>
<part name="g.6e" crc="408f2326"/>
<part name="h.4e" crc="f8bbabe0"/>
<!-- audio cpu -->
<part name="i.5a" crc="c7742460"/>
<part name="j.6a" crc="72166ccd"/>
<!-- gfx -->
<part name="n.1c" crc="4f64538d"/>
<part name="m.1d" crc="217b1402"/>
<part name="k.1b" crc="b8b2b8cc"/>
<part name="l.1a" crc="ab421a83"/>
</rom>
<rom index="1"><part>2</part></rom>
<rom index="2"></rom>
<rom_3></rom_3>
<rom_4></rom_4>
<nvram></nvram>
<remark></remark>
<!-- <mratimestamp></mratimestamp> -->
</misterromdescription>

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module Freeze (
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"Freeze;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blend,Off,On;",
"O6,Joystick Swap,Off,On;",
// "OOR,CRT H adjust,0,+1,+2,+3,+4,+5,+6,+7,-8,-7,-6,-5,-4,-3,-2,-1;",
// "OSV,CRT V adjust,0,+1,+2,+3,+4,+5,+6,+7,-8,-7,-6,-5,-4,-3,-2,-1;",
// "OC,Monochrome,Off,On;",
// "O7,Service,Off,On;",
"T0,Reset;",
"V,v1.00.",`BUILD_DATE
};
wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire joyswap = status[6];
//wire service = status[7];
wire [1:0] orientation = 2'b01;
assign LED = ~ioctl_downl;
assign AUDIO_R = AUDIO_L;
assign SDRAM_CLK = ~clock_48;
assign SDRAM_CKE = 1;
wire [63:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [11:0] kbjoy;
wire [31:0] joystick_0;
wire [31:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire no_csync;
wire [9:0] audio;
wire hs, vs, cs;
wire hb, vb;
wire blankn = ~(hb | vb);
wire [2:0] r, g;
wire [1:0] b;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
reg reset = 1;
reg rom_loaded = 0;
always @(posedge clock_24) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | ~rom_loaded;
end
wire clock_24, clock_48, pll_locked;
pll pll(
.inclk0(CLOCK_27),
.c0(clock_48),//48 MHz
.c1(clock_24),//24 MHz
.locked(pll_locked)
);
data_io data_io(
.clk_sys ( clock_48 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(9)) mist_video(
.clk_sys ( clock_24 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? r : 3'b0),
.G ( blankn ? g : 3'b0),
.B ( blankn ? {b[1],b} : 3'b0),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.ce_divider ( 0 ),
.rotate ( { orientation[1], rotate } ),
.blend ( blend ),
.scandoubler_disable( scandoublerD ),
.scanlines ( scanlines ),
.ypbpr ( ypbpr ),
.no_csync ( no_csync )
);
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
.clk_sys (clock_24 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD),
.ypbpr (ypbpr ),
.core_mod (core_mod ),
.no_csync (no_csync ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(.C_bits(16))dac_l(
.clk_i(clock_24),
.res_n_i(1),
.dac_i({ 1'b0, audio, 5'd0 }),
.dac_o(AUDIO_L)
);
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
arcade_inputs inputs (
.clk ( clock_24 ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( rotate ),
.orientation ( orientation ),
.joyswap ( joyswap ),
.oneplayer ( 1'b0 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
);
wire [13:0] mcpu_rom1_addr;
wire [15:0] mcpu_rom1_data;
wire [13:0] mcpu_rom2_addr;
wire [15:0] mcpu_rom2_data;
reg port1_req;
sdram #(48) sdram(
.*,
.init_n ( pll_locked ),
.clk ( clock_48 ),
// port1
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port1_we ( ioctl_downl ),
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_addr ( ioctl_downl ? 16'hffff : {2'b00, mcpu_rom1_addr[13:1]} ),
.cpu1_q ( mcpu_rom1_data ),
.cpu2_addr ( ioctl_downl ? 16'hffff : {2'b00, mcpu_rom2_addr[13:1] + 16'h2000} ),//check
.cpu2_q ( mcpu_rom2_data ),
// port2
.port2_req ( ),
.port2_ack ( ),
.port2_a ( ),
.port2_ds ( ),
.port2_we ( ),
.port2_d ( ),
.port2_q ( ),
.bg_addr ( ),
.bg_q ( )
);
// ROM download controller
always @(posedge clock_48) begin
reg ioctl_wr_last = 0;
ioctl_wr_last <= ioctl_wr;
if (ioctl_downl) begin
if (~ioctl_wr_last && ioctl_wr) begin
port1_req <= ~port1_req;
end
end
end
//wire [7:0] DSW1 = ~status[15:8];
//wire [7:0] DSW2 = ~status[23:16];
wire btn_A, btn_B, btn_C;
always @* begin
if(key_strobe) begin
case(key_code)
'h1C: btn_A <= key_pressed; // A
'h32: btn_B <= key_pressed; // B
'h21: btn_C <= key_pressed; // C
endcase
end
end
wire [7:0] p0, p1, p2, p3;
wire [6:0] core_mod;
always @* begin
case (core_mod)
7'h0: begin // freeze
p0 = { 2'b0, m_coin1 , 3'b0, m_two_players, m_one_player };//unknown
p1 = { m_left2, m_right2, m_down2, m_up2, m_left, m_right, m_down, m_up };
p2 = { 6'd0, m_fireB, m_fireA };
p3 = { 6'd0, m_fire2B, m_fire2A };
end
7'h1: begin // jack
p0 = { 1'b0, m_coin1, m_coin2 , 3'b0, m_two_players, m_one_player };
p1 = { m_down2, m_up2, m_right2, m_left2, m_down, m_up, m_right, m_left };
p2 = { 6'd0, m_fireB, m_fireA };
p3 = { 6'd0, m_fire2B, m_fire2A };
end
7'h2: begin // zzyzzyxx
p0 = { 1'b0, m_coin1, m_coin2 , 3'b0, m_two_players, m_one_player };
p1 = { m_down2, m_up2, m_right2, m_left2, m_down, m_up, m_right, m_left };
p2 = { 6'd0, m_fireB, m_fireA };
p3 = { 6'd0, m_fire2B, m_fire2A };
end
7'h3: begin // super casino
p0 = { 1'b0, m_coin1, 4'b0, m_two_players, m_one_player };
p1 = { m_down2, m_up2, 1'b0, 1'b0, m_down, m_up, 1'b0, 1'b0 };
p2 = { 6'd0, m_fireB, m_fireA };
p3 = { 6'd0, m_fire2B, m_fire2A };
end
7'h4: begin // tri-pool
p0 = { 1'b0, m_coin1, m_coin2 , btn_C, btn_B, btn_A, m_two_players, m_one_player };
p1 = { m_down2, m_up2, m_right2, m_left2, m_down, m_up, m_right, m_left };
p2 = { 6'd0, m_fireB, m_fireA };
p3 = { 6'd0, m_fire2B, m_fire2A };
end
default;
endcase
end
core core(
.reset (reset),
.clk_sys (clock_48),
.dsw1 (DSW1),
.dsw2 (DSW2),
.p0 (p0),
.p1 (p1),
.p2 (p2),
.p3 (p3),
.red (r),
.green (g),
.blue (b),
.hb (hb),
.vb (vb),
.hs (hs),
.vs (vs),
.ce_pix (),//out
.sound (audio),
.mcpu_rom1_addr (mcpu_rom1_addr),
.mcpu_rom1_data (mcpu_rom1_addr[0] ? mcpu_rom1_data[15:8] : mcpu_rom1_data[7:0]),
.mcpu_rom2_addr (mcpu_rom2_addr),
.mcpu_rom2_data (mcpu_rom2_addr[0] ? mcpu_rom2_data[15:8] : mcpu_rom2_data[7:0]),
.ioctl_download (ioctl_downl),
.ioctl_addr (ioctl_addr),
.ioctl_dout (ioctl_dout),
.ioctl_wr (ioctl_wr)
);
endmodule

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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module clk_en #(
parameter DIV=12,
parameter OFFSET=0
)
(
input ref_clk,
output reg cen,
output reg clk
);
reg [15:0] cnt = OFFSET;
always @(posedge ref_clk) begin
if (cnt == DIV) clk <= 1'b1;
if (cnt == (DIV >> 1)) clk <= 1'b0;
if (cnt == DIV) begin
cnt <= 16'd0;
cen <= 1'b1;
end
else begin
cen <= 1'b0;
cnt <= cnt + 16'd1;
end
end
endmodule

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module core(
input reset,
input clk_sys,
input [7:0] dsw1,
input [7:0] dsw2,
input [7:0] p0,
input [7:0] p1,
input [7:0] p2,
input [7:0] p3,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output hb,
output vb,
output hs,
output vs,
output ce_pix,
output [9:0] sound,
output [13:0] mcpu_rom1_addr,
input [7:0] mcpu_rom1_data,
output [13:0] mcpu_rom2_addr,
input [7:0] mcpu_rom2_data,
input ioctl_download,
input [26:0] ioctl_addr,
input [15:0] ioctl_dout,
input ioctl_wr
// input [7:0] encryption
);
wire [15:0] mcpu_ab;
wire [7:0] mcpu_din;
wire [7:0] mcpu_dout;
wire mcpu_rd;
wire mcpu_wr;
wire mcpu_io;
wire mcpu_m1;
wire [15:0] scpu_ab;
wire [7:0] scpu_din;
wire [7:0] scpu_dout;
wire scpu_rd;
wire scpu_wr;
wire scpu_io;
wire scpu_m1;
// enable signals
wire scpu_io_en = scpu_io;
wire mcpu_rom1_en;
wire mcpu_rom2_en;
wire mcpu_ram_en;
wire mcpu_spram_en;
wire mcpu_sndlatch_en;
wire mcpu_dsw1_en;
wire mcpu_dsw2_en;
wire mcpu_in0_en;
wire mcpu_in1_en;
wire mcpu_in2_en;
wire mcpu_in3_en;
wire mcpu_flip_en;
wire mcpu_pal_en;
wire mcpu_vram_en;
wire mcpu_cram_en;
wire scpu_rom_en;
wire scpu_ram_en;
wire scpu_ay_data_en;
wire scpu_ay_addr_en;
//wire [7:0] mcpu_rom1_data;
//wire [7:0] mcpu_rom2_data;
wire [7:0] mcpu_ram_data;
wire [7:0] mcpu_vdata;
reg [7:0] mcpu_sndlatch;
wire [7:0] scpu_rom_data;
wire [7:0] scpu_ram_data;
reg scpu_int;
wire [12:0] char_rom_addr;
wire [7:0] char_data1;
wire [7:0] char_data2;
wire [12:0] spr_rom_addr;
wire [7:0] spr_data1;
wire [7:0] spr_data2;
reg [3:0] ay_addr;
wire [7:0] ay_dout;
wire mcpu_vdata_en = mcpu_vram_en | mcpu_cram_en | mcpu_spram_en;
wire [7:0] decrypt_data_out;
assign mcpu_din =
mcpu_in0_en ? p0 :
mcpu_in1_en ? p1 :
mcpu_in2_en ? p2 :
mcpu_in3_en ? p3 :
mcpu_dsw1_en ? dsw1 :
mcpu_dsw2_en ? dsw2 :
mcpu_rom1_en ? decrypt_data_out :
mcpu_rom2_en ? mcpu_rom2_data :
mcpu_ram_en ? mcpu_ram_data :
mcpu_vdata_en ? mcpu_vdata :
8'd0;
assign scpu_din =
scpu_ram_en ? scpu_ram_data :
scpu_rom_en ? scpu_rom_data :
scpu_ay_data_en & scpu_rd ? ay_dout :
8'd0;
always @(posedge clk_sys) begin
if (scpu_ay_addr_en) begin
if (scpu_wr) ay_addr <= scpu_dout[3:0];
end
if (mcpu_sndlatch_en) begin
mcpu_sndlatch <= mcpu_dout;
scpu_int <= 1'b1;
end
else begin
scpu_int <= 1'b0;
end
end
decode decode(
.mcpu_ab ( mcpu_ab ),
.scpu_ab ( scpu_ab ),
.scpu_io_en ( scpu_io_en ),
.mcpu_rom1_en ( mcpu_rom1_en ),
.mcpu_rom2_en ( mcpu_rom2_en ),
.mcpu_ram_en ( mcpu_ram_en ),
.mcpu_spram_en ( mcpu_spram_en ),
.mcpu_sndlatch_en ( mcpu_sndlatch_en ),
.mcpu_dsw1_en ( mcpu_dsw1_en ),
.mcpu_dsw2_en ( mcpu_dsw2_en ),
.mcpu_in0_en ( mcpu_in0_en ),
.mcpu_in1_en ( mcpu_in1_en ),
.mcpu_in2_en ( mcpu_in2_en ),
.mcpu_in3_en ( mcpu_in3_en ),
.mcpu_flip_en ( mcpu_flip_en ),
.mcpu_pal_en ( mcpu_pal_en ),
.mcpu_vram_en ( mcpu_vram_en ),
.mcpu_cram_en ( mcpu_cram_en ),
.scpu_rom_en ( scpu_rom_en ),
.scpu_ram_en ( scpu_ram_en ),
.scpu_ay_data_en ( scpu_ay_data_en ),
.scpu_ay_addr_en ( scpu_ay_addr_en )
);
mcpu mcpu(
.clk_sys ( clk_sys ),
.reset ( reset ),
.mcpu_din ( mcpu_din ),
.mcpu_dout ( mcpu_dout ),
.mcpu_ab ( mcpu_ab ),
.mcpu_wr ( mcpu_wr ),
.mcpu_rd ( mcpu_rd ),
.mcpu_io ( mcpu_io ),
.mcpu_m1 ( mcpu_m1 ),
.vb ( vb )
);
scpu scpu(
.clk_sys ( clk_sys ),
.reset ( reset ),
.scpu_din ( scpu_din ),
.scpu_dout ( scpu_dout ),
.scpu_ab ( scpu_ab ),
.scpu_wr ( scpu_wr ),
.scpu_rd ( scpu_rd ),
.scpu_io ( scpu_io ),
.scpu_m1 ( scpu_m1 ),
.scpu_int ( scpu_int )
);
wire cen, cen_t;
clk_en #(16-1) jt49_clk_en(clk_sys, cen);
clk_en #(512) timer_clk_en(clk_sys, cen_t); // 512 seems not fast enough
reg [7:0] timer;
always @(posedge clk_sys)
if (cen_t) timer <= timer + 1;
jt49 u_jt49(
.rst_n ( ~reset ),
.clk ( clk_sys ),
.clk_en ( cen ),
.addr ( ay_addr ),
.cs_n ( ~scpu_ay_data_en ),
.wr_n ( ~(scpu_ay_data_en & scpu_wr) ),
.din ( scpu_dout ),
.sel ( 1'b0 ),
.dout ( ay_dout ),
.sound ( sound ),
.IOA_in ( mcpu_sndlatch ),
.IOB_in ( timer[7:0] )
);
decrypt_mcpu decrypt_mcpu(
.encryption ( 1'b0 ),
.data_in ( mcpu_rom1_data ),
.addr ( mcpu_ab ),
.data_out ( decrypt_data_out )
);
assign mcpu_rom1_addr = mcpu_ab[13:0];
//mcpu_rom1 mcpu_rom1(
// .clk_sys ( clk_sys ),
// .rom_data ( mcpu_rom1_data ),
// .cpu_ab ( mcpu_ab ),
// .ioctl_download ( ioctl_download ),
// .ioctl_addr ( ioctl_addr ),
// .ioctl_dout ( ioctl_dout ),
// .ioctl_wr ( ioctl_wr )
//);
assign mcpu_rom2_addr = mcpu_ab[13:0];
//mcpu_rom2 mcpu_rom2(
// .clk_sys ( clk_sys ),
// .rom_data ( mcpu_rom2_data ),
// .cpu_ab ( mcpu_ab ),
// .ioctl_download ( ioctl_download ),
// .ioctl_addr ( ioctl_addr ),
// .ioctl_dout ( ioctl_dout ),
// .ioctl_wr ( ioctl_wr )
//);
scpu_rom scpu_rom(
.clk_sys ( clk_sys ),
.rom_data ( scpu_rom_data ),
.cpu_ab ( scpu_ab ),
.ioctl_download ( ioctl_download ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout ),
.ioctl_wr ( ioctl_wr )
);
ram #(13,8) mcpu_ram(
.clk ( clk_sys ),
.addr ( mcpu_ab[12:0] ),
.din ( mcpu_dout ),
.q ( mcpu_ram_data ),
.rd_n ( ~mcpu_rd ),
.wr_n ( ~mcpu_wr ),
.ce_n ( ~mcpu_ram_en )
);
ram #(10,8) scpu_ram(
.clk ( clk_sys ),
.addr ( scpu_ab[9:0] ),
.din ( scpu_dout ),
.q ( scpu_ram_data ),
.rd_n ( ~scpu_rd ),
.wr_n ( ~scpu_wr ),
.ce_n ( ~scpu_ram_en )
);
vdata u_vdata(
.clk_sys ( clk_sys ),
.char_rom_addr ( char_rom_addr ),
.char_data1 ( char_data1 ),
.char_data2 ( char_data2 ),
.spr_rom_addr ( spr_rom_addr ),
.spr_data1 ( spr_data1 ),
.spr_data2 ( spr_data2 ),
.ioctl_download ( ioctl_download ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout ),
.ioctl_wr ( ioctl_wr )
);
video video(
.reset ( reset ),
.clk_sys ( clk_sys ),
.hb ( hb ),
.vb ( vb ),
.hs ( hs ),
.vs ( vs ),
.ce_pix ( ce_pix ),
.mcpu_ab ( mcpu_ab ),
.mcpu_data ( mcpu_dout ),
.mcpu_wr ( mcpu_wr ),
.mcpu_rd ( mcpu_rd ),
.mcpu_vdata ( mcpu_vdata ),
.mcpu_pal_en ( mcpu_pal_en ),
.mcpu_spram_en ( mcpu_spram_en ),
.mcpu_vram_en ( mcpu_vram_en ),
.mcpu_cram_en ( mcpu_cram_en ),
.mcpu_flip_en ( mcpu_flip_en ),
.char_rom_addr ( char_rom_addr ),
.char_data1 ( char_data1 ),
.char_data2 ( char_data2 ),
.spr_rom_addr ( spr_rom_addr ),
.spr_data1 ( spr_data1 ),
.spr_data2 ( spr_data2 ),
.red ( red ),
.green ( green ),
.blue ( blue )
);
endmodule

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module decode(
input [15:0] mcpu_ab,
input [15:0] scpu_ab,
input scpu_io_en,
output reg mcpu_rom1_en,
output reg mcpu_rom2_en,
output reg mcpu_ram_en,
output reg mcpu_spram_en,
output reg mcpu_sndlatch_en,
output reg mcpu_dsw1_en,
output reg mcpu_dsw2_en,
output reg mcpu_in0_en,
output reg mcpu_in1_en,
output reg mcpu_in2_en,
output reg mcpu_in3_en,
output reg mcpu_flip_en,
output reg mcpu_pal_en,
output reg mcpu_vram_en,
output reg mcpu_cram_en,
output reg scpu_rom_en,
output reg scpu_ram_en,
output reg scpu_ay_data_en,
output reg scpu_ay_addr_en
);
always @* begin
mcpu_rom1_en = 1'b0;
mcpu_rom2_en = 1'b0;
mcpu_ram_en = 1'b0;
mcpu_spram_en = 1'b0;
mcpu_sndlatch_en = 1'b0;
mcpu_dsw1_en = 1'b0;
mcpu_dsw2_en = 1'b0;
mcpu_in0_en = 1'b0;
mcpu_in1_en = 1'b0;
mcpu_in2_en = 1'b0;
mcpu_in3_en = 1'b0;
mcpu_flip_en = 1'b0;
mcpu_pal_en = 1'b0;
mcpu_vram_en = 1'b0;
mcpu_cram_en = 1'b0;
scpu_rom_en = 1'b0;
scpu_ram_en = 1'b0;
scpu_ay_data_en = 1'b0;
scpu_ay_addr_en = 1'b0;
if (mcpu_ab < 16'h4000) begin
mcpu_rom1_en = 1'b1;
end else if (mcpu_ab >= 16'h4000 && mcpu_ab < 16'h6000) begin
mcpu_ram_en = 1'b1;
end else if (mcpu_ab >= 16'hb000 && mcpu_ab < 16'hb080) begin
mcpu_spram_en = 1'b1;
end else if (mcpu_ab == 16'hb400) begin
mcpu_sndlatch_en = 1'b1;
end else if (mcpu_ab == 16'hb500) begin
mcpu_dsw1_en = 1'b1;
end else if (mcpu_ab == 16'hb501) begin
mcpu_dsw2_en = 1'b1;
end else if (mcpu_ab == 16'hb502) begin
mcpu_in0_en = 1'b1;
end else if (mcpu_ab == 16'hb503) begin
mcpu_in1_en = 1'b1;
end else if (mcpu_ab == 16'hb504) begin
mcpu_in2_en = 1'b1;
end else if (mcpu_ab == 16'hb505) begin
mcpu_in3_en = 1'b1;
end else if (mcpu_ab >= 16'hb506 && mcpu_ab < 16'hb508) begin
mcpu_flip_en = 1'b1;
end else if (mcpu_ab >= 16'hb600 && mcpu_ab < 16'hb620) begin
mcpu_pal_en = 1'b1;
end else if (mcpu_ab >= 16'hb800 && mcpu_ab < 16'hbc00) begin
mcpu_vram_en = 1'b1;
end else if (mcpu_ab >= 16'hbc00 && mcpu_ab < 16'hc000) begin
mcpu_cram_en = 1'b1;
end else if (mcpu_ab >= 16'hc000) begin
mcpu_rom2_en = 1'b1;
end
if (scpu_io_en) begin
if (scpu_ab[7:0] == 8'h40) begin
scpu_ay_data_en = 1'b1;
end else if (scpu_ab[7:0] == 8'h80) begin
scpu_ay_addr_en = 1'b1;
end
end
else begin
if (scpu_ab < 16'h2000) begin
scpu_rom_en = 1'b1;
end else if (scpu_ab >= 16'h4000 && scpu_ab < 16'h6000) begin
scpu_ram_en = 1'b1;
end
end
end
endmodule

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module decrypt_mcpu(
input [7:0] encryption,
input [7:0] data_in,
input [15:0] addr,
output reg [7:0] data_out
);
always @* begin
case (encryption)
8'd0: data_out = data_in;
8'd1: data_out = {
addr[13] ? (~addr[2] ? ~data_in[0] : data_in[0]) : ~data_in[7],
data_in[2],
data_in[5],
data_in[1],
data_in[3],
data_in[6],
data_in[4],
addr[13] ? (~addr[2] ? ~data_in[7] : data_in[7]) : ~data_in[0]
};
8'd2: data_out = {
addr[13] ? (~addr[2] ? ~data_in[0] : data_in[0]) : ~data_in[7],
data_in[2],
data_in[5],
data_in[1],
data_in[3],
data_in[6],
data_in[4],
addr[13] ? (~addr[2] ? ~data_in[7] : data_in[7]) : ~data_in[0]
};
default;
endcase
end
endmodule

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// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dpram
#(
parameter ADDRWIDTH=12,
parameter DATAWIDTH=8
)
(
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
rden_a,
rden_b,
q_a,
q_b);
input [ADDRWIDTH-1:0] address_a;
input [ADDRWIDTH-1:0] address_b;
input clock;
input [DATAWIDTH-1:0] data_a;
input [DATAWIDTH-1:0] data_b;
input wren_a;
input wren_b;
input rden_a;
input rden_b;
output [DATAWIDTH-1:0] q_a;
output [DATAWIDTH-1:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [DATAWIDTH-1:0] sub_wire0;
wire [DATAWIDTH-1:0] sub_wire1;
wire [DATAWIDTH-1:0] q_a = rden_a ? sub_wire0[DATAWIDTH-1:0] : {DATAWIDTH{1'b0}};
wire [DATAWIDTH-1:0] q_b = rden_b ? sub_wire1[DATAWIDTH-1:0] : {DATAWIDTH{1'b0}};
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2**ADDRWIDTH,
altsyncram_component.numwords_b = 2**ADDRWIDTH,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = ADDRWIDTH,
altsyncram_component.widthad_b = ADDRWIDTH,
altsyncram_component.width_a = DATAWIDTH,
altsyncram_component.width_b = DATAWIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule

39
Arcade_MiST/Noma Tri-Pool Hardware/rtl/hvgen.v Normal file
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module hvgen(
input clk_sys,
output reg hb, vb, hs, vs,
output reg [8:0] hcount, vcount,
output reg ce_pix
);
wire cen_vid;
clk_en #(8-1) hclk_en(clk_sys, cen_vid);
// 256x240 - 384/264
always @(posedge clk_sys) begin
ce_pix <= 1'b0;
if (cen_vid) begin
ce_pix <= 1'b1;
hcount <= hcount + 9'd1;
case (hcount)
1: hb <= 1'b0;
257: hb <= 1'b1;
308: hs <= 1'b0;
340: hs <= 1'b1;
383: begin
vcount <= vcount + 9'd1;
hcount <= 9'b0;
case (vcount)
15: vb <= 1'b0;
239: vb <= 1'b1;
249: vs <= 1'b0;
252: vs <= 1'b1;
263: vcount <= 9'd0;
endcase
end
endcase
end
end
endmodule

88
Arcade_MiST/Noma Tri-Pool Hardware/rtl/mcpu.v Normal file
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module mcpu(
input clk_sys,
input reset,
input [7:0] mcpu_din,
output [7:0] mcpu_dout,
output [15:0] mcpu_ab,
output mcpu_wr,
output mcpu_rd,
output mcpu_io,
output mcpu_m1,
input vb
);
wire mcpu_rd_n;
wire mcpu_wr_n;
wire mcpu_m1_n;
wire mcpu_mreq_n;
wire mcpu_iorq_n;
wire mcpu_rfsh_n;
wire mcpu_wait_n = 1'b1;
reg mcpu_int_n = 1'b1;
wire mcpu_nmi_n = 1'b1;
assign mcpu_io = ~mcpu_iorq_n;
assign mcpu_m1 = ~mcpu_m1_n;
assign mcpu_wr = ~mcpu_wr_n;
assign mcpu_rd = ~mcpu_rd_n;
wire cen;
clk_en #(16-1) mcpu_clk_en(clk_sys, cen);
reg old_vb;
reg [7:0] data_latch;
always @(posedge clk_sys) begin
old_vb <= vb;
if (~old_vb & vb) mcpu_int_n <= 1'b0;
if (~(mcpu_iorq_n|mcpu_m1_n)) mcpu_int_n <= 1'b1;
if (~mcpu_rd_n) data_latch <= mcpu_din;
end
//`define TV80_REFRESH 1
//tv80s cpu(
// .reset_n ( ~reset ),
// .clk ( clk_sys ),
// .cen ( cen ),
// .wait_n ( mcpu_wait_n ),
// .int_n ( mcpu_int_n ),
// .nmi_n ( mcpu_nmi_n ),
// .busrq_n ( 1'b1 ),
// .m1_n ( mcpu_m1_n ),
// .mreq_n ( mcpu_mreq_n ),
// .iorq_n ( mcpu_iorq_n ),
// .rd_n ( mcpu_rd_n ),
// .wr_n ( mcpu_wr_n ),
// .rfsh_n ( mcpu_rfsh_n ),
// .halt_n ( ),
// .busak_n ( ),
// .A ( mcpu_ab ),
// .di ( data_latch ),
// .dout ( mcpu_dout )
//);
defparam T80se_inst.Mode = 0;
defparam T80se_inst.T2Write = 0;
defparam T80se_inst.IOWait = 1;
T80se T80se_inst(
.RESET_n ( ~reset ),
.CLK_n ( clk_sys ),
.CLKEN ( cen ),
.WAIT_n ( mcpu_wait_n ),
.INT_n ( mcpu_int_n ),
.NMI_n ( mcpu_nmi_n ),
.BUSRQ_n ( 1'b1 ),
.M1_n ( mcpu_m1_n ),
.MREQ_n ( mcpu_mreq_n ),
.IORQ_n ( mcpu_iorq_n ),
.RD_n ( mcpu_rd_n ),
.WR_n ( mcpu_wr_n ),
.RFSH_n ( mcpu_rfsh_n ),
.HALT_n ( ),
.BUSAK_n ( ),
.A ( mcpu_ab ),
.DI ( data_latch ),
.DO ( mcpu_dout )
);
endmodule

26
Arcade_MiST/Noma Tri-Pool Hardware/rtl/mcpu_rom1.v Normal file
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module mcpu_rom1(
input clk_sys,
output [7:0] rom_data,
input [15:0] cpu_ab,
input ioctl_download,
input [26:0] ioctl_addr,
input [15:0] ioctl_dout,
input ioctl_wr
);
wire [13:0] rom_addr = ioctl_download ? ioctl_addr[13:0] : cpu_ab[13:0];
wire rom_wr = ioctl_download && ioctl_addr < 27'h4000 ? ioctl_wr : 1'b0;
ram #(14,8) rom(
.clk ( clk_sys ),
.addr ( rom_addr ),
.din ( ioctl_dout ),
.q ( rom_data ),
.rd_n ( 1'b0 ),
.wr_n ( ~rom_wr ),
.ce_n ( 1'b0 )
);
endmodule

26
Arcade_MiST/Noma Tri-Pool Hardware/rtl/mcpu_rom2.v Normal file
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@@ -0,0 +1,26 @@
module mcpu_rom2(
input clk_sys,
output [7:0] rom_data,
input [15:0] cpu_ab,
input ioctl_download,
input [26:0] ioctl_addr,
input [15:0] ioctl_dout,
input ioctl_wr
);
wire [13:0] rom_addr = ioctl_download ? ioctl_addr[13:0] - 27'h4000 : cpu_ab[13:0];
wire rom_wr = ioctl_download && ioctl_addr >= 27'h4000 && ioctl_addr < 27'h8000 ? ioctl_wr : 1'b0;
ram #(14,8) rom(
.clk ( clk_sys ),
.addr ( rom_addr ),
.din ( ioctl_dout ),
.q ( rom_data ),
.rd_n ( 1'b0 ),
.wr_n ( ~rom_wr ),
.ce_n ( 1'b0 )
);
endmodule

4
Arcade_MiST/Noma Tri-Pool Hardware/rtl/pll.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

348
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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 9,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 16,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 9,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 8,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "8"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

30
Arcade_MiST/Noma Tri-Pool Hardware/rtl/ram.v Normal file
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@@ -0,0 +1,30 @@
module ram
#(
parameter addr_width=12,
parameter data_width=8
)
(
input clk,
input [addr_width-1:0] addr,
input [data_width-1:0] din,
output [data_width-1:0] q,
input rd_n,
input wr_n,
input ce_n
);
reg [data_width-1:0] data;
reg [data_width-1:0] mem[(1<<addr_width)-1:0];
assign q = ~ce_n ? data : 0;
always @(posedge clk) begin
if (~rd_n) data <= mem[addr];
if (~wr_n & ~ce_n) mem[addr] <= din;
end
endmodule

87
Arcade_MiST/Noma Tri-Pool Hardware/rtl/scpu.v Normal file
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@@ -0,0 +1,87 @@
module scpu(
input clk_sys,
input reset,
input [7:0] scpu_din,
output [7:0] scpu_dout,
output [15:0] scpu_ab,
output scpu_wr,
output scpu_rd,
output scpu_io,
output scpu_m1,
input scpu_int
);
wire scpu_rd_n;
wire scpu_wr_n;
wire scpu_m1_n;
wire scpu_mreq_n;
wire scpu_iorq_n;
wire scpu_rfsh_n;
wire scpu_wait_n = 1'b1;
reg scpu_int_n = 1'b1;
wire scpu_nmi_n = 1'b1;
assign scpu_io = ~scpu_iorq_n;
assign scpu_m1 = ~scpu_m1_n;
assign scpu_wr = ~scpu_wr_n;
assign scpu_rd = ~scpu_rd_n;
wire cen;
clk_en #(16-1) scpu_clk_en(clk_sys, cen);
reg old_int;
reg [7:0] data_latch;
always @(posedge clk_sys) begin
old_int <= scpu_int;
if (~old_int & scpu_int) scpu_int_n <= 1'b0;
if (~(scpu_iorq_n|scpu_m1_n)) scpu_int_n <= 1'b1;
if (~scpu_rd_n) data_latch <= scpu_din;
end
//`define TV80_REFRESH 1
//tv80s cpu(
// .reset_n ( ~reset ),
// .clk ( clk_sys ),
// .cen ( cen ),
// .wait_n ( scpu_wait_n ),
// .int_n ( scpu_int_n ),
// .nmi_n ( scpu_nmi_n ),
// .busrq_n ( 1'b1 ),
// .m1_n ( scpu_m1_n ),
// .mreq_n ( scpu_mreq_n ),
// .iorq_n ( scpu_iorq_n ),
// .rd_n ( scpu_rd_n ),
// .wr_n ( scpu_wr_n ),
// .rfsh_n ( scpu_rfsh_n ),
// .halt_n ( ),
// .busak_n ( ),
// .A ( scpu_ab ),
// .di ( data_latch ),
// .dout ( scpu_dout )
//);
defparam T80se_inst.Mode = 0;
defparam T80se_inst.T2Write = 0;
defparam T80se_inst.IOWait = 1;
T80se T80se_inst(
.RESET_n ( ~reset ),
.CLK_n ( clk_sys ),
.CLKEN ( cen ),
.WAIT_n ( scpu_wait_n ),
.INT_n ( scpu_int_n ),
.NMI_n ( scpu_nmi_n ),
.BUSRQ_n ( 1'b1 ),
.M1_n ( scpu_m1_n ),
.MREQ_n ( scpu_mreq_n ),
.IORQ_n ( scpu_iorq_n ),
.RD_n ( scpu_rd_n ),
.WR_n ( scpu_wr_n ),
.RFSH_n ( scpu_rfsh_n ),
.HALT_n ( ),
.BUSAK_n ( ),
.A ( scpu_ab ),
.DI ( data_latch ),
.DO ( scpu_dout )
);
endmodule

26
Arcade_MiST/Noma Tri-Pool Hardware/rtl/scpu_rom.v Normal file
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@@ -0,0 +1,26 @@
module scpu_rom(
input clk_sys,
output [7:0] rom_data,
input [15:0] cpu_ab,
input ioctl_download,
input [26:0] ioctl_addr,
input [15:0] ioctl_dout,
input ioctl_wr
);
wire [12:0] rom_addr = ioctl_download ? ioctl_addr[12:0] - 27'h8000 : cpu_ab[12:0];
wire rom_wr = ioctl_download && ioctl_addr >= 27'h8000 && ioctl_addr < 27'ha000 ? ioctl_wr : 1'b0;
ram #(13,8) rom(
.clk ( clk_sys ),
.addr ( rom_addr ),
.din ( ioctl_dout ),
.q ( rom_data ),
.rd_n ( 1'b0 ),
.wr_n ( ~rom_wr ),
.ce_n ( 1'b0 )
);
endmodule

337
Arcade_MiST/Noma Tri-Pool Hardware/rtl/sdram.sv Normal file
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@@ -0,0 +1,337 @@
//
// sdram.v
//
// sdram controller implementation for the MiST board
// https://github.com/mist-devel/mist-board
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
// Copyright (c) 2019 Gyorgy Szombathelyi
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
output reg SDRAM_DQML, // two byte masks
output reg SDRAM_DQMH, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
// cpu/chipset interface
input init_n, // init signal after FPGA config to initialize RAM
input clk, // sdram clock
input port1_req,
output reg port1_ack,
input port1_we,
input [23:1] port1_a,
input [1:0] port1_ds,
input [15:0] port1_d,
output [15:0] port1_q,
input [16:1] cpu1_addr,
output reg [15:0] cpu1_q,
input [16:1] cpu2_addr,
output reg [15:0] cpu2_q,
input port2_req,
output reg port2_ack,
input port2_we,
input [23:1] port2_a,
input [1:0] port2_ds,
input [15:0] port2_d,
output [15:0] port2_q,
input [15:1] bg_addr,
output reg [15:0] bg_q
);
parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us
localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
/*
SDRAM state machine for 2 bank interleaved access
1 word burst, CL2
cmd issued registered
0 RAS0 cas1
1 ras0
2 CAS0 data1 returned
3 RAS1 cas0
4 ras1
5 CAS1 data0 returned
*/
localparam STATE_RAS0 = 3'd0; // first state in cycle
localparam STATE_RAS1 = 3'd3; // Second ACTIVE command after RAS0 + tRRD (15ns)
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 3
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 5
localparam STATE_READ0 = 3'd0; //STATE_CAS0 + CAS_LATENCY + 1'd1; // 7
localparam STATE_READ1 = 3'd3;
localparam STATE_LAST = 3'd5;
reg [2:0] t;
always @(posedge clk) begin
t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
reg init = 1'b1;
always @(posedge clk, negedge init_n) begin
if(!init_n) begin
reset <= 5'h1f;
init <= 1'b1;
end else begin
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
init <= !(reset == 0);
end
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
reg [15:0] sd_din;
// drive control signals according to current command
assign SDRAM_nCS = sd_cmd[3];
assign SDRAM_nRAS = sd_cmd[2];
assign SDRAM_nCAS = sd_cmd[1];
assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[2];
reg [24:1] addr_latch_next[2];
reg [16:1] addr_last[2];
reg [16:1] addr_last2[2];
reg [15:0] din_latch[2];
reg [1:0] oe_latch;
reg [1:0] we_latch;
reg [1:0] ds[2];
reg port1_state;
reg port2_state;
localparam PORT_NONE = 2'd0;
localparam PORT_CPU1 = 2'd1;
localparam PORT_TILE = 2'd2;
localparam PORT_REQ = 2'd3;
localparam PORT_SND = 2'd1;
reg [2:0] next_port[2];
reg [2:0] port[2];
reg refresh;
reg [10:0] refresh_cnt;
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
// PORT1: bank 0,1
always @(*) begin
if (refresh) begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end else if (port1_req ^ port1_state) begin
next_port[0] = PORT_REQ;
addr_latch_next[0] = { 1'b0, port1_a };
end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
next_port[0] = PORT_CPU1;
addr_latch_next[0] = { 8'd0, cpu1_addr };
end else if (cpu2_addr != addr_last[PORT_TILE]) begin
next_port[0] = PORT_TILE;
addr_latch_next[0] = { 8'd0, cpu2_addr };
end else begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end
end
// PORT2: bank 2,3
always @(*) begin
if (port2_req ^ port2_state) begin
next_port[1] = PORT_REQ;
addr_latch_next[1] = { 1'b1, port2_a };
end else if (bg_addr != addr_last2[PORT_SND]) begin
next_port[1] = PORT_SND;
addr_latch_next[1] = { 1'b1, 8'd0, bg_addr };
end else begin
next_port[1] = PORT_NONE;
addr_latch_next[1] = addr_latch[1];
end
end
always @(posedge clk) begin
// permanently latch ram data to reduce delays
sd_din <= SDRAM_DQ;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
sd_cmd <= CMD_NOP; // default: idle
refresh_cnt <= refresh_cnt + 1'd1;
if(init) begin
// initialization takes place at the end of the reset phase
if(t == STATE_RAS0) begin
if(reset == 15) begin
sd_cmd <= CMD_PRECHARGE;
SDRAM_A[10] <= 1'b1; // precharge all banks
end
if(reset == 10 || reset == 8) begin
sd_cmd <= CMD_AUTO_REFRESH;
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
SDRAM_A <= MODE;
SDRAM_BA <= 2'b00;
end
end
end else begin
// RAS phase
// bank 0,1
if(t == STATE_RAS0) begin
addr_latch[0] <= addr_latch_next[0];
port[0] <= next_port[0];
{ oe_latch[0], we_latch[0] } <= 2'b00;
if (next_port[0] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[0][22:10];
SDRAM_BA <= addr_latch_next[0][24:23];
addr_last[next_port[0]] <= addr_latch_next[0][16:1];
if (next_port[0] == PORT_REQ) begin
{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
ds[0] <= port1_ds;
din_latch[0] <= port1_d;
port1_state <= port1_req;
end else begin
{ oe_latch[0], we_latch[0] } <= 2'b10;
ds[0] <= 2'b11;
end
end
end
// bank 2,3
if(t == STATE_RAS1) begin
refresh <= 1'b0;
addr_latch[1] <= addr_latch_next[1];
{ oe_latch[1], we_latch[1] } <= 2'b00;
port[1] <= next_port[1];
if (next_port[1] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[1][22:10];
SDRAM_BA <= addr_latch_next[1][24:23];
addr_last2[next_port[1]] <= addr_latch_next[1][15:1];
if (next_port[1] == PORT_REQ) begin
{ oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we };
ds[1] <= port2_ds;
din_latch[1] <= port2_d;
port2_state <= port1_req;
end else begin
{ oe_latch[1], we_latch[1] } <= 2'b10;
ds[1] <= 2'b11;
end
end
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
refresh <= 1'b1;
refresh_cnt <= 0;
sd_cmd <= CMD_AUTO_REFRESH;
end
end
// CAS phase
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
if (we_latch[0]) begin
SDRAM_DQ <= din_latch[0];
port1_ack <= port1_req;
end
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[0][24:23];
end
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if (we_latch[1]) begin
SDRAM_DQ <= din_latch[1];
port2_ack <= port2_req;
end
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[1][24:23];
end
// Data returned
if(t == STATE_READ0 && oe_latch[0]) begin
case(port[0])
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1: begin cpu1_q <= sd_din; end
PORT_TILE: begin cpu2_q <= sd_din; end
default: ;
endcase;
end
if(t == STATE_READ1 && oe_latch[1]) begin
case(port[1])
PORT_REQ: begin port2_q <= sd_din; port2_ack <= port2_req; end
PORT_SND: begin bg_q <= sd_din; end
default: ;
endcase;
end
end
end
endmodule

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY spram IS
generic (
addr_width_g : integer := 8;
data_width_g : integer := 8
);
PORT
(
address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
);
END spram;
ARCHITECTURE SYN OF spram IS
BEGIN
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "NORMAL",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**addr_width_g,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => addr_width_g,
width_a => data_width_g,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
clocken0 => clken,
data_a => data,
wren_a => wren,
q_a => q
);
END SYN;

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module vdata(
input clk_sys,
// input [14:0] map_rom_addr,
// output [7:0] map_data,
input [12:0] char_rom_addr,
output [7:0] char_data1,
output [7:0] char_data2,
input [12:0] spr_rom_addr,
output [7:0] spr_data1,
output [7:0] spr_data2,
input ioctl_download,
input [26:0] ioctl_addr,
input [15:0] ioctl_dout,
input ioctl_wr
);
wire [12:0] chr_addr1 = ioctl_download ? ioctl_addr - 27'ha000 : char_rom_addr;
wire [12:0] chr_addr2 = ioctl_download ? ioctl_addr - 27'hc000 : char_rom_addr;
wire gfx_wr1 = ioctl_download && ioctl_addr >= 27'ha000 && ioctl_addr < 27'hc000 ? ioctl_wr : 1'b0;
wire gfx_wr2 = ioctl_download && ioctl_addr >= 27'hc000 && ioctl_addr < 27'he000 ? ioctl_wr : 1'b0;
dpram #(13,8) gfx_rom1(
.address_a ( chr_addr1 ),
.address_b ( spr_rom_addr ),
.clock ( clk_sys ),
.data_a ( ioctl_dout ),
.data_b ( ),
.wren_a ( gfx_wr1 ),
.wren_b ( ),
.rden_a ( 1'b1 ),
.rden_b ( 1'b1 ),
.q_a ( char_data1 ),
.q_b ( spr_data1 )
);
dpram #(13,8) gfx_rom2(
.address_a ( chr_addr2 ),
.address_b ( spr_rom_addr ),
.clock ( clk_sys ),
.data_a ( ioctl_dout ),
.data_b ( ),
.wren_a ( gfx_wr2 ),
.wren_b ( ),
.rden_a ( 1'b1 ),
.rden_b ( 1'b1 ),
.q_a ( char_data2 ),
.q_b ( spr_data2 )
);
endmodule

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module video(
input reset,
input clk_sys,
output hb,
output vb,
output hs,
output vs,
output ce_pix,
input [15:0] mcpu_ab,
input [7:0] mcpu_data,
input mcpu_wr,
input mcpu_rd,
input mcpu_pal_en,
input mcpu_spram_en,
input mcpu_vram_en,
input mcpu_cram_en,
input mcpu_flip_en,
output [7:0] mcpu_vdata,
output reg [12:0] char_rom_addr,
input [7:0] char_data1,
input [7:0] char_data2,
output reg [12:0] spr_rom_addr,
input [7:0] spr_data1,
input [7:0] spr_data2,
output reg [2:0] red,
output reg [2:0] green,
output reg [1:0] blue
);
reg vflip;
reg hflip;
always @(posedge clk_sys) begin
if (mcpu_flip_en) begin
if (mcpu_ab[0]) begin // flip set
vflip <= 1'b1;
hflip <= 1'b0;
end
else begin // flip clear
vflip <= 1'b0;
hflip <= 1'b1;
end
end
end
wire [8:0] hc;
wire [8:0] vc;
wire [8:0] hcount = hc^{9{hflip}};
wire [8:0] vcount = vc^{9{vflip}};
wire [7:0] mcpu_pal_data;
wire [7:0] mcpu_spr_data0;
wire [7:0] mcpu_spr_data1;
wire [7:0] mcpu_spr_data2;
wire [7:0] mcpu_spr_data3;
wire [7:0] mcpu_vram_data;
wire [7:0] mcpu_cram_data;
reg [9:0] cram_addr;
reg [9:0] vram_addr;
reg [4:0] pal_addr;
wire [7:0] cram_data;
wire [7:0] vram_data;
wire [7:0] pal_data;
reg [4:0] bg_color_data;
wire [3:0] spram_cs = { 3'b0, mcpu_spram_en } << mcpu_ab[1:0];
assign mcpu_vdata =
spram_cs[0] ? mcpu_spr_data0 :
spram_cs[1] ? mcpu_spr_data1 :
spram_cs[2] ? mcpu_spr_data2 :
spram_cs[3] ? mcpu_spr_data3 :
mcpu_vram_en ? mcpu_vram_data :
mcpu_cram_en ? mcpu_cram_data :
8'd0;
// h/v flip logic could be simplfied a lot but I don't want to spend more time on this
reg [4:0] sp_addr;
wire [7:0] sp_data0;
wire [7:0] sp_data1;
wire [7:0] sp_data2;
wire [7:0] sp_data3;
reg [4:0] sb[511:0];
wire sc1 = spr_data1[xp^{3{~sp_data3[7]}}];
wire sc2 = spr_data2[xp^{3{~sp_data3[7]}}];
wire [7:0] yy = vflip ? 8'd250 - sp_data0^{8{vflip}} : 8'd255 - sp_data0^{8{vflip}};
reg [7:0] xx;
reg [2:0] xp;
wire [2:0] yp = vflip ? vc - yy - 1 : yy - vc;
reg [7:0] xcl;
reg render;
always @(posedge clk_sys) begin
if (hc >= 9'h100) begin
sb[{ ~vc[0], xcl }] <= 5'd0;
xcl <= xcl + 8'd1;
end
if (ce_pix && hc < 9'h100) begin
if (hc == 0) sp_addr <= 5'd31;
else if (render) begin
if (sc1|sc2) sb[{ vc[0], xx+xp }] <= { sp_data3[2:0], sc1, sc2 };
xp <= xp + 3'd1;
if (xp == 3'd7) begin
render <= 1'b0;
sp_addr <= sp_addr - 5'd1;
end
end
else if (sp_addr >= 0) begin
if (yy >= vc && yy < vc+8) begin
xp <= 0;
xx <= sp_data1;
spr_rom_addr <= { sp_data3[3], sp_data2, yp^{3{sp_data3[6]}} };
render <= 1'b1;
end
else begin
sp_addr <= sp_addr - 5'd1;
end
end
end
end
reg cnt;
always @(posedge clk_sys) begin
cnt <= ~cnt;
if (~cnt) begin
hd <= hflip ? hcount[7:0]+8'd1 : hcount[7:0]-8'd1;
vram_addr <= { hcount[7:3], vcount[7:3] };
cram_addr <= { hcount[7:3], vcount[7:3] };
end
else begin
char_rom_addr <= { cram_data[4:3], vram_data, 3'd7-vcount[2:0] };
end
end
reg [5:0] sp_col;
wire [7:0] col = 8'hff ^ pal_data;
reg [7:0] hd;
always @(posedge clk_sys) begin
sp_col <= sb[{ ~vc[0], hcount[7:0] }];
if (~cnt) begin
pal_addr <= (|sp_col[1:0]) ?
sp_col :
{ cram_data[2:0], char_data1[3'd7^hd[2:0]], char_data2[3'd7^hd[2:0]] };
end
else begin
blue <= col[7:6];
green <= col[5:3];
red <= col[2:0];
end
end
dpram #(5,8) pal(
.clock ( clk_sys ),
.address_a ( mcpu_ab[4:0] ),
.data_a ( mcpu_data ),
.q_a ( mcpu_pal_data ),
.rden_a ( mcpu_rd ),
.wren_a ( mcpu_wr & mcpu_pal_en ),
.address_b ( pal_addr ),
.data_b ( ),
.q_b ( pal_data ),
.wren_b ( ),
.rden_b ( 1'b1 )
);
dpram #(5,8) spram0(
.clock ( clk_sys ),
.address_a ( mcpu_ab[6:2] ),
.data_a ( mcpu_data ),
.q_a ( mcpu_spr_data0 ),
.rden_a ( mcpu_rd & spram_cs[0] ),
.wren_a ( mcpu_wr & spram_cs[0] ),
.address_b ( sp_addr ),
.data_b ( ),
.q_b ( sp_data0 ),
.wren_b ( ),
.rden_b ( 1'b1 )
);
dpram #(5,8) spram1(
.clock ( clk_sys ),
.address_a ( mcpu_ab[6:2] ),
.data_a ( mcpu_data ),
.q_a ( mcpu_spr_data1 ),
.rden_a ( mcpu_rd & spram_cs[1] ),
.wren_a ( mcpu_wr & spram_cs[1] ),
.address_b ( sp_addr ),
.data_b ( ),
.q_b ( sp_data1 ),
.wren_b ( ),
.rden_b ( 1'b1 )
);
dpram #(5,8) spram2(
.clock ( clk_sys ),
.address_a ( mcpu_ab[6:2] ),
.data_a ( mcpu_data ),
.q_a ( mcpu_spr_data2 ),
.rden_a ( mcpu_rd & spram_cs[2] ),
.wren_a ( mcpu_wr & spram_cs[2] ),
.address_b ( sp_addr ),
.data_b ( ),
.q_b ( sp_data2 ),
.wren_b ( ),
.rden_b ( 1'b1 )
);
dpram #(5,8) spram3(
.clock ( clk_sys ),
.address_a ( mcpu_ab[6:2] ),
.data_a ( mcpu_data ),
.q_a ( mcpu_spr_data3 ),
.rden_a ( mcpu_rd & spram_cs[3] ),
.wren_a ( mcpu_wr & spram_cs[3] ),
.address_b ( sp_addr ),
.data_b ( ),
.q_b ( sp_data3 ),
.wren_b ( ),
.rden_b ( 1'b1 )
);
dpram #(10,8) vram(
.clock ( clk_sys ),
.address_a ( mcpu_ab[9:0] ),
.data_a ( mcpu_data ),
.q_a ( mcpu_vram_data ),
.rden_a ( mcpu_rd & mcpu_vram_en ),
.wren_a ( mcpu_wr & mcpu_vram_en ),
.address_b ( vram_addr ),
.data_b ( ),
.q_b ( vram_data ),
.wren_b ( ),
.rden_b ( 1'b1 )
);
dpram #(10,8) cram(
.clock ( clk_sys ),
.address_a ( mcpu_ab[9:0] ),
.data_a ( mcpu_data ),
.q_a ( mcpu_cram_data ),
.rden_a ( mcpu_rd & mcpu_cram_en ),
.wren_a ( mcpu_wr & mcpu_cram_en ),
.address_b ( cram_addr ),
.data_b ( ),
.q_b ( cram_data ),
.wren_b ( ),
.rden_b ( 1'b1 )
);
hvgen u_hvgen(
.clk_sys ( clk_sys ),
.hb ( hb ),
.vb ( vb ),
.hs ( hs ),
.vs ( vs ),
.hcount ( hc ),
.vcount ( vc ),
.ce_pix ( ce_pix )
);
endmodule