diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.srf b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.srf deleted file mode 100644 index 14cddd5e..00000000 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.srf +++ /dev/null @@ -1,54 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Release/Centipede.rbf b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Release/Centipede.rbf index ba674f37..0f2f9fc0 100644 Binary files a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Release/Centipede.rbf and b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Release/Centipede.rbf differ diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede.sv b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede.sv index b69b5d73..90732e01 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede.sv +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede.sv @@ -44,7 +44,7 @@ localparam CONF_STR = { "Centipede;;", "O1,Test,off,on;", "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", - "O5,Joystick Control,Upright,Normal;", + "O5,Joystick Control,Normal,Upright;", "T7,Reset;", "V,v1.00.",`BUILD_DATE }; @@ -75,15 +75,16 @@ pll pll .c4(clk_100mhz) ); -wire m_up = status[5] ? ~kbjoy[6] & ~joystick_0[1] & ~joystick_1[1] : ~kbjoy[4] & ~joystick_0[3] & ~joystick_1[3]; -wire m_down = status[5] ? ~kbjoy[7] & ~joystick_0[0] & ~joystick_1[0] : ~kbjoy[5] & ~joystick_0[2] & ~joystick_1[2]; -wire m_left = status[5] ? ~kbjoy[5] & ~joystick_0[2] & ~joystick_1[2] : ~kbjoy[6] & ~joystick_0[1] & ~joystick_1[1]; -wire m_right = status[5] ? ~kbjoy[4] & ~joystick_0[3] & ~joystick_1[3] : ~kbjoy[7] & ~joystick_0[0] & ~joystick_1[0]; +wire m_up = ~status[5] ? ~kbjoy[7] & ~joystick_0[0] & ~joystick_1[0] : ~kbjoy[4] & ~joystick_0[3] & ~joystick_1[3]; +wire m_down = ~status[5] ? ~kbjoy[6] & ~joystick_0[1] & ~joystick_1[1] : ~kbjoy[5] & ~joystick_0[2] & ~joystick_1[2]; +wire m_left = ~status[5] ? ~kbjoy[4] & ~joystick_0[3] & ~joystick_1[3] : ~kbjoy[6] & ~joystick_0[1] & ~joystick_1[1]; +wire m_right = ~status[5] ? ~kbjoy[5] & ~joystick_0[2] & ~joystick_1[2] : ~kbjoy[7] & ~joystick_0[0] & ~joystick_1[0]; +wire m_start1 = ~kbjoy[1]; +wire m_start2 = ~kbjoy[2]; +wire m_coin = ~kbjoy[3]; wire m_fire1 = ~kbjoy[0] & ~joystick_0[4] & ~joystick_1[4];// & ~joystick_0[4] & ~joystick_1[4]; wire m_fire2 = ~kbjoy[0] & ~joystick_0[5] & ~joystick_1[5];// & ~joystick_0[4] & ~joystick_1[4]; -wire m_start2 = 1'b1; -wire m_start1 = ~kbjoy[3];//ESC //wire l_coin = ~kbjoy[3]; wire l_coin, c_coin, r_coin = 1'b1; wire m_test = ~status[1]; diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/build_id.v b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/build_id.v index 18f92372..fd2c27be 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/build_id.v +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/build_id.v @@ -1,2 +1,2 @@ -`define BUILD_DATE "181218" -`define BUILD_TIME "200200" +`define BUILD_DATE "181220" +`define BUILD_TIME "180518" diff --git a/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/Release/ZigZag.rbf b/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/Release/ZigZag.rbf index 5922254b..b8e039fc 100644 Binary files a/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/Release/ZigZag.rbf and b/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/Release/ZigZag.rbf differ diff --git a/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/ZigZag.qsf b/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/ZigZag.qsf index 315d5299..f9e440fa 100644 --- a/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/ZigZag.qsf +++ b/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/ZigZag.qsf @@ -49,14 +49,12 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" set_global_assignment -name SYSTEMVERILOG_FILE rtl/ZigZag_MiST.sv set_global_assignment -name VHDL_FILE rtl/ZigZag.vhd set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd set_global_assignment -name VHDL_FILE rtl/mc_sprite.vhd set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_clut.vhd set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd diff --git a/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/ZigZag_MiST.sv b/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/ZigZag_MiST.sv index 9b8f210f..c5393f03 100644 --- a/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/ZigZag_MiST.sv +++ b/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/ZigZag_MiST.sv @@ -42,7 +42,7 @@ module ZigZag_MiST localparam CONF_STR = { "ZigZag;;", - "O2,Joystick Control,Upright,Normal;", + "O2,Joystick Control,Normal,Upright;", "O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;", "T6,Reset;", "V,v1.10.",`BUILD_DATE @@ -73,15 +73,18 @@ pll pll .c3(clk_6) ); -wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; -wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; -wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; -wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; +wire m_up = ~status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = ~status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = ~status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = ~status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; wire m_start1 = kbjoy[1]; wire m_start2 = kbjoy[2]; wire m_coin = kbjoy[3]; +wire m_skip = kbjoy[9]; + + ZigZag ZigZag ( diff --git a/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/build_id.v b/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/build_id.v index 45ead923..879bf68d 100644 --- a/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/build_id.v +++ b/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/build_id.v @@ -1,2 +1,2 @@ `define BUILD_DATE "181220" -`define BUILD_TIME "145810" +`define BUILD_TIME "173859" diff --git a/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/mc_clut.vhd b/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/mc_clut.vhd deleted file mode 100644 index ed0163d1..00000000 --- a/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/mc_clut.vhd +++ /dev/null @@ -1,24 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity mc_clut is -port ( - clk : in std_logic; - addr : in std_logic_vector(4 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of mc_clut is - type rom is array(0 to 31) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"00",X"C7",X"F0",X"3F",X"00",X"DB",X"C6",X"38",X"00",X"F0",X"15",X"1F",X"00",X"F6",X"06",X"07", - X"00",X"91",X"07",X"F6",X"00",X"F0",X"FE",X"07",X"00",X"38",X"07",X"FE",X"00",X"07",X"3F",X"FE"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/mc_col_pal.vhd index bc90d26b..2fa20b6d 100644 --- a/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/mc_col_pal.vhd +++ b/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/mc_col_pal.vhd @@ -34,11 +34,16 @@ architecture RTL of MC_COL_PAL is signal W_COL_ROM_DO : std_logic_vector(7 downto 0); begin - clut : entity work.mc_clut + +clut : entity work.sprom + generic map ( + init_file => "./Rom/col.hex", + widthad_a => 5, + width_a => 8) port map ( - CLK => I_CLK_6M, - ADDR => I_COL(2 downto 0) & I_VID(1 downto 0), - DATA => W_COL_ROM_DO + address => I_COL(2 downto 0) & I_VID(1 downto 0), + clock => I_CLK_6M, + q => W_COL_ROM_DO ); --- VID OUT -------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/mc_stars.vhd deleted file mode 100644 index b91197b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/ZigZag_MiST/rtl/mc_stars.vhd +++ /dev/null @@ -1,90 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA STARS --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity MC_STARS is - port ( - I_CLK_18M : in std_logic; - I_CLK_6M : in std_logic; - I_H_FLIP : in std_logic; - I_V_SYNC : in std_logic; - I_8HF : in std_logic; - I_256HnX : in std_logic; - I_1VF : in std_logic; - I_2V : in std_logic; - I_STARS_ON : in std_logic; - I_STARS_OFFn : in std_logic; - - O_R : out std_logic_vector(1 downto 0); - O_G : out std_logic_vector(1 downto 0); - O_B : out std_logic_vector(1 downto 0); - O_NOISE : out std_logic - ); -end; - -architecture RTL of MC_STARS is - signal CLK_1C : std_logic := '0'; - signal W_2D_Qn : std_logic := '0'; - - signal W_3B : std_logic := '0'; - signal noise : std_logic := '0'; - signal W_2A : std_logic := '0'; - signal W_4P : std_logic := '0'; - signal CLK_1AB : std_logic := '0'; - signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); - signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); -begin - O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); - CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); - W_3B <= W_2D_Qn xor W_1AB_Q(4); - - W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; - W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); - - O_NOISE <= noise ; - - process(I_2V) - begin - if rising_edge(I_2V) then - noise <= W_2D_Qn; - end if; - end process; - - process(CLK_1C, I_V_SYNC) - begin - if(I_V_SYNC = '1') then - W_1C_Q <= (others => '0'); - elsif rising_edge(CLK_1C) then - W_1C_Q <= W_1C_Q(0) & '1'; - end if; - end process; - - process(CLK_1AB, I_STARS_ON) - begin - if(I_STARS_ON = '0') then - W_1AB_Q <= (others => '0'); - W_2D_Qn <= '1'; - elsif rising_edge(CLK_1AB) then - W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; - W_2D_Qn <= not W_1AB_Q(15); - end if; - end process; -end RTL;