diff --git a/Arcade_MiST/Sega System 1 Hardware/Segasys1.sdc b/Arcade_MiST/Sega System 1 Hardware/Segasys1.sdc
index 8cd4fc88..c1a8b04e 100644
--- a/Arcade_MiST/Sega System 1 Hardware/Segasys1.sdc
+++ b/Arcade_MiST/Sega System 1 Hardware/Segasys1.sdc
@@ -53,8 +53,8 @@ set_time_format -unit ns -decimal_places 3
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
-set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
-set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
+set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
+set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
#**************************************************************
# Create Generated Clock
#**************************************************************
diff --git a/Arcade_MiST/Sega System 1 Hardware/meta/Pitfall II.mra b/Arcade_MiST/Sega System 1 Hardware/meta/Pitfall II.mra
index 762a69e7..540f5875 100644
--- a/Arcade_MiST/Sega System 1 Hardware/meta/Pitfall II.mra
+++ b/Arcade_MiST/Sega System 1 Hardware/meta/Pitfall II.mra
@@ -15,7 +15,7 @@
- 04
+ 00
diff --git a/Arcade_MiST/Sega System 1 Hardware/rtl/HVGEN.v b/Arcade_MiST/Sega System 1 Hardware/rtl/HVGEN.v
index bb0f2f20..9838a60a 100644
--- a/Arcade_MiST/Sega System 1 Hardware/rtl/HVGEN.v
+++ b/Arcade_MiST/Sega System 1 Hardware/rtl/HVGEN.v
@@ -23,41 +23,41 @@ module HVGEN
reg [8:0] hcnt = 0;
reg [8:0] vcnt = 0;
-assign HPOS = hcnt-9'd16;
+assign HPOS = hcnt;
assign VPOS = vcnt;
-wire [8:0] HS_B = 9'd288+(HOFFS*2'd2);
+wire [8:0] HS_B = 9'd462+(HOFFS*2'd2);
wire [8:0] HS_E = 9'd32+(HS_B);
-wire [8:0] HS_N = 9'd447+(HS_E-9'd320);
wire [8:0] VS_B = 9'd226+(VOFFS*3'd4);
wire [8:0] VS_E = 9'd4+(VS_B);
-wire [8:0] VS_N = 9'd481+(VS_E-9'd230);
always @(posedge CLK) begin
if (PCLK_EN) begin
hcnt <= hcnt + 1'd1;
case (hcnt)
- 25: HBLK <= H240;
- 37: HBLK <= 0;
- 277: HBLK <= H240;
- 281: HBLK <= 1;
- 511: begin
- hcnt <= 0;
+ 13: HBLK <= H240;
+ 21: HBLK <= 0;
+ 261: HBLK <= H240;
+ 269: begin
+ hcnt <= 9'd462; // original: 0-255, 448-511 = 320, now: 0-269, 462-511 = 320
+ HBLK <= 1;
+ vcnt <= vcnt + 1'd1;
case (vcnt)
- 223: begin VBLK <= 1; vcnt <= vcnt+9'd1; end
- 511: begin VBLK <= 0; vcnt <= 0; end
- default: vcnt <= vcnt+9'd1;
+ 223: VBLK <= 1;
+ 255: vcnt <= 9'd505;
+ 511: VBLK <= 0;
+ default: ;
endcase
end
- default: hcnt <= hcnt+9'd1;
+ default: ;
endcase
if (hcnt==HS_B) begin HSYN <= 0; end
- if (hcnt==HS_E) begin HSYN <= 1; hcnt <= HS_N; end
+ if (hcnt==HS_E) begin HSYN <= 1; end
if (vcnt==VS_B) begin VSYN <= 0; end
- if (vcnt==VS_E) begin VSYN <= 1; vcnt <= VS_N; end
+ if (vcnt==VS_E) begin VSYN <= 1; end
oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB;
end
diff --git a/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1.v b/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1.v
index dac44aac..412e54db 100644
--- a/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1.v
+++ b/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1.v
@@ -5,7 +5,7 @@
*********************************************************************/
module SEGASYSTEM1
(
- input clk48M,
+ input clk40M,
input reset,
input [7:0] INP0,
@@ -47,7 +47,7 @@ SEGASYS1_MAIN Main (
.RESET(reset),
.INP0(INP0),.INP1(INP1),.INP2(INP2),
.DSW0(DSW0),.DSW1(DSW1),
- .CLK48M(clk48M),
+ .CLK40M(clk40M),
.CPUAD(CPUAD),.CPUDO(CPUDO),.CPUWR(CPUWR),
.VBLK(VBLK),.VIDCS(VIDCS),.VIDDO(VIDDO),
.SNDRQ(SNDRQ),.SNDNO(SNDNO),
@@ -62,7 +62,7 @@ SEGASYS1_MAIN Main (
// Video
wire [7:0] OPIX;
SEGASYS1_VIDEO Video (
- .RESET(reset),.VCLKx8(clk48M),
+ .RESET(reset),.VCLKx8(clk40M),
.PH(PH),.PV(PV),.VFLP(VIDMD[7]),
.VBLK(VBLK),.PCLK_EN(PCLK_EN),.RGB8(OPIX),.PALDSW(1'b0),
@@ -78,7 +78,7 @@ assign POUT = VIDMD[4] ? 8'd0 : OPIX;
// Sound
SEGASYS1_SOUND Sound(
- clk48M, reset, SNDNO, SNDRQ, SOUT,
+ clk40M, reset, SNDNO, SNDRQ, SOUT,
snd_rom_addr, snd_rom_do
);
diff --git a/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1_MAIN.v b/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1_MAIN.v
index 40c02cea..071c35f0 100644
--- a/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1_MAIN.v
+++ b/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1_MAIN.v
@@ -5,7 +5,7 @@
module SEGASYS1_MAIN
(
- input CLK48M,
+ input CLK40M,
input RESET,
@@ -38,12 +38,17 @@ module SEGASYS1_MAIN
input ROMEN
);
-reg [3:0] clkdiv;
-always @(posedge CLK48M) clkdiv <= clkdiv+1'd1;
-wire CLK3M_EN = clkdiv[2:0] == 0;
-
-wire AXSCL = CLK48M;
-wire CPUCL_EN = CLK3M_EN;
+reg [4:0] clkdiv;
+reg CLK4M_EN;
+always @(posedge CLK40M) begin
+ clkdiv <= clkdiv+1'd1;
+ CLK4M_EN <= 0;
+ if (clkdiv == 9) begin
+ clkdiv <= 0;
+ CLK4M_EN <= 1;
+ end
+end
+wire CPUCL_EN = CLK4M_EN;
wire [7:0] CPUDI;
wire CPURD;
@@ -54,7 +59,7 @@ wire _cpu_rd, _cpu_wr;
Z80IP maincpu(
.reset(RESET),
- .clk(CLK48M),
+ .clk(CLK40M),
.clk_en(CPUCL_EN),
.adr(CPUAD),
.data_in(CPUDI),
@@ -88,7 +93,7 @@ wire [7:0] cpu_rd_mrom1;
wire [14:0] rad;
wire [7:0] rdt;
-SEGASYS1_PRGDEC decr(AXSCL,cpu_m1,CPUAD,cpu_rd_mrom0, rad,rdt, ROMCL,ROMAD,ROMDT,ROMEN);
+SEGASYS1_PRGDEC decr(CLK40M,cpu_m1,CPUAD,cpu_rd_mrom0, rad,rdt, ROMCL,ROMAD,ROMDT,ROMEN);
assign cpu_rom_addr = CPUAD[15] ? CPUAD[15:0] : {1'b0, rad};
assign rdt = cpu_rom_do;
@@ -101,7 +106,7 @@ assign cpu_rd_mrom1 = cpu_rom_do;
// Work RAM
wire [7:0] cpu_rd_mram;
wire cpu_cs_mram = (CPUAD[15:12] == 4'b1100) & cpu_mreq;
-SRAM_4096 mainram(CLK48M, CPUAD[11:0], cpu_rd_mram, cpu_cs_mram & CPUWR, CPUDO );
+SRAM_4096 mainram(CLK40M, CPUAD[11:0], cpu_rd_mram, cpu_cs_mram & CPUWR, CPUDO );
// Video mode latch & Sound Request
@@ -111,7 +116,7 @@ wire cpu_cs_vidm = ((CPUAD[7:0] == 8'h15)|(CPUAD[7:0] == 8'h19)) & cpu_iorq;
wire cpu_wr_sreq = cpu_cs_sreq & _cpu_wr;
wire cpu_wr_vidm = cpu_cs_vidm & _cpu_wr;
-always @(posedge CLK48M or posedge RESET) begin
+always @(posedge CLK40M or posedge RESET) begin
if (RESET) begin
VIDMD <= 0;
SNDRQ <= 0;
@@ -125,16 +130,12 @@ end
// CPU data selector
-dataselector6 mcpudisel(
- CPUDI,
- VIDCS & cpu_mreq, VIDDO,
- cpu_cs_vidm, VIDMD,
- cpu_cs_port, cpu_rd_port,
- cpu_cs_mram, cpu_rd_mram,
- cpu_cs_mrom0, cpu_rd_mrom0,
- cpu_cs_mrom1, cpu_rd_mrom1,
- 8'hFF
-);
+assign CPUDI = (VIDCS & cpu_mreq) ? VIDDO :
+ cpu_cs_vidm ? VIDMD :
+ cpu_cs_port ? cpu_rd_port :
+ cpu_cs_mram ? cpu_rd_mram :
+ cpu_cs_mrom0 ? cpu_rd_mrom0 :
+ cpu_cs_mrom1 ? cpu_rd_mrom1 : 8'hFF;
endmodule
@@ -162,15 +163,12 @@ wire cs_portA = (CPUAD[4:2] == 3'b0_11) & ~CPUAD[0] & CPUIO;
wire cs_portB =(((CPUAD[4:2] == 3'b0_11) & CPUAD[0]) | (CPUAD[4:2] == 3'b1_00)) & CPUIO;
wire [7:0] inp;
-dataselector5 dsel(
- inp,
- cs_port1,INP0,
- cs_port2,INP1,
- cs_portS,INP2,
- cs_portA,DSW0,
- cs_portB,DSW1,
- 8'hFF
-);
+
+assign inp = cs_port1 ? INP0 :
+ cs_port2 ? INP1 :
+ cs_portS ? INP2 :
+ cs_portA ? DSW0 :
+ cs_portB ? DSW1 : 8'hFF;
assign DV = cs_port1|cs_port2|cs_portS|cs_portA|cs_portB;
assign OD = inp;
diff --git a/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1_SOUND.v b/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1_SOUND.v
index 3127e030..87dc0693 100644
--- a/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1_SOUND.v
+++ b/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1_SOUND.v
@@ -4,7 +4,7 @@
module SEGASYS1_SOUND
(
- input clk48M,
+ input clk40M,
input reset,
input [7:0] sndno,
@@ -21,7 +21,7 @@ module SEGASYS1_SOUND
// ClockGen
//----------------------------------
wire clk8M_en,clk4M_en,clk2M_en;
-SndClkGen clkgen(clk48M,clk8M_en,clk4M_en,clk2M_en);
+SndClkGen clkgen(clk40M,clk8M_en,clk4M_en,clk2M_en);
//----------------------------------
// Z80 (1.5625MHz)
@@ -39,7 +39,7 @@ SndADec adec(
);
Z80IP cpu(
- .clk(clk48M),
+ .clk(clk40M),
.clk_en(clk4M_en & cpuwait_n),
.reset(reset),
.adr(cpu_ad),
@@ -63,19 +63,14 @@ assign snd_rom_addr = cpu_ad[12:0];
assign rom_dt = snd_rom_do;
//DLROM #(13,8) subir( cpuclkx2, cpu_ad[12:0], rom_dt, ROMCL,ROMAD,ROMDT,ROMEN & `EN_SCPU );
-SRAM_2048 wram( clk48M, cpu_ad[10:0], ram_do, cpu_wr_ram, cpu_do );
-
-dataselector3 scpudisel(
- cpu_di,
- cpu_cs_rom, rom_dt,
- cpu_cs_ram, ram_do,
- cpu_cs_com, comlatch,
- 8'hFF
-);
+SRAM_2048 wram( clk40M, cpu_ad[10:0], ram_do, cpu_wr_ram, cpu_do );
+assign cpu_di = cpu_cs_rom ? rom_dt :
+ cpu_cs_ram ? ram_do :
+ cpu_cs_com ? comlatch : 8'hFF;
SndPlayReq sndreq (
- clk48M, clk8M_en, reset,
+ clk40M, clk8M_en, reset,
sndno, sndstart,
cpu_irq, cpu_irqa,
cpu_nmi, cpu_nmia,
@@ -91,7 +86,7 @@ wire psg0wait, psg1wait;
wire cpuwait_n = psg0wait & psg1wait;
sn76489_top psg0(
- .clock_i(clk48M),
+ .clock_i(clk40M),
.clock_en_i(clk2M_en),
.res_n_i(~reset),
.ce_n_i(~(cpu_cs_psg0 & cpu_mreq)),
@@ -102,7 +97,7 @@ sn76489_top psg0(
);
sn76489_top psg1(
- .clock_i(clk48M),
+ .clock_i(clk40M),
.clock_en_i(clk4M_en),
.res_n_i(~reset),
.ce_n_i(~(cpu_cs_psg1 & cpu_mreq)),
@@ -120,21 +115,21 @@ endmodule
module SndClkGen
(
- input clk48M,
+ input clk40M,
output clk8M_en,
output clk4M_en,
output clk2M_en
);
reg [4:0] count;
-always @( posedge clk48M ) begin
+always @( posedge clk40M ) begin
count <= count + 1'd1;
- if (count == 23) count <= 0;
+ if (count == 19) count <= 0;
end
assign clk2M_en = count == 0;
-assign clk4M_en = count == 0 || count == 12;
-assign clk8M_en = count == 0 || count == 6 || count == 12 || count == 18;
+assign clk4M_en = count == 0 || count == 10;
+assign clk8M_en = count == 0 || count == 5 || count == 10 || count == 15;
endmodule
diff --git a/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1_VIDEO.v b/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1_VIDEO.v
index e8f98655..51f0ea74 100644
--- a/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1_VIDEO.v
+++ b/Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1_VIDEO.v
@@ -302,16 +302,12 @@ VRAM vram1(
// CPU Read Data Selector
-dataselector6 videodsel(
- cpu_dr,
- cpu_cs_palram, cpu_rd_palram,
- cpu_cs_vram0, cpu_rd_vram0,
- cpu_cs_vram1, cpu_rd_vram1,
- cpu_cs_spram, cpu_rd_spram,
- cpu_cs_sprcoll, cpu_rd_sprcoll,
- cpu_cs_mixcoll, cpu_rd_mixcoll,
- 8'hFF
-);
+assign cpu_dr = cpu_cs_palram ? cpu_rd_palram :
+ cpu_cs_vram0 ? cpu_rd_vram0 :
+ cpu_cs_vram1 ? cpu_rd_vram1 :
+ cpu_cs_spram ? cpu_rd_spram :
+ cpu_cs_sprcoll ? cpu_rd_sprcoll :
+ cpu_cs_mixcoll ? cpu_rd_mixcoll : 8'hFF;
endmodule
@@ -454,11 +450,7 @@ always @( posedge CLK ) begin
end
end
-dataselector1_32 pixsft(
- BGPIX,
- ( HP[2:0] != 0 ),{ BGPN, BGCD[22:0], 1'b0 },
- { BG_COL/*VRAMDT[12:5]*/, TILEDT }
-);
+assign BGPIX = ( HP[2:0] != 0 ) ? { BGPN, BGCD[22:0], 1'b0 } : { BG_COL/*VRAMDT[12:5]*/, TILEDT };
assign OPIX = { BGPN, BGCD[7], BGCD[15], BGCD[23] };
@@ -503,12 +495,10 @@ assign mixcoll = ~(cltval[2]);
assign mixcoll_ad = { cltval[3], SPRPX[8:4] };
wire [10:0] palno_i;
-dataselector2_11 colsel(
- palno_i,
- cltval[1], ( 11'h400 | BG0PX[8:0] ),
- cltval[0], ( 11'h200 | BG1PX[8:0] ),
- ( 11'h000 | SPRPX[8:0] )
-);
+
+assign palno_i = cltval[1] ? ( 11'h400 | BG0PX[8:0] ) :
+ cltval[0] ? ( 11'h200 | BG1PX[8:0] ) :
+ ( 11'h000 | SPRPX[8:0] );
wire [10:0] palno_d = {HPOS[7],VPOS[7:2],HPOS[6:3]};
diff --git a/Arcade_MiST/Sega System 1 Hardware/rtl/Segasys1_MiST.sv b/Arcade_MiST/Sega System 1 Hardware/rtl/Segasys1_MiST.sv
index 9c1b3bd3..51985ae8 100644
--- a/Arcade_MiST/Sega System 1 Hardware/rtl/Segasys1_MiST.sv
+++ b/Arcade_MiST/Sega System 1 Hardware/rtl/Segasys1_MiST.sv
@@ -74,8 +74,8 @@ wire clk_sys, sdram_clk;
wire pll_locked;
pll_mist pll(
.inclk0(CLOCK_27),
- .c0(clk_sys),//48
- .c1(sdram_clk),//96
+ .c0(sdram_clk),//80
+ .c1(clk_sys),//40
.locked(pll_locked)
);
@@ -145,7 +145,7 @@ data_io data_io(
reg port1_req, port2_req;
wire [24:0] tl_ioctl_addr = ioctl_addr - 18'h20000;
-sdram #(96) sdram(
+sdram #(80) sdram(
.*,
.init_n ( pll_locked ),
.clk ( sdram_clk ),
@@ -201,7 +201,7 @@ always @(posedge sdram_clk) begin
end
SEGASYSTEM1 System1_Top(
- .clk48M(clk_sys),
+ .clk40M(clk_sys),
.reset(reset),
.INP0(INP0),
@@ -237,8 +237,8 @@ SEGASYSTEM1 System1_Top(
wire PCLK_EN;
wire [8:0] HPOS,VPOS;
wire [7:0] POUT;
-wire [7:0] HOFFS = 8'd16;
-wire [7:0] VOFFS = 0;
+wire [7:0] HOFFS = 8'd2;
+wire [7:0] VOFFS = 8'd2;
wire hs, vs;
wire [2:0] g, r;
wire [1:0] b;
diff --git a/Arcade_MiST/Sega System 1 Hardware/rtl/parts.v b/Arcade_MiST/Sega System 1 Hardware/rtl/parts.v
index 0f483d18..a420f669 100644
--- a/Arcade_MiST/Sega System 1 Hardware/rtl/parts.v
+++ b/Arcade_MiST/Sega System 1 Hardware/rtl/parts.v
@@ -233,117 +233,3 @@ DPRAM1024_11B core (
endmodule
-//----------------------------------
-// Data Selector (32bits)
-//----------------------------------
-module dataselector1_32(
-
- output [31:0] oDATA,
-
- input iSEL0,
- input [31:0] iDATA0,
-
- input [31:0] dData
-);
-
-assign oDATA = iSEL0 ? iDATA0 :
- dData;
-
-endmodule
-
-
-//----------------------------------
-// Data Selector 3 to 1
-//----------------------------------
-module dataselector3(
-
- output [7:0] oDATA,
-
- input iSEL0, input [7:0] iDATA0,
- input iSEL1, input [7:0] iDATA1,
- input iSEL2, input [7:0] iDATA2,
-
- input [7:0] dData
-);
-
-assign oDATA = iSEL0 ? iDATA0 :
- iSEL1 ? iDATA1 :
- iSEL2 ? iDATA2 :
- dData;
-
-endmodule
-
-
-//----------------------------------
-// Data Selector 2 to 1 (11bits)
-//----------------------------------
-module dataselector2_11(
-
- output [10:0] oDATA,
-
- input iSEL0, input [10:0] iDATA0,
- input iSEL1, input [10:0] iDATA1,
-
- input [10:0] dData
-);
-
-assign oDATA = iSEL0 ? iDATA0 :
- iSEL1 ? iDATA1 :
- dData;
-
-endmodule
-
-
-//----------------------------------
-// Data Selector 5 to 1
-//----------------------------------
-module dataselector5(
-
- output [7:0] oDATA,
-
- input iSEL0, input [7:0] iDATA0,
- input iSEL1, input [7:0] iDATA1,
- input iSEL2, input [7:0] iDATA2,
- input iSEL3, input [7:0] iDATA3,
- input iSEL4, input [7:0] iDATA4,
-
- input [7:0] dData
-);
-
-assign oDATA = iSEL0 ? iDATA0 :
- iSEL1 ? iDATA1 :
- iSEL2 ? iDATA2 :
- iSEL3 ? iDATA3 :
- iSEL4 ? iDATA4 :
- dData;
-
-endmodule
-
-
-//----------------------------------
-// Data Selector 6 to 1
-//----------------------------------
-module dataselector6(
-
- output [7:0] oDATA,
-
- input iSEL0, input [7:0] iDATA0,
- input iSEL1, input [7:0] iDATA1,
- input iSEL2, input [7:0] iDATA2,
- input iSEL3, input [7:0] iDATA3,
- input iSEL4, input [7:0] iDATA4,
- input iSEL5, input [7:0] iDATA5,
-
- input [7:0] dData
-);
-
-assign oDATA = iSEL0 ? iDATA0 :
- iSEL1 ? iDATA1 :
- iSEL2 ? iDATA2 :
- iSEL3 ? iDATA3 :
- iSEL4 ? iDATA4 :
- iSEL5 ? iDATA5 :
- dData;
-
-endmodule
-
diff --git a/Arcade_MiST/Sega System 1 Hardware/rtl/pll_mist.v b/Arcade_MiST/Sega System 1 Hardware/rtl/pll_mist.v
index 82b6f255..9c60a3a3 100644
--- a/Arcade_MiST/Sega System 1 Hardware/rtl/pll_mist.v
+++ b/Arcade_MiST/Sega System 1 Hardware/rtl/pll_mist.v
@@ -14,7 +14,7 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
-// 13.1.4 Build 182 03/12/2014 SJ Full Version
+// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
// ************************************************************
@@ -98,13 +98,13 @@ module pll_mist (
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
- altpll_component.clk0_divide_by = 9,
+ altpll_component.clk0_divide_by = 27,
altpll_component.clk0_duty_cycle = 50,
- altpll_component.clk0_multiply_by = 16,
+ altpll_component.clk0_multiply_by = 80,
altpll_component.clk0_phase_shift = "0",
- altpll_component.clk1_divide_by = 9,
+ altpll_component.clk1_divide_by = 27,
altpll_component.clk1_duty_cycle = 50,
- altpll_component.clk1_multiply_by = 32,
+ altpll_component.clk1_multiply_by = 40,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
@@ -183,8 +183,8 @@ endmodule
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "96.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "80.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -212,10 +212,10 @@ endmodule
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "32"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "96.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "80.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -259,13 +259,13 @@ endmodule
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "80"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "32"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"