diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/README.txt b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/README.txt index 29720a5d..df6c2b18 100644 --- a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/README.txt +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/README.txt @@ -1,15 +1,9 @@ --- Zaxxon port to MiST +-- Zaxxon (Super Zaxxon, Future Spy) port to MiST -- -- Usage: --- Create ZAXXON.ROM from MAME ROM zaxxon.zip file using the mra utility and the Zaxxon.mra file. +-- Create .ROM and ARC files from MAME ROM zip files using the mra utility and the meta/mra files. -- Example: mra -A -z /path/to/mame/roms Zaxxon.mra --- Create the sound ROM file from MAME WAVE ROM zaxxon.zip (rename it to zaxxon_sample.zip) file --- using the mra utility and the Zaxxon_sound.mra file. --- Example: mra -A -z /path/to/mame/roms Zaxxon_sound.mra --- Concatenate the zaxxon.rom and Zaxxound.rom into ZAXXON.ROM. --- Copy the ZAXXON.ROM file to the root of the SD Card. --- --- Sound is optional, if you created the ROM with the samples, then enable sound in the OSD menu! +-- Copy the resulting ROM and ARC files to the root of the SD Card, next to the Zaxxon.rbf. -- -- MRA utilty: https://github.com/sebdel/mra-tools-c -- diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Zaxxon.qsf b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Zaxxon.qsf index 70ef6688..346dd9ee 100644 --- a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Zaxxon.qsf +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Zaxxon.qsf @@ -41,7 +41,7 @@ # ======================== set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26" set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" # Pin & Location Assignments @@ -222,6 +222,10 @@ set_global_assignment -name VERILOG_FILE rtl/pll_mist.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv set_global_assignment -name VHDL_FILE rtl/dpram.vhd set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/dec_315_5013.vhd +set_global_assignment -name VHDL_FILE rtl/dec_315_5061.vhd +set_global_assignment -name VERILOG_FILE rtl/Sega_Crypt.v set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip +set_global_assignment -name SIGNALTAP_FILE output_files/zaxx.stp set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/Future Spy.mra b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/Future Spy.mra new file mode 100644 index 00000000..a1547d8f --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/Future Spy.mra @@ -0,0 +1,67 @@ + + Future Spy + 0193 + 202003290000 + 1984 + Sega/Gremlin + Isometric Shoot'em up + Space + futspy + zaxxon + + + + + + + + + + 22 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/FutureSpy.mra b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/FutureSpy.mra deleted file mode 100644 index 8d34a078..00000000 --- a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/FutureSpy.mra +++ /dev/null @@ -1,34 +0,0 @@ - - Future Spy - 0193 - 202003290000 - 1984 - Sega/Gremlin - Isometric Shoot'em up - Space - futspy - futspy - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/SZaxxon.mra b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/SZaxxon.mra deleted file mode 100644 index 02cf2c9a..00000000 --- a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/SZaxxon.mra +++ /dev/null @@ -1,34 +0,0 @@ - - SZaxxon - 0193 - 202003290000 - 1982 - Sega/Gremlin - Isometric Shoot'em up - Space - szaxxon - szaxxon - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/Super Zaxxon.mra b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/Super Zaxxon.mra new file mode 100644 index 00000000..0b08ac25 --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/Super Zaxxon.mra @@ -0,0 +1,73 @@ + + Super Zaxxon + 0193 + 202003290000 + 1982 + Sega/Gremlin + Isometric Shoot'em up + Space + szaxxon + zaxxon + + + + + + + + + 10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/Zaxxon.mra b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/Zaxxon.mra index 0e85b305..a6f4988c 100644 --- a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/Zaxxon.mra +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/Zaxxon.mra @@ -1,34 +1,71 @@ - Zaxxon - 0193 - 202003290000 - 1982 - Sega/Gremlin - Isometric Shoot'em up - Space - zaxxon - zaxxon - - - - - - + Zaxxon + 0193 + 202003290000 + 1982 + Sega/Gremlin + Isometric Shoot'em up + Space + zaxxon + zaxxon - - - - + + + + + + - - - - - - - - - - - - \ No newline at end of file + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/Zaxxon_sound.mra b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/Zaxxon_sound.mra deleted file mode 100644 index c24af3fa..00000000 --- a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/meta/Zaxxon_sound.mra +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/Sega_Crypt.v b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/Sega_Crypt.v new file mode 100644 index 00000000..04dccf1a --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/Sega_Crypt.v @@ -0,0 +1,56 @@ +module Sega_Crypt +( + input clk, + input [3:0] enc_type, + + input mrom_m1, + input [14:0] mrom_ad, + output reg [7:0] mrom_dt, + output [14:0] cpu_rom_addr, + input [7:0] cpu_rom_do +); + +reg [15:0] madr; +wire [7:0] mdat; + +wire f = mdat[7]; +wire [7:0] xorv = { f, 1'b0, f, 1'b0, f, 3'b000 }; +wire [7:0] andv = ~(8'hA8); +wire [1:0] decidx0 = { mdat[5], mdat[3] } ^ { f, f }; +wire [6:0] decidx = { madr[12], madr[8], madr[4], madr[0], ~madr[15], decidx0 }; +reg [7:0] dectbl; +wire [7:0] mdec = ( mdat & andv ) | ( dectbl ^ xorv ); + +wire [7:0] dectbl_5013; +dec_315_5013 dec_315_5013( + .clk(clk), + .addr(decidx), + .data(dectbl_5013) +); + +wire [7:0] dectbl_5061; +dec_315_5061 dec_315_5061( + .clk(clk), + .addr(decidx), + .data(dectbl_5061) +); + +always @(*) begin + case (enc_type) + 4'h1: dectbl = dectbl_5013; + 4'h2: dectbl = dectbl_5061; + default: dectbl = 0; + endcase +end + +assign cpu_rom_addr = madr[14:0]; +assign mdat = cpu_rom_do; + +reg phase = 1'b0; +always @( negedge clk ) begin + if ( phase ) mrom_dt <= mdec; + else madr <= { mrom_m1, mrom_ad }; + phase <= ~phase; +end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/Zaxxon_MiST.sv b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/Zaxxon_MiST.sv index 3c584ec3..43155369 100644 --- a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/Zaxxon_MiST.sv +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/Zaxxon_MiST.sv @@ -32,15 +32,13 @@ module Zaxxon_MiST( `include "rtl/build_id.v" localparam CONF_STR = { - "ZAXXON;ROM;", + "ZAXXON;;", "O2,Rotate Controls,Off,On;", "O34,Scanlines,Off,25%,50%,75%;", "O5,Blend,Off,On;", "O6,Flip,Off,On;", "O7,Service,Off,On;", - "O8,Sound,Off,On;", - "O9A,Lives,3,5,4,Free ships;", - "OBC,Extra ship,40k,20k,30k,10k;", + "DIP;", "T0,Reset;", "V,v2.0.",`BUILD_DATE }; @@ -50,11 +48,28 @@ wire [1:0] scanlines = status[4:3]; wire blend = status[5]; wire flip = status[6]; wire service = status[7]; -wire sound = status[8]; -wire [1:0] ships = ~status[10:9]; -wire [1:0] extraship = status[12:11]; -wire [7:0] sw1 = {1'b0, sound, ships, 2'b11, extraship }; // cocktail(1) / sound(1) / ships(2) / N.U.(2) / extra ship (2) +wire [7:0] sw1 = status[23:16]; +wire [7:0] sw2 = status[31:24]; + +reg [7:0] p1_input, p2_input; + +always @(*) begin + case (core_mod) + 7'h22: // FUTSPY + begin + p1_input = {2'b00, m_fireB, m_fireA, m_down, m_up, m_left, m_right}; + p2_input = {2'b00, m_fire2B, m_fire2A, m_down2, m_up2, m_left2, m_right2}; + end + + default: // ZAXXON, SZAXXON + begin + p1_input = {3'b000, m_fireA, m_down, m_up, m_left, m_right}; + p2_input = {3'b000, m_fire2A, m_down2, m_up2, m_left2, m_right2}; + end + endcase + +end assign LED = ~ioctl_downl; assign SDRAM_CLK = clk_sd; @@ -65,7 +80,7 @@ wire clk_sys, clk_sd; wire pll_locked; pll_mist pll( .inclk0(CLOCK_27), - .c0(clk_sd),//36 + .c0(clk_sd),//48 .c1(clk_sys),//24 .locked(pll_locked) ); @@ -81,6 +96,7 @@ wire [7:0] key_code; wire scandoublerD; wire ypbpr; wire no_csync; +wire [6:0] core_mod; user_io #( .STRLEN(($size(CONF_STR)>>3))) @@ -101,7 +117,8 @@ user_io( .key_code (key_code ), .joystick_0 (joystick_0 ), .joystick_1 (joystick_1 ), - .status (status ) + .status (status ), + .core_mod (core_mod ) ); wire [15:0] audio_l; @@ -111,8 +128,10 @@ wire [2:0] g, r; wire [1:0] b; wire [14:0] rom_addr; wire [15:0] rom_do; -wire [13:0] gfx_addr; -wire [15:0] gfx_do; +wire [12:0] bg_addr; +wire [31:0] bg_do; +wire [13:0] sp_addr; +wire [31:0] sp_do; wire [19:0] wave_addr; wire [15:0] wave_do; wire ioctl_downl; @@ -122,14 +141,14 @@ wire [24:0] ioctl_addr; wire [7:0] ioctl_dout; // ROM structure -// 00000-06FFF CPU ROM 28k u27-u28-u29-u29-u29 +// 00000-06FFF CPU ROM 28k u27-u28-u29-(u29-u29) // 07000-0EFFF Tiledata 32k u91-u90-u93-u92 // 0F000-0F7FF char1 2k u68 // 0F800-0FFFF char2 2k u69 -// 10000-05FFF bg 24k u113-u112-u111 -// 16000-1BFFF spr 24k u77-u78-u79 -// 1C000-1C0FF 256b u76 -// 1C100-1C1FF 256b u72 +// 10000-17FFF bg 32k u113-u112-u111-(u111) +// 18000-27FFF spr 64k u77-u78-u79-(u79) +// 28000-280FF 256b u76 +// 28100-281FF 256b u72 data_io data_io( .clk_sys ( clk_sys ), @@ -143,10 +162,10 @@ data_io data_io( .ioctl_dout ( ioctl_dout ) ); -wire [24:0] gfx_ioctl_addr = ioctl_addr - 16'h7000; +wire [24:0] gfx_ioctl_addr = ioctl_addr - 17'h10000; reg port1_req, port2_req; -sdram #(36) sdram( +sdram #(48) sdram( .*, .init_n ( pll_locked ), .clk ( clk_sd ), @@ -160,22 +179,24 @@ sdram #(36) sdram( .port1_d ( {ioctl_dout, ioctl_dout} ), .port1_q ( ), - .cpu1_addr ( ioctl_downl ? 16'hffff : {2'b00, rom_addr[14:1]}), + .cpu1_addr ( ioctl_downl ? 19'h7ffff : {5'd0, rom_addr[14:1]}), .cpu1_q ( rom_do ), - .snd_addr ( wave_addr[19:1] + 16'he100 ), - .snd_q ( wave_do ), + .cpu2_addr ( wave_addr[19:1] + 17'h13100 ), + .cpu2_q ( wave_do ), // port2 for gfx .port2_req ( port2_req ), .port2_ack ( ), - .port2_a ( {gfx_ioctl_addr[23:15], gfx_ioctl_addr[13:0]} ), - .port2_ds ( {gfx_ioctl_addr[14], ~gfx_ioctl_addr[14]} ), + .port2_a ( gfx_ioctl_addr[23:1] ), + .port2_ds ( {gfx_ioctl_addr[0], ~gfx_ioctl_addr[0]} ), .port2_we ( ioctl_downl ), .port2_d ( {ioctl_dout, ioctl_dout} ), .port2_q ( ), - .gfx_addr ( gfx_addr ), - .gfx_q ( gfx_do ) + .bg_addr ( bg_addr ), + .bg_q ( bg_do ), + .sp_addr ( sp_addr + 16'h2000), + .sp_q ( sp_do ) ); always @(posedge clk_sys) begin @@ -200,7 +221,7 @@ always @(posedge clk_sd) begin reset <= status[0] | buttons[1] | ~rom_loaded; end -wire dl_wr = ioctl_wr && ioctl_addr < 17'h1c200; +wire dl_wr = ioctl_wr && ioctl_addr < 18'h28200; zaxxon zaxxon( .clock_24(clk_sys), @@ -216,15 +237,13 @@ zaxxon zaxxon( .audio_out_l(audio_l), + .hwsel(core_mod[1]), .coin1(m_coin1), .coin2(m_coin2), .start2(m_two_players), .start1(m_one_player), - .left(m_left), - .right(m_right), - .up(m_up), - .down(m_down), - .fire(m_fireA), + .p1_input(p1_input), + .p2_input(p2_input), .service(service), .sw1_input(sw1), // cocktail(1) / sound(1) / ships(2) / N.U.(2) / extra ship (2) @@ -232,14 +251,18 @@ zaxxon zaxxon( .flip_screen(flip), + .enc_type ( core_mod[6:4]) , .cpu_rom_addr ( rom_addr ), .cpu_rom_do ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ), - .map_addr ( gfx_addr ), - .map_do ( gfx_do ), .wave_addr ( wave_addr ), .wave_data ( wave_do ), - .dl_addr ( ioctl_addr[16:0] ), + .bg_graphics_addr( bg_addr ), + .bg_graphics_do ( bg_do ), + .sp_graphics_addr( sp_addr ), + .sp_graphics_do ( sp_do ), + + .dl_addr ( ioctl_addr[17:0] ), .dl_data ( ioctl_dout ), .dl_wr ( dl_wr ) ); diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/dec_315_5013.vhd b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/dec_315_5013.vhd new file mode 100644 index 00000000..1005daba --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/dec_315_5013.vhd @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity dec_315_5013 is +port ( + clk : in std_logic; + addr : in std_logic_vector(6 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of dec_315_5013 is + type rom is array(0 to 127) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"88",X"A8",X"80",X"A0",X"28",X"20",X"A8",X"A0",X"08",X"28",X"88",X"A8",X"88",X"80",X"08",X"00", + X"A8",X"28",X"A0",X"20",X"20",X"A0",X"00",X"80",X"88",X"A8",X"80",X"A0",X"28",X"20",X"A8",X"A0", + X"08",X"28",X"88",X"A8",X"88",X"80",X"08",X"00",X"88",X"A8",X"80",X"A0",X"28",X"20",X"A8",X"A0", + X"A8",X"28",X"A0",X"20",X"20",X"A0",X"00",X"80",X"08",X"28",X"88",X"A8",X"88",X"80",X"08",X"00", + X"08",X"28",X"88",X"A8",X"88",X"80",X"08",X"00",X"88",X"A8",X"80",X"A0",X"28",X"20",X"A8",X"A0", + X"88",X"A8",X"80",X"A0",X"28",X"20",X"A8",X"A0",X"A8",X"28",X"A0",X"20",X"20",X"A0",X"00",X"80", + X"A8",X"28",X"A0",X"20",X"20",X"A0",X"00",X"80",X"A8",X"28",X"A0",X"20",X"20",X"A0",X"00",X"80", + X"08",X"28",X"88",X"A8",X"88",X"80",X"08",X"00",X"88",X"A8",X"80",X"A0",X"28",X"20",X"A8",X"A0"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/dec_315_5061.vhd b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/dec_315_5061.vhd new file mode 100644 index 00000000..6faf433f --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/dec_315_5061.vhd @@ -0,0 +1,39 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity dec_315_5061 is +port ( + clk : in std_logic; + addr : in std_logic_vector(6 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of dec_315_5061 is + type rom is array(0 to 127) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + x"28",x"08",x"20",x"00", x"28",x"08",x"20",x"00", + x"80",x"00",x"a0",x"20", x"08",x"88",x"00",x"80", + x"80",x"00",x"a0",x"20", x"08",x"88",x"00",x"80", + x"a0",x"80",x"20",x"00", x"20",x"28",x"a0",x"a8", + x"28",x"08",x"20",x"00", x"88",x"80",x"a8",x"a0", + x"80",x"00",x"a0",x"20", x"08",x"88",x"00",x"80", + x"80",x"00",x"a0",x"20", x"20",x"28",x"a0",x"a8", + x"20",x"28",x"a0",x"a8", x"08",x"88",x"00",x"80", + x"88",x"80",x"a8",x"a0", x"28",x"08",x"20",x"00", + x"80",x"00",x"a0",x"20", x"a0",x"80",x"20",x"00", + x"20",x"28",x"a0",x"a8", x"08",x"88",x"00",x"80", + x"80",x"00",x"a0",x"20", x"20",x"28",x"a0",x"a8", + x"88",x"80",x"a8",x"a0", x"88",x"80",x"a8",x"a0", + x"80",x"00",x"a0",x"20", x"08",x"88",x"00",x"80", + x"80",x"00",x"a0",x"20", x"28",x"08",x"20",x"00", + x"20",x"28",x"a0",x"a8", x"a0",x"80",x"20",x"00"); + +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/pll_mist.qip b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/pll_mist.qip new file mode 100644 index 00000000..6182871f --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/pll_mist.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_mist.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"] diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/pll_mist.v b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/pll_mist.v index 851e7663..f54914f7 100644 --- a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/pll_mist.v +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/pll_mist.v @@ -98,9 +98,9 @@ module pll_mist ( .vcounderrange ()); defparam altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 3, + altpll_component.clk0_divide_by = 9, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 4, + altpll_component.clk0_multiply_by = 16, altpll_component.clk0_phase_shift = "0", altpll_component.clk1_divide_by = 9, altpll_component.clk1_duty_cycle = 50, @@ -183,7 +183,7 @@ endmodule // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" @@ -212,7 +212,7 @@ endmodule // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" @@ -259,9 +259,9 @@ endmodule // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/sdram.sv b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/sdram.sv index 728abae6..e561f665 100644 --- a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/sdram.sv +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/sdram.sv @@ -44,12 +44,12 @@ module sdram ( input [23:1] port1_a, input [1:0] port1_ds, input [15:0] port1_d, - output [15:0] port1_q, + output reg [15:0] port1_q, - input [15:1] cpu1_addr, + input [19:1] cpu1_addr, output reg [15:0] cpu1_q, - input [19:1] snd_addr, - output reg [15:0] snd_q, + input [19:1] cpu2_addr, + output reg [15:0] cpu2_q, input port2_req, output reg port2_ack, @@ -57,16 +57,18 @@ module sdram ( input [23:1] port2_a, input [1:0] port2_ds, input [15:0] port2_d, - output [15:0] port2_q, + output reg [31:0] port2_q, - input [15:1] gfx_addr, - output reg [15:0] gfx_q + input [14:2] bg_addr, + output reg [31:0] bg_q, + input [17:2] sp_addr, + output reg [31:0] sp_q ); parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz -localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 +localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8 localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved localparam CAS_LATENCY = 3'd2; // 2/3 allowed localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed @@ -85,21 +87,25 @@ localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10; SDRAM state machine for 2 bank interleaved access 1 word burst, CL2 cmd issued registered - 0 RAS0 cas1 - 1 ras0 - 2 CAS0 data1 returned - 3 RAS1 cas0 - 4 ras1 - 5 CAS1 data0 returned + 0 RAS0 + 1 ras0 - data1 returned + 2 data1 returned + 3 CAS0 + 4 RAS1 cas0 + 5 ras1 + 6 CAS1 data0 returned + 7 cas1 - data0 read masked by DQM */ localparam STATE_RAS0 = 3'd0; // first state in cycle -localparam STATE_RAS1 = 3'd3; // Second ACTIVE command after RAS0 + tRRD (15ns) -localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 3 -localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 5 -localparam STATE_READ0 = 3'd0; //STATE_CAS0 + CAS_LATENCY + 1'd1; // 7 -localparam STATE_READ1 = 3'd3; -localparam STATE_LAST = 3'd5; +localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns) +localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3 +localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6 +localparam STATE_READ0 = STATE_CAS0 + CAS_LATENCY + 2'd2; // 7 +localparam STATE_READ1 = 3'd2; +localparam STATE_DS1b = 3'd7; +localparam STATE_READ1b = 3'd3; +localparam STATE_LAST = 3'd7; reg [2:0] t; @@ -142,7 +148,8 @@ localparam CMD_AUTO_REFRESH = 4'b0001; localparam CMD_LOAD_MODE = 4'b0000; reg [3:0] sd_cmd; // current command sent to sd ram -reg [15:0] sd_din; +reg [15:0] sd_din; // Fast Input register latching incoming SDRAM data + // drive control signals according to current command assign SDRAM_nCS = sd_cmd[3]; assign SDRAM_nRAS = sd_cmd[2]; @@ -152,7 +159,7 @@ assign SDRAM_nWE = sd_cmd[0]; reg [24:1] addr_latch[2]; reg [24:1] addr_latch_next[2]; reg [19:1] addr_last[2]; -reg [15:1] addr_last2[2]; +reg [17:2] addr_last2[2]; reg [15:0] din_latch[2]; reg [1:0] oe_latch; reg [1:0] we_latch; @@ -163,46 +170,49 @@ reg port2_state; localparam PORT_NONE = 2'd0; localparam PORT_CPU1 = 2'd1; -localparam PORT_SND = 2'd2; +localparam PORT_CPU2 = 2'd2; +localparam PORT_BG = 2'd1; +localparam PORT_SP = 2'd2; localparam PORT_REQ = 2'd3; -localparam PORT_GFX = 2'd1; - -reg [2:0] next_port[2]; -reg [2:0] port[2]; +reg [1:0] next_port[2]; +reg [1:0] port[2]; reg refresh; -reg [10:0] refresh_cnt; -wire need_refresh = (refresh_cnt >= RFRSH_CYCLES); +reg [11:0] refresh_cnt; +reg need_refresh; // PORT1: bank 0,1 always @(*) begin if (refresh) begin next_port[0] = PORT_NONE; - addr_latch_next[0] = addr_latch[0]; + addr_latch_next[0] = addr_latch[1]; end else if (port1_req ^ port1_state) begin next_port[0] = PORT_REQ; addr_latch_next[0] = { 1'b0, port1_a }; end else if (cpu1_addr != addr_last[PORT_CPU1]) begin next_port[0] = PORT_CPU1; - addr_latch_next[0] = { 9'd0, cpu1_addr }; - end else if (snd_addr != addr_last[PORT_SND]) begin - next_port[0] = PORT_SND; - addr_latch_next[0] = { 5'd0, snd_addr }; + addr_latch_next[0] = { 5'd0, cpu1_addr }; + end else if (cpu2_addr != addr_last[PORT_CPU2]) begin + next_port[0] = PORT_CPU2; + addr_latch_next[0] = { 5'd0, cpu2_addr }; end else begin next_port[0] = PORT_NONE; addr_latch_next[0] = addr_latch[0]; end end -// PORT2: bank 2,3 +// PORT1: bank 2,3 always @(*) begin if (port2_req ^ port2_state) begin next_port[1] = PORT_REQ; addr_latch_next[1] = { 1'b1, port2_a }; - end else if (gfx_addr != addr_last2[PORT_GFX]) begin - next_port[1] = PORT_GFX; - addr_latch_next[1] = { 1'b1, 8'd0, gfx_addr }; + end else if (sp_addr != addr_last2[PORT_SP]) begin + next_port[1] = PORT_SP; + addr_latch_next[1] = { 1'b1, 6'd0, sp_addr, 1'b0 }; + end else if (bg_addr != addr_last2[PORT_BG]) begin + next_port[1] = PORT_BG; + addr_latch_next[1] = { 1'b1, 9'd0, bg_addr, 1'b0 }; end else begin next_port[1] = PORT_NONE; addr_latch_next[1] = addr_latch[1]; @@ -217,6 +227,7 @@ always @(posedge clk) begin { SDRAM_DQMH, SDRAM_DQML } <= 2'b11; sd_cmd <= CMD_NOP; // default: idle refresh_cnt <= refresh_cnt + 1'd1; + need_refresh <= (refresh_cnt >= RFRSH_CYCLES); if(init) begin // initialization takes place at the end of the reset phase @@ -264,7 +275,7 @@ always @(posedge clk) begin // bank 2,3 if(t == STATE_RAS1) begin - refresh <= 1'b0; + refresh <= 0; addr_latch[1] <= addr_latch_next[1]; { oe_latch[1], we_latch[1] } <= 2'b00; port[1] <= next_port[1]; @@ -273,9 +284,9 @@ always @(posedge clk) begin sd_cmd <= CMD_ACTIVE; SDRAM_A <= addr_latch_next[1][22:10]; SDRAM_BA <= addr_latch_next[1][24:23]; - addr_last2[next_port[1]] <= addr_latch_next[1][15:1]; + addr_last2[next_port[1]] <= addr_latch_next[1][16:2]; if (next_port[1] == PORT_REQ) begin - { oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we }; + { oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we }; ds[1] <= port2_ds; din_latch[1] <= port2_d; port2_state <= port2_req; @@ -283,10 +294,8 @@ always @(posedge clk) begin { oe_latch[1], we_latch[1] } <= 2'b10; ds[1] <= 2'b11; end - end - - if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin - refresh <= 1'b1; + end else if (need_refresh && !oe_latch[0] & !we_latch[0]) begin + refresh <= 1; refresh_cnt <= 0; sd_cmd <= CMD_AUTO_REFRESH; end @@ -320,14 +329,28 @@ always @(posedge clk) begin case(port[0]) PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end PORT_CPU1: begin cpu1_q <= sd_din; end - PORT_SND: begin snd_q <= sd_din; end + PORT_CPU2: begin cpu2_q <= sd_din; end default: ; endcase; end + if(t == STATE_READ1 && oe_latch[1]) begin case(port[1]) - PORT_REQ: begin port2_q <= sd_din; port2_ack <= port2_req; end - PORT_GFX: begin gfx_q <= sd_din; end + PORT_REQ: port2_q[15:0] <= sd_din; + PORT_SP : sp_q[15:0] <= sd_din; + PORT_BG : bg_q[15:0] <= sd_din; + default: ; + endcase; + end + + //set DQM two cycles before the 2nd word in the burst + if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1]; + + if(t == STATE_READ1b && oe_latch[1]) begin + case(port[1]) + PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end + PORT_SP : begin sp_q[31:16] <= sd_din; end + PORT_BG : begin bg_q[31:16] <= sd_din; end default: ; endcase; end diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/zaxxon.vhd b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/zaxxon.vhd index 57a680bb..3e08208e 100644 --- a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/zaxxon.vhd +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/zaxxon.vhd @@ -128,23 +128,16 @@ port( audio_out_l : out std_logic_vector(15 downto 0); audio_out_r : out std_logic_vector(15 downto 0); - + + hwsel : in std_logic_vector(1 downto 0); --00 - zaxxon, 01 - futspy + coin1 : in std_logic; coin2 : in std_logic; start1 : in std_logic; start2 : in std_logic; - - left : in std_logic; - right : in std_logic; - up : in std_logic; - down : in std_logic; - fire : in std_logic; - - left_c : in std_logic; - right_c : in std_logic; - up_c : in std_logic; - down_c : in std_logic; - fire_c : in std_logic; + + p1_input : in std_logic_vector(7 downto 0); + p2_input : in std_logic_vector(7 downto 0); sw1_input : in std_logic_vector( 7 downto 0); sw2_input : in std_logic_vector( 7 downto 0); @@ -152,12 +145,15 @@ port( service : in std_logic; flip_screen : in std_logic; + enc_type : in std_logic_vector(3 downto 0); cpu_rom_addr : out std_logic_vector(14 downto 0); cpu_rom_do : in std_logic_vector(7 downto 0); - map_addr : out std_logic_vector(13 downto 0); - map_do : in std_logic_vector(15 downto 0); + bg_graphics_addr : out std_logic_vector(12 downto 0); + bg_graphics_do : in std_logic_vector(31 downto 0); + sp_graphics_addr : out std_logic_vector(13 downto 0); + sp_graphics_do : in std_logic_vector(31 downto 0); - dl_addr : in std_logic_vector(16 downto 0); + dl_addr : in std_logic_vector(17 downto 0); dl_data : in std_logic_vector(7 downto 0); dl_wr : in std_logic; @@ -228,11 +224,11 @@ architecture struct of zaxxon is signal map_offset_l1 : std_logic_vector( 7 downto 0); signal map_offset_l2 : std_logic_vector( 7 downto 0); --- signal map_addr : std_logic_vector(13 downto 0); + signal map_addr : std_logic_vector(13 downto 0); signal map1_do : std_logic_vector( 7 downto 0); signal map2_do : std_logic_vector( 7 downto 0); - signal bg_graphics_addr : std_logic_vector(12 downto 0); +-- signal bg_graphics_addr : std_logic_vector(12 downto 0); signal bg_graphics1_do : std_logic_vector( 7 downto 0); signal bg_graphics2_do : std_logic_vector( 7 downto 0); signal bg_graphics3_do : std_logic_vector( 7 downto 0); @@ -240,7 +236,6 @@ architecture struct of zaxxon is signal bg_color_a : std_logic_vector(3 downto 0); signal bg_color : std_logic_vector(3 downto 0); signal bg_vid : std_logic_vector(2 downto 0); - signal bg_code_line : std_logic_vector(9 downto 0); signal sp_ram_addr : std_logic_vector(7 downto 0); signal sp_ram_we : std_logic; @@ -263,17 +258,20 @@ architecture struct of zaxxon is signal sp_color : std_logic_vector(4 downto 0); signal sp_color_r : std_logic_vector(4 downto 0); - signal sp_code_line : std_logic_vector(12 downto 0); + signal sp_code_line : std_logic_vector(13 downto 0); signal sp_hflip : std_logic; + signal sp_hflip_r : std_logic; signal sp_vflip : std_logic; - signal sp_graphics_addr : std_logic_vector(12 downto 0); +-- signal sp_graphics_addr : std_logic_vector(12 downto 0); signal sp_graphics1_do : std_logic_vector( 7 downto 0); signal sp_graphics2_do : std_logic_vector( 7 downto 0); signal sp_graphics3_do : std_logic_vector( 7 downto 0); signal sp_ok : std_logic; + signal sp_ok_r : std_logic; signal sp_bit_hpos : std_logic_vector(7 downto 0); + signal sp_bit_hpos_r : std_logic_vector(7 downto 0); signal sp_bit_nb : integer range 0 to 7; signal sp_buffer_ram_addr : std_logic_vector(7 downto 0); @@ -293,13 +291,14 @@ architecture struct of zaxxon is signal bg_color_ref : std_logic := '0'; signal bg_enable : std_logic := '0'; - signal p1_input : std_logic_vector(7 downto 0); - signal p2_input : std_logic_vector(7 downto 0); signal gen_input : std_logic_vector(7 downto 0); signal coin1_r, coin1_mem, coin1_ena : std_logic := '0'; signal coin2_r, coin2_mem, coin2_ena : std_logic := '0'; + signal map1_we : std_logic; + signal map2_we : std_logic; + signal map_dl_addr : std_logic_vector(17 downto 0); signal bg_graphics_1_we : std_logic; signal bg_graphics_2_we : std_logic; signal bg_graphics_bits_1_we : std_logic; @@ -314,6 +313,22 @@ architecture struct of zaxxon is signal port_a, port_a_r : std_logic_vector(7 downto 0); -- i8255 ports signal port_b, port_b_r : std_logic_vector(7 downto 0); signal port_c, port_c_r : std_logic_vector(7 downto 0); + + signal cpu_rom_dec : std_logic_vector(7 downto 0); + signal cpu_rom_addr_enc : std_logic_vector(14 downto 0); + +COMPONENT Sega_Crypt + PORT + ( + clk : IN STD_LOGIC; + enc_type : IN STD_LOGIC_VECTOR(3 downto 0); + mrom_m1 : IN STD_LOGIC; + mrom_ad : IN STD_LOGIC_VECTOR(14 DOWNTO 0); + mrom_dt : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + cpu_rom_addr : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); + cpu_rom_do : IN STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; begin @@ -465,17 +480,17 @@ begin end if; end process; ---------------------------------- --- players/dip switches inputs -- ---------------------------------- -p1_input <= "000" & fire & down & up & left & right ; -p2_input <= "000" & fire_c & down_c & up_c & left_c & right_c; -gen_input <= service & coin2_mem & coin1_mem & '0' & start2 & start1 & "00"; +----------------------------------------- +-- coin registers/start buttons inputs -- +----------------------------------------- +gen_input <= service & '0' & coin1_mem & '0' & start2 & start1 & "00"; ------------------------------------------ -- cpu data input with address decoding -- ------------------------------------------ -cpu_di <= cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"6" else -- 0000-5FFF +cpu_di <= + cpu_rom_dec when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"6" and enc_type /= x"0" else -- 0000-5FFF + cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"6" and enc_type = x"0" else -- 0000-5FFF wram_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = x"6" else -- 6000-6FFF ch_ram_do_to_cpu when cpu_mreq_n = '0' and (cpu_addr and x"E000") = x"8000" else -- video ram 8000-83FF + mirroring 1C00 sp_ram_do_to_cpu when cpu_mreq_n = '0' and (cpu_addr and x"E000") = x"A000" else -- sprite ram A000-A0FF + mirroring 1F00 @@ -631,19 +646,22 @@ end process; sp_online_vcnt <= sp_online_ram_do(7 downto 0) + ("111" & not(flip) & flip & flip & flip & '1') + vflip_r(7 downto 0) + 1; -sp_code_line <= (sp_code(5 downto 0)) & - (sp_line(4 downto 3) xor (sp_code(7) & sp_code(7))) & - ("00" xor (sp_code(6) & sp_code(6))) & - (sp_line(2 downto 0) xor (sp_code(7) & sp_code(7) & sp_code(7))); - -sp_buffer_ram_addr <= sp_bit_hpos when flip = '1' and hcnt(8) = '1' else not sp_bit_hpos; +sp_code_line <= (sp_code(6) and hwsel(0)) & + (sp_code(5 downto 0)) & + (sp_line(4 downto 3) xor (sp_code(7) & sp_code(7))) & + ("00" xor (sp_hflip & sp_hflip)) & + (sp_line(2 downto 0) xor (sp_code(7) & sp_code(7) & sp_code(7))); + +sp_buffer_ram_addr <= sp_bit_hpos_r when flip = '1' and hcnt(8) = '1' else not sp_bit_hpos_r; sp_buffer_ram_di <= x"00" when hcnt(8) = '1' else sp_color_r & sp_graphics3_do(sp_bit_nb) & sp_graphics2_do(sp_bit_nb) & sp_graphics1_do(sp_bit_nb); sp_buffer_ram_we <= pix_ena when hcnt(8) = '1' else - sp_ok and clock_cnt(0) when sp_buffer_ram_do(2 downto 0) = "000" else '0'; + sp_ok_r and clock_cnt(0) when sp_buffer_ram_do(2 downto 0) = "000" else '0'; + +sp_hflip <= sp_code(6) when hwsel = "00" else sp_code(7); process (clock_vid) begin @@ -658,45 +676,59 @@ begin if hcnt(8)='0' then if clock_cnt(0) = '1' then - if sp_hflip = '1' then sp_bit_nb <= sp_bit_nb + 1; end if; - if sp_hflip = '0' then sp_bit_nb <= sp_bit_nb - 1; end if; + if sp_hflip_r = '1' then sp_bit_nb <= sp_bit_nb + 1; end if; + if sp_hflip_r = '0' then sp_bit_nb <= sp_bit_nb - 1; end if; - sp_bit_hpos <= sp_bit_hpos + 1; + sp_bit_hpos_r <= sp_bit_hpos_r + 1; end if; - if pix_ena = '1' then - - if hcnt(3 downto 0) = "0000" then sp_line <= sp_online_vcnt; end if; - if hcnt(3 downto 0) = "0010" then sp_code <= sp_online_ram_do(7 downto 0); end if; - if hcnt(3 downto 0) = "0100" then sp_color <= sp_online_ram_do(4 downto 0); end if; - if hcnt(3 downto 0) = "0110" then sp_bit_hpos <= sp_online_ram_do(7 downto 0) + ("111" & not(flip) & flip & flip & flip & '1') +1; end if; - - if hcnt(3 downto 0) = "0110" then - sp_graphics_addr <= sp_code_line; - sp_ok <= sp_online_ram_do(8); - sp_hflip <= sp_code(6); - sp_vflip <= sp_code(7); - if sp_code(6) = '1' then sp_bit_nb <= 0; else sp_bit_nb <= 7; end if; - sp_color_r <= sp_color; - end if; - if hcnt(3 downto 0) = "1010" then - sp_graphics_addr(4 downto 3) <= "01" xor (sp_hflip & sp_hflip); - end if; - if hcnt(3 downto 0) = "1110" then - sp_graphics_addr(4 downto 3) <= "10" xor (sp_hflip & sp_hflip); - end if; - if hcnt(3 downto 0) = "0010" then - sp_graphics_addr(4 downto 3) <= "11" xor (sp_hflip & sp_hflip); - end if; + if pix_ena = '1' then + + if hcnt(3 downto 0) = "0000" then sp_line <= sp_online_vcnt; end if; + if hcnt(3 downto 0) = "0010" then sp_code <= sp_online_ram_do(7 downto 0); end if; + if hcnt(3 downto 0) = "0100" then sp_color <= sp_online_ram_do(4 downto 0); end if; + if hcnt(3 downto 0) = "0110" then + sp_ok <= sp_online_ram_do(8); + sp_bit_hpos <= sp_online_ram_do(7 downto 0) + ("111" & not(flip) & flip & flip & flip & '1') +1; + end if; + + if hcnt(3 downto 0) = "1000" then + if sp_hflip = '1' then sp_bit_nb <= 0; else sp_bit_nb <= 7; end if; + sp_bit_hpos_r <= sp_bit_hpos; + sp_color_r <= sp_color; + sp_hflip_r <= sp_hflip; + sp_vflip <= sp_code(7); + sp_ok_r <= sp_ok; + end if; + + -- sprite rom address setup + if hcnt(3 downto 0) = "0110" then + sp_graphics_addr <= sp_code_line; + end if; + if hcnt(3 downto 0) = "1010" then + sp_graphics_addr(4 downto 3) <= "01" xor (sp_hflip_r & sp_hflip_r); + end if; + if hcnt(3 downto 0) = "1110" then + sp_graphics_addr(4 downto 3) <= "10" xor (sp_hflip_r & sp_hflip_r); + end if; + if hcnt(3 downto 0) = "0010" then + sp_graphics_addr(4 downto 3) <= "11" xor (sp_hflip_r & sp_hflip_r); + end if; + -- sprite rom data latch + if hcnt(3 downto 0) = "0100" or hcnt(3 downto 0) = "1000" or hcnt(3 downto 0) = "1100" or hcnt(3 downto 0) = "0000" then + sp_graphics1_do <= sp_graphics_do(7 downto 0); + sp_graphics2_do <= sp_graphics_do(15 downto 8); + sp_graphics3_do <= sp_graphics_do(23 downto 16); + end if; end if; else if flip = '1' then - sp_bit_hpos <= hcnt(7 downto 0) - 5; -- tune sprite position w.r.t. background + sp_bit_hpos_r <= hcnt(7 downto 0) - 5; -- tune sprite position w.r.t. background else - sp_bit_hpos <= hcnt(7 downto 0) - 2; -- tune sprite position w.r.t. background + sp_bit_hpos_r <= hcnt(7 downto 0) - 2; -- tune sprite position w.r.t. background end if; end if; @@ -745,26 +777,28 @@ map_offset_h <= (bg_position & '1') + (x"0" & vflip(7 downto 0)) + 1; -- count from "00"->"FF" and then continue with "00"->"7F" instead of "80"->"FF" hflip2 <= hflip xor (not(hcnt(8)) & "0000000") when flip = '1' else hflip; -map_offset_l1 <= not('0' & vflip(7 downto 1)) + (hflip2(7 downto 3) & "111") + 1; +map_offset_l1 <= not('0' & vflip(7 downto 1)) + (hflip2(7 downto 3) & "111"); map_offset_l2 <= map_offset_l1 + ('0' & not(flip) & flip & flip & flip & "000"); map_addr <= map_offset_h(11 downto 3) & map_offset_l2(7 downto 3); -bg_graphics_addr(2 downto 0) <= map_offset_h(2 downto 0); - process (clock_vid) begin if rising_edge(clock_vid) then if pix_ena = '1' then - if hcnt(2 downto 0) = "011" then -- 4H^ - bg_code_line(9 downto 0) <= map2_do(1 downto 0) & map1_do; + if (not(vflip(3 downto 1)) + hflip(2 downto 0)) = "000" then + bg_graphics_addr(12 downto 3) <= map2_do(1 downto 0) & map1_do; -- bg_code_line + bg_graphics_addr(2 downto 0) <= map_offset_h(2 downto 0); bg_color_a <= map2_do(7 downto 4); end if; if (not(vflip(3 downto 1)) + hflip(2 downto 0)) = "011" then - bg_graphics_addr(12 downto 3) <= bg_code_line; + bg_graphics1_do <= bg_graphics_do(7 downto 0); + bg_graphics2_do <= bg_graphics_do(15 downto 8); + bg_graphics3_do <= bg_graphics_do(23 downto 16); + bg_color <= bg_color_a; if flip = '1' then bg_bit_nb <= 0; else bg_bit_nb <= 7; end if; @@ -847,7 +881,19 @@ port map( -- addr => cpu_addr(14 downto 0), -- data => cpu_rom_do --); -cpu_rom_addr <= cpu_addr(14 downto 0); + +rom_cpu : Sega_Crypt +port map( + clk => clock_vidn, + enc_type => enc_type, + mrom_m1 => not cpu_m1_n, + mrom_ad => cpu_addr(14 downto 0), + mrom_dt => cpu_rom_dec, + cpu_rom_addr => cpu_rom_addr_enc, + cpu_rom_do => cpu_rom_do +); + +cpu_rom_addr <= cpu_addr(14 downto 0) when enc_type = x"0" else cpu_rom_addr_enc; -- working RAM 0x6000-0x6FFF wram : entity work.gen_ram @@ -906,6 +952,7 @@ port map( q => sp_buffer_ram_do ); + -- char graphics ROM 1 bg_graphics_1 : entity work.dpram generic map( @@ -921,7 +968,7 @@ port map( we_b => bg_graphics_1_we, d_b => dl_data ); -bg_graphics_1_we <= '1' when dl_wr = '1' and dl_addr(16 downto 11) = "011110" else '0'; +bg_graphics_1_we <= '1' when dl_wr = '1' and dl_addr(17 downto 11) = "0011110" else '0'; -- char graphics ROM 2 bg_graphics_2 : entity work.dpram @@ -938,128 +985,45 @@ port map( we_b => bg_graphics_2_we, d_b => dl_data ); -bg_graphics_2_we <= '1' when dl_wr = '1' and dl_addr(16 downto 11) = "011111" else '0'; +bg_graphics_2_we <= '1' when dl_wr = '1' and dl_addr(17 downto 11) = "0011111" else '0'; +map_dl_addr <= dl_addr + x"1000"; -- map tile ROM 1 ---map_tile_1 : entity work.zaxxon_map_1 ---port map( --- clk => clock_vidn, --- addr => map_addr, --- data => map1_do ---); -map1_do <= map_do(7 downto 0); - +map_tile_1 : entity work.dpram +generic map( + dWidth => 8, + aWidth => 14 +) +port map( + clk_a => clock_vidn, + addr_a => map_addr, + q_a => map1_do, + clk_b => clock_vid, + addr_b => map_dl_addr(13 downto 0), + we_b => map1_we, + d_b => dl_data +); +--map1_do <= map_do(7 downto 0); +map1_we <= '1' when dl_wr = '1' and map_dl_addr(17 downto 14) = "0010" else '0';-- 7000-AFFF (+1000) +-- -- map tile ROM 2 ---map_tile_2 : entity work.zaxxon_map_2 ---port map( --- clk => clock_vidn, --- addr => map_addr, --- data => map2_do ---); -map2_do <= map_do(15 downto 8); - --- background graphics ROM 1 -bg_graphics_bits_1 : entity work.dpram +map_tile_2 : entity work.dpram generic map( dWidth => 8, - aWidth => 13 + aWidth => 14 ) port map( clk_a => clock_vidn, - addr_a => bg_graphics_addr, - q_a => bg_graphics1_do, + addr_a => map_addr, + q_a => map2_do, clk_b => clock_vid, - addr_b => dl_addr(12 downto 0), - we_b => bg_graphics_bits_1_we, + addr_b => map_dl_addr(13 downto 0), + we_b => map2_we, d_b => dl_data ); -bg_graphics_bits_1_we <= '1' when dl_wr = '1' and dl_addr(16 downto 13) = "1000" else '0'; --10000-11fff - --- background graphics ROM 2 -bg_graphics_bits_2 : entity work.dpram -generic map( - dWidth => 8, - aWidth => 13 -) -port map( - clk_a => clock_vidn, - addr_a => bg_graphics_addr, - q_a => bg_graphics2_do, - clk_b => clock_vid, - addr_b => dl_addr(12 downto 0), - we_b => bg_graphics_bits_2_we, - d_b => dl_data -); -bg_graphics_bits_2_we <= '1' when dl_wr = '1' and dl_addr(16 downto 13) = "1001" else '0'; --12000-13fff - --- background graphics ROM 3 -bg_graphics_bits_3 : entity work.dpram -generic map( - dWidth => 8, - aWidth => 13 -) -port map( - clk_a => clock_vidn, - addr_a => bg_graphics_addr, - q_a => bg_graphics3_do, - clk_b => clock_vid, - addr_b => dl_addr(12 downto 0), - we_b => bg_graphics_bits_3_we, - d_b => dl_data -); -bg_graphics_bits_3_we <= '1' when dl_wr = '1' and dl_addr(16 downto 13) = "1010" else '0'; --14000-15fff - --- sprite graphics ROM 1 -sp_graphics_bits_1 : entity work.dpram -generic map( - dWidth => 8, - aWidth => 13 -) -port map( - clk_a => clock_vidn, - addr_a => sp_graphics_addr, - q_a => sp_graphics1_do, - clk_b => clock_vid, - addr_b => dl_addr(12 downto 0), - we_b => sp_graphics_bits_1_we, - d_b => dl_data -); -sp_graphics_bits_1_we <= '1' when dl_wr = '1' and dl_addr(16 downto 13) = "1011" else '0'; --16000-17fff - --- sprite graphics ROM 2 -sp_graphics_bits_2 : entity work.dpram -generic map( - dWidth => 8, - aWidth => 13 -) -port map( - clk_a => clock_vidn, - addr_a => sp_graphics_addr, - q_a => sp_graphics2_do, - clk_b => clock_vid, - addr_b => dl_addr(12 downto 0), - we_b => sp_graphics_bits_2_we, - d_b => dl_data -); -sp_graphics_bits_2_we <= '1' when dl_wr = '1' and dl_addr(16 downto 13) = "1100" else '0'; --18000-19fff - --- sprite graphics ROM 3 -sp_graphics_bits_3 : entity work.dpram -generic map( - dWidth => 8, - aWidth => 13 -) -port map( - clk_a => clock_vidn, - addr_a => sp_graphics_addr, - q_a => sp_graphics3_do, - clk_b => clock_vid, - addr_b => dl_addr(12 downto 0), - we_b => sp_graphics_bits_3_we, - d_b => dl_data -); -sp_graphics_bits_3_we <= '1' when dl_wr = '1' and dl_addr(16 downto 13) = "1101" else '0'; --1a000-1bfff +--map2_do <= map_do(15 downto 8); +map2_we <= '1' when dl_wr = '1' and map_dl_addr(17 downto 14) = "0011" else '0'; -- B000-EFFF (+1000) -- char color char_color : entity work.dpram @@ -1076,7 +1040,7 @@ port map( we_b => char_color_we, d_b => dl_data ); -char_color_we <= '1' when dl_wr = '1' and dl_addr(16 downto 8) = "111000001" else '0'; --1C100-1C1FF +char_color_we <= '1' when dl_wr = '1' and dl_addr(17 downto 8) = "1010000001" else '0'; --28100-281FF -- palette palette : entity work.dpram @@ -1093,7 +1057,7 @@ port map( we_b => palette_we, d_b => dl_data ); -palette_we <= '1' when dl_wr = '1' and dl_addr(16 downto 8) = "111000000" else '0'; --1C000-1C0FF +palette_we <= '1' when dl_wr = '1' and dl_addr(17 downto 8) = "1010000000" else '0'; --28000-280FF --zaxxon_sound_board sound_board : entity work.zaxxon_sound