diff --git a/Bally - Astrocade_MiST/Snapshot/bally_mist.rbf b/Bally - Astrocade_MiST/Snapshot/bally_mist.rbf index 244bdd4f..b43d537e 100644 Binary files a/Bally - Astrocade_MiST/Snapshot/bally_mist.rbf and b/Bally - Astrocade_MiST/Snapshot/bally_mist.rbf differ diff --git a/Bally - Astrocade_MiST/bally_mist.qsf b/Bally - Astrocade_MiST/bally_mist.qsf index 92bc1614..236f41b6 100644 --- a/Bally - Astrocade_MiST/bally_mist.qsf +++ b/Bally - Astrocade_MiST/bally_mist.qsf @@ -137,7 +137,6 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end ENTITY(bally_mist) # ---------------------- set_global_assignment -name SYSTEMVERILOG_FILE rtl/bally_mist.sv -set_global_assignment -name VHDL_FILE rtl/bally_top.vhd set_global_assignment -name VHDL_FILE rtl/bally.vhd set_global_assignment -name VHDL_FILE rtl/ps2kbd.vhd set_global_assignment -name VHDL_FILE rtl/bally_rams.vhd @@ -163,4 +162,5 @@ set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd set_global_assignment -name VHDL_FILE rtl/pll.vhd set_global_assignment -name VERILOG_FILE rtl/game.v set_global_assignment -name QIP_FILE rtl/cart.qip +set_global_assignment -name VHDL_FILE rtl/bally_check_cart.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Bally - Astrocade_MiST/rtl/bally_check_cart.vhd b/Bally - Astrocade_MiST/rtl/bally_check_cart.vhd index 5fa046d2..22dd4812 100644 --- a/Bally - Astrocade_MiST/rtl/bally_check_cart.vhd +++ b/Bally - Astrocade_MiST/rtl/bally_check_cart.vhd @@ -70,25 +70,22 @@ end; architecture RTL of BALLY_CHECK_CART is - component BALLY_CHECK - port ( - CLK : in std_logic; - ADDR : in std_logic_vector(10 downto 0); - DATA : out std_logic_vector(7 downto 0) - ); - end component; - signal dout : std_logic_vector(7 downto 0); begin -- chars 0-9, a = '-', b = 'E', c = 'H', d = 'L', e = 'P', f = blank - u_rom : entity work.BALLY_CHECK - port map ( - clock => CLK, - clken => ENA, - address => I_EXP_ADDR(10 downto 0), - q => dout - ); + u_rom : entity work.sprom + generic map ( + init_file => ".\roms\balcheck.hex", + widthad_a => 11, + width_a => 8 + ) + port map ( + address => I_EXP_ADDR(10 downto 0), + clock => CLK, + q => dout + ); + p_dout : process(dout, I_EXP_ADDR) begin diff --git a/Bally - Astrocade_MiST/rtl/bally_mist.sv b/Bally - Astrocade_MiST/rtl/bally_mist.sv index 89cf26fc..7b7f45bb 100644 --- a/Bally - Astrocade_MiST/rtl/bally_mist.sv +++ b/Bally - Astrocade_MiST/rtl/bally_mist.sv @@ -20,6 +20,7 @@ module bally_mist( localparam CONF_STR = { "BALLY;BIN;", +// "O2,Check Cart, On, Off;", "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", "T6,Reset;", "V,v1.00.",`BUILD_DATE @@ -28,9 +29,11 @@ localparam CONF_STR = { wire clk_28;//28.5712 wire clk_14;//14.2856 wire clk_7;//7.1428 +wire clk_1;//1.0204 +wire reset = status[0] | status[6] | buttons[1] | ioctl_downl; wire [12:0] cart_addr; -wire [7:0] cart_do; +wire [7:0] cart_di, cart_do; wire cart_cs; wire ioctl_downl; wire [7:0] ioctl_index; @@ -49,19 +52,35 @@ wire [7:0] joystick_1; wire scandoubler_disable; wire ypbpr; wire ps2_kbd_clk, ps2_kbd_data; +wire [7:0] switch_col; +wire [7:0] switch_row; wire [7:0] audio; wire pix_ena; wire hs, vs; wire [3:0] r,g,b; +wire [15:0] exp_addr; +wire [7:0] exp_data_out; +wire [7:0] exp_data_in; +wire exp_oe_l; +wire exp_m1_l; +wire exp_mreq_l; +wire exp_iorq_l; +wire exp_wr_l; +wire exp_rd_l; + +wire [3:0] check_cart_msb; +wire [7:4] check_cart_lsb; + pll pll ( .inclk0(CLOCK_27), .c0(clk_28), .c1(clk_14), - .c2(clk_7) + .c2(clk_7), + .c3(clk_1) ); video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(0)) video_mixer @@ -125,7 +144,7 @@ cart cart ( .wren ( ioctl_downl && ioctl_wr), .q ( cart_do ) ); - +/* BALLY_TOP BALLY_TOP ( .cas_addr(cart_addr), .cas_data(cart_do), @@ -142,17 +161,86 @@ BALLY_TOP BALLY_TOP ( .pix_ena(pix_ena), .clk_14(clk_14), .clk_7(clk_7), - .reset((status[0] | status[6] | buttons[1] | ioctl_downl)) - ); + .reset(reset) + );*/ + +BALLY_PS2_IF BALLY_PS2_IF ( + .I_PS2_CLK(ps2_kbd_clk), + .I_PS2_DATA(ps2_kbd_data), + .I_COL (switch_col), + .O_ROW (switch_row), + .I_RESET_L (~reset), + .I_1MHZ_ENA(clk_1), + .CLK (clk_7) + ); + +BALLY BALLY ( + .O_AUDIO(audio), + + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_COMP_SYNC_L(), + .O_FPSYNC(), + + .O_CAS_ADDR(cart_addr), + .O_CAS_DATA(), + .I_CAS_DATA(cart_do), + .O_CAS_CS_L(cart_cs), + + .O_EXP_ADDR(exp_addr), + .O_EXP_DATA(exp_data_out), + .I_EXP_DATA(exp_data_in), + .I_EXP_OE_L(exp_oe_l), + .O_EXP_M1_L(exp_m1_l), + .O_EXP_MREQ_L(exp_mreq_l), + .O_EXP_IORQ_L(exp_iorq_l), + .O_EXP_WR_L(exp_wr_l), + .O_EXP_RD_L(exp_rd_l), + + .O_SWITCH_COL(switch_col), + .I_SWITCH_ROW(switch_row), + + .I_RESET_L(~reset), + .ENA(1'b1), + .pix_ena(pix_ena), + .CLK(clk_14), + .CLK7(clk_7) + ); dac dac ( .clk_i(clk_28), - .res_n_i(1'b1), + .res_n_i(~reset), .dac_i(audio), .dac_o(AUDIO_L) ); assign AUDIO_R = AUDIO_L; +/* +BALLY_CHECK_CART BALLY_CHECK_CART ( + .I_EXP_ADDR(exp_addr), + .I_EXP_DATA(exp_data_out), + .O_EXP_DATA(exp_data_in), + .O_EXP_OE_L(exp_oe_l), + .I_EXP_M1_L(exp_m1_l), + .I_EXP_MREQ_L(exp_mreq_l), + .I_EXP_IORQ_L(exp_iorq_l), + .I_EXP_WR_L(exp_wr_l), + .I_EXP_RD_L(exp_rd_l), + . O_CHAR_MSB(check_cart_msb), + .O_CHAR_LSB(check_cart_lsb), + .I_RESET_L(~reset), + .ENA(status[2]), + .CLK(clk_7) + );*/ + + +// if no expansion cart + assign exp_data_in = 8'hff; + assign exp_oe_l = 1'b1; endmodule diff --git a/Bally - Astrocade_MiST/rtl/build_id.v b/Bally - Astrocade_MiST/rtl/build_id.v index ab23e366..12e39796 100644 --- a/Bally - Astrocade_MiST/rtl/build_id.v +++ b/Bally - Astrocade_MiST/rtl/build_id.v @@ -1,2 +1,2 @@ `define BUILD_DATE "180725" -`define BUILD_TIME "160612" +`define BUILD_TIME "170812" diff --git a/Bally - Astrocade_MiST/rtl/pll.vhd b/Bally - Astrocade_MiST/rtl/pll.vhd index c9a1d016..6e93a0d3 100644 --- a/Bally - Astrocade_MiST/rtl/pll.vhd +++ b/Bally - Astrocade_MiST/rtl/pll.vhd @@ -45,7 +45,8 @@ ENTITY pll IS inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ); END pll; @@ -57,9 +58,10 @@ ARCHITECTURE SYN OF pll IS SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); @@ -78,6 +80,10 @@ ARCHITECTURE SYN OF pll IS clk2_duty_cycle : NATURAL; clk2_multiply_by : NATURAL; clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; compensate_clock : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; @@ -135,16 +141,18 @@ ARCHITECTURE SYN OF pll IS END COMPONENT; BEGIN - sub_wire6_bv(0 DOWNTO 0) <= "0"; - sub_wire6 <= To_stdlogicvector(sub_wire6_bv); - sub_wire3 <= sub_wire0(2); - sub_wire2 <= sub_wire0(0); + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); sub_wire1 <= sub_wire0(1); c1 <= sub_wire1; - c0 <= sub_wire2; - c2 <= sub_wire3; - sub_wire4 <= inclk0; - sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; altpll_component : altpll GENERIC MAP ( @@ -161,6 +169,10 @@ BEGIN clk2_duty_cycle => 50, clk2_multiply_by => 55, clk2_phase_shift => "0", + clk3_divide_by => 1456, + clk3_duty_cycle => 50, + clk3_multiply_by => 55, + clk3_phase_shift => "0", compensate_clock => "CLK0", inclk0_input_frequency => 37037, intended_device_family => "Cyclone III", @@ -196,7 +208,7 @@ BEGIN port_clk0 => "PORT_USED", port_clk1 => "PORT_USED", port_clk2 => "PORT_USED", - port_clk3 => "PORT_UNUSED", + port_clk3 => "PORT_USED", port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", @@ -212,7 +224,7 @@ BEGIN width_clock => 5 ) PORT MAP ( - inclk => sub_wire5, + inclk => sub_wire6, clk => sub_wire0 ); @@ -242,12 +254,15 @@ END SYN; -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "52" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "104" -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "208" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1456" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.557692" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "14.278846" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "7.139423" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "1.019918" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -270,32 +285,40 @@ END SYN; -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "55" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "55" -- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "55" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "55" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.57120000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.28560000" -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "7.14280000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "1.02040000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -320,15 +343,18 @@ END SYN; -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_CLK0 STRING "1" -- Retrieval info: PRIVATE: USE_CLK1 STRING "1" -- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -345,6 +371,10 @@ END SYN; -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "55" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1456" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "55" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -379,7 +409,7 @@ END SYN; -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" @@ -398,12 +428,14 @@ END SYN; -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE