diff --git a/Arcade_MiST/Toaplan v1 Hardware/DemonsWorld.qsf b/Arcade_MiST/Toaplan v1 Hardware/DemonsWorld.qsf deleted file mode 100644 index 2a77a5d9..00000000 --- a/Arcade_MiST/Toaplan v1 Hardware/DemonsWorld.qsf +++ /dev/null @@ -1,245 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Full Version -# Date created = 16:51:06 July 10, 2023 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# DemonsWorld_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SMART_RECOMPILE ON - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PIN_49 -to SDRAM_A[0] -set_location_assignment PIN_44 -to SDRAM_A[1] -set_location_assignment PIN_42 -to SDRAM_A[2] -set_location_assignment PIN_39 -to SDRAM_A[3] -set_location_assignment PIN_4 -to SDRAM_A[4] -set_location_assignment PIN_6 -to SDRAM_A[5] -set_location_assignment PIN_8 -to SDRAM_A[6] -set_location_assignment PIN_10 -to SDRAM_A[7] -set_location_assignment PIN_11 -to SDRAM_A[8] -set_location_assignment PIN_28 -to SDRAM_A[9] -set_location_assignment PIN_50 -to SDRAM_A[10] -set_location_assignment PIN_30 -to SDRAM_A[11] -set_location_assignment PIN_32 -to SDRAM_A[12] -set_location_assignment PIN_83 -to SDRAM_DQ[0] -set_location_assignment PIN_79 -to SDRAM_DQ[1] -set_location_assignment PIN_77 -to SDRAM_DQ[2] -set_location_assignment PIN_76 -to SDRAM_DQ[3] -set_location_assignment PIN_72 -to SDRAM_DQ[4] -set_location_assignment PIN_71 -to SDRAM_DQ[5] -set_location_assignment PIN_69 -to SDRAM_DQ[6] -set_location_assignment PIN_68 -to SDRAM_DQ[7] -set_location_assignment PIN_86 -to SDRAM_DQ[8] -set_location_assignment PIN_87 -to SDRAM_DQ[9] -set_location_assignment PIN_98 -to SDRAM_DQ[10] -set_location_assignment PIN_99 -to SDRAM_DQ[11] -set_location_assignment PIN_100 -to SDRAM_DQ[12] -set_location_assignment PIN_101 -to SDRAM_DQ[13] -set_location_assignment PIN_103 -to SDRAM_DQ[14] -set_location_assignment PIN_104 -to SDRAM_DQ[15] -set_location_assignment PIN_58 -to SDRAM_BA[0] -set_location_assignment PIN_51 -to SDRAM_BA[1] -set_location_assignment PIN_85 -to SDRAM_DQMH -set_location_assignment PIN_67 -to SDRAM_DQML -set_location_assignment PIN_60 -to SDRAM_nRAS -set_location_assignment PIN_64 -to SDRAM_nCAS -set_location_assignment PIN_66 -to SDRAM_nWE -set_location_assignment PIN_59 -to SDRAM_nCS -set_location_assignment PIN_33 -to SDRAM_CKE -set_location_assignment PIN_43 -to SDRAM_CLK -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name TOP_LEVEL_ENTITY DemonsWorld -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 -set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# SignalTap II Assignments -# ======================== -set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/dect.stp - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# ------------------------- -# start ENTITY(DemonsWorld) - - # Pin & Location Assignments - # ========================== - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS - set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] - set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] - - # Fitter Assignments - # ================== - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*] - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*] - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*] - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*] - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*] - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*] - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS - set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L - set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R - set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(DemonsWorld) -# ----------------------- -set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_demonsworld/DemonsWorld.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_demonsworld/DemonsWorld_Top.sv -set_global_assignment -name VERILOG_FILE rtl/rtl_demonsworld/chip_select.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv -set_global_assignment -name QIP_FILE rtl/common/common.qip -set_global_assignment -name VERILOG_FILE rtl/pll_mist.v -set_global_assignment -name QIP_FILE rtl/TMS320C1X/TMS320C1X.qip -set_global_assignment -name QIP_FILE ../../common/Sound/jtopl/jt26.qip -set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip -set_global_assignment -name QIP_FILE ../../common/CPU/68000/FX68k/fx68k.qip -set_global_assignment -name QIP_FILE ../../common/mist/mist.qip -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Toaplan v1 Hardware/RallyBike.qpf b/Arcade_MiST/Toaplan v1 Hardware/RallyBike.qpf deleted file mode 100644 index e486db1b..00000000 --- a/Arcade_MiST/Toaplan v1 Hardware/RallyBike.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Full Version -# Date created = 16:01:18 November 25, 2020 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "16:01:18 November 25, 2020" - -# Revisions - -PROJECT_REVISION = "RallyBike" diff --git a/Arcade_MiST/Toaplan v1 Hardware/RallyBike.qsf b/Arcade_MiST/Toaplan v1 Hardware/RallyBike.qsf deleted file mode 100644 index c4bf5816..00000000 --- a/Arcade_MiST/Toaplan v1 Hardware/RallyBike.qsf +++ /dev/null @@ -1,244 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Full Version -# Date created = 12:43:38 July 08, 2023 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# RallyBike_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SMART_RECOMPILE ON - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PIN_49 -to SDRAM_A[0] -set_location_assignment PIN_44 -to SDRAM_A[1] -set_location_assignment PIN_42 -to SDRAM_A[2] -set_location_assignment PIN_39 -to SDRAM_A[3] -set_location_assignment PIN_4 -to SDRAM_A[4] -set_location_assignment PIN_6 -to SDRAM_A[5] -set_location_assignment PIN_8 -to SDRAM_A[6] -set_location_assignment PIN_10 -to SDRAM_A[7] -set_location_assignment PIN_11 -to SDRAM_A[8] -set_location_assignment PIN_28 -to SDRAM_A[9] -set_location_assignment PIN_50 -to SDRAM_A[10] -set_location_assignment PIN_30 -to SDRAM_A[11] -set_location_assignment PIN_32 -to SDRAM_A[12] -set_location_assignment PIN_83 -to SDRAM_DQ[0] -set_location_assignment PIN_79 -to SDRAM_DQ[1] -set_location_assignment PIN_77 -to SDRAM_DQ[2] -set_location_assignment PIN_76 -to SDRAM_DQ[3] -set_location_assignment PIN_72 -to SDRAM_DQ[4] -set_location_assignment PIN_71 -to SDRAM_DQ[5] -set_location_assignment PIN_69 -to SDRAM_DQ[6] -set_location_assignment PIN_68 -to SDRAM_DQ[7] -set_location_assignment PIN_86 -to SDRAM_DQ[8] -set_location_assignment PIN_87 -to SDRAM_DQ[9] -set_location_assignment PIN_98 -to SDRAM_DQ[10] -set_location_assignment PIN_99 -to SDRAM_DQ[11] -set_location_assignment PIN_100 -to SDRAM_DQ[12] -set_location_assignment PIN_101 -to SDRAM_DQ[13] -set_location_assignment PIN_103 -to SDRAM_DQ[14] -set_location_assignment PIN_104 -to SDRAM_DQ[15] -set_location_assignment PIN_58 -to SDRAM_BA[0] -set_location_assignment PIN_51 -to SDRAM_BA[1] -set_location_assignment PIN_85 -to SDRAM_DQMH -set_location_assignment PIN_67 -to SDRAM_DQML -set_location_assignment PIN_60 -to SDRAM_nRAS -set_location_assignment PIN_64 -to SDRAM_nCAS -set_location_assignment PIN_66 -to SDRAM_nWE -set_location_assignment PIN_59 -to SDRAM_nCS -set_location_assignment PIN_33 -to SDRAM_CKE -set_location_assignment PIN_43 -to SDRAM_CLK -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name TOP_LEVEL_ENTITY RallyBike -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 -set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# SignalTap II Assignments -# ======================== -set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/dect.stp - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# --------------------- -# start ENTITY(TaitoSJ) - - # Pin & Location Assignments - # ========================== - - # Fitter Assignments - # ================== - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(TaitoSJ) -# ------------------- -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO -set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_rallybike/RallyBike.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_rallybike/RallyBike_Top.sv -set_global_assignment -name VERILOG_FILE rtl/rtl_rallybike/chip_select.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv -set_global_assignment -name QIP_FILE rtl/common/common.qip -set_global_assignment -name VERILOG_FILE rtl/pll_mist.v -set_global_assignment -name QIP_FILE ../../common/Sound/jtopl/jt26.qip -set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip -set_global_assignment -name QIP_FILE ../../common/CPU/68000/FX68k/fx68k.qip -set_global_assignment -name QIP_FILE ../../common/mist/mist.qip -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Toaplan v1 Hardware/DemonsWorld.qpf b/Arcade_MiST/Toaplan v1 Hardware/ToaplanV1.qpf similarity index 91% rename from Arcade_MiST/Toaplan v1 Hardware/DemonsWorld.qpf rename to Arcade_MiST/Toaplan v1 Hardware/ToaplanV1.qpf index ef2d0fbc..700c515b 100644 --- a/Arcade_MiST/Toaplan v1 Hardware/DemonsWorld.qpf +++ b/Arcade_MiST/Toaplan v1 Hardware/ToaplanV1.qpf @@ -18,13 +18,14 @@ # # Quartus II 64-Bit # Version 13.1.4 Build 182 03/12/2014 SJ Full Version -# Date created = 16:01:18 November 25, 2020 +# Date created = 11:52:25 July 11, 2023 # # -------------------------------------------------------------------------- # QUARTUS_VERSION = "13.1" -DATE = "16:01:18 November 25, 2020" +DATE = "11:52:25 July 11, 2023" # Revisions +PROJECT_REVISION = "ToaplanV1" PROJECT_REVISION = "DemonsWorld" diff --git a/Arcade_MiST/Toaplan v1 Hardware/Vimana.qsf b/Arcade_MiST/Toaplan v1 Hardware/ToaplanV1.qsf similarity index 94% rename from Arcade_MiST/Toaplan v1 Hardware/Vimana.qsf rename to Arcade_MiST/Toaplan v1 Hardware/ToaplanV1.qsf index 388d96e9..fb6ddddd 100644 --- a/Arcade_MiST/Toaplan v1 Hardware/Vimana.qsf +++ b/Arcade_MiST/Toaplan v1 Hardware/ToaplanV1.qsf @@ -18,14 +18,14 @@ # # Quartus II 64-Bit # Version 13.1.4 Build 182 03/12/2014 SJ Full Version -# Date created = 15:05:30 July 08, 2023 +# Date created = 16:51:06 July 10, 2023 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: -# Vimana_assignment_defaults.qdf +# DemonsWorld_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # @@ -42,8 +42,9 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SMART_RECOMPILE ON + # Pin & Location Assignments # ========================== set_location_assignment PIN_7 -to LED @@ -129,7 +130,7 @@ set_global_assignment -name FAMILY "Cyclone III" set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name TOP_LEVEL_ENTITY Vimana +set_global_assignment -name TOP_LEVEL_ENTITY ToaplanV1 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 @@ -176,8 +177,8 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall -# --------------------------- -# start ENTITY(RallyBike_Top) +# ------------------------- +# start ENTITY(DemonsWorld) # Pin & Location Assignments # ========================== @@ -194,14 +195,12 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # end DESIGN_PARTITION(Top) # ------------------------- -# end ENTITY(RallyBike_Top) -# ------------------------- -set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_vimana/Vimana.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_vimana/Vimana_Top.sv -set_global_assignment -name VERILOG_FILE rtl/rtl_vimana/chip_select.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv -set_global_assignment -name VERILOG_FILE rtl/pll_mist.v -set_global_assignment -name QIP_FILE rtl/common/common.qip +# end ENTITY(DemonsWorld) +# ----------------------- +set_global_assignment -name SYSTEMVERILOG_FILE rtl/ToaplanV1.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/ToaplanV1_Top.sv +set_global_assignment -name VERILOG_FILE rtl/chip_select.v +set_global_assignment -name QIP_FILE rtl/TMS320C1X/TMS320C1X.qip set_global_assignment -name QIP_FILE ../../common/Sound/jtopl/jt26.qip set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip set_global_assignment -name QIP_FILE ../../common/CPU/68000/FX68k/fx68k.qip @@ -240,4 +239,5 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO +set_global_assignment -name QIP_FILE rtl/common.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Toaplan v1 Hardware/Vimana.qpf b/Arcade_MiST/Toaplan v1 Hardware/Vimana.qpf deleted file mode 100644 index d2445240..00000000 --- a/Arcade_MiST/Toaplan v1 Hardware/Vimana.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Full Version -# Date created = 16:01:18 November 25, 2020 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "16:01:18 November 25, 2020" - -# Revisions - -PROJECT_REVISION = "Vimana" diff --git a/Arcade_MiST/Toaplan v1 Hardware/Zerowing.qpf b/Arcade_MiST/Toaplan v1 Hardware/Zerowing.qpf deleted file mode 100644 index 1cfc37d6..00000000 --- a/Arcade_MiST/Toaplan v1 Hardware/Zerowing.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Full Version -# Date created = 16:01:18 November 25, 2020 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "16:01:18 November 25, 2020" - -# Revisions - -PROJECT_REVISION = "Zerowing" diff --git a/Arcade_MiST/Toaplan v1 Hardware/Zerowing.qsf b/Arcade_MiST/Toaplan v1 Hardware/Zerowing.qsf deleted file mode 100644 index ef4d0a07..00000000 --- a/Arcade_MiST/Toaplan v1 Hardware/Zerowing.qsf +++ /dev/null @@ -1,244 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Full Version -# Date created = 15:42:51 July 08, 2023 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Zerowing_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PIN_49 -to SDRAM_A[0] -set_location_assignment PIN_44 -to SDRAM_A[1] -set_location_assignment PIN_42 -to SDRAM_A[2] -set_location_assignment PIN_39 -to SDRAM_A[3] -set_location_assignment PIN_4 -to SDRAM_A[4] -set_location_assignment PIN_6 -to SDRAM_A[5] -set_location_assignment PIN_8 -to SDRAM_A[6] -set_location_assignment PIN_10 -to SDRAM_A[7] -set_location_assignment PIN_11 -to SDRAM_A[8] -set_location_assignment PIN_28 -to SDRAM_A[9] -set_location_assignment PIN_50 -to SDRAM_A[10] -set_location_assignment PIN_30 -to SDRAM_A[11] -set_location_assignment PIN_32 -to SDRAM_A[12] -set_location_assignment PIN_83 -to SDRAM_DQ[0] -set_location_assignment PIN_79 -to SDRAM_DQ[1] -set_location_assignment PIN_77 -to SDRAM_DQ[2] -set_location_assignment PIN_76 -to SDRAM_DQ[3] -set_location_assignment PIN_72 -to SDRAM_DQ[4] -set_location_assignment PIN_71 -to SDRAM_DQ[5] -set_location_assignment PIN_69 -to SDRAM_DQ[6] -set_location_assignment PIN_68 -to SDRAM_DQ[7] -set_location_assignment PIN_86 -to SDRAM_DQ[8] -set_location_assignment PIN_87 -to SDRAM_DQ[9] -set_location_assignment PIN_98 -to SDRAM_DQ[10] -set_location_assignment PIN_99 -to SDRAM_DQ[11] -set_location_assignment PIN_100 -to SDRAM_DQ[12] -set_location_assignment PIN_101 -to SDRAM_DQ[13] -set_location_assignment PIN_103 -to SDRAM_DQ[14] -set_location_assignment PIN_104 -to SDRAM_DQ[15] -set_location_assignment PIN_58 -to SDRAM_BA[0] -set_location_assignment PIN_51 -to SDRAM_BA[1] -set_location_assignment PIN_85 -to SDRAM_DQMH -set_location_assignment PIN_67 -to SDRAM_DQML -set_location_assignment PIN_60 -to SDRAM_nRAS -set_location_assignment PIN_64 -to SDRAM_nCAS -set_location_assignment PIN_66 -to SDRAM_nWE -set_location_assignment PIN_59 -to SDRAM_nCS -set_location_assignment PIN_33 -to SDRAM_CKE -set_location_assignment PIN_43 -to SDRAM_CLK -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name TOP_LEVEL_ENTITY Zerowing -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 -set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# SignalTap II Assignments -# ======================== -set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/dect.stp - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# -------------------------- -# start ENTITY(Zerowing_Top) - - # Pin & Location Assignments - # ========================== - - # Fitter Assignments - # ================== - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(Zerowing_Top) -# ------------------------ -set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_zerowing/Zerowing.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_zerowing/Zerowing_Top.sv -set_global_assignment -name VERILOG_FILE rtl/rtl_zerowing/chip_select.v -set_global_assignment -name QIP_FILE rtl/common/common.qip -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv -set_global_assignment -name VERILOG_FILE rtl/pll_mist.v -set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip -set_global_assignment -name QIP_FILE ../../common/mist/mist.qip -set_global_assignment -name QIP_FILE ../../common/Sound/jtopl/jt26.qip -set_global_assignment -name QIP_FILE ../../common/CPU/68000/FX68k/fx68k.qip -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Toaplan v1 Hardware/meta/Demons World - Horror Story (Set 3).mra b/Arcade_MiST/Toaplan v1 Hardware/meta/Demons World - Horror Story (Set 3).mra index 8c5b3e12..783709a9 100644 --- a/Arcade_MiST/Toaplan v1 Hardware/meta/Demons World - Horror Story (Set 3).mra +++ b/Arcade_MiST/Toaplan v1 Hardware/meta/Demons World - Horror Story (Set 3).mra @@ -28,6 +28,10 @@ + + 00 + + diff --git a/Arcade_MiST/Toaplan v1 Hardware/meta/Rally Bike - Dash Yarou.mra b/Arcade_MiST/Toaplan v1 Hardware/meta/Rally Bike - Dash Yarou.mra index 0682c674..0dad0398 100644 --- a/Arcade_MiST/Toaplan v1 Hardware/meta/Rally Bike - Dash Yarou.mra +++ b/Arcade_MiST/Toaplan v1 Hardware/meta/Rally Bike - Dash Yarou.mra @@ -27,6 +27,10 @@ + + 01 + + diff --git a/Arcade_MiST/Toaplan v1 Hardware/meta/Same! Same! Same! (2P Set).mra b/Arcade_MiST/Toaplan v1 Hardware/meta/Same! Same! Same! (2P Set).mra index 8060b630..46f7df8a 100644 --- a/Arcade_MiST/Toaplan v1 Hardware/meta/Same! Same! Same! (2P Set).mra +++ b/Arcade_MiST/Toaplan v1 Hardware/meta/Same! Same! Same! (2P Set).mra @@ -31,7 +31,7 @@ - 01 + 03 diff --git a/Arcade_MiST/Toaplan v1 Hardware/meta/Truxton - Tatsujin.mra b/Arcade_MiST/Toaplan v1 Hardware/meta/Truxton - Tatsujin.mra index ef937409..d145dcfc 100644 --- a/Arcade_MiST/Toaplan v1 Hardware/meta/Truxton - Tatsujin.mra +++ b/Arcade_MiST/Toaplan v1 Hardware/meta/Truxton - Tatsujin.mra @@ -31,7 +31,7 @@ - 04 + 05 diff --git a/Arcade_MiST/Toaplan v1 Hardware/meta/Vimana (Japan).mra b/Arcade_MiST/Toaplan v1 Hardware/meta/Vimana (Japan).mra index 1876fa7a..37876252 100644 --- a/Arcade_MiST/Toaplan v1 Hardware/meta/Vimana (Japan).mra +++ b/Arcade_MiST/Toaplan v1 Hardware/meta/Vimana (Japan).mra @@ -30,7 +30,7 @@ - 00 + 02 diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/ToaplanV1.sv b/Arcade_MiST/Toaplan v1 Hardware/rtl/ToaplanV1.sv new file mode 100644 index 00000000..9eb7dfc3 --- /dev/null +++ b/Arcade_MiST/Toaplan v1 Hardware/rtl/ToaplanV1.sv @@ -0,0 +1,304 @@ +//============================================================================ +// Toaplan Hardware v1 HW top-level for MiST +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module ToaplanV1( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + inout SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input SPI_SS4, + input CONF_DATA0, + input CLOCK_27, + + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE +); + +`include "build_id.v" +// CoreMod Game +// 0 Demons World +// 1 Rally Bike +// 2 Vimana +// 3 Same! Same! Same! +// 4 Zerowing +// 5 Truxton +// 6 Out Zone +// 7 Out Zone Conversation +// 8 HellFire + +assign LED = ~ioctl_downl; +assign SDRAM_CLK = clk_72; +assign SDRAM_CKE = 1; + +localparam CONF_STR = { + "ToaplanV1", ";;", + "O2,Rotate Controls,Off,On;", + "O34,Scanlines,Off,25%,50%,75%;", + "O5,Blending,Off,On;", + "O6,Joystick Swap,Off,On;", + "DIP;", + "T0,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire rotate = status[2]; +wire [1:0] scanlines = status[4:3]; +wire blend = status[5]; +wire joyswap = status[6]; + +wire [7:0] dsw1 = status[23:16]; +wire [7:0] dsw2 = status[31:24]; +wire [7:0] dsw3 = status[39:32]; +wire flipped; +wire key_service;// = m_fire1[4]; +wire key_test;// = m_fire1[3]; +wire key_tilt; + + +wire clk_72; +wire pll_locked; +pll_mist pll( + .inclk0(CLOCK_27), + .c0(clk_72), + .locked(pll_locked) + ); + +// reset generation +reg reset = 1; +reg rom_loaded = 0; +always @(posedge clk_72) begin + reg ioctl_downlD; + ioctl_downlD <= ioctl_downl; + if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1; + reset <= status[0] | buttons[1] | ~rom_loaded | ioctl_downl; +end + +// ARM connection +wire [63:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [31:0] joystick_0; +wire [31:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire no_csync; +wire key_strobe; +wire key_pressed; +wire [7:0] key_code; +wire [6:0] core_mod; + +user_io #( + .STRLEN($size(CONF_STR)>>3), + .ROM_DIRECT_UPLOAD(1)) +user_io( + .clk_sys (clk_72 ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .no_csync (no_csync ), + .core_mod (core_mod ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +wire ioctl_downl; +wire [7:0] ioctl_index; +wire ioctl_wr; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; + +data_io #(.ROM_DIRECT_UPLOAD(1)) data_io( + .clk_sys ( clk_72 ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS2 ( SPI_SS2 ), + .SPI_SS4 ( SPI_SS4 ), + .SPI_DI ( SPI_DI ), + .SPI_DO ( SPI_DO ), + .ioctl_download( ioctl_downl ), + .ioctl_index ( ioctl_index ), + .ioctl_wr ( ioctl_wr ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ) +); + +wire [15:0] laudio, raudio; +wire hs, vs; +wire blankn = ~(hb | vb); +wire hb, vb; +wire [4:0] r,b,g; + +ToaplanV1_Top ToaplanV1_Top( + .pll_locked ( pll_locked ), + .clk_sys ( clk_72 ), + .reset ( reset ), + .core_mod ( core_mod ), + .turbo_68k ( 0 ),//cpu_turbo + .pause_cpu ( 0 ), +// input scrollDBG, + .p1_right ( m_right1 ), + .p1_left ( m_left1 ), + .p1_down ( m_down1 ), + .p1_up ( m_up1 ), + .p1_buttons ( m_fire1[3:0] ), + .p2_right ( m_right2 ), + .p2_left ( m_left2 ), + .p2_down ( m_down2 ), + .p2_up ( m_up2 ), + .p2_buttons ( m_fire2[3:0] ), + .start1 ( m_one_player ), + .start2 ( m_two_players ), + .coin_a ( m_coin1 ), + .coin_b ( m_coin2 ), + .b_pause ( 0 ), + .service ( key_test ), + .key_tilt ( key_tilt ), + .key_service ( key_service ), + .sw0 ( dsw1 ), + .sw1 ( dsw2 ), + .sw2 ( dsw3 ), + + .hblank ( hb ), + .vblank ( vb ), + .hsync ( hs ), + .vsync ( vs ), + .r ( r ), + .g ( g ), + .b ( b ), + .hs_offset (0), + .vs_offset (0), + .hs_width (0), + .vs_width (0), + .refresh_mod (0), + + .ntsc (0), + .opl2_level (2'b00), + + + .audio_l ( laudio ), + .audio_r ( raudio ), + + .ioctl_download( ioctl_downl), + .ioctl_index (ioctl_index), + .ioctl_addr ( ioctl_addr - 2'd2 ),//check + .ioctl_wr ( ioctl_wr ), + .ioctl_dout ( ioctl_dout ), + + .SDRAM_A ( SDRAM_A ), + .SDRAM_BA ( SDRAM_BA ), + .SDRAM_DQ ( SDRAM_DQ ), + .SDRAM_DQML ( SDRAM_DQML ), + .SDRAM_DQMH ( SDRAM_DQMH ), + .SDRAM_nCS ( SDRAM_nCS ), + .SDRAM_nCAS ( SDRAM_nCAS ), + .SDRAM_nRAS ( SDRAM_nRAS ), + .SDRAM_nWE ( SDRAM_nWE ) +); + +mist_video #(.COLOR_DEPTH(5),.SD_HCNT_WIDTH(10)) mist_video( + .clk_sys(clk_72), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn ? r : 5'd0), + .G(blankn ? g : 5'd0), + .B(blankn ? b : 5'd0), + .HSync(~hs), + .VSync(~vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .no_csync(no_csync), + .rotate({~flipped,rotate}), + .ce_divider(3'd5), // pix clock = 72/6 + .blend(blend), + .scandoubler_disable(scandoublerD), + .scanlines(scanlines), + .ypbpr(ypbpr) + ); + +dac #(16) dacl( + .clk_i(clk_72), + .res_n_i(1), + .dac_i({~laudio[15], laudio[14:0]}), + .dac_o(AUDIO_L) + ); + +dac #(16) dacr( + .clk_i(clk_72), + .res_n_i(1), + .dac_i({~raudio[15], raudio[14:0]}), + .dac_o(AUDIO_R) + ); + +// Common inputs +wire m_up1, m_down1, m_left1, m_right1, m_up1B, m_down1B, m_left1B, m_right1B; +wire m_up2, m_down2, m_left2, m_right2, m_up2B, m_down2B, m_left2B, m_right2B; +wire m_up3, m_down3, m_left3, m_right3, m_up3B, m_down3B, m_left3B, m_right3B; +wire m_up4, m_down4, m_left4, m_right4, m_up4B, m_down4B, m_left4B, m_right4B; +wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players; +wire [11:0] m_fire1, m_fire2, m_fire3, m_fire4; + +arcade_inputs inputs ( + .clk ( clk_72 ), + .key_strobe ( key_strobe ), + .key_pressed ( key_pressed ), + .key_code ( key_code ), + .joystick_0 ( joystick_0 ), + .joystick_1 ( joystick_1 ), + .rotate ( rotate ), + .orientation ( {~flipped, 1'b0} ), + .joyswap ( joyswap ), + .oneplayer ( 1'b0 ), + .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ), + .player1 ( {m_up1B, m_down1B, m_left1B, m_right1B, m_fire1, m_up1, m_down1, m_left1, m_right1} ), + .player2 ( {m_up2B, m_down2B, m_left2B, m_right2B, m_fire2, m_up2, m_down2, m_left2, m_right2} ), + .player3 ( {m_up3B, m_down3B, m_left3B, m_right3B, m_fire3, m_up3, m_down3, m_left3, m_right3} ), + .player4 ( {m_up4B, m_down4B, m_left4B, m_right4B, m_fire4, m_up4, m_down4, m_left4, m_right4} ) +); + +endmodule diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_zerowing/zerowing0.sv b/Arcade_MiST/Toaplan v1 Hardware/rtl/ToaplanV1_Top.sv similarity index 64% rename from Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_zerowing/zerowing0.sv rename to Arcade_MiST/Toaplan v1 Hardware/rtl/ToaplanV1_Top.sv index 2fba241f..e3c511e2 100644 --- a/Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_zerowing/zerowing0.sv +++ b/Arcade_MiST/Toaplan v1 Hardware/rtl/ToaplanV1_Top.sv @@ -1,136 +1,57 @@ -//============================================================================ -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -// -//============================================================================ - -`default_nettype none - -module emu -( - //Master input clock - input CLK_50M, - - //Async reset from top-level module. - //Can be used as initial reset. - input RESET, - - //Must be passed to hps_io module - inout [48:0] HPS_BUS, - - //Base video clock. Usually equals to CLK_SYS. - output CLK_VIDEO, - - //Multiple resolutions are supported using different CE_PIXEL rates. - //Must be based on CLK_VIDEO - output CE_PIXEL, - - //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. - //if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio. - output [12:0] VIDEO_ARX, - output [12:0] VIDEO_ARY, - - output [7:0] VGA_R, - output [7:0] VGA_G, - output [7:0] VGA_B, - output VGA_HS, - output VGA_VS, - output VGA_DE, // = ~(VBlank | HBlank) - output VGA_F1, - output [2:0] VGA_SL, - output VGA_SCALER, // Force VGA scaler - - input [11:0] HDMI_WIDTH, - input [11:0] HDMI_HEIGHT, - output HDMI_FREEZE, - -`ifdef MISTER_FB - // Use framebuffer in DDRAM (USE_FB=1 in qsf) - // FB_FORMAT: - // [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp - // [3] : 0=16bits 565 1=16bits 1555 - // [4] : 0=RGB 1=BGR (for 16/24/32 modes) - // - // FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes) - output FB_EN, - output [4:0] FB_FORMAT, - output [11:0] FB_WIDTH, - output [11:0] FB_HEIGHT, - output [31:0] FB_BASE, - output [13:0] FB_STRIDE, - input FB_VBL, - input FB_LL, - output FB_FORCE_BLANK, - -`ifdef MISTER_FB_PALETTE - // Palette control for 8bit modes. - // Ignored for other video modes. - output FB_PAL_CLK, - output [7:0] FB_PAL_ADDR, - output [23:0] FB_PAL_DOUT, - input [23:0] FB_PAL_DIN, - output FB_PAL_WR, -`endif -`endif - - output LED_USER, // 1 - ON, 0 - OFF. - - // b[1]: 0 - LED status is system status OR'd with b[0] - // 1 - LED status is controled solely by b[0] - // hint: supply 2'b00 to let the system control the LED. - output [1:0] LED_POWER, - output [1:0] LED_DISK, - - // I/O board button press simulation (active high) - // b[1]: user button - // b[0]: osd button - output [1:0] BUTTONS, - - //Audio - input CLK_AUDIO, // 24.576 MHz - output [15:0] AUDIO_L, - output [15:0] AUDIO_R, - output AUDIO_S, // 1 - signed audio samples, 0 - unsigned - output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono) - - //ADC - inout [3:0] ADC_BUS, - - //SD-SPI - output SD_SCK, - output SD_MOSI, - input SD_MISO, - output SD_CS, - input SD_CD, - - //High latency DDR3 RAM interface - //Use for non-critical time purposes - output DDRAM_CLK, - input DDRAM_BUSY, - output [7:0] DDRAM_BURSTCNT, - output [28:0] DDRAM_ADDR, - input [63:0] DDRAM_DOUT, - input DDRAM_DOUT_READY, - output DDRAM_RD, - output [63:0] DDRAM_DIN, - output [7:0] DDRAM_BE, - output DDRAM_WE, - - //SDRAM interface with lower latency - output SDRAM_CLK, - output SDRAM_CKE, +module ToaplanV1_Top( + input clk_sys, + input pll_locked, + input turbo_68k,//cpu_turbo + input reset, + input [6:0] core_mod, + input pause_cpu, +//------------------------------------ + input scrollDBG, + input p1_right, + input p1_left, + input p1_down, + input p1_up, + input [3:0] p1_buttons, + input p2_right, + input p2_left, + input p2_down, + input p2_up, + input [3:0] p2_buttons, + input start1, + input start2, + input coin_a, + input coin_b, + input b_pause, + input service, + input key_tilt, + input key_service, + input [7:0] sw0, + input [7:0] sw1, + input [7:0] sw2, +//------------------------------------ + output hsync, + output vsync, + output hblank, + output vblank, + input [3:0] hs_offset, + input [3:0] vs_offset, + input [3:0] hs_width, + input [3:0] vs_width, + input refresh_mod, + output [4:0] r, + output [4:0] g, + output [4:0] b, + input ntsc, + input [1:0] opl2_level, +//------------------------------------ + output [15:0] audio_l, + output [15:0] audio_r, +//------------------------------------ + input ioctl_download, + input ioctl_index, + input [23:0] ioctl_addr, + input ioctl_wr, + input [7:0] ioctl_dout, output [12:0] SDRAM_A, output [1:0] SDRAM_BA, inout [15:0] SDRAM_DQ, @@ -139,214 +60,17 @@ module emu output SDRAM_nCS, output SDRAM_nCAS, output SDRAM_nRAS, - output SDRAM_nWE, - -`ifdef MISTER_DUAL_SDRAM - //Secondary SDRAM - //Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0 - input SDRAM2_EN, - output SDRAM2_CLK, - output [12:0] SDRAM2_A, - output [1:0] SDRAM2_BA, - inout [15:0] SDRAM2_DQ, - output SDRAM2_nCS, - output SDRAM2_nCAS, - output SDRAM2_nRAS, - output SDRAM2_nWE, -`endif - - input UART_CTS, - output UART_RTS, - input UART_RXD, - output UART_TXD, - output UART_DTR, - input UART_DSR, - -`ifdef MISTER_ENABLE_YC - output [39:0] CHROMA_PHASE_INC, - output YC_EN, - output PALFLAG, -`endif - - // Open-drain User port. - // 0 - D+/RX - // 1 - D-/TX - // 2..6 - USR2..USR6 - // Set USER_OUT to 1 to read from USER_IN. - input [6:0] USER_IN, - output [6:0] USER_OUT, - - input OSD_STATUS + output SDRAM_nWE ); -///////// Default values for ports not used in this core ///////// - -assign ADC_BUS = 'Z; -assign USER_OUT = 0; -assign {UART_RTS, UART_TXD, UART_DTR} = 0; -assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; -//assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z; -//assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0; -assign VGA_F1 = 0; -assign VGA_SCALER = 0; -assign HDMI_FREEZE = 0; - -assign AUDIO_MIX = 0; -assign LED_USER = ioctl_download & cpu_a[0]; -assign LED_DISK = 0; -assign LED_POWER = 0; -assign BUTTONS = 0; - -// Status Bit Map: -// Upper Case Lower Case -// 0 1 2 3 4 5 6 -// 01234567890123456789012345678901 23456789012345678901234567890123 -// 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV -// X XXXXXXXXXXX X X XXXXXXXX XX XX XXXXXXXX - -wire [1:0] aspect_ratio = status[9:8]; -wire orientation = ~status[3]; -wire [2:0] scan_lines = status[6:4]; -reg refresh_mod; -reg new_vmode; - -always @(posedge clk_sys) begin - if (refresh_mod != status[19]) begin - refresh_mod <= status[19]; - new_vmode <= ~new_vmode; - end -end - -wire [3:0] hs_offset = status[27:24]; -wire [3:0] vs_offset = status[31:28]; -wire [3:0] hs_width = status[59:56]; -wire [3:0] vs_width = status[63:60]; - -assign VIDEO_ARX = (!aspect_ratio) ? (orientation ? 8'd4 : 8'd3) : (aspect_ratio - 1'd1); -assign VIDEO_ARY = (!aspect_ratio) ? (orientation ? 8'd3 : 8'd4) : 12'd0; - -`include "build_id.v" -localparam CONF_STR = { - "Toaplan V1;;", - "-;", - "P1,Video Settings;", - "P1-;", - "P1O89,Aspect Ratio,Original,Full Screen,[ARC1],[ARC2];", - "P1O3,Orientation,Horz,Vert;", - "P1-;", - "P1O46,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%,CRT 100%;", - "P1OA,Force Scandoubler,Off,On;", - "P1-;", - "P1O7,Video Mode,NTSC,PAL;", - "P1OM,Video Signal,RGBS/YPbPr,Y/C;", - "P1OJ,Refresh Rate,Native,NTSC;", - "P1-;", - "P1OOR,H-sync Pos Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", - "P1OSV,V-sync Pos Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", - "P1-;", - "P1oOR,H-sync Width Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", - "P1oSV,V-sync Width Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", - "P1-;", - "P2,Audio Settings;", - "P2-;", - "P2oBC,OPL2 Volume,Default,50%,25%,0%;", - "P2-;", - "-;", - "P3,Core Options;", - "P3-;", - "P3o6,Swap P1/P2 Joystick,Off,On;", - "P3-;", - "P3OF,68k Freq.,10Mhz,17.5MHz;", - "P3-;", - "P3o0,Scroll Debug,Off,On;", - "P3-;", - "DIP;", - "-;", - "OK,Pause OSD,Off,When Open;", - "OL,Dim Video,Off,10s;", - "-;", - "R0,Reset;", - "V,v",`BUILD_DATE -}; - -wire hps_forced_scandoubler; -wire forced_scandoubler = hps_forced_scandoubler | status[10]; - -wire [1:0] buttons; -wire [63:0] status; -wire [10:0] ps2_key; -wire [15:0] joy0, joy1; - -hps_io #(.CONF_STR(CONF_STR)) hps_io -( - .clk_sys(clk_sys), - .HPS_BUS(HPS_BUS), - - .buttons(buttons), - .ps2_key(ps2_key), - .status(status), - .status_menumask(direct_video), - .forced_scandoubler(hps_forced_scandoubler), - .gamma_bus(gamma_bus), - .new_vmode(new_vmode), - .direct_video(direct_video), - .video_rotated(video_rotated), - - .ioctl_download(ioctl_download), - .ioctl_upload(ioctl_upload), - .ioctl_wr(ioctl_wr), - .ioctl_addr(ioctl_addr), - .ioctl_dout(ioctl_dout), - .ioctl_din(ioctl_din), - .ioctl_index(ioctl_index), - .ioctl_wait(ioctl_wait), - - .joystick_0(joy0), - .joystick_1(joy1) -); - -// INPUT - -// 8 dip switches of 8 bits -reg [7:0] sw[8]; -always @(posedge clk_sys) begin - if (ioctl_wr && (ioctl_index==254) && !ioctl_addr[24:3]) begin - sw[ioctl_addr[2:0]] <= ioctl_dout; - end -end - -always @(posedge clk_sys) begin - if (ioctl_wr && ioctl_index==1) begin - pcb <= ioctl_dout; - end -end - -wire direct_video; - -wire ioctl_download; -wire ioctl_upload; -wire ioctl_upload_req; -wire ioctl_wait; -wire ioctl_wr; -wire [15:0] ioctl_index; -wire [26:0] ioctl_addr; -wire [15:0] ioctl_dout; -wire [15:0] ioctl_din; - -reg [3:0] pcb; -wire tile_priority_type; +//// INPUT +// +// +// +//wire tile_priority_type; wire [15:0] scroll_y_offset; +wire [15:0] scroll_x_offset = 30; -localparam pcb_zero_wing = 0; -localparam pcb_out_zone_conv = 1; -localparam pcb_out_zone = 2; -localparam pcb_hellfire = 3; -localparam pcb_truxton = 4; - -wire [21:0] gamma_bus; - -// -// Inputs tied to z80_din reg [7:0] p1; reg [7:0] p2; reg [7:0] z80_dswa; @@ -354,155 +78,57 @@ reg [7:0] z80_dswb; reg [7:0] z80_tjump; reg [7:0] system; -always @ ( posedge clk_sys ) begin - p1 <= { 1'b0, p1_buttons[2:0], p1_right, p1_left, p1_down, p1_up }; - p2 <= { 1'b0, p2_buttons[2:0], p2_right, p2_left, p2_down, p2_up }; - z80_tjump <= sw[2]; +always @ (posedge clk_sys ) begin + p1 <= { 1'b0, p1_buttons[2:0], p1_right, p1_left, p1_down, p1_up }; + p2 <= { 1'b0, p2_buttons[2:0], p2_right, p2_left, p2_down, p2_up }; +case (core_mod) + 0,1: begin + z80_dswa <= sw0; + z80_dswb <= sw1; + z80_tjump <= sw2; + if ( scrollDBG == 1 ) begin + system <= { vblank, start2 | p1_buttons[3], start1 | p1_buttons[3], coin_b, coin_a, service | scrollDBG, key_tilt, key_service }; + end else begin + system <= { vblank, start2, start1, coin_b, coin_a, service, key_tilt, key_service }; + end + end + 2,3: begin - if ( pcb == 0 || pcb == 1 || pcb == 2 || pcb == 3 && status[32] == 1 ) begin + z80_dswa <= sw0; + z80_tjump <= sw2; + if ( scrollDBG == 1 ) begin + z80_dswb <= { sw1[7], sw1[6] | scrollDBG, sw1[5:0] }; + system <= { vblank, start2 | p1_buttons[3], start1 | p1_buttons[3], coin_b, coin_a, service, key_tilt, key_service }; + end else begin + z80_dswb <= sw1; + system <= { vblank, start2, start1, coin_b, coin_a, service, key_tilt, key_service }; + end + end + 4,5,6,7,8: begin + z80_tjump <= sw2; + if ( core_mod == 4 || core_mod == 6 || core_mod == 7 || core_mod == 8 && scrollDBG == 1 ) begin // zerowing, hellfire, outzone, outzone conversion debug options - z80_dswa <= sw[0]; - z80_dswb <= { sw[1][7], sw[1][6] | status[32], sw[1][5:0] }; - system <= { vbl, start2 | p1_buttons[3], start1 | p1_buttons[3], coin_b, coin_a, service, key_tilt, key_service }; - end else if ( pcb == 4 && status[32] == 1 ) begin + z80_dswa <= sw0; + z80_dswb <= { sw1[7], sw1[6] | scrollDBG, sw1[5:0] }; + system <= { vblank, start2 | p1_buttons[3], start1 | p1_buttons[3], coin_b, coin_a, service, key_tilt, key_service }; + end else if ( core_mod == 5 && scrollDBG == 1 ) begin // truxton debug options - z80_dswa <= { sw[0][7:3], sw[0][2] | status[32], sw[0][1:0] }; - z80_dswb <= sw[1]; - system <= { vbl, start2, start1, coin_b, coin_a, service, key_tilt, key_service }; - end else begin + z80_dswa <= { sw0[7:3], sw0[2] | scrollDBG, sw0[1:0] }; + z80_dswb <= sw1; + system <= { vblank, start2, start1, coin_b, coin_a, service, key_tilt, key_service }; + end else begin // default - z80_dswa <= sw[0]; - z80_dswb <= sw[1]; - system <= { vbl, start2, start1, coin_b, coin_a, service, key_tilt, key_service }; - end + z80_dswa <= sw0; + z80_dswb <= sw1; + system <= { vblank, start2, start1, coin_b, coin_a, service, key_tilt, key_service }; + end + end +endcase + end -reg p1_swap; -reg p1_right; -reg p1_left; -reg p1_down; -reg p1_up; -reg [3:0] p1_buttons; - -reg p2_right; -reg p2_left; -reg p2_down; -reg p2_up; -reg [3:0] p2_buttons; - -reg start1; -reg start2; -reg coin_a; -reg coin_b; -reg b_pause; -reg service; - -always @ * begin - p1_swap <= status[38]; - - if ( status[38] == 0 ) begin - p1_right <= joy0[0] | key_p1_right; - p1_left <= joy0[1] | key_p1_left; - p1_down <= joy0[2] | key_p1_down; - p1_up <= joy0[3] | key_p1_up; - p1_buttons <= joy0[7:4] | {key_p1_c, key_p1_b, key_p1_a}; - - p2_right <= joy1[0] | key_p2_right; - p2_left <= joy1[1] | key_p2_left; - p2_down <= joy1[2] | key_p2_down; - p2_up <= joy1[3] | key_p2_up; - p2_buttons <= joy1[7:4] | {key_p2_c, key_p2_b, key_p2_a}; - end else begin - p2_right <= joy0[0] | key_p1_right; - p2_left <= joy0[1] | key_p1_left; - p2_down <= joy0[2] | key_p1_down; - p2_up <= joy0[3] | key_p1_up; - p2_buttons <= joy0[7:4] | {key_p1_c, key_p1_b, key_p1_a}; - - p1_right <= joy1[0] | key_p2_right; - p1_left <= joy1[1] | key_p2_left; - p1_down <= joy1[2] | key_p2_down; - p1_up <= joy1[3] | key_p2_up; - p1_buttons <= joy1[7:4] | {key_p2_c, key_p2_b, key_p2_a}; - end -end - -always @ * begin - start1 <= joy0[8] | joy1[8] | key_start_1p; - start2 <= joy0[9] | joy1[9] | key_start_2p; - - coin_a <= joy0[10] | joy1[10] | key_coin_a; - coin_b <= joy0[11] | joy1[11] | key_coin_b; - - b_pause <= joy0[12] | key_pause; - service <= key_test; -end - -// Keyboard handler - -reg key_start_1p, key_start_2p, key_coin_a, key_coin_b; -reg key_tilt, key_test, key_reset, key_service, key_pause; - -reg key_p1_up, key_p1_left, key_p1_down, key_p1_right, key_p1_a, key_p1_b, key_p1_c; -reg key_p2_up, key_p2_left, key_p2_down, key_p2_right, key_p2_a, key_p2_b, key_p2_c; - -wire pressed = ps2_key[9]; - -always @(posedge clk_sys) begin - reg old_state; - old_state <= ps2_key[10]; - if ( old_state ^ ps2_key[10] ) begin - casex ( ps2_key[8:0] ) - 'h016 : key_start_1p <= pressed; // 1 - 'h01E : key_start_2p <= pressed; // 2 - 'h02E : key_coin_a <= pressed; // 5 - 'h036 : key_coin_b <= pressed; // 6 - 'h006 : key_test <= key_test ^ pressed; // f2 - 'h004 : key_reset <= pressed; // f3 - 'h046 : key_service <= pressed; // 9 - 'h02C : key_tilt <= pressed; // t - 'h04D : key_pause <= pressed; // p - - 'h175 : key_p1_up <= pressed; // up - 'h172 : key_p1_down <= pressed; // down - 'h16B : key_p1_left <= pressed; // left - 'h174 : key_p1_right <= pressed; // right - 'h014 : key_p1_a <= pressed; // lctrl - 'h011 : key_p1_b <= pressed; // lalt - 'h029 : key_p1_c <= pressed; // spacebar - - 'h02D : key_p2_up <= pressed; // r - 'h02B : key_p2_down <= pressed; // f - 'h023 : key_p2_left <= pressed; // d - 'h034 : key_p2_right <= pressed; // g - 'h01C : key_p2_a <= pressed; // a - 'h01B : key_p2_b <= pressed; // s - 'h015 : key_p2_c <= pressed; // q - endcase - end -end - -wire pll_locked; - -wire clk_sys; -wire turbo_68k = status[15]; -reg clk_3_5M, clk_7M, clk_10M, clk_14M; - -wire clk_70M; - -pll pll -( - .refclk(CLK_50M), - .rst(0), - .outclk_0(clk_sys), - .outclk_1(clk_70M), - .locked(pll_locked) -); - -assign SDRAM_CLK = clk_70M; - -localparam CLKSYS=70; +reg clk_3_5M, clk_7M, clk_10M, clk_14M, clk_14M_N; reg [5:0] clk14_count; reg [5:0] clk10_count; @@ -540,6 +166,7 @@ always @ (posedge clk_sys ) begin clk7_count <= clk7_count + 1; end clk_14M <= ( clk14_count == 0); + clk_14M_N <= ( clk14_count == 2); if ( clk14_count == 4 ) begin clk14_count <= 0; end else begin @@ -553,30 +180,15 @@ always @ (posedge clk_sys ) begin end end -wire reset; -assign reset = RESET | status[0] | (ioctl_download & !ioctl_index) | buttons[1] | key_reset; - -////////////////////////////////////////////////////////////////// -wire rotate_ccw = 1; -wire no_rotate = orientation | direct_video; -wire video_rotated; - -reg [23:0] rgb; - -wire hbl; -wire vbl; - wire [8:0] hc; wire [8:0] vc; -wire hsync; -wire vsync; reg hbl_delay, vbl_delay; always @ ( posedge clk_7M ) begin - hbl_delay <= hbl; - vbl_delay <= vbl; + hbl_delay <= hblank; + vbl_delay <= vblank; end video_timing video_timing ( @@ -593,73 +205,12 @@ video_timing video_timing ( .refresh_mod(refresh_mod), .hc(hc), .vc(vc), - .hbl_delay(hbl), - .vbl(vbl), + .hbl_delay(hblank), + .vbl(vblank), .hsync(hsync), .vsync(vsync) ); -// PAUSE SYSTEM -wire pause_cpu; -wire hs_pause; - -// 8 bits per colour, 70MHz sys clk -pause #(8,8,8,70) pause -( - .clk_sys(clk_sys), - .reset(reset), - .user_button(b_pause), - .pause_request(hs_pause), - .options(status[21:20]), - .pause_cpu(pause_cpu), - .dim_video(dim_video), - .OSD_STATUS(OSD_STATUS), - .r(rgb[23:16]), - .g(rgb[15:8]), - .b(rgb[7:0]), - .rgb_out(rgb_pause_out) -); - -wire [23:0] rgb_pause_out; -wire dim_video; - -arcade_video #(320,24) arcade_video -( - .*, - - .clk_video(clk_sys), - .ce_pix(clk_7M), - - .RGB_in(rgb_pause_out), - - .HBlank(hbl), - .VBlank(vbl), - .HSync(hsync), - .VSync(vsync), - - .fx(scan_lines) -); - -/* - Phase Accumulator Increments (Fractional Size 32, look up size 8 bit, total 40 bits) - Increment Calculation - (Output Clock * 2 ^ Word Size) / Reference Clock - Example - NTSC = 3.579545 - PAL = 4.43361875 - W = 40 ( 32 bit fraction, 8 bit look up reference) - Ref CLK = 42.954544 (This could us any clock) - NTSC_Inc = 3.579545333 * 2 ^ 40 / 96 = 40997413706 -*/ - -// SET PAL and NTSC TIMING -`ifdef MISTER_ENABLE_YC - assign CHROMA_PHASE_INC = PALFLAG ? 40'd56225080500: 40'd56225080500; - assign YC_EN = status[22]; - assign PALFLAG = status[7]; -`endif - -screen_rotate screen_rotate (.*); - wire [9:0] sprite_adj_x = 0; wire [9:0] sprite_adj_y = 0; wire bcu_flip_cs; @@ -670,7 +221,6 @@ reg [15:0] scroll_adj_x [3:0]; reg [15:0] scroll_adj_y [3:0]; reg layer_en [3:0]; -reg ce_pix; // flip is done in the rendering so leave screen_rotate flip off wire flip = 0; @@ -753,7 +303,7 @@ fx68k fx68k ( .BERRn(1'b1), .BRn(1'b1), .BGACKn(1'b1), - + .IPL0n(1'b1), .IPL1n(1'b1), .IPL2n(ipl2_n), @@ -769,7 +319,6 @@ always @ (posedge clk_sys) begin // tell 68k to wait for valid data. 0=ready 1=wait // always ack when it's not program rom dtack_n <= prog_rom_cs ? !prog_rom_data_valid : 0; - // add dsp_ctrl_cs to cpu_din // select cpu data input based on what is active cpu_din <= prog_rom_cs ? prog_rom_data : ram_cs ? ram_dout : @@ -785,13 +334,63 @@ always @ (posedge clk_sys) begin sprite_2_cs ? sprite_2_dout : sprite_3_cs ? sprite_3_dout : sprite_size_cs ? sprite_size_cpu_dout : - frame_done_cs ? { 16 { vbl } } : // get vblank state - vblank_cs ? { 15'b0, vbl } : + frame_done_cs ? { 16 { vblank } } : // get vblank state + vblank_cs ? { 15'b0, vblank } : int_en_cs ? 16'hffff : 16'd0; end end +wire tms_reset; +reg [7:0] tms_reset_count; + +always @ (posedge clk_sys) begin + if ( reset == 1 ) begin + tms_reset_count <= 0; + tms_reset <= 1 ; + end else begin + if ( tms_reset_count < 50 ) begin + tms_reset_count <= tms_reset_count + 1; + end else begin + tms_reset <= 0 ; + end + end +end + +TMS320C1X dsp +( + .CLK(clk_sys), // (X2/CLKIN) Crystal input internal oscillator or external system clock input + .RST_N(~reset), + .EN(1), // (DEN) Data enable for device input data on D15-D0 + + .CE_F(clk_14M), // Phased clocks for chip enable + .CE_R(clk_14M_N), // Chip enable clock phase + + .RS_N(~tms_reset), // (RS) Reset for initializing the device + .INT_N(tms_int_n), // (INT) External interrupt input + .BIO_N(tms_bio), // (BIO) External polling input + + .A(tms_addr), + .DI(tms_din), + .DO(tms_dout), + + .PC(tms_rom_addr), // output reg [11:0] PC, + .ROM_Q(tms_rom_dout), // input [15:0] ROM_Q, + + .WE_N(tms_we_n), // (WE) Write enable for device output data on D15-D0 (OUT instruction) + .DEN_N(tms_den_n), // (DEN) Data enable for device input data on D15-D0 (IN instruction) + .MEN_N(tms_men_n) // (MEN) Memory enable indicates that D15-D0 will accept external memory instruction. (External instruction) +); + +wire [11:0] tms_addr ; +reg [15:0] tms_din ; +wire [15:0] tms_dout ; +wire tms_we_n; +wire tms_den_n; +wire tms_men_n; +wire tms_bio; +reg tms_int_n; + wire [15:0] cpu_shared_dout; wire [7:0] z80_shared_dout; reg [15:0] z80_a; @@ -864,7 +463,6 @@ wire opl_irq_n; reg signed [15:0] sample; -assign AUDIO_S = 1'b1; wire opl_sample_clk; @@ -883,8 +481,6 @@ jtopl #(.OPL_TYPE(2)) jtopl2 .sample(opl_sample_clk) ); -wire [1:0] opl2_level = status[44:43]; // opl2 audio mix - reg [7:0] opl2_mult; // set the multiplier for each channel from menu @@ -924,17 +520,18 @@ jtframe_mixer #(.W0(16), .WOUT(16)) u_mix_mono( always @ (posedge clk_sys ) begin if ( pause_cpu == 1 ) begin - AUDIO_L <= 0; - AUDIO_R <= 0; + audio_l <= 0; + audio_r <= 0; end else if ( pause_cpu == 0 ) begin // mix audio - AUDIO_L <= mono; - AUDIO_R <= mono; + audio_l <= {mono[15:0]}; + audio_r <= {mono[15:0]}; end end + T80pa u_cpu( - .RESET_n ( reset_n ), + .RESET_n ( reset_n & reset_z80_n ), .CLK ( clk_sys ), .CEN_p ( clk_3_5M ), .CEN_n ( ~clk_3_5M ), @@ -983,6 +580,14 @@ wire sprite_cs; // *** offset needs to be auto-incremented wire sprite_size_cs; // *** offset needs to be auto-incremented wire sprite_ram_cs; +wire dsp_ctrl_cs; +wire dsp_addr_cs; +wire dsp_r_cs; +wire dsp_bio_cs; + +//TMS32010 mapping may not be necessary here or the chipselect +//wire dsp_rom_1_cs; // map(0x000, 0x7ff).rom(); + wire z80_p1_cs; wire z80_p2_cs; wire z80_dswa_cs; @@ -1015,7 +620,8 @@ always @ (posedge clk_sys ) begin ipl2_n <= 1; int_ack <= 0; end else begin - vbl_sr <= { vbl_sr[0], vbl }; + vbl_sr <= { vbl_sr[0], vblank }; + // vbl_sr <= { vbl_sr[0], ( vc == 224 ) }; if ( clk_10M == 1 ) begin int_ack <= ( cpu_as_n == 0 ) && ( cpu_fc == 3'b111 ); // cpu acknowledged the interrupt end @@ -1040,39 +646,71 @@ reg [15:0] crtc[4]; always @ (posedge clk_sys) begin if ( reset == 1 ) begin int_en <= 0; - reset_z80_n <= 0; + reset_z80_n <= 1; + tms_int_n <= 1; + tms_bio <= 1 ; end else begin - if ( pcb != 3 && pcb != 4 ) begin - // if the pcb uses the 68k reset pin to drive the reset line - reset_z80_n <= cpu_reset_n_o; - end + // if the pcb uses the 68k reset pin to drive the reset line + //reset_z80_n <= cpu_reset_n_o; + +// if ( clk_14M == 1 ) begin +// shared_dsp_ram_w <= 0; +// if ( tms_we_n == 0 ) begin // tms port write + +// case ( tms_addr[2:0] ) +// 3'h0 : shared_dsp_ram_addr <= tms_dout[11:0] ; +// 3'h1 : begin +// shared_dsp_ram_din <= tms_dout ; +// shared_dsp_ram_w <= 1; +// end +// 3'h3 : begin +// if ( tms_dout[15] == 1 ) begin +// // clear +// tms_bio <= 1 ; +// end else if ( tms_dout == 0 ) begin +// // assert +// tms_bio <= 0 ; +// end +// end +// endcase +// end +// end + // write asserted and rising cpu clock if ( clk_10M == 1 && cpu_rw == 0 ) begin if ( tile_ofs_cs ) begin curr_tile_ofs <= cpu_dout; end + if ( int_en_cs ) begin int_en <= cpu_dout[0]; end + if ( crtc_cs ) begin crtc[ cpu_a[2:1] ] <= cpu_dout; end + if ( bcu_flip_cs ) begin tile_flip <= cpu_dout[0]; end + if ( fcu_flip_cs ) begin sprite_flip <= cpu_dout[15]; end + if ( sprite_ofs_cs ) begin // mask out valid range curr_sprite_ofs <= { 6'b0, cpu_dout[9:0] }; end + if ( scroll_ofs_x_cs ) begin scroll_ofs_x <= cpu_dout; end + if ( scroll_ofs_y_cs ) begin scroll_ofs_y <= cpu_dout; end + // x layer values are even addresses if ( scroll_cs ) begin if ( cpu_a[1] == 0 ) begin @@ -1081,15 +719,24 @@ always @ (posedge clk_sys) begin scroll_y[ cpu_a[3:2] ] <= cpu_dout[15:7]; end end + // offset needs to be auto-incremented if ( sprite_cs | sprite_size_cs ) begin inc_sprite_ofs <= 1; end + if ( reset_z80_cs ) begin // the pcb writes to a latch to control the reset reset_z80_n <= cpu_dout[0]; end + + if ( dsp_ctrl_cs ) begin + // set/clear dsp interrupt line + tms_int_n <= cpu_dout[0]; + end + end + // write lasts multiple cpu clocks so limit to one increment per write signal if ( inc_sprite_ofs == 1 && cpu_rw == 1 ) begin curr_sprite_ofs <= curr_sprite_ofs + 1; @@ -1098,6 +745,13 @@ always @ (posedge clk_sys) begin end end +reg dsp_int_en; + +//wire [15:0] shared_dsp_ram_dout ; +//reg [15:0] shared_dsp_ram_din ; +//reg [11:0] shared_dsp_ram_addr ; +//reg shared_dsp_ram_w ; + reg [15:0] scroll_x_total [3:0]; reg [15:0] scroll_y_total [3:0]; @@ -1177,8 +831,8 @@ dual_port_ram #(.LEN(1024), .DATA_WIDTH(16)) tile_line_buffer ( .wren_b ( 0 ), // .data_b ( ), .q_b ( tile_fb_out ) -); - + ); + dual_port_ram #(.LEN(1024), .DATA_WIDTH(16)) sprite_line_buffer ( .clock_a ( clk_sys ), .address_a ( sprite_fb_addr_w ), @@ -1191,13 +845,12 @@ dual_port_ram #(.LEN(1024), .DATA_WIDTH(16)) sprite_line_buffer ( .wren_b ( 0 ), // .data_b ( ), .q_b ( sprite_fb_out ) -); + ); reg [9:0] x_ofs; reg [9:0] x; reg [9:0] y_ofs; - // y needs to be one line ahaed of the visible line // render the first line at the end of the previous frame // this depends on the timing that the sprite list is valid @@ -1212,7 +865,7 @@ wire [9:0] y_ofs_dx_flipped = 255; // calculate scrolling wire [9:0] tile_x_unflipped = scroll_x_latch[layer[1:0]] + x_ofs_dx; wire [9:0] tile_y_unflipped = scroll_y_latch[layer[1:0]] + y_ofs_dx + scroll_y_offset; -wire [9:0] tile_x_flipped = 319 + scroll_x_latch[layer[1:0]] + x_ofs_dx_flipped; +wire [9:0] tile_x_flipped = 319 + scroll_x_latch[layer[1:0]] + x_ofs_dx_flipped; wire [9:0] tile_y_flipped = 239 + scroll_y_latch[layer[1:0]] + y_ofs_dx_flipped + scroll_y_offset; // reverse tiles when flipped @@ -1225,7 +878,6 @@ wire [9:0] sprite_buf_x = sprite_flip ? 320 - (sprite_x + sprite_pos_x ) : sprit reg [3:0] draw_state; reg [3:0] sprite_state; -reg [3:0] tile_copy_state; reg [3:0] sprite_copy_state; // pixel 4 bit colour @@ -1251,7 +903,7 @@ reg [31:0] tile_attr; // [3:0] = tile colour index. reg [3:0] tile_priority_buf [327:0]; -reg [3:0] sprite_priority_buf [327:0]; +reg [4:0] sprite_priority_buf [327:0]; reg [9:0] sprite_x; // offset from left side of sprite reg [9:0] sprite_y; @@ -1272,7 +924,7 @@ wire [8:0] sprite_width = { sprite_size_buf_dout[3:0], 3'b0 } /* synthesis k reg [7:0] sprite_buf_num; -reg [1:0] vtotal_282_flag; +reg [1:0] vtotal_282_flag; always @ (posedge clk_sys) begin // Check System Vcount flag for 60Hz mode if ({crtc[2][7:0], 1'b1 } == 269) @@ -1287,7 +939,6 @@ always @ (posedge clk_sys) begin draw_state <= 0; sprite_rom_cs <= 0; tile_rom_cs <= 0; - tile_copy_state <= 0; sprite_copy_state <= 0; tile_draw_state <= 0; end else begin @@ -1348,15 +999,10 @@ always @ (posedge clk_sys) begin end else if ( sprite_state == 7 ) begin sprite_fb_w <= 0; // draw if pixel value not zero and priority >= previous sprite data -// if ( sprite_pix > 0 && sprite_priority_buf[sprite_buf_x] == 0 ) begin -// if ( sprite_pix != 0 && ( sprite_priority == 0 || sprite_priority >= sprite_priority_buf[sprite_buf_x] ) ) begin - if ( sprite_pix != 0 ) begin - sprite_fb_din <= { 2'b11, sprite_priority, sprite_pal_addr, sprite_pix }; -// if ( sprite_priority == 0 ) begin -// sprite_priority_buf[sprite_buf_x] <= { 1'b1, sprite_priority }; -// end else begin + if ( sprite_pix != 0 ) begin + sprite_fb_din <= { 2'b11, sprite_priority[3:0], sprite_pal_addr, sprite_pix }; sprite_fb_addr_w <= { y[0], 9'b0 } + sprite_buf_x; - sprite_priority_buf[sprite_buf_x] <= sprite_priority; + sprite_priority_buf[sprite_buf_x] <= { 1'b0, sprite_priority }; sprite_fb_w <= 1; end if ( sprite_x < ( sprite_width - 1 ) ) begin @@ -1375,21 +1021,6 @@ always @ (posedge clk_sys) begin sprite_state <= 15; // done end end - // copy tile ram and scroll info - // not sure if this is needed. need to check to see when tile ram is updated. - if ( tile_copy_state == 0 && vc == 256 ) begin - tile_copy_state <= 1; - end else begin - // copy scroll registers - scroll_x_latch[0] <= scroll_x[0] - scroll_ofs_x; - scroll_x_latch[1] <= scroll_x[1] - scroll_ofs_x; - scroll_x_latch[2] <= scroll_x[2] - scroll_ofs_x; - scroll_x_latch[3] <= scroll_x[3] - scroll_ofs_x; - scroll_y_latch[0] <= scroll_y[0] - scroll_ofs_y; - scroll_y_latch[1] <= scroll_y[1] - scroll_ofs_y; - scroll_y_latch[2] <= scroll_y[2] - scroll_ofs_y; - scroll_y_latch[3] <= scroll_y[3] - scroll_ofs_y; - end // copy sprite attr/size to buffer if ( sprite_copy_state == 0 && vc == 240 ) begin sprite_copy_state <= 1; @@ -1408,7 +1039,15 @@ always @ (posedge clk_sys) begin sprite_copy_state <= 0; end // tile state machine - if ( draw_state == 0 && vc == ({ crtc[2][7:0], 1'b1 } - (status[19] ? (vtotal_282_flag ? 5'd19 : 4'd7) : 3'd0)) ) begin // 282 Lines standard (263 Lines for 60Hz) + if ( draw_state == 0 && vc == ({ crtc[2][7:0], 1'b1 } - (ntsc ? (vtotal_282_flag ? 5'd19 : 4'd7) : 3'd0)) ) begin // 282 Lines standard (263 Lines for 60Hz) + scroll_x_latch[0] <= scroll_x[0] - scroll_ofs_x; + scroll_x_latch[1] <= scroll_x[1] - scroll_ofs_x; + scroll_x_latch[2] <= scroll_x[2] - scroll_ofs_x; + scroll_x_latch[3] <= scroll_x[3] - scroll_ofs_x; + scroll_y_latch[0] <= scroll_y[0] - scroll_ofs_y; + scroll_y_latch[1] <= scroll_y[1] - scroll_ofs_y; + scroll_y_latch[2] <= scroll_y[2] - scroll_ofs_y; + scroll_y_latch[3] <= scroll_y[3] - scroll_ofs_y; layer <= 4; // layer 4 is layer 0 but draws hidden and transparent y <= 0; draw_state <= 2; @@ -1422,14 +1061,15 @@ always @ (posedge clk_sys) begin tile_draw_state <= 0; end else if ( draw_state == 3 ) begin if ( tile_draw_state == 0 ) begin - tile <= { layer[1:0], curr_y[8:3], curr_x[8:3] }; // works + tile <= { layer[1:0], curr_y[8:3], curr_x[8:3] }; // works tile_draw_state <= 4'h1; end else if ( tile_draw_state == 1 ) begin tile_draw_state <= 2; end else if ( tile_draw_state == 2 ) begin // latch attribute - tile_attr <= tile_attr_dout; - if ( layer == 4 || tile_attr_dout[15] == 0 ) begin + // tile_attr <= tile_attr_dout; + tile_attr <= tile_buf_dout ; + if ( layer == 4 || tile_buf_dout[15] == 0 ) begin tile_draw_state <= 3; end else begin if ( x < 320 ) begin// 319 @@ -1437,7 +1077,7 @@ always @ (posedge clk_sys) begin // do we need to read another tile? // last pixel of this tile changes based on flip direction if ( curr_x[2:0] == ( tile_flip ? 0 : 7) ) begin - draw_state <= 3; + draw_state <= 3; tile_draw_state <= 0; end x <= x + 1; @@ -1465,7 +1105,7 @@ always @ (posedge clk_sys) begin tile_rom_cs <= 0; end end else if ( tile_draw_state == 5 ) begin - tile_fb_w <= 0; + tile_fb_w <= 0; tile_fb_addr_w <= { y[0], 9'b0 } + x; // force render of first layer. // if layer == 4 then tile_pix == 0 is not transparent @@ -1475,7 +1115,8 @@ always @ (posedge clk_sys) begin //fb_din <= { layer[1:0], tile_priority, tile_palette_idx, tile_pix }; fb_din <= { layer[1:0], 4'b0, tile_palette_idx, tile_pix }; tile_fb_w <= 1; - end else if (tile_hidden == 0 && tile_pix > 0 && tile_priority > 0 && tile_priority >= tile_priority_buf[x] ) begin + //end else if (tile_hidden == 0 && tile_pix > 0 && tile_priority > 0 && tile_priority >= tile_priority_buf[x] ) begin + end else if (tile_hidden == 0 && tile_pix > 0 && tile_priority > tile_priority_buf[x] ) begin tile_priority_buf[x] <= tile_priority; // if tile hidden then make the pallette index 0. ie transparent fb_din <= { layer[1:0], tile_priority, tile_palette_idx, tile_pix }; @@ -1485,7 +1126,7 @@ always @ (posedge clk_sys) begin // do we need to read another tile? // last pixel of this tile changes based on flip direction if ( curr_x[2:0] == ( tile_flip ? 0 : 7) ) begin - draw_state <= 3; + draw_state <= 3; tile_draw_state <= 0; end x <= x + 1; @@ -1502,7 +1143,7 @@ always @ (posedge clk_sys) begin // wait for next line or quit if ( y == 239 ) begin draw_state <= 0; - end else if ( hc == (status[19] ? 9'd444 : 9'd449) ) begin // 450 Lines standard (445 Lines for NTSC standard 15.73kHz line freq) + end else if ( hc == (ntsc ? 9'd444 : 9'd449) ) begin // 450 Lines standard (445 Lines for NTSC standard 15.73kHz line freq) y <= y + 1; draw_state <= 2; sprite_state <= 0; @@ -1523,6 +1164,7 @@ reg draw_sprite; // [3:0] = tile colour index. // there are 10 70MHz cycles per pixel. clk7_count from 0-9 +// // dac values based on 120 ohm driver for the resistor dac and 75 ohm output. 4.7k, 2.2k, 1k, 470, 220 // modeled in spice @@ -1534,39 +1176,124 @@ always @ (posedge clk_sys) begin sprite_palette_addr <= sprite_fb_out[9:0]; end else if ( clk7_count == 6 ) begin // if palette index is zero then it's from layer 3 and is transparent render as blank (black). - rgb <= { dac[tile_palette_dout[4:0]], dac[tile_palette_dout[9:5]], dac[tile_palette_dout[14:10]] }; - + r <= dac[tile_palette_dout[4:0]]; + g <= dac[tile_palette_dout[9:5]]; + b <= dac[tile_palette_dout[14:10]]; // if not transparent and sprite is higher priority if ( sprite_fb_out[3:0] > 0 && (sprite_fb_out[13:10] > tile_fb_out[13:10]) ) begin // draw sprite - rgb <= { dac[sprite_palette_dout[4:0]], dac[sprite_palette_dout[9:5]], dac[sprite_palette_dout[14:10]] }; + r <= dac[sprite_palette_dout[4:0]]; + g <= dac[sprite_palette_dout[9:5]]; + b <= dac[sprite_palette_dout[14:10]]; end end end +reg download_en; +reg [15:0] download_index; +reg [11:0] download_addr; +reg [7:0] download_data; +reg download_wr; +wire download_wait; + +// download tms32010 internal rom +always @ (posedge clk_sys) begin + + download_en <= ioctl_download & (download_index == 0) ; + download_index <= ioctl_index ; + + if ( ioctl_addr >= 26'h208000 && ioctl_addr < 26'h209000 ) begin + // dsp rom is 16 bits wide + download_addr <= ioctl_addr[11:1] ; + tms_rom_w <= ioctl_wr & ioctl_addr[0]; + tms_rom_din[ { ~ioctl_addr[0], 3'b111 } -: 8 ] <= ioctl_dout ; + end +end + +reg tms_rom_w; +wire [11:0] tms_rom_addr ; +wire [15:0] tms_rom_din ; +wire [15:0] tms_rom_dout ; + +dual_port_ram #(.LEN(4096), .DATA_WIDTH(16)) dsp_rom +( + .clock_a( clk_sys ), // rom download. ioctl stuff. + .address_a( download_addr ), + .wren_a( tms_rom_w ), // + .data_a( tms_rom_din ), // 16 bit wide + .q_a( ), + + .clock_b( clk_14M ), // tms clock + .address_b( tms_rom_addr ), + .wren_b( 0 ), + .data_b( ), + .q_b( tms_rom_dout ) +); + +// // copy sprite attr/size to buffer +// if ( sprite_copy_state == 0 && vc == 240 ) begin +// sprite_copy_state <= 1; +// sprite_buf_w <= 0; +// sprite_num_copy <= 8'h00; +// end else if ( sprite_copy_state == 1 ) begin +// sprite_num_copy <= sprite_num_copy + 1; +// sprite_buf_num <= sprite_num_copy; +// sprite_buf_w <= 1; +// // wait for read from source +// if ( sprite_num_copy == 8'hff ) begin +// sprite_copy_state <= 2; +// end +// end else if ( sprite_copy_state == 2 ) begin +// sprite_buf_w <= 0; +// sprite_copy_state <= 0; +// end + // tile data buffer -reg tile_buf_w; -reg [31:0] tile_buf_din; -reg [31:0] tile_buf_dout; -reg [13:0] tile_buf_addr; +reg tile_buf_w; +reg [31:0] tile_buf_din; +reg [31:0] tile_buf_dout; +reg [13:0] tile_buf_count; +reg [13:0] tile_buf_addr; -dual_port_ram #(.LEN(16384), .DATA_WIDTH(32)) ram_tile_buf ( - .clock_a ( clk_sys ), - .address_a ( tile[13:0] ), - .wren_a ( tile_buf_w ), - .data_a ( tile_attr_dout ), +reg [2:0] tile_copy_state; - .clock_b ( clk_sys ), - .address_b ( tile[13:0] ), // only read the tile # for now - .wren_b ( 0 ), - .q_b ( tile_buf_dout ) +always @ (posedge clk_sys) begin + if ( vc < 240 ) begin + tile_buf_count <= 0; + tile_copy_state <= 0; + tile_buf_w <= 0; + end else if ( tile_copy_state == 0 ) begin + tile_buf_count <= tile_buf_count + 1; + + tile_buf_addr <= tile_buf_count ; + tile_buf_w <= 1 ; + + if ( &tile_buf_count ) begin + tile_copy_state <= 1; + end + end else if ( tile_copy_state == 1 ) begin + tile_buf_w <= 0; + end +end + +dual_port_ram #(.LEN(16384), .DATA_WIDTH(32)) ram_tile_buf +( + .clock_a( clk_sys ), + .address_a( tile_buf_addr ), + .wren_a( tile_buf_w ), + .data_a( tile_attr_dout ), + + .clock_b( clk_sys ), + .address_b( tile[13:0] ), // only read the tile # for now + .wren_b( 0 ), + .q_b( tile_buf_dout ) ); // tile attribute ram. each tile attribute is 2 16bit words // pppp ---- --cc cccc httt tttt tttt tttt = Tile number (0 - $7fff) // indirect access through offset register -dual_port_ram #(.LEN(16384), .DATA_WIDTH(16)) ram_tile_h ( +dual_port_ram #(.LEN(16384), .DATA_WIDTH(16)) tile_ram_h ( .clock_a ( clk_10M ), .address_a ( curr_tile_ofs ), .wren_a ( tile_attr_cs & !cpu_rw ), @@ -1577,9 +1304,9 @@ dual_port_ram #(.LEN(16384), .DATA_WIDTH(16)) ram_tile_h ( .address_b ( tile[13:0] ), // only read the tile # for now .wren_b ( 0 ), .q_b ( tile_attr_dout[31:16] ) -); - -dual_port_ram #(.LEN(16384), .DATA_WIDTH(16)) ram_tile_l ( + ); + +dual_port_ram #(.LEN(16384), .DATA_WIDTH(16)) tile_ram_l ( .clock_a ( clk_10M ), .address_a ( curr_tile_ofs ), .wren_a ( tile_num_cs & !cpu_rw ), @@ -1587,10 +1314,11 @@ dual_port_ram #(.LEN(16384), .DATA_WIDTH(16)) ram_tile_l ( .q_a ( cpu_tile_dout_num ), .clock_b ( clk_sys ), - .address_b ( tile[13:0] ), // only read the tile # for now +// .address_b ( tile[13:0] ), // only read the tile # for now + .address_b( tile_buf_count ), .wren_b ( 0 ), .q_b ( tile_attr_dout[15:0] ) -); + ); // sprite attribute ram. each tile attribute is 4 16bit words // indirect access through offset register @@ -1598,7 +1326,7 @@ dual_port_ram #(.LEN(16384), .DATA_WIDTH(16)) ram_tile_l ( dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_0 ( .clock_a ( clk_10M ), .address_a ( curr_sprite_ofs[9:2] ), - .wren_a ( sprite_0_cs & !cpu_rw), + .wren_a ( sprite_0_cs & !cpu_rw), .data_a ( cpu_dout ), .q_a ( sprite_0_dout ), @@ -1606,7 +1334,7 @@ dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_0 ( .address_b ( sprite_num_copy ), .wren_b ( 0 ), .q_b ( sprite_attr_0_dout[15:0] ) -); + ); dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_0_buf ( .clock_a ( clk_sys ), @@ -1619,7 +1347,7 @@ dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_0_buf ( .address_b ( sprite_num ), .wren_b ( 0 ), .q_b ( sprite_attr_0_buf_dout[15:0] ) -); + ); dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_1 ( .clock_a ( clk_10M ), @@ -1632,7 +1360,7 @@ dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_1 ( .address_b ( sprite_num_copy ), .wren_b ( 0 ), .q_b ( sprite_attr_1_dout[15:0] ) -); + ); dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_1_buf ( .clock_a ( clk_sys ), @@ -1645,7 +1373,7 @@ dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_1_buf ( .address_b ( sprite_num ), .wren_b ( 0 ), .q_b ( sprite_attr_1_buf_dout[15:0] ) -); + ); dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_2 ( .clock_a ( clk_10M ), @@ -1658,7 +1386,7 @@ dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_2 ( .address_b ( sprite_num_copy ), .wren_b ( 0 ), .q_b ( sprite_attr_2_dout[15:0] ) -); + ); dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_2_buf ( .clock_a ( clk_sys ), @@ -1671,7 +1399,7 @@ dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_2_buf ( .address_b ( sprite_num ), .wren_b ( 0 ), .q_b ( sprite_attr_2_buf_dout[15:0] ) -); + ); dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_3 ( .clock_a ( clk_10M ), @@ -1684,7 +1412,7 @@ dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_3 ( .address_b ( sprite_num_copy ), .wren_b ( 0 ), .q_b ( sprite_attr_3_dout[15:0] ) -); + ); dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_3_buf ( .clock_a ( clk_sys ), @@ -1697,12 +1425,12 @@ dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_3_buf ( .address_b ( sprite_num ), .wren_b ( 0 ), .q_b ( sprite_attr_3_buf_dout[15:0] ) -); + ); dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_size ( .clock_a ( clk_10M ), .address_a ( curr_sprite_ofs ), - .wren_a ( sprite_size_cs & !cpu_rw), + .wren_a ( sprite_size_cs & !cpu_rw), .data_a ( cpu_dout ), .q_a ( sprite_size_cpu_dout ), @@ -1710,7 +1438,7 @@ dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_size ( .address_b ( sprite_num_copy ), .wren_b ( 0 ), .q_b ( sprite_size_dout ) -); + ); dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_size_buf ( .clock_a ( clk_sys ), @@ -1723,7 +1451,8 @@ dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_size_buf ( .address_b ( sprite_size_addr ), .wren_b ( 0 ), .q_b ( sprite_size_buf_dout ) -); + + ); // tiles 1024 15 bit values. index is ( 6 bits from tile attribute, 4 bits from bitmap ) @@ -1733,28 +1462,28 @@ dual_port_ram #(.LEN(1024), .DATA_WIDTH(8)) tile_palram_l ( .clock_a ( clk_10M ), .address_a ( cpu_a[10:1] ), .wren_a ( tile_palette_cs & !cpu_rw & !cpu_lds_n), - .data_a ( cpu_dout[7:0] ), + .data_a ( cpu_dout[7:0] ), .q_a ( tile_palette_cpu_dout[7:0] ), .clock_b ( clk_sys ), .address_b ( tile_palette_addr ), .wren_b ( 0 ), .q_b ( tile_palette_dout[7:0] ) -); + ); // background palette ram high dual_port_ram #(.LEN(1024), .DATA_WIDTH(8)) tile_palram_h ( .clock_a ( clk_10M ), .address_a ( cpu_a[10:1] ), .wren_a ( tile_palette_cs & !cpu_rw & !cpu_uds_n), - .data_a ( cpu_dout[15:8] ), + .data_a ( cpu_dout[15:8] ), .q_a ( tile_palette_cpu_dout[15:8] ), .clock_b ( clk_sys ), .address_b ( tile_palette_addr ), .wren_b ( 0 ), .q_b ( tile_palette_dout[15:8] ) -); + ); // sprite palette ram low // does this need to be byte addressable? @@ -1762,47 +1491,66 @@ dual_port_ram #(.LEN(1024), .DATA_WIDTH(8)) sprite_palram_l ( .clock_a ( clk_10M ), .address_a ( cpu_a[10:1] ), .wren_a ( sprite_palette_cs & !cpu_rw & !cpu_lds_n), - .data_a ( cpu_dout[7:0] ), + .data_a ( cpu_dout[7:0] ), .q_a ( sprite_palette_cpu_dout[7:0] ), .clock_b ( clk_sys ), .address_b ( sprite_palette_addr ), .wren_b ( 0 ), .q_b ( sprite_palette_dout[7:0] ) -); + ); // background palette ram high dual_port_ram #(.LEN(1024), .DATA_WIDTH(8)) sprite_palram_h ( .clock_a ( clk_10M ), .address_a ( cpu_a[10:1] ), .wren_a ( sprite_palette_cs & !cpu_rw & !cpu_uds_n), - .data_a ( cpu_dout[15:8] ), + .data_a ( cpu_dout[15:8] ), .q_a ( sprite_palette_cpu_dout[15:8] ), .clock_b ( clk_sys ), .address_b ( sprite_palette_addr ), .wren_b ( 0 ), .q_b ( sprite_palette_dout[15:8] ) -); - - -// main 68k ram low -dual_port_ram #(.LEN(16384), .DATA_WIDTH(8)) ram16kx8_L ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[14:1] ), - .wren_a ( !cpu_rw & ram_cs & !cpu_lds_n ), - .data_a ( cpu_dout[7:0] ), - .q_a ( ram_dout[7:0] ) ); +wire [15:0] shared_dsp_ram_dout ; +reg [15:0] shared_dsp_ram_din ; +reg [11:0] shared_dsp_ram_addr ; +reg shared_dsp_ram_w ; + // main 68k ram high -dual_port_ram #(.LEN(16384), .DATA_WIDTH(8)) ram16kx8_H ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[14:1] ), - .wren_a ( !cpu_rw & ram_cs & !cpu_uds_n ), - .data_a ( cpu_dout[15:8] ), - .q_a ( ram_dout[15:8] ) -); +//dual_port_ram #(.LEN(16384), .DATA_WIDTH(8)) ram16kx8_H +//( +// .clock_a ( clk_10M ), +// .address_a ( cpu_a[14:1] ), +// .wren_a ( !cpu_rw & ram_cs & !cpu_uds_n ), +// .data_a ( cpu_dout[15:8] ), +// .q_a ( ram_dout[15:8] ), +// +// .clock_b( clk_14M ), +// .address_b( shared_dsp_ram_addr[11:0] ), +// .wren_b( shared_dsp_ram_w ), +// .data_b( shared_dsp_ram_din[15:8] ), +// .q_b( shared_dsp_ram_dout[15:8] ) +//); +// +//// main 68k ram low +//dual_port_ram #(.LEN(16384), .DATA_WIDTH(8)) ram16kx8_L +//( +// .clock_a( clk_10M ), +// .address_a( cpu_a[14:1] ), +// .wren_a( !cpu_rw & ram_cs & !cpu_lds_n ), +// .data_a( cpu_dout[7:0] ), +// .q_a( ram_dout[7:0] ), +// +// .clock_b( clk_14M ), +// .address_b( shared_dsp_ram_addr[11:0] ), +// .wren_b( shared_dsp_ram_w ), +// .data_b( shared_dsp_ram_din[7:0] ), +// .q_b( shared_dsp_ram_dout[7:0] ) +//); + //wire [15:0] z80_shared_addr = z80_addr - 16'h8000; @@ -1810,48 +1558,51 @@ dual_port_ram #(.LEN(16384), .DATA_WIDTH(8)) ram16kx8_H ( // z80 and 68k shared ram // 4k -dual_port_ram #(.LEN(4096), .DATA_WIDTH(8)) shared_ram ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[12:1] ), - .wren_a ( shared_ram_cs & !cpu_rw & !cpu_lds_n), - .data_a ( cpu_dout[7:0] ), - .q_a ( cpu_shared_dout[7:0] ), - - .clock_b ( clk_3_5M ), // z80 clock is 3.5M - .address_b ( z80_addr[11:0] ), - .data_b ( z80_dout ), - .wren_b ( sound_ram_1_cs & ~z80_wr_n ), - .q_b ( z80_shared_dout ) -); +//dual_port_ram #(.LEN(4096), .DATA_WIDTH(8)) shared_ram +//( +// .clock_a( clk_10M ), +// .address_a( cpu_a[12:1] ), +// .wren_a( shared_ram_cs & !cpu_rw & !cpu_lds_n), +// .data_a( cpu_dout[7:0] ), +// .q_a( cpu_shared_dout[7:0] ), +// +// .clock_b( clk_3_5M ), // z80 clock is 3.5M +// .address_b( z80_addr[11:0] ), +// .data_b( z80_dout ), +// .wren_b( sound_ram_1_cs & ~z80_wr_n ), +// .q_b( z80_shared_dout ) +// ); reg [11:0] sprite_rb_addr; wire [15:0] sprite_rb_dout; -dual_port_ram #(.LEN(4096), .DATA_WIDTH(8)) sprite_ram_rb_l ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[12:1] ), - .wren_a ( sprite_ram_cs & !cpu_rw & !cpu_lds_n), - .data_a ( cpu_dout[7:0] ), - .q_a ( sprite_rb_dout[7:0] ), +dual_port_ram #(.LEN(4096), .DATA_WIDTH(8)) sprite_ram_rb_l +( + .clock_a( clk_10M ), + .address_a( cpu_a[12:1] ), + .wren_a( sprite_ram_cs & !cpu_rw & !cpu_lds_n), + .data_a( cpu_dout[7:0] ), + .q_a( sprite_rb_dout[7:0] ), - .clock_b ( clk_sys ), - .address_b ( sprite_rb_addr ), - .wren_b ( 0 ), - .q_b ( sprite_rb_dout[7:0] ) -); + .clock_b( clk_sys ), + .address_b( sprite_rb_addr ), + .wren_b( 0 ), + .q_b( sprite_rb_dout[7:0] ) + ); -dual_port_ram #(.LEN(4096), .DATA_WIDTH(8)) sprite_ram_rb_h ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[12:1] ), - .wren_a ( sprite_ram_cs & !cpu_rw & !cpu_uds_n), - .data_a ( cpu_dout[15:8] ), - .q_a ( cpu_shared_dout[15:8] ), +dual_port_ram #(.LEN(4096), .DATA_WIDTH(8)) sprite_ram_rb_h +( + .clock_a( clk_10M ), + .address_a( cpu_a[12:1] ), + .wren_a( sprite_ram_cs & !cpu_rw & !cpu_uds_n), + .data_a( cpu_dout[15:8] ), + .q_a( cpu_shared_dout[15:8] ), - .clock_b ( clk_sys ), - .address_b ( sprite_rb_addr ), - .wren_b ( 0 ), - .q_b ( sprite_rb_dout[15:8] ) -); + .clock_b( clk_sys ), + .address_b( sprite_rb_addr ), + .wren_b( 0 ), + .q_b( sprite_rb_dout[15:8] ) + ); reg [22:0] sdram_addr; reg [31:0] sdram_data; @@ -1862,33 +1613,33 @@ wire sdram_ack; wire sdram_valid; wire [31:0] sdram_q; -sdram #(.CLK_FREQ(70.0)) sdram -( - .reset(~pll_locked), - .clk(clk_sys), - - // controller interface - .addr(sdram_addr), - .data(sdram_data), - .we(sdram_we), - .req(sdram_req), - - .ack(sdram_ack), - .valid(sdram_valid), - .q(sdram_q), - - // SDRAM interface - .sdram_a(SDRAM_A), - .sdram_ba(SDRAM_BA), - .sdram_dq(SDRAM_DQ), - .sdram_cke(SDRAM_CKE), - .sdram_cs_n(SDRAM_nCS), - .sdram_ras_n(SDRAM_nRAS), - .sdram_cas_n(SDRAM_nCAS), - .sdram_we_n(SDRAM_nWE), - .sdram_dqml(SDRAM_DQML), - .sdram_dqmh(SDRAM_DQMH) -); +//sdram #(.CLK_FREQ(70.0)) sdram +//( +// .reset(~pll_locked), +// .clk(clk_sys), +// +// // controller interface +// .addr(sdram_addr), +// .data(sdram_data), +// .we(sdram_we), +// .req(sdram_req), +// +// .ack(sdram_ack), +// .valid(sdram_valid), +// .q(sdram_q), +// +// // SDRAM interface +// .sdram_a(SDRAM_A), +// .sdram_ba(SDRAM_BA), +// .sdram_dq(SDRAM_DQ), +// .sdram_cke(SDRAM_CKE), +// .sdram_cs_n(SDRAM_nCS), +// .sdram_ras_n(SDRAM_nRAS), +// .sdram_cas_n(SDRAM_nCAS), +// .sdram_we_n(SDRAM_nWE), +// .sdram_dqml(SDRAM_DQML), +// .sdram_dqmh(SDRAM_DQMH) +//); wire prog_cache_rom_cs; wire [22:0] prog_cache_addr; @@ -1921,6 +1672,9 @@ wire [15:0] sound_rom_1_addr; wire [7:0] sound_rom_1_data; wire sound_rom_1_data_valid; + + + // sdram priority based rom controller // is a oe needed? rom_controller rom_controller @@ -1974,7 +1728,7 @@ rom_controller rom_controller .sdram_ack(sdram_ack), .sdram_valid(sdram_valid), .sdram_q(sdram_q) -); + ); cache prog_cache @@ -1993,7 +1747,8 @@ cache prog_cache .rom_addr(prog_cache_addr), .rom_valid(prog_cache_valid), .rom_data(prog_cache_data) -); + +); tile_cache tile_cache ( @@ -2011,10 +1766,10 @@ tile_cache tile_cache .rom_addr(tile_cache_addr), .rom_data(tile_cache_data), .rom_valid(tile_cache_valid) + ); -endmodule - +endmodule module cc_shifter ( @@ -2033,6 +1788,4 @@ always @(posedge clk_out) begin r[1] <= r[0]; // notice that we use clkB end -endmodule - - +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/cache.v b/Arcade_MiST/Toaplan v1 Hardware/rtl/cache.v similarity index 100% rename from Arcade_MiST/Toaplan v1 Hardware/rtl/common/cache.v rename to Arcade_MiST/Toaplan v1 Hardware/rtl/cache.v diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/chip_select.v b/Arcade_MiST/Toaplan v1 Hardware/rtl/chip_select.v new file mode 100644 index 00000000..4d70940e --- /dev/null +++ b/Arcade_MiST/Toaplan v1 Hardware/rtl/chip_select.v @@ -0,0 +1,117 @@ +// + +module chip_select +( + input [23:0] cpu_a, + input cpu_as_n, + + input [15:0] z80_addr, + input MREQ_n, + input IORQ_n, + + // M68K selects + output prog_rom_cs, + output ram_cs, + output scroll_ofs_x_cs, + output scroll_ofs_y_cs, + output frame_done_cs, + output int_en_cs, + output crtc_cs, + output tile_ofs_cs, + output tile_attr_cs, + output tile_num_cs, + output scroll_cs, + output shared_ram_cs, + output vblank_cs, + output tile_palette_cs, + output bcu_flip_cs, + output sprite_palette_cs, + output sprite_ofs_cs, + output sprite_cs, + output sprite_size_cs, + output sprite_ram_cs, + output fcu_flip_cs, + output reset_z80_cs, + output dsp_ctrl_cs, + output dsp_addr_cs, + output dsp_r_cs, + output dsp_bio_cs, + + // Z80 selects + output z80_p1_cs, + output z80_p2_cs, + output z80_dswa_cs, + output z80_dswb_cs, + output z80_system_cs, + output z80_tjump_cs, + output z80_sound0_cs, + output z80_sound1_cs, + + // other params + output reg [15:0] scroll_y_offset +); + +function m68k_cs; + input [23:0] start_address; + input [23:0] end_address; +begin + m68k_cs = ( cpu_a[23:0] >= start_address && cpu_a[23:0] <= end_address) & !cpu_as_n; +end +endfunction + +function z80_cs; + input [7:0] address_lo; +begin + z80_cs = ( IORQ_n == 0 && z80_addr[7:0] == address_lo ); +end +endfunction + +always @ (*) begin + + scroll_y_offset = 16; + + prog_rom_cs = m68k_cs( 24'h000000, 24'h03ffff ); + ram_cs = m68k_cs( 24'hc00000, 24'hc03fff ); + + scroll_ofs_x_cs = m68k_cs( 24'he00000, 24'he00001 ); + scroll_ofs_y_cs = m68k_cs( 24'he00002, 24'he00003 ); + fcu_flip_cs = m68k_cs( 24'he00006, 24'he00007 ); + + vblank_cs = m68k_cs( 24'h400000, 24'h400001 ); + int_en_cs = m68k_cs( 24'h400002, 24'h400003 ); + crtc_cs = m68k_cs( 24'h400008, 24'h40000f ); + + tile_palette_cs = m68k_cs( 24'h404000, 24'h4047ff ); + sprite_palette_cs = m68k_cs( 24'h406000, 24'h4067ff ); + + shared_ram_cs = m68k_cs( 24'h600000, 24'h600fff ); + + bcu_flip_cs = m68k_cs( 24'h800000, 24'h800001 ); + tile_ofs_cs = m68k_cs( 24'h800002, 24'h800003 ); + tile_attr_cs = m68k_cs( 24'h800004, 24'h800005 ); + tile_num_cs = m68k_cs( 24'h800006, 24'h800006 ); + scroll_cs = m68k_cs( 24'h800010, 24'h80001f ); + + frame_done_cs = m68k_cs( 24'ha00000, 24'ha00001 ); + sprite_ofs_cs = m68k_cs( 24'ha00002, 24'ha00003 ); + sprite_cs = m68k_cs( 24'ha00004, 24'ha00005 ); + sprite_size_cs = m68k_cs( 24'ha00006, 24'ha00007 ); + + reset_z80_cs = m68k_cs( 24'he00008, 24'he00009 ); + + //dsp_ctrl_cs = m68k_cs( 24'he0000a, 24'he0000b ); + //dsp_addr_cs = m68k_cs( 4'h0 ); + //dsp_r_cs = m68k_cs( 4'h1 ); + //dsp_bio_cs = m68k_cs( 4'h3 ); + + z80_p1_cs = z80_cs( 8'h80 ); + z80_p2_cs = z80_cs( 8'hc0 ); + z80_dswa_cs = z80_cs( 8'he0 ); + z80_dswb_cs = z80_cs( 8'ha0 ); + z80_system_cs = z80_cs( 8'h60 ); + z80_tjump_cs = z80_cs( 8'h20 ); + z80_sound0_cs = z80_cs( 8'h00 ); + z80_sound1_cs = z80_cs( 8'h01 ); +end + +endmodule diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/common.qip b/Arcade_MiST/Toaplan v1 Hardware/rtl/common.qip similarity index 86% rename from Arcade_MiST/Toaplan v1 Hardware/rtl/common/common.qip rename to Arcade_MiST/Toaplan v1 Hardware/rtl/common.qip index d6afbd55..cb1ad2be 100644 --- a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/common.qip +++ b/Arcade_MiST/Toaplan v1 Hardware/rtl/common.qip @@ -12,3 +12,6 @@ set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) true_dual_ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtframe_fir_mono.v ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtframe_mixer.v ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) video_timing.v ] + +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sdram.sv ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_mist.v ] diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/sdram.vhd b/Arcade_MiST/Toaplan v1 Hardware/rtl/common/sdram.vhd deleted file mode 100644 index 63cf0958..00000000 --- a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/sdram.vhd +++ /dev/null @@ -1,443 +0,0 @@ --- __ __ __ __ __ __ --- /\ "-.\ \ /\ \/\ \ /\ \ /\ \ --- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____ --- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\ --- \/_/ \/_/ \/_____/ \/_____/ \/_____/ --- ______ ______ __ ______ ______ ______ --- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\ --- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/ --- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\ --- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/ --- --- https://joshbassett.info --- https://twitter.com/nullobject --- https://github.com/nullobject --- --- Copyright (c) 2020 Josh Bassett --- --- Permission is hereby granted, free of charge, to any person obtaining a copy --- of this software and associated documentation files (the "Software"), to deal --- in the Software without restriction, including without limitation the rights --- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell --- copies of the Software, and to permit persons to whom the Software is --- furnished to do so, subject to the following conditions: --- --- The above copyright notice and this permission notice shall be included in all --- copies or substantial portions of the Software. --- --- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR --- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, --- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE --- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER --- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, --- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE --- SOFTWARE. - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use ieee.math_real.all; - ---use work.common.all; -use work.math.all; - --- This SDRAM controller provides a symmetric 32-bit synchronous read/write --- interface for a 16Mx16-bit SDRAM chip (e.g. AS4C16M16SA-6TCN, IS42S16400F, --- etc.). -entity sdram is - generic ( - -- clock frequency (in MHz) - -- - -- This value must be provided, as it is used to calculate the number of - -- clock cycles required for the other timing values. - CLK_FREQ : real; - - -- 32-bit controller interface - ADDR_WIDTH : natural := 23; - DATA_WIDTH : natural := 32; - - -- SDRAM interface - SDRAM_ADDR_WIDTH : natural := 13; - SDRAM_DATA_WIDTH : natural := 16; - SDRAM_COL_WIDTH : natural := 9; - SDRAM_ROW_WIDTH : natural := 13; - SDRAM_BANK_WIDTH : natural := 2; - - -- The delay in clock cycles, between the start of a read command and the - -- availability of the output data. - CAS_LATENCY : natural := 2; -- 2=below 133MHz, 3=above 133MHz - - -- The number of 16-bit words to be bursted during a read/write. - BURST_LENGTH : natural := 2; - - -- timing values (in nanoseconds) - -- - -- These values can be adjusted to match the exact timing of your SDRAM - -- chip (refer to the datasheet). - T_DESL : real := 200000.0; -- startup delay - T_MRD : real := 12.0; -- mode register cycle time - T_RC : real := 60.0; -- row cycle time - T_RCD : real := 18.0; -- RAS to CAS delay - T_RP : real := 18.0; -- precharge to activate delay - T_WR : real := 12.0; -- write recovery time - T_REFI : real := 7800.0 -- average refresh interval - ); - port ( - -- reset - reset : in std_logic := '0'; - - -- clock - clk : in std_logic; - - -- address bus - addr : in unsigned(ADDR_WIDTH-1 downto 0); - - -- input data bus - data : in std_logic_vector(DATA_WIDTH-1 downto 0); - - -- When the write enable signal is asserted, a write operation will be performed. - we : in std_logic; - - -- When the request signal is asserted, an operation will be performed. - req : in std_logic; - - -- The acknowledge signal is asserted by the SDRAM controller when - -- a request has been accepted. - ack : out std_logic; - - -- The valid signal is asserted when there is a valid word on the output - -- data bus. - valid : out std_logic; - - -- output data bus - q : out std_logic_vector(DATA_WIDTH-1 downto 0); - - -- SDRAM interface (e.g. AS4C16M16SA-6TCN, IS42S16400F, etc.) - sdram_a : out unsigned(SDRAM_ADDR_WIDTH-1 downto 0); - sdram_ba : out unsigned(SDRAM_BANK_WIDTH-1 downto 0); - sdram_dq : inout std_logic_vector(SDRAM_DATA_WIDTH-1 downto 0); - sdram_cke : out std_logic; - sdram_cs_n : out std_logic; - sdram_ras_n : out std_logic; - sdram_cas_n : out std_logic; - sdram_we_n : out std_logic; - sdram_dqml : out std_logic; - sdram_dqmh : out std_logic - ); -end sdram; - -architecture arch of sdram is - subtype command_t is std_logic_vector(3 downto 0); - - -- commands - constant CMD_DESELECT : command_t := "1---"; - constant CMD_LOAD_MODE : command_t := "0000"; - constant CMD_AUTO_REFRESH : command_t := "0001"; - constant CMD_PRECHARGE : command_t := "0010"; - constant CMD_ACTIVE : command_t := "0011"; - constant CMD_WRITE : command_t := "0100"; - constant CMD_READ : command_t := "0101"; - constant CMD_STOP : command_t := "0110"; - constant CMD_NOP : command_t := "0111"; - - -- the ordering of the accesses within a burst - constant BURST_TYPE : std_logic := '0'; -- 0=sequential, 1=interleaved - - -- the write burst mode enables bursting for write operations - constant WRITE_BURST_MODE : std_logic := '0'; -- 0=burst, 1=single - - -- the value written to the mode register to configure the memory - constant MODE_REG : unsigned(SDRAM_ADDR_WIDTH-1 downto 0) := ( - "000" & - WRITE_BURST_MODE & - "00" & - to_unsigned(CAS_LATENCY, 3) & - BURST_TYPE & - to_unsigned(ilog2(BURST_LENGTH), 3) - ); - - -- calculate the clock period (in nanoseconds) - constant CLK_PERIOD : real := 1.0/CLK_FREQ*1000.0; - - -- the number of clock cycles to wait before initialising the device - constant INIT_WAIT : natural := natural(ceil(T_DESL/CLK_PERIOD)); - - -- the number of clock cycles to wait while a LOAD MODE command is being - -- executed - constant LOAD_MODE_WAIT : natural := natural(ceil(T_MRD/CLK_PERIOD)); - - -- the number of clock cycles to wait while an ACTIVE command is being - -- executed - constant ACTIVE_WAIT : natural := natural(ceil(T_RCD/CLK_PERIOD)); - - -- the number of clock cycles to wait while a REFRESH command is being - -- executed - constant REFRESH_WAIT : natural := natural(ceil(T_RC/CLK_PERIOD)); - - -- the number of clock cycles to wait while a PRECHARGE command is being - -- executed - constant PRECHARGE_WAIT : natural := natural(ceil(T_RP/CLK_PERIOD)); - - -- the number of clock cycles to wait while a READ command is being executed - constant READ_WAIT : natural := CAS_LATENCY+BURST_LENGTH; - - -- the number of clock cycles to wait while a WRITE command is being executed - constant WRITE_WAIT : natural := BURST_LENGTH+natural(ceil((T_WR+T_RP)/CLK_PERIOD)); - - -- the number of clock cycles before the memory controller needs to refresh - -- the SDRAM - constant REFRESH_INTERVAL : natural := natural(floor(T_REFI/CLK_PERIOD))-10; - - type state_t is (INIT, MODE, IDLE, ACTIVE, READ, WRITE, REFRESH); - - -- state signals - signal state, next_state : state_t; - - -- command signals - signal cmd, next_cmd : command_t := CMD_NOP; - - -- control signals - signal start : std_logic; - signal load_mode_done : std_logic; - signal active_done : std_logic; - signal refresh_done : std_logic; - signal first_word : std_logic; - signal read_done : std_logic; - signal write_done : std_logic; - signal should_refresh : std_logic; - - -- counters - signal wait_counter : natural range 0 to 16383; - signal refresh_counter : natural range 0 to 1023; - - -- registers - signal addr_reg : unsigned(SDRAM_COL_WIDTH+SDRAM_ROW_WIDTH+SDRAM_BANK_WIDTH-1 downto 0); - signal data_reg : std_logic_vector(DATA_WIDTH-1 downto 0); - signal we_reg : std_logic; - signal q_reg : std_logic_vector(DATA_WIDTH-1 downto 0); - - -- aliases to decode the address register - alias col : unsigned(SDRAM_COL_WIDTH-1 downto 0) is addr_reg(SDRAM_COL_WIDTH-1 downto 0); - alias row : unsigned(SDRAM_ROW_WIDTH-1 downto 0) is addr_reg(SDRAM_COL_WIDTH+SDRAM_ROW_WIDTH-1 downto SDRAM_COL_WIDTH); - alias bank : unsigned(SDRAM_BANK_WIDTH-1 downto 0) is addr_reg(SDRAM_COL_WIDTH+SDRAM_ROW_WIDTH+SDRAM_BANK_WIDTH-1 downto SDRAM_COL_WIDTH+SDRAM_ROW_WIDTH); -begin - -- state machine - fsm : process (state, wait_counter, req, we_reg, load_mode_done, active_done, refresh_done, read_done, write_done, should_refresh) - begin - next_state <= state; - - -- default to a NOP command - next_cmd <= CMD_NOP; - - case state is - -- execute the initialisation sequence - when INIT => - if wait_counter = 0 then - next_cmd <= CMD_DESELECT; - elsif wait_counter = INIT_WAIT-1 then - next_cmd <= CMD_PRECHARGE; - elsif wait_counter = INIT_WAIT+PRECHARGE_WAIT-1 then - next_cmd <= CMD_AUTO_REFRESH; - elsif wait_counter = INIT_WAIT+PRECHARGE_WAIT+REFRESH_WAIT-1 then - next_cmd <= CMD_AUTO_REFRESH; - elsif wait_counter = INIT_WAIT+PRECHARGE_WAIT+REFRESH_WAIT+REFRESH_WAIT-1 then - next_state <= MODE; - next_cmd <= CMD_LOAD_MODE; - end if; - - -- load the mode register - when MODE => - if load_mode_done = '1' then - next_state <= IDLE; - end if; - - -- wait for a read/write request - when IDLE => - if should_refresh = '1' then - next_state <= REFRESH; - next_cmd <= CMD_AUTO_REFRESH; - elsif req = '1' then - next_state <= ACTIVE; - next_cmd <= CMD_ACTIVE; - end if; - - -- activate the row - when ACTIVE => - if active_done = '1' then - if we_reg = '1' then - next_state <= WRITE; - next_cmd <= CMD_WRITE; - else - next_state <= READ; - next_cmd <= CMD_READ; - end if; - end if; - - -- execute a read command - when READ => - if read_done = '1' then - if should_refresh = '1' then - next_state <= REFRESH; - next_cmd <= CMD_AUTO_REFRESH; - elsif req = '1' then - next_state <= ACTIVE; - next_cmd <= CMD_ACTIVE; - else - next_state <= IDLE; - end if; - end if; - - -- execute a write command - when WRITE => - if write_done = '1' then - if should_refresh = '1' then - next_state <= REFRESH; - next_cmd <= CMD_AUTO_REFRESH; - elsif req = '1' then - next_state <= ACTIVE; - next_cmd <= CMD_ACTIVE; - else - next_state <= IDLE; - end if; - end if; - - -- execute an auto refresh - when REFRESH => - if refresh_done = '1' then - if req = '1' then - next_state <= ACTIVE; - next_cmd <= CMD_ACTIVE; - else - next_state <= IDLE; - end if; - end if; - end case; - end process; - - -- latch the next state - latch_next_state : process (clk, reset) - begin - if reset = '1' then - state <= INIT; - cmd <= CMD_NOP; - elsif rising_edge(clk) then - state <= next_state; - cmd <= next_cmd; - end if; - end process; - - -- the wait counter is used to hold the current state for a number of clock - -- cycles - update_wait_counter : process (clk, reset) - begin - if reset = '1' then - wait_counter <= 0; - elsif rising_edge(clk) then - if state /= next_state then -- state changing - wait_counter <= 0; - else - wait_counter <= wait_counter + 1; - end if; - end if; - end process; - - -- the refresh counter is used to periodically trigger a refresh operation - update_refresh_counter : process (clk, reset) - begin - if reset = '1' then - refresh_counter <= 0; - elsif rising_edge(clk) then - if state = REFRESH and wait_counter = 0 then - refresh_counter <= 0; - else - refresh_counter <= refresh_counter + 1; - end if; - end if; - end process; - - -- latch the rquest - latch_request : process (clk) - begin - if rising_edge(clk) then - if start = '1' then - -- we need to multiply the address by two, because we are converting - -- from a 32-bit controller address to a 16-bit SDRAM address - addr_reg <= shift_left(resize(addr, addr_reg'length), 1); - data_reg <= data; - we_reg <= we; - end if; - end if; - end process; - - -- latch the output data as it's bursted from the SDRAM - latch_sdram_data : process (clk) - begin - if rising_edge(clk) then - valid <= '0'; - - if state = READ then - if first_word = '1' then - q_reg(31 downto 16) <= sdram_dq; - elsif read_done = '1' then - q_reg(15 downto 0) <= sdram_dq; - valid <= '1'; - end if; - end if; - end if; - end process; - - -- set wait signals - load_mode_done <= '1' when wait_counter = LOAD_MODE_WAIT-1 else '0'; - active_done <= '1' when wait_counter = ACTIVE_WAIT-1 else '0'; - refresh_done <= '1' when wait_counter = REFRESH_WAIT-1 else '0'; - first_word <= '1' when wait_counter = CAS_LATENCY else '0'; - read_done <= '1' when wait_counter = READ_WAIT-1 else '0'; - write_done <= '1' when wait_counter = WRITE_WAIT-1 else '0'; - - -- the SDRAM should be refreshed when the refresh interval has elapsed - should_refresh <= '1' when refresh_counter >= REFRESH_INTERVAL-1 else '0'; - - -- a new request is only allowed at the end of the IDLE, READ, WRITE, and - -- REFRESH states - start <= '1' when (state = IDLE) or - (state = READ and read_done = '1') or - (state = WRITE and write_done = '1') or - (state = REFRESH and refresh_done = '1') else '0'; - - -- assert the acknowledge signal at the beginning of the ACTIVE state - ack <= '1' when state = ACTIVE and wait_counter = 0 else '0'; - - -- set output data - q <= q_reg; - - -- deassert the clock enable at the beginning of the INIT state - sdram_cke <= '0' when state = INIT and wait_counter = 0 else '1'; - - -- set SDRAM control signals - (sdram_cs_n, sdram_ras_n, sdram_cas_n, sdram_we_n) <= cmd; - - -- set SDRAM bank - with state select - sdram_ba <= - bank when ACTIVE, - bank when READ, - bank when WRITE, - (others => '0') when others; - - -- set SDRAM address - with state select - sdram_a <= - "0010000000000" when INIT, - MODE_REG when MODE, - row when ACTIVE, - "0010" & col when READ, -- auto precharge - "0010" & col when WRITE, -- auto precharge - (others => '0') when others; - - -- decode the next 16-bit word from the write buffer - sdram_dq <= data_reg((BURST_LENGTH-wait_counter)*SDRAM_DATA_WIDTH-1 downto (BURST_LENGTH-wait_counter-1)*SDRAM_DATA_WIDTH) when state = WRITE else (others => 'Z'); - - -- set SDRAM data mask - sdram_dqmh <= '0'; - sdram_dqml <= '0'; -end architecture arch; diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/download_buffer.vhd b/Arcade_MiST/Toaplan v1 Hardware/rtl/download_buffer.vhd similarity index 100% rename from Arcade_MiST/Toaplan v1 Hardware/rtl/common/download_buffer.vhd rename to Arcade_MiST/Toaplan v1 Hardware/rtl/download_buffer.vhd diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/dual_port_ram.vhd b/Arcade_MiST/Toaplan v1 Hardware/rtl/dual_port_ram.vhd similarity index 100% rename from Arcade_MiST/Toaplan v1 Hardware/rtl/common/dual_port_ram.vhd rename to Arcade_MiST/Toaplan v1 Hardware/rtl/dual_port_ram.vhd diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/jtframe_fir_mono.v b/Arcade_MiST/Toaplan v1 Hardware/rtl/jtframe_fir_mono.v similarity index 100% rename from Arcade_MiST/Toaplan v1 Hardware/rtl/common/jtframe_fir_mono.v rename to Arcade_MiST/Toaplan v1 Hardware/rtl/jtframe_fir_mono.v diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/jtframe_mixer.v b/Arcade_MiST/Toaplan v1 Hardware/rtl/jtframe_mixer.v similarity index 100% rename from Arcade_MiST/Toaplan v1 Hardware/rtl/common/jtframe_mixer.v rename to Arcade_MiST/Toaplan v1 Hardware/rtl/jtframe_mixer.v diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/math.vhd b/Arcade_MiST/Toaplan v1 Hardware/rtl/math.vhd similarity index 100% rename from Arcade_MiST/Toaplan v1 Hardware/rtl/common/math.vhd rename to Arcade_MiST/Toaplan v1 Hardware/rtl/math.vhd diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/rom_controller.v b/Arcade_MiST/Toaplan v1 Hardware/rtl/rom_controller.v similarity index 100% rename from Arcade_MiST/Toaplan v1 Hardware/rtl/common/rom_controller.v rename to Arcade_MiST/Toaplan v1 Hardware/rtl/rom_controller.v diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_demonsworld/demonwld.sv b/Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_demonsworld/demonwld.sv deleted file mode 100644 index 3a4ae14f..00000000 --- a/Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_demonsworld/demonwld.sv +++ /dev/null @@ -1,475 +0,0 @@ -////============================================================================ -//// -//// This program is free software; you can redistribute it and/or modify it -//// under the terms of the GNU General Public License as published by the Free -//// Software Foundation; either version 2 of the License, or (at your option) -//// any later version. -//// -//// This program is distributed in the hope that it will be useful, but WITHOUT -//// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -//// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -//// more details. -//// -//// You should have received a copy of the GNU General Public License along -//// with this program; if not, write to the Free Software Foundation, Inc., -//// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//// -////============================================================================ -// -//`default_nettype none -// -//module emu -//( -// //Master input clock -// input CLK_50M, -// -// //Async reset from top-level module. -// //Can be used as initial reset. -// input RESET, -// -// //Must be passed to hps_io module -// inout [48:0] HPS_BUS, -// -// //Base video clock. Usually equals to CLK_SYS. -// output CLK_VIDEO, -// -// //Multiple resolutions are supported using different CE_PIXEL rates. -// //Must be based on CLK_VIDEO -// output CE_PIXEL, -// -// //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. -// //if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio. -// output [12:0] VIDEO_ARX, -// output [12:0] VIDEO_ARY, -// -// output [7:0] VGA_R, -// output [7:0] VGA_G, -// output [7:0] VGA_B, -// output VGA_HS, -// output VGA_VS, -// output VGA_DE, // = ~(VBlank | HBlank) -// output VGA_F1, -// output [2:0] VGA_SL, -// output VGA_SCALER, // Force VGA scaler -// -// input [11:0] HDMI_WIDTH, -// input [11:0] HDMI_HEIGHT, -// output HDMI_FREEZE, -// -//`ifdef MISTER_FB -// // Use framebuffer in DDRAM (USE_FB=1 in qsf) -// // FB_FORMAT: -// // [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp -// // [3] : 0=16bits 565 1=16bits 1555 -// // [4] : 0=RGB 1=BGR (for 16/24/32 modes) -// // -// // FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes) -// output FB_EN, -// output [4:0] FB_FORMAT, -// output [11:0] FB_WIDTH, -// output [11:0] FB_HEIGHT, -// output [31:0] FB_BASE, -// output [13:0] FB_STRIDE, -// input FB_VBL, -// input FB_LL, -// output FB_FORCE_BLANK, -// -//`ifdef MISTER_FB_PALETTE -// // Palette control for 8bit modes. -// // Ignored for other video modes. -// output FB_PAL_CLK, -// output [7:0] FB_PAL_ADDR, -// output [23:0] FB_PAL_DOUT, -// input [23:0] FB_PAL_DIN, -// output FB_PAL_WR, -//`endif -//`endif -// -// output LED_USER, // 1 - ON, 0 - OFF. -// -// // b[1]: 0 - LED status is system status OR'd with b[0] -// // 1 - LED status is controled solely by b[0] -// // hint: supply 2'b00 to let the system control the LED. -// output [1:0] LED_POWER, -// output [1:0] LED_DISK, -// -// // I/O board button press simulation (active high) -// // b[1]: user button -// // b[0]: osd button -// output [1:0] BUTTONS, -// -// //Audio -// input CLK_AUDIO, // 24.576 MHz -// output [15:0] AUDIO_L, -// output [15:0] AUDIO_R, -// output AUDIO_S, // 1 - signed audio samples, 0 - unsigned -// output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono) -// -// //ADC -// inout [3:0] ADC_BUS, -// -// //SD-SPI -// output SD_SCK, -// output SD_MOSI, -// input SD_MISO, -// output SD_CS, -// input SD_CD, -// -// //High latency DDR3 RAM interface -// //Use for non-critical time purposes -// output DDRAM_CLK, -// input DDRAM_BUSY, -// output [7:0] DDRAM_BURSTCNT, -// output [28:0] DDRAM_ADDR, -// input [63:0] DDRAM_DOUT, -// input DDRAM_DOUT_READY, -// output DDRAM_RD, -// output [63:0] DDRAM_DIN, -// output [7:0] DDRAM_BE, -// output DDRAM_WE, -// -// //SDRAM interface with lower latency -// output SDRAM_CLK, -// output SDRAM_CKE, -// output [12:0] SDRAM_A, -// output [1:0] SDRAM_BA, -// inout [15:0] SDRAM_DQ, -// output SDRAM_DQML, -// output SDRAM_DQMH, -// output SDRAM_nCS, -// output SDRAM_nCAS, -// output SDRAM_nRAS, -// output SDRAM_nWE, -// -//`ifdef MISTER_DUAL_SDRAM -// //Secondary SDRAM -// //Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0 -// input SDRAM2_EN, -// output SDRAM2_CLK, -// output [12:0] SDRAM2_A, -// output [1:0] SDRAM2_BA, -// inout [15:0] SDRAM2_DQ, -// output SDRAM2_nCS, -// output SDRAM2_nCAS, -// output SDRAM2_nRAS, -// output SDRAM2_nWE, -//`endif -// -// input UART_CTS, -// output UART_RTS, -// input UART_RXD, -// output UART_TXD, -// output UART_DTR, -// input UART_DSR, -// -//`ifdef MISTER_ENABLE_YC -// output [39:0] CHROMA_PHASE_INC, -// output YC_EN, -// output PALFLAG, -//`endif -// -// // Open-drain User port. -// // 0 - D+/RX -// // 1 - D-/TX -// // 2..6 - USR2..USR6 -// // Set USER_OUT to 1 to read from USER_IN. -// input [6:0] USER_IN, -// output [6:0] USER_OUT, -// -// input OSD_STATUS -//); -// -/////////// Default values for ports not used in this core ///////// -// -//assign ADC_BUS = 'Z; -//assign USER_OUT = 0; -//assign {UART_RTS, UART_TXD, UART_DTR} = 0; -//assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; -////assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z; -////assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0; -//assign VGA_F1 = 0; -//assign VGA_SCALER = 0; -//assign HDMI_FREEZE = 0; -// -//assign AUDIO_MIX = 0; -//assign LED_USER = ioctl_download & cpu_a[0] & & tms_addr & & tms_dout & & tms_rom_addr & & tms_rom_dout ; -//assign LED_DISK = 0; -//assign LED_POWER = 0; -//assign BUTTONS = 0; -// -//// Status Bit Map: -//// Upper Case Lower Case -//// 0 1 2 3 4 5 6 -//// 01234567890123456789012345678901 23456789012345678901234567890123 -//// 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV -//// X XXXXXXXX X XXXX XXXXXXXX X X XX XXXXXXXX -// -//wire [1:0] aspect_ratio = status[9:8]; -//wire orientation = ~status[3]; -//wire [2:0] scan_lines = status[6:4]; -//reg refresh_mod; -//reg new_vmode; -// -//always @(posedge clk_sys) begin -// if (refresh_mod != status[19]) begin -// refresh_mod <= status[19]; -// new_vmode <= ~new_vmode; -// end -//end -// -//wire [3:0] hs_offset = status[27:24]; -//wire [3:0] vs_offset = status[31:28]; -//wire [3:0] hs_width = status[59:56]; -//wire [3:0] vs_width = status[63:60]; -// -//assign VIDEO_ARX = (!aspect_ratio) ? (orientation ? 8'd4 : 8'd3) : (aspect_ratio - 1'd1); -//assign VIDEO_ARY = (!aspect_ratio) ? (orientation ? 8'd3 : 8'd4) : 12'd0; -// -//`include "build_id.v" -//localparam CONF_STR = { -// "Toaplan V1;;", -// "-;", -// "P1,Video Settings;", -// "P1-;", -// "P1O89,Aspect Ratio,Original,Full Screen,[ARC1],[ARC2];", -// "P1O3,Orientation,Horz,Vert;", -// "P1-;", -// "P1O46,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%,CRT 100%;", -// "P1OA,Force Scandoubler,Off,On;", -// "P1-;", -// "P1O7,Video Mode,NTSC,PAL;", -// "P1OM,Video Signal,RGBS/YPbPr,Y/C;", -// "P1OJ,Refresh Rate,Native,NTSC;", -// "P1-;", -// "P1OOR,H-sync Pos Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", -// "P1OSV,V-sync Pos Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", -// "P1-;", -// "P1oOR,H-sync Width Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", -// "P1oSV,V-sync Width Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", -// "P1-;", -// "P2,Audio Settings;", -// "P2-;", -// "P2oBC,OPL2 Volume,Default,50%,25%,0%;", -// "P2-;", -// "-;", -// "P3,Core Options;", -// "P3-;", -// "P3o6,Swap P1/P2 Joystick,Off,On;", -// "P3-;", -// "P3OF,68k Freq.,10Mhz,17.5MHz;", -// "P3-;", -// "P3o0,Scroll Debug,Off,On;", -// "P3-;", -// "DIP;", -// "-;", -// "OK,Pause OSD,Off,When Open;", -// "OL,Dim Video,Off,10s;", -// "-;", -// "R0,Reset;", -// "V,v",`BUILD_DATE -//}; -// -//wire hps_forced_scandoubler; -//wire forced_scandoubler = hps_forced_scandoubler | status[10]; -// -//wire [1:0] buttons; -//wire [63:0] status; -//wire [10:0] ps2_key; -//wire [15:0] joy0, joy1; -// -//hps_io #(.CONF_STR(CONF_STR)) hps_io -//( -// .clk_sys(clk_sys), -// .HPS_BUS(HPS_BUS), -// -// .buttons(buttons), -// .ps2_key(ps2_key), -// .status(status), -// .status_menumask(direct_video), -// .forced_scandoubler(hps_forced_scandoubler), -// .gamma_bus(gamma_bus), -// .new_vmode(new_vmode), -// .direct_video(direct_video), -// .video_rotated(video_rotated), -// -// .ioctl_download(ioctl_download), -// .ioctl_upload(ioctl_upload), -// .ioctl_wr(ioctl_wr), -// .ioctl_addr(ioctl_addr), -// .ioctl_dout(ioctl_dout), -// .ioctl_din(ioctl_din), -// .ioctl_index(ioctl_index), -// .ioctl_wait(ioctl_wait), -// -// .joystick_0(joy0), -// .joystick_1(joy1) -//); -// -//// INPUT -// -//// 8 dip switches of 8 bits -//reg [7:0] sw[8]; -//always @(posedge clk_sys) begin -// if (ioctl_wr && (ioctl_index==254) && !ioctl_addr[24:3]) begin -// sw[ioctl_addr[2:0]] <= ioctl_dout; -// end -//end -// -//wire direct_video; -// -//wire ioctl_download; -//wire ioctl_upload; -//wire ioctl_upload_req; -//wire ioctl_wait; -//wire ioctl_wr; -//wire [15:0] ioctl_index; -//wire [26:0] ioctl_addr; -//wire [15:0] ioctl_dout; -//wire [15:0] ioctl_din; -// -//wire tile_priority_type; -//wire [15:0] scroll_y_offset; -// -//wire [21:0] gamma_bus; -// -//// -//// Inputs tied to z80_din -//reg [7:0] p1; -//reg [7:0] p2; -//reg [7:0] z80_dswa; -//reg [7:0] z80_dswb; -//reg [7:0] z80_tjump; -//reg [7:0] system; -// -//always @ (posedge clk_sys ) begin -// p1 <= { 1'b0, p1_buttons[2:0], p1_right, p1_left, p1_down, p1_up }; -// p2 <= { 1'b0, p2_buttons[2:0], p2_right, p2_left, p2_down, p2_up }; -// z80_dswa <= sw[0]; -// z80_dswb <= sw[1]; -// z80_tjump <= sw[2]; -// -// if ( status[32] == 1 ) begin -// system <= { vbl, start2 | p1_buttons[3], start1 | p1_buttons[3], coin_b, coin_a, service | status[32], key_tilt, key_service }; -// end else begin -// system <= { vbl, start2, start1, coin_b, coin_a, service, key_tilt, key_service }; -// end -//end -// -//reg p1_swap; -// -//reg p1_right; -//reg p1_left; -//reg p1_down; -//reg p1_up; -//reg [3:0] p1_buttons; -// -//reg p2_right; -//reg p2_left; -//reg p2_down; -//reg p2_up; -//reg [3:0] p2_buttons; -// -//reg start1; -//reg start2; -//reg coin_a; -//reg coin_b; -//reg b_pause; -//reg service; -// -//always @ * begin -// p1_swap <= status[38]; -// -// if ( status[38] == 0 ) begin -// p1_right <= joy0[0] | key_p1_right; -// p1_left <= joy0[1] | key_p1_left; -// p1_down <= joy0[2] | key_p1_down; -// p1_up <= joy0[3] | key_p1_up; -// p1_buttons <= joy0[7:4] | {key_p1_c, key_p1_b, key_p1_a}; -// -// p2_right <= joy1[0] | key_p2_right; -// p2_left <= joy1[1] | key_p2_left; -// p2_down <= joy1[2] | key_p2_down; -// p2_up <= joy1[3] | key_p2_up; -// p2_buttons <= joy1[7:4] | {key_p2_c, key_p2_b, key_p2_a}; -// end else begin -// p2_right <= joy0[0] | key_p1_right; -// p2_left <= joy0[1] | key_p1_left; -// p2_down <= joy0[2] | key_p1_down; -// p2_up <= joy0[3] | key_p1_up; -// p2_buttons <= joy0[7:4] | {key_p1_c, key_p1_b, key_p1_a}; -// -// p1_right <= joy1[0] | key_p2_right; -// p1_left <= joy1[1] | key_p2_left; -// p1_down <= joy1[2] | key_p2_down; -// p1_up <= joy1[3] | key_p2_up; -// p1_buttons <= joy1[7:4] | {key_p2_c, key_p2_b, key_p2_a}; -// end -//end -// -//always @ * begin -// start1 <= joy0[8] | joy1[8] | key_start_1p; -// start2 <= joy0[9] | joy1[9] | key_start_2p; -// -// coin_a <= joy0[10] | joy1[10] | key_coin_a; -// coin_b <= joy0[11] | joy1[11] | key_coin_b; -// -// b_pause <= joy0[12] | key_pause; -// service <= key_test; -//end -// -//// Keyboard handler -// -//reg key_start_1p, key_start_2p, key_coin_a, key_coin_b; -//reg key_tilt, key_test, key_reset, key_service, key_pause; -// -//reg key_p1_up, key_p1_left, key_p1_down, key_p1_right, key_p1_a, key_p1_b, key_p1_c; -//reg key_p2_up, key_p2_left, key_p2_down, key_p2_right, key_p2_a, key_p2_b, key_p2_c; -// -//wire pressed = ps2_key[9]; -// -//always @(posedge clk_sys) begin -// reg old_state; -// old_state <= ps2_key[10]; -// if ( old_state ^ ps2_key[10] ) begin -// casex ( ps2_key[8:0] ) -// 'h016 : key_start_1p <= pressed; // 1 -// 'h01E : key_start_2p <= pressed; // 2 -// 'h02E : key_coin_a <= pressed; // 5 -// 'h036 : key_coin_b <= pressed; // 6 -// 'h006 : key_test <= key_test ^ pressed; // f2 -// 'h004 : key_reset <= pressed; // f3 -// 'h046 : key_service <= pressed; // 9 -// 'h02C : key_tilt <= pressed; // t -// 'h04D : key_pause <= pressed; // p -// -// 'h175 : key_p1_up <= pressed; // up -// 'h172 : key_p1_down <= pressed; // down -// 'h16B : key_p1_left <= pressed; // left -// 'h174 : key_p1_right <= pressed; // right -// 'h014 : key_p1_a <= pressed; // lctrl -// 'h011 : key_p1_b <= pressed; // lalt -// 'h029 : key_p1_c <= pressed; // spacebar -// -// 'h02D : key_p2_up <= pressed; // r -// 'h02B : key_p2_down <= pressed; // f -// 'h023 : key_p2_left <= pressed; // d -// 'h034 : key_p2_right <= pressed; // g -// 'h01C : key_p2_a <= pressed; // a -// 'h01B : key_p2_b <= pressed; // s -// 'h015 : key_p2_c <= pressed; // q -// endcase -// end -//end -// -// -// -// -// -// -// -//endmodule - - - - - diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_demonsworld/rtl_demonsworld.rar b/Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_demonsworld/rtl_demonsworld.rar new file mode 100644 index 00000000..d517b583 Binary files /dev/null and b/Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_demonsworld/rtl_demonsworld.rar differ diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_rallybike/rallybik.sv b/Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_rallybike/rallybik.sv deleted file mode 100644 index 3d64d607..00000000 --- a/Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_rallybike/rallybik.sv +++ /dev/null @@ -1,1988 +0,0 @@ -//============================================================================ -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -// -//============================================================================ - -`default_nettype none - -module emu -( - //Master input clock - input CLK_50M, - - //Async reset from top-level module. - //Can be used as initial reset. - input RESET, - - //Must be passed to hps_io module - inout [48:0] HPS_BUS, - - //Base video clock. Usually equals to CLK_SYS. - output CLK_VIDEO, - - //Multiple resolutions are supported using different CE_PIXEL rates. - //Must be based on CLK_VIDEO - output CE_PIXEL, - - //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. - //if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio. - output [12:0] VIDEO_ARX, - output [12:0] VIDEO_ARY, - - output [7:0] VGA_R, - output [7:0] VGA_G, - output [7:0] VGA_B, - output VGA_HS, - output VGA_VS, - output VGA_DE, // = ~(VBlank | HBlank) - output VGA_F1, - output [2:0] VGA_SL, - output VGA_SCALER, // Force VGA scaler - - input [11:0] HDMI_WIDTH, - input [11:0] HDMI_HEIGHT, - output HDMI_FREEZE, - -`ifdef MISTER_FB - // Use framebuffer in DDRAM (USE_FB=1 in qsf) - // FB_FORMAT: - // [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp - // [3] : 0=16bits 565 1=16bits 1555 - // [4] : 0=RGB 1=BGR (for 16/24/32 modes) - // - // FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes) - output FB_EN, - output [4:0] FB_FORMAT, - output [11:0] FB_WIDTH, - output [11:0] FB_HEIGHT, - output [31:0] FB_BASE, - output [13:0] FB_STRIDE, - input FB_VBL, - input FB_LL, - output FB_FORCE_BLANK, - -`ifdef MISTER_FB_PALETTE - // Palette control for 8bit modes. - // Ignored for other video modes. - output FB_PAL_CLK, - output [7:0] FB_PAL_ADDR, - output [23:0] FB_PAL_DOUT, - input [23:0] FB_PAL_DIN, - output FB_PAL_WR, -`endif -`endif - - output LED_USER, // 1 - ON, 0 - OFF. - - // b[1]: 0 - LED status is system status OR'd with b[0] - // 1 - LED status is controled solely by b[0] - // hint: supply 2'b00 to let the system control the LED. - output [1:0] LED_POWER, - output [1:0] LED_DISK, - - // I/O board button press simulation (active high) - // b[1]: user button - // b[0]: osd button - output [1:0] BUTTONS, - - //Audio - input CLK_AUDIO, // 24.576 MHz - output [15:0] AUDIO_L, - output [15:0] AUDIO_R, - output AUDIO_S, // 1 - signed audio samples, 0 - unsigned - output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono) - - //ADC - inout [3:0] ADC_BUS, - - //SD-SPI - output SD_SCK, - output SD_MOSI, - input SD_MISO, - output SD_CS, - input SD_CD, - - //High latency DDR3 RAM interface - //Use for non-critical time purposes - output DDRAM_CLK, - input DDRAM_BUSY, - output [7:0] DDRAM_BURSTCNT, - output [28:0] DDRAM_ADDR, - input [63:0] DDRAM_DOUT, - input DDRAM_DOUT_READY, - output DDRAM_RD, - output [63:0] DDRAM_DIN, - output [7:0] DDRAM_BE, - output DDRAM_WE, - - //SDRAM interface with lower latency - output SDRAM_CLK, - output SDRAM_CKE, - output [12:0] SDRAM_A, - output [1:0] SDRAM_BA, - inout [15:0] SDRAM_DQ, - output SDRAM_DQML, - output SDRAM_DQMH, - output SDRAM_nCS, - output SDRAM_nCAS, - output SDRAM_nRAS, - output SDRAM_nWE, - -`ifdef MISTER_DUAL_SDRAM - //Secondary SDRAM - //Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0 - input SDRAM2_EN, - output SDRAM2_CLK, - output [12:0] SDRAM2_A, - output [1:0] SDRAM2_BA, - inout [15:0] SDRAM2_DQ, - output SDRAM2_nCS, - output SDRAM2_nCAS, - output SDRAM2_nRAS, - output SDRAM2_nWE, -`endif - - input UART_CTS, - output UART_RTS, - input UART_RXD, - output UART_TXD, - output UART_DTR, - input UART_DSR, - -`ifdef MISTER_ENABLE_YC - output [39:0] CHROMA_PHASE_INC, - output YC_EN, - output PALFLAG, -`endif - - // Open-drain User port. - // 0 - D+/RX - // 1 - D-/TX - // 2..6 - USR2..USR6 - // Set USER_OUT to 1 to read from USER_IN. - input [6:0] USER_IN, - output [6:0] USER_OUT, - - input OSD_STATUS -); - -///////// Default values for ports not used in this core ///////// - -assign ADC_BUS = 'Z; -assign USER_OUT = 0; -assign {UART_RTS, UART_TXD, UART_DTR} = 0; -assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; -//assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z; -//assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0; -assign VGA_F1 = 0; -assign VGA_SCALER = 0; -assign HDMI_FREEZE = 0; - -assign AUDIO_MIX = 0; -assign LED_USER = ioctl_download & cpu_a[0]; -assign LED_DISK = 0; -assign LED_POWER = 0; -assign BUTTONS = 0; - -// Status Bit Map: -// Upper Case Lower Case -// 0 1 2 3 4 5 6 -// 01234567890123456789012345678901 23456789012345678901234567890123 -// 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV -// X XXXXXXXX XX X X XXXXXXXX X XX XXXXXXXX - -wire [1:0] aspect_ratio = status[9:8]; -wire orientation = ~status[3]; -wire [2:0] scan_lines = status[6:4]; -reg refresh_mod; -reg new_vmode; - -always @(posedge clk_sys) begin - if (refresh_mod != status[19]) begin - refresh_mod <= status[19]; - new_vmode <= ~new_vmode; - end -end - -wire [3:0] hs_offset = status[27:24]; -wire [3:0] vs_offset = status[31:28]; -wire [3:0] hs_width = status[59:56]; -wire [3:0] vs_width = status[63:60]; - -assign VIDEO_ARX = (!aspect_ratio) ? (orientation ? 8'd4 : 8'd3) : (aspect_ratio - 1'd1); -assign VIDEO_ARY = (!aspect_ratio) ? (orientation ? 8'd3 : 8'd4) : 12'd0; - -`include "build_id.v" -localparam CONF_STR = { - "Toaplan V1;;", - "-;", - "P1,Video Settings;", - "P1-;", - "P1O89,Aspect Ratio,Original,Full Screen,[ARC1],[ARC2];", - "P1O3,Orientation,Horz,Vert;", - "P1-;", - "P1O46,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%,CRT 100%;", - "P1OA,Force Scandoubler,Off,On;", - "P1-;", - "P1O7,Video Mode,NTSC,PAL;", - "P1OM,Video Signal,RGBS/YPbPr,Y/C;", - "P1OJ,Refresh Rate,Native,NTSC;", - "P1-;", - "P1OOR,H-sync Pos Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", - "P1OSV,V-sync Pos Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", - "P1-;", - "P1oOR,H-sync Width Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", - "P1oSV,V-sync Width Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", - "P1-;", - "P2,Audio Settings;", - "P2-;", - "P2oBC,OPL2 Volume,Default,50%,25%,0%;", - "P2-;", - "-;", - "P3,Core Options;", - "P3-;", - "P3OF,68k Freq.,10Mhz,17.5MHz;", - "P3-;", - "P3o0,Scroll Debug,Off,On;", - "P3-;", - "DIP;", - "-;", - "OK,Pause OSD,Off,When Open;", - "OL,Dim Video,Off,10s;", - "-;", - "R0,Reset;", - "V,v",`BUILD_DATE -}; - -wire hps_forced_scandoubler; -wire forced_scandoubler = hps_forced_scandoubler | status[10]; - -wire [1:0] buttons; -wire [63:0] status; -wire [10:0] ps2_key; -wire [15:0] joy0, joy1; - -hps_io #(.CONF_STR(CONF_STR)) hps_io -( - .clk_sys(clk_sys), - .HPS_BUS(HPS_BUS), - - .buttons(buttons), - .ps2_key(ps2_key), - .status(status), - .status_menumask(direct_video), - .forced_scandoubler(hps_forced_scandoubler), - .gamma_bus(gamma_bus), - .new_vmode(new_vmode), - .direct_video(direct_video), - .video_rotated(video_rotated), - - .ioctl_download(ioctl_download), - .ioctl_upload(ioctl_upload), - .ioctl_wr(ioctl_wr), - .ioctl_addr(ioctl_addr), - .ioctl_dout(ioctl_dout), - .ioctl_din(ioctl_din), - .ioctl_index(ioctl_index), - .ioctl_wait(ioctl_wait), - - .joystick_0(joy0), - .joystick_1(joy1) -); - -// INPUT - -// 8 dip switches of 8 bits -reg [7:0] sw[8]; -always @(posedge clk_sys) begin - if (ioctl_wr && (ioctl_index==254) && !ioctl_addr[24:3]) begin - sw[ioctl_addr[2:0]] <= ioctl_dout; - end -end - -wire direct_video; - -wire ioctl_download; -wire ioctl_upload; -wire ioctl_upload_req; -wire ioctl_wait; -wire ioctl_wr; -wire [15:0] ioctl_index; -wire [26:0] ioctl_addr; -wire [15:0] ioctl_dout; -wire [15:0] ioctl_din; - -wire tile_priority_type; -wire [15:0] scroll_y_offset; -wire [15:0] scroll_x_offset = 30; - -wire [21:0] gamma_bus; - -// -// Inputs tied to z80_din -reg [7:0] p1; -reg [7:0] p2; -reg [7:0] z80_dswa; -reg [7:0] z80_dswb; -reg [7:0] z80_tjump; -reg [7:0] system; - -always @ (posedge clk_sys ) begin - - p1 <= { 1'b0, p1_buttons[2:0], p1_right, p1_left, p1_down, p1_up }; - p2 <= { 1'b0, p2_buttons[2:0], p2_right, p2_left, p2_down, p2_up }; - z80_dswa <= sw[0]; - z80_dswb <= sw[1]; - z80_tjump <= sw[2]; - - if ( status[32] == 1 ) begin - system <= { vbl, start2 | p1_buttons[3], start1 | p1_buttons[3], coin_b, coin_a, service | status[32], key_tilt, key_service }; - end else begin - system <= { vbl, start2, start1, coin_b, coin_a, service, key_tilt, key_service }; - end -end - -reg p1_right; -reg p1_left; -reg p1_down; -reg p1_up; -reg [3:0] p1_buttons; - -reg p2_right; -reg p2_left; -reg p2_down; -reg p2_up; -reg [3:0] p2_buttons; - -reg start1; -reg start2; -reg coin_a; -reg coin_b; -reg b_pause; -reg service; - -always @ * begin - p1_right <= joy0[0] | key_p1_right; - p1_left <= joy0[1] | key_p1_left; - p1_down <= joy0[2] | key_p1_down; - p1_up <= joy0[3] | key_p1_up; - p1_buttons <= joy0[7:4] | {key_p1_c, key_p1_b, key_p1_a}; - - p2_right <= joy1[0] | key_p2_right; - p2_left <= joy1[1] | key_p2_left; - p2_down <= joy1[2] | key_p2_down; - p2_up <= joy1[3] | key_p2_up; - p2_buttons <= joy1[7:4] | {key_p2_c, key_p2_b, key_p2_a}; - - start1 <= joy0[8] | joy1[8] | key_start_1p; - start2 <= joy0[9] | joy1[9] | key_start_2p; - - coin_a <= joy0[10] | joy1[10] | key_coin_a; - coin_b <= joy0[11] | joy1[11] | key_coin_b; - - b_pause <= joy0[12] | key_pause; - service <= key_test; -end - -// Keyboard handler - -reg key_start_1p, key_start_2p, key_coin_a, key_coin_b; -reg key_tilt, key_test, key_reset, key_service, key_pause; - -reg key_p1_up, key_p1_left, key_p1_down, key_p1_right, key_p1_a, key_p1_b, key_p1_c; -reg key_p2_up, key_p2_left, key_p2_down, key_p2_right, key_p2_a, key_p2_b, key_p2_c; - -wire pressed = ps2_key[9]; - -always @(posedge clk_sys) begin - reg old_state; - old_state <= ps2_key[10]; - if ( old_state ^ ps2_key[10] ) begin - casex ( ps2_key[8:0] ) - 'h016 : key_start_1p <= pressed; // 1 - 'h01E : key_start_2p <= pressed; // 2 - 'h02E : key_coin_a <= pressed; // 5 - 'h036 : key_coin_b <= pressed; // 6 - 'h006 : key_test <= key_test ^ pressed; // f2 - 'h004 : key_reset <= pressed; // f3 - 'h046 : key_service <= pressed; // 9 - 'h02C : key_tilt <= pressed; // t - 'h04D : key_pause <= pressed; // p - - 'h175 : key_p1_up <= pressed; // up - 'h172 : key_p1_down <= pressed; // down - 'h16B : key_p1_left <= pressed; // left - 'h174 : key_p1_right <= pressed; // right - 'h014 : key_p1_a <= pressed; // lctrl - 'h011 : key_p1_b <= pressed; // lalt - 'h029 : key_p1_c <= pressed; // spacebar - - 'h02D : key_p2_up <= pressed; // r - 'h02B : key_p2_down <= pressed; // f - 'h023 : key_p2_left <= pressed; // d - 'h034 : key_p2_right <= pressed; // g - 'h01C : key_p2_a <= pressed; // a - 'h01B : key_p2_b <= pressed; // s - 'h015 : key_p2_c <= pressed; // q - endcase - end -end - -wire pll_locked; - -wire clk_sys; -wire turbo_68k = status[15]; -reg clk_3_5M, clk_7M, clk_10M, clk_14M; - -wire clk_70M; - -pll pll -( - .refclk(CLK_50M), - .rst(0), - .outclk_0(clk_sys), - .outclk_1(clk_70M), - .locked(pll_locked) -); - -assign SDRAM_CLK = clk_70M; - -localparam CLKSYS=70; - -reg [5:0] clk14_count; -reg [5:0] clk10_count; -reg [5:0] clk7_count; -reg [5:0] clk_3_5_count; - -always @ (posedge clk_sys ) begin - clk_10M <= 0; - if ( turbo_68k == 0 ) begin - // standard speed 20MHz = 10MHz 68k - case (clk10_count) - 1: clk_10M <= 1; - 3: clk_10M <= 1; - endcase - if ( clk10_count == 6 ) begin - clk10_count <= 0; - end else if ( pause_cpu == 0 ) begin - clk10_count <= clk10_count + 1; - end - end else begin - // standard speed 35MHz = 17.5MHz 68k - case (clk10_count) - 1: clk_10M <= 1; - endcase - if ( clk10_count == 1 ) begin - clk10_count <= 0; - end else if ( pause_cpu == 0 ) begin - clk10_count <= clk10_count + 1; - end - end - - clk_7M <= ( clk7_count == 0); - if ( clk7_count == 9 ) begin - clk7_count <= 0; - end else begin - clk7_count <= clk7_count + 1; - end - - clk_14M <= ( clk14_count == 0); - if ( clk14_count == 4 ) begin - clk14_count <= 0; - end else begin - clk14_count <= clk14_count + 1; - end - - clk_3_5M <= ( clk_3_5_count == 0); - if ( clk_3_5_count == 19 ) begin - clk_3_5_count <= 0; - end else if ( pause_cpu == 0 ) begin - clk_3_5_count <= clk_3_5_count + 1; - end -end - -wire reset; -assign reset = RESET | status[0] | (ioctl_download & !ioctl_index) | buttons[1] | key_reset; - -////////////////////////////////////////////////////////////////// -wire rotate_ccw = 1; -wire no_rotate = orientation | direct_video; -wire video_rotated; - -reg [23:0] rgb; - -wire hbl; -wire vbl; - -wire [8:0] hc; -wire [8:0] vc; - -wire hsync; -wire vsync; - -reg hbl_delay, vbl_delay; - -always @ ( posedge clk_7M ) begin - hbl_delay <= hbl; - vbl_delay <= vbl; -end - -video_timing video_timing ( - .clk(clk_7M), - .reset(reset), - .crtc0(crtc[0]), - .crtc1(crtc[1]), - .crtc2(crtc[2]), - .crtc3(crtc[3]), - .hs_offset(hs_offset), - .vs_offset(vs_offset), - .hs_width(hs_width), - .vs_width(vs_width), - .refresh_mod(refresh_mod), - .hc(hc), - .vc(vc), - .hbl_delay(hbl), - .vbl(vbl), - .hsync(hsync), - .vsync(vsync) -); - -// PAUSE SYSTEM -wire pause_cpu; -wire hs_pause; - -// 8 bits per colour, 70MHz sys clk -pause #(8,8,8,70) pause -( - .clk_sys(clk_sys), - .reset(reset), - .user_button(b_pause), - .pause_request(hs_pause), - .options(status[21:20]), - .pause_cpu(pause_cpu), - .dim_video(dim_video), - .OSD_STATUS(OSD_STATUS), - .r(rgb[23:16]), - .g(rgb[15:8]), - .b(rgb[7:0]), - .rgb_out(rgb_pause_out) -); - -wire [23:0] rgb_pause_out; -wire dim_video; - -arcade_video #(320,24) arcade_video -( - .*, - - .clk_video(clk_sys), - .ce_pix(clk_7M), - - .RGB_in(rgb_pause_out), - - .HBlank(hbl), - .VBlank(vbl), - .HSync(hsync), - .VSync(vsync), - - .fx(scan_lines) -); - -/* - Phase Accumulator Increments (Fractional Size 32, look up size 8 bit, total 40 bits) - Increment Calculation - (Output Clock * 2 ^ Word Size) / Reference Clock - Example - NTSC = 3.579545 - PAL = 4.43361875 - W = 40 ( 32 bit fraction, 8 bit look up reference) - Ref CLK = 42.954544 (This could us any clock) - NTSC_Inc = 3.579545333 * 2 ^ 40 / 96 = 40997413706 -*/ - -// SET PAL and NTSC TIMING -`ifdef MISTER_ENABLE_YC - assign CHROMA_PHASE_INC = PALFLAG ? 40'd56225080500: 40'd56225080500; - assign YC_EN = status[22]; - assign PALFLAG = status[7]; -`endif - -screen_rotate screen_rotate (.*); - -wire [9:0] sprite_adj_x = 0; -wire [9:0] sprite_adj_y = 0; -wire bcu_flip_cs; - -reg [1:0] adj_layer; -reg [15:0] scroll_adj_x [3:0]; -reg [15:0] scroll_adj_y [3:0]; -reg layer_en [3:0]; - -reg ce_pix; - -// flip is done in the rendering so leave screen_rotate flip off -wire flip = 0; - -reg tile_flip; - -//assign vc = vcx - vs_offset; - -// =============================================================== -// 68000 CPU -// =============================================================== - -// clock generation -reg fx68_phi1 = 0; -wire fx68_phi2 = !fx68_phi1; - -// phases for 68k clock -always @(posedge clk_sys) begin - if ( clk_10M == 1 ) begin - fx68_phi1 <= ~fx68_phi1; - end -end - -// CPU outputs -wire cpu_rw; // Read = 1, Write = 0 -wire cpu_as_n; // Address strobe -wire cpu_lds_n; // Lower byte strobe -wire cpu_uds_n; // Upper byte strobe -wire cpu_E; -wire [2:0]cpu_fc; // Processor state -wire cpu_reset_n_o; // Reset output signal -wire cpu_halted_n; // Halt output - -// CPU busses -wire [15:0] cpu_dout; -wire [23:0] cpu_a /* synthesis keep */; -reg [15:0] cpu_din; - -// CPU inputs -reg dtack_n; // Data transfer ack (always ready) -reg ipl2_n; - -wire reset_n; -wire vpa_n = ~ ( cpu_lds_n == 0 && cpu_fc == 3'b111 ); // from outzone schematic - -assign cpu_a[0] = reset; // debug hack odd memory address should cause cpu exception - -cc_shifter cc_reset ( - .clk_out(clk_10M), - .i(reset_z80_n & cpu_reset_n_o), - .o(reset_n) -); - -fx68k fx68k ( - // input - .clk( clk_10M ), - .enPhi1(fx68_phi1), - .enPhi2(fx68_phi2), - .extReset(reset), - .pwrUp(reset), - - // output - .eRWn(cpu_rw), - .ASn( cpu_as_n), - .LDSn(cpu_lds_n), - .UDSn(cpu_uds_n), -// .E(cpu_E), -// .VMAn(), - .FC0(cpu_fc[0]), - .FC1(cpu_fc[1]), - .FC2(cpu_fc[2]), -// .BGn(), - .oRESETn(cpu_reset_n_o), - .oHALTEDn(cpu_halted_n), - - // input - .VPAn( vpa_n ), - .DTACKn(dtack_n ), - .BERRn(1'b1), - .BRn(1'b1), - .BGACKn(1'b1), - - .IPL0n(1'b1), - .IPL1n(1'b1), - .IPL2n(ipl2_n), - - // busses - .iEdb(cpu_din), - .oEdb(cpu_dout), - .eab(cpu_a[23:1]) -); - -always @ (posedge clk_sys) begin - if ( clk_10M == 1 ) begin - // tell 68k to wait for valid data. 0=ready 1=wait - // always ack when it's not program rom - dtack_n <= prog_rom_cs ? !prog_rom_data_valid : 0; - // add dsp_ctrl_cs to cpu_din - // select cpu data input based on what is active - cpu_din <= prog_rom_cs ? prog_rom_data : - ram_cs ? ram_dout : - tile_palette_cs ? tile_palette_cpu_dout : - sprite_palette_cs ? sprite_palette_cpu_dout : - sprite_ram_cs ? sprite_ram_dout : - tile_ofs_cs ? curr_tile_ofs : - sprite_ofs_cs ? curr_sprite_ofs : - shared_ram_cs ? cpu_shared_dout : - tile_attr_cs ? ( cpu_tile_dout_attr | { 4'b0, cpu_tile_dout_attr[15:12], cpu_tile_dout_attr[5:4], 6'b0 } ) : - tile_num_cs ? cpu_tile_dout_num : - vblank_cs ? { 15'b0, vbl } : - int_en_cs ? { 15'b0, int_en } : - 16'hffff; - end -end - -wire [15:0] cpu_shared_dout; -wire [7:0] z80_shared_dout; -reg [15:0] z80_a; - -wire [15:0] z80_addr; -reg [7:0] z80_din; -wire [7:0] z80_dout; - -wire z80_wr_n; -wire z80_rd_n; -reg z80_wait_n; - -wire IORQ_n; -wire MREQ_n; - -always @ (posedge clk_sys) begin - if ( reset == 1 ) begin - z80_wait_n <= 0; - sound_wr <= 0; - end else if ( clk_3_5M == 1 ) begin - z80_wait_n <= 1; - if ( ioctl_download | ( z80_rd_n == 0 && sound_rom_1_data_valid == 0 && sound_rom_1_cs == 1 ) ) begin - // wait if rom is selected and data is not yet available - z80_wait_n <= 0; - end - - if ( z80_rd_n == 0 ) begin - if ( sound_rom_1_cs ) begin - if ( sound_rom_1_data_valid ) begin - z80_din <= sound_rom_1_data; - end else begin - z80_wait_n <= 0; - end - end else if ( sound_ram_1_cs ) begin - z80_din <= z80_shared_dout; - end else if ( z80_p1_cs ) begin - z80_din <= p1; - end else if ( z80_p2_cs ) begin - z80_din <= p2; - end else if ( z80_dswa_cs ) begin - z80_din <= z80_dswa; - end else if ( z80_dswb_cs ) begin - z80_din <= z80_dswb; - end else if ( z80_tjump_cs ) begin - z80_din <= z80_tjump; - end else if ( z80_system_cs ) begin - z80_din <= system; - end else if ( z80_sound0_cs ) begin - z80_din <= opl_dout; - end else begin - z80_din <= 8'h00; - end - end - - sound_wr <= 0; - if ( z80_wr_n == 0 ) begin - if ( z80_sound0_cs | z80_sound1_cs ) begin - sound_data <= z80_dout; - sound_addr <= { 1'b0, z80_sound1_cs }; // pad for opl3. opl2 is single bit address - sound_wr <= 1; - end - end - end -end - -reg [1:0] sound_addr; -reg [7:0] sound_data; -reg sound_wr; - -wire [7:0] opl_dout; -wire opl_irq_n; - -reg signed [15:0] sample; - -assign AUDIO_S = 1'b1; - -wire opl_sample_clk; - -jtopl #(.OPL_TYPE(2)) jtopl2 -( - .rst(~reset_n), - .clk(clk_sys), - .cen(clk_3_5M), - .din(sound_data), - .addr(sound_addr), - .cs_n('0), - .wr_n(~sound_wr), - .dout(opl_dout), - .irq_n(opl_irq_n), - .snd(sample), - .sample(opl_sample_clk) -); - -wire [1:0] opl2_level = status[44:43]; // opl2 audio mix - -reg [7:0] opl2_mult; - -// set the multiplier for each channel from menu - -always @( posedge clk_sys, posedge reset ) begin - if (reset) begin - opl2_mult<=0; - end else begin - case( opl2_level ) - 0: opl2_mult <= 8'h0c; // 75% - 1: opl2_mult <= 8'h08; // 50% - 2: opl2_mult <= 8'h04; // 25% - 3: opl2_mult <= 8'h00; // 0% - endcase - end -end - -wire signed [15:0] mono; - -jtframe_mixer #(.W0(16), .WOUT(16)) u_mix_mono( - .rst ( reset ), - .clk ( clk_sys ), - .cen ( 1'b1 ), - // input signals - .ch0 ( sample ), - .ch1 ( 16'd0 ), - .ch2 ( 16'd0 ), - .ch3 ( 16'd0 ), - // gain for each channel in 4.4 fixed point format - .gain0 ( opl2_mult ), - .gain1 ( 8'd0 ), - .gain2 ( 8'd0 ), - .gain3 ( 8'd0 ), - .mixed ( mono ), - .peak ( ) -); - -always @ (posedge clk_sys ) begin - if ( pause_cpu == 1 ) begin - AUDIO_L <= 0; - AUDIO_R <= 0; - end else if ( pause_cpu == 0 ) begin - // mix audio - AUDIO_L <= mono; - AUDIO_R <= mono; - end -end - -T80pa u_cpu( - .RESET_n ( reset_n ), - .CLK ( clk_sys ), - .CEN_p ( clk_3_5M ), - .CEN_n ( ~clk_3_5M ), - - .WAIT_n ( z80_wait_n ), // don't wait if data is valid or rom access isn't selected - .INT_n ( opl_irq_n ), // opl timer - .NMI_n ( 1'b1 ), - .BUSRQ_n ( 1'b1 ), - .RD_n ( z80_rd_n ), - .WR_n ( z80_wr_n ), - .A ( z80_addr ), - .DI ( z80_din ), - .DO ( z80_dout ), - // unused - .DIRSET ( 1'b0 ), - .DIR ( 212'b0 ), - .OUT0 ( 1'b0 ), - .RFSH_n (), - .IORQ_n ( IORQ_n ), - .M1_n (), - .BUSAK_n (), - .HALT_n ( 1'b1 ), - .MREQ_n ( MREQ_n ), - .Stop (), - .REG () -); - -// Chip select mux -wire prog_rom_cs; -wire scroll_ofs_x_cs; -wire scroll_ofs_y_cs; -wire ram_cs; -wire vblank_cs; -wire int_en_cs; -wire crtc_cs; -wire tile_ofs_cs; -wire tile_attr_cs; -wire tile_num_cs; -wire scroll_cs; -wire shared_ram_cs; -wire frame_done_cs; // word -wire tile_palette_cs; -wire sprite_palette_cs; -wire sprite_ofs_cs; -wire sprite_cs; // *** offset needs to be auto-incremented -wire sprite_size_cs; // *** offset needs to be auto-incremented -wire sprite_ram_cs; - -wire z80_p1_cs; -wire z80_p2_cs; -wire z80_dswa_cs; -wire z80_dswb_cs; -wire z80_system_cs; -wire z80_tjump_cs; -wire z80_sound0_cs; -wire z80_sound1_cs; - -chip_select cs (.*); - -wire sprite_0_cs = ( curr_sprite_ofs[1:0] == 2'b00 ) & sprite_cs; -wire sprite_1_cs = ( curr_sprite_ofs[1:0] == 2'b01 ) & sprite_cs; -wire sprite_2_cs = ( curr_sprite_ofs[1:0] == 2'b10 ) & sprite_cs; -wire sprite_3_cs = ( curr_sprite_ofs[1:0] == 2'b11 ) & sprite_cs; - -reg reset_z80_n; -wire reset_z80_cs; -wire sound_rom_1_cs = ( MREQ_n == 0 && z80_addr <= 16'h7fff ); -wire sound_ram_1_cs = ( MREQ_n == 0 && z80_addr >= 16'h8000 && z80_addr <= 16'h87ff ); - -reg int_en; -reg int_ack; - -reg [1:0] vbl_sr; - -// vblank interrupt on rising vbl -always @ (posedge clk_sys ) begin - if ( reset == 1 ) begin - ipl2_n <= 1; - int_ack <= 0; - end else begin - vbl_sr <= { vbl_sr[0], vbl }; - if ( clk_10M == 1 ) begin - int_ack <= ( cpu_as_n == 0 ) && ( cpu_fc == 3'b111 ); // cpu acknowledged the interrupt - end - if ( vbl_sr == 2'b01 ) begin// rising edge - ipl2_n <= ~int_en; - end else if ( int_ack == 1 || vbl_sr == 2'b10 ) begin - ipl2_n <= 1; - end - end -end - -reg [15:0] scroll_x [3:0]; -reg [15:0] scroll_y [3:0]; - -reg [15:0] scroll_x_latch [3:0]; -reg [15:0] scroll_y_latch [3:0]; - -reg inc_sprite_ofs; - -reg [15:0] crtc[4]; -reg [7:0] reset_counter; - -always @ (posedge clk_sys) begin - if ( reset == 1 ) begin - int_en <= 0; - reset_z80_n <= 1; - reset_counter <= 0; - end else begin - if ( reset_counter > 0 ) begin - reset_counter <= reset_counter - 1; - end else begin - reset_z80_n = 1; - end - // write asserted and rising cpu clock - if ( clk_10M == 1 && cpu_rw == 0 ) begin - if ( tile_ofs_cs ) begin - curr_tile_ofs <= cpu_dout; - end - - if ( int_en_cs ) begin - int_en <= cpu_dout[0]; - end - - if ( crtc_cs ) begin - crtc[ cpu_a[2:1] ] <= cpu_dout; - end - - if ( bcu_flip_cs ) begin - tile_flip <= cpu_dout[0]; - end - - if ( sprite_ofs_cs ) begin - // mask out valid range - curr_sprite_ofs <= { 6'b0, cpu_dout[9:0] }; - end - - if ( scroll_ofs_x_cs ) begin - scroll_ofs_x <= cpu_dout; - end - - if ( scroll_ofs_y_cs ) begin - scroll_ofs_y <= cpu_dout; - end - - // x layer values are even addresses - if ( scroll_cs ) begin - if ( cpu_a[1] == 0 ) begin - scroll_x[ cpu_a[3:2] ] <= cpu_dout[15:7]; - end else begin - scroll_y[ cpu_a[3:2] ] <= cpu_dout[15:7]; - end - end - - // offset needs to be auto-incremented - if ( sprite_cs | sprite_size_cs ) begin - inc_sprite_ofs <= 1; - end - - if ( reset_z80_cs ) begin - // the pcb writes to a latch to control the reset - if ( cpu_dout == 0 ) begin - reset_z80_n <= 0; - reset_counter <= 8'h3f; - end - end - end - - // write lasts multiple cpu clocks so limit to one increment per write signal - if ( inc_sprite_ofs == 1 && cpu_rw == 1 ) begin - curr_sprite_ofs <= curr_sprite_ofs + 1; - inc_sprite_ofs <= 0; - end - end -end - -reg [15:0] scroll_x_total [3:0]; -reg [15:0] scroll_y_total [3:0]; - -wire [15:0] ram_dout; -wire [9:0] tile_palette_addr; -wire [15:0] tile_palette_cpu_dout; -wire [15:0] tile_palette_dout; - -wire [9:0] sprite_palette_addr; -wire [15:0] sprite_palette_cpu_dout; -wire [15:0] sprite_palette_dout; - -reg [15:0] curr_tile_ofs; -reg [15:0] curr_sprite_ofs; - -reg [15:0] scroll_ofs_x; -reg [15:0] scroll_ofs_y; - -wire [15:0] cpu_tile_dout_attr; -wire [15:0] cpu_tile_dout_num; - -wire [31:0] tile_attr_dout; - -reg [15:0] sprite_buf_din; - -reg [14:0] tile; - -reg [8:0] sprite_num; -reg [8:0] sprite_num_copy; - -reg [3:0] tile_draw_state; - -reg [2:0] layer; // 4 layers + 1 for initial background - -wire [14:0] tile_idx = tile_attr[14:0]; -wire [3:0] tile_priority = tile_attr[31:28]; -wire [5:0] tile_palette_idx = tile_attr[21:16]; -wire tile_hidden = tile_attr[15]; - -reg [15:0] fb_dout; -wire [15:0] tile_fb_out; -wire [15:0] sprite_fb_out; -reg [15:0] fb_din; -reg [15:0] sprite_fb_din; - -reg tile_fb_w; -reg sprite_fb_w; -reg sprite_size_buf_w; - -dual_port_ram #(.LEN(1024), .DATA_WIDTH(16)) tile_line_buffer ( - .clock_a ( clk_sys ), - .address_a ( tile_fb_addr_w ), - .wren_a ( tile_fb_w ), - .data_a ( fb_din ), - .q_a ( ), - - .clock_b ( clk_sys ), - .address_b ( fb_addr_r ), - .wren_b ( 0 ), -// .data_b ( ), - .q_b ( tile_fb_out ) -); - -dual_port_ram #(.LEN(1024), .DATA_WIDTH(16)) sprite_line_buffer ( - .clock_a ( clk_sys ), - .address_a ( sprite_fb_addr_w ), - .wren_a ( sprite_fb_w ), - .data_a ( sprite_fb_din ), - .q_a ( ), - - .clock_b ( clk_sys ), - .address_b ( fb_addr_r ), - .wren_b ( 0 ), -// .data_b ( ), - .q_b ( sprite_fb_out ) -); - -reg [9:0] x_ofs; -reg [9:0] x; - -reg [9:0] y_ofs; - -// y needs to be one line ahaed of the visible line -// render the first line at the end of the previous frame -// this depends on the timing that the sprite list is valid -// sprites values are copied at the start of vblank (line 240) - -// global offsets -wire [9:0] x_ofs_dx = 495 + { ~layer[1:0], 1'b0 }; -wire [9:0] y_ofs_dx = 257; -wire [9:0] x_ofs_dx_flipped = 17 - { ~layer[1:0], 1'b0 }; -wire [9:0] y_ofs_dx_flipped = 255; - -// calculate scrolling -wire [9:0] tile_x_unflipped = scroll_x_latch[layer[1:0]] + x_ofs_dx + scroll_x_offset; -wire [9:0] tile_y_unflipped = scroll_y_latch[layer[1:0]] + y_ofs_dx + scroll_y_offset; - -wire [9:0] tile_x_flipped = ( scroll_x_latch[layer[1:0]] + x_ofs_dx_flipped + scroll_x_offset - 112); -wire [9:0] tile_y_flipped = ( scroll_y_latch[layer[1:0]] + y_ofs_dx_flipped + scroll_y_offset - 40 ); - -// reverse tiles when flipped -wire [9:0] curr_x = tile_flip ? ( tile_x_flipped - x ) : ( tile_x_unflipped + x ); -wire [9:0] curr_y = tile_flip ? ( tile_y_flipped - y ) : ( tile_y_unflipped + y ); - -reg sprite_flip_x; -reg sprite_flip_y; - -reg [9:0] y; -//wire [9:0] y_flipped = ( flip ? (240 - y ) : y ); -//wire [9:0] sprite_buf_x = flip ? 320 - (sprite_x + sprite_pos_x ) : sprite_x + sprite_pos_x; // offset from left of frame - -wire [9:0] y_flipped = y ; -wire [9:0] sprite_buf_x = tile_flip + ( sprite_flip_x ? (sprite_pos_x + ~sprite_x) : (sprite_pos_x + sprite_x) ) ; // offset from left of frame - -reg [3:0] draw_state; -reg [3:0] sprite_state; -reg [3:0] tile_copy_state; -reg [3:0] sprite_copy_state; - -// pixel 4 bit colour -wire [3:0] tile_pix; -assign tile_pix = { tile_data[7-curr_x[2:0]], tile_data[15-curr_x[2:0]], tile_data[23-curr_x[2:0]], tile_data[31-curr_x[2:0]] }; - -wire [2:0] sprite_bit = ~sprite_x[2:0]; -wire [3:0] sprite_pix; -assign sprite_pix = { sprite_data[sprite_bit], sprite_data[8+sprite_bit], sprite_data[16+sprite_bit], sprite_data[24+sprite_bit] }; - -// two lines of buffer alternate -reg [9:0] tile_fb_addr_w; -wire [9:0] fb_addr_r = {vc[0], 9'b0 } + hc; - -reg [9:0] sprite_fb_addr_w; - -reg [31:0] tile_attr; - -// two lines worth for 4 layers (~8k) -// [15:14] = layer. -// [13:10] = prioity -// [9:4] = palette offset -// [3:0] = tile colour index. - -reg [3:0] tile_priority_buf [327:0]; -reg [3:0] sprite_priority_buf [327:0]; - -reg [9:0] sprite_x; // offset from left side of sprite -reg [9:0] sprite_y; - -reg [7:0] sprite_buf_num; - - -reg [1:0] vtotal_282_flag; - -always @ (posedge clk_sys) begin // Check System Vcount flag for 60Hz mode - if ({crtc[2][7:0], 1'b1 } == 269) - vtotal_282_flag <= 0; - else - vtotal_282_flag <= 1; -end - -reg [10:0] sprite_index ;//= sprite_attr_dout[10:0]; -reg [5:0] sprite_pal_addr;//= sprite_attr_dout[5:0]; -reg [1:0] sprite_priority;//= sprite_attr_dout[11:10]; -reg [9:0] sprite_pos_x ;//= sprite_attr_dout[15:7]; -reg [9:0] sprite_pos_y ;//= sprite_attr_dout[15:7]; - -always @ (posedge clk_sys) begin - if ( reset == 1 ) begin - sprite_state <= 0; - draw_state <= 0; - tile_rom_cs <= 0; - tile_copy_state <= 0; - sprite_copy_state <= 0; - tile_draw_state <= 0; - sprite_flip_x <= 0 ; - sprite_flip_y <= 0 ; - end else begin - // render sprites - // triggered when the tile rendering starts - if ( sprite_state == 0 && draw_state > 0 ) begin - sprite_num <= 9'h000; - sprite_x <= 0; - sprite_fb_w <= 1; - sprite_state <= 1; - sprite_fb_din <= 0; - sprite_fb_addr_w <= { y[0], 9'b0 }; - end else if ( sprite_state == 1 ) begin - // erase line buffer - sprite_fb_addr_w <= { y[0], 9'b0 } + sprite_x; - sprite_priority_buf[sprite_x] <= 0; - if ( sprite_x < 320 ) begin - sprite_x <= sprite_x + 1; - end else begin - sprite_x <= 0; - sprite_fb_w <= 0; - sprite_state <= 2; - end -// sprite y could be read first so reading the rest -// could be skipped if not in range of the current scanline - end else if ( sprite_state == 2 ) begin - // sprite num is valid now - sprite_fb_w <= 0; - spritebuf_attr_addr <= { sprite_num, 2'b00 } ; // sprite num - sprite_state <= 3; - end else if ( sprite_state == 3 ) begin - spritebuf_attr_addr <= { sprite_num, 2'b01 } ; // sprite colour / priority - sprite_state <= 4; - end else if ( sprite_state == 4 ) begin - // sprite num ready - spritebuf_attr_addr <= { sprite_num, 2'b10 } ; // sprite x pos - sprite_index <= spritebuf_attr_dout[10:0]; - sprite_state <= 5; - end else if ( sprite_state == 5 ) begin - // sprite colour ready - spritebuf_attr_addr <= { sprite_num, 2'b11 } ; // sprite y pos - - sprite_pal_addr <= spritebuf_attr_dout[5:0] ; - sprite_flip_x <= spritebuf_attr_dout[8]; - sprite_flip_y <= spritebuf_attr_dout[9]; - sprite_priority <= spritebuf_attr_dout[11:10] ; - - sprite_state <= 6; - end else if ( sprite_state == 6 ) begin - // sprite x ready - sprite_pos_x <= spritebuf_attr_dout[15:7] - 31; - sprite_state <= 7; - end else if ( sprite_state == 7 ) begin - // sprite y ready - sprite_pos_y <= spritebuf_attr_dout[15:7] - 16; - if ( spritebuf_attr_dout[15:7] == 9'h100 ) begin - if ( sprite_num < 9'h1ff ) begin - sprite_num <= sprite_num + 1; - sprite_state <= 2; - end else begin - sprite_state <= 15; - end - end else begin - sprite_state <= 8; - end - end else if ( sprite_state == 8 ) begin - // start loop - sprite_fb_w <= 0; - sprite_y <= y_flipped - sprite_pos_y; - // is sprite visible and is current y in sprite y range - // sprite pos can be negative? - if ( ( $signed(y_flipped) >= $signed(sprite_pos_y) ) && $signed(y_flipped) < ( $signed(sprite_pos_y) + 16 ) ) begin - sprite_state <= 9; - end else if ( sprite_num < 9'h1ff ) begin - sprite_num <= sprite_num + 1; - sprite_state <= 2; - end else begin - sprite_state <= 15; - end - end else if ( sprite_state == 9 ) begin - if ( sprite_flip_y == 0 ) begin - sprite_rom_addr <= { sprite_index, sprite_y[3:0], sprite_x[3] }; - end else begin - sprite_rom_addr <= { sprite_index, ~sprite_y[3:0], sprite_x[3] }; - end - sprite_state <= 10; - end else if ( sprite_state == 10 ) begin - sprite_state <= 11; - end else if ( sprite_state == 11 ) begin - sprite_data <= sprite_rom_dout; - sprite_state <= 12; - end else if ( sprite_state == 12 ) begin - sprite_fb_w <= 0; - // draw if pixel value not zero and priority >= previous sprite data - if ( sprite_pix > 0 && sprite_priority >= sprite_priority_buf[sprite_buf_x] ) begin - sprite_fb_din <= { 2'b11, sprite_priority, 2'b00, sprite_pal_addr, sprite_pix }; - - sprite_fb_addr_w <= { y[0], sprite_buf_x[8:0] }; - sprite_priority_buf[sprite_buf_x] <= sprite_priority; - sprite_fb_w <= 1; - end - if ( sprite_x < 15 ) begin - sprite_x <= sprite_x + 1; - if ( sprite_x[2:0] == 7 ) begin - // do recalc bitmap address - sprite_state <= 9; - end - end else if ( sprite_num < 9'h1ff ) begin - sprite_num <= sprite_num + 1; - sprite_x <= 0; - // need to load new attributes and size - sprite_state <= 2; - end else begin - // tile state machine will reset sprite_state when line completes. - sprite_state <= 14; // done - end - end else if ( sprite_state == 14 ) begin - sprite_fb_w <= 0; - sprite_state <= 15; // done - end - - // copy tile ram and scroll info - // not sure if this is needed. need to check to see when tile ram is updated. - if ( tile_copy_state == 0 && vc == 240 ) begin - tile_copy_state <= 1; - end else begin - // copy scroll registers - scroll_x_latch[0] <= scroll_x[0] - scroll_ofs_x; - scroll_x_latch[1] <= scroll_x[1] - scroll_ofs_x; - scroll_x_latch[2] <= scroll_x[2] - scroll_ofs_x; - scroll_x_latch[3] <= scroll_x[3] - scroll_ofs_x; - scroll_y_latch[0] <= scroll_y[0] - scroll_ofs_y; - scroll_y_latch[1] <= scroll_y[1] - scroll_ofs_y; - scroll_y_latch[2] <= scroll_y[2] - scroll_ofs_y; - scroll_y_latch[3] <= scroll_y[3] - scroll_ofs_y; - end - - // copy sprite attr/size to buffer - // write is delayed one clock - if ( sprite_copy_state == 0 && vc == 240 ) begin - sprite_copy_state <= 1; - sprite_attr_w <= 0; - sprite_attr_addr <= 11'h000; - end else if ( sprite_copy_state == 1 ) begin - // sprite_attr_addr valid - sprite_attr_w <= 1; - sprite_copy_state <= 2; - end else if ( sprite_copy_state == 2 ) begin - // sprite_attr_dout valid and write enabled - sprite_attr_addr <= sprite_attr_addr + 1; - // wait for read from source - if ( sprite_attr_addr == 11'h7ff ) begin - sprite_attr_w <= 0; - sprite_copy_state <= 3; - end else begin - sprite_copy_state <= 1; - end - end else if ( sprite_copy_state == 3 ) begin - // wait for vc > 240 so copy isn't triggered again this frame - if ( vc > 240 ) begin - sprite_copy_state <= 0; - end - end - - // tile state machine - if ( draw_state == 0 && vc == ({ crtc[2][7:0], 1'b1 } - (status[19] ? (vtotal_282_flag ? 5'd19 : 4'd7) : 3'd0)) ) begin // 282 Lines standard (263 Lines for 60Hz) - layer <= 4; // layer 4 is layer 0 but draws hidden and transparent - y <= 0; - draw_state <= 2; - sprite_state <= 0; - end else if ( draw_state == 2 ) begin - x <= 0; - x_ofs <= scroll_x_latch[layer[1:0]]; - y_ofs <= scroll_y_latch[layer[1:0]]; - // latch offset info - draw_state <= 3; - tile_draw_state <= 0; - end else if ( draw_state == 3 ) begin - if ( tile_draw_state == 0 ) begin - tile <= { layer[1:0], curr_y[8:3], curr_x[8:3] }; // works - tile_draw_state <= 4'h1; - end else if ( tile_draw_state == 1 ) begin - tile_draw_state <= 2; - end else if ( tile_draw_state == 2 ) begin - // latch attribute - tile_attr <= tile_attr_dout; - if ( layer == 4 || tile_attr_dout[15] == 0 ) begin - tile_draw_state <= 3; - end else begin - if ( x < 320 ) begin// 319 - tile_draw_state <= 3; - // do we need to read another tile? - // last pixel of this tile changes based on flip direction - if ( curr_x[2:0] == ( tile_flip ? 0 : 7) ) begin - draw_state <= 3; - tile_draw_state <= 0; - end - x <= x + 1; - end else if ( layer > 0 ) begin - layer <= layer - 1; - tile_fb_w <= 0; - draw_state <= 2; - end else begin - // done - tile_draw_state <= 7; - tile_fb_w <= 0; - end - end - end else if ( tile_draw_state == 3 ) begin - // read bitmap info - tile_rom_cs <= 1; - tile_rom_addr <= { tile_idx, curr_y[2:0] }; - tile_draw_state <= 4; - end else if ( tile_draw_state == 4 ) begin - // wait for bitmap ram ready - if ( tile_rom_data_valid ) begin - // latch data and deassert cs - tile_data <= tile_rom_data; - tile_draw_state <= 5; - tile_rom_cs <= 0; - end - end else if ( tile_draw_state == 5 ) begin - tile_fb_w <= 0; - tile_fb_addr_w <= { y[0], 9'b0 } + x; - // force render of first layer. - // if layer == 4 then tile_pix == 0 is not transparent - // layer 4 is really layer 0 - if ( layer == 4 ) begin - tile_priority_buf[x] <= 0; //tile_pix == 0 ? 0 : tile_priority; - //fb_din <= { layer[1:0], tile_priority, tile_palette_idx, tile_pix }; - fb_din <= { layer[1:0], 4'b0, tile_palette_idx, tile_pix }; - tile_fb_w <= 1; - end else if (tile_hidden == 0 && tile_pix > 0 && tile_priority > 0 && tile_priority >= tile_priority_buf[x] ) begin - tile_priority_buf[x] <= tile_priority; - // if tile hidden then make the pallette index 0. ie transparent - fb_din <= { layer[1:0], tile_priority, tile_palette_idx, tile_pix }; - tile_fb_w <= 1; - end - if ( x < 320 ) begin// 319 - // do we need to read another tile? - // last pixel of this tile changes based on flip direction - if ( curr_x[2:0] == ( tile_flip ? 0 : 7) ) begin - draw_state <= 3; - tile_draw_state <= 0; - end - x <= x + 1; - end else if ( layer > 0 ) begin - layer <= layer - 1; - tile_fb_w <= 0; - draw_state <= 2; - end else begin - // done - tile_draw_state <= 7; - tile_fb_w <= 0; - end - end else if ( tile_draw_state == 7 ) begin - // wait for next line or quit - if ( y == 239 ) begin - draw_state <= 0; - end else if ( hc == (status[19] ? 9'd444 : 9'd449) ) begin // 450 Lines standard (445 Lines for NTSC standard 15.73kHz line freq) - y <= y + 1; - draw_state <= 2; - sprite_state <= 0; - layer <= 4; - end - end - end - end -end - -// render -reg draw_sprite; - -// two lines worth for 4 layers (~8k) -// [15:14] = layer. -// [13:10] = prioity -// [9:4] = palette offset -// [3:0] = tile colour index. - -// there are 10 70MHz cycles per pixel. clk7_count from 0-9 - -// dac values based on 120 ohm driver for the resistor dac and 75 ohm output. 4.7k, 2.2k, 1k, 470, 220 -// modeled in spice -wire [7:0] dac [0:31] = '{0,12,25,36,50,61,73,83,91,100,111,120,131,139,149,157,145,154,162,170,180,187,195,202,208,214,222,228,236,242,249,255}; - -always @ (posedge clk_sys) begin - if ( clk7_count == 4 ) begin - tile_palette_addr <= tile_fb_out[9:0]; - sprite_palette_addr <= sprite_fb_out[9:0]; - end else if ( clk7_count == 6 ) begin - // if palette index is zero then it's from layer 3 and is transparent render as blank (black). - rgb <= { dac[tile_palette_dout[4:0]], dac[tile_palette_dout[9:5]], dac[tile_palette_dout[14:10]] }; - // if not transparent and sprite is higher priority - if ( sprite_fb_out[3:0] > 0 && (sprite_fb_out[13:10] >= tile_fb_out[13:10]) ) begin - // draw sprite - rgb <= { dac[sprite_palette_dout[4:0]], dac[sprite_palette_dout[9:5]], dac[sprite_palette_dout[14:10]] }; - end - end -end - -// tile data buffer - -reg tile_buf_w; -reg [31:0] tile_buf_din; -reg [31:0] tile_buf_dout; -reg [13:0] tile_buf_addr; - -dual_port_ram #(.LEN(16384), .DATA_WIDTH(32)) ram_tile_buf ( - .clock_a ( clk_sys ), - .address_a ( tile[13:0] ), - .wren_a ( tile_buf_w ), - .data_a ( tile_attr_dout ), - - .clock_b ( clk_sys ), - .address_b ( tile[13:0] ), // only read the tile # for now - .wren_b ( 0 ), - .q_b ( tile_buf_dout ) -); - -// tile attribute ram. each tile attribute is 2 16bit words -// pppp ---- --cc cccc httt tttt tttt tttt = Tile number (0 - $7fff) -// indirect access through offset register -dual_port_ram #(.LEN(16384), .DATA_WIDTH(16)) ram_tile_h ( - .clock_a ( clk_10M ), - .address_a ( curr_tile_ofs ), - .wren_a ( tile_attr_cs & !cpu_rw ), - .data_a ( cpu_dout ), - .q_a ( cpu_tile_dout_attr ), - - .clock_b ( clk_sys ), - .address_b ( tile[13:0] ), // only read the tile # for now - .wren_b ( 0 ), - .q_b ( tile_attr_dout[31:16] ) -); - -dual_port_ram #(.LEN(16384), .DATA_WIDTH(16)) ram_tile_l ( - .clock_a ( clk_10M ), - .address_a ( curr_tile_ofs ), - .wren_a ( tile_num_cs & !cpu_rw ), - .data_a ( cpu_dout ), - .q_a ( cpu_tile_dout_num ), - - .clock_b ( clk_sys ), - .address_b ( tile[13:0] ), // only read the tile # for now - .wren_b ( 0 ), - .q_b ( tile_attr_dout[15:0] ) -); - -// tiles 1024 15 bit values. index is ( 6 bits from tile attribute, 4 bits from bitmap ) -// background palette ram low -// does this need to be byte addressable? -dual_port_ram #(.LEN(1024), .DATA_WIDTH(8)) tile_palram_l ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[10:1] ), - .wren_a ( tile_palette_cs & !cpu_rw & !cpu_lds_n), - .data_a ( cpu_dout[7:0] ), - .q_a ( tile_palette_cpu_dout[7:0] ), - - .clock_b ( clk_sys ), - .address_b ( tile_palette_addr ), - .wren_b ( 0 ), - .q_b ( tile_palette_dout[7:0] ) -); - -// background palette ram high -dual_port_ram #(.LEN(1024), .DATA_WIDTH(8)) tile_palram_h ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[10:1] ), - .wren_a ( tile_palette_cs & !cpu_rw & !cpu_uds_n), - .data_a ( cpu_dout[15:8] ), - .q_a ( tile_palette_cpu_dout[15:8] ), - - .clock_b ( clk_sys ), - .address_b ( tile_palette_addr ), - .wren_b ( 0 ), - .q_b ( tile_palette_dout[15:8] ) -); - -// sprite palette ram low -// does this need to be byte addressable? -dual_port_ram #(.LEN(1024), .DATA_WIDTH(8)) sprite_palram_l ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[10:1] ), - .wren_a ( sprite_palette_cs & !cpu_rw & !cpu_lds_n), - .data_a ( cpu_dout[7:0] ), - .q_a ( sprite_palette_cpu_dout[7:0] ), - - .clock_b ( clk_sys ), - .address_b ( sprite_palette_addr ), - .wren_b ( 0 ), - .q_b ( sprite_palette_dout[7:0] ) -); - -// background palette ram high -dual_port_ram #(.LEN(1024), .DATA_WIDTH(8)) sprite_palram_h ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[10:1] ), - .wren_a ( sprite_palette_cs & !cpu_rw & !cpu_uds_n), - .data_a ( cpu_dout[15:8] ), - .q_a ( sprite_palette_cpu_dout[15:8] ), - - .clock_b ( clk_sys ), - .address_b ( sprite_palette_addr ), - .wren_b ( 0 ), - .q_b ( sprite_palette_dout[15:8] ) -); - - -// main 68k ram low -dual_port_ram #(.LEN(16384), .DATA_WIDTH(8)) ram16kx8_L ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[14:1] ), - .wren_a ( !cpu_rw & ram_cs & !cpu_lds_n ), - .data_a ( cpu_dout[7:0] ), - .q_a ( ram_dout[7:0] ) -); - -// main 68k ram high -dual_port_ram #(.LEN(16384), .DATA_WIDTH(8)) ram16kx8_H ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[14:1] ), - .wren_a ( !cpu_rw & ram_cs & !cpu_uds_n ), - .data_a ( cpu_dout[15:8] ), - .q_a ( ram_dout[15:8] ) -); - - -//wire [15:0] z80_shared_addr = z80_addr - 16'h8000; -//wire [23:0] m68k_shard_addr = cpu_a - 24'h040000; - -// z80 and 68k shared ram -// 4k -dual_port_ram #(.LEN(4096), .DATA_WIDTH(8)) shared_ram ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[12:1] ), - .wren_a ( shared_ram_cs & !cpu_rw & !cpu_lds_n), - .data_a ( cpu_dout[7:0] ), - .q_a ( cpu_shared_dout[7:0] ), - - .clock_b ( clk_3_5M ), // z80 clock is 3.5M - .address_b ( z80_addr[11:0] ), - .data_b ( z80_dout ), - .wren_b ( sound_ram_1_cs & ~z80_wr_n ), - .q_b ( z80_shared_dout ) -); - -reg sprite_attr_w ; -reg [10:0] sprite_attr_addr; -wire [15:0] sprite_attr_dout; -wire [15:0] sprite_ram_dout; - -reg [10:0] spritebuf_attr_addr; -wire [15:0] spritebuf_attr_dout; - -dual_port_ram #(.LEN(2048), .DATA_WIDTH(8)) sprite_ram_l -( - .clock_a( clk_10M ), - .address_a( cpu_a[11:1] ), - .wren_a( sprite_ram_cs & !cpu_rw & !cpu_lds_n), - .data_a( cpu_dout[7:0] ), - .q_a( sprite_ram_dout[7:0] ), - - .clock_b( clk_sys ), - .address_b( sprite_attr_addr ), - .wren_b( 0 ), - .q_b( sprite_attr_dout[7:0] ) -); - -dual_port_ram #(.LEN(2048), .DATA_WIDTH(8)) sprite_ram_h -( - .clock_a( clk_10M ), - .address_a( cpu_a[11:1] ), - .wren_a( sprite_ram_cs & !cpu_rw & !cpu_uds_n), - .data_a( cpu_dout[15:8] ), - .q_a( sprite_ram_dout[15:8] ), - - .clock_b( clk_sys ), - .address_b( sprite_attr_addr ), - .wren_b( 0 ), - .q_b( sprite_attr_dout[15:8] ) -); - -dual_port_ram #(.LEN(2048), .DATA_WIDTH(16)) spritebuf_ram -( - .clock_a( clk_sys ), - .address_a( sprite_attr_addr ), - .wren_a( sprite_attr_w ), - .data_a( sprite_attr_dout ), - .q_a( ), - - .clock_b( clk_sys ), - .address_b( spritebuf_attr_addr ), - .wren_b( 0 ), - .q_b( spritebuf_attr_dout ) -); - - -reg [15:0] sprite_rom_addr ; -wire [31:0] sprite_rom_dout ; - -wire sprite_rom_w = ioctl_download & ioctl_wr & ( ioctl_index == 0 ); - -wire sbit0 = (ioctl_addr >= 24'h180000 && ioctl_addr < 24'h190000 ); -wire sbit1 = (ioctl_addr >= 24'h190000 && ioctl_addr < 24'h1a0000 ); -wire sbit2 = (ioctl_addr >= 24'h1a0000 && ioctl_addr < 24'h1b0000 ); -wire sbit3 = (ioctl_addr >= 24'h1b0000 && ioctl_addr < 24'h1c0000 ); - -dual_port_ram #(.LEN(65536), .DATA_WIDTH(8)) sprite_rom_0 -( - .clock_a( clk_sys ), - .address_a( ioctl_addr[15:0] ), - .wren_a( sprite_rom_w & sbit0 ), - .data_a( ioctl_dout ), - .q_a( ), - - .clock_b( clk_sys ), - .address_b( sprite_rom_addr ), - .wren_b( 0 ), - .q_b( sprite_rom_dout[7:0] ) -); - -dual_port_ram #(.LEN(65536), .DATA_WIDTH(8)) sprite_rom_1 -( - .clock_a ( clk_sys ), - .address_a ( ioctl_addr[15:0] ), - .wren_a( sprite_rom_w & sbit1 ), - .data_a ( ioctl_dout ), - .q_a ( ), - - .clock_b ( clk_sys ), - .address_b ( sprite_rom_addr ), - .wren_b ( 0 ), - .q_b ( sprite_rom_dout[15:8] ) -); - -dual_port_ram #(.LEN(65536), .DATA_WIDTH(8)) sprite_rom_2 -( - .clock_a ( clk_sys ), - .address_a ( ioctl_addr[15:0] ), - .wren_a( sprite_rom_w & sbit2 ), - .data_a ( ioctl_dout ), - .q_a ( ), - - .clock_b ( clk_sys ), - .address_b ( sprite_rom_addr ), - .wren_b ( 0 ), - .q_b ( sprite_rom_dout[23:16] ) -); - -dual_port_ram #(.LEN(65536), .DATA_WIDTH(8)) sprite_rom_3 -( - .clock_a ( clk_sys ), - .address_a ( ioctl_addr[15:0] ), - .wren_a( sprite_rom_w & sbit3 ), - .data_a ( ioctl_dout ), - .q_a ( ), - - .clock_b ( clk_sys ), - .address_b ( sprite_rom_addr ), - .wren_b ( 0 ), - .q_b ( sprite_rom_dout[31:24] ) -); - -reg [22:0] sdram_addr; -reg [31:0] sdram_data; -reg sdram_we; -reg sdram_req; - -wire sdram_ack; -wire sdram_valid; -wire [31:0] sdram_q; - -sdram #(.CLK_FREQ(70.0)) sdram -( - .reset(~pll_locked), - .clk(clk_sys), - - // controller interface - .addr(sdram_addr), - .data(sdram_data), - .we(sdram_we), - .req(sdram_req), - - .ack(sdram_ack), - .valid(sdram_valid), - .q(sdram_q), - - // SDRAM interface - .sdram_a(SDRAM_A), - .sdram_ba(SDRAM_BA), - .sdram_dq(SDRAM_DQ), - .sdram_cke(SDRAM_CKE), - .sdram_cs_n(SDRAM_nCS), - .sdram_ras_n(SDRAM_nRAS), - .sdram_cas_n(SDRAM_nCAS), - .sdram_we_n(SDRAM_nWE), - .sdram_dqml(SDRAM_DQML), - .sdram_dqmh(SDRAM_DQMH) -); - -wire prog_cache_rom_cs; -wire [22:0] prog_cache_addr; -wire [15:0] prog_cache_data; -wire prog_cache_valid; - -wire [15:0] prog_rom_data; -wire prog_rom_data_valid; - -reg tile_rom_cs; -reg [17:0] tile_rom_addr; -wire [31:0] tile_rom_data; -wire tile_rom_data_valid; - -wire tile_cache_cs; -wire [17:0] tile_cache_addr; -wire [31:0] tile_cache_data; -wire tile_cache_valid; - -reg [31:0] tile_data; - -//wire sprite_rom_cs; -//wire [17:0] sprite_rom_addr; -//wire [31:0] sprite_rom_data; -//wire sprite_rom_data_valid; - -reg [31:0] sprite_data; - -wire [15:0] sound_rom_1_addr; -wire [7:0] sound_rom_1_data; -wire sound_rom_1_data_valid; - -// sdram priority based rom controller -// is a oe needed? -rom_controller rom_controller -( - .reset(reset), - - // clock - .clk(clk_sys), - - // program ROM interface - .prog_rom_cs(prog_cache_rom_cs), - .prog_rom_oe(1), - .prog_rom_addr(prog_cache_addr), - .prog_rom_data(prog_cache_data), - .prog_rom_data_valid(prog_cache_valid), - - // character ROM interface - .tile_rom_cs(tile_cache_cs), - .tile_rom_oe(1), - .tile_rom_addr(tile_cache_addr), - .tile_rom_data(tile_cache_data), - .tile_rom_data_valid(tile_cache_valid), - - - // sprite ROM interface -// .sprite_rom_cs(sprite_rom_cs), -// .sprite_rom_oe(1), -// .sprite_rom_addr(sprite_rom_addr), -// .sprite_rom_data(sprite_rom_data), -// .sprite_rom_data_valid(sprite_rom_data_valid), - - // sound ROM #1 interface - .sound_rom_1_cs(sound_rom_1_cs), - .sound_rom_1_oe(1), - .sound_rom_1_addr(z80_addr), - .sound_rom_1_data(sound_rom_1_data), - .sound_rom_1_data_valid(sound_rom_1_data_valid), - - // IOCTL interface - .ioctl_addr(ioctl_addr), - .ioctl_data(ioctl_dout), - .ioctl_index(ioctl_index), - .ioctl_wr(ioctl_wr), - .ioctl_download(ioctl_download), - - // SDRAM interface - .sdram_addr(sdram_addr), - .sdram_data(sdram_data), - .sdram_we(sdram_we), - .sdram_req(sdram_req), - .sdram_ack(sdram_ack), - .sdram_valid(sdram_valid), - .sdram_q(sdram_q) -); - - -cache prog_cache -( - .reset(reset), - .clk(clk_sys), - - // client - .cache_req(prog_rom_cs), - .cache_addr(cpu_a[23:1]), - .cache_valid(prog_rom_data_valid), - .cache_data(prog_rom_data), - - // to rom controller - .rom_req(prog_cache_rom_cs), - .rom_addr(prog_cache_addr), - .rom_valid(prog_cache_valid), - .rom_data(prog_cache_data) -); - -tile_cache tile_cache -( - .reset(reset), - .clk(clk_sys), - - // client - .cache_req(tile_rom_cs), - .cache_addr(tile_rom_addr), - .cache_data(tile_rom_data), - .cache_valid(tile_rom_data_valid), - - // to rom controller - .rom_req(tile_cache_cs), - .rom_addr(tile_cache_addr), - .rom_data(tile_cache_data), - .rom_valid(tile_cache_valid) -); - -endmodule - - -module cc_shifter -( - input clk_out, - input i, - output o -); - -// We use a two-stages shift-register to synchronize SignalIn_clkA to the clkB clock domain -reg [1:0] r; - -assign o = r[1]; // new signal synchronized to (=ready to be used in) clkB domain - -always @(posedge clk_out) begin - r[0] <= i; - r[1] <= r[0]; // notice that we use clkB -end - -endmodule - - diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_vimana/vimanas.sv b/Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_vimana/vimanas.sv deleted file mode 100644 index 6d435793..00000000 --- a/Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_vimana/vimanas.sv +++ /dev/null @@ -1,2089 +0,0 @@ -//============================================================================ -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -// -//============================================================================ - -`default_nettype none - -module emu -( - //Master input clock - input CLK_50M, - - //Async reset from top-level module. - //Can be used as initial reset. - input RESET, - - //Must be passed to hps_io module - inout [48:0] HPS_BUS, - - //Base video clock. Usually equals to CLK_SYS. - output CLK_VIDEO, - - //Multiple resolutions are supported using different CE_PIXEL rates. - //Must be based on CLK_VIDEO - output CE_PIXEL, - - //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. - //if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio. - output [12:0] VIDEO_ARX, - output [12:0] VIDEO_ARY, - - output [7:0] VGA_R, - output [7:0] VGA_G, - output [7:0] VGA_B, - output VGA_HS, - output VGA_VS, - output VGA_DE, // = ~(VBlank | HBlank) - output VGA_F1, - output [2:0] VGA_SL, - output VGA_SCALER, // Force VGA scaler - - input [11:0] HDMI_WIDTH, - input [11:0] HDMI_HEIGHT, - output HDMI_FREEZE, - -`ifdef MISTER_FB - // Use framebuffer in DDRAM (USE_FB=1 in qsf) - // FB_FORMAT: - // [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp - // [3] : 0=16bits 565 1=16bits 1555 - // [4] : 0=RGB 1=BGR (for 16/24/32 modes) - // - // FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes) - output FB_EN, - output [4:0] FB_FORMAT, - output [11:0] FB_WIDTH, - output [11:0] FB_HEIGHT, - output [31:0] FB_BASE, - output [13:0] FB_STRIDE, - input FB_VBL, - input FB_LL, - output FB_FORCE_BLANK, - -`ifdef MISTER_FB_PALETTE - // Palette control for 8bit modes. - // Ignored for other video modes. - output FB_PAL_CLK, - output [7:0] FB_PAL_ADDR, - output [23:0] FB_PAL_DOUT, - input [23:0] FB_PAL_DIN, - output FB_PAL_WR, -`endif -`endif - - output LED_USER, // 1 - ON, 0 - OFF. - - // b[1]: 0 - LED status is system status OR'd with b[0] - // 1 - LED status is controled solely by b[0] - // hint: supply 2'b00 to let the system control the LED. - output [1:0] LED_POWER, - output [1:0] LED_DISK, - - // I/O board button press simulation (active high) - // b[1]: user button - // b[0]: osd button - output [1:0] BUTTONS, - - //Audio - input CLK_AUDIO, // 24.576 MHz - output [15:0] AUDIO_L, - output [15:0] AUDIO_R, - output AUDIO_S, // 1 - signed audio samples, 0 - unsigned - output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono) - - //ADC - inout [3:0] ADC_BUS, - - //SD-SPI - output SD_SCK, - output SD_MOSI, - input SD_MISO, - output SD_CS, - input SD_CD, - - //High latency DDR3 RAM interface - //Use for non-critical time purposes - output DDRAM_CLK, - input DDRAM_BUSY, - output [7:0] DDRAM_BURSTCNT, - output [28:0] DDRAM_ADDR, - input [63:0] DDRAM_DOUT, - input DDRAM_DOUT_READY, - output DDRAM_RD, - output [63:0] DDRAM_DIN, - output [7:0] DDRAM_BE, - output DDRAM_WE, - - //SDRAM interface with lower latency - output SDRAM_CLK, - output SDRAM_CKE, - output [12:0] SDRAM_A, - output [1:0] SDRAM_BA, - inout [15:0] SDRAM_DQ, - output SDRAM_DQML, - output SDRAM_DQMH, - output SDRAM_nCS, - output SDRAM_nCAS, - output SDRAM_nRAS, - output SDRAM_nWE, - -`ifdef MISTER_DUAL_SDRAM - //Secondary SDRAM - //Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0 - input SDRAM2_EN, - output SDRAM2_CLK, - output [12:0] SDRAM2_A, - output [1:0] SDRAM2_BA, - inout [15:0] SDRAM2_DQ, - output SDRAM2_nCS, - output SDRAM2_nCAS, - output SDRAM2_nRAS, - output SDRAM2_nWE, -`endif - - input UART_CTS, - output UART_RTS, - input UART_RXD, - output UART_TXD, - output UART_DTR, - input UART_DSR, - -`ifdef MISTER_ENABLE_YC - output [39:0] CHROMA_PHASE_INC, - output YC_EN, - output PALFLAG, -`endif - - // Open-drain User port. - // 0 - D+/RX - // 1 - D-/TX - // 2..6 - USR2..USR6 - // Set USER_OUT to 1 to read from USER_IN. - input [6:0] USER_IN, - output [6:0] USER_OUT, - - input OSD_STATUS -); - -///////// Default values for ports not used in this core ///////// - -assign ADC_BUS = 'Z; -assign USER_OUT = 0; -assign {UART_RTS, UART_TXD, UART_DTR} = 0; -assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; -//assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z; -//assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0; -assign VGA_F1 = 0; -assign VGA_SCALER = 0; -assign HDMI_FREEZE = 0; - -assign AUDIO_MIX = 0; -assign LED_USER = ioctl_download & cpu_a[0]; -assign LED_DISK = 0; -assign LED_POWER = 0; -assign BUTTONS = 0; - -// Status Bit Map: -// Upper Case Lower Case -// 0 1 2 3 4 5 6 -// 01234567890123456789012345678901 23456789012345678901234567890123 -// 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV -// X XXXXXXXX XX X X XXXXXXXX X XX XXXXXXXX - -wire [1:0] aspect_ratio = status[9:8]; -wire orientation = ~status[3]; -wire [2:0] scan_lines = status[6:4]; -reg refresh_mod; -reg new_vmode; - -always @(posedge clk_sys) begin - if (refresh_mod != status[19]) begin - refresh_mod <= status[19]; - new_vmode <= ~new_vmode; - end -end - -wire [3:0] hs_offset = status[27:24]; -wire [3:0] vs_offset = status[31:28]; -wire [3:0] hs_width = status[59:56]; -wire [3:0] vs_width = status[63:60]; - -assign VIDEO_ARX = (!aspect_ratio) ? (orientation ? 8'd4 : 8'd3) : (aspect_ratio - 1'd1); -assign VIDEO_ARY = (!aspect_ratio) ? (orientation ? 8'd3 : 8'd4) : 12'd0; - -`include "build_id.v" -localparam CONF_STR = { - "Toaplan V1;;", - "-;", - "P1,Video Settings;", - "P1-;", - "P1O89,Aspect Ratio,Original,Full Screen,[ARC1],[ARC2];", - "P1O3,Orientation,Horz,Vert;", - "P1-;", - "P1O46,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%,CRT 100%;", - "P1OA,Force Scandoubler,Off,On;", - "P1-;", - "P1O7,Video Mode,NTSC,PAL;", - "P1OM,Video Signal,RGBS/YPbPr,Y/C;", - "P1OJ,Refresh Rate,Native,NTSC;", - "P1-;", - "P1OOR,H-sync Pos Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", - "P1OSV,V-sync Pos Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", - "P1-;", - "P1oOR,H-sync Width Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", - "P1oSV,V-sync Width Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", - "P1-;", - "P2,Audio Settings;", - "P2-;", - "P2oBC,OPL2 Volume,Default,50%,25%,0%;", - "P2-;", - "-;", - "P3,Core Options;", - "P3-;", - "P3o6,Swap P1/P2 Joystick,Off,On;", - "P3-;", - "P3OF,68k Freq.,10Mhz,17.5MHz;", - "P3-;", - "P3o0,Scroll Debug,Off,On;", - "P3-;", - "DIP;", - "-;", - "OK,Pause OSD,Off,When Open;", - "OL,Dim Video,Off,10s;", - "-;", - "R0,Reset;", - "V,v",`BUILD_DATE -}; - -wire hps_forced_scandoubler; -wire forced_scandoubler = hps_forced_scandoubler | status[10]; - -wire [1:0] buttons; -wire [63:0] status; -wire [10:0] ps2_key; -wire [15:0] joy0, joy1; - -hps_io #(.CONF_STR(CONF_STR)) hps_io -( - .clk_sys(clk_sys), - .HPS_BUS(HPS_BUS), - - .buttons(buttons), - .ps2_key(ps2_key), - .status(status), - .status_menumask(direct_video), - .forced_scandoubler(hps_forced_scandoubler), - .gamma_bus(gamma_bus), - .new_vmode(new_vmode), - .direct_video(direct_video), - .video_rotated(video_rotated), - - .ioctl_download(ioctl_download), - .ioctl_upload(ioctl_upload), - .ioctl_wr(ioctl_wr), - .ioctl_addr(ioctl_addr), - .ioctl_dout(ioctl_dout), - .ioctl_din(ioctl_din), - .ioctl_index(ioctl_index), - .ioctl_wait(ioctl_wait), - - .joystick_0(joy0), - .joystick_1(joy1) -); - -// INPUT - -// 8 dip switches of 8 bits -reg [7:0] sw[8]; -always @(posedge clk_sys) begin - if (ioctl_wr && (ioctl_index==254) && !ioctl_addr[24:3]) begin - sw[ioctl_addr[2:0]] <= ioctl_dout; - end -end - -always @(posedge clk_sys) begin - if (ioctl_wr && ioctl_index==1) begin - pcb <= ioctl_dout; - end -end - -wire direct_video; - -wire ioctl_download; -wire ioctl_upload; -wire ioctl_upload_req; -wire ioctl_wait; -wire ioctl_wr; -wire [15:0] ioctl_index; -wire [26:0] ioctl_addr; -wire [15:0] ioctl_dout; -wire [15:0] ioctl_din; - -reg [1:0] pcb; -wire tile_priority_type; -wire [15:0] scroll_y_offset; - -localparam pcb_vimana = 0; -localparam pcb_samesame = 1; - -wire [21:0] gamma_bus; - -// -// Inputs tied to z80_din -reg [7:0] p1; -reg [7:0] p2; -reg [7:0] z80_dswa; -reg [7:0] z80_dswb; -reg [7:0] z80_tjump; -reg [7:0] system; - -always @ (posedge clk_sys ) begin - p1 <= { 1'b0, p1_buttons[2:0], p1_right, p1_left, p1_down, p1_up }; - p2 <= { 1'b0, p2_buttons[2:0], p2_right, p2_left, p2_down, p2_up }; - z80_dswa <= sw[0]; - z80_tjump <= sw[2]; - - if ( status[32] == 1 ) begin - z80_dswb <= { sw[1][7], sw[1][6] | status[32], sw[1][5:0] }; - system <= { vbl, start2 | p1_buttons[3], start1 | p1_buttons[3], coin_b, coin_a, service, key_tilt, key_service }; - end else begin - z80_dswb <= sw[1]; - system <= { vbl, start2, start1, coin_b, coin_a, service, key_tilt, key_service }; - end -end - -reg p1_swap; - -reg p1_right; -reg p1_left; -reg p1_down; -reg p1_up; -reg [3:0] p1_buttons; - -reg p2_right; -reg p2_left; -reg p2_down; -reg p2_up; -reg [3:0] p2_buttons; - -reg start1; -reg start2; -reg coin_a; -reg coin_b; -reg b_pause; -reg service; -reg [7:0] credits; - -always @ * begin - p1_swap <= status[38]; - - if ( status[38] == 0 ) begin - p1_right <= joy0[0] | key_p1_right; - p1_left <= joy0[1] | key_p1_left; - p1_down <= joy0[2] | key_p1_down; - p1_up <= joy0[3] | key_p1_up; - p1_buttons <= joy0[7:4] | {key_p1_c, key_p1_b, key_p1_a}; - - p2_right <= joy1[0] | key_p2_right; - p2_left <= joy1[1] | key_p2_left; - p2_down <= joy1[2] | key_p2_down; - p2_up <= joy1[3] | key_p2_up; - p2_buttons <= joy1[7:4] | {key_p2_c, key_p2_b, key_p2_a}; - end else begin - p2_right <= joy0[0] | key_p1_right; - p2_left <= joy0[1] | key_p1_left; - p2_down <= joy0[2] | key_p1_down; - p2_up <= joy0[3] | key_p1_up; - p2_buttons <= joy0[7:4] | {key_p1_c, key_p1_b, key_p1_a}; - - p1_right <= joy1[0] | key_p2_right; - p1_left <= joy1[1] | key_p2_left; - p1_down <= joy1[2] | key_p2_down; - p1_up <= joy1[3] | key_p2_up; - p1_buttons <= joy1[7:4] | {key_p2_c, key_p2_b, key_p2_a}; - end -end - -always @ * begin - start1 <= joy0[8] | joy1[8] | key_start_1p; - start2 <= joy0[9] | joy1[9] | key_start_2p; - - coin_a <= joy0[10] | joy1[10] | key_coin_a; - coin_b <= joy0[11] | joy1[11] | key_coin_b; - - b_pause <= joy0[12] | key_pause; - service <= key_test; -end - -// Keyboard handler - -reg key_start_1p, key_start_2p, key_coin_a, key_coin_b; -reg key_tilt, key_test, key_reset, key_service, key_pause; - -reg key_p1_up, key_p1_left, key_p1_down, key_p1_right, key_p1_a, key_p1_b, key_p1_c; -reg key_p2_up, key_p2_left, key_p2_down, key_p2_right, key_p2_a, key_p2_b, key_p2_c; - -wire pressed = ps2_key[9]; - -always @(posedge clk_sys) begin - reg old_state; - old_state <= ps2_key[10]; - if ( old_state ^ ps2_key[10] ) begin - casex ( ps2_key[8:0] ) - 'h016 : key_start_1p <= pressed; // 1 - 'h01E : key_start_2p <= pressed; // 2 - 'h02E : key_coin_a <= pressed; // 5 - 'h036 : key_coin_b <= pressed; // 6 - 'h006 : key_test <= key_test ^ pressed; // f2 - 'h004 : key_reset <= pressed; // f3 - 'h046 : key_service <= pressed; // 9 - 'h02C : key_tilt <= pressed; // t - 'h04D : key_pause <= pressed; // p - - 'h175 : key_p1_up <= pressed; // up - 'h172 : key_p1_down <= pressed; // down - 'h16B : key_p1_left <= pressed; // left - 'h174 : key_p1_right <= pressed; // right - 'h014 : key_p1_a <= pressed; // lctrl - 'h011 : key_p1_b <= pressed; // lalt - 'h029 : key_p1_c <= pressed; // spacebar - - 'h02D : key_p2_up <= pressed; // r - 'h02B : key_p2_down <= pressed; // f - 'h023 : key_p2_left <= pressed; // d - 'h034 : key_p2_right <= pressed; // g - 'h01C : key_p2_a <= pressed; // a - 'h01B : key_p2_b <= pressed; // s - 'h015 : key_p2_c <= pressed; // q - endcase - end -end - -wire pll_locked; - -wire clk_sys; -wire turbo_68k = status[15]; -reg clk_3_5M, clk_7M, clk_10M, clk_14M; - -wire clk_70M; - -pll pll -( - .refclk(CLK_50M), - .rst(0), - .outclk_0(clk_sys), - .outclk_1(clk_70M), - .locked(pll_locked) -); - -assign SDRAM_CLK = clk_70M; - -localparam CLKSYS=70; - -reg [5:0] clk14_count; -reg [5:0] clk10_count; -reg [5:0] clk7_count; -reg [5:0] clk_3_5_count; - -always @ (posedge clk_sys ) begin - clk_10M <= 0; - if ( turbo_68k == 0 ) begin - // standard speed 20MHz = 10MHz 68k - case (clk10_count) - 1: clk_10M <= 1; - 3: clk_10M <= 1; - endcase - if ( clk10_count == 6 ) begin - clk10_count <= 0; - end else if ( pause_cpu == 0 ) begin - clk10_count <= clk10_count + 1; - end - end else begin - // standard speed 35MHz = 17.5MHz 68k - case (clk10_count) - 1: clk_10M <= 1; - endcase - if ( clk10_count == 1 ) begin - clk10_count <= 0; - end else if ( pause_cpu == 0 ) begin - clk10_count <= clk10_count + 1; - end - end - clk_7M <= ( clk7_count == 0); - if ( clk7_count == 9 ) begin - clk7_count <= 0; - end else begin - clk7_count <= clk7_count + 1; - end - clk_14M <= ( clk14_count == 0); - if ( clk14_count == 4 ) begin - clk14_count <= 0; - end else begin - clk14_count <= clk14_count + 1; - end - clk_3_5M <= ( clk_3_5_count == 0); - if ( clk_3_5_count == 19 ) begin - clk_3_5_count <= 0; - end else if ( pause_cpu == 0 ) begin - clk_3_5_count <= clk_3_5_count + 1; - end -end - -wire reset; -assign reset = RESET | status[0] | (ioctl_download & !ioctl_index) | buttons[1] | key_reset; - -////////////////////////////////////////////////////////////////// -wire rotate_ccw = 1; -wire no_rotate = orientation | direct_video; -wire video_rotated; - -reg [23:0] rgb; - -wire hbl; -wire vbl; - -wire [8:0] hc; -wire [8:0] vc; - -wire hsync; -wire vsync; - -reg hbl_delay, vbl_delay; - -always @ ( posedge clk_7M ) begin - hbl_delay <= hbl; - vbl_delay <= vbl; -end - -video_timing video_timing ( - .clk(clk_7M), - .reset(reset), - .crtc0(crtc[0]), - .crtc1(crtc[1]), - .crtc2(crtc[2]), - .crtc3(crtc[3]), - .hs_offset(hs_offset), - .vs_offset(vs_offset), - .hs_width(hs_width), - .vs_width(vs_width), - .refresh_mod(refresh_mod), - .hc(hc), - .vc(vc), - .hbl_delay(hbl), - .vbl(vbl), - .hsync(hsync), - .vsync(vsync) -); - -// PAUSE SYSTEM -wire pause_cpu; -wire hs_pause; - -// 8 bits per colour, 70MHz sys clk -pause #(8,8,8,70) pause -( - .clk_sys(clk_sys), - .reset(reset), - .user_button(b_pause), - .pause_request(hs_pause), - .options(status[21:20]), - .pause_cpu(pause_cpu), - .dim_video(dim_video), - .OSD_STATUS(OSD_STATUS), - .r(rgb[23:16]), - .g(rgb[15:8]), - .b(rgb[7:0]), - .rgb_out(rgb_pause_out) -); - -wire [23:0] rgb_pause_out; -wire dim_video; - -arcade_video #(320,24) arcade_video -( - .*, - - .clk_video(clk_sys), - .ce_pix(clk_7M), - - .RGB_in(rgb_pause_out), - - .HBlank(hbl), - .VBlank(vbl), - .HSync(hsync), - .VSync(vsync), - - .fx(scan_lines) -); - -/* - Phase Accumulator Increments (Fractional Size 32, look up size 8 bit, total 40 bits) - Increment Calculation - (Output Clock * 2 ^ Word Size) / Reference Clock - Example - NTSC = 3.579545 - PAL = 4.43361875 - W = 40 ( 32 bit fraction, 8 bit look up reference) - Ref CLK = 42.954544 (This could us any clock) - NTSC_Inc = 3.579545333 * 2 ^ 40 / 96 = 40997413706 -*/ - -// SET PAL and NTSC TIMING -`ifdef MISTER_ENABLE_YC - assign CHROMA_PHASE_INC = PALFLAG ? 40'd56225080500: 40'd56225080500; - assign YC_EN = status[22]; - assign PALFLAG = status[7]; -`endif - -screen_rotate screen_rotate (.*); - -wire [9:0] sprite_adj_x = 0; -wire [9:0] sprite_adj_y = 0; -wire bcu_flip_cs; -wire fcu_flip_cs; - -reg [1:0] adj_layer; -reg [15:0] scroll_adj_x [3:0]; -reg [15:0] scroll_adj_y [3:0]; -reg layer_en [3:0]; - -reg ce_pix; - -// flip is done in the rendering so leave screen_rotate flip off -wire flip = 0; - -reg tile_flip; -reg sprite_flip; - -//assign vc = vcx - vs_offset; - -// =============================================================== -// 68000 CPU -// =============================================================== - -// clock generation -reg fx68_phi1 = 0; -wire fx68_phi2 = !fx68_phi1; - -// phases for 68k clock -always @(posedge clk_sys) begin - if ( clk_10M == 1 ) begin - fx68_phi1 <= ~fx68_phi1; - end -end - -// CPU outputs -wire cpu_rw; // Read = 1, Write = 0 -wire cpu_as_n; // Address strobe -wire cpu_lds_n; // Lower byte strobe -wire cpu_uds_n; // Upper byte strobe -wire cpu_E; -wire [2:0]cpu_fc; // Processor state -wire cpu_reset_n_o; // Reset output signal -wire cpu_halted_n; // Halt output - -// CPU busses -wire [15:0] cpu_dout; -wire [23:0] cpu_a /* synthesis keep */; -reg [15:0] cpu_din; - -// CPU inputs -reg dtack_n; // Data transfer ack (always ready) - -reg ipl1_n; -reg ipl2_n; - -wire reset_n; -wire vpa_n = ~ ( cpu_lds_n == 0 && cpu_fc == 3'b111 ); // from outzone schematic - -assign cpu_a[0] = reset; // debug hack odd memory address should cause cpu exception - -cc_shifter cc_reset ( - .clk_out(clk_10M), - .i(reset_z80_n), - .o(reset_n) -); - -fx68k fx68k ( - // input - .clk( clk_10M ), - .enPhi1(fx68_phi1), - .enPhi2(fx68_phi2), - .extReset(reset), - .pwrUp(reset), - - // output - .eRWn(cpu_rw), - .ASn( cpu_as_n), - .LDSn(cpu_lds_n), - .UDSn(cpu_uds_n), -// .E(cpu_E), -// .VMAn(), - .FC0(cpu_fc[0]), - .FC1(cpu_fc[1]), - .FC2(cpu_fc[2]), -// .BGn(), - .oRESETn(cpu_reset_n_o), - .oHALTEDn(cpu_halted_n), - - // input - .VPAn( vpa_n ), - .DTACKn(dtack_n ), - .BERRn(1'b1), - .BRn(1'b1), - .BGACKn(1'b1), - - .IPL0n(1'b1), - .IPL1n(ipl1_n), - .IPL2n(ipl2_n), - - // busses - .iEdb(cpu_din), - .oEdb(cpu_dout), - .eab(cpu_a[23:1]) -); - - - -always @ (posedge clk_sys) begin -end - -wire [15:0] cpu_shared_dout; -wire [7:0] z80_shared_dout; -reg [15:0] z80_a; - -wire [15:0] z80_addr; -reg [7:0] z80_din; -wire [7:0] z80_dout; - -wire z80_wr_n; -wire z80_rd_n; -reg z80_wait_n; - -wire IORQ_n; -wire MREQ_n; - -always @ (posedge clk_sys) begin - if ( reset == 1 ) begin - z80_wait_n <= 0; - sound_wr <= 0; - int_en <= 1; - reset_z80_n <= 1; - - end else begin - reset_z80_n <= cpu_reset_n_o; - - // write lasts multiple cpu clocks so limit to one increment per write signal - if ( inc_sprite_ofs == 1 && cpu_rw == 1 ) begin - curr_sprite_ofs <= curr_sprite_ofs + 1; - inc_sprite_ofs <= 0; - end - - if ( clk_10M == 1 ) begin - // tell 68k to wait for valid data. 0=ready 1=wait - // always ack when it's not program rom - dtack_n <= prog_rom_cs ? !prog_rom_data_valid : 0; - // add dsp_ctrl_cs to cpu_din - // select cpu data input based on what is active - if ( pcb == 0 ) begin - cpu_din <= prog_rom_cs ? prog_rom_data : - ram_cs ? ram_dout : - tile_palette_cs ? tile_palette_cpu_dout : - sprite_palette_cs ? sprite_palette_cpu_dout : - tile_ofs_cs ? curr_tile_ofs : - sprite_ofs_cs ? curr_sprite_ofs : - tile_attr_cs ? cpu_tile_dout_attr : - tile_num_cs ? cpu_tile_dout_num : - sprite_0_cs ? sprite_0_dout : - sprite_1_cs ? sprite_1_dout : - sprite_2_cs ? sprite_2_dout : - sprite_3_cs ? sprite_3_dout : - sprite_size_cs ? sprite_size_cpu_dout : - frame_done_cs ? { 16 { vbl } } : // get vblank state - shared_ram_cs ? cpu_shared_dout : - vblank_cs ? { 15'b0, vbl } : - int_en_cs ? 16'hffff : - 16'd0; - - end else begin - // same same same - cpu_din <= prog_rom_cs ? prog_rom_data : - ram_cs ? ram_dout : - tile_palette_cs ? tile_palette_cpu_dout : - sprite_palette_cs ? sprite_palette_cpu_dout : - tile_ofs_cs ? curr_tile_ofs : - sprite_ofs_cs ? curr_sprite_ofs : - tile_attr_cs ? cpu_tile_dout_attr : - tile_num_cs ? cpu_tile_dout_num : - sprite_0_cs ? sprite_0_dout : - sprite_1_cs ? sprite_1_dout : - sprite_2_cs ? sprite_2_dout : - sprite_3_cs ? sprite_3_dout : - sprite_size_cs ? sprite_size_cpu_dout : - p1_cs ? { 8'h00, p1[7:0] }: - p2_cs ? { 8'h00, p2[7:0] } : - dswa_cs ? { 8'h00, z80_dswa[7:0] } : - dswb_cs ? { 8'h00, z80_dswb[7:0] } : - system_cs ? { 8'h00, system[7:0] } : - tjump_cs ? { 8'h00, 1'b1, z80_tjump[6:0] } : - frame_done_cs ? { 15'b0, vbl } : // get vblank state - vblank_cs ? { 15'b0, vbl } : - int_en_cs ? 16'hffff : - 16'd0; - end - - if ( cpu_rw == 0 ) begin - if ( tile_ofs_cs ) begin - curr_tile_ofs <= cpu_dout; - end - if ( int_en_cs ) begin - int_en <= cpu_dout[0]; - end - if ( crtc_cs ) begin - crtc[ cpu_a[2:1] ] <= cpu_dout; - end - if ( bcu_flip_cs ) begin - tile_flip <= cpu_dout[0]; - end - if ( fcu_flip_cs ) begin - sprite_flip <= cpu_dout[15]; - end - if ( sprite_ofs_cs ) begin - // mask out valid range - curr_sprite_ofs <= { 6'b0, cpu_dout[9:0] }; - end - if ( scroll_ofs_x_cs ) begin - scroll_ofs_x <= cpu_dout; - end - if ( scroll_ofs_y_cs ) begin - scroll_ofs_y <= cpu_dout; - end - // x layer values are even addresses - if ( scroll_cs ) begin - if ( cpu_a[1] == 0 ) begin - scroll_x[ cpu_a[3:2] ] <= cpu_dout[15:7]; - end else begin - scroll_y[ cpu_a[3:2] ] <= cpu_dout[15:7]; - end - end - // offset needs to be auto-incremented - if ( sprite_cs | sprite_size_cs ) begin - inc_sprite_ofs <= 1; - end - if ( reset_z80_cs ) begin - // the pcb writes to a latch to control the reset - reset_z80_n <= cpu_dout[0]; - end - - if ( sound_latch_w_cs ) begin - sound_latch <= cpu_dout[7:0]; - sound_latch_set <= 1; - end - end - end - - if ( clk_3_5M == 1 ) begin - z80_wait_n <= 1; - if ( ioctl_download | ( z80_rd_n == 0 && sound_rom_1_data_valid == 0 && sound_rom_1_cs == 1 ) ) begin - // wait if rom is selected and data is not yet available - z80_wait_n <= 0; - end - - if ( z80_rd_n == 0 ) begin - if ( sound_rom_1_cs ) begin - if ( sound_rom_1_data_valid ) begin - z80_din <= sound_rom_1_data; - end else begin - z80_wait_n <= 0; - end - end else if ( sound_ram_1_cs ) begin - z80_din <= z80_shared_dout; - end else if ( sound0_cs ) begin - z80_din <= opl_dout; - end else if ( sound_latch_r_cs ) begin - z80_din <= sound_latch ; - end else if ( sound_status_cs ) begin - z80_din <= sound_latch_set ? 8'hff : 8'h00 ; - end else begin - z80_din <= 8'h00; - end - - if ( pcb == 0 ) begin - if ( p1_cs ) begin - z80_din <= p1 ; - end else if ( p2_cs ) begin - z80_din <= p2 ; - end else if ( dswa_cs ) begin - z80_din <= z80_dswa ; - end else if ( dswb_cs ) begin - z80_din <= ~z80_dswb ; - end else if ( tjump_cs ) begin - z80_din <= 8'hc0 | ~z80_tjump ; - end else if ( system_cs ) begin - z80_din <= system ; - end - end - end - sound_wr <= 0; - if ( z80_wr_n == 0 ) begin - if ( sound0_cs | sound1_cs ) begin - sound_data <= z80_dout; - sound_addr <= { 1'b0, sound1_cs }; - sound_wr <= 1; - end else if ( sound_done_cs ) begin - sound_latch <= z80_dout ; - sound_latch_set <= 0; - end - end - end - end -end - -reg [1:0] sound_addr; -reg [7:0] sound_data; -reg sound_wr; - -wire [7:0] opl_dout; -wire opl_irq_n; - -reg signed [15:0] sample; - -assign AUDIO_S = 1'b1; - -wire opl_sample_clk; - -jtopl #(.OPL_TYPE(2)) jtopl2 -( - .rst(~reset_n), - .clk(clk_sys), - .cen(clk_3_5M), - .din(sound_data), - .addr(sound_addr), - .cs_n('0), - .wr_n(~sound_wr), - .dout(opl_dout), - .irq_n(opl_irq_n), - .snd(sample), - .sample(opl_sample_clk) -); - -wire [1:0] opl2_level = status[44:43]; // opl2 audio mix - -reg [7:0] opl2_mult; - -// set the multiplier for each channel from menu - -always @( posedge clk_sys, posedge reset ) begin - if (reset) begin - opl2_mult<=0; - end else begin - case( opl2_level ) - 0: opl2_mult <= 8'h0c; // 75% - 1: opl2_mult <= 8'h08; // 50% - 2: opl2_mult <= 8'h04; // 25% - 3: opl2_mult <= 8'h00; // 0% - endcase - end -end - -wire signed [15:0] mono; - -jtframe_mixer #(.W0(16), .WOUT(16)) u_mix_mono( - .rst ( reset ), - .clk ( clk_sys ), - .cen ( 1'b1 ), - // input signals - .ch0 ( sample ), - .ch1 ( 16'd0 ), - .ch2 ( 16'd0 ), - .ch3 ( 16'd0 ), - // gain for each channel in 4.4 fixed point format - .gain0 ( opl2_mult ), - .gain1 ( 8'd0 ), - .gain2 ( 8'd0 ), - .gain3 ( 8'd0 ), - .mixed ( mono ), - .peak ( ) -); - -always @ (posedge clk_sys ) begin - if ( pause_cpu == 1 ) begin - AUDIO_L <= 0; - AUDIO_R <= 0; - end else if ( pause_cpu == 0 ) begin - // mix audio - AUDIO_L <= mono; - AUDIO_R <= mono; - end -end - -T80pa u_cpu( - .RESET_n ( reset_n & reset_z80_n ), - .CLK ( clk_sys ), - .CEN_p ( clk_3_5M ), - .CEN_n ( ~clk_3_5M ), - - .WAIT_n ( z80_wait_n ), // don't wait if data is valid or rom access isn't selected - .INT_n ( opl_irq_n ), // opl timer - .NMI_n ( 1'b1 ), - .BUSRQ_n ( 1'b1 ), - .RD_n ( z80_rd_n ), - .WR_n ( z80_wr_n ), - .A ( z80_addr ), - .DI ( z80_din ), - .DO ( z80_dout ), - // unused - .DIRSET ( 1'b0 ), - .DIR ( 212'b0 ), - .OUT0 ( 1'b0 ), - .RFSH_n (), - .IORQ_n ( IORQ_n ), - .M1_n (), - .BUSAK_n (), - .HALT_n ( 1'b1 ), - .MREQ_n ( MREQ_n ), - .Stop (), - .REG () -); - -// Chip select mux -wire prog_rom_cs; -wire scroll_ofs_x_cs; -wire scroll_ofs_y_cs; -wire ram_cs; -wire vblank_cs; -wire int_en_cs; -wire crtc_cs; -wire tile_ofs_cs; -wire tile_attr_cs; -wire tile_num_cs; -wire scroll_cs; -wire shared_ram_cs; -wire frame_done_cs; // word -wire tile_palette_cs; -wire sprite_palette_cs; -wire sprite_ofs_cs; -wire sprite_cs; // *** offset needs to be auto-incremented -wire sprite_size_cs; // *** offset needs to be auto-incremented -wire sprite_ram_cs; - -wire p1_cs; -wire p2_cs; -wire dswa_cs; -wire dswb_cs; -wire system_cs; -wire tjump_cs; -wire sound0_cs; -wire sound1_cs; -wire sound_latch_cs; -wire sound_latch_w_cs; -wire sound_latch_r_cs; -wire sound_status_cs; -wire sound_done_cs; - -chip_select cs (.*); - -wire sprite_0_cs = ( curr_sprite_ofs[1:0] == 2'b00 ) & sprite_cs; -wire sprite_1_cs = ( curr_sprite_ofs[1:0] == 2'b01 ) & sprite_cs; -wire sprite_2_cs = ( curr_sprite_ofs[1:0] == 2'b10 ) & sprite_cs; -wire sprite_3_cs = ( curr_sprite_ofs[1:0] == 2'b11 ) & sprite_cs; - -reg reset_z80_n; -wire reset_z80_cs; -wire sound_rom_1_cs = ( MREQ_n == 0 && z80_addr <= 16'h7fff ); -wire sound_ram_1_cs = ( MREQ_n == 0 && z80_addr >= 16'h8000 && z80_addr <= 16'hffff ); - -reg int_en; -reg int_ack; - -reg sound_latch_set; -reg [7:0] sound_latch ; - -reg [1:0] vbl_sr; - -// vblank interrupt on rising vbl -always @ (posedge clk_sys ) begin - if ( reset == 1 ) begin - ipl2_n <= 1; - ipl1_n <= 1; - int_ack <= 0; - end else begin - vbl_sr <= { vbl_sr[0], vbl }; - if ( clk_10M == 1 ) begin - int_ack <= ( cpu_as_n == 0 ) && ( cpu_fc == 3'b111 ); // cpu acknowledged the interrupt - end - if ( vbl_sr == 2'b01 ) begin// rising edge - ipl2_n <= ~int_en; - end else if ( vbl_sr == 2'b10 ) begin - if ( pcb == 1 ) begin - ipl1_n <= 0; - end - end else if ( int_ack == 1 || vbl_sr == 2'b10 ) begin - ipl2_n <= 1; - ipl1_n <= 1; - end - end -end - -reg [15:0] scroll_x [3:0]; -reg [15:0] scroll_y [3:0]; - -reg [15:0] scroll_x_latch [3:0]; -reg [15:0] scroll_y_latch [3:0]; - -reg inc_sprite_ofs; - -reg [15:0] crtc[4]; - -reg [15:0] scroll_x_total [3:0]; -reg [15:0] scroll_y_total [3:0]; - -wire [15:0] ram_dout; -wire [9:0] tile_palette_addr; -wire [15:0] tile_palette_cpu_dout; -wire [15:0] tile_palette_dout; - -wire [9:0] sprite_palette_addr; -wire [15:0] sprite_palette_cpu_dout; -wire [15:0] sprite_palette_dout; - -reg [15:0] curr_tile_ofs; -reg [15:0] curr_sprite_ofs; - -reg [15:0] scroll_ofs_x; -reg [15:0] scroll_ofs_y; - -wire [15:0] cpu_tile_dout_attr; -wire [15:0] cpu_tile_dout_num; - -wire [15:0] sprite_0_dout; -wire [15:0] sprite_1_dout; -wire [15:0] sprite_2_dout; -wire [15:0] sprite_3_dout; -wire [15:0] sprite_size_dout; -wire [15:0] sprite_size_cpu_dout; - -wire [31:0] tile_attr_dout; -wire [15:0] sprite_attr_0_dout; -wire [15:0] sprite_attr_1_dout; -wire [15:0] sprite_attr_2_dout; -wire [15:0] sprite_attr_3_dout; - -wire [15:0] sprite_size_buf_dout; -wire [15:0] sprite_attr_0_buf_dout; -wire [15:0] sprite_attr_1_buf_dout; -wire [15:0] sprite_attr_2_buf_dout; -wire [15:0] sprite_attr_3_buf_dout; - -reg [15:0] sprite_buf_din; - -reg [14:0] tile; - -reg [7:0] sprite_num; -reg [7:0] sprite_num_copy; - -reg [3:0] tile_draw_state; - -reg [2:0] layer; // 4 layers + 1 for initial background - -wire [14:0] tile_idx = tile_attr[14:0]; -wire [3:0] tile_priority = tile_attr[31:28]; -wire [5:0] tile_palette_idx = tile_attr[21:16]; -wire tile_hidden = tile_attr[15]; - -reg [15:0] fb_dout; -wire [15:0] tile_fb_out; -wire [15:0] sprite_fb_out; -reg [15:0] fb_din; -reg [15:0] sprite_fb_din; - -reg tile_fb_w; -reg sprite_fb_w; -reg sprite_buf_w; -reg sprite_size_buf_w; - -dual_port_ram #(.LEN(1024), .DATA_WIDTH(16)) tile_line_buffer ( - .clock_a ( clk_sys ), - .address_a ( tile_fb_addr_w ), - .wren_a ( tile_fb_w ), - .data_a ( fb_din ), - .q_a ( ), - - .clock_b ( clk_sys ), - .address_b ( fb_addr_r ), - .wren_b ( 0 ), -// .data_b ( ), - .q_b ( tile_fb_out ) -); - -dual_port_ram #(.LEN(1024), .DATA_WIDTH(16)) sprite_line_buffer ( - .clock_a ( clk_sys ), - .address_a ( sprite_fb_addr_w ), - .wren_a ( sprite_fb_w ), - .data_a ( sprite_fb_din ), - .q_a ( ), - - .clock_b ( clk_sys ), - .address_b ( fb_addr_r ), - .wren_b ( 0 ), -// .data_b ( ), - .q_b ( sprite_fb_out ) -); - -reg [9:0] x_ofs; -reg [9:0] x; - -reg [9:0] y_ofs; - -// y needs to be one line ahaed of the visible line -// render the first line at the end of the previous frame -// this depends on the timing that the sprite list is valid -// sprites values are copied at the start of vblank (line 240) - -// global offsets -wire [9:0] x_ofs_dx = 495 + { ~layer[1:0], 1'b0 }; -wire [9:0] y_ofs_dx = 257; -wire [9:0] x_ofs_dx_flipped = 17 - { ~layer[1:0], 1'b0 }; -wire [9:0] y_ofs_dx_flipped = 255; - -// calculate scrolling -wire [9:0] tile_x_unflipped = scroll_x_latch[layer[1:0]] + x_ofs_dx; -wire [9:0] tile_y_unflipped = scroll_y_latch[layer[1:0]] + y_ofs_dx + scroll_y_offset; -wire [9:0] tile_x_flipped = 319 + scroll_x_latch[layer[1:0]] + x_ofs_dx_flipped; -wire [9:0] tile_y_flipped = 239 + scroll_y_latch[layer[1:0]] + y_ofs_dx_flipped + scroll_y_offset; - -// reverse tiles when flipped -wire [9:0] curr_x = tile_flip ? tile_x_flipped - x : tile_x_unflipped + x; -wire [9:0] curr_y = tile_flip ? tile_y_flipped - y : tile_y_unflipped + y; - -reg [9:0] y; -wire [9:0] y_flipped = ( sprite_flip ? (240 - y ) + scroll_y_offset : y + scroll_y_offset); -wire [9:0] sprite_buf_x = sprite_flip ? 320 - (sprite_x + sprite_pos_x ) : sprite_x + sprite_pos_x; // offset from left of frame - -reg [3:0] draw_state; -reg [3:0] sprite_state; -reg [3:0] tile_copy_state; -reg [3:0] sprite_copy_state; - -// pixel 4 bit colour -wire [3:0] tile_pix; -assign tile_pix = { tile_data[7-curr_x[2:0]], tile_data[15-curr_x[2:0]], tile_data[23-curr_x[2:0]], tile_data[31-curr_x[2:0]] }; - -wire [2:0] sprite_bit = sprite_x[2:0]; -wire [3:0] sprite_pix; -assign sprite_pix = { sprite_data[7-sprite_bit], sprite_data[15-sprite_bit], sprite_data[23-sprite_bit], sprite_data[31-sprite_bit] }; - -// two lines of buffer alternate -reg [9:0] tile_fb_addr_w; -wire [9:0] fb_addr_r = {vc[0], 9'b0 } + hc; - -reg [9:0] sprite_fb_addr_w; - -reg [31:0] tile_attr; - -// two lines worth for 4 layers (~8k) -// [15:14] = layer. -// [13:10] = prioity -// [9:4] = palette offset -// [3:0] = tile colour index. - -reg [3:0] tile_priority_buf [327:0]; -reg [3:0] sprite_priority_buf [327:0]; - -reg [9:0] sprite_x; // offset from left side of sprite -reg [9:0] sprite_y; - -wire [14:0] sprite_index = sprite_attr_0_buf_dout[14:0] /* synthesis keep */; -wire sprite_hidden = sprite_attr_0_buf_dout[15] /* synthesis keep */; - -wire [5:0] sprite_pal_addr = sprite_attr_1_buf_dout[5:0] /* synthesis keep */; -wire [5:0] sprite_size_addr = sprite_attr_1_buf_dout[11:6] /* synthesis keep */; -wire [3:0] sprite_priority = sprite_attr_1_buf_dout[15:12] /* synthesis keep */; - -wire [9:0] sprite_pos_x = sprite_adj_x + (( sprite_attr_2_buf_dout[15:7] < 9'h180 ) ? sprite_attr_2_buf_dout[15:7] : ( sprite_attr_2_buf_dout[15:7] - 10'h200)); -wire [9:0] sprite_pos_y = sprite_adj_y + (( sprite_attr_3_buf_dout[15:7] < 9'h180 ) ? sprite_attr_3_buf_dout[15:7] : ( sprite_attr_3_buf_dout[15:7] - 10'h200)); - -// valid 1 cycle after sprite attr ready -wire [8:0] sprite_height = { sprite_size_buf_dout[7:4], 3'b0 } /* synthesis keep */; // in pixels -wire [8:0] sprite_width = { sprite_size_buf_dout[3:0], 3'b0 } /* synthesis keep */; - -reg [7:0] sprite_buf_num; - -reg [1:0] vtotal_282_flag; - -always @ (posedge clk_sys) begin // Check System Vcount flag for 60Hz mode - if ({crtc[2][7:0], 1'b1 } == 269) - vtotal_282_flag <= 0; - else - vtotal_282_flag <= 1; -end - -always @ (posedge clk_sys) begin - if ( reset == 1 ) begin - sprite_state <= 0; - draw_state <= 0; - sprite_rom_cs <= 0; - tile_rom_cs <= 0; - tile_copy_state <= 0; - sprite_copy_state <= 0; - tile_draw_state <= 0; - end else begin - // render sprites - // triggered when the tile rendering starts - if ( sprite_state == 0 && draw_state > 0 ) begin - sprite_num <= 8'h00; - sprite_x <= 0; - sprite_fb_w <= 1; - sprite_state <= 1; - sprite_fb_din <= 0; - sprite_fb_addr_w <= { y[0], 9'b0 }; - end else if ( sprite_state == 1 ) begin - // erase line buffer - sprite_fb_addr_w <= { y[0], 9'b0 } + sprite_x; - sprite_priority_buf[sprite_x] <= 0; - if ( sprite_x < 320 ) begin - sprite_x <= sprite_x + 1; - end else begin - sprite_x <= 0; - sprite_fb_w <= 0; - sprite_state <= 2; - end - end else if ( sprite_state == 2 ) begin - // sprite num is valid now - sprite_state <= 3; - end else if ( sprite_state == 3 ) begin - // sprite attr valid now. - // delay one more cycle to read sprite size - sprite_state <= 4; - end else if ( sprite_state == 4 ) begin - // start loop - sprite_rom_cs <= 0; - sprite_fb_w <= 0; - sprite_y <= y_flipped - sprite_pos_y; - // is sprite visible and is current y in sprite y range - // sprite pos can be negative? - if ( sprite_hidden == 0 && sprite_width > 0 && ( $signed(y_flipped) >= $signed(sprite_pos_y) ) && $signed(y_flipped) < ( $signed(sprite_pos_y) + $signed(sprite_height) ) ) begin - sprite_state <= 5; - end else if ( sprite_num < 8'hff ) begin - sprite_num <= sprite_num + 1; - sprite_state <= 2; - end else begin - sprite_state <= 15; - end - end else if ( sprite_state == 5 ) begin - sprite_rom_addr <= { sprite_index, 3'b0 } + { sprite_x[8:3], 3'b0 } + ( sprite_y[8:3] * sprite_width ) + sprite_y[2:0]; - sprite_rom_cs <= 1; - sprite_state <= 6; - end else if ( sprite_state == 6 ) begin - // wait for sprite bitmap ready - if ( sprite_rom_data_valid ) begin - // latch data and deassert cs - sprite_data <= sprite_rom_data; - sprite_rom_cs <= 0; - sprite_state <= 7; - end - end else if ( sprite_state == 7 ) begin - sprite_fb_w <= 0; - // draw if pixel value not zero and priority >= previous sprite data -// if ( sprite_pix > 0 && sprite_priority_buf[sprite_buf_x] == 0 ) begin -// if ( sprite_pix != 0 && ( sprite_priority == 0 || sprite_priority >= sprite_priority_buf[sprite_buf_x] ) ) begin - if ( sprite_pix != 0 ) begin - sprite_fb_din <= { 2'b11, sprite_priority, sprite_pal_addr, sprite_pix }; -// if ( sprite_priority == 0 ) begin -// sprite_priority_buf[sprite_buf_x] <= { 1'b1, sprite_priority }; -// end else begin - sprite_fb_addr_w <= { y[0], 9'b0 } + sprite_buf_x; - sprite_priority_buf[sprite_buf_x] <= sprite_priority; - sprite_fb_w <= 1; - end - if ( sprite_x < ( sprite_width - 1 ) ) begin - sprite_x <= sprite_x + 1; - if ( sprite_x[2:0] == 7 ) begin - // do recalc bitmap address - sprite_state <= 5; - end - end else if ( sprite_num < 8'hff ) begin - sprite_num <= sprite_num + 1; - sprite_x <= 0; - // need to load new attributes and size - sprite_state <= 2; - end else begin - // tile state machine will reset sprite_state when line completes. - sprite_state <= 15; // done - end - end - // copy tile ram and scroll info - // not sure if this is needed. need to check to see when tile ram is updated. - if ( tile_copy_state == 0 && vc == 256 ) begin - tile_copy_state <= 1; - end else begin - // copy scroll registers - scroll_x_latch[0] <= scroll_x[0] - scroll_ofs_x; - scroll_x_latch[1] <= scroll_x[1] - scroll_ofs_x; - scroll_x_latch[2] <= scroll_x[2] - scroll_ofs_x; - scroll_x_latch[3] <= scroll_x[3] - scroll_ofs_x; - scroll_y_latch[0] <= scroll_y[0] - scroll_ofs_y; - scroll_y_latch[1] <= scroll_y[1] - scroll_ofs_y; - scroll_y_latch[2] <= scroll_y[2] - scroll_ofs_y; - scroll_y_latch[3] <= scroll_y[3] - scroll_ofs_y; - end - // copy sprite attr/size to buffer - if ( sprite_copy_state == 0 && vc == 240 ) begin - sprite_copy_state <= 1; - sprite_buf_w <= 0; - sprite_num_copy <= 8'h00; - end else if ( sprite_copy_state == 1 ) begin - sprite_num_copy <= sprite_num_copy + 1; - sprite_buf_num <= sprite_num_copy; - sprite_buf_w <= 1; - // wait for read from source - if ( sprite_num_copy == 8'hff ) begin - sprite_copy_state <= 2; - end - end else if ( sprite_copy_state == 2 ) begin - sprite_buf_w <= 0; - sprite_copy_state <= 0; - end - // tile state machine - if ( draw_state == 0 && vc == ({ crtc[2][7:0], 1'b1 } - (status[19] ? (vtotal_282_flag ? 5'd19 : 4'd7) : 3'd0)) ) begin // 282 Lines standard (263 Lines for 60Hz) - layer <= 4; // layer 4 is layer 0 but draws hidden and transparent - y <= 0; - draw_state <= 2; - sprite_state <= 0; - end else if ( draw_state == 2 ) begin - x <= 0; - x_ofs <= scroll_x_latch[layer[1:0]]; - y_ofs <= scroll_y_latch[layer[1:0]]; - // latch offset info - draw_state <= 3; - tile_draw_state <= 0; - end else if ( draw_state == 3 ) begin - if ( tile_draw_state == 0 ) begin - tile <= { layer[1:0], curr_y[8:3], curr_x[8:3] }; // works - tile_draw_state <= 4'h1; - end else if ( tile_draw_state == 1 ) begin - tile_draw_state <= 2; - end else if ( tile_draw_state == 2 ) begin - // latch attribute - tile_attr <= tile_attr_dout; - if ( layer == 4 || tile_attr_dout[15] == 0 ) begin - tile_draw_state <= 3; - end else begin - if ( x < 320 ) begin// 319 - tile_draw_state <= 3; - // do we need to read another tile? - // last pixel of this tile changes based on flip direction - if ( curr_x[2:0] == ( tile_flip ? 0 : 7) ) begin - draw_state <= 3; - tile_draw_state <= 0; - end - x <= x + 1; - end else if ( layer > 0 ) begin - layer <= layer - 1; - tile_fb_w <= 0; - draw_state <= 2; - end else begin - // done - tile_draw_state <= 7; - tile_fb_w <= 0; - end - end - end else if ( tile_draw_state == 3 ) begin - // read bitmap info - tile_rom_cs <= 1; - tile_rom_addr <= { tile_idx, curr_y[2:0] }; - tile_draw_state <= 4; - end else if ( tile_draw_state == 4 ) begin - // wait for bitmap ram ready - if ( tile_rom_data_valid ) begin - // latch data and deassert cs - tile_data <= tile_rom_data; - tile_draw_state <= 5; - tile_rom_cs <= 0; - end - end else if ( tile_draw_state == 5 ) begin - tile_fb_w <= 0; - tile_fb_addr_w <= { y[0], 9'b0 } + x; - // force render of first layer. - // if layer == 4 then tile_pix == 0 is not transparent - // layer 4 is really layer 0 - if ( layer == 4 ) begin - tile_priority_buf[x] <= 0; //tile_pix == 0 ? 0 : tile_priority; - //fb_din <= { layer[1:0], tile_priority, tile_palette_idx, tile_pix }; - fb_din <= { layer[1:0], 4'b0, tile_palette_idx, tile_pix }; - tile_fb_w <= 1; - end else if (tile_hidden == 0 && tile_pix > 0 && tile_priority > 0 && tile_priority >= tile_priority_buf[x] ) begin - tile_priority_buf[x] <= tile_priority; - // if tile hidden then make the pallette index 0. ie transparent - fb_din <= { layer[1:0], tile_priority, tile_palette_idx, tile_pix }; - tile_fb_w <= 1; - end - if ( x < 320 ) begin// 319 - // do we need to read another tile? - // last pixel of this tile changes based on flip direction - if ( curr_x[2:0] == ( tile_flip ? 0 : 7) ) begin - draw_state <= 3; - tile_draw_state <= 0; - end - x <= x + 1; - end else if ( layer > 0 ) begin - layer <= layer - 1; - tile_fb_w <= 0; - draw_state <= 2; - end else begin - // done - tile_draw_state <= 7; - tile_fb_w <= 0; - end - end else if ( tile_draw_state == 7 ) begin - // wait for next line or quit - if ( y == 239 ) begin - draw_state <= 0; - end else if ( hc == (status[19] ? 9'd444 : 9'd449) ) begin // 450 Lines standard (445 Lines for NTSC standard 15.73kHz line freq) - y <= y + 1; - draw_state <= 2; - sprite_state <= 0; - layer <= 4; - end - end - end - end -end - -// render -reg draw_sprite; - -// two lines worth for 4 layers (~8k) -// [15:14] = layer. -// [13:10] = prioity -// [9:4] = palette offset -// [3:0] = tile colour index. - -// there are 10 70MHz cycles per pixel. clk7_count from 0-9 - -// dac values based on 120 ohm driver for the resistor dac and 75 ohm output. 4.7k, 2.2k, 1k, 470, 220 -// modeled in spice -wire [7:0] dac [0:31] = '{0,12,25,36,50,61,73,83,91,100,111,120,131,139,149,157,145,154,162,170,180,187,195,202,208,214,222,228,236,242,249,255}; - -always @ (posedge clk_sys) begin - if ( clk7_count == 4 ) begin - tile_palette_addr <= tile_fb_out[9:0]; - sprite_palette_addr <= sprite_fb_out[9:0]; - end else if ( clk7_count == 6 ) begin - // if palette index is zero then it's from layer 3 and is transparent render as blank (black). - rgb <= { dac[tile_palette_dout[4:0]], dac[tile_palette_dout[9:5]], dac[tile_palette_dout[14:10]] }; - - // if not transparent and sprite is higher priority - if ( sprite_fb_out[3:0] > 0 && (sprite_fb_out[13:10] > tile_fb_out[13:10]) ) begin - // draw sprite - rgb <= { dac[sprite_palette_dout[4:0]], dac[sprite_palette_dout[9:5]], dac[sprite_palette_dout[14:10]] }; - end - end -end - -// tile data buffer - -reg tile_buf_w; -reg [31:0] tile_buf_din; -reg [31:0] tile_buf_dout; -reg [13:0] tile_buf_addr; - -dual_port_ram #(.LEN(16384), .DATA_WIDTH(32)) ram_tile_buf ( - .clock_a ( clk_sys ), - .address_a ( tile[13:0] ), - .wren_a ( tile_buf_w ), - .data_a ( tile_attr_dout ), - - .clock_b ( clk_sys ), - .address_b ( tile[13:0] ), // only read the tile # for now - .wren_b ( 0 ), - .q_b ( tile_buf_dout ) -); - -// tile attribute ram. each tile attribute is 2 16bit words -// pppp ---- --cc cccc httt tttt tttt tttt = Tile number (0 - $7fff) -// indirect access through offset register -dual_port_ram #(.LEN(16384), .DATA_WIDTH(16)) ram_tile_h ( - .clock_a ( clk_10M ), - .address_a ( curr_tile_ofs ), - .wren_a ( tile_attr_cs & !cpu_rw ), - .data_a ( cpu_dout ), - .q_a ( cpu_tile_dout_attr ), - - .clock_b ( clk_sys ), - .address_b ( tile[13:0] ), // only read the tile # for now - .wren_b ( 0 ), - .q_b ( tile_attr_dout[31:16] ) -); - -dual_port_ram #(.LEN(16384), .DATA_WIDTH(16)) ram_tile_l ( - .clock_a ( clk_10M ), - .address_a ( curr_tile_ofs ), - .wren_a ( tile_num_cs & !cpu_rw ), - .data_a ( cpu_dout ), - .q_a ( cpu_tile_dout_num ), - - .clock_b ( clk_sys ), - .address_b ( tile[13:0] ), // only read the tile # for now - .wren_b ( 0 ), - .q_b ( tile_attr_dout[15:0] ) -); - -// sprite attribute ram. each tile attribute is 4 16bit words -// indirect access through offset register -// split up so 64 bits can be read in a single clock -dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_0 ( - .clock_a ( clk_10M ), - .address_a ( curr_sprite_ofs[9:2] ), - .wren_a ( sprite_0_cs & !cpu_rw), - .data_a ( cpu_dout ), - .q_a ( sprite_0_dout ), - - .clock_b ( clk_sys ), - .address_b ( sprite_num_copy ), - .wren_b ( 0 ), - .q_b ( sprite_attr_0_dout[15:0] ) -); - -dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_0_buf ( - .clock_a ( clk_sys ), - .address_a ( sprite_buf_num ), - .wren_a ( sprite_buf_w ), - .data_a ( sprite_attr_0_dout[15:0] ), - .q_a ( ), - - .clock_b ( clk_sys ), - .address_b ( sprite_num ), - .wren_b ( 0 ), - .q_b ( sprite_attr_0_buf_dout[15:0] ) -); - -dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_1 ( - .clock_a ( clk_10M ), - .address_a ( curr_sprite_ofs[9:2] ), - .wren_a ( sprite_1_cs & !cpu_rw ), - .data_a ( cpu_dout ), - .q_a ( sprite_1_dout ), - - .clock_b ( clk_sys ), - .address_b ( sprite_num_copy ), - .wren_b ( 0 ), - .q_b ( sprite_attr_1_dout[15:0] ) -); - -dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_1_buf ( - .clock_a ( clk_sys ), - .address_a ( sprite_buf_num ), - .wren_a ( sprite_buf_w ), - .data_a ( sprite_attr_1_dout[15:0] ), - .q_a ( ), - - .clock_b ( clk_sys ), - .address_b ( sprite_num ), - .wren_b ( 0 ), - .q_b ( sprite_attr_1_buf_dout[15:0] ) -); - -dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_2 ( - .clock_a ( clk_10M ), - .address_a ( curr_sprite_ofs[9:2] ), - .wren_a ( sprite_2_cs & !cpu_rw ), - .data_a ( cpu_dout ), - .q_a ( sprite_2_dout ), - - .clock_b ( clk_sys ), - .address_b ( sprite_num_copy ), - .wren_b ( 0 ), - .q_b ( sprite_attr_2_dout[15:0] ) -); - -dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_2_buf ( - .clock_a ( clk_sys ), - .address_a ( sprite_buf_num ), - .wren_a ( sprite_buf_w ), - .data_a ( sprite_attr_2_dout[15:0] ), - .q_a ( ), - - .clock_b ( clk_sys ), - .address_b ( sprite_num ), - .wren_b ( 0 ), - .q_b ( sprite_attr_2_buf_dout[15:0] ) -); - -dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_3 ( - .clock_a ( clk_10M ), - .address_a ( curr_sprite_ofs[9:2] ), - .wren_a ( sprite_3_cs & !cpu_rw ), - .data_a ( cpu_dout ), - .q_a ( sprite_3_dout ), - - .clock_b ( clk_sys ), - .address_b ( sprite_num_copy ), - .wren_b ( 0 ), - .q_b ( sprite_attr_3_dout[15:0] ) -); - -dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_3_buf ( - .clock_a ( clk_sys ), - .address_a ( sprite_buf_num ), - .wren_a ( sprite_buf_w ), - .data_a ( sprite_attr_3_dout[15:0] ), - .q_a ( ), - - .clock_b ( clk_sys ), - .address_b ( sprite_num ), - .wren_b ( 0 ), - .q_b ( sprite_attr_3_buf_dout[15:0] ) -); - -dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_size ( - .clock_a ( clk_10M ), - .address_a ( curr_sprite_ofs ), - .wren_a ( sprite_size_cs & !cpu_rw), - .data_a ( cpu_dout ), - .q_a ( sprite_size_cpu_dout ), - - .clock_b ( clk_sys ), - .address_b ( sprite_num_copy ), - .wren_b ( 0 ), - .q_b ( sprite_size_dout ) -); - -dual_port_ram #(.LEN(256), .DATA_WIDTH(16)) sprite_ram_size_buf ( - .clock_a ( clk_sys ), - .address_a ( sprite_buf_num ), - .wren_a ( sprite_buf_w ), - .data_a ( sprite_size_dout ), - .q_a ( ), - - .clock_b ( clk_sys ), - .address_b ( sprite_size_addr ), - .wren_b ( 0 ), - .q_b ( sprite_size_buf_dout ) -); - - -// tiles 1024 15 bit values. index is ( 6 bits from tile attribute, 4 bits from bitmap ) -// background palette ram low -// does this need to be byte addressable? -dual_port_ram #(.LEN(1024), .DATA_WIDTH(8)) tile_palram_l ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[10:1] ), - .wren_a ( tile_palette_cs & !cpu_rw & !cpu_lds_n), - .data_a ( cpu_dout[7:0] ), - .q_a ( tile_palette_cpu_dout[7:0] ), - - .clock_b ( clk_sys ), - .address_b ( tile_palette_addr ), - .wren_b ( 0 ), - .q_b ( tile_palette_dout[7:0] ) -); - -// background palette ram high -dual_port_ram #(.LEN(1024), .DATA_WIDTH(8)) tile_palram_h ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[10:1] ), - .wren_a ( tile_palette_cs & !cpu_rw & !cpu_uds_n), - .data_a ( cpu_dout[15:8] ), - .q_a ( tile_palette_cpu_dout[15:8] ), - - .clock_b ( clk_sys ), - .address_b ( tile_palette_addr ), - .wren_b ( 0 ), - .q_b ( tile_palette_dout[15:8] ) -); - -// sprite palette ram low -// does this need to be byte addressable? -dual_port_ram #(.LEN(1024), .DATA_WIDTH(8)) sprite_palram_l ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[10:1] ), - .wren_a ( sprite_palette_cs & !cpu_rw & !cpu_lds_n), - .data_a ( cpu_dout[7:0] ), - .q_a ( sprite_palette_cpu_dout[7:0] ), - - .clock_b ( clk_sys ), - .address_b ( sprite_palette_addr ), - .wren_b ( 0 ), - .q_b ( sprite_palette_dout[7:0] ) -); - -// background palette ram high -dual_port_ram #(.LEN(1024), .DATA_WIDTH(8)) sprite_palram_h ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[10:1] ), - .wren_a ( sprite_palette_cs & !cpu_rw & !cpu_uds_n), - .data_a ( cpu_dout[15:8] ), - .q_a ( sprite_palette_cpu_dout[15:8] ), - - .clock_b ( clk_sys ), - .address_b ( sprite_palette_addr ), - .wren_b ( 0 ), - .q_b ( sprite_palette_dout[15:8] ) -); - - -// main 68k ram low -dual_port_ram #(.LEN(16384), .DATA_WIDTH(8)) ram16kx8_L ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[14:1] ), - .wren_a ( !cpu_rw & ram_cs & !cpu_lds_n ), - .data_a ( cpu_dout[7:0] ), - .q_a ( ram_dout[7:0] ) - ); - -// main 68k ram high -dual_port_ram #(.LEN(16384), .DATA_WIDTH(8)) ram16kx8_H ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[14:1] ), - .wren_a ( !cpu_rw & ram_cs & !cpu_uds_n ), - .data_a ( cpu_dout[15:8] ), - .q_a ( ram_dout[15:8] ) -); - - -//wire [15:0] z80_shared_addr = z80_addr - 16'h8000; -//wire [23:0] m68k_shard_addr = cpu_a - 24'h040000; - -// z80 and 68k shared ram -// 4k -dual_port_ram #(.LEN(32768), .DATA_WIDTH(8)) shared_ram -( - .clock_a ( clk_10M ), - .address_a ( cpu_a[12:1] ), - .wren_a ( shared_ram_cs & !cpu_rw & !cpu_lds_n), - .data_a ( cpu_dout[7:0] ), - .q_a ( cpu_shared_dout[7:0] ), - - .clock_b ( clk_3_5M ), // z80 clock is 3.5M - .address_b ( z80_addr[14:0] ), - .data_b ( z80_dout ), - .wren_b ( sound_ram_1_cs & ~z80_wr_n ), - .q_b ( z80_shared_dout ) -); - -reg [11:0] sprite_rb_addr; -wire [15:0] sprite_rb_dout; - -dual_port_ram #(.LEN(4096), .DATA_WIDTH(8)) sprite_ram_rb_l ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[12:1] ), - .wren_a ( sprite_ram_cs & !cpu_rw & !cpu_lds_n), - .data_a ( cpu_dout[7:0] ), - .q_a ( ), - - .clock_b ( clk_sys ), - .address_b ( sprite_rb_addr ), - .wren_b ( 0 ), - .q_b ( sprite_rb_dout[7:0] ) -); - -dual_port_ram #(.LEN(4096), .DATA_WIDTH(8)) sprite_ram_rb_h ( - .clock_a ( clk_10M ), - .address_a ( cpu_a[12:1] ), - .wren_a ( sprite_ram_cs & !cpu_rw & !cpu_uds_n), - .data_a ( cpu_dout[15:8] ), - .q_a ( ), - - .clock_b ( clk_sys ), - .address_b ( sprite_rb_addr ), - .wren_b ( 0 ), - .q_b ( sprite_rb_dout[15:8] ) -); - -reg [22:0] sdram_addr; -reg [31:0] sdram_data; -reg sdram_we; -reg sdram_req; - -wire sdram_ack; -wire sdram_valid; -wire [31:0] sdram_q; - -sdram #(.CLK_FREQ(70.0)) sdram -( - .reset(~pll_locked), - .clk(clk_sys), - - // controller interface - .addr(sdram_addr), - .data(sdram_data), - .we(sdram_we), - .req(sdram_req), - - .ack(sdram_ack), - .valid(sdram_valid), - .q(sdram_q), - - // SDRAM interface - .sdram_a(SDRAM_A), - .sdram_ba(SDRAM_BA), - .sdram_dq(SDRAM_DQ), - .sdram_cke(SDRAM_CKE), - .sdram_cs_n(SDRAM_nCS), - .sdram_ras_n(SDRAM_nRAS), - .sdram_cas_n(SDRAM_nCAS), - .sdram_we_n(SDRAM_nWE), - .sdram_dqml(SDRAM_DQML), - .sdram_dqmh(SDRAM_DQMH) -); - -wire prog_cache_rom_cs; -wire [22:0] prog_cache_addr; -wire [15:0] prog_cache_data; -wire prog_cache_valid; - -wire [15:0] prog_rom_data; -wire prog_rom_data_valid; - -reg tile_rom_cs; -reg [17:0] tile_rom_addr; -wire [31:0] tile_rom_data; -wire tile_rom_data_valid; - -wire tile_cache_cs; -wire [17:0] tile_cache_addr; -wire [31:0] tile_cache_data; -wire tile_cache_valid; - -reg [31:0] tile_data; - -wire sprite_rom_cs; -wire [18:0] sprite_rom_addr; -wire [31:0] sprite_rom_data; -wire sprite_rom_data_valid; - -reg [31:0] sprite_data; - -wire [15:0] sound_rom_1_addr; -wire [7:0] sound_rom_1_data; -wire sound_rom_1_data_valid; - -// sdram priority based rom controller -// is a oe needed? -rom_controller rom_controller -( - .reset(reset), - - // clock - .clk(clk_sys), - - // program ROM interface - .prog_rom_cs(prog_cache_rom_cs), - .prog_rom_oe(1), - .prog_rom_addr(prog_cache_addr), - .prog_rom_data(prog_cache_data), - .prog_rom_data_valid(prog_cache_valid), - - // character ROM interface - .tile_rom_cs(tile_cache_cs), - .tile_rom_oe(1), - .tile_rom_addr(tile_cache_addr), - .tile_rom_data(tile_cache_data), - .tile_rom_data_valid(tile_cache_valid), - - - // sprite ROM interface - .sprite_rom_cs(sprite_rom_cs), - .sprite_rom_oe(1), - .sprite_rom_addr(sprite_rom_addr), - .sprite_rom_data(sprite_rom_data), - .sprite_rom_data_valid(sprite_rom_data_valid), - - // sound ROM #1 interface - .sound_rom_1_cs(sound_rom_1_cs), - .sound_rom_1_oe(1), - .sound_rom_1_addr(z80_addr), - .sound_rom_1_data(sound_rom_1_data), - .sound_rom_1_data_valid(sound_rom_1_data_valid), - - // IOCTL interface - .ioctl_addr(ioctl_addr), - .ioctl_data(ioctl_dout), - .ioctl_index(ioctl_index), - .ioctl_wr(ioctl_wr), - .ioctl_download(ioctl_download), - - // SDRAM interface - .sdram_addr(sdram_addr), - .sdram_data(sdram_data), - .sdram_we(sdram_we), - .sdram_req(sdram_req), - .sdram_ack(sdram_ack), - .sdram_valid(sdram_valid), - .sdram_q(sdram_q) -); - - -cache prog_cache -( - .reset(reset), - .clk(clk_sys), - - // client - .cache_req(prog_rom_cs), - .cache_addr(cpu_a[23:1]), - .cache_valid(prog_rom_data_valid), - .cache_data(prog_rom_data), - - // to rom controller - .rom_req(prog_cache_rom_cs), - .rom_addr(prog_cache_addr), - .rom_valid(prog_cache_valid), - .rom_data(prog_cache_data) -); - -tile_cache tile_cache -( - .reset(reset), - .clk(clk_sys), - - // client - .cache_req(tile_rom_cs), - .cache_addr(tile_rom_addr), - .cache_data(tile_rom_data), - .cache_valid(tile_rom_data_valid), - - // to rom controller - .rom_req(tile_cache_cs), - .rom_addr(tile_cache_addr), - .rom_data(tile_cache_data), - .rom_valid(tile_cache_valid) -); - -endmodule - - -module cc_shifter -( - input clk_out, - input i, - output o -); - -// We use a two-stages shift-register to synchronize SignalIn_clkA to the clkB clock domain -reg [1:0] r; - -assign o = r[1]; // new signal synchronized to (=ready to be used in) clkB domain - -always @(posedge clk_out) begin - r[0] <= i; - r[1] <= r[0]; // notice that we use clkB -end - -endmodule - - diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/segment.vhd b/Arcade_MiST/Toaplan v1 Hardware/rtl/segment.vhd similarity index 100% rename from Arcade_MiST/Toaplan v1 Hardware/rtl/common/segment.vhd rename to Arcade_MiST/Toaplan v1 Hardware/rtl/segment.vhd diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/single_port_ram.vhd b/Arcade_MiST/Toaplan v1 Hardware/rtl/single_port_ram.vhd similarity index 100% rename from Arcade_MiST/Toaplan v1 Hardware/rtl/common/single_port_ram.vhd rename to Arcade_MiST/Toaplan v1 Hardware/rtl/single_port_ram.vhd diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/single_port_rom.vhd b/Arcade_MiST/Toaplan v1 Hardware/rtl/single_port_rom.vhd similarity index 100% rename from Arcade_MiST/Toaplan v1 Hardware/rtl/common/single_port_rom.vhd rename to Arcade_MiST/Toaplan v1 Hardware/rtl/single_port_rom.vhd diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/tile_cache.v b/Arcade_MiST/Toaplan v1 Hardware/rtl/tile_cache.v similarity index 100% rename from Arcade_MiST/Toaplan v1 Hardware/rtl/common/tile_cache.v rename to Arcade_MiST/Toaplan v1 Hardware/rtl/tile_cache.v diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/true_dual_port_ram.vhd b/Arcade_MiST/Toaplan v1 Hardware/rtl/true_dual_port_ram.vhd similarity index 100% rename from Arcade_MiST/Toaplan v1 Hardware/rtl/common/true_dual_port_ram.vhd rename to Arcade_MiST/Toaplan v1 Hardware/rtl/true_dual_port_ram.vhd diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/common/video_timing.v b/Arcade_MiST/Toaplan v1 Hardware/rtl/video_timing.v similarity index 100% rename from Arcade_MiST/Toaplan v1 Hardware/rtl/common/video_timing.v rename to Arcade_MiST/Toaplan v1 Hardware/rtl/video_timing.v