diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/README.txt b/Arcade_MiST/Custom Hardware/Galaga_MIST/README.txt index 82a73631..8768e4d5 100644 --- a/Arcade_MiST/Custom Hardware/Galaga_MIST/README.txt +++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/README.txt @@ -1,24 +1,237 @@ --------------------------------------------------------------------------------- --- --- Arcade: Galaga for MiST by Gehstock --- 18 December 2017 --- +-- Galaga Midway by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr --------------------------------------------------------------------------------- --- Copyright (c) DAR - Dez 2016 --- https://sourceforge.net/projects/darfpga/files/Software%20VHDL/galaga/ +-- Galaga releases +-- +-- Release 0.3 - 06/05/2018 - Dar +-- add cs54XX mb88 explosion sound ship +-- +-- Release 0.2 - 06/11/2017 - Dar +-- fixes twice bullets on single shot => add edge detection en fire +-- +-- Release 0.1 - 04 November 2017 - Dar +-- fixes 2 ships bullets bug (swap 2xH/2xV command bits) +-- add top level for DE10_lite +-- +-- Release 0.0 - 29 December 2016 - Dar +-- initial release (DE2 only) +-- --------------------------------------------------------------------------------- --- --- Only controls are rotated on VGA output. --- --- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 0247 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- + +-- Features : +-- TV 15KHz mode only (atm) +-- Coctail mode ok +-- Sound ok, Ship explode missing (custom chip 0x54XX todo) +-- Starfield from MAME information + +-- Use with MAME roms from galagamw.zip +-- +-- Use make_galaga_proms.bat to build vhd file from binaries + +-- galaga_cpu1.vhd : 3200a.bin, 3300b.bin, 3400c.bin,3500d.bin, +-- galaga_cpu2.vhd : 3600e.bin +-- galaga_cpu3.vhd : 3700g.bin +-- bg_graphx.vhd : 2600j.bin +-- sp_graphx.vhd : 2800l.bin, 2700k.bin +-- rgb.vhd : prom-5.5n +-- bg_palette.vhd : prom-4.2n +-- sp_palette.vhd : prom-3.1c +-- sound_seq.vhd : prom-2.5c +-- sound_samples.vhd : prom-1.1d + +-- Galaga Hardware caracteristics : +-- +-- 3xZ80 CPU accessing each own program rom and shared ram/devices +-- +-- One char tile map 32x28 (called background/bg although being front of other layers) +-- 3 colors/64sets among 16 colors +-- 1Ko ram, 4Ko rom graphics, 4pixels of 2bits/byte +-- full emulation in vhdl +-- +-- 64 sprites with priorities, flip H/V, 2x size H/V, +-- 3 colors/64sets among 16 colors (different of char colors). +-- 8Ko rom graphics, 4pixels of 2bits/byte +-- full emulation in vhdl (improved capabilities : more sprites/scanline) +-- +-- Namco 05XX Starfield +-- 4 sets, 63 stars/set, 2 set displayed at one time for blinking +-- 6bits colors: 2red/2green/2blue +-- full emulation in vhdl (from MAME information) +-- +-- Char/sprites color palette 2x16 colors among 256 colors +-- 8bits 3red/3green/2blue +-- full emulation in vhdl +-- +-- Namco 06XX for 51/54XX control +-- simplified emulation in vhdl +-- +-- Namco 51XX for coin/credit management +-- simplified emulation in vhdl : 1coin/1credit, 1 or 2 players start +-- +-- Namco 54XX for sound effects +-- mb88 ok +-- +-- Namco sound waveform and frequency synthetizer +-- full original emulation in vhdl +-- +-- Namco 00XX,04XX,02XX,07XX,08XX address generator, H/V counters and shift registers +-- full emulation in vhdl from what I think they should do. +-- +-- Working ram : 3x1Kx8bits shared +-- Sprites ram : 1 scan line delay flip/flop 512x4bits +-- Sound registers ram : 2x16x4bits +-- Sound sequencer rom : 256x4bits (3 sequential 4 bits adders) +-- Sound wavetable rom : 256x4bits 8 waveform of 32 samples of 4bits/level +--------------------------------------------------------------------------------- + +--------------------------------------------------------------------------------- +-- DE2-35 Top level for Galaga Midway by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- +-- Main features : +-- PS2 keyboard input +-- Wm8731 sound output +-- NO board SRAM/Flash used +-- +-- Uses 1 pll for 18MHz and 11MHz generation from 50MHz +-- +-- Board key : +-- 0 : reset +-- -- Keyboard inputs : +-- F3 : Add coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- SPACE : Fire player 1 & 2 +-- RIGHT arrow : Move right player 1 & 2 +-- LEFT arrow : Move left player 1 & 2 -- --- ESC : Coin --- F1 : Start 1 player --- F2 : Start 2 players --- SPACE : Fire --- ARROW KEYS : Movement --- --- Joystick support. --- ---------------------------------------------------------------------------------- \ No newline at end of file +-- Dip switch and other details : see galaga.vhd + +--------------------------------------------------------------------------------- +--------------- +VHDL File list +--------------- + +rtl_dar/galaga_de2.vhd Top level for de2 board +rtl_dar/galaga.vhd Main logic + +rtl_dar/pll50_to_11_and_18.vhd PLL 11MHz and 18 MHz from 50MHz altera mf +rtl_dar/gen_video.vhd Video genertor H/V counter, blanking and syncs + +rtl_dar/stars.vhd Starfield 4 star set list +rtl_dar/stars_machine.vhd Starfield machine for one set +rtl_dar/sound_machine.vhd Namco sound waveform/frequency synthetizer +rtl_dar/mb88.vhd mb88 fujitsu 4bits microprocessor + +rtl_dar/galaga_cpu1.vhd CPU1 program PROM +rtl_dar/galaga_cpu2.vhd CPU2 program PROM +rtl_dar/galaga_cpu3.vhd CPU3 program PROM +rtl_dar/sound_samples.vhd Sound wavetable PROM +rtl_dar/sound_seq.vhd Sound slice adder sequencer PROM +rtl_dar/rgb.vhd 32 colors 8bits palette (3r/3g/2b) PROM +rtl_dar/bg_graphx.vhd Background (char) graphix 2bits/pixel (4Ko) PROM +rtl_dar/bg_palette.vhd 2bits 64sets => 16 colors char LUT PROM +rtl_dar/sp_graphx.vhd Sprites graphix 2bits/pixel (8Ko) PROM +rtl_dar/sp_palette.vhd 2bits 64sets => 16 colors sprites LUT PROM +rtl_dar/cs54xx_prog.vhd Namco custom chip 54xx pgm PROM + +rtl_dar/gen_ram.vhd Generic RAM (Peter Wendrich + DAR Modification) + +wm_8731_dac.vhd DE1/DE2 audio dac + +io_ps2_keyboard.vhd Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +kbd_joystick.vhd Keyboard key to player/coin input + +rtl_T80/T80se.vhd T80 Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +rtl_T80/T80_Reg.vhd +rtl_T80/T80_Pack.vhd +rtl_T80/T80_MCode.vhd +rtl_T80/T80_ALU.vhd +rtl_T80/T80.vhd + +---------------------- +Quartus project files +---------------------- +de2/galaga_de2.qsf de2 settings (files,pins...) +de2/galaga_de2.qpf de2 project + +----------------------------- +Required ROMs (Not included) +----------------------------- +You need the following 15 ROMs binary files from galagamw.zip +(MAME Galaga - Midway set 1) + +-- galaga_cpu1.vhd : 3200a.bin, 3300b.bin, 3400c.bin,3500d.bin, +-- galaga_cpu2.vhd : 3600e.bin +-- galaga_cpu3.vhd : 3700g.bin +-- bg_graphx.vhd : 2600j.bin +-- sp_graphx.vhd : 2800l.bin, 2700k.bin +-- rgb.vhd : prom-5.5n +-- bg_palette.vhd : prom-4.2n +-- sp_palette.vhd : prom-3.1c +-- sound_seq.vhd : prom-2.5c +-- sound_samples.vhd : prom-1.1d +-- cs54xx_prog.vhd : 54xx.bin +------ +Tools +------ +You need to build vhdl files from the binary file : + - Unzip the roms file in the tools/galaga_unzip directory + - Double click (execute) the script tools/make_galaga_proms.bat to get the following files + + galaga_cpu1.vhd + galaga_cpu2.vhd + galaga_cpu3.vhd + bg_graphx.vhd + sp_graphx.vhd + rgb.vhd + bg_palette.vhd + sp_palette.vhd + sound_seq.vhd + sound_samples.vhd + cs54xx_prog.vhd + +*DO NOT REDISTRIBUTE THESE FILES* + +VHDL files are needed to compile and include roms into the project + +The script make_galaga_proms.bat uses make_vhdl_prom executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux. + +Source code of make_vhdl_prom.c is also delivered. + +--------------------------------- +Compiling for de2 +--------------------------------- +You can build the project with ROM image embeded in the sof file. DO NOT REDISTRIBUTE THESE FILES. +3 steps + + - put the VHDL ROM files (.vhd) into the project directory + - build galag_de2 + - program galaga_de2.sof + +------------------------ +------------------------ +End of file +------------------------ diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/Release/galaga_mist.rbf b/Arcade_MiST/Custom Hardware/Galaga_MIST/Release/galaga_mist.rbf index d4587015..1493ce50 100644 Binary files a/Arcade_MiST/Custom Hardware/Galaga_MIST/Release/galaga_mist.rbf and b/Arcade_MiST/Custom Hardware/Galaga_MIST/Release/galaga_mist.rbf differ diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qpf b/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qpf index 82a737e3..c2212bda 100644 --- a/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qpf +++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qpf @@ -1,31 +1,31 @@ # -------------------------------------------------------------------------- # # -# Copyright (C) 2016 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. # # -------------------------------------------------------------------------- # # -# Quartus Prime -# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition -# Date created = 11:01:44 November 04, 2017 +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 17:44:51 March 04, 2019 # # -------------------------------------------------------------------------- # -QUARTUS_VERSION = "16.1" -DATE = "11:01:44 November 04, 2017" +QUARTUS_VERSION = "13.1" +DATE = "17:44:51 March 04, 2019" # Revisions -PROJECT_REVISION = "galaga_mist" +PROJECT_REVISION = "Galaga_MiST" +PROJECT_REVISION = "Berzerk_MiST" diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qsf b/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qsf index c6ee1f1f..1eec429f 100644 --- a/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qsf +++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qsf @@ -1,6 +1,6 @@ # -------------------------------------------------------------------------- # # -# Copyright (C) 1991-2013 Altera Corporation +# Copyright (C) 1991-2014 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing @@ -17,15 +17,15 @@ # -------------------------------------------------------------------------- # # # Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 15:12:41 May 07, 2018 +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 21:36:26 March 08, 2019 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: -# galaga_mist_assignment_defaults.qdf +# Galaga_MiST_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # @@ -34,12 +34,54 @@ # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:59:05 MARCH 16, 2017" set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_location_assignment PIN_7 -to LED +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY Output +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/galaga_mist.sv +set_global_assignment -name VHDL_FILE rtl/galaga.vhd +set_global_assignment -name VHDL_FILE rtl/gen_video.vhd +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/galaga_video.vhd +set_global_assignment -name VHDL_FILE rtl/stars_machine.vhd +set_global_assignment -name VHDL_FILE rtl/stars.vhd +set_global_assignment -name VHDL_FILE rtl/sound_machine.vhd +set_global_assignment -name VHDL_FILE rtl/mb88.vhd +set_global_assignment -name VHDL_FILE rtl/roms/sp_palette.vhd +set_global_assignment -name VHDL_FILE rtl/roms/sp_graphx.vhd +set_global_assignment -name VHDL_FILE rtl/roms/sound_seq.vhd +set_global_assignment -name VHDL_FILE rtl/roms/sound_samples.vhd +set_global_assignment -name VHDL_FILE rtl/roms/rgb.vhd +set_global_assignment -name VHDL_FILE rtl/roms/galaga_cpu3.vhd +set_global_assignment -name VHDL_FILE rtl/roms/galaga_cpu2.vhd +set_global_assignment -name VHDL_FILE rtl/roms/galaga_cpu1.vhd +set_global_assignment -name VHDL_FILE rtl/roms/bg_palette.vhd +set_global_assignment -name VHDL_FILE rtl/roms/bg_graphx.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cs54xx_prog.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80se.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd + +# Pin & Location Assignments +# ========================== set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_7 -to LED set_location_assignment PIN_144 -to VGA_R[5] set_location_assignment PIN_143 -to VGA_R[4] set_location_assignment PIN_142 -to VGA_R[3] @@ -67,74 +109,125 @@ set_location_assignment PIN_88 -to SPI_DI set_location_assignment PIN_126 -to SPI_SCK set_location_assignment PIN_127 -to SPI_SS2 set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_90 -to SPI_SS4 set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PIN_31 -to UART_RX +set_location_assignment PIN_46 -to UART_TX + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY galaga_mist +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name TOP_LEVEL_ENTITY galaga_mist + +# Fitter Assignments +# ================== set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# EDA Netlist Writer Assignments +# ============================== set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" + +# Assembler Assignments +# ===================== set_global_assignment -name USE_CONFIGURATION_DEVICE OFF set_global_assignment -name GENERATE_RBF_FILE ON + +# Power Estimation Assignments +# ============================ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation + +# start EDA_TOOL_SETTINGS(eda_simulation) +# --------------------------------------- + + # EDA Netlist Writer Assignments + # ============================== set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE10_LITE_Default -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity DE10_LITE_Default -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -entity DE10_LITE_Default -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE10_LITE_Default -section_id Top + +# end EDA_TOOL_SETTINGS(eda_simulation) +# ------------------------------------- + +# ------------------------- +# start ENTITY(galaga_mist) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name VHDL_FILE rtl/galaga_mist.vhd -set_global_assignment -name VHDL_FILE rtl/galaga.vhd -set_global_assignment -name VHDL_FILE rtl/stars.vhd -set_global_assignment -name VHDL_FILE rtl/sp_palette.vhd -set_global_assignment -name VHDL_FILE rtl/sp_graphx.vhd -set_global_assignment -name VHDL_FILE rtl/sound_seq.vhd -set_global_assignment -name VHDL_FILE rtl/sound_samples.vhd -set_global_assignment -name VHDL_FILE rtl/sound_machine.vhd -set_global_assignment -name VHDL_FILE rtl/galaga_cpu3.vhd -set_global_assignment -name VHDL_FILE rtl/galaga_cpu2.vhd -set_global_assignment -name VHDL_FILE rtl/galaga_cpu1.vhd -set_global_assignment -name VHDL_FILE rtl/stars_machine.vhd -set_global_assignment -name VHDL_FILE rtl/cs54xx_prog.vhd -set_global_assignment -name VHDL_FILE rtl/bg_palette.vhd -set_global_assignment -name VHDL_FILE rtl/bg_graphx.vhd -set_global_assignment -name VHDL_FILE rtl/gen_video.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/mb88.vhd -set_global_assignment -name VERILOG_FILE rtl/keyboard.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VHDL_FILE rtl/rgb.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(galaga_mist) +# ----------------------- set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.sdc b/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.sdc deleted file mode 100644 index 3eba3b05..00000000 --- a/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.sdc +++ /dev/null @@ -1,33 +0,0 @@ -#************************************************************ -# THIS IS A WIZARD-GENERATED FILE. -# -# Version 13.1.4 Build 182 03/12/2014 SJ Full Version -# -#************************************************************ - -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - - - -# Clock constraints - -create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}] -create_clock -name {SPI_SCK} -period 10.000 -waveform { 0.000 0.500 } [get_ports {SPI_SCK}] - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.srf b/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.srf index f5b4c3aa..549b16a8 100644 --- a/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.srf +++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.srf @@ -1 +1,3 @@ { "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10541 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 113028 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/dac.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/dac.vhd index 47b2185e..0f78fe97 100644 --- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/dac.vhd +++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/dac.vhd @@ -2,6 +2,8 @@ -- -- Delta-Sigma DAC -- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- -- Refer to Xilinx Application Note XAPP154. -- -- This DAC requires an external RC low-pass filter: @@ -15,34 +17,55 @@ ------------------------------------------------------------------------------- library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; +use ieee.std_logic_1164.all; entity dac is - generic ( - C_bits : integer := 10 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(C_bits-1 downto 0); - dac_o : out std_logic - ); + + generic ( + msbi_g : integer := 12 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + end dac; +library ieee; +use ieee.numeric_std.all; + architecture rtl of dac is - signal sig_in: unsigned(C_bits downto 0); + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + begin - seq: process(clk_i, res_n_i) - begin - if res_n_i = '0' then - sig_in <= to_unsigned(2**C_bits, sig_in'length); - dac_o <= '0'; - elsif rising_edge(clk_i) then - -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i - --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); - sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); - dac_o <= sig_in(C_bits); - end if; - end process seq; + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + end rtl; diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga.vhd index 3627d8a9..a848b22e 100644 --- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga.vhd +++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga.vhd @@ -106,14 +106,15 @@ entity galaga is port( clock_18 : in std_logic; reset : in std_logic; --- tv15Khz_mode : in std_logic; video_r : out std_logic_vector(2 downto 0); video_g : out std_logic_vector(2 downto 0); video_b : out std_logic_vector(1 downto 0); - video_blankn : out std_logic; + video_clk : out std_logic; + video_csync : out std_logic; + video_hb : out std_logic; + video_vb : out std_logic; video_hs : out std_logic; video_vs : out std_logic; - pix_ce : out std_logic; audio : out std_logic_vector(9 downto 0); b_test : in std_logic; @@ -131,6 +132,7 @@ port( end galaga; architecture struct of galaga is + signal reset_n: std_logic; signal clock_18n : std_logic; @@ -315,7 +317,7 @@ architecture struct of galaga is begin -pix_ce <= ena_vidgen; + clock_18n <= not clock_18; reset_n <= not reset; @@ -911,7 +913,7 @@ cs06XX_di <= cs51XX_do when "0001", cs06XX_do <= cs06XX_di when mux_addr(8)= '0' else cs06XX_control; -process (clock_18, nmion_n) +process (clock_18, nmion_n, ena_vidgen) begin if nmion_n = '1' then elsif rising_edge(clock_18) and ena_vidgen = '1' then @@ -970,7 +972,9 @@ hcnt => hcnt, vcnt => vcnt, hsync => video_hs, vsync => video_vs, -blankn => video_blankn +csync => video_csync, +hblank => video_hb, +vblank => video_vb ); -- microprocessor Z80 - 1 @@ -1086,7 +1090,7 @@ port map( clk => clock_18n, addr => cs54xx_rom_addr(9 downto 0), data => cs54xx_rom_do -); + ); -- cpu1 program ROM rom_cpu1 : entity work.galaga_cpu1 diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_mist.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_mist.vhd deleted file mode 100644 index 3190482a..00000000 --- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_mist.vhd +++ /dev/null @@ -1,243 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.ALL; -use ieee.numeric_std.all; - -entity galaga_mist is -port( - CLOCK_27 : in std_logic; - LED : out std_logic; - VGA_R : out std_logic_vector(5 downto 0); - VGA_G : out std_logic_vector(5 downto 0); - VGA_B : out std_logic_vector(5 downto 0); - VGA_HS : out std_logic; - VGA_VS : out std_logic; - SPI_SCK : in std_logic; - SPI_DI : in std_logic; - SPI_DO : out std_logic; - SPI_SS3 : in std_logic; - CONF_DATA0 : in std_logic; - AUDIO_L : out std_logic; - AUDIO_R : out std_logic - -); -end galaga_mist; - -architecture struct of galaga_mist is - signal clock_72 : std_logic; - signal clock_18 : std_logic; - signal pll_locked : std_logic; - signal r : std_logic_vector(2 downto 0); - signal g : std_logic_vector(2 downto 0); - signal b : std_logic_vector(1 downto 0); - signal hsync : std_logic; - signal vsync : std_logic; - signal blankn : std_logic; - signal pix_ce : std_logic; - signal audio : std_logic_vector(9 downto 0); - signal audio_pwm : std_logic; - signal reset : std_logic; - signal scanlines : std_logic_vector(1 downto 0); - signal hq2x : std_logic; - - -- User IO - signal buttons : std_logic_vector(1 downto 0); - signal joy0 : std_logic_vector(7 downto 0); - signal joy1 : std_logic_vector(7 downto 0); - signal status : std_logic_vector(31 downto 0); - signal scandoubler_disable : std_logic; - signal ypbpr : std_logic; - - signal kbd_joy : std_logic_vector(7 downto 0); - signal mright : std_logic; - signal mleft : std_logic; - signal ps2Clk : std_logic; - signal ps2Data : std_logic; - signal ps2_scancode : std_logic_vector(7 downto 0); - - signal VGA_R_O : std_logic_vector(2 downto 0); - signal VGA_G_O : std_logic_vector(2 downto 0); - signal VGA_B_O : std_logic_vector(2 downto 0); - - constant CONF_STR : string := - "Galaga;;O4,Screen Direction,Upright,Normal;O89,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;T5,Reset;"; - - function to_slv(s: string) return std_logic_vector is - constant ss: string(1 to s'length) := s; - variable rval: std_logic_vector(1 to 8 * s'length); - variable p: integer; - variable c: integer; - begin - for i in ss'range loop - p := 8 * i; - c := character'pos(ss(i)); - rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); - end loop; - return rval; - end function; - - component mist_io - generic ( STRLEN : integer := 0 ); - port ( - clk_sys :in std_logic; - SPI_SCK, CONF_DATA0, SPI_DI :in std_logic; - SPI_DO : out std_logic; - conf_str : in std_logic_vector(8*STRLEN-1 downto 0); - buttons : out std_logic_vector(1 downto 0); - joystick_0 : out std_logic_vector(7 downto 0); - joystick_1 : out std_logic_vector(7 downto 0); - status : out std_logic_vector(31 downto 0); - scandoubler_disable, ypbpr : out std_logic; - ps2_kbd_clk : out std_logic; - ps2_kbd_data : out std_logic - ); - end component mist_io; - - component video_mixer - generic ( LINE_LENGTH : integer := 384; HALF_DEPTH : integer := 1 ); - port ( - clk_sys, ce_pix, ce_pix_actual : in std_logic; - SPI_SCK, SPI_SS3, SPI_DI : in std_logic; - scanlines : in std_logic_vector(1 downto 0); - scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic; - rotate : in std_logic_vector(1 downto 0); - R, G, B : in std_logic_vector(2 downto 0); - HSync, VSync, line_start, mono : in std_logic; - - VGA_R,VGA_G, VGA_B : out std_logic_vector(5 downto 0); - VGA_VS, VGA_HS : out std_logic - ); - end component video_mixer; - - component keyboard - PORT( - clk : in std_logic; - reset : in std_logic; - ps2_kbd_clk : in std_logic; - ps2_kbd_data : in std_logic; - joystick : out std_logic_vector (7 downto 0) - ); - end component; - -begin - -reset <= status(0) or status(5) or buttons(1) or not pll_locked; - -pll : entity work.pll - port map( - inclk0 => CLOCK_27, - c0 => clock_72, - c1 => clock_18, - locked => pll_locked -); - -scanlines(1) <= '1' when status(9 downto 8) = "11" and scandoubler_disable = '0' else '0'; -scanlines(0) <= '1' when status(9 downto 8) = "10" and scandoubler_disable = '0' else '0'; -hq2x <= '1' when status(9 downto 8) = "01" else '0'; - -vmixer : video_mixer - port map ( - clk_sys => clock_72, - ce_pix => pix_ce, - ce_pix_actual => pix_ce, - - SPI_SCK => SPI_SCK, - SPI_SS3 => SPI_SS3, - SPI_DI => SPI_DI, - - scanlines => scanlines, - scandoubler_disable => scandoubler_disable, - hq2x => hq2x, - ypbpr => ypbpr, - ypbpr_full => '1', - rotate => '1' & not status(4), - R => VGA_R_O, - G => VGA_G_O, - B => VGA_B_O, - HSync => hsync, - VSync => vsync, - line_start => '0', - mono => '0', - - VGA_R => VGA_R, - VGA_G => VGA_G, - VGA_B => VGA_B, - VGA_VS => VGA_VS, - VGA_HS => VGA_HS -); - -mist_io_inst : mist_io - generic map (STRLEN => CONF_STR'length) - port map ( - clk_sys => clock_18, - SPI_SCK => SPI_SCK, - CONF_DATA0 => CONF_DATA0, - SPI_DI => SPI_DI, - SPI_DO => SPI_DO, - conf_str => to_slv(CONF_STR), - buttons => buttons, - scandoubler_disable => scandoubler_disable, - ypbpr => ypbpr, - joystick_1 => joy1, - joystick_0 => joy0, - status => status, - ps2_kbd_clk => ps2Clk, - ps2_kbd_data => ps2Data -); - - mleft <= joy0(1) or joy1(1) or kbd_joy(6) when status(4) = '0' else joy0(2) or joy1(2) or kbd_joy(5); - mright <= joy0(0) or joy1(0) or kbd_joy(7) when status(4) = '0' else joy0(3) or joy1(3) or kbd_joy(4); - -galaga : entity work.galaga - port map( - clock_18 => clock_18, - reset => reset, - video_r => r, - video_g => g, - video_b => b, - video_blankn => blankn, - video_hs => hsync, - video_vs => vsync, - pix_ce => pix_ce, - - audio => audio, - b_test => '0', - b_svce => '0', - coin => kbd_joy(3) or status(1), - start1 => kbd_joy(1) or status(2), - start2 => kbd_joy(2) or status(3), - left1 => mleft, - right1 => mright, - fire1 => joy0(4) or joy1(4) or kbd_joy(0), - left2 => mleft, - right2 => mright, - fire2 => joy0(4) or joy1(4) or kbd_joy(0) -); - -VGA_R_O <= r when blankn = '1' else "000"; -VGA_G_O <= g when blankn = '1' else "000"; -VGA_B_O <= b&b(1) when blankn = '1' else "000"; - -u_dac : entity work.dac - port map( - clk_i => clock_18, - res_n_i => not reset, - dac_i => audio, - dac_o => audio_pwm -); - -AUDIO_L <= audio_pwm; -AUDIO_R <= audio_pwm; - -u_keyboard : keyboard - port map( - clk => clock_18, - reset => reset, - ps2_kbd_clk => ps2Clk, - ps2_kbd_data => ps2Data, - joystick => kbd_joy -); - -LED <= '1'; - -end struct; diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/gen_video.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/gen_video.vhd index 47379532..c5dee924 100644 --- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/gen_video.vhd +++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/gen_video.vhd @@ -7,25 +7,34 @@ use ieee.std_logic_1164.all,ieee.numeric_std.ALL; entity gen_video is port( - clk : in std_logic; - enable : in std_logic; - hcnt : out std_logic_vector(8 downto 0); - vcnt : out std_logic_vector(8 downto 0); - hsync : out std_logic; - vsync : out std_logic; - blankn : out std_logic +clk : in std_logic; +enable : in std_logic; +hcnt : out std_logic_vector(8 downto 0); +vcnt : out std_logic_vector(8 downto 0); +hsync : out std_logic; +vsync : out std_logic; +csync : out std_logic; -- composite sync for TV +hblank : out std_logic; +vblank : out std_logic ); end gen_video; architecture struct of gen_video is - signal hblank : std_logic; - signal vblank : std_logic; - signal hcntReg : unsigned (8 DOWNTO 0) := to_unsigned(000,9); - signal vcntReg : unsigned (8 DOWNTO 0) := to_unsigned(015,9); +signal hclkReg : unsigned (1 DOWNTO 0); +--signal hblank : std_logic; +--signal vblank : std_logic; +signal hcntReg : unsigned (8 DOWNTO 0) := to_unsigned(000,9); +signal vcntReg : unsigned (8 DOWNTO 0) := to_unsigned(015,9); + +signal hsync0 : std_logic; +signal hsync1 : std_logic; +signal hsync2 : std_logic; + begin hcnt <= std_logic_vector(hcntReg); vcnt <= std_logic_vector(vcntReg); +hsync <= hsync0; -- Compteur horizontal : 511-128+1=384 pixels (48 tiles) -- 192 à 255 : 64 pixels debut de ligne (8 dont 2 dernières tiles affichées) @@ -40,43 +49,67 @@ vcnt <= std_logic_vector(vcntReg); -- Synchro horizontale : hcnt=[176 à 204] (29 pixels) -- Synchro verticale : vcnt=[260 à 003] ( 8 lignes) -process(clk) begin - if rising_edge(clk) then -- clk & ena at 6MHz - if enable = '1' then +process(clk, enable) +begin - if hcntReg = 511 then - hcntReg <= to_unsigned (128,9); - else - hcntReg <= hcntReg + 1; - end if; +if rising_edge(clk) and enable = '1' then -- clk & ena at 6MHz - if hcntReg = 191 then - if vcntReg = 261 then - vcntReg <= to_unsigned(0,9); - else - vcntReg <= vcntReg + 1; - end if; - end if; + if hcntReg = 511 then + hcntReg <= to_unsigned (128,9); + else + hcntReg <= hcntReg + 1; + end if; - if hcntReg = (175+ 0-8+8) then hsync <= '1'; -- 1 - elsif hcntReg = (175+29-8+8) then hsync <= '0'; - end if; + if hcntReg = 191 then + if vcntReg = 263 then + vcntReg <= to_unsigned(0,9); + else + vcntReg <= vcntReg + 1; + end if; + end if; - if vcntReg = 252 then vsync <= '1'; - elsif vcntReg = 260 then vsync <= '0'; - end if; + if hcntReg = (175+ 0-8+8) then hsync0 <= '0'; -- 1 + elsif hcntReg = (175+29-8+8) then hsync0 <= '1'; + end if; - if hcntReg = (127+16+8) then hblank <= '1'; - elsif hcntReg = (255-17+8+1) then hblank <= '0'; - end if; + if hcntReg = (175-8+8) then hsync1 <= '0'; + elsif hcntReg = (175+13-8+8) then hsync1 <= '1'; -- 11 + elsif hcntReg = (175 +192-8+8) then hsync1 <= '0'; + elsif hcntReg = (175+13+192-8+8) then hsync1 <= '1'; -- 11 + end if; - if vcntReg = (240+1-1) then vblank <= '1'; - elsif vcntReg = (015+1) then vblank <= '0'; - end if; + if hcntReg = (175-8+8) then hsync2 <= '0'; + elsif hcntReg = (175-28-8+8) then hsync2 <= '1'; + end if; + + if vcntReg = 252-1 then csync <= hsync1; + elsif vcntReg = 253-1 then csync <= hsync1; + elsif vcntReg = 254-1 then csync <= hsync1; -- and hsync2; + elsif vcntReg = 255-1 then csync <= hsync2; -- not(hsync1); + elsif vcntReg = 256-1 then csync <= hsync2; -- not(hsync1); + elsif vcntReg = 257-1 then csync <= hsync2; -- not(hsync1) or not(hsync2); + elsif vcntReg = 258-1 then csync <= hsync1; + elsif vcntReg = 259-1 then csync <= hsync1; + elsif vcntReg = 260-1 then csync <= hsync1; + else csync <= hsync0; + end if; + + if vcntReg = 260 then vsync <= '0'; + elsif vcntReg = 003 then vsync <= '1'; + end if; + + if hcntReg = (127+16+8) then hblank <= '1'; + elsif hcntReg = (255-17+8+1) then hblank <= '0'; + end if; + + if vcntReg = (240+1-1) then vblank <= '1'; + elsif vcntReg = (015+1) then vblank <= '0'; + end if; + + -- blankn <= not (hblank or vblank); + +end if; - blankn <= not (hblank or vblank); - end if; - end if; end process; end architecture; \ No newline at end of file diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/keyboard.v b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/keyboard.v deleted file mode 100644 index 89f7e34e..00000000 --- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/keyboard.v +++ /dev/null @@ -1,82 +0,0 @@ - - -module keyboard -( - input clk, - input reset, - input ps2_kbd_clk, - input ps2_kbd_data, - - output reg[7:0] joystick -); - -reg [11:0] shift_reg = 12'hFFF; -wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; -wire [7:0] kcode = kdata[9:2]; -reg release_btn = 0; - -reg [7:0] code; -reg input_strobe = 0; - -always @(negedge clk) begin - reg old_reset = 0; - - old_reset <= reset; - - if(~old_reset & reset)begin - joystick <= 0; - end - - if(input_strobe) begin - case(code) - 'h16: joystick[1] <= ~release_btn; // 1 - 'h1E: joystick[2] <= ~release_btn; // 2 - - 'h75: joystick[4] <= ~release_btn; // arrow up - 'h72: joystick[5] <= ~release_btn; // arrow down - 'h6B: joystick[6] <= ~release_btn; // arrow left - 'h74: joystick[7] <= ~release_btn; // arrow right - - 'h29: joystick[0] <= ~release_btn; // Space - 'h11: joystick[1] <= ~release_btn; // Left Alt - 'h0d: joystick[2] <= ~release_btn; // Tab - 'h76: joystick[3] <= ~release_btn; // Escape - endcase - end -end - -always @(posedge clk) begin - reg [3:0] prev_clk = 0; - reg old_reset = 0; - reg action = 0; - - old_reset <= reset; - input_strobe <= 0; - - if(~old_reset & reset)begin - prev_clk <= 0; - shift_reg <= 12'hFFF; - end else begin - prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; - if(prev_clk == 1) begin - if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin - shift_reg <= 12'hFFF; - if (kcode == 8'he0) ; - // Extended key code follows - else if (kcode == 8'hf0) - // Release code follows - action <= 1; - else begin - // Cancel extended/release flags for next time - action <= 0; - release_btn <= action; - code <= kcode; - input_strobe <= 1; - end - end else begin - shift_reg <= kdata; - end - end - end -end -endmodule diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/mist_io.v b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/mist_io.v index ad233a3b..2f41221f 100644 --- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/mist_io.v +++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/mist_io.v @@ -5,6 +5,7 @@ // http://code.google.com/p/mist-board/ // // Copyright (c) 2014 Till Harbaum +// Copyright (c) 2015-2017 Sorgelig // // This source file is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published @@ -47,13 +48,16 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) output SPI_DO, input SPI_DI, - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, +// output reg [31:0] joystick_2, +// output reg [31:0] joystick_3, +// output reg [31:0] joystick_4, output reg [15:0] joystick_analog_0, output reg [15:0] joystick_analog_1, output [1:0] buttons, output [1:0] switches, - output scandoubler_disable, + output scandoublerD, output ypbpr, output reg [31:0] status, @@ -61,13 +65,13 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) // SD config input sd_conf, input sd_sdhc, - output img_mounted, // signaling that new image has been mounted + output [1:0] img_mounted, // signaling that new image has been mounted output reg [31:0] img_size, // size of image in bytes // SD block level access input [31:0] sd_lba, - input sd_rd, - input sd_wr, + input [1:0] sd_rd, + input [1:0] sd_wr, output reg sd_ack, output reg sd_ack_conf, @@ -82,192 +86,222 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) output reg ps2_kbd_data, output ps2_mouse_clk, output reg ps2_mouse_data, - input ps2_caps_led, + + // ps2 alternative interface. + + // [8] - extended, [9] - pressed, [10] - toggles with every press/release + output reg [10:0] ps2_key = 0, + + // [24] - toggles with every event + output reg [24:0] ps2_mouse = 0, // ARM -> FPGA download + input ioctl_ce, output reg ioctl_download = 0, // signal indicating an active download output reg [7:0] ioctl_index, // menu index used to upload the file - output ioctl_wr, + output reg ioctl_wr = 0, output reg [24:0] ioctl_addr, output reg [7:0] ioctl_dout ); -reg [7:0] b_data; -reg [6:0] sbuf; -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes reg [7:0] but_sw; reg [2:0] stick_idx; -reg mount_strobe = 0; +reg [1:0] mount_strobe = 0; assign img_mounted = mount_strobe; assign buttons = but_sw[1:0]; assign switches = but_sw[3:2]; -assign scandoubler_disable = but_sw[4]; +assign scandoublerD = but_sw[4]; assign ypbpr = but_sw[5]; -wire [7:0] spi_dout = { sbuf, SPI_DI}; - // this variant of user_io is for 8 bit cores (type == a4) only wire [7:0] core_type = 8'ha4; // command byte read by the io controller -wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; +wire drive_sel = sd_rd[1] | sd_wr[1]; +wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; + +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes reg spi_do; assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; -wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; +reg [7:0] spi_data_out; -// drive MISO only when transmitting core id -always@(negedge SPI_SCK) begin - if(!CONF_DATA0) begin - // first byte returned is always core type, further bytes are - // command dependent - if(byte_cnt == 0) begin - spi_do <= core_type[~bit_cnt]; +// SPI transmitter +always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - end else begin - case(cmd) - // reading config string - 8'h14: begin - // returning a byte from string - if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; - else spi_do <= 0; - end - - // reading sd card status - 8'h16: begin - if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; - else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; - else spi_do <= 0; - end - - // reading sd card write data - 8'h18: - spi_do <= b_data[~bit_cnt]; - - // reading keyboard LED status - 8'h1f: - spi_do <= kbd_led[~bit_cnt]; - - default: - spi_do <= 0; - endcase - end - end -end - -reg b_wr2,b_wr3; -always @(negedge clk_sys) begin - b_wr3 <= b_wr2; - sd_buff_wr <= b_wr3; -end +reg [7:0] spi_data_in; +reg spi_data_ready = 0; // SPI receiver always@(posedge SPI_SCK or posedge CONF_DATA0) begin + reg [6:0] sbuf; + reg [31:0] sd_lba_r; + reg drive_sel_r; if(CONF_DATA0) begin - b_wr2 <= 0; bit_cnt <= 0; byte_cnt <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - end else begin - b_wr2 <= 0; - - sbuf <= spi_dout[6:0]; + spi_data_out <= core_type; + end + else + begin bit_cnt <= bit_cnt + 1'd1; - if(bit_cnt == 5) begin - if (byte_cnt == 0) sd_buff_addr <= 0; - if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; - if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; - end + sbuf <= {sbuf[5:0], SPI_DI}; // finished reading command byte if(bit_cnt == 7) begin + if(!byte_cnt) cmd <= {sbuf, SPI_DI}; + + spi_data_in <= {sbuf, SPI_DI}; + spi_data_ready <= ~spi_data_ready; if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - if(byte_cnt == 0) begin - cmd <= spi_dout; - - if(spi_dout == 8'h19) begin - sd_ack_conf <= 1; - sd_buff_addr <= 0; - end - if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin - sd_ack <= 1; - sd_buff_addr <= 0; - end - if(spi_dout == 8'h18) b_data <= sd_buff_din; - - mount_strobe <= 0; - - end else begin - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_dout; - 8'h02: joystick_0 <= spi_dout; - 8'h03: joystick_1 <= spi_dout; + spi_data_out <= 0; + case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) + // reading config string + 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - // store incoming ps2 mouse bytes - 8'h04: begin - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end + // reading sd card status + 8'h16: if(byte_cnt == 0) begin + spi_data_out <= sd_cmd; + sd_lba_r <= sd_lba; + drive_sel_r <= drive_sel; + end else if (byte_cnt == 1) begin + spi_data_out <= drive_sel_r; + end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - // store incoming ps2 keyboard bytes - 8'h05: begin - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_dout; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_dout; - b_wr2 <= 1; - end + // reading sd card write data + 8'h18: spi_data_out <= sd_buff_din; + endcase + end + end +end - 8'h18: b_data <= sd_buff_din; +reg [31:0] ps2_key_raw = 0; +wire pressed = (ps2_key_raw[15:8] != 8'hf0); +wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; - else if(byte_cnt == 2) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; - end else if(byte_cnt == 3) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; - end - end +// transfer to clk_sys domain +always@(posedge clk_sys) begin + reg old_ss1, old_ss2; + reg old_ready1, old_ready2; + reg [2:0] b_wr; + reg got_ps2 = 0; - // notify image selection - 8'h1c: mount_strobe <= 1; + old_ss1 <= CONF_DATA0; + old_ss2 <= old_ss1; + old_ready1 <= spi_data_ready; + old_ready2 <= old_ready1; + + sd_buff_wr <= b_wr[0]; + if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; + b_wr <= (b_wr<<1); - // send image info - 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; - - // status, 32bit version - 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; - default: ; - endcase + if(old_ss2) begin + got_ps2 <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + sd_buff_addr <= 0; + if(got_ps2) begin + if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; + if(cmd == 5) begin + ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; + if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed + if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released + if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed end end end + else + if(old_ready2 ^ old_ready1) begin + + if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; + + if(byte_cnt < 2) begin + + if (cmd == 8'h19) sd_ack_conf <= 1; + if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; + mount_strobe <= 0; + + if(cmd == 5) ps2_key_raw <= 0; + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_data_in; + 8'h02: joystick_0 <= spi_data_in; + 8'h03: joystick_1 <= spi_data_in; +// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; +// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; +// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; +// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; +// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; + // store incoming ps2 mouse bytes + 8'h04: begin + got_ps2 <= 1; + case(byte_cnt) + 2: ps2_mouse[7:0] <= spi_data_in; + 3: ps2_mouse[15:8] <= spi_data_in; + 4: ps2_mouse[23:16] <= spi_data_in; + endcase + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + got_ps2 <= 1; + ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_data_in; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_data_in; + b_wr <= 1; + end + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; + else if(byte_cnt == 3) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; + end else if(byte_cnt == 4) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; + end + end + + // notify image selection + 8'h1c: mount_strobe[spi_data_in[0]] <= 1; + + // send image info + 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; + + // status, 32bit version + 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; + default: ; + endcase + end + end end @@ -422,6 +456,8 @@ localparam UIO_FILE_TX = 8'h53; localparam UIO_FILE_TX_DAT = 8'h54; localparam UIO_FILE_INDEX = 8'h55; +reg rdownload = 0; + // data_io has its own SPI interface to the io controller always@(posedge SPI_SCK, posedge SPI_SS2) begin reg [6:0] sbuf; @@ -431,15 +467,10 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin if(SPI_SS2) cnt <= 0; else begin - rclk <= 0; - // don't shift in last bit. It is evaluated directly // when writing to ram if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - // increase target address after write - if(rclk) addr <= addr + 1'd1; - // count 0-7 8-15 8-15 ... if(cnt < 15) cnt <= cnt + 1'd1; else cnt <= 8; @@ -451,11 +482,15 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin if((cmd == UIO_FILE_TX) && (cnt == 15)) begin // prepare if(SPI_DI) begin - addr <= 0; - ioctl_download <= 1; + case(ioctl_index[4:0]) + 1: addr <= 25'h200000; // TRD buffer at 2MB + 2: addr <= 25'h400000; // tape buffer at 4MB + default: addr <= 25'h150000; // boot rom + endcase + rdownload <= 1; end else begin addr_w <= addr; - ioctl_download <= 0; + rdownload <= 0; end end @@ -463,7 +498,8 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin addr_w <= addr; data_w <= {sbuf, SPI_DI}; - rclk <= 1; + addr <= addr + 1'd1; + rclk <= ~rclk; end // expose file (menu) index @@ -471,21 +507,24 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin end end -assign ioctl_wr = |ioctl_wrd; -reg [1:0] ioctl_wrd; - -always@(negedge clk_sys) begin +// transfer to ioctl_clk domain. +// ioctl_index is set before ioctl_download, so it's stable already +always@(posedge clk_sys) begin reg rclkD, rclkD2; - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wrd<= {ioctl_wrd[0],1'b0}; + if(ioctl_ce) begin + ioctl_download <= rdownload; - if(rclkD & ~rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wrd <= 2'b11; + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wr <= 0; + + if(rclkD != rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wr <= 1; + end end end -endmodule +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/pll.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/pll.vhd deleted file mode 100644 index ce065a7b..00000000 --- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/pll.vhd +++ /dev/null @@ -1,389 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Full Version --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - self_reset_on_loss_lock : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - locked : OUT STD_LOGIC - ); - END COMPONENT; - -BEGIN - sub_wire6_bv(0 DOWNTO 0) <= "0"; - sub_wire6 <= To_stdlogicvector(sub_wire6_bv); - sub_wire3 <= sub_wire0(0); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - locked <= sub_wire2; - c0 <= sub_wire3; - sub_wire4 <= inclk0; - sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 3, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NO_COMPENSATION", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_USED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - self_reset_on_loss_lock => "ON", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire5, - clk => sub_wire0, - locked => sub_wire2 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "13500" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "72.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "7" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "72.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/scandoubler.v b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/scandoubler.v index e85cba43..5a3ccd17 100644 --- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/scandoubler.v +++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/scandoubler.v @@ -19,6 +19,18 @@ // TODO: Delay vsync one line +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) ( // system interface diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_machine.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_machine.vhd index d4cfda81..3243e6fb 100644 --- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_machine.vhd +++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_machine.vhd @@ -69,7 +69,7 @@ snd_ram_1_we <= ram_1_we; sum <= ('0' & snd_ram_0_do) + ('0' & snd_ram_1_do) + ("0000" & sum_r(4)); -process (clock_18) +process (clock_18, ena) begin if rising_edge(clock_18) and ena = '1' then if snd_seq_do(3) = '0' then diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/video_mixer.sv b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/video_mixer.sv index 3dd47eec..126ca276 100644 --- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/video_mixer.sv +++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/video_mixer.sv @@ -50,7 +50,7 @@ module video_mixer input [1:0] scanlines, // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoubler_disable, + input scandoublerD, // High quality 2x scaling input hq2x, @@ -113,9 +113,9 @@ scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler .b_out(B_sd) ); -wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); -wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); -wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); +wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); +wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); +wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); generate if(HALF_DEPTH) begin @@ -129,8 +129,8 @@ generate end endgenerate -wire hs = (scandoubler_disable ? HSync : hs_sd); -wire vs = (scandoubler_disable ? VSync : vs_sd); +wire hs = (scandoublerD ? HSync : hs_sd); +wire vs = (scandoublerD ? VSync : vs_sd); reg scanline = 0; always @(posedge clk_sys) begin @@ -237,7 +237,7 @@ wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[1 assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; +assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; endmodule diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/build_id.tcl b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/build_id.v b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/build_id.v new file mode 100644 index 00000000..35a7b1c4 --- /dev/null +++ b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "190308" +`define BUILD_TIME "213631" diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/galaga_mist.sv b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/galaga_mist.sv new file mode 100644 index 00000000..394fb329 --- /dev/null +++ b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/galaga_mist.sv @@ -0,0 +1,179 @@ +module galaga_mist +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Galaga;;", + "O2,Rotate Controls,Off,On;", + "O34,Scanlines,Off,25%,50%,75%;", +// "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.20.",`BUILD_DATE +}; + +assign LED = 1; +assign AUDIO_R = AUDIO_L; + +wire clk_36, clk_18, clk_9; +pll pll( + .inclk0(CLOCK_27), + .c0(clk_36), + .c1(clk_18), + .c2(clk_9) + ); + + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire [10:0] ps2_key; +wire [9:0] audio; +wire hs, vs; +wire blankn = ~(hb | vb); +wire hb, vb; +wire [2:0] r,g; +wire [1:0] b; + +galaga galaga( + .clock_18(clk_18), + .reset(status[0] | status[6] | buttons[1]), + .video_r(r), + .video_g(g), + .video_b(b), + .video_hb(hb), + .video_vb(vb), + .video_hs(hs), + .video_vs(vs), + .audio(audio), + .coin(btn_coin), + .start1(btn_one_player), + .left1(m_left), + .right1(m_right), + .fire1(m_fire), + .start2(btn_two_players), + .left2(m_left), + .right2(m_right), + .fire2(m_fire) + ); + +video_mixer video_mixer( + .clk_sys(clk_36), + .ce_pix(clk_9), + .ce_pix_actual(clk_9), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn ? {r,3'b1} : 0), + .G(blankn ? {g,3'b1} : 0), + .B(blankn ? {b,4'b1} : 0), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .rotate({1'b1,status[2]}), + .scanlines(scandoublerD ? 2'b00 : status[4:3]), +// .scanlines(scandoublerD ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), +// .hq2x(status[4:3]==1), + .scandoublerD(scandoublerD), + .ypbpr(ypbpr), + .ypbpr_full(1), + .line_start(0), + .mono(0) + ); + +mist_io #( + .STRLEN(($size(CONF_STR)>>3))) +mist_io( + .clk_sys (clk_36 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoublerD (scandoublerD ), + .ypbpr (ypbpr ), + .ps2_key (ps2_key ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac #( + .msbi_g(9)) +dac ( + .clk_i(clk_36), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +// Rotated Normal +wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; +wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; +wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; +wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; + +wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; +wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; + +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +reg btn_fire2 = 0; +reg btn_fire3 = 0; +reg btn_coin = 0; +wire pressed = ps2_key[9]; +wire [7:0] code = ps2_key[7:0]; + +always @(posedge clk_36) begin + reg old_state; + old_state <= ps2_key[10]; + if(old_state != ps2_key[10]) begin + case(code) + 'h75: btn_up <= pressed; // up + 'h72: btn_down <= pressed; // down + 'h6B: btn_left <= pressed; // left + 'h74: btn_right <= pressed; // right + 'h76: btn_coin <= pressed; // ESC + 'h05: btn_one_player <= pressed; // F1 + 'h06: btn_two_players <= pressed; // F2 + 'h14: btn_fire3 <= pressed; // ctrl + 'h11: btn_fire2 <= pressed; // alt + 'h29: btn_fire1 <= pressed; // Space + endcase + end +end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/galaga_video.vhd b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/galaga_video.vhd new file mode 100644 index 00000000..c3c7b644 --- /dev/null +++ b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/galaga_video.vhd @@ -0,0 +1,211 @@ +--------------------------------------------------------------------------------- +-- Phoenix video generator by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.ALL; +use ieee.numeric_std.all; + +entity phoenix_video is +port( + clk11 : in std_logic; + reset : in std_logic; + hclk : out std_logic; + hcnt : out std_logic_vector(9 downto 1); + vcnt : out std_logic_vector(8 downto 1); + sync : out std_logic; + adrsel : out std_logic; + rdy : out std_logic; + vblank : out std_logic; + hblank_frgrd : out std_logic; + hblank_bkgrd : out std_logic +); end phoenix_video; + +architecture struct of phoenix_video is + signal hclk_i : std_logic := '0'; + signal hstb_i : std_logic := '0'; + signal hcnt_i : unsigned(9 downto 1) := (others=>'0'); + signal vcnt_i : unsigned(8 downto 1) := (others=>'0'); + signal vblank_n : std_logic := '0'; + signal sync1_i : std_logic; + signal sync2_i : std_logic; + + signal pulse_a : std_logic; + signal pulse_b1 : std_logic; + signal pulse_b2 : std_logic; + signal pulse_c1 : std_logic; + signal pulse_c2 : std_logic; + signal pulse_d1 : std_logic; + signal pulse_d2 : std_logic; + signal sync_i : std_logic; + signal vcntr_i : unsigned(8 downto 1) := (others=>'0'); + + signal rdy1_i : std_logic; + signal rdy2_i : std_logic; + signal j1 : std_logic; + signal k1 : std_logic; + signal q1 : std_logic; + signal j2 : std_logic; + signal k2 : std_logic; + signal q2 : std_logic; + +begin + +-- horizontal counter clock (pixel clock) +process (clk11) +begin + if rising_edge(clk11) then + hclk_i <= not hclk_i; + end if; +end process; + +-- horizontal counter from 0x0A0 to 0x1FF : 352 pixels +process (hclk_i) +begin + if rising_edge(hclk_i) then + if reset = '1' then + hcnt_i <= (others=>'0'); + else + hcnt_i <= hcnt_i +1; + if hcnt_i = "111111111" then + hcnt_i <= "010100000"; + end if; + end if; + end if; +end process; + +-- vertical counter clock (line clock) = hblank +process (hclk_i) +begin + if rising_edge(hclk_i) then + if (hcnt_i(3) and hcnt_i(2) and hcnt_i(1)) = '1' then hstb_i <= not hcnt_i(9); end if; + end if; +end process; + +-- vertical clock from 0x00 to 0xFF : 256 lines +process (hstb_i) +begin + if rising_edge(hstb_i) then + if reset = '1' then + vcnt_i <= (others=>'0'); + else + vcnt_i <= vcnt_i +1; + if vcnt_i = "11111111" then + vcnt_i <= "00000000"; + end if; + end if; + end if; +end process; + +-- vertical blanking +vblank_n <= + not(vcnt_i(8) and vcnt_i(7)) + or + ( not + ( not (vcnt_i(8) and vcnt_i(7) and not vcnt_i(6) and not vcnt_i(5) and not vcnt_i(4)) + and + not (vcnt_i(8) and vcnt_i(7) and not vcnt_i(6) and not vcnt_i(5) and vcnt_i(4)) + ) + ); + +-- vertical syncs +sync1_i <= not( vcnt_i(8) and vcnt_i(7) and (vcnt_i(6) and not vcnt_i(5) and not vcnt_i(4) and not vcnt_i(3))); +-- horizontal syncs +sync2_i <= not( not hcnt_i(9) and (hcnt_i(7) and not hcnt_i(6) and not hcnt_i(5))); + +-- ready signal for microprocessor +rdy1_i <= not( not(hcnt_i(9)) and not hcnt_i(7) and hcnt_i(6) and not hcnt_i(5)); +rdy2_i <= not( not(hcnt_i(9)) and hcnt_i(7) and hcnt_i(6) and hcnt_i(5)); + +-- background horizontal blanking +j1 <= hcnt_i(6) and hcnt_i(4); +k1 <= hstb_i; + +process (hclk_i) +begin + if rising_edge(hclk_i) then + if (j1 xor k1) = '1' then + q1 <= j1; + elsif j1 = '1' then + q1 <= not q1; + else + q1 <= q1; + end if; + end if; +end process; + +j2 <= not hcnt_i(6) and hcnt_i(5); +k2 <= hcnt_i(8) and hcnt_i(7) and hcnt_i(6) and hcnt_i(4); + +process (hclk_i) +begin + if rising_edge(hclk_i) then + if (j2 xor k2) = '1' then + q2 <= j2; + elsif j2 = '1' then + q2 <= not q2; + else + q2 <= q2; + end if; + end if; +end process; + +-- output +hclk <= hclk_i; +hcnt <= std_logic_vector(hcnt_i); +vcnt <= std_logic_vector(vcnt_i); +--sync <= not(sync1_i xor sync2_i) ; original syncs +rdy <= not(vblank_n and (not (rdy1_i and rdy2_i and not hcnt_i(9)))); +adrsel <= vblank_n and hcnt_i(9); + +vblank <= not vblank_n; +hblank_frgrd <= hstb_i; +hblank_bkgrd <= not(hcnt_i(9) and q1) and not(hcnt_i(9) and (q2)); + +-- make sync pulses width close to 4.7us (26 pixels) +-- and add compensation pulse 2.35us (13 pixels) +-- falling edge should always occured at 32 or 64us +process (hclk_i) +begin + if rising_edge(hclk_i) then + if hcnt_i = '0'&X"BF" then pulse_a <= '0'; end if; -- 4.7us normal sync + if hcnt_i = '0'&X"D9" then pulse_a <= '1'; end if; -- negative pulse , start at 0x0C0 + + if hcnt_i = '0'&X"BF" then pulse_b1 <= '0'; end if; -- 2.35us fisrt precomp sync + if hcnt_i = '0'&X"CC" then pulse_b1 <= '1'; end if; -- negative pulse, start at 0x0C0 + + if hcnt_i = '1'&X"6F" then pulse_b2 <= '0'; end if; -- 2.35us 2nd precomp sync + if hcnt_i = '1'&X"7C" then pulse_b2 <= '1'; end if; -- negative pulse, start at 0x170 + + if hcnt_i = '0'&X"A5" then pulse_c1 <= '1'; end if; -- 4.7us fisrt precomp sync + if hcnt_i = '0'&X"BF" then pulse_c1 <= '0'; end if; -- positive pulse, end at 0x0C0 + + if hcnt_i = '1'&X"55" then pulse_c2 <= '1'; end if; -- 4.7us 2nd precomp sync + if hcnt_i = '1'&X"6F" then pulse_c2 <= '0'; end if; -- positive pulse, end at 0x170 + + if hcnt_i = '1'&X"FF" then pulse_d1 <= '0'; end if; -- begin of vsync field + if hcnt_i = '0'&X"BF" then pulse_d1 <= '1'; end if; -- falling edge at 0x0C0 + + if hcnt_i = '1'&X"FF" then pulse_d2 <= '1'; end if; -- end of vsync field + if hcnt_i = '1'&X"6F" then pulse_d2 <= '0'; end if; -- rising edge at 0x0170 + + sync <= sync_i; + + if hcnt_i = '1'&X"FF" then vcntr_i <= vcnt_i; end if; -- synchronise vcnt with hcnt + end if; +end process; + +-- mux syncs with respect to line counter +with vcntr_i select +sync_i <= pulse_b1 and pulse_b2 when X"DF", + pulse_b1 and pulse_b2 when X"E0", + pulse_b1 and pulse_d2 when X"E1", + pulse_c1 or pulse_c2 when X"E2", + pulse_c1 or pulse_c2 when X"E3", + (pulse_c1 and not pulse_d1) or (pulse_b1 and pulse_b2 and pulse_d1) when X"E4", + pulse_b1 and pulse_b2 when X"E5", + pulse_a when others; + +end struct; diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/mb88.vhd b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/mb88.vhd new file mode 100644 index 00000000..a85b39f7 --- /dev/null +++ b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/mb88.vhd @@ -0,0 +1,580 @@ +--------------------------------------------------------------------------------- +-- mb88 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- +-- Version 0.3 -- 28/02/2017 -- +-- fixed instruction JMP (0xC0..0xFF) let r_pa be incremented when r_pc = 0x3F +-- +-- Version 0.2 -- 26/02/2017 -- +-- corrected r_stf for tstR instruction (0x24) +-- corrected r_stf for tbit instruction (0x38-0x3B) +-- +-- Version 0.1 -- 25/02/2017 -- +-- outO instruction write to ol,oh depending on r_cf +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- + +-- Todo : Timer, Serial + +-- Features : + +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity mb88 is +port( + clock : in std_logic; + ena : in std_logic; + reset_n : in std_logic; + + r0_port_in : in std_logic_vector(3 downto 0); + r1_port_in : in std_logic_vector(3 downto 0); + r2_port_in : in std_logic_vector(3 downto 0); + r3_port_in : in std_logic_vector(3 downto 0); + r0_port_out : out std_logic_vector(3 downto 0); + r1_port_out : out std_logic_vector(3 downto 0); + r2_port_out : out std_logic_vector(3 downto 0); + r3_port_out : out std_logic_vector(3 downto 0); + k_port_in : in std_logic_vector(3 downto 0); + ol_port_out : out std_logic_vector(3 downto 0); + oh_port_out : out std_logic_vector(3 downto 0); + p_port_out : out std_logic_vector(3 downto 0); + + stby_n : in std_logic; + tc_n : in std_logic; + irq_n : in std_logic; + sc_in_n : in std_logic; + si_n : in std_logic; + sc_out_n : out std_logic; + so_n : out std_logic; + to_n : out std_logic; + + rom_addr : out std_logic_vector(10 downto 0); + rom_data : in std_logic_vector( 7 downto 0) + + ); +end mb88; + +architecture struct of mb88 is + + signal reset : std_logic; + signal clock_n : std_logic; + + signal ram_addr : std_logic_vector(6 downto 0); + signal ram_we : std_logic; + signal ram_di : std_logic_vector(3 downto 0); + signal ram_do : std_logic_vector(3 downto 0); + + signal r_pc : std_logic_vector(5 downto 0) := (others=>'0'); + signal r_pa : std_logic_vector(4 downto 0) := (others=>'0'); + signal r_si : std_logic_vector(1 downto 0) := (others=>'0'); + signal r_a : std_logic_vector(3 downto 0) := (others=>'0'); + signal r_x : std_logic_vector(3 downto 0) := (others=>'0'); + signal r_y : std_logic_vector(3 downto 0) := (others=>'0'); + signal r_stf : std_logic := '1'; + signal r_zf : std_logic := '0'; + signal r_cf : std_logic := '0'; + signal r_vf : std_logic := '0'; + signal r_sf : std_logic := '0'; + signal r_nf : std_logic := '0'; + + signal r_pio : std_logic_vector(7 downto 0) := (others=>'0'); + signal r_th : std_logic_vector(3 downto 0) := (others=>'0'); + signal r_tl : std_logic_vector(3 downto 0) := (others=>'0'); + signal r_tp : std_logic_vector(5 downto 0) := (others=>'0'); + signal r_ctr : std_logic_vector(5 downto 0) := (others=>'0'); + + signal r_sb : std_logic_vector(3 downto 0) := (others=>'0'); + signal r_sbcnt : std_logic_vector(3 downto 0) := (others=>'0'); + + signal interrupt_pending : std_logic := '0'; + signal irq_n_r : std_logic := '0'; + + subtype stack_size is integer range 0 to 3; + type stack_def is array(stack_size) of std_logic_vector(15 downto 0); + signal stack : stack_def := (others=>(others=>'0')); + + subtype ram_size is integer range 0 to 127; + type ram_def is array(ram_size) of std_logic_vector(3 downto 0); + signal ram : ram_def := (others=>(others=>'0')); + + signal single_byte_op : std_logic := '1'; + signal op_code : std_logic_vector(7 downto 0) := X"00"; + + signal a_p1 : std_logic_vector(3 downto 0); + signal a_p1_z : std_logic; + signal a_p1_c : std_logic; + signal a_m1 : std_logic_vector(3 downto 0); + signal a_m1_z : std_logic; + signal a_m1_c : std_logic; + signal y_p1 : std_logic_vector(3 downto 0); + signal y_p1_z : std_logic; + signal y_p1_c : std_logic; + signal y_m1 : std_logic_vector(3 downto 0); + signal y_m1_z : std_logic; + signal y_m1_c : std_logic; + signal m_p1 : std_logic_vector(3 downto 0); + signal m_p1_z : std_logic; + signal m_p1_c : std_logic; + signal m_m1 : std_logic_vector(3 downto 0); + signal m_m1_z : std_logic; + signal m_m1_c : std_logic; + signal adc : std_logic_vector(4 downto 0); + signal adc_z : std_logic; + signal adc_c : std_logic; + signal sbc : std_logic_vector(4 downto 0); + signal sbc_z : std_logic; + signal sbc_c : std_logic; + signal cma : std_logic_vector(4 downto 0); + signal cma_z : std_logic; + signal cma_c : std_logic; + signal a_pim : std_logic_vector(4 downto 0); + signal a_pim_z: std_logic; + signal a_pim_c: std_logic; + signal im_my : std_logic_vector(4 downto 0); + signal im_my_z: std_logic; + signal im_my_c: std_logic; + signal im_ma : std_logic_vector(4 downto 0); + signal im_ma_z: std_logic; + signal im_ma_c: std_logic; + signal a_and_m : std_logic_vector(3 downto 0); + signal a_and_m_z : std_logic; + signal a_or_m : std_logic_vector(3 downto 0); + signal a_or_m_z : std_logic; + signal a_xor_m : std_logic_vector(3 downto 0); + signal a_xor_m_z : std_logic; + signal nega : std_logic_vector(3 downto 0); + signal nega_z : std_logic; + signal rola : std_logic_vector(3 downto 0); + signal rola_z : std_logic; + signal rora : std_logic_vector(3 downto 0); + signal rora_z : std_logic; + signal do_da : std_logic; + signal daa : std_logic_vector(3 downto 0); + signal daa_z : std_logic; + signal daa_c : std_logic; + signal das : std_logic_vector(3 downto 0); + signal das_z : std_logic; + signal das_c : std_logic; + signal dca : std_logic_vector(3 downto 0); + signal dca_z : std_logic; + signal dca_c : std_logic; + signal x_z : std_logic; + signal y_z : std_logic; + signal tl_z : std_logic; + signal th_z : std_logic; + signal sb_z : std_logic; + signal k_port_in_z : std_logic; + signal r0_port_in_z : std_logic; + signal r1_port_in_z : std_logic; + signal r2_port_in_z : std_logic; + signal r3_port_in_z : std_logic; + signal sel_bit_y : std_logic_vector(3 downto 0); + + signal m_set_bit : std_logic_vector(3 downto 0); + signal m_clr_bit : std_logic_vector(3 downto 0); + signal m_tst_bit : std_logic; + + signal mem : std_logic_vector(3 downto 0); + signal mem_z : std_logic; + signal imm_x7_z : std_logic; + signal imm_xF_z : std_logic; + +begin + +clock_n <= not clock; +reset <= not reset_n; + +rom_addr <= r_pa & r_pc; + +ram_addr <= X"0" & rom_data(2 downto 0) when ((rom_data >= X"50") and (rom_data <= X"57")) else r_x(2 downto 0) & r_y; + +ram_we <= '1' when(( (rom_data = X"1D") or (rom_data = X"1A") or + (rom_data = X"0A") or (rom_data = X"0B") or + (rom_data = X"2A") or + (rom_data = X"19") or (rom_data = X"09") or + ((rom_data >= X"30") and (rom_data <= X"37") ) or + ((rom_data >= X"50") and (rom_data <= X"57") ) + ) and (single_byte_op = '1')and ena = '1') + else '0'; + +with rom_data select +ram_di <= r_a when X"1D", r_a when X"1A", + r_a when X"0A", r_a when X"0B", + r_sb when X"2A", + m_m1 when X"19", m_p1 when X"09", + m_set_bit when X"30", m_clr_bit when X"34", + m_set_bit when X"31", m_clr_bit when X"35", + m_set_bit when X"32", m_clr_bit when X"36", + m_set_bit when X"33", m_clr_bit when X"37", + r_a when X"50", r_y when X"54", + r_a when X"51", r_y when X"55", + r_a when X"52", r_y when X"56", + r_a when X"53", r_y when X"57", + X"A" when others; + + +a_p1 <= r_a + X"1"; +a_p1_z <= '1' when a_p1 = X"0" else '0'; +a_p1_c <= '1' when a_p1 = X"0" else '0'; + +a_m1 <= r_a - X"1"; +a_m1_z <= '1' when a_m1 = X"0" else '0'; +a_m1_c <= '1' when a_m1 = X"F" else '0'; + +y_p1 <= r_y + X"1"; +y_p1_z <= '1' when y_p1 = X"0" else '0'; +y_p1_c <= '1' when y_p1 = X"0" else '0'; + +y_m1 <= r_y - X"1"; +y_m1_z <= '1' when y_m1 = X"0" else '0'; +y_m1_c <= '1' when y_m1 = X"F" else '0'; + +m_p1 <= ram_do + X"1"; +--m_p1_z <= '1' when m_p1 = X"0" else '0'; +--m_p1_c <= '1' when m_p1 = X"0" else '0'; + +m_m1 <= ram_do - X"1"; +--m_m1_z <= '1' when m_m1 = X"0" else '0'; +--m_m1_c <= '1' when m_m1 = X"F" else '0'; + +with rom_data(2 downto 0) select +m_set_bit <= ram_do or X"1" when "000", + ram_do or X"2" when "001", + ram_do or X"4" when "010", + ram_do or X"8" when others; + +with rom_data(2 downto 0) select +m_clr_bit <= ram_do and not X"1" when "000", + ram_do and not X"2" when "001", + ram_do and not X"4" when "010", + ram_do and not X"8" when others; + +m_tst_bit <= ram_do(to_integer(unsigned(rom_data(1 downto 0)))); + +rola <= r_a(2 downto 0) & r_cf; +rola_z <= '1' when rola = X"0" else '0'; + +rora <= r_cf & r_a(3 downto 1); +rora_z <= '1' when rora = X"0" else '0'; + +nega <= not(r_a) + X"1"; +nega_z <= '1' when nega = X"0" else '0'; + +adc <= ('0'&ram_do) + ('0'&r_a) + ("0000"&r_cf); +adc_z <= '1' when adc(3 downto 0) = X"0" else '0'; +adc_c <= '1' when adc(4) = '1' else '0'; + +sbc <= ('0'&ram_do) - ('0'&r_a) - ("0000"&r_cf); +sbc_z <= '1' when sbc(3 downto 0) = X"0" else '0'; +sbc_c <= '1' when sbc(4) = '1' else '0'; + +cma <= ('0'&ram_do) - ('0'&r_a); +cma_z <= '1' when cma(3 downto 0) = X"0" else '0'; +cma_c <= '1' when cma(4) = '1' else '0'; + +a_pim <= ('0'&rom_data(3 downto 0)) + ('0'&r_a); +a_pim_z <= '1' when a_pim(3 downto 0) = X"0" else '0'; +a_pim_c <= '1' when a_pim(4) = '1' else '0'; + +im_my <= ('0'&rom_data(3 downto 0)) - ('0'&r_y); +im_my_z <= '1' when im_my(3 downto 0) = X"0" else '0'; +im_my_c <= '1' when im_my(4) = '1' else '0'; + +im_ma <= ('0'&rom_data(3 downto 0)) - ('0'&r_a); +im_ma_z <= '1' when im_ma(3 downto 0) = X"0" else '0'; +im_ma_c <= '1' when im_ma(4) = '1' else '0'; + +a_and_m <= r_a and ram_do; +a_and_m_z <= '1' when a_and_m = X"0" else '0'; + +a_or_m <= r_a or ram_do; +a_or_m_z <= '1' when a_or_m = X"0" else '0'; + +a_xor_m <= r_a xor ram_do; +a_xor_m_z <= '1' when a_xor_m = X"0" else '0'; + +do_da <= '1' when (r_a > X"9") or (r_cf = '1') else '0'; + +daa <= r_a + X"6"; +daa_z <= '1' when daa = X"0" else '0'; +daa_c <= '1' when r_a > X"9" else '0'; + +das <= r_a + X"A"; +das_z <= '1' when das = X"0" else '0'; +das_c <= '1' when r_a > X"5" else '0'; + +dca <= r_a + X"F"; +dca_z <= '1' when dca = X"0" else '0'; +dca_c <= '1' when dca = X"F" else '0'; + +x_z <= '1' when r_x = X"0" else '0'; +y_z <= '1' when r_y = X"0" else '0'; +tl_z <= '1' when r_tl = X"0" else '0'; +th_z <= '1' when r_th = X"0" else '0'; +sb_z <= '1' when r_sb = X"0" else '0'; +k_port_in_z <= '1' when k_port_in = X"0" else '0'; +r0_port_in_z <= '1' when r0_port_in = X"0" else '0'; +r1_port_in_z <= '1' when r1_port_in = X"0" else '0'; +r2_port_in_z <= '1' when r2_port_in = X"0" else '0'; +r3_port_in_z <= '1' when r3_port_in = X"0" else '0'; + +with r_y(1 downto 0) select +sel_bit_y <= "0001" when "00", + "0010" when "01", + "0100" when "10", + "1000" when others; + +imm_x7_z <= '1' when rom_data(2 downto 0) = "000" else '0'; +imm_xF_z <= '1' when rom_data(3 downto 0) = "0000" else '0'; + +process (clock_n) -- register data before memory value update at middle cycle +begin + if rising_edge(clock_n) then + mem <= ram_do; + if ram_do = X"0" then mem_z <= '1'; else mem_z <= '0'; end if; + if m_p1 = X"0" then m_p1_z <= '1'; else m_p1_z <= '0'; end if; + if m_p1 = X"0" then m_p1_c <= '1'; else m_p1_c <= '0'; end if; + if m_m1 = X"0" then m_m1_z <= '1'; else m_m1_z <= '0'; end if; + if m_m1 = X"F" then m_m1_c <= '1'; else m_m1_c <= '0'; end if; +end if; +end process; + +process (clock) +begin + if rising_edge(clock) then +-- mem <= ram_do; +-- if ram_do = X"0" then mem_z <= '1'; else mem_z <= '0'; end if; + + irq_n_r <= irq_n; + r_nf <= not irq_n; + if irq_n = '0' and irq_n_r = '1' and r_pio(2) = '1' then + interrupt_pending <= '1'; + end if; + + if reset = '1' then + r_pc <= (others=>'0'); + r_pa <= (others=>'0'); + r_si <= (others=>'0'); + r_a <= (others=>'0'); + r_x <= (others=>'0'); + r_y <= (others=>'0'); + r_stf <= '1'; + r_zf <= '0'; + r_cf <= '0'; + r_vf <= '0'; + r_sf <= '0'; + r_nf <= '0'; + r_pio <= (others=>'0'); + r_th <= (others=>'0'); + r_tl <= (others=>'0'); + r_tp <= (others=>'0'); + r_ctr <= (others=>'0'); + r_sb <= (others=>'0'); + r_sbcnt <= (others=>'0'); + interrupt_pending <= '0'; + stack <= (others=>(others=>'0')); + single_byte_op <= '1'; + else + if ena = '1' then + + op_code <= rom_data; + single_byte_op <= '1'; + + if r_pc = "111111" then + r_pc <= "000000"; + r_pa <= r_pa + "0001"; + else + r_pc <= r_pc + "000001"; + end if; + + if single_byte_op = '1' then + if interrupt_pending = '1' then + stack(to_integer(unsigned(r_si)))(13 downto 0) <= (r_cf & r_zf & r_stf & r_pa & r_pc); + r_pc <= "000010"; + r_pa <= "00000"; + r_si <= r_si + "01"; + interrupt_pending <= '0'; + else -- no irq + case rom_data is + when X"00" => r_stf <='1'; -- nop + when X"01" => r_stf <='1'; -- outO portO <- A //!PLA todo + if r_cf = '0' then ol_port_out <= r_a; end if; + if r_cf = '1' then oh_port_out <= r_a; end if; + when X"02" => r_stf <='1'; p_port_out <= r_a; -- outP portP <- A + when X"03" => r_stf <='1'; -- outR(Y) portR(Y) <- A + if r_y = X"0" then r0_port_out <= r_a; end if; + if r_y = X"1" then r1_port_out <= r_a; end if; + if r_y = X"2" then r2_port_out <= r_a; end if; + if r_y = X"3" then r3_port_out <= r_a; end if; + when X"04" => r_stf <='1'; r_y <= r_a; -- tay Y <- A + when X"05" => r_stf <='1'; r_th <= r_a; -- tath TH <- A + when X"06" => r_stf <='1'; r_tl <= r_a; -- tatl TL <- A + when X"07" => r_stf <='1'; r_sb <= r_a; -- tas SB <- A + when X"08" => r_stf <= not y_p1_c; r_y <= y_p1; r_zf <= y_p1_z; -- icy Y <- Y+1 + when X"09" => r_stf <= not m_p1_c; r_zf <= m_p1_z; -- icm M[X,Y] <- M[X,Y]+1 + when X"0A" => r_stf <= not y_p1_c; r_y <= y_p1; r_zf <= y_p1_z; -- stic M[X,Y] <- A; Y <- Y+1 + when X"0B" => r_stf <='1'; r_a <= mem; r_zf <= mem_z; -- x A <- M[X,Y]; M[X,Y] <- A + when X"0C" => r_stf <= not r_a(3); r_a <= rola; r_zf <= rola_z; r_cf <= r_a(3); -- rol + when X"0D" => r_stf <='1'; r_a <= mem; r_zf <= mem_z; -- l A <- M[X,Y]; + when X"0E" => r_stf <= not adc_c; r_a <= adc(3 downto 0); r_zf <= adc_z; r_cf <= adc_c; -- adc A <- M[X,Y]+A+CF; + when X"0F" => r_stf <= not a_and_m_z; r_a <= a_and_m; r_zf <= a_and_m_z; -- and A <- A & M[X,Y]; + when X"10" => + if do_da = '1' then r_stf <= not daa_c; r_a <= daa; r_cf <= daa_c; -- daa A <- A + 6 ; si A>9 or CF + else r_stf <= '1'; r_cf <= '0'; end if; + when X"11" => + if do_da = '1' then r_stf <= not das_c; r_a <= das; r_cf <= das_c; -- das A <- A + 10; si A>9 or CF + else r_stf <= '1'; r_cf <= '0'; end if; + when X"12" => r_stf <='1'; r_a <= k_port_in; r_zf <= k_port_in_z; -- inK A <- K + when X"13" => r_stf <='1'; -- inR A <- R(Y) + if r_y = X"0" then r_a <= r0_port_in; r_zf <= r0_port_in_z; end if; + if r_y = X"1" then r_a <= r1_port_in; r_zf <= r1_port_in_z; end if; + if r_y = X"2" then r_a <= r2_port_in; r_zf <= r2_port_in_z; end if; + if r_y = X"3" then r_a <= r3_port_in; r_zf <= r3_port_in_z; end if; + when X"14" => r_stf <='1'; r_a <= r_y; r_zf <= y_z; -- tya A <- Y + when X"15" => r_stf <='1'; r_a <= r_th; r_zf <= th_z; -- ttha A <- TH + when X"16" => r_stf <='1'; r_a <= r_tl; r_zf <= tl_z; -- ttla A <- TH + when X"17" => r_stf <='1'; r_a <= r_sb; r_zf <= sb_z; -- tsa A <- SB + when X"18" => r_stf <= not y_m1_c; r_y <= y_m1; -- dcy Y <- Y-1 + when X"19" => r_stf <= not m_m1_c; r_zf <= m_m1_z; -- dcm M[X,Y] <- M[X,Y]-1 + when X"1A" => r_stf <= not y_m1_c; r_y <= y_m1; r_zf <= y_m1_z; -- stdc M[X,Y] <- A; Y <- Y-1 + when X"1B" => r_stf <='1'; r_a <= r_x; r_x <= r_a; r_zf <= x_z; -- xx A <- X, X <- A + when X"1C" => r_stf <= not r_a(0); r_a <= rora; r_zf <= rora_z; r_cf <= r_a(0); -- ror + when X"1D" => r_stf <='1'; -- st M[X,Y] <- A + when X"1E" => r_stf <= not sbc_c; r_a <= sbc(3 downto 0); r_zf <= sbc_z; r_cf <= sbc_c; -- sbc A <- M[X,Y]-A-CF; + when X"1F" => r_stf <= not a_or_m_z; r_a <= a_or_m; r_zf <= a_or_m_z; -- or A <- A | M[X,Y]; + when X"20" => r_stf <='1'; -- setR + if r_y(3 downto 2) = "00" then r0_port_out <= (r0_port_in or sel_bit_y ); end if; + if r_y(3 downto 2) = "01" then r1_port_out <= (r1_port_in or sel_bit_y ); end if; + if r_y(3 downto 2) = "10" then r2_port_out <= (r2_port_in or sel_bit_y ); end if; + if r_y(3 downto 2) = "11" then r3_port_out <= (r3_port_in or sel_bit_y ); end if; + when X"21" => r_stf <='1'; r_cf <= '1'; -- setCF + when X"22" => r_stf <='1'; -- clrR + if r_y(3 downto 2) = "00" then r0_port_out <= (r0_port_in and not sel_bit_y ); end if; + if r_y(3 downto 2) = "01" then r1_port_out <= (r1_port_in and not sel_bit_y ); end if; + if r_y(3 downto 2) = "10" then r2_port_out <= (r2_port_in and not sel_bit_y ); end if; + if r_y(3 downto 2) = "11" then r3_port_out <= (r3_port_in and not sel_bit_y ); end if; + when X"23" => r_stf <='1'; r_cf <= '0'; -- clrCF + when X"24" => -- tstR + if r_y(3 downto 2) = "00" then r_stf <= not r0_port_in(to_integer(unsigned(r_y(1 downto 0)))); end if; + if r_y(3 downto 2) = "01" then r_stf <= not r1_port_in(to_integer(unsigned(r_y(1 downto 0)))); end if; + if r_y(3 downto 2) = "10" then r_stf <= not r2_port_in(to_integer(unsigned(r_y(1 downto 0)))); end if; + if r_y(3 downto 2) = "11" then r_stf <= not r3_port_in(to_integer(unsigned(r_y(1 downto 0)))); end if; + when X"25" => r_stf <= not r_nf; -- tsti (interrupt) + when X"26" => r_stf <= not r_vf; r_vf <= '0'; -- tstv (timer overflow) + when X"27" => r_stf <= not r_sf; r_sf <= '0'; -- tsts (serial) + when X"28" => r_stf <= not r_cf; -- tstc (CF) + when X"29" => r_stf <= not r_zf; -- tstz (ZF) + when X"2A" => r_stf <= '1'; r_zf <= sb_z; -- sts M[X,Y] <- SB + when X"2B" => r_stf <= '1'; r_sb <= mem; r_zf <= mem_z; -- ls SB <- M[X,Y] + when X"2C" => r_stf <= '1'; -- rts + r_pa <= stack(to_integer(unsigned(r_si-"01")))(10 downto 6); + r_pc <= stack(to_integer(unsigned(r_si-"01")))( 5 downto 0); + r_si <= r_si - "01"; + when X"2D" => r_stf <= not nega_z; r_a <= nega; -- negA A <- -A + when X"2E" => r_stf <= not cma_z; r_zf <= cma_z; r_cf <= cma_c; -- c M[X,Y]-A ?= + when X"2F" => r_stf <= not a_xor_m_z; r_a <= a_xor_m; r_zf <= a_xor_m_z;-- eor A <- A xor M[X,Y]; + when X"30" | X"31" | X"32" | X"33" => r_stf <='1'; -- sbit M[X,Y](op&3) <- 1 + when X"34" | X"35" | X"36" | X"37" => r_stf <='1'; -- rbit M[X,Y](op&3) <- 0 + when X"38" | X"39" | X"3A" | X"3B" => r_stf <= not m_tst_bit; -- tbit M[X,Y](op&3) == 1 + when X"3C" => -- rti + r_pa <= stack(to_integer(unsigned(r_si-"01")))(10 downto 6); + r_pc <= stack(to_integer(unsigned(r_si-"01")))( 5 downto 0); + r_stf <= stack(to_integer(unsigned(r_si-"01")))(11); + r_zf <= stack(to_integer(unsigned(r_si-"01")))(12); + r_cf <= stack(to_integer(unsigned(r_si-"01")))(13); + r_si <= r_si - "01"; + when X"3D" => single_byte_op <= '0'; -- jpa + when X"3E" => single_byte_op <= '0'; -- en + when X"3F" => single_byte_op <= '0'; -- dis + when X"40" => r_stf <= '1'; r0_port_out <= (r0_port_in or X"1"); -- setd RO(op&3) <- 1 + when X"41" => r_stf <= '1'; r0_port_out <= (r0_port_in or X"2"); -- setd RO(op&3) <- 1 + when X"42" => r_stf <= '1'; r0_port_out <= (r0_port_in or X"4"); -- setd RO(op&3) <- 1 + when X"43" => r_stf <= '1'; r0_port_out <= (r0_port_in or X"8"); -- setd RO(op&3) <- 1 + when X"44" => r_stf <= '1'; r0_port_out <= (r0_port_in and not X"1"); -- setd RO(op&3) <- 0 + when X"45" => r_stf <= '1'; r0_port_out <= (r0_port_in and not X"2"); -- setd RO(op&3) <- 0 + when X"46" => r_stf <= '1'; r0_port_out <= (r0_port_in and not X"4"); -- setd RO(op&3) <- 0 + when X"47" => r_stf <= '1'; r0_port_out <= (r0_port_in and not X"8"); -- setd RO(op&3) <- 0 + when X"48" | X"49" | X"4A" | X"4B" => -- tstd R2(op&3) ?= + r_stf <= not r2_port_in(to_integer(unsigned(rom_data(1 downto 0)))); + when X"4C" | X"4D" | X"4E" | X"4F" => -- tba A(op&3) ?= + r_stf <= not r_a(to_integer(unsigned(rom_data(1 downto 0)))); + when X"50" | X"51" | X"52" | X"53" => -- xd A <-> M[0,op&3] + r_stf <= '1'; r_a <= mem; r_zf <= mem_z; + when X"54" | X"55" | X"56" | X"57" => -- xyd Y <-> M[0,op&3] + r_stf <= '1'; r_y <= mem; r_zf <= mem_z; + when X"58" | X"59" | X"5A" | X"5B" | X"5C" | X"5D" | X"5E" | X"5F" => -- lxi imm (op&7) + r_stf <='1'; r_x <= '0' & rom_data(2 downto 0); r_zf <= imm_x7_z; + when X"60" | X"61" | X"62" | X"63" | X"64" | X"65" | X"66" | X"67" => -- call addr + single_byte_op <= '0'; + when X"68" | X"69" | X"6A" | X"6B" | X"6C" | X"6D" | X"6E" | X"6F" => -- jpl addr + single_byte_op <= '0'; + when X"70" | X"71" | X"72" | X"73" | X"74" | X"75" | X"76" | X"77" | + X"78" | X"79" | X"7A" | X"7B" | X"7C" | X"7D" | X"7E" | X"7F" => -- ai A <- A+imm (op&F) + r_stf <= not a_pim_c; r_a <= a_pim(3 downto 0); r_zf <= a_pim_z; r_cf <= a_pim_c; + when X"80" | X"81" | X"82" | X"83" | X"84" | X"85" | X"86" | X"87" | + X"88" | X"89" | X"8A" | X"8B" | X"8C" | X"8D" | X"8E" | X"8F" => -- lyi Y <- imm (op&F) + r_stf <='1'; r_y <= rom_data(3 downto 0); r_zf <= imm_xF_z; + when X"90" | X"91" | X"92" | X"93" | X"94" | X"95" | X"96" | X"97" | + X"98" | X"99" | X"9A" | X"9B" | X"9C" | X"9D" | X"9E" | X"9F" => -- li A <- imm (op&F) + r_stf <='1'; r_a <= rom_data(3 downto 0); r_zf <= imm_xF_z; + when X"A0" | X"A1" | X"A2" | X"A3" | X"A4" | X"A5" | X"A6" | X"A7" | + X"A8" | X"A9" | X"AA" | X"AB" | X"AC" | X"AD" | X"AE" | X"AF" => -- cyi imm - Y ?= + r_stf <= not im_my_z; r_zf <= im_my_z; r_cf <= im_my_c; + when X"B0" | X"B1" | X"B2" | X"B3" | X"B4" | X"B5" | X"B6" | X"B7" | + X"B8" | X"B9" | X"BA" | X"BB" | X"BC" | X"BD" | X"BE" | X"BF" => -- ci imm - A ?= + r_stf <= not im_ma_z; r_zf <= im_ma_z; r_cf <= im_ma_c; + when others => r_stf <='1'; -- jmp addr if ST (op_code C0..FF) + if r_stf = '1' then r_pc <= rom_data(5 downto 0); end if; -- (let r_pa be incremented when r_pc = 0x3F) + end case; + end if ; + else -- 2 bytes op_code, rom_data = 2nd byte + case op_code is + when X"3D" => r_stf <='1'; r_pa <= rom_data(4 downto 0); r_pc <= r_a & "00"; -- jpa PA <- data&0x1f; PC <- A*4 + when X"3E" => r_stf <='1'; r_pio <= r_pio or rom_data; -- en PIO <- PIO or imm data + when X"3F" => r_stf <='1'; r_pio <= r_pio and not rom_data; -- dis PIO <- PIO and not imm data + when X"60" | X"61" | X"62" | X"63" | X"64" | X"65" | X"66" | X"67" => -- call addr if ST + r_stf <= '1'; + if r_stf = '1' then + stack(to_integer(unsigned(r_si)))(10 downto 0) <= (r_pa & r_pc) + '1'; + r_pc <= rom_data(5 downto 0); + r_pa <= op_code(2 downto 0) & rom_data(7 downto 6); + r_si <= r_si + "01"; + end if; + when X"68" | X"69" | X"6A" | X"6B" | X"6C" | X"6D" | X"6E" | X"6F" => -- jpl if ST + r_stf <= '1'; + if r_stf = '1' then + r_pc <= rom_data(5 downto 0); + r_pa <= op_code(2 downto 0) & rom_data(7 downto 6); + end if; + when others => r_stf <='1'; + end case; + end if; + + end if; + end if; + end if; +end process; + +-- RAM +process(clock_n) +begin + if rising_edge(clock_n) then + if ram_we = '1' then + ram(to_integer(unsigned(ram_addr))) <= ram_di; + end if; + end if; +end process; + +ram_do <= ram(to_integer(unsigned(ram_addr))); + +end struct; \ No newline at end of file diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.ppf b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.ppf new file mode 100644 index 00000000..93e67f9f --- /dev/null +++ b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.qip b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.v b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.v new file mode 100644 index 00000000..7fa0e4da --- /dev/null +++ b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.v @@ -0,0 +1,365 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0, + c1, + c2, + locked); + + input inclk0; + output c0; + output c1; + output c2; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + + altpll altpll_component ( + .inclk (sub_wire6), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 3, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 4, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 3, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 2, + altpll_component.clk1_phase_shift = "0", + altpll_component.clk2_divide_by = 3, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 1, + altpll_component.clk2_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "3" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "9.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "9.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "3" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/bg_graphx.vhd b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/bg_graphx.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/bg_graphx.vhd rename to Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/bg_graphx.vhd diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/bg_palette.vhd b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/bg_palette.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/bg_palette.vhd rename to Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/bg_palette.vhd diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/cs54xx_prog.vhd b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/cs54xx_prog.vhd new file mode 100644 index 00000000..6bc7f7fd --- /dev/null +++ b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/cs54xx_prog.vhd @@ -0,0 +1,86 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cs54xx_prog is +port ( + clk : in std_logic; + addr : in std_logic_vector(9 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cs54xx_prog is + type rom is array(0 to 1023) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"C6",X"C6",X"52",X"12",X"3D",X"06",X"58",X"80",X"90",X"1B",X"0A",X"CA",X"1B",X"71",X"B8",X"C9", + X"3E",X"04",X"59",X"84",X"0D",X"1C",X"18",X"0D",X"1C",X"1A",X"0D",X"1C",X"1A",X"0D",X"1C",X"1A", + X"0D",X"1C",X"1D",X"1C",X"83",X"2F",X"71",X"08",X"0A",X"0D",X"80",X"38",X"F8",X"23",X"01",X"88", + X"20",X"08",X"0D",X"21",X"0E",X"1A",X"68",X"41",X"88",X"22",X"23",X"90",X"01",X"89",X"0D",X"0E", + X"1A",X"0D",X"7F",X"68",X"90",X"58",X"19",X"68",X"90",X"59",X"86",X"19",X"68",X"90",X"08",X"19", + X"68",X"90",X"08",X"19",X"0D",X"B1",X"D8",X"DF",X"B2",X"FF",X"90",X"85",X"1D",X"92",X"E6",X"5B", + X"81",X"0D",X"59",X"85",X"1D",X"91",X"23",X"0C",X"04",X"5B",X"0D",X"B0",X"F5",X"50",X"08",X"0D", + X"B0",X"F8",X"88",X"59",X"D3",X"50",X"08",X"0D",X"59",X"87",X"1A",X"50",X"1D",X"68",X"90",X"85", + X"0D",X"7F",X"68",X"90",X"0D",X"23",X"1C",X"23",X"0E",X"1C",X"1D",X"91",X"88",X"1D",X"68",X"66", + X"89",X"59",X"93",X"0F",X"B1",X"D8",X"8E",X"09",X"8A",X"0D",X"8E",X"38",X"DE",X"90",X"21",X"01", + X"38",X"E5",X"89",X"20",X"E7",X"89",X"22",X"8D",X"0D",X"7F",X"68",X"FC",X"58",X"19",X"68",X"FC", + X"59",X"8B",X"19",X"68",X"FC",X"08",X"19",X"68",X"FC",X"08",X"19",X"0D",X"B1",X"68",X"C0",X"C9", + X"B2",X"68",X"EC",X"90",X"8A",X"1D",X"92",X"68",X"D0",X"5B",X"89",X"0D",X"59",X"8A",X"1D",X"91", + X"23",X"0C",X"78",X"04",X"5B",X"0D",X"B0",X"68",X"E3",X"50",X"08",X"0D",X"B0",X"68",X"E6",X"59", + X"8D",X"68",X"BA",X"50",X"08",X"0D",X"59",X"8C",X"1A",X"50",X"1D",X"FC",X"8A",X"0D",X"7F",X"FC", + X"0D",X"23",X"1C",X"23",X"0E",X"1C",X"1D",X"91",X"8D",X"1D",X"68",X"D0",X"5A",X"8F",X"0D",X"8B", + X"3B",X"C3",X"90",X"81",X"03",X"88",X"0D",X"8A",X"23",X"0E",X"1D",X"89",X"0D",X"8B",X"0E",X"1D", + X"59",X"80",X"38",X"E1",X"5A",X"86",X"0D",X"23",X"8A",X"0E",X"1D",X"87",X"0D",X"8B",X"0E",X"1D", + X"59",X"8F",X"0D",X"7F",X"68",X"12",X"5A",X"8C",X"19",X"68",X"12",X"08",X"19",X"68",X"12",X"08", + X"19",X"68",X"12",X"8F",X"59",X"19",X"0D",X"B0",X"69",X"47",X"5A",X"0D",X"1C",X"23",X"0E",X"1C", + X"1D",X"7F",X"68",X"12",X"91",X"59",X"1D",X"5A",X"84",X"0D",X"8D",X"1D",X"7F",X"D7",X"85",X"0D", + X"8E",X"1D",X"8C",X"90",X"1D",X"68",X"12",X"85",X"0D",X"8E",X"1D",X"B0",X"E3",X"8F",X"1D",X"59", + X"1D",X"68",X"12",X"90",X"8C",X"1D",X"68",X"12",X"1B",X"53",X"54",X"80",X"13",X"5A",X"8F",X"1D", + X"54",X"53",X"1B",X"52",X"3E",X"04",X"3C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FC",X"00",X"00",X"00",X"69",X"C0",X"00",X"00",X"69",X"DC",X"00",X"00",X"6A",X"55",X"00",X"00", + X"6A",X"5D",X"00",X"00",X"69",X"F9",X"00",X"00",X"6A",X"40",X"00",X"00",X"69",X"68",X"00",X"00", + X"FC",X"00",X"00",X"00",X"FC",X"00",X"00",X"00",X"FC",X"00",X"00",X"00",X"FC",X"00",X"00",X"00", + X"FC",X"00",X"00",X"00",X"FC",X"00",X"00",X"00",X"FC",X"00",X"00",X"00",X"52",X"3E",X"04",X"3C", + X"1B",X"53",X"54",X"5B",X"80",X"0D",X"59",X"85",X"1D",X"88",X"93",X"1D",X"5B",X"87",X"0D",X"59", + X"1A",X"5B",X"0D",X"59",X"1D",X"54",X"53",X"1B",X"52",X"3E",X"04",X"3C",X"1B",X"53",X"54",X"5B", + X"88",X"0D",X"59",X"8A",X"1D",X"8D",X"93",X"0A",X"5B",X"0D",X"51",X"08",X"0D",X"59",X"8C",X"1A", + X"51",X"1D",X"53",X"1B",X"52",X"54",X"3E",X"04",X"3C",X"1B",X"53",X"54",X"5A",X"81",X"0D",X"8C", + X"1D",X"82",X"0D",X"8D",X"1D",X"83",X"0D",X"8E",X"1D",X"80",X"0D",X"8F",X"1D",X"92",X"59",X"1D", + X"53",X"1B",X"52",X"54",X"3E",X"04",X"3C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"1B",X"53",X"54",X"5A",X"89",X"55",X"3F",X"04",X"25",X"CB",X"C8",X"25",X"CB",X"80",X"13",X"55", + X"1A",X"12",X"1A",X"55",X"E5",X"1B",X"53",X"54",X"87",X"55",X"3F",X"04",X"E5",X"1B",X"53",X"5B", + X"54",X"8F",X"55",X"3F",X"04",X"25",X"E8",X"E5",X"25",X"E8",X"80",X"13",X"55",X"1A",X"12",X"1A", + X"14",X"55",X"23",X"0C",X"BE",X"E5",X"53",X"1B",X"52",X"54",X"3E",X"04",X"3C",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_cpu1.vhd b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/galaga_cpu1.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_cpu1.vhd rename to Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/galaga_cpu1.vhd diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_cpu2.vhd b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/galaga_cpu2.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_cpu2.vhd rename to Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/galaga_cpu2.vhd diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_cpu3.vhd b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/galaga_cpu3.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_cpu3.vhd rename to Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/galaga_cpu3.vhd diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/rgb.vhd b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/rgb.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/rgb.vhd rename to Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/rgb.vhd diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_samples.vhd b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sound_samples.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_samples.vhd rename to Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sound_samples.vhd diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_seq.vhd b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sound_seq.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_seq.vhd rename to Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sound_seq.vhd diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sp_graphx.vhd b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sp_graphx.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sp_graphx.vhd rename to Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sp_graphx.vhd diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sp_palette.vhd b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sp_palette.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sp_palette.vhd rename to Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sp_palette.vhd