From d543ba623f62c3fd972530b86c9f9a411daebcff Mon Sep 17 00:00:00 2001 From: Gehstock Date: Thu, 26 Mar 2020 02:25:15 +0100 Subject: [PATCH] New Core Sonson by Slingshot --- Arcade_MiST/Capcom SonSon Hardware/README.txt | 14 + .../Sonson_MiST.qpf | 0 .../Sonson_MiST.qsf | 68 +- .../Sonson_MiST.sdc | 2 +- .../clean.bat | 0 .../Capcom SonSon Hardware/meta/SonSon.mra | 42 + .../rtl/Graphics.VHD | 111 +- .../rtl/SonSon_MiST.sv | 144 +- .../rtl/YM2149.sv | 0 .../rtl/bitmapctl_e.vhd | 0 .../rtl/build_id.tcl | 0 .../rtl/dpram.vhd | 0 .../rtl/dprom_2r.vhd | 0 .../rtl/pace.vhd | 105 +- .../rtl/pace_pkg.vhd | 0 .../rtl/pace_pkg_body.vhd | 0 .../Capcom SonSon Hardware/rtl/platform.vhd | 469 ++ .../rtl/platform_pkg.vhd | 35 +- .../rtl/pll.qip | 0 .../rtl/pll.v | 90 +- .../rtl/roms/cram.hex | 0 .../rtl/roms/ss_10_m6.hex | 0 .../rtl/roms/ss_11_m3.hex | 0 .../rtl/roms/ss_12_m4.hex | 0 .../rtl/roms/ss_13_m1.hex | 0 .../rtl/roms/ss_14_m2.hex | 0 .../rtl/roms/ss_9_m5.hex | 0 .../rtl/roms/vram.hex | 0 .../rtl/sdram.sv | 34 +- .../rtl/sonson_soundboard.vhd | 262 + .../rtl/sonson_video_controller.vhd | 129 + .../rtl/sound.vhd | 0 .../rtl/spram.vhd | 0 .../rtl/sprite_array.vhd | 2 +- .../rtl/sprite_pkg.vhd | 0 .../rtl/sprite_pkg_body.vhd | 0 .../rtl/spritectl.vhd | 43 +- .../rtl/spritereg.vhd | 2 +- .../rtl/sprom.vhd | 0 .../Capcom SonSon Hardware/rtl/target_top.vhd | 109 + .../rtl/tilemapctl.vhd | 23 +- .../rtl/tilemapctl_e.vhd | 0 .../rtl/video_controller_pkg.vhd | 0 .../rtl/video_controller_pkg_body.vhd | 0 .../rtl/video_mixer.vhd | 0 .../Sonson_MiST/rtl/cpu09s.vhd | 5679 ----------------- .../Sonson_MiST/rtl/mc6809-master/README.md | 109 - .../Sonson_MiST/rtl/mc6809-master/mc6809.v | 80 - .../Sonson_MiST/rtl/mc6809-master/mc6809e.v | 48 - .../Sonson_MiST/rtl/mc6809-master/mc6809i.v | 4156 ------------ .../Sonson_MiST/rtl/mc6809-master/mc6809s.v | 82 - .../Sonson_MiST/rtl/platform.vhd | 567 -- .../Sonson_MiST/rtl/pll_mist.qip | 4 - .../Sonson_MiST/rtl/pll_mist.vhd | 429 -- .../Sonson_MiST/rtl/roms/sonson.zip | Bin 64728 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/make.bat | 10 - .../rtl/roms/sonson/make_vhdl_prom.exe | Bin 119861 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/sound_rom.vhd | 534 -- .../Sonson_MiST/rtl/roms/sonson/ss.01e | Bin 16384 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ss.02e | Bin 16384 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ss.03e | Bin 16384 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ss_10.m6 | Bin 8192 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ss_11.m3 | Bin 8192 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ss_12.m4 | Bin 8192 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ss_13.m1 | Bin 8192 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ss_14.m2 | Bin 8192 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ss_6.c11 | Bin 8192 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ss_7.b6 | Bin 8192 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ss_8.b5 | Bin 8192 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ss_9.m5 | Bin 8192 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ssb1.k11 | Bin 256 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ssb2.c4 | Bin 256 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ssb3.h7 | Bin 256 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ssb4.b2 | Bin 32 -> 0 bytes .../Sonson_MiST/rtl/roms/sonson/ssb5.b1 | Bin 32 -> 0 bytes .../Sonson_MiST/rtl/roms/ss_01e.hex | 1025 --- .../Sonson_MiST/rtl/roms/ss_02e.hex | 1025 --- .../Sonson_MiST/rtl/roms/ss_03e.hex | 1025 --- .../Sonson_MiST/rtl/roms/ss_7_b6.hex | 513 -- .../Sonson_MiST/rtl/roms/ss_8_b5.hex | 513 -- .../Sonson_MiST/rtl/sonson_soundboard.vhd | 315 - .../Sonson_MiST/rtl/target_top.vhd | 107 - .../Sonson_MiST/rtl/video_controller.vhd | 455 -- 83 files changed, 1318 insertions(+), 17042 deletions(-) create mode 100644 Arcade_MiST/Capcom SonSon Hardware/README.txt rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/Sonson_MiST.qpf (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/Sonson_MiST.qsf (94%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/Sonson_MiST.sdc (98%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/clean.bat (100%) create mode 100644 Arcade_MiST/Capcom SonSon Hardware/meta/SonSon.mra rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/Graphics.VHD (74%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/SonSon_MiST.sv (74%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/YM2149.sv (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/bitmapctl_e.vhd (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/build_id.tcl (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/dpram.vhd (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/dprom_2r.vhd (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/pace.vhd (60%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/pace_pkg.vhd (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/pace_pkg_body.vhd (100%) create mode 100644 Arcade_MiST/Capcom SonSon Hardware/rtl/platform.vhd rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/platform_pkg.vhd (89%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/pll.qip (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/pll.v (84%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/roms/cram.hex (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/roms/ss_10_m6.hex (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/roms/ss_11_m3.hex (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/roms/ss_12_m4.hex (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/roms/ss_13_m1.hex (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/roms/ss_14_m2.hex (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/roms/ss_9_m5.hex (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/roms/vram.hex (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/sdram.sv (91%) create mode 100644 Arcade_MiST/Capcom SonSon Hardware/rtl/sonson_soundboard.vhd create mode 100644 Arcade_MiST/Capcom SonSon Hardware/rtl/sonson_video_controller.vhd rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/sound.vhd (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/spram.vhd (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/sprite_array.vhd (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/sprite_pkg.vhd (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/sprite_pkg_body.vhd (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/spritectl.vhd (79%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/spritereg.vhd (98%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/sprom.vhd (100%) create mode 100644 Arcade_MiST/Capcom SonSon Hardware/rtl/target_top.vhd rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/tilemapctl.vhd (87%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/tilemapctl_e.vhd (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/video_controller_pkg.vhd (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/video_controller_pkg_body.vhd (100%) rename Arcade_MiST/{SonSon Hardware/Sonson_MiST => Capcom SonSon Hardware}/rtl/video_mixer.vhd (100%) delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/cpu09s.vhd delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/README.md delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809.v delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809e.v delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809i.v delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809s.v delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform.vhd delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.qip delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.vhd delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson.zip delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/make.bat delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/make_vhdl_prom.exe delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/sound_rom.vhd delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss.01e delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss.02e delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss.03e delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_10.m6 delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_11.m3 delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_12.m4 delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_13.m1 delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_14.m2 delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_6.c11 delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_7.b6 delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_8.b5 delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_9.m5 delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb1.k11 delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb2.c4 delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb3.h7 delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb4.b2 delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb5.b1 delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_01e.hex delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_02e.hex delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_03e.hex delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_7_b6.hex delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_8_b5.hex delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sonson_soundboard.vhd delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/target_top.vhd delete mode 100644 Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller.vhd diff --git a/Arcade_MiST/Capcom SonSon Hardware/README.txt b/Arcade_MiST/Capcom SonSon Hardware/README.txt new file mode 100644 index 00000000..d0a991de --- /dev/null +++ b/Arcade_MiST/Capcom SonSon Hardware/README.txt @@ -0,0 +1,14 @@ +Capcom SonSon Arcade game +========================= + +Based on old PACE code by Mark McDougall(tcdev) + +MiST port usage +=============== + +- Create ROM file from the MRA file using the MRA utility. + Example: mra -z /path/to/mame/roms SonSon.mra +- Copy the ROM files to the root of the SD Card +- Copy the RBF files to the SD Card + +MRA utility: https://github.com/sebdel/mra-tools-c/ diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qpf b/Arcade_MiST/Capcom SonSon Hardware/Sonson_MiST.qpf similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qpf rename to Arcade_MiST/Capcom SonSon Hardware/Sonson_MiST.qpf diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qsf b/Arcade_MiST/Capcom SonSon Hardware/Sonson_MiST.qsf similarity index 94% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qsf rename to Arcade_MiST/Capcom SonSon Hardware/Sonson_MiST.qsf index 2cb18b50..d4b6aaf3 100644 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qsf +++ b/Arcade_MiST/Capcom SonSon Hardware/Sonson_MiST.qsf @@ -158,7 +158,7 @@ set_global_assignment -name GENERATE_RBF_FILE ON # SignalTap II Assignments # ======================== set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/druaga.stp +set_global_assignment -name USE_SIGNALTAP_FILE output_files/sprite.stp # Power Estimation Assignments # ============================ @@ -190,40 +190,6 @@ set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name SYSTEMVERILOG_FILE rtl/SonSon_MiST.sv -set_global_assignment -name VHDL_FILE rtl/target_top.vhd -set_global_assignment -name VHDL_FILE rtl/platform_pkg.vhd -set_global_assignment -name VHDL_FILE rtl/platform.vhd -set_global_assignment -name VHDL_FILE rtl/pace_pkg_body.vhd -set_global_assignment -name VHDL_FILE rtl/pace_pkg.vhd -set_global_assignment -name VHDL_FILE rtl/pace.vhd -set_global_assignment -name VHDL_FILE rtl/Graphics.VHD -set_global_assignment -name VHDL_FILE rtl/video_mixer.vhd -set_global_assignment -name VHDL_FILE rtl/video_controller_pkg_body.vhd -set_global_assignment -name VHDL_FILE rtl/video_controller_pkg.vhd -set_global_assignment -name VHDL_FILE rtl/video_controller.vhd -set_global_assignment -name VHDL_FILE rtl/spritereg.vhd -set_global_assignment -name VHDL_FILE rtl/spritectl.vhd -set_global_assignment -name VHDL_FILE rtl/sprite_pkg_body.vhd -set_global_assignment -name VHDL_FILE rtl/sprite_pkg.vhd -set_global_assignment -name VHDL_FILE rtl/sprite_array.vhd -set_global_assignment -name VHDL_FILE rtl/bitmapctl_e.vhd -set_global_assignment -name VHDL_FILE rtl/tilemapctl_e.vhd -set_global_assignment -name VHDL_FILE rtl/tilemapctl.vhd -set_global_assignment -name VHDL_FILE rtl/sonson_soundboard.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv -set_global_assignment -name VHDL_FILE rtl/sound.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv -set_global_assignment -name VERILOG_FILE rtl/pll.v -set_global_assignment -name VHDL_FILE rtl/dprom_2r.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/cpu09s.vhd -set_global_assignment -name VHDL_FILE rtl/roms/sonson/sound_rom.vhd -set_global_assignment -name VHDL_FILE ../../../common/CPU/T80/Z80.vhd -set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip -set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top @@ -258,6 +224,34 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO -set_global_assignment -name VERILOG_FILE ../../../common/CPU/MC6809/mc6809.v -set_global_assignment -name VERILOG_FILE ../../../common/CPU/MC6809/mc6809i.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/SonSon_MiST.sv +set_global_assignment -name VHDL_FILE rtl/target_top.vhd +set_global_assignment -name VHDL_FILE rtl/platform_pkg.vhd +set_global_assignment -name VHDL_FILE rtl/platform.vhd +set_global_assignment -name VHDL_FILE rtl/pace_pkg_body.vhd +set_global_assignment -name VHDL_FILE rtl/pace_pkg.vhd +set_global_assignment -name VHDL_FILE rtl/pace.vhd +set_global_assignment -name VHDL_FILE rtl/Graphics.VHD +set_global_assignment -name VHDL_FILE rtl/video_mixer.vhd +set_global_assignment -name VHDL_FILE rtl/sonson_video_controller.vhd +set_global_assignment -name VHDL_FILE rtl/video_controller_pkg_body.vhd +set_global_assignment -name VHDL_FILE rtl/video_controller_pkg.vhd +set_global_assignment -name VHDL_FILE rtl/spritereg.vhd +set_global_assignment -name VHDL_FILE rtl/spritectl.vhd +set_global_assignment -name VHDL_FILE rtl/sprite_pkg_body.vhd +set_global_assignment -name VHDL_FILE rtl/sprite_pkg.vhd +set_global_assignment -name VHDL_FILE rtl/sprite_array.vhd +set_global_assignment -name VHDL_FILE rtl/bitmapctl_e.vhd +set_global_assignment -name VHDL_FILE rtl/tilemapctl_e.vhd +set_global_assignment -name VHDL_FILE rtl/tilemapctl.vhd +set_global_assignment -name VHDL_FILE rtl/sonson_soundboard.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name VHDL_FILE rtl/dprom_2r.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/sprom.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VERILOG_FILE ../../common/CPU/MC6809/mc6809i.v +set_global_assignment -name QIP_FILE ../../common/mist/mist.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.sdc b/Arcade_MiST/Capcom SonSon Hardware/Sonson_MiST.sdc similarity index 98% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.sdc rename to Arcade_MiST/Capcom SonSon Hardware/Sonson_MiST.sdc index 80fe5371..6f6e4cc0 100644 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.sdc +++ b/Arcade_MiST/Capcom SonSon Hardware/Sonson_MiST.sdc @@ -54,7 +54,7 @@ set_time_format -unit ns -decimal_places 3 create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]" -set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]" +set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[2]" #************************************************************** # Create Generated Clock #************************************************************** diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/clean.bat b/Arcade_MiST/Capcom SonSon Hardware/clean.bat similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/clean.bat rename to Arcade_MiST/Capcom SonSon Hardware/clean.bat diff --git a/Arcade_MiST/Capcom SonSon Hardware/meta/SonSon.mra b/Arcade_MiST/Capcom SonSon Hardware/meta/SonSon.mra new file mode 100644 index 00000000..2bebb5dc --- /dev/null +++ b/Arcade_MiST/Capcom SonSon Hardware/meta/SonSon.mra @@ -0,0 +1,42 @@ + + SonSon + 0216 + sonson + Capcom + sonson + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/Graphics.VHD b/Arcade_MiST/Capcom SonSon Hardware/rtl/Graphics.VHD similarity index 74% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/Graphics.VHD rename to Arcade_MiST/Capcom SonSon Hardware/rtl/Graphics.VHD index 9b3d355e..5d551730 100644 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/Graphics.VHD +++ b/Arcade_MiST/Capcom SonSon Hardware/rtl/Graphics.VHD @@ -20,20 +20,20 @@ entity Graphics is sprite_reg_i : in to_SPRITE_REG_t; sprite_ctl_i : in to_SPRITE_CTL_t; sprite_ctl_o : out from_SPRITE_CTL_t; - spr0_hit : out std_logic; - + spr0_hit : out std_logic; + graphics_i : in to_GRAPHICS_t; graphics_o : out from_GRAPHICS_t; - video_i : in from_VIDEO_t; - video_o : out to_VIDEO_t + video_i : in from_VIDEO_t; + video_o : out to_VIDEO_t ); end Graphics; architecture SYN of Graphics is - alias clk : std_logic is video_i.clk; + alias clk : std_logic is video_i.clk; signal from_video_ctl : from_VIDEO_CTL_t; signal bitmap_ctl_o_s : from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); @@ -41,21 +41,21 @@ architecture SYN of Graphics is signal sprite_ctl_o_s : from_SPRITE_CTL_t; signal sprite_pri : std_logic; - signal rgb_data : RGB_t; + signal rgb_data : RGB_t; -- before OSD is mixed in signal video_o_s : to_VIDEO_t; - + begin -- dodgy OSD transparency... - video_o.clk <= video_o_s.clk; + video_o.clk <= video_o_s.clk; video_o.rgb.r <= video_o_s.rgb.r; video_o.rgb.g <= video_o_s.rgb.g; video_o.rgb.b <= video_o_s.rgb.b; - video_o.hsync <= video_o_s.hsync; - video_o.vsync <= video_o_s.vsync; - video_o.hblank <= video_o_s.hblank; - video_o.vblank <= video_o_s.vblank; + video_o.hsync <= video_o_s.hsync; + video_o.vsync <= video_o_s.vsync; + video_o.hblank <= video_o_s.hblank; + video_o.vblank <= video_o_s.vblank; graphics_o.y <= from_video_ctl.y; -- should this be the 'real' vblank or the 'active' vblank? @@ -63,38 +63,21 @@ begin graphics_o.hblank <= video_o_s.hblank; graphics_o.vblank <= video_o_s.vblank; --graphics_o.vblank <= from_video_ctl.vblank; - - pace_video_controller_inst : entity work.pace_video_controller - generic map - ( - CONFIG => PACE_VIDEO_CONTROLLER_TYPE, - DELAY => PACE_VIDEO_PIPELINE_DELAY, - H_SIZE => PACE_VIDEO_H_SIZE, - V_SIZE => PACE_VIDEO_V_SIZE, - L_CROP => PACE_VIDEO_L_CROP, - R_CROP => PACE_VIDEO_R_CROP, - H_SCALE => PACE_VIDEO_H_SCALE, - V_SCALE => PACE_VIDEO_V_SCALE, - H_SYNC_POL => PACE_VIDEO_H_SYNC_POLARITY, - V_SYNC_POL => PACE_VIDEO_V_SYNC_POLARITY, - BORDER_RGB => PACE_VIDEO_BORDER_RGB - ) + + pace_video_controller_inst : entity work.sonson_video_controller port map ( -- clocking etc video_i => video_i, - - -- register interface - reg_i.h_scale => "000", - reg_i.v_scale => "000", + -- video data signals (in) - rgb_i => rgb_data, + rgb_i => rgb_data, -- video control signals (out) video_ctl_o => from_video_ctl, -- VGA signals (out) - video_o => video_o_s + video_o => video_o_s ); pace_video_mixer_inst : entity work.pace_video_mixer @@ -105,19 +88,19 @@ begin sprite_rgb => sprite_ctl_o_s.rgb, sprite_set => sprite_ctl_o_s.set, sprite_pri => sprite_pri, - + video_ctl_i => from_video_ctl, graphics_i => graphics_i, rgb_o => rgb_data ); - - GEN_NO_BITMAPS : if PACE_VIDEO_NUM_BITMAPS = 0 generate + + GEN_NO_BITMAPS : if PACE_VIDEO_NUM_BITMAPS = 0 generate --bitmap_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0'); - end generate GEN_NO_BITMAPS; - - GEN_BITMAP_1 : if PACE_VIDEO_NUM_BITMAPS > 0 generate - - forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_1) + end generate GEN_NO_BITMAPS; + + GEN_BITMAP_1 : if PACE_VIDEO_NUM_BITMAPS > 0 generate + + forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_1) generic map ( DELAY => PACE_VIDEO_PIPELINE_DELAY @@ -222,30 +205,30 @@ begin ctl_o => tilemap_ctl_o_s(2), graphics_i => graphics_i - ); + ); + + end generate GEN_TILEMAP_2; - end generate GEN_TILEMAP_2; - tilemap_ctl_o <= tilemap_ctl_o_s; - GEN_NO_SPRITES : if PACE_VIDEO_NUM_SPRITES = 0 generate + GEN_NO_SPRITES : if PACE_VIDEO_NUM_SPRITES = 0 generate sprite_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0'); sprite_pri <= '0'; spr0_hit <= '0'; - end generate GEN_NO_SPRITES; - - GEN_SPRITES : if PACE_VIDEO_NUM_SPRITES > 0 generate - - sprites_inst : sprite_array + end generate GEN_NO_SPRITES; + + GEN_SPRITES : if PACE_VIDEO_NUM_SPRITES > 0 generate + + sprites_inst : sprite_array generic map ( N_SPRITES => PACE_VIDEO_NUM_SPRITES, DELAY => PACE_VIDEO_PIPELINE_DELAY ) - port map - ( - reset => video_i.reset, - + port map + ( + reset => video_i.reset, + -- register interface reg_i => sprite_reg_i, @@ -254,16 +237,16 @@ begin graphics_i => graphics_i, - row_a => sprite_ctl_o_s.a, - row_d => sprite_ctl_i.d, - - rgb => sprite_ctl_o_s.rgb, - set => sprite_ctl_o_s.set, - pri => sprite_pri, - spr0_set => spr0_hit - ); + row_a => sprite_ctl_o_s.a, + row_d => sprite_ctl_i.d, - end generate GEN_SPRITES; + rgb => sprite_ctl_o_s.rgb, + set => sprite_ctl_o_s.set, + pri => sprite_pri, + spr0_set => spr0_hit + ); + + end generate GEN_SPRITES; sprite_ctl_o <= sprite_ctl_o_s; diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/SonSon_MiST.sv b/Arcade_MiST/Capcom SonSon Hardware/rtl/SonSon_MiST.sv similarity index 74% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/SonSon_MiST.sv rename to Arcade_MiST/Capcom SonSon Hardware/rtl/SonSon_MiST.sv index ce52ed4b..198d047a 100644 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/SonSon_MiST.sv +++ b/Arcade_MiST/Capcom SonSon Hardware/rtl/SonSon_MiST.sv @@ -1,38 +1,3 @@ -/*************************************************************************** -Son Son memory map (preliminary) -driver by Mirko Buffoni -MAIN CPU: -0000-0fff RAM -1000-13ff Video RAM -1400-17ff Color RAM -2020-207f Sprites -4000-ffff ROM -read: -3002 IN0 -3003 IN1 -3004 IN2 -3005 DSW0 -3006 DSW1 -write: -3000 horizontal scroll -3008 watchdog reset -3018 flipscreen (inverted) -3010 command for the audio CPU -3019 trigger FIRQ on audio CPU -SOUND CPU: -0000-07ff RAM -e000-ffff ROM -read: -a000 command from the main CPU -write: -2000 8910 #1 control -2001 8910 #1 write -4000 8910 #2 control -4001 8910 #2 write -TODO: -- Fix Service Mode Output Test: press p1/p2 shot to insert coin -- Flip Screen DIP is noted in service manual and added to DIP LOCATIONS, but not working. -***************************************************************************/ module SonSon_MiST( output LED, output [5:0] VGA_R, @@ -66,12 +31,12 @@ module SonSon_MiST( `include "rtl/build_id.v" localparam CONF_STR = { - "SONSON;ROM;", + "SONSON;;", "O2,Rotate Controls,Off,On;", "O34,Scanlines,Off,25%,50%,75%;", "O5,Blending,Off,On;", "O6,Freeze,Off,On;", - "O7,Flip,Off,On;", + //"O7,Flip,Off,On;", "O8,Test,Off,On;", "T0,Reset;", "V,v1.0.",`BUILD_DATE @@ -87,13 +52,13 @@ wire test = status[8]; assign LED = ~ioctl_downl; assign SDRAM_CKE = 1; assign SDRAM_CLK = clk_sd; -wire clk_sys, clk_vid, clk_sd; +wire clk_sys, clk_sd; wire pll_locked; + pll pll( .inclk0(CLOCK_27), .areset(0), - .c0(clk_sys),//20 - .c1(clk_vid),//40 + .c0(clk_sys),//24 .c2(clk_sd), .locked(pll_locked) ); @@ -133,11 +98,12 @@ user_io( ); wire [15:0] cpu_rom_addr; -//wire [15:0] rom_addr; wire [15:0] rom_do; -wire [12:0] tile_rom_addr; -//wire [12:0] tile_addr; +wire [12:0] snd_rom_addr; +wire [15:0] snd_do; + +wire [13:1] tile_rom_addr; wire [15:0] tile_do; wire ioctl_downl; @@ -147,7 +113,7 @@ wire [24:0] ioctl_addr; wire [7:0] ioctl_dout; data_io data_io( - .clk_sys ( clk_sd ), + .clk_sys ( clk_sys ), .SPI_SCK ( SPI_SCK ), .SPI_SS2 ( SPI_SS2 ), .SPI_DI ( SPI_DI ), @@ -164,7 +130,7 @@ sdram sdram( .init_n ( pll_locked ), .clk ( clk_sd ), - // port1 used for main + sound CPU + // port1 used for main CPU + tiledata .port1_req ( port1_req ), .port1_ack ( ), .port1_a ( ioctl_addr[23:1] ), @@ -175,17 +141,19 @@ sdram sdram( .cpu1_addr ( ioctl_downl ? 16'hffff : {1'b0, cpu_rom_addr[15:1]} ), .cpu1_q ( rom_do ), - .snd_addr ( ioctl_downl ? 16'hffff : (16'h6000 + tile_rom_addr[12:1]) ), - .snd_q ( tile_do ), + .tile_addr ( ioctl_downl ? 16'hffff : {1'b1, 2'b00, tile_rom_addr} ), + .tile_q ( tile_do ), - // port2 for sprite graphics - .port2_req ( ), + // port2 for sound CPU + .port2_req ( port2_req ), .port2_ack ( ), - .port2_a ( ), - .port2_ds ( ), - .port2_we ( ), - .port2_d ( ), - .port2_q ( ) + .port2_a ( ioctl_addr[23:1] ), + .port2_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ), + .port2_we ( ioctl_downl ), + .port2_d ( {ioctl_dout, ioctl_dout} ), + .port2_q ( ), + .snd_addr ( snd_rom_addr[12:1] ), + .snd_q ( snd_do ) ); // ROM download controller @@ -198,7 +166,6 @@ always @(posedge clk_sys) begin port2_req <= ~port2_req; end end - // async clock domain crossing here (clk_snd -> clk_sys) end // reset signal generation @@ -217,18 +184,28 @@ always @(posedge clk_sys) begin end -wire [11:0] audio; +wire [9:0] snd_l, snd_r; wire hs, vs, hb, vb; -wire blankn = ~(hb | vb); +reg blankn; wire [3:0] g,b,r; -wire vma; +reg clk_vid_en; // 6 MHz + +always @(posedge clk_sys) begin + reg [1:0] count; + count <= count + 1'd1; + + clk_vid_en <= 0; + if (count == 0) clk_vid_en <= 1; + + if (clk_vid_en) blankn <= ~(hb | vb); +end + target_top target_top( .clk_sys(clk_sys), - .clk_vid(clk_vid), + .clk_vid_en(clk_vid_en), .reset_in(reset), - .vma(vma), - .snd_l(), - .snd_r(), + .snd_l(snd_l), + .snd_r(snd_r), .vid_hs(hs), .vid_vs(vs), .vid_hb(hb), @@ -236,16 +213,18 @@ target_top target_top( .vid_r(r), .vid_g(g), .vid_b(b), - .inputs_p1(~{2'b00,m_down,m_up,m_right,m_left,1'b0,m_fireC}), - .inputs_p2(~{2'b00,m_down2,m_up2,m_right2,m_left2,1'b0,m_fire2C}), + .inputs_p1(~{2'b00,m_down,m_up,m_right,m_left,1'b0,m_fireA}), + .inputs_p2(~{2'b00,m_down2,m_up2,m_right2,m_left2,1'b0,m_fire2A}), .inputs_sys(~{2'b00,m_coin2,m_coin1,2'b00,m_two_players,m_one_player}), - .inputs_dip1(~{flip,test,"011111"}), - .inputs_dip2(~{freeze,"1111111"}), + .inputs_dip1(~{flip,test,6'b011111}), + .inputs_dip2(~{freeze,7'b1111111}), .cpu_rom_addr(cpu_rom_addr), .cpu_rom_do(cpu_rom_addr[0] ? rom_do[15:8] : rom_do[7:0]), + .snd_rom_addr(snd_rom_addr), + .snd_rom_do(snd_rom_addr[0] ? snd_do[15:8] : snd_do[7:0]), .tile_rom_addr(tile_rom_addr), .tile_rom_do(tile_do) - ); + ); mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video( .clk_sys ( clk_sys ), @@ -255,35 +234,40 @@ mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video( .R ( blankn ? r : 0 ), .G ( blankn ? g : 0 ), .B ( blankn ? b : 0 ), - .HSync ( hs ), - .VSync ( vs ), + .HSync ( ~hs ), + .VSync ( ~vs ), .VGA_R ( VGA_R ), .VGA_G ( VGA_G ), .VGA_B ( VGA_B ), .VGA_VS ( VGA_VS ), .VGA_HS ( VGA_HS ), .rotate ( { 1'b1, rotate } ), - .ce_divider ( 1'b0 ), - .scandoubler_disable( 1),// scandoublerD ), + .ce_divider ( 1'b1 ), + .scandoubler_disable( scandoublerD ), .scanlines ( scanlines ), .blend ( blend ), .ypbpr ( ypbpr ), .no_csync ( no_csync ) ); -wire dac_o; -assign AUDIO_L = dac_o; -assign AUDIO_R = dac_o; - dac #( - .C_bits(12)) -dac( + .C_bits(10)) +dac_l( .clk_i(clk_sys), .res_n_i(1), - .dac_i(audio), - .dac_o(dac_o) + .dac_i(snd_l), + .dac_o(AUDIO_L) ); - + +dac #( + .C_bits(10)) +dac_r( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(snd_r), + .dac_o(AUDIO_R) + ); + wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF; wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F; wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players; diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/YM2149.sv b/Arcade_MiST/Capcom SonSon Hardware/rtl/YM2149.sv similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/YM2149.sv rename to Arcade_MiST/Capcom SonSon Hardware/rtl/YM2149.sv diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/bitmapctl_e.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/bitmapctl_e.vhd similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/bitmapctl_e.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/bitmapctl_e.vhd diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/build_id.tcl b/Arcade_MiST/Capcom SonSon Hardware/rtl/build_id.tcl similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/build_id.tcl rename to Arcade_MiST/Capcom SonSon Hardware/rtl/build_id.tcl diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/dpram.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/dpram.vhd similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/dpram.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/dpram.vhd diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/dprom_2r.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/dprom_2r.vhd similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/dprom_2r.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/dprom_2r.vhd diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/pace.vhd similarity index 60% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/pace.vhd index 9693c4e4..7daabdd2 100644 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace.vhd +++ b/Arcade_MiST/Capcom SonSon Hardware/rtl/pace.vhd @@ -13,7 +13,7 @@ entity PACE is ( -- clocks and resets clkrst_i : in from_CLKRST_t; - vma : out std_logic; + -- controller inputs inputs_p1 : in std_logic_vector(7 downto 0); inputs_p2 : in std_logic_vector(7 downto 0); @@ -29,10 +29,12 @@ entity PACE is audio_o : out to_AUDIO_t; platform_i : in from_PLATFORM_IO_t; platform_o : out to_PLATFORM_IO_t; - cpu_rom_addr : out std_logic_vector(15 downto 0); - cpu_rom_do : in std_logic_vector(7 downto 0); - tile_rom_addr : out std_logic_vector(12 downto 0); - tile_rom_do : in std_logic_vector(15 downto 0) + cpu_rom_addr : out std_logic_vector(15 downto 0); + cpu_rom_do : in std_logic_vector(7 downto 0); + tile_rom_addr : out std_logic_vector(12 downto 0); + tile_rom_do : in std_logic_vector(15 downto 0); + snd_rom_addr : out std_logic_vector(12 downto 0); + snd_rom_do : in std_logic_vector(7 downto 0) ); end entity PACE; @@ -54,50 +56,53 @@ architecture SYN of PACE is signal to_graphics : to_GRAPHICS_t; signal from_graphics : from_GRAPHICS_t; - - signal to_sound : to_SOUND_t; - signal from_sound : from_sound_t; + + signal snd_irq : std_logic; + signal snd_data : std_logic_vector(7 downto 0); + + signal video_out : to_VIDEO_t; begin + video_o <= video_out; platform_inst : entity work.platform port map ( -- clocking and reset clkrst_i => clkrst_i, - vma => vma, -- controller inputs - inputs_p1 => inputs_p1, - inputs_p2 => inputs_p2, - inputs_sys => inputs_sys, - inputs_dip1 => inputs_dip1, - inputs_dip2 => inputs_dip2, + inputs_p1 => inputs_p1, + inputs_p2 => inputs_p2, + inputs_sys => inputs_sys, + inputs_dip1 => inputs_dip1, + inputs_dip2 => inputs_dip2, -- graphics bitmap_i => from_bitmap_ctl, bitmap_o => to_bitmap_ctl, - + tilemap_i => from_tilemap_ctl, tilemap_o => to_tilemap_ctl, - + sprite_reg_o => to_sprite_reg, sprite_i => from_sprite_ctl, sprite_o => to_sprite_ctl, spr0_hit => spr0_hit, - + graphics_i => from_graphics, graphics_o => to_graphics, - + -- sound - snd_i => from_sound, - snd_o => to_sound, + snd_irq => snd_irq, + snd_data => snd_data, + platform_i => platform_i, platform_o => platform_o, - cpu_rom_addr => cpu_rom_addr, - cpu_rom_do => cpu_rom_do, - tile_rom_addr => tile_rom_addr, - tile_rom_do => tile_rom_do + cpu_rom_addr => cpu_rom_addr, + cpu_rom_do => cpu_rom_do, + tile_rom_addr => tile_rom_addr, + tile_rom_do => tile_rom_do ); graphics_inst : entity work.Graphics @@ -113,48 +118,30 @@ begin sprite_ctl_i => to_sprite_ctl, sprite_ctl_o => from_sprite_ctl, spr0_hit => spr0_hit, - + graphics_i => to_graphics, graphics_o => from_graphics, - + -- video (incl. clk) - video_i => video_i, - video_o => video_o + video_i => video_i, + video_o => video_out ); - SOUND_BLOCK : block - signal snd_data_l : std_logic_vector(7 downto 0); - signal snd_data_r : std_logic_vector(7 downto 0); - signal snd_a : std_logic_vector(15 downto 0); - begin - - snd_a <= std_logic_vector(resize(unsigned(to_sound.a), snd_a'length)); - - sound_inst : entity work.Sound - generic map + sound_inst : entity work.sonson_soundboard + port map ( - CLK_MHz => CLK0_FREQ_MHz - ) - port map - ( - sysclk => clkrst_i.clk(0), -- fudge for now - reset => clkrst_i.rst(0), + -- clocking and reset + clkrst_i => clkrst_i, - sndif_rd => to_sound.rd, - sndif_wr => to_sound.wr, - sndif_addr => snd_a, - sndif_datai => to_sound.d, + sound_irq => snd_irq, + sound_data => snd_data, + vblank => video_out.vblank, - snd_clk => audio_o.clk, - snd_data_l => snd_data_l, - snd_data_r => snd_data_r, - sndif_datao => from_sound.d - ); + audio_out_l => audio_o.ldata(9 downto 0), + audio_out_r => audio_o.rdata(9 downto 0), + + snd_rom_addr => snd_rom_addr, + snd_rom_do => snd_rom_do + ); - -- route audio to both channels - audio_o.ldata <= snd_data_l & "00000000"; - audio_o.rdata <= snd_data_r & "00000000"; - - end block SOUND_BLOCK; - end SYN; diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace_pkg.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/pace_pkg.vhd similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace_pkg.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/pace_pkg.vhd diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace_pkg_body.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/pace_pkg_body.vhd similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace_pkg_body.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/pace_pkg_body.vhd diff --git a/Arcade_MiST/Capcom SonSon Hardware/rtl/platform.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/platform.vhd new file mode 100644 index 00000000..0b024e00 --- /dev/null +++ b/Arcade_MiST/Capcom SonSon Hardware/rtl/platform.vhd @@ -0,0 +1,469 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; +use work.sprite_pkg.all; +use work.platform_pkg.all; + +entity platform is + port + ( + -- clocking and reset + clkrst_i : in from_CLKRST_t; + -- controller inputs + inputs_p1 : in std_logic_vector(7 downto 0); + inputs_p2 : in std_logic_vector(7 downto 0); + inputs_sys : in std_logic_vector(7 downto 0); + inputs_dip1 : in std_logic_vector(7 downto 0); + inputs_dip2 : in std_logic_vector(7 downto 0); + + bitmap_i : in from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); + bitmap_o : out to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); + + tilemap_i : in from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); + tilemap_o : out to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); + + sprite_reg_o : out to_SPRITE_REG_t; + sprite_i : in from_SPRITE_CTL_t; + sprite_o : out to_SPRITE_CTL_t; + spr0_hit : in std_logic; + + snd_irq : out std_logic; + snd_data : out std_logic_vector(7 downto 0); + + -- various graphics information + graphics_i : in from_GRAPHICS_t; + graphics_o : out to_GRAPHICS_t; + + platform_i : in from_PLATFORM_IO_t; + platform_o : out to_PLATFORM_IO_t; + + cpu_rom_addr : out std_logic_vector(15 downto 0); + cpu_rom_do : in std_logic_vector(7 downto 0); + tile_rom_addr : out std_logic_vector(12 downto 0); + tile_rom_do : in std_logic_vector(15 downto 0) + ); + +end platform; + +architecture SYN of platform is + + alias clk_24M : std_logic is clkrst_i.clk(0); + alias rst_24M : std_logic is clkrst_i.rst(0); + alias clk_video : std_logic is clkrst_i.clk(1); + signal cpu_reset : std_logic; + + -- uP signals + signal clk_E : std_logic; + signal clk_Q : std_logic; + signal cpu_r_wn : std_logic; + signal cpu_a : std_logic_vector(15 downto 0); + signal cpu_d_i : std_logic_vector(7 downto 0); + signal cpu_d_o : std_logic_vector(7 downto 0); + signal cpu_irq : std_logic; + signal cpu_bs : std_logic; + signal cpu_ba : std_logic; + + -- ROM signals + signal rom_cs : std_logic; + signal rom_d_o : std_logic_vector(7 downto 0); + + -- RAM signals + signal wram_cs : std_logic; + signal wram_wr : std_logic; + signal wram_d_o : std_logic_vector(7 downto 0); + signal vram_cs : std_logic; + signal vram_d_o : std_logic_vector(7 downto 0); + signal vram_wr : std_logic; + signal cram_cs : std_logic; + signal cram_d_o : std_logic_vector(7 downto 0); + signal cram_wr : std_logic; + signal sprite_cs : std_logic; + + -- I/O signals + signal scroll_cs : std_logic; + signal in0_cs : std_logic; + signal in1_cs : std_logic; + signal in2_cs : std_logic; + signal dsw1_cs : std_logic; + signal dsw2_cs : std_logic; + signal snd_cs : std_logic; + + signal vblank_r : std_logic; + + COMPONENT mc6809i + GENERIC ( ILLEGAL_INSTRUCTIONS : STRING := "GHOST" ); + PORT + ( + D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DOut : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + RnW : OUT STD_LOGIC; + E : IN STD_LOGIC; + Q : IN STD_LOGIC; + BS : OUT STD_LOGIC; + BA : OUT STD_LOGIC; + nIRQ : IN STD_LOGIC; + nFIRQ : IN STD_LOGIC; + nNMI : IN STD_LOGIC; + AVMA : OUT STD_LOGIC; + BUSY : OUT STD_LOGIC; + LIC : OUT STD_LOGIC; + nHALT : IN STD_LOGIC; + nRESET : IN STD_LOGIC; + nDMABREQ : IN STD_LOGIC; + RegData : OUT STD_LOGIC_VECTOR(111 DOWNTO 0) + ); +END COMPONENT; + +begin + + wram_cs <= '1' when STD_MATCH(cpu_a, "0000------------") else '0';-- RAM $0000-$0FFF + vram_cs <= '1' when STD_MATCH(cpu_a, "000100----------") else '0';-- video ram $1000-$13FF + cram_cs <= '1' when STD_MATCH(cpu_a, "000101----------") else '0';-- colour ram $1400-$17FF + sprite_cs <= '1' when STD_MATCH(cpu_a, X"20"&"001-----") else + '1' when STD_MATCH(cpu_a, X"20"&"01------") else + '0';-- sprite 'ram' $2020-$207F + -- I/O + scroll_cs <= '1' when STD_MATCH(cpu_a, X"3000") else '0'; + in0_cs <= '1' when STD_MATCH(cpu_a, X"3002") else '0'; + in1_cs <= '1' when STD_MATCH(cpu_a, X"3003") else '0'; + in2_cs <= '1' when STD_MATCH(cpu_a, X"3004") else '0'; + dsw1_cs <= '1' when STD_MATCH(cpu_a, X"3005") else '0'; + dsw2_cs <= '1' when STD_MATCH(cpu_a, X"3006") else '0'; + rom_cs <= '1' when (cpu_a > X"3FFF") else '0'; + snd_cs <= '1' when cpu_a(15 downto 4) = x"301" else '0'; + + -- memory block write enables + wram_wr <= wram_cs and not cpu_r_wn; + vram_wr <= vram_cs and not cpu_r_wn; + cram_wr <= cram_cs and not cpu_r_wn; + + -- memory read mux + cpu_d_i <= wram_d_o when wram_cs = '1' else + vram_d_o when vram_cs = '1' else + cram_d_o when cram_cs = '1' else + inputs_p1 when in0_cs = '1' else + inputs_p2 when in1_cs = '1' else + inputs_sys when in2_cs = '1' else + inputs_dip1 when dsw1_cs = '1' else + inputs_dip2 when dsw2_cs = '1' else + -- flip off, service off, coin A, 1C1C +-- (X"80" or X"40" or X"10" or X"0F") when dsw1_cs = '1' else + -- freeze off, easy, 20K/80K/100K, 3 lives +-- (X"80" or X"60" or X"08" or X"03") when dsw2_cs = '1' else + rom_d_o when rom_cs = '1' else + (others => 'Z'); + + -- sound control + process (clk_24M, rst_24M) + variable count : unsigned(3 downto 0); + begin + if rst_24M = '1' then + snd_irq <= '0'; + snd_data <= (others => '0'); + elsif rising_edge(clk_24M) then + if snd_cs = '1' then + if cpu_a(3) = '1' then + snd_irq <= cpu_d_o(0); + else + snd_data <= cpu_d_o; + end if; + end if; + end if; + end process; + + -- system timing + process (clk_24M) + variable count : unsigned(3 downto 0); + begin + if rising_edge(clk_24M) then + count := count + 1; + if count(1 downto 0) = "11" then + case count(3 downto 2) is + when "00" => clk_E <= '0'; + when "01" => clk_Q <= '1'; + when "10" => clk_E <= '1'; + when "11" => clk_Q <= '0'; + end case; + end if; + end if; + end process; + + cpu_reset <= rst_24M; + + cpu_inst : mc6809i + port map + ( + D => cpu_d_i, + DOut => cpu_d_o, + ADDR => cpu_a, + RnW => cpu_r_wn, + E => clk_E, + Q => clk_Q, + BS => cpu_bs, + BA => cpu_ba, + nIRQ => not cpu_irq, + nFIRQ => '1', + nNMI => '1', + AVMA => open, + BUSY => open, + LIC => open, + nHALT => '1', + nRESET => not cpu_reset, + nDMABREQ => '1', + RegData => open + ); + +--WRAm_cs + wram_inst : entity work.spram + generic map + ( + widthad_a => 12, + width_a => 8 + ) + port map + ( + address => cpu_a(11 downto 0), + clock => clk_24M, + data => cpu_d_o, + wren => wram_wr, + q => wram_d_o + ); + + -- irq vblank interrupt + process (clk_24M, rst_24M) + begin + if rst_24M = '1' then + cpu_irq <= '0'; + elsif rising_edge(clk_24M) then + vblank_r <= graphics_i.vblank; + if vblank_r = '0' and graphics_i.vblank = '1' then + cpu_irq <= '1'; + elsif cpu_ba = '0' and cpu_bs = '1' then + cpu_irq <= '0'; + end if; + end if; + end process; + + -- scroll register + process (clk_24M, rst_24M) + begin + if rst_24M = '1' then + graphics_o.bit8(0) <= (others => '0'); + elsif rising_edge(clk_24M) then + if scroll_cs and not cpu_r_wn then + graphics_o.bit8(0) <= cpu_d_o; + end if; + end if; + end process; + + cpu_rom_addr <= cpu_a(15 downto 0); + rom_d_o <= cpu_rom_do; + + -- wren_a *MUST* be GND for CYCLONEII_SAFE_WRITE=VERIFIED_SAFE + vram_inst : entity work.dpram + generic map + ( + init_file => "./roms/vram.hex", + widthad_a => 10 + ) + port map + ( + clock_b => clk_24M, + address_b => cpu_a(9 downto 0), + wren_b => vram_wr, + data_b => cpu_d_o, + q_b => vram_d_o, + + clock_a => clk_video, + address_a => tilemap_i(1).map_a(9 downto 0), + wren_a => '0', + data_a => (others => 'X'), + q_a => tilemap_o(1).map_d(7 downto 0) + ); + tilemap_o(1).map_d(tilemap_o(1).map_d'left downto 8) <= (others => 'Z'); + + -- wren_a *MUST* be GND for CYCLONEII_SAFE_WRITE=VERIFIED_SAFE + cram_inst : entity work.dpram + generic map + ( + init_file => "./roms/cram.hex", + widthad_a => 10 + ) + port map + ( + clock_b => clk_24M, + address_b => cpu_a(9 downto 0), + wren_b => cram_wr, + data_b => cpu_d_o, + q_b => cram_d_o, + + clock_a => clk_video, + address_a => tilemap_i(1).attr_a(9 downto 0), + wren_a => '0', + data_a => (others => 'X'), + q_a => tilemap_o(1).attr_d(7 downto 0) + ); + tilemap_o(1).attr_d(tilemap_o(1).attr_d'left downto 8) <= (others => 'Z'); + + tile_rom_addr <= tilemap_i(1).tile_a(12 downto 0); + tilemap_o(1).tile_d(15 downto 0) <= tile_rom_do; + + BLK_SPRITES : block + signal bit0_1 : std_logic_vector(7 downto 0); -- offset 0 + signal bit0_2 : std_logic_vector(7 downto 0); -- offset 0 + signal bit0_3 : std_logic_vector(7 downto 0); -- offset 16 + signal bit0_4 : std_logic_vector(7 downto 0); -- offset 16 + signal bit1_1 : std_logic_vector(7 downto 0); + signal bit1_2 : std_logic_vector(7 downto 0); + signal bit1_3 : std_logic_vector(7 downto 0); + signal bit1_4 : std_logic_vector(7 downto 0); + signal bit2_1 : std_logic_vector(7 downto 0); + signal bit2_2 : std_logic_vector(7 downto 0); + signal bit2_3 : std_logic_vector(7 downto 0); + signal bit2_4 : std_logic_vector(7 downto 0); + + signal sprite_a_00 : std_logic_vector(12 downto 0); + signal sprite_a_16 : std_logic_vector(12 downto 0); + + begin + + -- registers + sprite_reg_o.clk <= clk_24M; + sprite_reg_o.clk_ena <= '1'; + sprite_reg_o.a <= cpu_a(sprite_reg_o.a'range); + sprite_reg_o.d <= cpu_d_o; + sprite_reg_o.wr <= sprite_cs and not cpu_r_wn; + + -- - sprite data consists of: + -- 16 consecutive bytes for the 1st half + -- then the next 16 bytes for the 2nd half + -- - because we need to fetch an entire row at once + -- use dual-port memory to access both halves of each row + + -- generate address for each port + sprite_a_00 <= sprite_i.a(12 downto 5) & '0' & sprite_i.a(3 downto 0); + sprite_a_16 <= sprite_i.a(12 downto 5) & '1' & sprite_i.a(3 downto 0); + + -- sprite rom (bit 0, part 1/2) + ss_9_m5_inst : entity work.dprom_2r + generic map + ( + init_file => "./roms/ss_9_m5.hex", + widthad_a => 13, + widthad_b => 13 + ) + port map + ( + clock => clk_video, + address_a => sprite_a_00, + q_a => bit0_1, + address_b => sprite_a_16, + q_b => bit0_3 + ); + + -- sprite rom (bit 0, part 2/2) + ss_10_m6_inst : entity work.dprom_2r + generic map + ( + init_file => "./roms/ss_10_m6.hex", + widthad_a => 13, + widthad_b => 13 + ) + port map + ( + clock => clk_video, + address_a => sprite_a_00, + q_a => bit0_2, + address_b => sprite_a_16, + q_b => bit0_4 + ); + + sprite_o.d(15 downto 0) <= (bit0_1 & bit0_3) when sprite_i.a(13) = '0' else + (bit0_2 & bit0_4); + + -- sprite rom (bit 1, part 1/2) + ss_11_m3_inst : entity work.dprom_2r + generic map + ( + init_file => "./roms/ss_11_m3.hex", + widthad_a => 13, + widthad_b => 13 + ) + port map + ( + clock => clk_video, + address_a => sprite_a_00, + q_a => bit1_1, + address_b => sprite_a_16, + q_b => bit1_3 + ); + + -- sprite rom (bit 1, part 2/2) + ss_12_m4_inst : entity work.dprom_2r + generic map + ( + init_file => "./roms/ss_12_m4.hex", + widthad_a => 13, + widthad_b => 13 + ) + port map + ( + clock => clk_video, + address_a => sprite_a_00, + q_a => bit1_2, + address_b => sprite_a_16, + q_b => bit1_4 + ); + + sprite_o.d(31 downto 16) <= (bit1_1 & bit1_3) when sprite_i.a(13) = '0' else + (bit1_2 & bit1_4); + + -- sprite rom (bit 2, part 1/2) + ss_13_m1_inst : entity work.dprom_2r + generic map + ( + init_file => "./roms/ss_13_m1.hex", + widthad_a => 13, + widthad_b => 13 + ) + port map + ( + clock => clk_video, + address_a => sprite_a_00, + q_a => bit2_1, + address_b => sprite_a_16, + q_b => bit2_3 + ); + + -- sprite rom (bit 2, part 2/2) + ss_14_m2_inst : entity work.dprom_2r + generic map + ( + init_file => "./roms/ss_14_m2.hex", + widthad_a => 13, + widthad_b => 13 + ) + port map + ( + clock => clk_video, + address_a => sprite_a_00, + q_a => bit2_2, + address_b => sprite_a_16, + q_b => bit2_4 + ); + + sprite_o.d(47 downto 32) <= (bit2_1 & bit2_3) when sprite_i.a(13) = '0' else + (bit2_2 & bit2_4); + + end block BLK_SPRITES; + + -- unused outputs + + graphics_o.bit16(0) <= (others => '0'); + +end SYN; diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform_pkg.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/platform_pkg.vhd similarity index 89% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform_pkg.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/platform_pkg.vhd index 83d03cdc..283ee674 100644 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform_pkg.vhd +++ b/Arcade_MiST/Capcom SonSon Hardware/rtl/platform_pkg.vhd @@ -8,35 +8,24 @@ use work.video_controller_pkg.all; package platform_pkg is - constant PACE_HAS_PLL : boolean := true; - constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_VGA_800x600_60Hz; --40 constant PACE_CLK0_DIVIDE_BY : natural := 27; - constant PACE_CLK0_MULTIPLY_BY : natural := 20; -- 20MHz + constant PACE_CLK0_MULTIPLY_BY : natural := 24; -- 20MHz constant PACE_CLK1_DIVIDE_BY : natural := 27; - constant PACE_CLK1_MULTIPLY_BY : natural := 40; -- 40MHz - constant PACE_VIDEO_H_SCALE : integer := 2; - constant PACE_VIDEO_V_SCALE : integer := 2; - constant PACE_VIDEO_H_SYNC_POLARITY : std_logic := '1'; - constant PACE_VIDEO_V_SYNC_POLARITY : std_logic := '1'; + constant PACE_CLK1_MULTIPLY_BY : natural := 6; -- 40MHz - constant PACE_VIDEO_BORDER_RGB : RGB_t := RGB_BLACK; - constant PACE_VIDEO_NUM_BITMAPS : natural := 0; - constant PACE_VIDEO_NUM_TILEMAPS : natural := 1; - constant PACE_VIDEO_NUM_SPRITES : natural := 24; - constant PACE_VIDEO_H_SIZE : integer := 256; -- 240 - constant PACE_VIDEO_V_SIZE : integer := 256; -- 240 - constant PACE_VIDEO_L_CROP : integer := (256-240)/2; - constant PACE_VIDEO_R_CROP : integer := PACE_VIDEO_L_CROP; - constant PACE_VIDEO_PIPELINE_DELAY : integer := 3; - - constant PACE_INPUTS_NUM_BYTES : integer := 4; - - -- - -- Platform-specific constants (optional) - -- + constant PACE_VIDEO_NUM_BITMAPS : natural := 0; + constant PACE_VIDEO_NUM_TILEMAPS : natural := 1; + constant PACE_VIDEO_NUM_SPRITES : natural := 24; + constant PACE_VIDEO_PIPELINE_DELAY : integer := 3; + + constant PACE_INPUTS_NUM_BYTES : integer := 4; + + -- + -- Platform-specific constants (optional) + -- constant CLK0_FREQ_MHz : natural := 27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY; diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll.qip b/Arcade_MiST/Capcom SonSon Hardware/rtl/pll.qip similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll.qip rename to Arcade_MiST/Capcom SonSon Hardware/rtl/pll.qip diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll.v b/Arcade_MiST/Capcom SonSon Hardware/rtl/pll.v similarity index 84% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll.v rename to Arcade_MiST/Capcom SonSon Hardware/rtl/pll.v index 34b615f3..a1892f9d 100644 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll.v +++ b/Arcade_MiST/Capcom SonSon Hardware/rtl/pll.v @@ -14,11 +14,11 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition // ************************************************************ -//Copyright (C) 1991-2013 Altera Corporation +//Copyright (C) 1991-2014 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing @@ -40,14 +40,12 @@ module pll ( areset, inclk0, c0, - c1, c2, locked); input areset; input inclk0; output c0; - output c1; output c2; output locked; `ifndef ALTERA_RESERVED_QIS @@ -58,24 +56,22 @@ module pll ( // synopsys translate_on `endif - wire [4:0] sub_wire0; - wire sub_wire2; - wire [0:0] sub_wire7 = 1'h0; - wire [2:2] sub_wire4 = sub_wire0[2:2]; - wire [0:0] sub_wire3 = sub_wire0[0:0]; - wire [1:1] sub_wire1 = sub_wire0[1:1]; - wire c1 = sub_wire1; - wire locked = sub_wire2; - wire c0 = sub_wire3; - wire c2 = sub_wire4; - wire sub_wire5 = inclk0; - wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire6 = 1'h0; + wire locked = sub_wire0; + wire [2:2] sub_wire3 = sub_wire1[2:2]; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire c2 = sub_wire3; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; altpll altpll_component ( .areset (areset), - .inclk (sub_wire6), - .clk (sub_wire0), - .locked (sub_wire2), + .inclk (sub_wire5), + .locked (sub_wire0), + .clk (sub_wire1), .activeclock (), .clkbad (), .clkena ({6{1'b1}}), @@ -111,17 +107,13 @@ module pll ( .vcounderrange ()); defparam altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 27, + altpll_component.clk0_divide_by = 9, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 20, + altpll_component.clk0_multiply_by = 8, altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 27, - altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 40, - altpll_component.clk1_phase_shift = "0", - altpll_component.clk2_divide_by = 40, + altpll_component.clk2_divide_by = 3, altpll_component.clk2_duty_cycle = 50, - altpll_component.clk2_multiply_by = 83, + altpll_component.clk2_multiply_by = 8, altpll_component.clk2_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, @@ -156,7 +148,7 @@ module pll ( altpll_component.port_scanread = "PORT_UNUSED", altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", altpll_component.port_clk2 = "PORT_USED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", @@ -197,14 +189,11 @@ endmodule // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "40" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "56.025002" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "72.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -225,33 +214,25 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "20" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40" // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "83" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "56.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "72.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" @@ -275,32 +256,25 @@ endmodule // Retrieval info: PRIVATE: SPREAD_USE STRING "0" // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: USE_CLK1 STRING "1" // Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" -// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40" -// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "40" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "3" // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "83" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8" // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" @@ -334,7 +308,7 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" @@ -354,7 +328,6 @@ endmodule // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" @@ -362,7 +335,6 @@ endmodule // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/cram.hex b/Arcade_MiST/Capcom SonSon Hardware/rtl/roms/cram.hex similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/cram.hex rename to Arcade_MiST/Capcom SonSon Hardware/rtl/roms/cram.hex diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_10_m6.hex b/Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_10_m6.hex similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_10_m6.hex rename to Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_10_m6.hex diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_11_m3.hex b/Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_11_m3.hex similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_11_m3.hex rename to Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_11_m3.hex diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_12_m4.hex b/Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_12_m4.hex similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_12_m4.hex rename to Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_12_m4.hex diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_13_m1.hex b/Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_13_m1.hex similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_13_m1.hex rename to Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_13_m1.hex diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_14_m2.hex b/Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_14_m2.hex similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_14_m2.hex rename to Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_14_m2.hex diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_9_m5.hex b/Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_9_m5.hex similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_9_m5.hex rename to Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_9_m5.hex diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/vram.hex b/Arcade_MiST/Capcom SonSon Hardware/rtl/roms/vram.hex similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/vram.hex rename to Arcade_MiST/Capcom SonSon Hardware/rtl/roms/vram.hex diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sdram.sv b/Arcade_MiST/Capcom SonSon Hardware/rtl/sdram.sv similarity index 91% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sdram.sv rename to Arcade_MiST/Capcom SonSon Hardware/rtl/sdram.sv index bc78584d..d1dd1d9d 100644 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sdram.sv +++ b/Arcade_MiST/Capcom SonSon Hardware/rtl/sdram.sv @@ -46,8 +46,10 @@ module sdram ( input [15:0] port1_d, output [15:0] port1_q, - input [15:1] cpu1_addr, + input [16:1] cpu1_addr, output reg [15:0] cpu1_q, + input [16:1] tile_addr, + output reg [15:0] tile_q, input port2_req, output reg port2_ack, @@ -61,6 +63,8 @@ module sdram ( output reg [15:0] snd_q ); +parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate + localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved @@ -70,8 +74,8 @@ localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single acc localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; -// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz -localparam RFRSH_CYCLES = 10'd842; +// 64ms/8192 rows = 7.8us +localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10; // --------------------------------------------------------------------- // ------------------------ cycle state machine ------------------------ @@ -147,16 +151,20 @@ assign SDRAM_nWE = sd_cmd[0]; reg [24:1] addr_latch[2]; reg [24:1] addr_latch_next[2]; -reg [15:1] addr_last[2]; -reg [15:1] addr_last2[2]; +reg [16:1] addr_last[2]; +reg [16:1] addr_last2[2]; reg [15:0] din_latch[2]; reg [1:0] oe_latch; reg [1:0] we_latch; reg [1:0] ds[2]; +reg port1_state; +reg port2_state; + localparam PORT_NONE = 2'd0; localparam PORT_CPU1 = 2'd1; -localparam PORT_REQ = 2'd2; +localparam PORT_TILE = 2'd2; +localparam PORT_REQ = 2'd3; localparam PORT_SND = 2'd1; @@ -172,12 +180,15 @@ always @(*) begin if (refresh) begin next_port[0] = PORT_NONE; addr_latch_next[0] = addr_latch[0]; - end else if (port1_req ^ port1_ack) begin + end else if (port1_req ^ port1_state) begin next_port[0] = PORT_REQ; addr_latch_next[0] = { 1'b0, port1_a }; end else if (cpu1_addr != addr_last[PORT_CPU1]) begin next_port[0] = PORT_CPU1; - addr_latch_next[0] = { 9'd0, cpu1_addr }; + addr_latch_next[0] = { 8'd0, cpu1_addr }; + end else if (tile_addr != addr_last[PORT_TILE]) begin + next_port[0] = PORT_TILE; + addr_latch_next[0] = { 8'd0, tile_addr }; end else begin next_port[0] = PORT_NONE; addr_latch_next[0] = addr_latch[0]; @@ -186,7 +197,7 @@ end // PORT2: bank 2,3 always @(*) begin - if (port2_req ^ port2_ack) begin + if (port2_req ^ port2_state) begin next_port[1] = PORT_REQ; addr_latch_next[1] = { 1'b1, port2_a }; end else if (snd_addr != addr_last2[PORT_SND]) begin @@ -238,11 +249,12 @@ always @(posedge clk) begin sd_cmd <= CMD_ACTIVE; SDRAM_A <= addr_latch_next[0][22:10]; SDRAM_BA <= addr_latch_next[0][24:23]; - addr_last[next_port[0]] <= addr_latch_next[0][15:1]; + addr_last[next_port[0]] <= addr_latch_next[0][16:1]; if (next_port[0] == PORT_REQ) begin { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we }; ds[0] <= port1_ds; din_latch[0] <= port1_d; + port1_state <= port1_req; end else begin { oe_latch[0], we_latch[0] } <= 2'b10; ds[0] <= 2'b11; @@ -266,6 +278,7 @@ always @(posedge clk) begin { oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we }; ds[1] <= port2_ds; din_latch[1] <= port2_d; + port2_state <= port1_req; end else begin { oe_latch[1], we_latch[1] } <= 2'b10; ds[1] <= 2'b11; @@ -307,6 +320,7 @@ always @(posedge clk) begin case(port[0]) PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end PORT_CPU1: begin cpu1_q <= sd_din; end + PORT_TILE: begin tile_q <= sd_din; end default: ; endcase; end diff --git a/Arcade_MiST/Capcom SonSon Hardware/rtl/sonson_soundboard.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/sonson_soundboard.vhd new file mode 100644 index 00000000..7a3e017f --- /dev/null +++ b/Arcade_MiST/Capcom SonSon Hardware/rtl/sonson_soundboard.vhd @@ -0,0 +1,262 @@ +library ieee; + +use work.pace_pkg.all; + +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; +library work; + +entity sonson_soundboard is +port( + clkrst_i : in from_CLKRST_t; + sound_irq : in std_logic; + sound_data : in std_logic_vector(7 downto 0); + vblank : in std_logic; + audio_out_l : out std_logic_vector(9 downto 0); + audio_out_r : out std_logic_vector(9 downto 0); + snd_rom_addr : out std_logic_vector(12 downto 0); + snd_rom_do : in std_logic_vector(7 downto 0) + ); + +end sonson_soundboard; + +architecture SYN of sonson_soundboard is + + component YM2149 + port ( + CLK : in std_logic; + CE : in std_logic; + RESET : in std_logic; + A8 : in std_logic := '1'; + A9_L : in std_logic := '0'; + BDIR : in std_logic; -- Bus Direction (0 - read , 1 - write) + BC : in std_logic; -- Bus control + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + CHANNEL_A : out std_logic_vector(7 downto 0); + CHANNEL_B : out std_logic_vector(7 downto 0); + CHANNEL_C : out std_logic_vector(7 downto 0); + + SEL : in std_logic; + MODE : in std_logic; + + ACTIVE : out std_logic_vector(5 downto 0); + + IOA_in : in std_logic_vector(7 downto 0); + IOA_out : out std_logic_vector(7 downto 0); + + IOB_in : in std_logic_vector(7 downto 0); + IOB_out : out std_logic_vector(7 downto 0) + ); + end component; + + COMPONENT mc6809i + GENERIC ( ILLEGAL_INSTRUCTIONS : STRING := "GHOST" ); + PORT + ( + D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DOut : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + RnW : OUT STD_LOGIC; + E : IN STD_LOGIC; + Q : IN STD_LOGIC; + BS : OUT STD_LOGIC; + BA : OUT STD_LOGIC; + nIRQ : IN STD_LOGIC; + nFIRQ : IN STD_LOGIC; + nNMI : IN STD_LOGIC; + AVMA : OUT STD_LOGIC; + BUSY : OUT STD_LOGIC; + LIC : OUT STD_LOGIC; + nHALT : IN STD_LOGIC; + nRESET : IN STD_LOGIC; + nDMABREQ : IN STD_LOGIC; + RegData : OUT STD_LOGIC_VECTOR(111 DOWNTO 0) + ); +END COMPONENT; + + alias clk : std_logic is clkrst_i.clk(0); + alias reset : std_logic is clkrst_i.rst(0); + + signal clk_E : std_logic; + signal clk_Q : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_rw : std_logic; + signal cpu_irq : std_logic; + signal cpu_ba : std_logic; + signal cpu_bs : std_logic; + + signal wram_cs : std_logic; + signal wram_we : std_logic; + signal wram_do : std_logic_vector( 7 downto 0); + + signal rom_cs : std_logic; + signal snd_rd : std_logic; + + signal clk_en_snd : std_logic; -- 1.5 MHz + signal ay1_cs : std_logic; + signal ay1_chan_a : std_logic_vector(7 downto 0); + signal ay1_chan_b : std_logic_vector(7 downto 0); + signal ay1_chan_c : std_logic_vector(7 downto 0); + signal ay1_do : std_logic_vector(7 downto 0); + signal ay1_port_b_do : std_logic_vector(7 downto 0); + + signal ay2_cs : std_logic; + signal ay2_chan_a : std_logic_vector(7 downto 0); + signal ay2_chan_b : std_logic_vector(7 downto 0); + signal ay2_chan_c : std_logic_vector(7 downto 0); + signal ay2_do : std_logic_vector(7 downto 0); + + signal vblank_r : std_logic; + +begin + + -- cs + snd_rd <= '1' when cpu_addr(15 downto 13) = "101" else '0'; -- a000 + wram_cs <= '1' when cpu_addr(15 downto 13) = "000" else '0'; -- 0000-07ff RAM + rom_cs <= '1' when cpu_addr(15 downto 13) = "111" else '0'; -- e000-ffff ROM + ay1_cs <= '1' when cpu_addr(15 downto 13) = "001" else '0'; -- 2000 + ay2_cs <= '1' when cpu_addr(15 downto 13) = "010" else '0'; -- 4000 + + -- write enables + wram_we <= '1' when cpu_rw = '0' and wram_cs = '1' else '0'; + + -- mux cpu in data between roms/io/wram + cpu_di <= wram_do when wram_cs = '1' else + sound_data when snd_rd = '1' else + ay1_do when ay1_cs = '1' else + ay2_do when ay2_cs = '1' else + snd_rom_do when rom_cs = '1' else X"FF"; + + process (clk) + variable count : unsigned(3 downto 0); + begin + if rising_edge(clk) then + count := count + 1; + if count(1 downto 0) = "11" then + case count(3 downto 2) is + when "00" => clk_E <= '0'; + when "01" => clk_Q <= '1'; + when "10" => clk_E <= '1'; + when "11" => clk_Q <= '0'; + end case; + end if; + + clk_en_snd <= '0'; + if count = "0000" then + clk_en_snd <= '1'; + end if; + end if; + end process; + + process (clk, reset) + begin + if reset = '1' then + cpu_irq <= '0'; + elsif rising_edge(clk) then + vblank_r <= vblank; + if vblank_r = '0' and vblank = '1' then + cpu_irq <= '1'; + elsif cpu_ba = '0' and cpu_bs = '1' then + cpu_irq <= '0'; + end if; + end if; + end process; + + cpu_inst : mc6809i + port map + ( + D => cpu_di, + DOut => cpu_do, + ADDR => cpu_addr, + RnW => cpu_rw, + E => clk_E, + Q => clk_Q, + BS => cpu_bs, + BA => cpu_ba, + nIRQ => not cpu_irq, + nFIRQ => sound_irq, + nNMI => '1', + AVMA => open, + BUSY => open, + LIC => open, + nHALT => '1', + nRESET => not reset, + nDMABREQ => '1', + RegData => open + ); + + snd_rom_addr <= cpu_addr(12 downto 0); + + cpu_ram : entity work.spram + generic map( widthad_a => 11) + port map( + clock => clk, + wren => wram_we, + address => cpu_addr(10 downto 0), + data => cpu_do, + q => wram_do + ); + + ay83910_inst1: YM2149 + port map ( + CLK => clk, + CE => clk_en_snd, + RESET => reset, + A8 => '1', + A9_L => not ay1_cs, + BDIR => not cpu_rw, + BC => not cpu_addr(0) or cpu_rw, + DI => cpu_do, + DO => ay1_do, + CHANNEL_A => ay1_chan_a, + CHANNEL_B => ay1_chan_b, + CHANNEL_C => ay1_chan_c, + + SEL => '0', + MODE => '1', + + ACTIVE => open, + + IOA_in => (others => '0'), + IOA_out => open, + + IOB_in => (others => '0'), + IOB_out => open + ); + + audio_out_l <= "0000000000" + ay1_chan_a + ay1_chan_b + ay1_chan_c; + + ay83910_inst2: YM2149 + port map ( + CLK => clk, + CE => clk_en_snd, + RESET => reset, + A8 => '1', + A9_L => not ay2_cs, + BDIR => not cpu_rw, + BC => not cpu_addr(0) or cpu_rw, + DI => cpu_do, + DO => ay2_do, + CHANNEL_A => ay2_chan_a, + CHANNEL_B => ay2_chan_b, + CHANNEL_C => ay2_chan_c, + + SEL => '0', + MODE => '1', + + ACTIVE => open, + + IOA_in => (others => '0'), + IOA_out => open, + + IOB_in => (others => '0'), + IOB_out => open + ); + + audio_out_r <= "0000000000" + ay2_chan_a + ay2_chan_b + ay2_chan_c; + +end SYN; \ No newline at end of file diff --git a/Arcade_MiST/Capcom SonSon Hardware/rtl/sonson_video_controller.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/sonson_video_controller.vhd new file mode 100644 index 00000000..9c61afeb --- /dev/null +++ b/Arcade_MiST/Capcom SonSon Hardware/rtl/sonson_video_controller.vhd @@ -0,0 +1,129 @@ +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.video_controller_pkg.all; + +entity sonson_video_controller is + port + ( + -- clocking etc + video_i : in from_VIDEO_t; + + -- video input data + rgb_i : in RGB_t; + + -- control signals (out) + video_ctl_o : out from_VIDEO_CTL_t; + + -- video output control & data + video_o : out to_VIDEO_t + ); +end sonson_video_controller; + +architecture SYN of sonson_video_controller is + + alias clk : std_logic is video_i.clk; + alias clk_ena : std_logic is video_i.clk_ena; + alias reset : std_logic is video_i.reset; + + signal hcnt : unsigned(8 downto 0); + signal vcnt : unsigned(8 downto 0); + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; -- hblank mux + signal hblank1 : std_logic; -- normal hblank + signal hblank2 : std_logic; -- shifted hblank for some games + signal vblank : std_logic; +begin + + ------------------- + -- Video scanner -- + ------------------- + -- Note: this is not what the hardware originally has. + -- hcnt [x180..x1FF-x000..x0FF] => 128+256 = 384 pixels, 384/6Mhz => 1 line is 64us (15.6KHz) + -- vcnt [x1FA..x1FF-x000..x0FF] => 6+256 = 262 lines, 1 frame is 262 x 64us = 16.76ms (59.6Hz) + + process (reset, clk, clk_ena) + begin + if reset='1' then + hcnt <= (others=>'0'); + vcnt <= '1'&X"FC"; + elsif rising_edge(clk) and clk_ena = '1'then + hcnt <= hcnt + 1; + if hcnt = '0'&x"FF" then + hcnt <= '1'&x"80"; + vcnt <= vcnt + 1; + if vcnt = '0'&x"FF" then + vcnt <= '1'&x"FA"; + end if; + end if; + end if; + end process; + + process (reset, clk, clk_ena) + begin + if reset = '1' then + hsync <= '0'; + vsync <= '0'; + hblank <= '1'; + vblank <= '1'; + elsif rising_edge(clk) and clk_ena = '1' then + -- display blank + if hcnt = '0'&x"0F" then + hblank <= '0'; + if vcnt = '0'&x"00" then + vblank <= '0'; + end if; + end if; + if hcnt = '0'&x"FF" then + hblank <= '1'; + if vcnt = '0'&x"FF" then + vblank <= '1'; + end if; + end if; + + -- display sync + if hcnt = '1'&x"A8" then + hsync <= '1'; + if vcnt = '1'&x"FC" then + vsync <= '1'; + end if; + end if; + if hcnt = '1'&x"DF" then + hsync <= '0'; + if vcnt = '1'&x"FE" then + vsync <= '0'; + end if; + end if; + + -- registered rgb output + if hblank = '1' or vblank = '1' then + video_o.rgb <= RGB_BLACK; + else + video_o.rgb <= rgb_i; + end if; + + end if; + end process; + + video_o.hsync <= hsync; + video_o.vsync <= vsync; + video_o.hblank <= hblank; + video_o.vblank <= vblank; + video_ctl_o.stb <= '1'; + video_ctl_o.x <= "00"&std_logic_vector(hcnt); + video_ctl_o.y <= "00"&std_logic_vector(vcnt); + -- blank signal goes to tilemap/spritectl + video_ctl_o.hblank <= hblank; + video_ctl_o.vblank <= vblank; + + -- pass-through for tile/bitmap & sprite controllers + video_ctl_o.clk <= clk; + video_ctl_o.clk_ena <= clk_ena; + + -- for video DACs and TFT output + video_o.clk <= clk; + +end SYN; diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sound.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/sound.vhd similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sound.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/sound.vhd diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spram.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/spram.vhd similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spram.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/spram.vhd diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_array.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/sprite_array.vhd similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_array.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/sprite_array.vhd index 880f09f2..dda56e48 100644 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_array.vhd +++ b/Arcade_MiST/Capcom SonSon Hardware/rtl/sprite_array.vhd @@ -73,12 +73,12 @@ begin i := 0; elsif rising_edge(clk) and clk_ena = '1' then ld_r <= ld_r(ld_r'left-1 downto 0) & ld_r(ld_r'left); + row_a <= ctl_o(i).a; if i = N_SPRITES-1 then i := 0; else i := i + 1; end if; - row_a <= ctl_o(i).a; end if; end process; diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_pkg.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/sprite_pkg.vhd similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_pkg.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/sprite_pkg.vhd diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_pkg_body.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/sprite_pkg_body.vhd similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_pkg_body.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/sprite_pkg_body.vhd diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spritectl.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/spritectl.vhd similarity index 79% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spritectl.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/spritectl.vhd index d4758aa3..b8fbf40d 100644 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spritectl.vhd +++ b/Arcade_MiST/Capcom SonSon Hardware/rtl/spritectl.vhd @@ -47,10 +47,9 @@ architecture SYN of spritectl is begin - -- handle xflip - flipData(47 downto 32) <= flip_row (ctl_i.d(47 downto 32), reg_i.xflip); - flipData(31 downto 16) <= flip_row (ctl_i.d(31 downto 16), reg_i.xflip); - flipData(15 downto 0) <= flip_row (ctl_i.d(15 downto 0), reg_i.xflip); + flipData(47 downto 32) <= ctl_i.d(47 downto 32); + flipData(31 downto 16) <= ctl_i.d(31 downto 16); + flipData(15 downto 0) <= ctl_i.d(15 downto 0); process (clk) @@ -61,10 +60,7 @@ begin variable yMat : boolean; -- raster is between first and last line of sprite variable xMat : boolean; -- raster in between left edge and end of line - -- the width of rowCount determines the scanline multipler - -- - eg. (4 downto 0) is 1:1 - -- (5 downto 0) is 2:1 (scan-doubling) - variable rowCount : std_logic_vector(3+PACE_VIDEO_V_SCALE downto 0); + variable rowCount : std_logic_vector(4 downto 0); variable clut_i : integer range 0 to 31; variable clut_entry : sprite_clut_entry_t; @@ -77,7 +73,7 @@ begin if rising_edge(clk) then if clk_ena = '1' then - x := unsigned(reg_i.x); + x := unsigned(reg_i.x) + 8; y := unsigned(reg_i.y); if video_ctl.hblank = '1' then @@ -92,7 +88,7 @@ begin -- start counting sprite row rowCount := (others => '0'); yMat := true; - elsif rowCount(rowCount'left downto rowCount'left-4) = "10000" then + elsif rowCount(4 downto 0) = "10000" then yMat := false; end if; @@ -103,21 +99,28 @@ begin rowStore := (others => '0'); end if; end if; - + elsif video_ctl.stb = '1' then - + if unsigned(video_ctl.x) = x then -- count up at left edge of sprite rowCount := std_logic_vector(unsigned(rowCount) + 1); xMat := true; end if; - + if xMat then -- shift in next pixel - pel := rowStore(32) & rowStore(16) & rowStore(0); - rowStore(47 downto 32) := '0' & rowStore(47 downto 33); - rowStore(31 downto 16) := '0' & rowStore(31 downto 17); - rowStore(15 downto 0) := '0' & rowStore(15 downto 1); + if reg_i.xflip = '1' then + pel := rowStore(47) & rowStore(31) & rowStore(15); + rowStore(47 downto 32) := rowStore(46 downto 32) & '0'; + rowStore(31 downto 16) := rowStore(30 downto 16) & '0'; + rowStore(15 downto 0) := rowStore(14 downto 0) & '0'; + else + pel := rowStore(32) & rowStore(16) & rowStore(0); + rowStore(47 downto 32) := '0' & rowStore(47 downto 33); + rowStore(31 downto 16) := '0' & rowStore(31 downto 17); + rowStore(15 downto 0) := '0' & rowStore(15 downto 1); + end if; end if; end if; @@ -149,11 +152,11 @@ begin -- use dual-port memory to access both halves of each row ctl_o.a(4) <= '0'; -- used for 1st/2nd port of dual-port memory if reg_i.yflip = '1' then - ctl_o.a(3 downto 0) <= not rowCount(rowCount'left-1 downto rowCount'left-4); + ctl_o.a(3 downto 0) <= not rowCount(3 downto 0); else - ctl_o.a(3 downto 0) <= rowCount(rowCount'left-1 downto rowCount'left-4); + ctl_o.a(3 downto 0) <= rowCount(3 downto 0); end if; - + end if; -- rising_edge(clk) end process; diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spritereg.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/spritereg.vhd similarity index 98% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spritereg.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/spritereg.vhd index 0635ea3e..d1c2d6fd 100644 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spritereg.vhd +++ b/Arcade_MiST/Capcom SonSon Hardware/rtl/spritereg.vhd @@ -26,7 +26,7 @@ architecture SYN of sptReg is begin - process (clk) + process (clk, reg_i) variable i : integer range 0 to 31; begin -- sprite registers $2020-$207F, 4 bytes per sprite diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprom.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/sprom.vhd similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprom.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/sprom.vhd diff --git a/Arcade_MiST/Capcom SonSon Hardware/rtl/target_top.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/target_top.vhd new file mode 100644 index 00000000..142ab98f --- /dev/null +++ b/Arcade_MiST/Capcom SonSon Hardware/rtl/target_top.vhd @@ -0,0 +1,109 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; +use work.platform_pkg.all; + +entity target_top is + port( + clk_sys : in std_logic; + clk_vid_en : in std_logic; + reset_in : in std_logic; + snd_l : out std_logic_vector(9 downto 0); + snd_r : out std_logic_vector(9 downto 0); + vid_hs : out std_logic; + vid_vs : out std_logic; + vid_hb : out std_logic; + vid_vb : out std_logic; + vid_r : out std_logic_vector(3 downto 0); + vid_g : out std_logic_vector(3 downto 0); + vid_b : out std_logic_vector(3 downto 0); + inputs_p1 : in std_logic_vector(7 downto 0); + inputs_p2 : in std_logic_vector(7 downto 0); + inputs_sys : in std_logic_vector(7 downto 0); + inputs_dip1 : in std_logic_vector(7 downto 0); + inputs_dip2 : in std_logic_vector(7 downto 0); + cpu_rom_addr : out std_logic_vector(15 downto 0); + cpu_rom_do : in std_logic_vector(7 downto 0); + tile_rom_addr : out std_logic_vector(12 downto 0); + tile_rom_do : in std_logic_vector(15 downto 0); + snd_rom_addr : out std_logic_vector(12 downto 0); + snd_rom_do : in std_logic_vector(7 downto 0) + ); + +end target_top; + +architecture SYN of target_top is + + signal clkrst_i : from_CLKRST_t; + signal video_i : from_VIDEO_t; + signal video_o : to_VIDEO_t; + signal audio_i : from_AUDIO_t; + signal audio_o : to_AUDIO_t; + signal platform_i : from_PLATFORM_IO_t; + signal platform_o : to_PLATFORM_IO_t; + + +begin + +clkrst_i.clk(0) <=clk_sys; +clkrst_i.clk(1) <= clk_sys; +clkrst_i.arst <= reset_in; +clkrst_i.arst_n <= not clkrst_i.arst; + +video_i.clk <= clk_sys; +video_i.clk_ena <= clk_vid_en; +video_i.reset <= reset_in; + + GEN_RESETS : for i in 0 to 3 generate + + process (clkrst_i) + variable rst_r : std_logic_vector(2 downto 0) := (others => '0'); + begin + if clkrst_i.arst = '1' then + rst_r := (others => '1'); + elsif rising_edge(clkrst_i.clk(i)) then + rst_r := rst_r(rst_r'left-1 downto 0) & '0'; + end if; + clkrst_i.rst(i) <= rst_r(rst_r'left); + end process; + + end generate GEN_RESETS; + +vid_r <= video_o.rgb.r(9 downto 6); +vid_g <= video_o.rgb.g(9 downto 6); +vid_b <= video_o.rgb.b(9 downto 6); +vid_hs <= video_o.hsync; +vid_vs <= video_o.vsync; +vid_hb <= video_o.hblank; +vid_vb <= video_o.vblank; +snd_l <= audio_o.ldata(9 downto 0); +snd_r <= audio_o.rdata(9 downto 0); + +pace_inst : entity work.pace + port map( + clkrst_i => clkrst_i, + inputs_p1 => inputs_p1, + inputs_p2 => inputs_p2, + inputs_sys => inputs_sys, + inputs_dip1 => inputs_dip1, + inputs_dip2 => inputs_dip2, + video_i => video_i, + video_o => video_o, + audio_i => audio_i, + audio_o => audio_o, + platform_i => platform_i, + platform_o => platform_o, + cpu_rom_addr => cpu_rom_addr, + cpu_rom_do => cpu_rom_do, + tile_rom_addr => tile_rom_addr, + tile_rom_do => tile_rom_do, + snd_rom_addr => snd_rom_addr, + snd_rom_do => snd_rom_do + ); + +end SYN; diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/tilemapctl.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/tilemapctl.vhd similarity index 87% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/tilemapctl.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/tilemapctl.vhd index 1b541124..b4439f45 100644 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/tilemapctl.vhd +++ b/Arcade_MiST/Capcom SonSon Hardware/rtl/tilemapctl.vhd @@ -55,34 +55,35 @@ begin if rising_edge(clk) then if clk_ena = '1' then - -- video is clipped left and right (only 224 wide) + -- don't scroll the fist 5 lines if unsigned(y) < 40 then x_adj := unsigned(x); else x_adj := unsigned(x) + unsigned(scroll); end if; - + -- 1st stage of pipeline -- - read tile from tilemap -- - read attribute data if stb = '1' then - ctl_o.map_a(4 downto 0) <= std_logic_vector(x_adj(7 downto 3)); - ctl_o.attr_a(4 downto 0) <= std_logic_vector(x_adj(7 downto 3)); + if x_adj(2 downto 0) = "000" then + ctl_o.map_a(4 downto 0) <= std_logic_vector(x_adj(7 downto 3)); + ctl_o.attr_a(4 downto 0) <= std_logic_vector(x_adj(7 downto 3)); + end if; end if; - + -- 2nd stage of pipeline -- - read tile data from tile ROM if stb = '1' then - if x_adj(2 downto 0) = "001" then - attr_d_r := ctl_i.attr_d(attr_d_r'range); - --map_d_r := ctl_i.map_d(map_d_r'range); + if x_adj(2 downto 0) = "010" then + ctl_o.tile_a(12 downto 11) <= ctl_i.attr_d(1 downto 0); + ctl_o.tile_a(10 downto 3) <= ctl_i.map_d(7 downto 0); end if; end if; - ctl_o.tile_a(12 downto 11) <= attr_d_r(1 downto 0); - ctl_o.tile_a(10 downto 3) <= ctl_i.map_d(7 downto 0); if stb = '1' then - if x_adj(2 downto 0) = "010" then + if x_adj(2 downto 0) = "111" then + attr_d_r := ctl_i.attr_d(attr_d_r'range); tile_d_r := ctl_i.tile_d(tile_d_r'range); else tile_d_r(15 downto 8) := tile_d_r(14 downto 8) & '0'; diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/tilemapctl_e.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/tilemapctl_e.vhd similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/tilemapctl_e.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/tilemapctl_e.vhd diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller_pkg.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/video_controller_pkg.vhd similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller_pkg.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/video_controller_pkg.vhd diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller_pkg_body.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/video_controller_pkg_body.vhd similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller_pkg_body.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/video_controller_pkg_body.vhd diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_mixer.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/video_mixer.vhd similarity index 100% rename from Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_mixer.vhd rename to Arcade_MiST/Capcom SonSon Hardware/rtl/video_mixer.vhd diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/cpu09s.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/cpu09s.vhd deleted file mode 100644 index e404bbdf..00000000 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/cpu09s.vhd +++ /dev/null @@ -1,5679 +0,0 @@ ---===========================================================================-- --- -- --- Synthesizable 6809 instruction compatible VHDL CPU core -- --- -- ---===========================================================================-- --- --- File name : cpu09.vhd --- --- Entity name : cpu09 --- --- Purpose : 6809 instruction compatible CPU core written in VHDL --- Not cycle compatible with the original 6809 CPU --- --- Dependencies : ieee.std_logic_1164 --- ieee.std_logic_unsigned --- --- Author : John E. Kent --- --- Email : dilbert57@opencores.org --- --- Web : http://opencores.org/project,system09 --- --- --- Copyright (C) 2003 - 2010 John Kent --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- ---===========================================================================-- --- -- --- Revision History -- --- -- ---===========================================================================-- --- --- Version 0.1 - 26 June 2003 - John Kent --- Added extra level in state stack --- fixed some calls to the extended addressing state --- --- Version 0.2 - 5 Sept 2003 - John Kent --- Fixed 16 bit indexed offset (was doing read rather than fetch) --- Added/Fixed STY and STS instructions. --- ORCC_STATE ANDed CC state rather than ORed it - Now fixed --- CMPX Loaded ACCA and ACCB - Now fixed --- --- Version 1.0 - 6 Sep 2003 - John Kent --- Initial release to Open Cores --- reversed clock edge --- --- Version 1.1 - 29 November 2003 John kent --- ACCA and ACCB indexed offsets are 2's complement. --- ALU Right Mux now sign extends ACCA & ACCB offsets --- Absolute Indirect addressing performed a read on the --- second byte of the address rather than a fetch --- so it formed an incorrect address. Now fixed. --- --- Version 1.2 - 29 November 2003 John Kent --- LEAX and LEAY affect the Z bit only --- LEAS and LEAU do not affect any condition codes --- added an extra ALU control for LEA. --- --- Version 1.3 - 12 December 2003 John Kent --- CWAI did not work, was missed a PUSH_ST on calling --- the ANDCC_STATE. Thanks go to Ghassan Kraidy for --- finding this fault. --- --- Version 1.4 - 12 December 2003 John Kent --- Missing cc_ctrl assignment in otherwise case of --- lea_state resulted in cc_ctrl being latched in --- that state. --- The otherwise statement should never be reached, --- and has been fixed simply to resolve synthesis warnings. --- --- Version 1.5 - 17 january 2004 John kent --- The clear instruction used "alu_ld8" to control the ALU --- rather than "alu_clr". This mean the Carry was not being --- cleared correctly. --- --- Version 1.6 - 24 January 2004 John Kent --- Fixed problems in PSHU instruction --- --- Version 1.7 - 25 January 2004 John Kent --- removed redundant "alu_inx" and "alu_dex' --- Removed "test_alu" and "test_cc" --- STD instruction did not set condition codes --- JMP direct was not decoded properly --- CLR direct performed an unwanted read cycle --- Bogus "latch_md" in Page2 indexed addressing --- --- Version 1.8 - 27 January 2004 John Kent --- CWAI in decode1_state should increment the PC. --- ABX is supposed to be an unsigned addition. --- Added extra ALU function --- ASR8 slightly changed in the ALU. --- --- Version 1.9 - 20 August 2005 --- LSR8 is now handled in ASR8 and ROR8 case in the ALU, --- rather than LSR16. There was a problem with single --- operand instructions using the MD register which is --- sign extended on the first 8 bit fetch. --- --- Version 1.10 - 13 September 2005 --- TFR & EXG instructions did not work for the Condition Code Register --- An extra case has been added to the ALU for the alu_tfr control --- to assign the left ALU input (alu_left) to the condition code --- outputs (cc_out). --- --- Version 1.11 - 16 September 2005 --- JSR ,X should not predecrement S before calculating the jump address. --- The reason is that JSR [0,S] needs S to point to the top of the stack --- to fetch a valid vector address. The solution is to have the addressing --- mode microcode called before decrementing S and then decrementing S in --- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than --- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are --- pushed on the stack. This adds one extra bus cycle, but resolves the --- addressing conflict. I've also removed the pre-decement S in --- JSR EXTENDED as it also calls JSR_STATE. --- --- Version 1.12 - 6th June 2006 --- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR --- This is different to the 6800. CLR should reset the V bit. --- --- Version 1.13 - 7th July 2006 --- Disable NMI on reset until S Stack pointer has been loaded. --- Added nmi_enable signal in sp_reg process and nmi_handler process. --- --- Version 1.14 - 11th July 2006 --- 1. Added new state to RTI called rti_entire_state. --- This state tests the CC register after it has been loaded --- from the stack. Previously the current CC was tested which --- was incorrect. The Entire Flag should be set before the --- interrupt stacks the CC. --- 2. On bogus Interrupts, int_cc_state went to rti_state, --- which was an enumerated state, but not defined anywhere. --- rti_state has been changed to rti_cc_state so that bogus interrupt --- will perform an RTI after entering that state. --- 3. Sync should generate an interrupt if the interrupt masks --- are cleared. If the interrupt masks are set, then an interrupt --- will cause the the PC to advance to the next instruction. --- Note that I don't wait for an interrupt to be asserted for --- three clock cycles. --- 4. Added new ALU control state "alu_mul". "alu_mul" is used in --- the Multiply instruction replacing "alu_add16". This is similar --- to "alu_add16" except it sets the Carry bit to B7 of the result --- in ACCB, sets the Zero bit if the 16 bit result is zero, but --- does not affect The Half carry (H), Negative (N) or Overflow (V) --- flags. The logic was re-arranged so that it adds md or zero so --- that the Carry condition code is set on zero multiplicands. --- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N) --- and Zero Flags. It will also affect the Overflow (V) flag although --- the operation is undefined. It's anyones guess what DAA does to V. --- --- Version 1.15 - 25th Feb 2007 - John Kent --- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then" --- Changed sensitivity lists. --- --- Version 1.16 - 5th February 2008 - John Kent --- FIRQ interrupts should take priority over IRQ Interrupts. --- This presumably means they should be tested for before IRQ --- when they happen concurrently. --- --- Version 1.17 - 18th February 2008 - John Kent --- NMI in CWAI should mask IRQ and FIRQ interrupts --- --- Version 1.18 - 21st February 2008 - John Kent --- Removed default register settings in each case statement --- and placed them at the beginning of the state sequencer. --- Modified the SYNC instruction so that the interrupt vector(iv) --- is not set unless an unmasked FIRQ or IRQ is received. --- --- Version 1.19 - 25th February 2008 - John Kent --- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE --- Enumerated separate states for MASKI and MASKIF states --- Removed code on BSR/JSR in fetch cycle --- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity cpu09 is - generic ( - CLK_POL : std_logic := '0' - ); - port ( - clk : in std_logic; - clk_en : in std_logic := '1'; - rst : in std_logic; - vma : out std_logic; - addr : out std_logic_vector(15 downto 0); - rw : out std_logic; - data_out : out std_logic_vector(7 downto 0); - data_in : in std_logic_vector(7 downto 0); - irq : in std_logic; - firq : in std_logic; - nmi : in std_logic; - halt : in std_logic; - hold : in std_logic - ); -end cpu09; - -architecture rtl of cpu09 is - - constant EBIT : integer := 7; - constant FBIT : integer := 6; - constant HBIT : integer := 5; - constant IBIT : integer := 4; - constant NBIT : integer := 3; - constant ZBIT : integer := 2; - constant VBIT : integer := 1; - constant CBIT : integer := 0; - - -- - -- Interrupt vector modifiers - -- - constant RST_VEC : std_logic_vector(2 downto 0) := "111"; - constant NMI_VEC : std_logic_vector(2 downto 0) := "110"; - constant SWI_VEC : std_logic_vector(2 downto 0) := "101"; - constant IRQ_VEC : std_logic_vector(2 downto 0) := "100"; - constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011"; - constant SWI2_VEC : std_logic_vector(2 downto 0) := "010"; - constant SWI3_VEC : std_logic_vector(2 downto 0) := "001"; - constant RESV_VEC : std_logic_vector(2 downto 0) := "000"; - - type state_type is (-- Start off in Reset - reset_state, - -- Fetch Interrupt Vectors (including reset) - vect_lo_state, vect_hi_state, - -- Fetch Instruction Cycle - fetch_state, - -- Decode Instruction Cycles - decode1_state, decode2_state, decode3_state, - -- Calculate Effective Address - imm16_state, - indexed_state, index8_state, index16_state, index16_2_state, - pcrel8_state, pcrel16_state, pcrel16_2_state, - indexaddr_state, indexaddr2_state, - postincr1_state, postincr2_state, - indirect_state, indirect2_state, indirect3_state, - extended_state, - -- single ops - single_op_read_state, - single_op_exec_state, - single_op_write_state, - -- Dual op states - dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state, - dual_op_write8_state, dual_op_write16_state, - -- - sync_state, halt_state, error_state, - -- - andcc_state, orcc_state, - tfr_state, exg_state, exg1_state, - lea_state, - -- Multiplication - mul_state, mulea_state, muld_state, - mul0_state, mul1_state, mul2_state, mul3_state, - mul4_state, mul5_state, mul6_state, mul7_state, - -- Branches - lbranch_state, sbranch_state, - -- Jumps, Subroutine Calls and Returns - jsr_state, jmp_state, - push_return_hi_state, push_return_lo_state, - pull_return_hi_state, pull_return_lo_state, - -- Interrupt cycles - int_nmiirq_state, int_firq_state, - int_entire_state, int_fast_state, - int_pcl_state, int_pch_state, - int_upl_state, int_uph_state, - int_iyl_state, int_iyh_state, - int_ixl_state, int_ixh_state, - int_dp_state, - int_accb_state, int_acca_state, - int_cc_state, - int_cwai_state, - int_maski_state, int_maskif_state, - -- Return From Interrupt - rti_cc_state, rti_entire_state, - rti_acca_state, rti_accb_state, - rti_dp_state, - rti_ixl_state, rti_ixh_state, - rti_iyl_state, rti_iyh_state, - rti_upl_state, rti_uph_state, - rti_pcl_state, rti_pch_state, - -- Push Registers using SP - pshs_state, - pshs_pcl_state, pshs_pch_state, - pshs_upl_state, pshs_uph_state, - pshs_iyl_state, pshs_iyh_state, - pshs_ixl_state, pshs_ixh_state, - pshs_dp_state, - pshs_acca_state, pshs_accb_state, - pshs_cc_state, - -- Pull Registers using SP - puls_state, - puls_cc_state, - puls_acca_state, puls_accb_state, - puls_dp_state, - puls_ixl_state, puls_ixh_state, - puls_iyl_state, puls_iyh_state, - puls_upl_state, puls_uph_state, - puls_pcl_state, puls_pch_state, - -- Push Registers using UP - pshu_state, - pshu_pcl_state, pshu_pch_state, - pshu_spl_state, pshu_sph_state, - pshu_iyl_state, pshu_iyh_state, - pshu_ixl_state, pshu_ixh_state, - pshu_dp_state, - pshu_acca_state, pshu_accb_state, - pshu_cc_state, - -- Pull Registers using UP - pulu_state, - pulu_cc_state, - pulu_acca_state, pulu_accb_state, - pulu_dp_state, - pulu_ixl_state, pulu_ixh_state, - pulu_iyl_state, pulu_iyh_state, - pulu_spl_state, pulu_sph_state, - pulu_pcl_state, pulu_pch_state ); - - type stack_type is array(2 downto 0) of state_type; - type st_type is (idle_st, push_st, pull_st ); - type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad ); - type dout_type is (cc_dout, acca_dout, accb_dout, dp_dout, - ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout, - up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout, - pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout ); - type op_type is (reset_op, fetch_op, latch_op ); - type pre_type is (reset_pre, fetch_pre, latch_pre ); - type cc_type is (reset_cc, load_cc, pull_cc, latch_cc ); - type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca ); - type accb_type is (reset_accb, load_accb, pull_accb, latch_accb ); - type dp_type is (reset_dp, load_dp, pull_dp, latch_dp ); - type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix ); - type iy_type is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy ); - type sp_type is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp ); - type up_type is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up ); - type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc ); - type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md ); - type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea ); - type iv_type is (latch_iv, reset_iv, nmi_iv, irq_iv, firq_iv, swi_iv, swi2_iv, swi3_iv, resv_iv); - type nmi_type is (reset_nmi, set_nmi, latch_nmi ); - type left_type is (cc_left, acca_left, accb_left, dp_left, - ix_left, iy_left, up_left, sp_left, - accd_left, md_left, pc_left, ea_left ); - type right_type is (ea_right, zero_right, one_right, two_right, - acca_right, accb_right, accd_right, - md_right, md_sign5_right, md_sign8_right ); - type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc, - alu_and, alu_ora, alu_eor, - alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com, - alu_lsr16, alu_lsl16, - alu_ror8, alu_rol8, alu_mul, - alu_asr8, alu_asl8, alu_lsr8, - alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx, - alu_seif, alu_sei, alu_see, alu_cle, - alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa ); - - signal op_code: std_logic_vector(7 downto 0); - signal pre_code: std_logic_vector(7 downto 0); - signal acca: std_logic_vector(7 downto 0); - signal accb: std_logic_vector(7 downto 0); - signal cc: std_logic_vector(7 downto 0); - signal cc_out: std_logic_vector(7 downto 0); - signal dp: std_logic_vector(7 downto 0); - signal xreg: std_logic_vector(15 downto 0); - signal yreg: std_logic_vector(15 downto 0); - signal sp: std_logic_vector(15 downto 0); - signal up: std_logic_vector(15 downto 0); - signal ea: std_logic_vector(15 downto 0); - signal pc: std_logic_vector(15 downto 0); - signal md: std_logic_vector(15 downto 0); - signal left: std_logic_vector(15 downto 0); - signal right: std_logic_vector(15 downto 0); - signal out_alu: std_logic_vector(15 downto 0); - signal iv: std_logic_vector(2 downto 0); - signal nmi_req: std_logic; - signal nmi_ack: std_logic; - signal nmi_enable: std_logic; - - signal state: state_type; - signal next_state: state_type; - signal saved_state: state_type; - signal return_state: state_type; - signal state_stack: stack_type; - signal st_ctrl: st_type; - signal pc_ctrl: pc_type; - signal ea_ctrl: ea_type; - signal op_ctrl: op_type; - signal pre_ctrl: pre_type; - signal md_ctrl: md_type; - signal acca_ctrl: acca_type; - signal accb_ctrl: accb_type; - signal ix_ctrl: ix_type; - signal iy_ctrl: iy_type; - signal cc_ctrl: cc_type; - signal dp_ctrl: dp_type; - signal sp_ctrl: sp_type; - signal up_ctrl: up_type; - signal iv_ctrl: iv_type; - signal left_ctrl: left_type; - signal right_ctrl: right_type; - signal alu_ctrl: alu_type; - signal addr_ctrl: addr_type; - signal dout_ctrl: dout_type; - signal nmi_ctrl: nmi_type; - - -begin - ----------------------------------- --- --- State machine stack --- ----------------------------------- ---state_stack_proc: process( clk, hold, state_stack, st_ctrl, --- return_state, fetch_state ) -state_stack_proc: process( clk, state_stack ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold= '1' then - state_stack(0) <= state_stack(0); - state_stack(1) <= state_stack(1); - state_stack(2) <= state_stack(2); - else - case st_ctrl is - when idle_st => - state_stack(0) <= state_stack(0); - state_stack(1) <= state_stack(1); - state_stack(2) <= state_stack(2); - when push_st => - state_stack(0) <= return_state; - state_stack(1) <= state_stack(0); - state_stack(2) <= state_stack(1); - when pull_st => - state_stack(0) <= state_stack(1); - state_stack(1) <= state_stack(2); - state_stack(2) <= fetch_state; - when others => - state_stack(0) <= state_stack(0); - state_stack(1) <= state_stack(1); - state_stack(2) <= state_stack(2); - end case; - end if; - end if; -- clk_en - end if; -- clk'event - saved_state <= state_stack(0); -end process; - ----------------------------------- --- --- Program Counter Control --- ----------------------------------- - ---pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in ) -pc_reg: process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold= '1' then - pc <= pc; - else - case pc_ctrl is - when reset_pc => - pc <= "0000000000000000"; - when load_pc => - pc <= out_alu(15 downto 0); - when pull_lo_pc => - pc(7 downto 0) <= data_in; - when pull_hi_pc => - pc(15 downto 8) <= data_in; - when incr_pc => - pc <= pc + 1; - when others => - -- when latch_pc => - pc <= pc; - end case; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - ----------------------------------- --- --- Effective Address Control --- ----------------------------------- - ---ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp ) -ea_reg: process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold= '1' then - ea <= ea; - else - case ea_ctrl is - when reset_ea => - ea <= "0000000000000000"; - when fetch_first_ea => - ea(7 downto 0) <= data_in; - ea(15 downto 8) <= dp; - when fetch_next_ea => - ea(15 downto 8) <= ea(7 downto 0); - ea(7 downto 0) <= data_in; - when load_ea => - ea <= out_alu(15 downto 0); - when others => - -- when latch_ea => - ea <= ea; - end case; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - --------------------------------- --- --- Accumulator A --- --------------------------------- ---acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in ) -acca_reg : process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold= '1' then - acca <= acca; - else - case acca_ctrl is - when reset_acca => - acca <= "00000000"; - when load_acca => - acca <= out_alu(7 downto 0); - when load_hi_acca => - acca <= out_alu(15 downto 8); - when pull_acca => - acca <= data_in; - when others => - -- when latch_acca => - acca <= acca; - end case; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - --------------------------------- --- --- Accumulator B --- --------------------------------- ---accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in ) -accb_reg : process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold= '1' then - accb <= accb; - else - case accb_ctrl is - when reset_accb => - accb <= "00000000"; - when load_accb => - accb <= out_alu(7 downto 0); - when pull_accb => - accb <= data_in; - when others => - -- when latch_accb => - accb <= accb; - end case; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - --------------------------------- --- --- X Index register --- --------------------------------- ---ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in ) -ix_reg : process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold= '1' then - xreg <= xreg; - else - case ix_ctrl is - when reset_ix => - xreg <= "0000000000000000"; - when load_ix => - xreg <= out_alu(15 downto 0); - when pull_hi_ix => - xreg(15 downto 8) <= data_in; - when pull_lo_ix => - xreg(7 downto 0) <= data_in; - when others => - -- when latch_ix => - xreg <= xreg; - end case; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - --------------------------------- --- --- Y Index register --- --------------------------------- ---iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in ) -iy_reg : process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold= '1' then - yreg <= yreg; - else - case iy_ctrl is - when reset_iy => - yreg <= "0000000000000000"; - when load_iy => - yreg <= out_alu(15 downto 0); - when pull_hi_iy => - yreg(15 downto 8) <= data_in; - when pull_lo_iy => - yreg(7 downto 0) <= data_in; - when others => - -- when latch_iy => - yreg <= yreg; - end case; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - --------------------------------- --- --- S stack pointer --- --------------------------------- ---sp_reg : process( clk, sp_ctrl, hold, sp, out_alu, data_in, nmi_enable ) -sp_reg : process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold= '1' then - sp <= sp; - nmi_enable <= nmi_enable; - else - case sp_ctrl is - when reset_sp => - sp <= "0000000000000000"; - nmi_enable <= '0'; - when load_sp => - sp <= out_alu(15 downto 0); - nmi_enable <= '1'; - when pull_hi_sp => - sp(15 downto 8) <= data_in; - nmi_enable <= nmi_enable; - when pull_lo_sp => - sp(7 downto 0) <= data_in; - nmi_enable <= '1'; - when others => - -- when latch_sp => - sp <= sp; - nmi_enable <= nmi_enable; - end case; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - --------------------------------- --- --- U stack pointer --- --------------------------------- ---up_reg : process( clk, up_ctrl, hold, up, out_alu, data_in ) -up_reg : process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold= '1' then - up <= up; - else - case up_ctrl is - when reset_up => - up <= "0000000000000000"; - when load_up => - up <= out_alu(15 downto 0); - when pull_hi_up => - up(15 downto 8) <= data_in; - when pull_lo_up => - up(7 downto 0) <= data_in; - when others => - -- when latch_up => - up <= up; - end case; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - --------------------------------- --- --- Memory Data --- --------------------------------- ---md_reg : process( clk, md_ctrl, hold, out_alu, data_in, md ) -md_reg : process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold= '1' then - md <= md; - else - case md_ctrl is - when reset_md => - md <= "0000000000000000"; - when load_md => - md <= out_alu(15 downto 0); - when fetch_first_md => -- sign extend md for branches - md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) & - data_in(7) & data_in(7) & data_in(7) & data_in(7) ; - md(7 downto 0) <= data_in; - when fetch_next_md => - md(15 downto 8) <= md(7 downto 0); - md(7 downto 0) <= data_in; - when shiftl_md => - md(15 downto 1) <= md(14 downto 0); - md(0) <= '0'; - when others => - -- when latch_md => - md <= md; - end case; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - - ----------------------------------- --- --- Condition Codes --- ----------------------------------- - ---cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in ) -cc_reg: process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold= '1' then - cc <= cc; - else - case cc_ctrl is - when reset_cc => - cc <= "11010000"; -- set EBIT, FBIT & IBIT - when load_cc => - cc <= cc_out; - when pull_cc => - cc <= data_in; - when others => - -- when latch_cc => - cc <= cc; - end case; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - ----------------------------------- --- --- Direct Page register --- ----------------------------------- - ---dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in ) -dp_reg: process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold= '1' then - dp <= dp; - else - case dp_ctrl is - when reset_dp => - dp <= "00000000"; - when load_dp => - dp <= out_alu(7 downto 0); - when pull_dp => - dp <= data_in; - when others => - -- when latch_dp => - dp <= dp; - end case; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - ----------------------------------- --- --- interrupt vector --- ----------------------------------- - ---iv_mux: process( clk, iv_ctrl, hold, iv ) -iv_mux: process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold= '1' then - iv <= iv; - else - case iv_ctrl is - when reset_iv => - iv <= RST_VEC; - when nmi_iv => - iv <= NMI_VEC; - when swi_iv => - iv <= SWI_VEC; - when irq_iv => - iv <= IRQ_VEC; - when firq_iv => - iv <= FIRQ_VEC; - when swi2_iv => - iv <= SWI2_VEC; - when swi3_iv => - iv <= SWI3_VEC; - when resv_iv => - iv <= RESV_VEC; - when others => - iv <= iv; - end case; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - - ----------------------------------- --- --- op code register --- ----------------------------------- - ---op_reg: process( clk, op_ctrl, hold, op_code, data_in ) -op_reg: process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold= '1' then - op_code <= op_code; - else - case op_ctrl is - when reset_op => - op_code <= "00010010"; - when fetch_op => - op_code <= data_in; - when others => - -- when latch_op => - op_code <= op_code; - end case; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - - ----------------------------------- --- --- pre byte op code register --- ----------------------------------- - ---pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in ) -pre_reg: process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold= '1' then - pre_code <= pre_code; - else - case pre_ctrl is - when reset_pre => - pre_code <= "00000000"; - when fetch_pre => - pre_code <= data_in; - when others => - -- when latch_pre => - pre_code <= pre_code; - end case; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - --------------------------------- --- --- state machine --- --------------------------------- - ---change_state: process( clk, rst, state, hold, next_state ) -change_state: process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if rst = '1' then - state <= reset_state; - else - if hold = '1' then - state <= state; - else - state <= next_state; - end if; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - -- output - ------------------------------------- --- --- Nmi register --- ------------------------------------- - ---nmi_reg: process( clk, nmi_ctrl, hold, nmi_ack ) -nmi_reg: process( clk ) -begin - if clk'event and clk = CLK_POL then - if clk_en = '1' then - if hold = '1' then - nmi_ack <= nmi_ack; - else - case nmi_ctrl is - when set_nmi => - nmi_ack <= '1'; - when reset_nmi => - nmi_ack <= '0'; - when others => - -- when latch_nmi => - nmi_ack <= nmi_ack; - end case; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - ------------------------------------- --- --- Detect Edge of NMI interrupt --- ------------------------------------- - ---nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable ) -nmi_handler : process( rst, clk ) -begin - if rst='1' then - nmi_req <= '0'; - elsif clk'event and clk = CLK_POL then - if clk_en = '1' then - if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then - nmi_req <= '1'; - else - if (nmi='0') and (nmi_ack='1') then - nmi_req <= '0'; - end if; - end if; - end if; -- clk_en - end if; -- clk'event -end process; - - ----------------------------------- --- --- Address output multiplexer --- ----------------------------------- - -addr_mux: process( addr_ctrl, pc, ea, up, sp, iv ) -begin - case addr_ctrl is - when idle_ad => - vma <= '0'; - addr <= "1111111111111111"; - rw <= '1'; - when fetch_ad => - vma <= '1'; - addr <= pc; - rw <= '1'; - when read_ad => - vma <= '1'; - addr <= ea; - rw <= '1'; - when write_ad => - vma <= '1'; - addr <= ea; - rw <= '0'; - when pushs_ad => - vma <= '1'; - addr <= sp; - rw <= '0'; - when pulls_ad => - vma <= '1'; - addr <= sp; - rw <= '1'; - when pushu_ad => - vma <= '1'; - addr <= up; - rw <= '0'; - when pullu_ad => - vma <= '1'; - addr <= up; - rw <= '1'; - when int_hi_ad => - vma <= '1'; - addr <= "111111111111" & iv & "0"; - rw <= '1'; - when int_lo_ad => - vma <= '1'; - addr <= "111111111111" & iv & "1"; - rw <= '1'; - when others => - vma <= '0'; - addr <= "1111111111111111"; - rw <= '1'; - end case; -end process; - --------------------------------- --- --- Data Bus output --- --------------------------------- -dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc ) -begin - case dout_ctrl is - when cc_dout => -- condition code register - data_out <= cc; - when acca_dout => -- accumulator a - data_out <= acca; - when accb_dout => -- accumulator b - data_out <= accb; - when dp_dout => -- direct page register - data_out <= dp; - when ix_lo_dout => -- X index reg - data_out <= xreg(7 downto 0); - when ix_hi_dout => -- X index reg - data_out <= xreg(15 downto 8); - when iy_lo_dout => -- Y index reg - data_out <= yreg(7 downto 0); - when iy_hi_dout => -- Y index reg - data_out <= yreg(15 downto 8); - when up_lo_dout => -- U stack pointer - data_out <= up(7 downto 0); - when up_hi_dout => -- U stack pointer - data_out <= up(15 downto 8); - when sp_lo_dout => -- S stack pointer - data_out <= sp(7 downto 0); - when sp_hi_dout => -- S stack pointer - data_out <= sp(15 downto 8); - when md_lo_dout => -- alu output - data_out <= md(7 downto 0); - when md_hi_dout => -- alu output - data_out <= md(15 downto 8); - when pc_lo_dout => -- low order pc - data_out <= pc(7 downto 0); - when pc_hi_dout => -- high order pc - data_out <= pc(15 downto 8); - when others => - data_out <= "00000000"; - end case; -end process; - ----------------------------------- --- --- Left Mux --- ----------------------------------- - -left_mux: process( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md ) -begin - case left_ctrl is - when cc_left => - left(15 downto 8) <= "00000000"; - left(7 downto 0) <= cc; - when acca_left => - left(15 downto 8) <= "00000000"; - left(7 downto 0) <= acca; - when accb_left => - left(15 downto 8) <= "00000000"; - left(7 downto 0) <= accb; - when dp_left => - left(15 downto 8) <= "00000000"; - left(7 downto 0) <= dp; - when accd_left => - left(15 downto 8) <= acca; - left(7 downto 0) <= accb; - when md_left => - left <= md; - when ix_left => - left <= xreg; - when iy_left => - left <= yreg; - when sp_left => - left <= sp; - when up_left => - left <= up; - when pc_left => - left <= pc; - when others => --- when ea_left => - left <= ea; - end case; -end process; - ----------------------------------- --- --- Right Mux --- ----------------------------------- - -right_mux: process( right_ctrl, md, acca, accb, ea ) -begin - case right_ctrl is - when ea_right => - right <= ea; - when zero_right => - right <= "0000000000000000"; - when one_right => - right <= "0000000000000001"; - when two_right => - right <= "0000000000000010"; - when acca_right => - if acca(7) = '0' then - right <= "00000000" & acca(7 downto 0); - else - right <= "11111111" & acca(7 downto 0); - end if; - when accb_right => - if accb(7) = '0' then - right <= "00000000" & accb(7 downto 0); - else - right <= "11111111" & accb(7 downto 0); - end if; - when accd_right => - right <= acca & accb; - when md_sign5_right => - if md(4) = '0' then - right <= "00000000000" & md(4 downto 0); - else - right <= "11111111111" & md(4 downto 0); - end if; - when md_sign8_right => - if md(7) = '0' then - right <= "00000000" & md(7 downto 0); - else - right <= "11111111" & md(7 downto 0); - end if; - when others => --- when md_right => - right <= md; - end case; -end process; - ----------------------------------- --- --- Arithmetic Logic Unit --- ----------------------------------- - -alu: process( alu_ctrl, cc, left, right, out_alu, cc_out ) -variable valid_lo, valid_hi : boolean; -variable carry_in : std_logic; -variable daa_reg : std_logic_vector(7 downto 0); -begin - - case alu_ctrl is - when alu_adc | alu_sbc | - alu_rol8 | alu_ror8 => - carry_in := cc(CBIT); - when alu_asr8 => - carry_in := left(7); - when others => - carry_in := '0'; - end case; - - valid_lo := left(3 downto 0) <= 9; - valid_hi := left(7 downto 4) <= 9; - - if (cc(CBIT) = '0') then - if( cc(HBIT) = '1' ) then - if valid_hi then - daa_reg := "00000110"; - else - daa_reg := "01100110"; - end if; - else - if valid_lo then - if valid_hi then - daa_reg := "00000000"; - else - daa_reg := "01100000"; - end if; - else - if( left(7 downto 4) <= 8 ) then - daa_reg := "00000110"; - else - daa_reg := "01100110"; - end if; - end if; - end if; - else - if ( cc(HBIT) = '1' )then - daa_reg := "01100110"; - else - if valid_lo then - daa_reg := "01100000"; - else - daa_reg := "01100110"; - end if; - end if; - end if; - - case alu_ctrl is - when alu_add8 | alu_inc | - alu_add16 | alu_adc | alu_mul => - out_alu <= left + right + ("000000000000000" & carry_in); - when alu_sub8 | alu_dec | - alu_sub16 | alu_sbc => - out_alu <= left - right - ("000000000000000" & carry_in); - when alu_abx => - out_alu <= left + ("00000000" & right(7 downto 0)) ; - when alu_and => - out_alu <= left and right; -- and/bit - when alu_ora => - out_alu <= left or right; -- or - when alu_eor => - out_alu <= left xor right; -- eor/xor - when alu_lsl16 | alu_asl8 | alu_rol8 => - out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16 - when alu_lsr16 => - out_alu <= carry_in & left(15 downto 1); -- lsr16 - when alu_lsr8 | alu_asr8 | alu_ror8 => - out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror8/asr8/lsr8 - when alu_neg => - out_alu <= right - left; -- neg (right=0) - when alu_com => - out_alu <= not left; - when alu_clr | alu_ld8 | alu_ld16 | alu_lea => - out_alu <= right; -- clr, ld - when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr => - out_alu <= left; - when alu_daa => - out_alu <= left + ("00000000" & daa_reg); - when alu_sex => - if left(7) = '0' then - out_alu <= "00000000" & left(7 downto 0); - else - out_alu <= "11111111" & left(7 downto 0); - end if; - when others => - out_alu <= left; -- nop - end case; - - -- - -- carry bit - -- - case alu_ctrl is - when alu_add8 | alu_adc => - cc_out(CBIT) <= (left(7) and right(7)) or - (left(7) and not out_alu(7)) or - (right(7) and not out_alu(7)); - when alu_sub8 | alu_sbc => - cc_out(CBIT) <= ((not left(7)) and right(7)) or - ((not left(7)) and out_alu(7)) or - (right(7) and out_alu(7)); - when alu_add16 => - cc_out(CBIT) <= (left(15) and right(15)) or - (left(15) and not out_alu(15)) or - (right(15) and not out_alu(15)); - when alu_sub16 => - cc_out(CBIT) <= ((not left(15)) and right(15)) or - ((not left(15)) and out_alu(15)) or - (right(15) and out_alu(15)); - when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 => - cc_out(CBIT) <= left(0); - when alu_rol8 | alu_asl8 => - cc_out(CBIT) <= left(7); - when alu_lsl16 => - cc_out(CBIT) <= left(15); - when alu_com => - cc_out(CBIT) <= '1'; - when alu_neg | alu_clr => - cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or - out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0); - when alu_mul => - cc_out(CBIT) <= out_alu(7); - when alu_daa => - if ( daa_reg(7 downto 4) = "0110" ) then - cc_out(CBIT) <= '1'; - else - cc_out(CBIT) <= '0'; - end if; - when alu_andcc => - cc_out(CBIT) <= left(CBIT) and cc(CBIT); - when alu_orcc => - cc_out(CBIT) <= left(CBIT) or cc(CBIT); - when alu_tfr => - cc_out(CBIT) <= left(CBIT); - when others => - cc_out(CBIT) <= cc(CBIT); - end case; - -- - -- Zero flag - -- - case alu_ctrl is - when alu_add8 | alu_sub8 | - alu_adc | alu_sbc | - alu_and | alu_ora | alu_eor | - alu_inc | alu_dec | - alu_neg | alu_com | alu_clr | - alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 | - alu_ld8 | alu_st8 | alu_sex | alu_daa => - cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or - out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) ); - when alu_add16 | alu_sub16 | alu_mul | - alu_lsl16 | alu_lsr16 | - alu_ld16 | alu_st16 | alu_lea => - cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or - out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or - out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or - out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) ); - when alu_andcc => - cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT); - when alu_orcc => - cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT); - when alu_tfr => - cc_out(ZBIT) <= left(ZBIT); - when others => - cc_out(ZBIT) <= cc(ZBIT); - end case; - - -- - -- negative flag - -- - case alu_ctrl is - when alu_add8 | alu_sub8 | - alu_adc | alu_sbc | - alu_and | alu_ora | alu_eor | - alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 | - alu_inc | alu_dec | alu_neg | alu_com | alu_clr | - alu_ld8 | alu_st8 | alu_sex | alu_daa => - cc_out(NBIT) <= out_alu(7); - when alu_add16 | alu_sub16 | - alu_lsl16 | alu_lsr16 | - alu_ld16 | alu_st16 => - cc_out(NBIT) <= out_alu(15); - when alu_andcc => - cc_out(NBIT) <= left(NBIT) and cc(NBIT); - when alu_orcc => - cc_out(NBIT) <= left(NBIT) or cc(NBIT); - when alu_tfr => - cc_out(NBIT) <= left(NBIT); - when others => - cc_out(NBIT) <= cc(NBIT); - end case; - - -- - -- Interrupt mask flag - -- - case alu_ctrl is - when alu_andcc => - cc_out(IBIT) <= left(IBIT) and cc(IBIT); - when alu_orcc => - cc_out(IBIT) <= left(IBIT) or cc(IBIT); - when alu_tfr => - cc_out(IBIT) <= left(IBIT); - when alu_seif | alu_sei => - cc_out(IBIT) <= '1'; - when others => - cc_out(IBIT) <= cc(IBIT); -- interrupt mask - end case; - - -- - -- Half Carry flag - -- - case alu_ctrl is - when alu_add8 | alu_adc => - cc_out(HBIT) <= (left(3) and right(3)) or - (right(3) and not out_alu(3)) or - (left(3) and not out_alu(3)); - when alu_andcc => - cc_out(HBIT) <= left(HBIT) and cc(HBIT); - when alu_orcc => - cc_out(HBIT) <= left(HBIT) or cc(HBIT); - when alu_tfr => - cc_out(HBIT) <= left(HBIT); - when others => - cc_out(HBIT) <= cc(HBIT); - end case; - - -- - -- Overflow flag - -- - case alu_ctrl is - when alu_add8 | alu_adc => - cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or - ((not left(7)) and (not right(7)) and out_alu(7)); - when alu_sub8 | alu_sbc => - cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or - ((not left(7)) and right(7) and out_alu(7)); - when alu_add16 => - cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or - ((not left(15)) and (not right(15)) and out_alu(15)); - when alu_sub16 => - cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or - ((not left(15)) and right(15) and out_alu(15)); - when alu_inc => - cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and - left(3) and left(2) and left(1) and left(0)); - when alu_dec | alu_neg => - cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and - (not left(3)) and (not left(2)) and (not left(1)) and (not left(0))); --- 6809 Programming reference manual says --- V not affected by ASR, LSR and ROR --- This is different to the 6800 --- John Kent 6th June 2006 --- when alu_asr8 => --- cc_out(VBIT) <= left(0) xor left(7); --- when alu_lsr8 | alu_lsr16 => --- cc_out(VBIT) <= left(0); --- when alu_ror8 => --- cc_out(VBIT) <= left(0) xor cc(CBIT); - when alu_lsl16 => - cc_out(VBIT) <= left(15) xor left(14); - when alu_rol8 | alu_asl8 => - cc_out(VBIT) <= left(7) xor left(6); --- --- 11th July 2006 - John Kent --- What DAA does with V is anyones guess --- It is undefined in the 6809 programming manual --- - when alu_daa => - cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT); --- CLR resets V Bit --- John Kent 6th June 2006 - when alu_and | alu_ora | alu_eor | alu_com | alu_clr | - alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex => - cc_out(VBIT) <= '0'; - when alu_andcc => - cc_out(VBIT) <= left(VBIT) and cc(VBIT); - when alu_orcc => - cc_out(VBIT) <= left(VBIT) or cc(VBIT); - when alu_tfr => - cc_out(VBIT) <= left(VBIT); - when others => - cc_out(VBIT) <= cc(VBIT); - end case; - - case alu_ctrl is - when alu_andcc => - cc_out(FBIT) <= left(FBIT) and cc(FBIT); - when alu_orcc => - cc_out(FBIT) <= left(FBIT) or cc(FBIT); - when alu_tfr => - cc_out(FBIT) <= left(FBIT); - when alu_seif => - cc_out(FBIT) <= '1'; - when others => - cc_out(FBIT) <= cc(FBIT); - end case; - - case alu_ctrl is - when alu_andcc => - cc_out(EBIT) <= left(EBIT) and cc(EBIT); - when alu_orcc => - cc_out(EBIT) <= left(EBIT) or cc(EBIT); - when alu_tfr => - cc_out(EBIT) <= left(EBIT); - when alu_see => - cc_out(EBIT) <= '1'; - when alu_cle => - cc_out(EBIT) <= '0'; - when others => - cc_out(EBIT) <= cc(EBIT); - end case; -end process; - ------------------------------------- --- --- state sequencer --- ------------------------------------- -process( state, saved_state, - op_code, pre_code, - cc, ea, md, iv, - irq, firq, nmi_req, nmi_ack, halt ) -variable cond_true : boolean; -- variable used to evaluate coditional branches -begin - -- Registers preserved - cc_ctrl <= latch_cc; - acca_ctrl <= latch_acca; - accb_ctrl <= latch_accb; - dp_ctrl <= latch_dp; - ix_ctrl <= latch_ix; - iy_ctrl <= latch_iy; - up_ctrl <= latch_up; - sp_ctrl <= latch_sp; - pc_ctrl <= latch_pc; - md_ctrl <= latch_md; - ea_ctrl <= latch_ea; - iv_ctrl <= latch_iv; - op_ctrl <= latch_op; - pre_ctrl <= latch_pre; - nmi_ctrl <= latch_nmi; - -- ALU Idle - left_ctrl <= pc_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_nop; - -- Bus idle - addr_ctrl <= idle_ad; - dout_ctrl <= cc_dout; - -- Next State Fetch - st_ctrl <= idle_st; - return_state <= fetch_state; - next_state <= fetch_state; - - case state is - when reset_state => -- released from reset - -- reset the registers - op_ctrl <= reset_op; - pre_ctrl <= reset_pre; - cc_ctrl <= reset_cc; - acca_ctrl <= reset_acca; - accb_ctrl <= reset_accb; - dp_ctrl <= reset_dp; - ix_ctrl <= reset_ix; - iy_ctrl <= reset_iy; - up_ctrl <= reset_up; - sp_ctrl <= reset_sp; - pc_ctrl <= reset_pc; - ea_ctrl <= reset_ea; - md_ctrl <= reset_md; - iv_ctrl <= reset_iv; - nmi_ctrl <= reset_nmi; - next_state <= vect_hi_state; - - -- - -- Jump via interrupt vector - -- iv holds interrupt type - -- fetch PC hi from vector location - -- - when vect_hi_state => - -- fetch pc low interrupt vector - pc_ctrl <= pull_hi_pc; - addr_ctrl <= int_hi_ad; - next_state <= vect_lo_state; - -- - -- jump via interrupt vector - -- iv holds vector type - -- fetch PC lo from vector location - -- - when vect_lo_state => - -- fetch the vector low byte - pc_ctrl <= pull_lo_pc; - addr_ctrl <= int_lo_ad; - next_state <= fetch_state; - -- - -- Here to fetch an instruction - -- PC points to opcode - -- Should service interrupt requests at this point - -- either from the timer - -- or from the external input. - -- - when fetch_state => - -- fetch the op code - op_ctrl <= fetch_op; - pre_ctrl <= fetch_pre; - ea_ctrl <= reset_ea; - -- Fetch op code - addr_ctrl <= fetch_ad; - -- - case op_code(7 downto 6) is - when "10" => -- acca - case op_code(3 downto 0) is - when "0000" => -- suba - left_ctrl <= acca_left; - right_ctrl <= md_right; - alu_ctrl <= alu_sub8; - cc_ctrl <= load_cc; - acca_ctrl <= load_acca; - when "0001" => -- cmpa - left_ctrl <= acca_left; - right_ctrl <= md_right; - alu_ctrl <= alu_sub8; - cc_ctrl <= load_cc; - when "0010" => -- sbca - left_ctrl <= acca_left; - right_ctrl <= md_right; - alu_ctrl <= alu_sbc; - cc_ctrl <= load_cc; - acca_ctrl <= load_acca; - when "0011" => - case pre_code is - when "00010000" => -- page 2 -- cmpd - left_ctrl <= accd_left; - right_ctrl <= md_right; - alu_ctrl <= alu_sub16; - cc_ctrl <= load_cc; - when "00010001" => -- page 3 -- cmpu - left_ctrl <= up_left; - right_ctrl <= md_right; - alu_ctrl <= alu_sub16; - cc_ctrl <= load_cc; - when others => -- page 1 -- subd - left_ctrl <= accd_left; - right_ctrl <= md_right; - alu_ctrl <= alu_sub16; - cc_ctrl <= load_cc; - acca_ctrl <= load_hi_acca; - accb_ctrl <= load_accb; - end case; - when "0100" => -- anda - left_ctrl <= acca_left; - right_ctrl <= md_right; - alu_ctrl <= alu_and; - cc_ctrl <= load_cc; - acca_ctrl <= load_acca; - when "0101" => -- bita - left_ctrl <= acca_left; - right_ctrl <= md_right; - alu_ctrl <= alu_and; - cc_ctrl <= load_cc; - when "0110" => -- ldaa - left_ctrl <= acca_left; - right_ctrl <= md_right; - alu_ctrl <= alu_ld8; - cc_ctrl <= load_cc; - acca_ctrl <= load_acca; - when "0111" => -- staa - left_ctrl <= acca_left; - right_ctrl <= md_right; - alu_ctrl <= alu_st8; - cc_ctrl <= load_cc; - when "1000" => -- eora - left_ctrl <= acca_left; - right_ctrl <= md_right; - alu_ctrl <= alu_eor; - cc_ctrl <= load_cc; - acca_ctrl <= load_acca; - when "1001" => -- adca - left_ctrl <= acca_left; - right_ctrl <= md_right; - alu_ctrl <= alu_adc; - cc_ctrl <= load_cc; - acca_ctrl <= load_acca; - when "1010" => -- oraa - left_ctrl <= acca_left; - right_ctrl <= md_right; - alu_ctrl <= alu_ora; - cc_ctrl <= load_cc; - acca_ctrl <= load_acca; - when "1011" => -- adda - left_ctrl <= acca_left; - right_ctrl <= md_right; - alu_ctrl <= alu_add8; - cc_ctrl <= load_cc; - acca_ctrl <= load_acca; - when "1100" => - case pre_code is - when "00010000" => -- page 2 -- cmpy - left_ctrl <= iy_left; - right_ctrl <= md_right; - alu_ctrl <= alu_sub16; - cc_ctrl <= load_cc; - when "00010001" => -- page 3 -- cmps - left_ctrl <= sp_left; - right_ctrl <= md_right; - alu_ctrl <= alu_sub16; - cc_ctrl <= load_cc; - when others => -- page 1 -- cmpx - left_ctrl <= ix_left; - right_ctrl <= md_right; - alu_ctrl <= alu_sub16; - cc_ctrl <= load_cc; - end case; - when "1101" => -- bsr / jsr - null; - when "1110" => -- ldx - case pre_code is - when "00010000" => -- page 2 -- ldy - left_ctrl <= iy_left; - right_ctrl <= md_right; - alu_ctrl <= alu_ld16; - cc_ctrl <= load_cc; - iy_ctrl <= load_iy; - when others => -- page 1 -- ldx - left_ctrl <= ix_left; - right_ctrl <= md_right; - alu_ctrl <= alu_ld16; - cc_ctrl <= load_cc; - ix_ctrl <= load_ix; - end case; - when "1111" => -- stx - case pre_code is - when "00010000" => -- page 2 -- sty - left_ctrl <= iy_left; - right_ctrl <= md_right; - alu_ctrl <= alu_st16; - cc_ctrl <= load_cc; - when others => -- page 1 -- stx - left_ctrl <= ix_left; - right_ctrl <= md_right; - alu_ctrl <= alu_st16; - cc_ctrl <= load_cc; - end case; - when others => - null; - end case; - when "11" => -- accb dual op - case op_code(3 downto 0) is - when "0000" => -- subb - left_ctrl <= accb_left; - right_ctrl <= md_right; - alu_ctrl <= alu_sub8; - cc_ctrl <= load_cc; - accb_ctrl <= load_accb; - when "0001" => -- cmpb - left_ctrl <= accb_left; - right_ctrl <= md_right; - alu_ctrl <= alu_sub8; - cc_ctrl <= load_cc; - when "0010" => -- sbcb - left_ctrl <= accb_left; - right_ctrl <= md_right; - alu_ctrl <= alu_sbc; - cc_ctrl <= load_cc; - accb_ctrl <= load_accb; - when "0011" => -- addd - left_ctrl <= accd_left; - right_ctrl <= md_right; - alu_ctrl <= alu_add16; - cc_ctrl <= load_cc; - acca_ctrl <= load_hi_acca; - accb_ctrl <= load_accb; - when "0100" => -- andb - left_ctrl <= accb_left; - right_ctrl <= md_right; - alu_ctrl <= alu_and; - cc_ctrl <= load_cc; - accb_ctrl <= load_accb; - when "0101" => -- bitb - left_ctrl <= accb_left; - right_ctrl <= md_right; - alu_ctrl <= alu_and; - cc_ctrl <= load_cc; - when "0110" => -- ldab - left_ctrl <= accb_left; - right_ctrl <= md_right; - alu_ctrl <= alu_ld8; - cc_ctrl <= load_cc; - accb_ctrl <= load_accb; - when "0111" => -- stab - left_ctrl <= accb_left; - right_ctrl <= md_right; - alu_ctrl <= alu_st8; - cc_ctrl <= load_cc; - when "1000" => -- eorb - left_ctrl <= accb_left; - right_ctrl <= md_right; - alu_ctrl <= alu_eor; - cc_ctrl <= load_cc; - accb_ctrl <= load_accb; - when "1001" => -- adcb - left_ctrl <= accb_left; - right_ctrl <= md_right; - alu_ctrl <= alu_adc; - cc_ctrl <= load_cc; - accb_ctrl <= load_accb; - when "1010" => -- orab - left_ctrl <= accb_left; - right_ctrl <= md_right; - alu_ctrl <= alu_ora; - cc_ctrl <= load_cc; - accb_ctrl <= load_accb; - when "1011" => -- addb - left_ctrl <= accb_left; - right_ctrl <= md_right; - alu_ctrl <= alu_add8; - cc_ctrl <= load_cc; - accb_ctrl <= load_accb; - when "1100" => -- ldd - left_ctrl <= accd_left; - right_ctrl <= md_right; - alu_ctrl <= alu_ld16; - cc_ctrl <= load_cc; - acca_ctrl <= load_hi_acca; - accb_ctrl <= load_accb; - when "1101" => -- std - left_ctrl <= accd_left; - right_ctrl <= md_right; - alu_ctrl <= alu_st16; - cc_ctrl <= load_cc; - when "1110" => -- ldu - case pre_code is - when "00010000" => -- page 2 -- lds - left_ctrl <= sp_left; - right_ctrl <= md_right; - alu_ctrl <= alu_ld16; - cc_ctrl <= load_cc; - sp_ctrl <= load_sp; - when others => -- page 1 -- ldu - left_ctrl <= up_left; - right_ctrl <= md_right; - alu_ctrl <= alu_ld16; - cc_ctrl <= load_cc; - up_ctrl <= load_up; - end case; - when "1111" => - case pre_code is - when "00010000" => -- page 2 -- sts - left_ctrl <= sp_left; - right_ctrl <= md_right; - alu_ctrl <= alu_st16; - cc_ctrl <= load_cc; - when others => -- page 1 -- stu - left_ctrl <= up_left; - right_ctrl <= md_right; - alu_ctrl <= alu_st16; - cc_ctrl <= load_cc; - end case; - when others => - null; - end case; - when others => - null; - end case; - if halt = '1' then - iv_ctrl <= reset_iv; - next_state <= halt_state; - -- service non maskable interrupts - elsif (nmi_req = '1') and (nmi_ack = '0') then - iv_ctrl <= nmi_iv; - nmi_ctrl <= set_nmi; - next_state <= int_nmiirq_state; - -- service maskable interrupts - else - -- - -- nmi request is not cleared until nmi input goes low - -- - if(nmi_req = '0') and (nmi_ack='1') then - nmi_ctrl <= reset_nmi; - end if; - -- - -- FIRQ & IRQ are level sensitive - -- - if (firq = '1') and (cc(FBIT) = '0') then - iv_ctrl <= firq_iv; - next_state <= int_firq_state; - elsif (irq = '1') and (cc(IBIT) = '0') then - iv_ctrl <= irq_iv; - next_state <= int_nmiirq_state; - else - -- Advance the PC to fetch next instruction byte - iv_ctrl <= reset_iv; -- default to reset - pc_ctrl <= incr_pc; - next_state <= decode1_state; - end if; - end if; - -- - -- Here to decode instruction - -- and fetch next byte of intruction - -- whether it be necessary or not - -- - when decode1_state => - -- fetch first byte of address or immediate data - ea_ctrl <= fetch_first_ea; - md_ctrl <= fetch_first_md; - addr_ctrl <= fetch_ad; - case op_code(7 downto 4) is - -- - -- direct single op (2 bytes) - -- 6809 => 6 cycles - -- cpu09 => 5 cycles - -- 1 op=(pc) / pc=pc+1 - -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1 - -- 3 md_lo=(ea) / pc=pc - -- 4 alu_left=md / md=alu_out / pc=pc - -- 5 (ea)=md_lo / pc=pc - -- - -- Exception is JMP - -- 6809 => 3 cycles - -- cpu09 => 3 cycles - -- 1 op=(pc) / pc=pc+1 - -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1 - -- 3 pc=ea - -- - when "0000" => - -- advance the PC - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "1110" => -- jmp - next_state <= jmp_state; - when "1111" => -- clr - next_state <= single_op_exec_state; - when others => - next_state <= single_op_read_state; - end case; - - -- acca / accb inherent instructions - when "0001" => - case op_code(3 downto 0) is - -- - -- Page2 pre byte - -- pre=(pc) / pc=pc+1 - -- op=(pc) / pc=pc+1 - -- - when "0000" => -- page2 - op_ctrl <= fetch_op; - -- advance pc - pc_ctrl <= incr_pc; - next_state <= decode2_state; - - -- - -- Page3 pre byte - -- pre=(pc) / pc=pc+1 - -- op=(pc) / pc=pc+1 - -- - when "0001" => -- page3 - op_ctrl <= fetch_op; - -- advance pc - pc_ctrl <= incr_pc; - next_state <= decode3_state; - - -- - -- nop - No operation ( 1 byte ) - -- 6809 => 2 cycles - -- cpu09 => 2 cycles - -- 1 op=(pc) / pc=pc+1 - -- 2 decode - -- - when "0010" => -- nop - next_state <= fetch_state; - - -- - -- sync - halt execution until an interrupt is received - -- interrupt may be NMI, IRQ or FIRQ - -- program execution continues if the - -- interrupt is asserted for 3 clock cycles - -- note that registers are not pushed onto the stack - -- CPU09 => Interrupts need only be asserted for one clock cycle - -- - when "0011" => -- sync - next_state <= sync_state; - - -- - -- lbra -- long branch (3 bytes) - -- 6809 => 5 cycles - -- cpu09 => 4 cycles - -- 1 op=(pc) / pc=pc+1 - -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 - -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1 - -- 4 pc=pc+md - -- - when "0110" => - -- increment the pc - pc_ctrl <= incr_pc; - next_state <= lbranch_state; - - -- - -- lbsr - long branch to subroutine (3 bytes) - -- 6809 => 9 cycles - -- cpu09 => 6 cycles - -- 1 op=(pc) /pc=pc+1 - -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1 - -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1 - -- 4 (sp)= pc_lo / sp=sp-1 / pc=pc - -- 5 (sp)=pc_hi / pc=pc - -- 6 pc=pc+md - -- - when "0111" => - -- pre decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- increment the pc - pc_ctrl <= incr_pc; - next_state <= lbranch_state; - - when "1001" => -- daa - left_ctrl <= acca_left; - right_ctrl <= accb_right; - alu_ctrl <= alu_daa; - cc_ctrl <= load_cc; - acca_ctrl <= load_acca; - next_state <= fetch_state; - - when "1010" => -- orcc - -- increment the pc - pc_ctrl <= incr_pc; - st_ctrl <= push_st; - return_state <= fetch_state; - next_state <= orcc_state; - - when "1100" => -- andcc - -- increment the pc - pc_ctrl <= incr_pc; - st_ctrl <= push_st; - return_state <= fetch_state; - next_state <= andcc_state; - - when "1101" => -- sex - -- have sex - left_ctrl <= accb_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_sex; - cc_ctrl <= load_cc; - acca_ctrl <= load_hi_acca; - next_state <= fetch_state; - - when "1110" => -- exg - -- increment the pc - pc_ctrl <= incr_pc; - next_state <= exg_state; - - when "1111" => -- tfr - -- increment the pc - pc_ctrl <= incr_pc; - -- call transfer as a subroutine - st_ctrl <= push_st; - return_state <= fetch_state; - next_state <= tfr_state; - - when others => - -- increment the pc - pc_ctrl <= incr_pc; - next_state <= fetch_state; - end case; - -- - -- Short branch conditional - -- 6809 => always 3 cycles - -- cpu09 => always = 3 cycles - -- 1 op=(pc) / pc=pc+1 - -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc - -- 3 if cc tru pc=pc+md else pc=pc - -- - when "0010" => -- branch conditional - -- increment the pc - pc_ctrl <= incr_pc; - next_state <= sbranch_state; - -- - -- Single byte stack operators - -- Do not advance PC - -- - when "0011" => - -- - -- lea - load effective address (2+ bytes) - -- 6809 => 4 cycles + addressing mode - -- cpu09 => 4 cycles + addressing mode - -- 1 op=(pc) / pc=pc+1 - -- 2 md_lo=(pc) / pc=pc+1 - -- 3 calculate ea - -- 4 ix/iy/sp/up = ea - -- - case op_code(3 downto 0) is - when "0000" | -- leax - "0001" | -- leay - "0010" | -- leas - "0011" => -- leau - -- advance PC - pc_ctrl <= incr_pc; - st_ctrl <= push_st; - return_state <= lea_state; - next_state <= indexed_state; - - -- - -- pshs - push registers onto sp stack - -- 6809 => 5 cycles + registers - -- cpu09 => 3 cycles + registers - -- 1 op=(pc) / pc=pc+1 - -- 2 ea_lo=(pc) / pc=pc+1 - -- 3 if ea(7 downto 0) != "00000000" then sp=sp-1 - -- 4 if ea(7) = 1 (sp)=pcl, sp=sp-1 - -- 5 if ea(7) = 1 (sp)=pch - -- if ea(6 downto 0) != "0000000" then sp=sp-1 - -- 6 if ea(6) = 1 (sp)=upl, sp=sp-1 - -- 7 if ea(6) = 1 (sp)=uph - -- if ea(5 downto 0) != "000000" then sp=sp-1 - -- 8 if ea(5) = 1 (sp)=iyl, sp=sp-1 - -- 9 if ea(5) = 1 (sp)=iyh - -- if ea(4 downto 0) != "00000" then sp=sp-1 - -- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1 - -- 11 if ea(4) = 1 (sp)=ixh - -- if ea(3 downto 0) != "0000" then sp=sp-1 - -- 12 if ea(3) = 1 (sp)=dp - -- if ea(2 downto 0) != "000" then sp=sp-1 - -- 13 if ea(2) = 1 (sp)=accb - -- if ea(1 downto 0) != "00" then sp=sp-1 - -- 14 if ea(1) = 1 (sp)=acca - -- if ea(0 downto 0) != "0" then sp=sp-1 - -- 15 if ea(0) = 1 (sp)=cc - -- - when "0100" => -- pshs - -- advance PC - pc_ctrl <= incr_pc; - next_state <= pshs_state; - - -- - -- puls - pull registers of sp stack - -- 6809 => 5 cycles + registers - -- cpu09 => 3 cycles + registers - -- - when "0101" => -- puls - -- advance PC - pc_ctrl <= incr_pc; - next_state <= puls_state; - - -- - -- pshu - push registers onto up stack - -- 6809 => 5 cycles + registers - -- cpu09 => 3 cycles + registers - -- - when "0110" => -- pshu - -- advance PC - pc_ctrl <= incr_pc; - next_state <= pshu_state; - - -- - -- pulu - pull registers of up stack - -- 6809 => 5 cycles + registers - -- cpu09 => 3 cycles + registers - -- - when "0111" => -- pulu - -- advance PC - pc_ctrl <= incr_pc; - next_state <= pulu_state; - - -- - -- rts - return from subroutine - -- 6809 => 5 cycles - -- cpu09 => 4 cycles - -- 1 op=(pc) / pc=pc+1 - -- 2 decode op - -- 3 pc_hi = (sp) / sp=sp+1 - -- 4 pc_lo = (sp) / sp=sp+1 - -- - when "1001" => - st_ctrl <= push_st; - return_state <= fetch_state; - next_state <= pull_return_hi_state; - - -- - -- add accb to index register - -- *** Note: this is an unsigned addition. - -- does not affect any condition codes - -- 6809 => 3 cycles - -- cpu09 => 2 cycles - -- 1 op=(pc) / pc=pc+1 - -- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc - -- - when "1010" => -- abx - left_ctrl <= ix_left; - right_ctrl <= accb_right; - alu_ctrl <= alu_abx; - ix_ctrl <= load_ix; - next_state <= fetch_state; - - when "1011" => -- rti - next_state <= rti_cc_state; - - when "1100" => -- cwai #$ - -- pre decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - iv_ctrl <= reset_iv; - -- increment pc - pc_ctrl <= incr_pc; - st_ctrl <= push_st; - return_state <= int_entire_state; -- set entire flag - next_state <= andcc_state; - - when "1101" => -- mul - next_state <= mul_state; - - when "1111" => -- swi - -- predecrement SP - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - iv_ctrl <= swi_iv; - next_state <= int_entire_state; - - when others => - next_state <= fetch_state; - - end case; - -- - -- Accumulator A Single operand - -- source = acca, dest = acca - -- Do not advance PC - -- Typically 2 cycles 1 bytes - -- 1 opcode fetch - -- 2 post byte fetch / instruction decode - -- Note that there is no post byte - -- so do not advance PC in decode cycle - -- Re-run opcode fetch cycle after decode - -- - when "0100" => -- acca single op - left_ctrl <= acca_left; - case op_code(3 downto 0) is - when "0000" => -- neg - right_ctrl <= zero_right; - alu_ctrl <= alu_neg; - acca_ctrl <= load_acca; - cc_ctrl <= load_cc; - when "0011" => -- com - right_ctrl <= zero_right; - alu_ctrl <= alu_com; - acca_ctrl <= load_acca; - cc_ctrl <= load_cc; - when "0100" => -- lsr - right_ctrl <= zero_right; - alu_ctrl <= alu_lsr8; - acca_ctrl <= load_acca; - cc_ctrl <= load_cc; - when "0110" => -- ror - right_ctrl <= zero_right; - alu_ctrl <= alu_ror8; - acca_ctrl <= load_acca; - cc_ctrl <= load_cc; - when "0111" => -- asr - right_ctrl <= zero_right; - alu_ctrl <= alu_asr8; - acca_ctrl <= load_acca; - cc_ctrl <= load_cc; - when "1000" => -- asl - right_ctrl <= zero_right; - alu_ctrl <= alu_asl8; - acca_ctrl <= load_acca; - cc_ctrl <= load_cc; - when "1001" => -- rol - right_ctrl <= zero_right; - alu_ctrl <= alu_rol8; - acca_ctrl <= load_acca; - cc_ctrl <= load_cc; - when "1010" => -- dec - right_ctrl <= one_right; - alu_ctrl <= alu_dec; - acca_ctrl <= load_acca; - cc_ctrl <= load_cc; - when "1011" => -- undefined - right_ctrl <= zero_right; - alu_ctrl <= alu_nop; - acca_ctrl <= latch_acca; - cc_ctrl <= latch_cc; - when "1100" => -- inc - right_ctrl <= one_right; - alu_ctrl <= alu_inc; - acca_ctrl <= load_acca; - cc_ctrl <= load_cc; - when "1101" => -- tst - right_ctrl <= zero_right; - alu_ctrl <= alu_st8; - acca_ctrl <= latch_acca; - cc_ctrl <= load_cc; - when "1110" => -- jmp (not defined) - right_ctrl <= zero_right; - alu_ctrl <= alu_nop; - acca_ctrl <= latch_acca; - cc_ctrl <= latch_cc; - when "1111" => -- clr - right_ctrl <= zero_right; - alu_ctrl <= alu_clr; - acca_ctrl <= load_acca; - cc_ctrl <= load_cc; - when others => - right_ctrl <= zero_right; - alu_ctrl <= alu_nop; - acca_ctrl <= latch_acca; - cc_ctrl <= latch_cc; - end case; - next_state <= fetch_state; - -- - -- Single Operand accb - -- source = accb, dest = accb - -- Typically 2 cycles 1 bytes - -- 1 opcode fetch - -- 2 post byte fetch / instruction decode - -- Note that there is no post byte - -- so do not advance PC in decode cycle - -- Re-run opcode fetch cycle after decode - -- - when "0101" => - left_ctrl <= accb_left; - case op_code(3 downto 0) is - when "0000" => -- neg - right_ctrl <= zero_right; - alu_ctrl <= alu_neg; - accb_ctrl <= load_accb; - cc_ctrl <= load_cc; - when "0011" => -- com - right_ctrl <= zero_right; - alu_ctrl <= alu_com; - accb_ctrl <= load_accb; - cc_ctrl <= load_cc; - when "0100" => -- lsr - right_ctrl <= zero_right; - alu_ctrl <= alu_lsr8; - accb_ctrl <= load_accb; - cc_ctrl <= load_cc; - when "0110" => -- ror - right_ctrl <= zero_right; - alu_ctrl <= alu_ror8; - accb_ctrl <= load_accb; - cc_ctrl <= load_cc; - when "0111" => -- asr - right_ctrl <= zero_right; - alu_ctrl <= alu_asr8; - accb_ctrl <= load_accb; - cc_ctrl <= load_cc; - when "1000" => -- asl - right_ctrl <= zero_right; - alu_ctrl <= alu_asl8; - accb_ctrl <= load_accb; - cc_ctrl <= load_cc; - when "1001" => -- rol - right_ctrl <= zero_right; - alu_ctrl <= alu_rol8; - accb_ctrl <= load_accb; - cc_ctrl <= load_cc; - when "1010" => -- dec - right_ctrl <= one_right; - alu_ctrl <= alu_dec; - accb_ctrl <= load_accb; - cc_ctrl <= load_cc; - when "1011" => -- undefined - right_ctrl <= zero_right; - alu_ctrl <= alu_nop; - accb_ctrl <= latch_accb; - cc_ctrl <= latch_cc; - when "1100" => -- inc - right_ctrl <= one_right; - alu_ctrl <= alu_inc; - accb_ctrl <= load_accb; - cc_ctrl <= load_cc; - when "1101" => -- tst - right_ctrl <= zero_right; - alu_ctrl <= alu_st8; - accb_ctrl <= latch_accb; - cc_ctrl <= load_cc; - when "1110" => -- jmp (undefined) - right_ctrl <= zero_right; - alu_ctrl <= alu_nop; - accb_ctrl <= latch_accb; - cc_ctrl <= latch_cc; - when "1111" => -- clr - right_ctrl <= zero_right; - alu_ctrl <= alu_clr; - accb_ctrl <= load_accb; - cc_ctrl <= load_cc; - when others => - right_ctrl <= zero_right; - alu_ctrl <= alu_nop; - accb_ctrl <= latch_accb; - cc_ctrl <= latch_cc; - end case; - next_state <= fetch_state; - -- - -- Single operand indexed - -- Two byte instruction so advance PC - -- EA should hold index offset - -- - when "0110" => -- indexed single op - -- increment the pc - pc_ctrl <= incr_pc; - st_ctrl <= push_st; - case op_code(3 downto 0) is - when "1110" => -- jmp - return_state <= jmp_state; - when "1111" => -- clr - return_state <= single_op_exec_state; - when others => - return_state <= single_op_read_state; - end case; - next_state <= indexed_state; - -- - -- Single operand extended addressing - -- three byte instruction so advance the PC - -- Low order EA holds high order address - -- - when "0111" => -- extended single op - -- increment PC - pc_ctrl <= incr_pc; - st_ctrl <= push_st; - case op_code(3 downto 0) is - when "1110" => -- jmp - return_state <= jmp_state; - when "1111" => -- clr - return_state <= single_op_exec_state; - when others => - return_state <= single_op_read_state; - end case; - next_state <= extended_state; - - when "1000" => -- acca immediate - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- subd # - "1100" | -- cmpx # - "1110" => -- ldx # - st_ctrl <= push_st; - return_state <= fetch_state; - next_state <= imm16_state; - - -- - -- bsr offset - Branch to subroutine (2 bytes) - -- 6809 => 7 cycles - -- cpu09 => 5 cycles - -- 1 op=(pc) / pc=pc+1 - -- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1 - -- 3 (sp)=pc_lo / sp=sp-1 - -- 4 (sp)=pc_hi - -- 5 pc=pc+md - -- - when "1101" => -- bsr - -- pre decrement SP - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- - st_ctrl <= push_st; - return_state <= sbranch_state; - next_state <= push_return_lo_state; - - when others => - next_state <= fetch_state; - end case; - - when "1001" => -- acca direct - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- subd - "1100" | -- cmpx - "1110" => -- ldx - next_state <= dual_op_read16_state; - - when "0111" => -- sta direct - next_state <= dual_op_write8_state; - - when "1111" => -- stx direct - -- idle ALU - left_ctrl <= ix_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_nop; - cc_ctrl <= latch_cc; - sp_ctrl <= latch_sp; - next_state <= dual_op_write16_state; - - -- - -- jsr direct - Jump to subroutine in direct page (2 bytes) - -- 6809 => 7 cycles - -- cpu09 => 5 cycles - -- 1 op=(pc) / pc=pc+1 - -- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1 - -- 3 (sp)=pc_lo / sp=sp-1 - -- 4 (sp)=pc_hi - -- 5 pc=ea - -- - when "1101" => -- jsr direct - -- pre decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- - st_ctrl <= push_st; - return_state <= jmp_state; - next_state <= push_return_lo_state; - - when others => - next_state <= dual_op_read8_state; - end case; - - when "1010" => -- acca indexed - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- subd - "1100" | -- cmpx - "1110" => -- ldx - st_ctrl <= push_st; - return_state <= dual_op_read16_state; - next_state <= indexed_state; - - when "0111" => -- staa ,x - st_ctrl <= push_st; - return_state <= dual_op_write8_state; - next_state <= indexed_state; - - when "1111" => -- stx ,x - st_ctrl <= push_st; - return_state <= dual_op_write16_state; - next_state <= indexed_state; - - when "1101" => -- jsr ,x - -- DO NOT pre decrement SP - st_ctrl <= push_st; - return_state <= jsr_state; - next_state <= indexed_state; - - when others => - st_ctrl <= push_st; - return_state <= dual_op_read8_state; - next_state <= indexed_state; - end case; - - when "1011" => -- acca extended - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- subd - "1100" | -- cmpx - "1110" => -- ldx - st_ctrl <= push_st; - return_state <= dual_op_read16_state; - next_state <= extended_state; - - when "0111" => -- staa > - st_ctrl <= push_st; - return_state <= dual_op_write8_state; - next_state <= extended_state; - - when "1111" => -- stx > - st_ctrl <= push_st; - return_state <= dual_op_write16_state; - next_state <= extended_state; - - when "1101" => -- jsr >extended - -- DO NOT pre decrement sp - st_ctrl <= push_st; - return_state <= jsr_state; - next_state <= extended_state; - - when others => - st_ctrl <= push_st; - return_state <= dual_op_read8_state; - next_state <= extended_state; - end case; - - when "1100" => -- accb immediate - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- addd # - "1100" | -- ldd # - "1110" => -- ldu # - st_ctrl <= push_st; - return_state <= fetch_state; - next_state <= imm16_state; - - when others => - next_state <= fetch_state; - - end case; - - - when "1101" => -- accb direct - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- addd - "1100" | -- ldd - "1110" => -- ldu - next_state <= dual_op_read16_state; - - when "0111" => -- stab direct - next_state <= dual_op_write8_state; - - when "1101" => -- std direct - next_state <= dual_op_write16_state; - - when "1111" => -- stu direct - next_state <= dual_op_write16_state; - - when others => - next_state <= dual_op_read8_state; - end case; - - when "1110" => -- accb indexed - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- addd - "1100" | -- ldd - "1110" => -- ldu - st_ctrl <= push_st; - return_state <= dual_op_read16_state; - next_state <= indexed_state; - - when "0111" => -- stab indexed - st_ctrl <= push_st; - return_state <= dual_op_write8_state; - next_state <= indexed_state; - - when "1101" => -- std indexed - st_ctrl <= push_st; - return_state <= dual_op_write16_state; - next_state <= indexed_state; - - when "1111" => -- stu indexed - st_ctrl <= push_st; - return_state <= dual_op_write16_state; - next_state <= indexed_state; - - when others => - st_ctrl <= push_st; - return_state <= dual_op_read8_state; - next_state <= indexed_state; - end case; - - when "1111" => -- accb extended - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- addd - "1100" | -- ldd - "1110" => -- ldu - st_ctrl <= push_st; - return_state <= dual_op_read16_state; - next_state <= extended_state; - - when "0111" => -- stab extended - st_ctrl <= push_st; - return_state <= dual_op_write8_state; - next_state <= extended_state; - - when "1101" => -- std extended - st_ctrl <= push_st; - return_state <= dual_op_write16_state; - next_state <= extended_state; - - when "1111" => -- stu extended - st_ctrl <= push_st; - return_state <= dual_op_write16_state; - next_state <= extended_state; - - when others => - st_ctrl <= push_st; - return_state <= dual_op_read8_state; - next_state <= extended_state; - end case; - - when others => - null; - end case; - - -- - -- Here to decode prefix 2 instruction - -- and fetch next byte of intruction - -- whether it be necessary or not - -- - when decode2_state => - -- fetch first byte of address or immediate data - ea_ctrl <= fetch_first_ea; - md_ctrl <= fetch_first_md; - addr_ctrl <= fetch_ad; - case op_code(7 downto 4) is - -- - -- lbcc -- long branch conditional - -- 6809 => branch 6 cycles, no branch 5 cycles - -- cpu09 => always 5 cycles - -- 1 pre=(pc) / pc=pc+1 - -- 2 op=(pc) / pc=pc+1 - -- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 - -- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1 - -- 5 if cond pc=pc+md else pc=pc - -- - when "0010" => - -- increment the pc - pc_ctrl <= incr_pc; - next_state <= lbranch_state; - - -- - -- Single byte stack operators - -- Do not advance PC - -- - when "0011" => - case op_code(3 downto 0) is - when "1111" => -- swi 2 - -- predecrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - iv_ctrl <= swi2_iv; - next_state <= int_entire_state; - - when others => - next_state <= fetch_state; - end case; - - when "1000" => -- acca immediate - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- cmpd # - "1100" | -- cmpy # - "1110" => -- ldy # - st_ctrl <= push_st; - return_state <= fetch_state; - next_state <= imm16_state; - - when others => - next_state <= fetch_state; - - end case; - - when "1001" => -- acca direct - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- cmpd < - "1100" | -- cmpy < - "1110" => -- ldy < - next_state <= dual_op_read16_state; - - when "1111" => -- sty < - next_state <= dual_op_write16_state; - - when others => - next_state <= fetch_state; - - end case; - - when "1010" => -- acca indexed - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- cmpd ,ind - "1100" | -- cmpy ,ind - "1110" => -- ldy ,ind - st_ctrl <= push_st; - return_state <= dual_op_read16_state; - next_state <= indexed_state; - - when "1111" => -- sty ,ind - st_ctrl <= push_st; - return_state <= dual_op_write16_state; - next_state <= indexed_state; - - when others => - next_state <= fetch_state; - end case; - - when "1011" => -- acca extended - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- cmpd < - "1100" | -- cmpy < - "1110" => -- ldy < - st_ctrl <= push_st; - return_state <= dual_op_read16_state; - next_state <= extended_state; - - when "1111" => -- sty > - st_ctrl <= push_st; - return_state <= dual_op_write16_state; - next_state <= extended_state; - - when others => - next_state <= fetch_state; - - end case; - - when "1100" => -- accb immediate - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- undef # - "1100" | -- undef # - "1110" => -- lds # - st_ctrl <= push_st; - return_state <= fetch_state; - next_state <= imm16_state; - - when others => - next_state <= fetch_state; - - end case; - - when "1101" => -- accb direct - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- undef < - "1100" | -- undef < - "1110" => -- lds < - next_state <= dual_op_read16_state; - - when "1111" => -- sts < - next_state <= dual_op_write16_state; - - when others => - next_state <= fetch_state; - - end case; - - when "1110" => -- accb indexed - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- undef ,ind - "1100" | -- undef ,ind - "1110" => -- lds ,ind - st_ctrl <= push_st; - return_state <= dual_op_read16_state; - next_state <= indexed_state; - - when "1111" => -- sts ,ind - st_ctrl <= push_st; - return_state <= dual_op_write16_state; - next_state <= indexed_state; - - when others => - next_state <= fetch_state; - - end case; - - when "1111" => -- accb extended - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- undef > - "1100" | -- undef > - "1110" => -- lds > - st_ctrl <= push_st; - return_state <= dual_op_read16_state; - next_state <= extended_state; - - when "1111" => -- sts > - st_ctrl <= push_st; - return_state <= dual_op_write16_state; - next_state <= extended_state; - - when others => - next_state <= fetch_state; - end case; - - when others => - next_state <= fetch_state; - end case; - -- - -- Here to decode instruction - -- and fetch next byte of intruction - -- whether it be necessary or not - -- - when decode3_state => - ea_ctrl <= fetch_first_ea; - md_ctrl <= fetch_first_md; - addr_ctrl <= fetch_ad; - dout_ctrl <= md_lo_dout; - case op_code(7 downto 4) is - -- - -- Single byte stack operators - -- Do not advance PC - -- - when "0011" => - case op_code(3 downto 0) is - when "1111" => -- swi3 - -- predecrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - iv_ctrl <= swi3_iv; - next_state <= int_entire_state; - when others => - next_state <= fetch_state; - end case; - - when "1000" => -- acca immediate - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- cmpu # - "1100" | -- cmps # - "1110" => -- undef # - st_ctrl <= push_st; - return_state <= fetch_state; - next_state <= imm16_state; - when others => - next_state <= fetch_state; - end case; - - when "1001" => -- acca direct - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- cmpu < - "1100" | -- cmps < - "1110" => -- undef < - st_ctrl <= idle_st; - return_state <= fetch_state; - next_state <= dual_op_read16_state; - - when others => - next_state <= fetch_state; - - end case; - - when "1010" => -- acca indexed - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- cmpu ,X - "1100" | -- cmps ,X - "1110" => -- undef ,X - st_ctrl <= push_st; - return_state <= dual_op_read16_state; - next_state <= indexed_state; - - when others => - next_state <= fetch_state; - - end case; - - when "1011" => -- acca extended - -- increment the pc - pc_ctrl <= incr_pc; - case op_code(3 downto 0) is - when "0011" | -- cmpu > - "1100" | -- cmps > - "1110" => -- undef > - st_ctrl <= push_st; - return_state <= dual_op_read16_state; - next_state <= extended_state; - when others => - next_state <= fetch_state; - end case; - - when others => - next_state <= fetch_state; - end case; - - -- - -- here if ea holds low byte - -- Direct - -- Extended - -- Indexed - -- read memory location - -- - when single_op_read_state => - -- read memory into md - md_ctrl <= fetch_first_md; - addr_ctrl <= read_ad; - dout_ctrl <= md_lo_dout; - next_state <= single_op_exec_state; - - when single_op_exec_state => - case op_code(3 downto 0) is - when "0000" => -- neg - left_ctrl <= md_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_neg; - cc_ctrl <= load_cc; - md_ctrl <= load_md; - next_state <= single_op_write_state; - when "0011" => -- com - left_ctrl <= md_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_com; - cc_ctrl <= load_cc; - md_ctrl <= load_md; - next_state <= single_op_write_state; - when "0100" => -- lsr - left_ctrl <= md_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_lsr8; - cc_ctrl <= load_cc; - md_ctrl <= load_md; - next_state <= single_op_write_state; - when "0110" => -- ror - left_ctrl <= md_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_ror8; - cc_ctrl <= load_cc; - md_ctrl <= load_md; - next_state <= single_op_write_state; - when "0111" => -- asr - left_ctrl <= md_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_asr8; - cc_ctrl <= load_cc; - md_ctrl <= load_md; - next_state <= single_op_write_state; - when "1000" => -- asl - left_ctrl <= md_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_asl8; - cc_ctrl <= load_cc; - md_ctrl <= load_md; - next_state <= single_op_write_state; - when "1001" => -- rol - left_ctrl <= md_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_rol8; - cc_ctrl <= load_cc; - md_ctrl <= load_md; - next_state <= single_op_write_state; - when "1010" => -- dec - left_ctrl <= md_left; - right_ctrl <= one_right; - alu_ctrl <= alu_dec; - cc_ctrl <= load_cc; - md_ctrl <= load_md; - next_state <= single_op_write_state; - when "1011" => -- undefined - next_state <= fetch_state; - when "1100" => -- inc - left_ctrl <= md_left; - right_ctrl <= one_right; - alu_ctrl <= alu_inc; - cc_ctrl <= load_cc; - md_ctrl <= load_md; - next_state <= single_op_write_state; - when "1101" => -- tst - left_ctrl <= md_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_st8; - cc_ctrl <= load_cc; - next_state <= fetch_state; - when "1110" => -- jmp - left_ctrl <= md_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_ld16; - pc_ctrl <= load_pc; - next_state <= fetch_state; - when "1111" => -- clr - left_ctrl <= md_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_clr; - cc_ctrl <= load_cc; - md_ctrl <= load_md; - next_state <= single_op_write_state; - when others => - next_state <= fetch_state; - end case; - -- - -- single operand 8 bit write - -- Write low 8 bits of ALU output - -- EA holds address - -- MD holds data - -- - when single_op_write_state => - -- write ALU low byte output - addr_ctrl <= write_ad; - dout_ctrl <= md_lo_dout; - next_state <= fetch_state; - - -- - -- here if ea holds address of low byte - -- read memory location - -- - when dual_op_read8_state => - -- read first data byte from ea - md_ctrl <= fetch_first_md; - addr_ctrl <= read_ad; - next_state <= fetch_state; - - -- - -- Here to read a 16 bit value into MD - -- pointed to by the EA register - -- The first byte is read - -- and the EA is incremented - -- - when dual_op_read16_state => - -- increment the effective address - left_ctrl <= ea_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - -- read the high byte of the 16 bit data - md_ctrl <= fetch_first_md; - addr_ctrl <= read_ad; - next_state <= dual_op_read16_2_state; - - -- - -- here to read the second byte - -- pointed to by EA into MD - -- - when dual_op_read16_2_state => - -- read the low byte of the 16 bit data - md_ctrl <= fetch_next_md; - addr_ctrl <= read_ad; - next_state <= fetch_state; - - -- - -- 16 bit Write state - -- EA hold address of memory to write to - -- Advance the effective address in ALU - -- decode op_code to determine which - -- register to write - -- - when dual_op_write16_state => - -- increment the effective address - left_ctrl <= ea_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - -- write the ALU hi byte at ea - addr_ctrl <= write_ad; - if op_code(6) = '0' then - case op_code(3 downto 0) is - when "1111" => -- stx / sty - case pre_code is - when "00010000" => -- page 2 -- sty - dout_ctrl <= iy_hi_dout; - when others => -- page 1 -- stx - dout_ctrl <= ix_hi_dout; - end case; - when others => - dout_ctrl <= md_hi_dout; - end case; - else - case op_code(3 downto 0) is - when "1101" => -- std - dout_ctrl <= acca_dout; -- acca is high byte of ACCD - when "1111" => -- stu / sts - case pre_code is - when "00010000" => -- page 2 -- sts - dout_ctrl <= sp_hi_dout; - when others => -- page 1 -- stu - dout_ctrl <= up_hi_dout; - end case; - when others => - dout_ctrl <= md_hi_dout; - end case; - end if; - next_state <= dual_op_write8_state; - - -- - -- Dual operand 8 bit write - -- Write 8 bit accumulator - -- or low byte of 16 bit register - -- EA holds address - -- decode opcode to determine - -- which register to apply to the bus - -- Also set the condition codes here - -- - when dual_op_write8_state => - if op_code(6) = '0' then - case op_code(3 downto 0) is - when "0111" => -- sta - dout_ctrl <= acca_dout; - when "1111" => -- stx / sty - case pre_code is - when "00010000" => -- page 2 -- sty - dout_ctrl <= iy_lo_dout; - when others => -- page 1 -- stx - dout_ctrl <= ix_lo_dout; - end case; - when others => - dout_ctrl <= md_lo_dout; - end case; - else - case op_code(3 downto 0) is - when "0111" => -- stb - dout_ctrl <= accb_dout; - when "1101" => -- std - dout_ctrl <= accb_dout; -- accb is low byte of accd - when "1111" => -- stu / sts - case pre_code is - when "00010000" => -- page 2 -- sts - dout_ctrl <= sp_lo_dout; - when others => -- page 1 -- stu - dout_ctrl <= up_lo_dout; - end case; - when others => - dout_ctrl <= md_lo_dout; - end case; - end if; - -- write ALU low byte output - addr_ctrl <= write_ad; - next_state <= fetch_state; - - -- - -- 16 bit immediate addressing mode - -- - when imm16_state => - -- increment pc - pc_ctrl <= incr_pc; - -- fetch next immediate byte - md_ctrl <= fetch_next_md; - addr_ctrl <= fetch_ad; - st_ctrl <= pull_st; - next_state <= saved_state; - - -- - -- md & ea holds 8 bit index offset - -- calculate the effective memory address - -- using the alu - -- - when indexed_state => - -- - -- decode indexing mode - -- - if md(7) = '0' then - case md(6 downto 5) is - when "00" => - left_ctrl <= ix_left; - when "01" => - left_ctrl <= iy_left; - when "10" => - left_ctrl <= up_left; - when others => - -- when "11" => - left_ctrl <= sp_left; - end case; - right_ctrl <= md_sign5_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - st_ctrl <= pull_st; - next_state <= saved_state; - - else - case md(3 downto 0) is - when "0000" => -- ,R+ - case md(6 downto 5) is - when "00" => - left_ctrl <= ix_left; - when "01" => - left_ctrl <= iy_left; - when "10" => - left_ctrl <= up_left; - when others => - left_ctrl <= sp_left; - end case; - -- - right_ctrl <= zero_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - next_state <= postincr1_state; - - when "0001" => -- ,R++ - case md(6 downto 5) is - when "00" => - left_ctrl <= ix_left; - when "01" => - left_ctrl <= iy_left; - when "10" => - left_ctrl <= up_left; - when others => - -- when "11" => - left_ctrl <= sp_left; - end case; - right_ctrl <= zero_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - next_state <= postincr2_state; - - when "0010" => -- ,-R - case md(6 downto 5) is - when "00" => - left_ctrl <= ix_left; - ix_ctrl <= load_ix; - when "01" => - left_ctrl <= iy_left; - iy_ctrl <= load_iy; - when "10" => - left_ctrl <= up_left; - up_ctrl <= load_up; - when others => - -- when "11" => - left_ctrl <= sp_left; - sp_ctrl <= load_sp; - end case; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - ea_ctrl <= load_ea; - st_ctrl <= pull_st; - next_state <= saved_state; - - when "0011" => -- ,--R - case md(6 downto 5) is - when "00" => - left_ctrl <= ix_left; - ix_ctrl <= load_ix; - when "01" => - left_ctrl <= iy_left; - iy_ctrl <= load_iy; - when "10" => - left_ctrl <= up_left; - up_ctrl <= load_up; - when others => - -- when "11" => - left_ctrl <= sp_left; - sp_ctrl <= load_sp; - end case; - right_ctrl <= two_right; - alu_ctrl <= alu_sub16; - ea_ctrl <= load_ea; - if md(4) = '0' then - st_ctrl <= pull_st; - next_state <= saved_state; - else - next_state <= indirect_state; - end if; - - when "0100" => -- ,R (zero offset) - case md(6 downto 5) is - when "00" => - left_ctrl <= ix_left; - when "01" => - left_ctrl <= iy_left; - when "10" => - left_ctrl <= up_left; - when others => - -- when "11" => - left_ctrl <= sp_left; - end case; - right_ctrl <= zero_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - if md(4) = '0' then - st_ctrl <= pull_st; - next_state <= saved_state; - else - next_state <= indirect_state; - end if; - - when "0101" => -- ACCB,R - case md(6 downto 5) is - when "00" => - left_ctrl <= ix_left; - when "01" => - left_ctrl <= iy_left; - when "10" => - left_ctrl <= up_left; - when others => - -- when "11" => - left_ctrl <= sp_left; - end case; - right_ctrl <= accb_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - if md(4) = '0' then - st_ctrl <= pull_st; - next_state <= saved_state; - else - next_state <= indirect_state; - end if; - - when "0110" => -- ACCA,R - case md(6 downto 5) is - when "00" => - left_ctrl <= ix_left; - when "01" => - left_ctrl <= iy_left; - when "10" => - left_ctrl <= up_left; - when others => - -- when "11" => - left_ctrl <= sp_left; - end case; - right_ctrl <= acca_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - if md(4) = '0' then - st_ctrl <= pull_st; - next_state <= saved_state; - else - next_state <= indirect_state; - end if; - - when "0111" => -- undefined - case md(6 downto 5) is - when "00" => - left_ctrl <= ix_left; - when "01" => - left_ctrl <= iy_left; - when "10" => - left_ctrl <= up_left; - when others => - -- when "11" => - left_ctrl <= sp_left; - end case; - right_ctrl <= zero_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - if md(4) = '0' then - st_ctrl <= pull_st; - next_state <= saved_state; - else - next_state <= indirect_state; - end if; - - when "1000" => -- offset8,R - md_ctrl <= fetch_first_md; -- pick up 8 bit offset - addr_ctrl <= fetch_ad; - pc_ctrl <= incr_pc; - next_state <= index8_state; - - when "1001" => -- offset16,R - md_ctrl <= fetch_first_md; -- pick up first byte of 16 bit offset - addr_ctrl <= fetch_ad; - pc_ctrl <= incr_pc; - next_state <= index16_state; - - when "1010" => -- undefined - case md(6 downto 5) is - when "00" => - left_ctrl <= ix_left; - when "01" => - left_ctrl <= iy_left; - when "10" => - left_ctrl <= up_left; - when others => - -- when "11" => - left_ctrl <= sp_left; - end case; - right_ctrl <= zero_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - -- - if md(4) = '0' then - st_ctrl <= pull_st; - next_state <= saved_state; - else - next_state <= indirect_state; - end if; - - when "1011" => -- ACCD,R - case md(6 downto 5) is - when "00" => - left_ctrl <= ix_left; - when "01" => - left_ctrl <= iy_left; - when "10" => - left_ctrl <= up_left; - when others => - -- when "11" => - left_ctrl <= sp_left; - end case; - right_ctrl <= accd_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - if md(4) = '0' then - st_ctrl <= pull_st; - next_state <= saved_state; - else - next_state <= indirect_state; - end if; - - when "1100" => -- offset8,PC - -- fetch 8 bit offset - md_ctrl <= fetch_first_md; - addr_ctrl <= fetch_ad; - pc_ctrl <= incr_pc; - next_state <= pcrel8_state; - - when "1101" => -- offset16,PC - -- fetch offset - md_ctrl <= fetch_first_md; - addr_ctrl <= fetch_ad; - pc_ctrl <= incr_pc; - next_state <= pcrel16_state; - - when "1110" => -- undefined - case md(6 downto 5) is - when "00" => - left_ctrl <= ix_left; - when "01" => - left_ctrl <= iy_left; - when "10" => - left_ctrl <= up_left; - when others => - -- when "11" => - left_ctrl <= sp_left; - end case; - right_ctrl <= zero_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - if md(4) = '0' then - st_ctrl <= pull_st; - next_state <= saved_state; - else - next_state <= indirect_state; - end if; - - when others => --- when "1111" => -- [,address] - -- advance PC to pick up address - md_ctrl <= fetch_first_md; - addr_ctrl <= fetch_ad; - pc_ctrl <= incr_pc; - next_state <= indexaddr_state; - end case; - end if; - - -- load index register with ea plus one - when postincr1_state => - left_ctrl <= ea_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - case md(6 downto 5) is - when "00" => - ix_ctrl <= load_ix; - when "01" => - iy_ctrl <= load_iy; - when "10" => - up_ctrl <= load_up; - when others => - -- when "11" => - sp_ctrl <= load_sp; - end case; - -- return to previous state - if md(4) = '0' then - st_ctrl <= pull_st; - next_state <= saved_state; - else - next_state <= indirect_state; - end if; - - -- load index register with ea plus two - when postincr2_state => - -- increment register by two (address) - left_ctrl <= ea_left; - right_ctrl <= two_right; - alu_ctrl <= alu_add16; - case md(6 downto 5) is - when "00" => - ix_ctrl <= load_ix; - when "01" => - iy_ctrl <= load_iy; - when "10" => - up_ctrl <= load_up; - when others => - -- when "11" => - sp_ctrl <= load_sp; - end case; - -- return to previous state - if md(4) = '0' then - st_ctrl <= pull_st; - next_state <= saved_state; - else - next_state <= indirect_state; - end if; - -- - -- ea = index register + md (8 bit signed offset) - -- ea holds post byte - -- - when index8_state => - case ea(6 downto 5) is - when "00" => - left_ctrl <= ix_left; - when "01" => - left_ctrl <= iy_left; - when "10" => - left_ctrl <= up_left; - when others => - -- when "11" => - left_ctrl <= sp_left; - end case; - -- ea = index reg + md - right_ctrl <= md_sign8_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - -- return to previous state - if ea(4) = '0' then - st_ctrl <= pull_st; - next_state <= saved_state; - else - next_state <= indirect_state; - end if; - - -- fetch low byte of 16 bit indexed offset - when index16_state => - -- advance pc - pc_ctrl <= incr_pc; - -- fetch low byte - md_ctrl <= fetch_next_md; - addr_ctrl <= fetch_ad; - next_state <= index16_2_state; - - -- ea = index register + md (16 bit offset) - -- ea holds post byte - when index16_2_state => - case ea(6 downto 5) is - when "00" => - left_ctrl <= ix_left; - when "01" => - left_ctrl <= iy_left; - when "10" => - left_ctrl <= up_left; - when others => - -- when "11" => - left_ctrl <= sp_left; - end case; - -- ea = index reg + md - right_ctrl <= md_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - -- return to previous state - if ea(4) = '0' then - st_ctrl <= pull_st; - next_state <= saved_state; - else - next_state <= indirect_state; - end if; - -- - -- pc relative with 8 bit signed offest - -- md holds signed offset - -- - when pcrel8_state => - -- ea = pc + signed md - left_ctrl <= pc_left; - right_ctrl <= md_sign8_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - -- return to previous state - if ea(4) = '0' then - st_ctrl <= pull_st; - next_state <= saved_state; - else - next_state <= indirect_state; - end if; - - -- pc relative addressing with 16 bit offset - -- pick up the low byte of the offset in md - -- advance the pc - when pcrel16_state => - -- advance pc - pc_ctrl <= incr_pc; - -- fetch low byte - md_ctrl <= fetch_next_md; - addr_ctrl <= fetch_ad; - next_state <= pcrel16_2_state; - - -- pc relative with16 bit signed offest - -- md holds signed offset - when pcrel16_2_state => - -- ea = pc + md - left_ctrl <= pc_left; - right_ctrl <= md_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - -- return to previous state - if ea(4) = '0' then - st_ctrl <= pull_st; - next_state <= saved_state; - else - next_state <= indirect_state; - end if; - - -- indexed to address - -- pick up the low byte of the address - -- advance the pc - when indexaddr_state => - -- advance pc - pc_ctrl <= incr_pc; - -- fetch low byte - md_ctrl <= fetch_next_md; - addr_ctrl <= fetch_ad; - next_state <= indexaddr2_state; - - -- indexed to absolute address - -- md holds address - -- ea hold indexing mode byte - when indexaddr2_state => - -- ea = md - left_ctrl <= pc_left; - right_ctrl <= md_right; - alu_ctrl <= alu_ld16; - ea_ctrl <= load_ea; - -- return to previous state - if ea(4) = '0' then - st_ctrl <= pull_st; - next_state <= saved_state; - else - next_state <= indirect_state; - end if; - - -- - -- load md with high byte of indirect address - -- pointed to by ea - -- increment ea - -- - when indirect_state => - -- increment ea - left_ctrl <= ea_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - ea_ctrl <= load_ea; - -- fetch high byte - md_ctrl <= fetch_first_md; - addr_ctrl <= read_ad; - next_state <= indirect2_state; - -- - -- load md with low byte of indirect address - -- pointed to by ea - -- ea has previously been incremented - -- - when indirect2_state => - -- fetch high byte - md_ctrl <= fetch_next_md; - addr_ctrl <= read_ad; - dout_ctrl <= md_lo_dout; - next_state <= indirect3_state; - -- - -- complete idirect addressing - -- by loading ea with md - -- - when indirect3_state => - -- load ea with md - left_ctrl <= ea_left; - right_ctrl <= md_right; - alu_ctrl <= alu_ld16; - ea_ctrl <= load_ea; - -- return to previous state - st_ctrl <= pull_st; - next_state <= saved_state; - - -- - -- ea holds the low byte of the absolute address - -- Move ea low byte into ea high byte - -- load new ea low byte to for absolute 16 bit address - -- advance the program counter - -- - when extended_state => -- fetch ea low byte - -- increment pc - pc_ctrl <= incr_pc; - -- fetch next effective address bytes - ea_ctrl <= fetch_next_ea; - addr_ctrl <= fetch_ad; - -- return to previous state - st_ctrl <= pull_st; - next_state <= saved_state; - - when lea_state => -- here on load effective address - -- load index register with effective address - left_ctrl <= pc_left; - right_ctrl <= ea_right; - alu_ctrl <= alu_lea; - case op_code(3 downto 0) is - when "0000" => -- leax - cc_ctrl <= load_cc; - ix_ctrl <= load_ix; - when "0001" => -- leay - cc_ctrl <= load_cc; - iy_ctrl <= load_iy; - when "0010" => -- leas - sp_ctrl <= load_sp; - when "0011" => -- leau - up_ctrl <= load_up; - when others => - null; - end case; - next_state <= fetch_state; - - -- - -- jump to subroutine - -- sp=sp-1 - -- call push_return_lo_state to save pc - -- return to jmp_state - -- - when jsr_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- call push_return_state - st_ctrl <= push_st; - return_state <= jmp_state; - next_state <= push_return_lo_state; - - -- - -- Load pc with ea - -- (JMP) - -- - when jmp_state => - -- load PC with effective address - left_ctrl <= pc_left; - right_ctrl <= ea_right; - alu_ctrl <= alu_ld16; - pc_ctrl <= load_pc; - next_state <= fetch_state; - - -- - -- long branch or branch to subroutine - -- pick up next md byte - -- md_hi = md_lo - -- md_lo = (pc) - -- pc=pc+1 - -- if a lbsr push return address - -- continue to sbranch_state - -- to evaluate conditional branches - -- - when lbranch_state => - pc_ctrl <= incr_pc; - -- fetch the next byte into md_lo - md_ctrl <= fetch_next_md; - addr_ctrl <= fetch_ad; - -- if lbsr - push return address - -- then continue on to short branch - if op_code = "00010111" then - st_ctrl <= push_st; - return_state <= sbranch_state; - next_state <= push_return_lo_state; - else - next_state <= sbranch_state; - end if; - - -- - -- here to execute conditional branch - -- short conditional branch md = signed 8 bit offset - -- long branch md = 16 bit offset - -- - when sbranch_state => - left_ctrl <= pc_left; - right_ctrl <= md_right; - alu_ctrl <= alu_add16; - -- Test condition for branch - if op_code(7 downto 4) = "0010" then -- conditional branch - case op_code(3 downto 0) is - when "0000" => -- bra - cond_true := (1 = 1); - when "0001" => -- brn - cond_true := (1 = 0); - when "0010" => -- bhi - cond_true := ((cc(CBIT) or cc(ZBIT)) = '0'); - when "0011" => -- bls - cond_true := ((cc(CBIT) or cc(ZBIT)) = '1'); - when "0100" => -- bcc/bhs - cond_true := (cc(CBIT) = '0'); - when "0101" => -- bcs/blo - cond_true := (cc(CBIT) = '1'); - when "0110" => -- bne - cond_true := (cc(ZBIT) = '0'); - when "0111" => -- beq - cond_true := (cc(ZBIT) = '1'); - when "1000" => -- bvc - cond_true := (cc(VBIT) = '0'); - when "1001" => -- bvs - cond_true := (cc(VBIT) = '1'); - when "1010" => -- bpl - cond_true := (cc(NBIT) = '0'); - when "1011" => -- bmi - cond_true := (cc(NBIT) = '1'); - when "1100" => -- bge - cond_true := ((cc(NBIT) xor cc(VBIT)) = '0'); - when "1101" => -- blt - cond_true := ((cc(NBIT) xor cc(VBIT)) = '1'); - when "1110" => -- bgt - cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0'); - when "1111" => -- ble - cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1'); - when others => - null; - end case; - else - cond_true := (1 = 1); -- lbra, lbsr, bsr - end if; - if cond_true then - pc_ctrl <= load_pc; - end if; - next_state <= fetch_state; - - -- - -- push return address onto the S stack - -- - -- (sp) = pc_lo - -- sp = sp - 1 - -- - when push_return_lo_state => - -- decrement the sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write PC low - addr_ctrl <= pushs_ad; - dout_ctrl <= pc_lo_dout; - next_state <= push_return_hi_state; - - -- - -- push program counter hi byte onto the stack - -- (sp) = pc_hi - -- sp = sp - -- return to originating state - -- - when push_return_hi_state => - -- write pc hi bytes - addr_ctrl <= pushs_ad; - dout_ctrl <= pc_hi_dout; - st_ctrl <= pull_st; - next_state <= saved_state; - - when pull_return_hi_state => - -- increment the sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read pc hi - pc_ctrl <= pull_hi_pc; - addr_ctrl <= pulls_ad; - next_state <= pull_return_lo_state; - - when pull_return_lo_state => - -- increment the SP - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read pc low - pc_ctrl <= pull_lo_pc; - addr_ctrl <= pulls_ad; - dout_ctrl <= pc_lo_dout; - -- - st_ctrl <= pull_st; - next_state <= saved_state; - - when andcc_state => - -- AND CC with md - left_ctrl <= md_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_andcc; - cc_ctrl <= load_cc; - -- - st_ctrl <= pull_st; - next_state <= saved_state; - - when orcc_state => - -- OR CC with md - left_ctrl <= md_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_orcc; - cc_ctrl <= load_cc; - -- - st_ctrl <= pull_st; - next_state <= saved_state; - - when tfr_state => - -- select source register - case md(7 downto 4) is - when "0000" => - left_ctrl <= accd_left; - when "0001" => - left_ctrl <= ix_left; - when "0010" => - left_ctrl <= iy_left; - when "0011" => - left_ctrl <= up_left; - when "0100" => - left_ctrl <= sp_left; - when "0101" => - left_ctrl <= pc_left; - when "1000" => - left_ctrl <= acca_left; - when "1001" => - left_ctrl <= accb_left; - when "1010" => - left_ctrl <= cc_left; - when "1011" => - left_ctrl <= dp_left; - when others => - left_ctrl <= md_left; - end case; - right_ctrl <= zero_right; - alu_ctrl <= alu_tfr; - -- select destination register - case md(3 downto 0) is - when "0000" => -- accd - acca_ctrl <= load_hi_acca; - accb_ctrl <= load_accb; - when "0001" => -- ix - ix_ctrl <= load_ix; - when "0010" => -- iy - iy_ctrl <= load_iy; - when "0011" => -- up - up_ctrl <= load_up; - when "0100" => -- sp - sp_ctrl <= load_sp; - when "0101" => -- pc - pc_ctrl <= load_pc; - when "1000" => -- acca - acca_ctrl <= load_acca; - when "1001" => -- accb - accb_ctrl <= load_accb; - when "1010" => -- cc - cc_ctrl <= load_cc; - when "1011" => --dp - dp_ctrl <= load_dp; - when others => - null; - end case; - -- - st_ctrl <= pull_st; - next_state <= saved_state; - - when exg_state => - -- save destination register - case md(3 downto 0) is - when "0000" => - left_ctrl <= accd_left; - when "0001" => - left_ctrl <= ix_left; - when "0010" => - left_ctrl <= iy_left; - when "0011" => - left_ctrl <= up_left; - when "0100" => - left_ctrl <= sp_left; - when "0101" => - left_ctrl <= pc_left; - when "1000" => - left_ctrl <= acca_left; - when "1001" => - left_ctrl <= accb_left; - when "1010" => - left_ctrl <= cc_left; - when "1011" => - left_ctrl <= dp_left; - when others => - left_ctrl <= md_left; - end case; - right_ctrl <= zero_right; - alu_ctrl <= alu_tfr; - ea_ctrl <= load_ea; - -- call tranfer microcode - st_ctrl <= push_st; - return_state <= exg1_state; - next_state <= tfr_state; - - when exg1_state => - -- restore destination - left_ctrl <= ea_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_tfr; - -- save as source register - case md(7 downto 4) is - when "0000" => -- accd - acca_ctrl <= load_hi_acca; - accb_ctrl <= load_accb; - when "0001" => -- ix - ix_ctrl <= load_ix; - when "0010" => -- iy - iy_ctrl <= load_iy; - when "0011" => -- up - up_ctrl <= load_up; - when "0100" => -- sp - sp_ctrl <= load_sp; - when "0101" => -- pc - pc_ctrl <= load_pc; - when "1000" => -- acca - acca_ctrl <= load_acca; - when "1001" => -- accb - accb_ctrl <= load_accb; - when "1010" => -- cc - cc_ctrl <= load_cc; - when "1011" => --dp - dp_ctrl <= load_dp; - when others => - null; - end case; - next_state <= fetch_state; - - when mul_state => - -- move acca to md - left_ctrl <= acca_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_st16; - md_ctrl <= load_md; - next_state <= mulea_state; - - when mulea_state => - -- move accb to ea - left_ctrl <= accb_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_st16; - ea_ctrl <= load_ea; - next_state <= muld_state; - - when muld_state => - -- clear accd - left_ctrl <= acca_left; - right_ctrl <= zero_right; - alu_ctrl <= alu_ld8; - acca_ctrl <= load_hi_acca; - accb_ctrl <= load_accb; - next_state <= mul0_state; - - when mul0_state => - -- if bit 0 of ea set, add accd to md - left_ctrl <= accd_left; - if ea(0) = '1' then - right_ctrl <= md_right; - else - right_ctrl <= zero_right; - end if; - alu_ctrl <= alu_mul; - cc_ctrl <= load_cc; - acca_ctrl <= load_hi_acca; - accb_ctrl <= load_accb; - md_ctrl <= shiftl_md; - next_state <= mul1_state; - - when mul1_state => - -- if bit 1 of ea set, add accd to md - left_ctrl <= accd_left; - if ea(1) = '1' then - right_ctrl <= md_right; - else - right_ctrl <= zero_right; - end if; - alu_ctrl <= alu_mul; - cc_ctrl <= load_cc; - acca_ctrl <= load_hi_acca; - accb_ctrl <= load_accb; - md_ctrl <= shiftl_md; - next_state <= mul2_state; - - when mul2_state => - -- if bit 2 of ea set, add accd to md - left_ctrl <= accd_left; - if ea(2) = '1' then - right_ctrl <= md_right; - else - right_ctrl <= zero_right; - end if; - alu_ctrl <= alu_mul; - cc_ctrl <= load_cc; - acca_ctrl <= load_hi_acca; - accb_ctrl <= load_accb; - md_ctrl <= shiftl_md; - next_state <= mul3_state; - - when mul3_state => - -- if bit 3 of ea set, add accd to md - left_ctrl <= accd_left; - if ea(3) = '1' then - right_ctrl <= md_right; - else - right_ctrl <= zero_right; - end if; - alu_ctrl <= alu_mul; - cc_ctrl <= load_cc; - acca_ctrl <= load_hi_acca; - accb_ctrl <= load_accb; - md_ctrl <= shiftl_md; - next_state <= mul4_state; - - when mul4_state => - -- if bit 4 of ea set, add accd to md - left_ctrl <= accd_left; - if ea(4) = '1' then - right_ctrl <= md_right; - else - right_ctrl <= zero_right; - end if; - alu_ctrl <= alu_mul; - cc_ctrl <= load_cc; - acca_ctrl <= load_hi_acca; - accb_ctrl <= load_accb; - md_ctrl <= shiftl_md; - next_state <= mul5_state; - - when mul5_state => - -- if bit 5 of ea set, add accd to md - left_ctrl <= accd_left; - if ea(5) = '1' then - right_ctrl <= md_right; - else - right_ctrl <= zero_right; - end if; - alu_ctrl <= alu_mul; - cc_ctrl <= load_cc; - acca_ctrl <= load_hi_acca; - accb_ctrl <= load_accb; - md_ctrl <= shiftl_md; - next_state <= mul6_state; - - when mul6_state => - -- if bit 6 of ea set, add accd to md - left_ctrl <= accd_left; - if ea(6) = '1' then - right_ctrl <= md_right; - else - right_ctrl <= zero_right; - end if; - alu_ctrl <= alu_mul; - cc_ctrl <= load_cc; - acca_ctrl <= load_hi_acca; - accb_ctrl <= load_accb; - md_ctrl <= shiftl_md; - next_state <= mul7_state; - - when mul7_state => - -- if bit 7 of ea set, add accd to md - left_ctrl <= accd_left; - if ea(7) = '1' then - right_ctrl <= md_right; - else - right_ctrl <= zero_right; - end if; - alu_ctrl <= alu_mul; - cc_ctrl <= load_cc; - acca_ctrl <= load_hi_acca; - accb_ctrl <= load_accb; - md_ctrl <= shiftl_md; - next_state <= fetch_state; - - -- - -- Enter here on pushs - -- ea holds post byte - -- - when pshs_state => - -- decrement sp if any registers to be pushed - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - -- idle address - addr_ctrl <= idle_ad; - dout_ctrl <= cc_dout; - if ea(7 downto 0) = "00000000" then - sp_ctrl <= latch_sp; - else - sp_ctrl <= load_sp; - end if; - if ea(7) = '1' then - next_state <= pshs_pcl_state; - elsif ea(6) = '1' then - next_state <= pshs_upl_state; - elsif ea(5) = '1' then - next_state <= pshs_iyl_state; - elsif ea(4) = '1' then - next_state <= pshs_ixl_state; - elsif ea(3) = '1' then - next_state <= pshs_dp_state; - elsif ea(2) = '1' then - next_state <= pshs_accb_state; - elsif ea(1) = '1' then - next_state <= pshs_acca_state; - elsif ea(0) = '1' then - next_state <= pshs_cc_state; - else - next_state <= fetch_state; - end if; - - when pshs_pcl_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write pc low - addr_ctrl <= pushs_ad; - dout_ctrl <= pc_lo_dout; - next_state <= pshs_pch_state; - - when pshs_pch_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - if ea(6 downto 0) = "0000000" then - sp_ctrl <= latch_sp; - else - sp_ctrl <= load_sp; - end if; - -- write pc hi - addr_ctrl <= pushs_ad; - dout_ctrl <= pc_hi_dout; - if ea(6) = '1' then - next_state <= pshs_upl_state; - elsif ea(5) = '1' then - next_state <= pshs_iyl_state; - elsif ea(4) = '1' then - next_state <= pshs_ixl_state; - elsif ea(3) = '1' then - next_state <= pshs_dp_state; - elsif ea(2) = '1' then - next_state <= pshs_accb_state; - elsif ea(1) = '1' then - next_state <= pshs_acca_state; - elsif ea(0) = '1' then - next_state <= pshs_cc_state; - else - next_state <= fetch_state; - end if; - - - when pshs_upl_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write pc low - addr_ctrl <= pushs_ad; - dout_ctrl <= up_lo_dout; - next_state <= pshs_uph_state; - - when pshs_uph_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - if ea(5 downto 0) = "000000" then - sp_ctrl <= latch_sp; - else - sp_ctrl <= load_sp; - end if; - -- write pc hi - addr_ctrl <= pushs_ad; - dout_ctrl <= up_hi_dout; - if ea(5) = '1' then - next_state <= pshs_iyl_state; - elsif ea(4) = '1' then - next_state <= pshs_ixl_state; - elsif ea(3) = '1' then - next_state <= pshs_dp_state; - elsif ea(2) = '1' then - next_state <= pshs_accb_state; - elsif ea(1) = '1' then - next_state <= pshs_acca_state; - elsif ea(0) = '1' then - next_state <= pshs_cc_state; - else - next_state <= fetch_state; - end if; - - when pshs_iyl_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write iy low - addr_ctrl <= pushs_ad; - dout_ctrl <= iy_lo_dout; - next_state <= pshs_iyh_state; - - when pshs_iyh_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - if ea(4 downto 0) = "00000" then - sp_ctrl <= latch_sp; - else - sp_ctrl <= load_sp; - end if; - -- write iy hi - addr_ctrl <= pushs_ad; - dout_ctrl <= iy_hi_dout; - if ea(4) = '1' then - next_state <= pshs_ixl_state; - elsif ea(3) = '1' then - next_state <= pshs_dp_state; - elsif ea(2) = '1' then - next_state <= pshs_accb_state; - elsif ea(1) = '1' then - next_state <= pshs_acca_state; - elsif ea(0) = '1' then - next_state <= pshs_cc_state; - else - next_state <= fetch_state; - end if; - - when pshs_ixl_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write ix low - addr_ctrl <= pushs_ad; - dout_ctrl <= ix_lo_dout; - next_state <= pshs_ixh_state; - - when pshs_ixh_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - if ea(3 downto 0) = "0000" then - sp_ctrl <= latch_sp; - else - sp_ctrl <= load_sp; - end if; - -- write ix hi - addr_ctrl <= pushs_ad; - dout_ctrl <= ix_hi_dout; - if ea(3) = '1' then - next_state <= pshs_dp_state; - elsif ea(2) = '1' then - next_state <= pshs_accb_state; - elsif ea(1) = '1' then - next_state <= pshs_acca_state; - elsif ea(0) = '1' then - next_state <= pshs_cc_state; - else - next_state <= fetch_state; - end if; - - when pshs_dp_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - if ea(2 downto 0) = "000" then - sp_ctrl <= latch_sp; - else - sp_ctrl <= load_sp; - end if; - -- write dp - addr_ctrl <= pushs_ad; - dout_ctrl <= dp_dout; - if ea(2) = '1' then - next_state <= pshs_accb_state; - elsif ea(1) = '1' then - next_state <= pshs_acca_state; - elsif ea(0) = '1' then - next_state <= pshs_cc_state; - else - next_state <= fetch_state; - end if; - - when pshs_accb_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - if ea(1 downto 0) = "00" then - sp_ctrl <= latch_sp; - else - sp_ctrl <= load_sp; - end if; - -- write accb - addr_ctrl <= pushs_ad; - dout_ctrl <= accb_dout; - if ea(1) = '1' then - next_state <= pshs_acca_state; - elsif ea(0) = '1' then - next_state <= pshs_cc_state; - else - next_state <= fetch_state; - end if; - - when pshs_acca_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - if ea(0) = '1' then - sp_ctrl <= load_sp; - else - sp_ctrl <= latch_sp; - end if; - -- write acca - addr_ctrl <= pushs_ad; - dout_ctrl <= acca_dout; - if ea(0) = '1' then - next_state <= pshs_cc_state; - else - next_state <= fetch_state; - end if; - - when pshs_cc_state => - -- idle sp - -- write cc - addr_ctrl <= pushs_ad; - dout_ctrl <= cc_dout; - next_state <= fetch_state; - - -- - -- enter here on PULS - -- ea hold register mask - -- - when puls_state => - if ea(0) = '1' then - next_state <= puls_cc_state; - elsif ea(1) = '1' then - next_state <= puls_acca_state; - elsif ea(2) = '1' then - next_state <= puls_accb_state; - elsif ea(3) = '1' then - next_state <= puls_dp_state; - elsif ea(4) = '1' then - next_state <= puls_ixh_state; - elsif ea(5) = '1' then - next_state <= puls_iyh_state; - elsif ea(6) = '1' then - next_state <= puls_uph_state; - elsif ea(7) = '1' then - next_state <= puls_pch_state; - else - next_state <= fetch_state; - end if; - - when puls_cc_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read cc - cc_ctrl <= pull_cc; - addr_ctrl <= pulls_ad; - if ea(1) = '1' then - next_state <= puls_acca_state; - elsif ea(2) = '1' then - next_state <= puls_accb_state; - elsif ea(3) = '1' then - next_state <= puls_dp_state; - elsif ea(4) = '1' then - next_state <= puls_ixh_state; - elsif ea(5) = '1' then - next_state <= puls_iyh_state; - elsif ea(6) = '1' then - next_state <= puls_uph_state; - elsif ea(7) = '1' then - next_state <= puls_pch_state; - else - next_state <= fetch_state; - end if; - - when puls_acca_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read acca - acca_ctrl <= pull_acca; - addr_ctrl <= pulls_ad; - if ea(2) = '1' then - next_state <= puls_accb_state; - elsif ea(3) = '1' then - next_state <= puls_dp_state; - elsif ea(4) = '1' then - next_state <= puls_ixh_state; - elsif ea(5) = '1' then - next_state <= puls_iyh_state; - elsif ea(6) = '1' then - next_state <= puls_uph_state; - elsif ea(7) = '1' then - next_state <= puls_pch_state; - else - next_state <= fetch_state; - end if; - - when puls_accb_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read accb - accb_ctrl <= pull_accb; - addr_ctrl <= pulls_ad; - if ea(3) = '1' then - next_state <= puls_dp_state; - elsif ea(4) = '1' then - next_state <= puls_ixh_state; - elsif ea(5) = '1' then - next_state <= puls_iyh_state; - elsif ea(6) = '1' then - next_state <= puls_uph_state; - elsif ea(7) = '1' then - next_state <= puls_pch_state; - else - next_state <= fetch_state; - end if; - - when puls_dp_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read dp - dp_ctrl <= pull_dp; - addr_ctrl <= pulls_ad; - if ea(4) = '1' then - next_state <= puls_ixh_state; - elsif ea(5) = '1' then - next_state <= puls_iyh_state; - elsif ea(6) = '1' then - next_state <= puls_uph_state; - elsif ea(7) = '1' then - next_state <= puls_pch_state; - else - next_state <= fetch_state; - end if; - - when puls_ixh_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- pull ix hi - ix_ctrl <= pull_hi_ix; - addr_ctrl <= pulls_ad; - next_state <= puls_ixl_state; - - when puls_ixl_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read ix low - ix_ctrl <= pull_lo_ix; - addr_ctrl <= pulls_ad; - if ea(5) = '1' then - next_state <= puls_iyh_state; - elsif ea(6) = '1' then - next_state <= puls_uph_state; - elsif ea(7) = '1' then - next_state <= puls_pch_state; - else - next_state <= fetch_state; - end if; - - when puls_iyh_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- pull iy hi - iy_ctrl <= pull_hi_iy; - addr_ctrl <= pulls_ad; - next_state <= puls_iyl_state; - - when puls_iyl_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read iy low - iy_ctrl <= pull_lo_iy; - addr_ctrl <= pulls_ad; - if ea(6) = '1' then - next_state <= puls_uph_state; - elsif ea(7) = '1' then - next_state <= puls_pch_state; - else - next_state <= fetch_state; - end if; - - when puls_uph_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- pull up hi - up_ctrl <= pull_hi_up; - addr_ctrl <= pulls_ad; - next_state <= puls_upl_state; - - when puls_upl_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read up low - up_ctrl <= pull_lo_up; - addr_ctrl <= pulls_ad; - if ea(7) = '1' then - next_state <= puls_pch_state; - else - next_state <= fetch_state; - end if; - - when puls_pch_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- pull pc hi - pc_ctrl <= pull_hi_pc; - addr_ctrl <= pulls_ad; - next_state <= puls_pcl_state; - - when puls_pcl_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read pc low - pc_ctrl <= pull_lo_pc; - addr_ctrl <= pulls_ad; - next_state <= fetch_state; - - -- - -- Enter here on pshu - -- ea holds post byte - -- - when pshu_state => - -- decrement up if any registers to be pushed - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - if ea(7 downto 0) = "00000000" then - up_ctrl <= latch_up; - else - up_ctrl <= load_up; - end if; - -- write idle bus - if ea(7) = '1' then - next_state <= pshu_pcl_state; - elsif ea(6) = '1' then - next_state <= pshu_spl_state; - elsif ea(5) = '1' then - next_state <= pshu_iyl_state; - elsif ea(4) = '1' then - next_state <= pshu_ixl_state; - elsif ea(3) = '1' then - next_state <= pshu_dp_state; - elsif ea(2) = '1' then - next_state <= pshu_accb_state; - elsif ea(1) = '1' then - next_state <= pshu_acca_state; - elsif ea(0) = '1' then - next_state <= pshu_cc_state; - else - next_state <= fetch_state; - end if; - -- - -- push PC onto U stack - -- - when pshu_pcl_state => - -- decrement up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - up_ctrl <= load_up; - -- write pc low - addr_ctrl <= pushu_ad; - dout_ctrl <= pc_lo_dout; - next_state <= pshu_pch_state; - - when pshu_pch_state => - -- decrement up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - if ea(6 downto 0) = "0000000" then - up_ctrl <= latch_up; - else - up_ctrl <= load_up; - end if; - -- write pc hi - addr_ctrl <= pushu_ad; - dout_ctrl <= pc_hi_dout; - if ea(6) = '1' then - next_state <= pshu_spl_state; - elsif ea(5) = '1' then - next_state <= pshu_iyl_state; - elsif ea(4) = '1' then - next_state <= pshu_ixl_state; - elsif ea(3) = '1' then - next_state <= pshu_dp_state; - elsif ea(2) = '1' then - next_state <= pshu_accb_state; - elsif ea(1) = '1' then - next_state <= pshu_acca_state; - elsif ea(0) = '1' then - next_state <= pshu_cc_state; - else - next_state <= fetch_state; - end if; - - when pshu_spl_state => - -- decrement up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - up_ctrl <= load_up; - -- write sp low - addr_ctrl <= pushu_ad; - dout_ctrl <= sp_lo_dout; - next_state <= pshu_sph_state; - - when pshu_sph_state => - -- decrement up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - if ea(5 downto 0) = "000000" then - up_ctrl <= latch_up; - else - up_ctrl <= load_up; - end if; - -- write sp hi - addr_ctrl <= pushu_ad; - dout_ctrl <= sp_hi_dout; - if ea(5) = '1' then - next_state <= pshu_iyl_state; - elsif ea(4) = '1' then - next_state <= pshu_ixl_state; - elsif ea(3) = '1' then - next_state <= pshu_dp_state; - elsif ea(2) = '1' then - next_state <= pshu_accb_state; - elsif ea(1) = '1' then - next_state <= pshu_acca_state; - elsif ea(0) = '1' then - next_state <= pshu_cc_state; - else - next_state <= fetch_state; - end if; - - when pshu_iyl_state => - -- decrement up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - up_ctrl <= load_up; - -- write iy low - addr_ctrl <= pushu_ad; - dout_ctrl <= iy_lo_dout; - next_state <= pshu_iyh_state; - - when pshu_iyh_state => - -- decrement up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - if ea(4 downto 0) = "00000" then - up_ctrl <= latch_up; - else - up_ctrl <= load_up; - end if; - -- write iy hi - addr_ctrl <= pushu_ad; - dout_ctrl <= iy_hi_dout; - if ea(4) = '1' then - next_state <= pshu_ixl_state; - elsif ea(3) = '1' then - next_state <= pshu_dp_state; - elsif ea(2) = '1' then - next_state <= pshu_accb_state; - elsif ea(1) = '1' then - next_state <= pshu_acca_state; - elsif ea(0) = '1' then - next_state <= pshu_cc_state; - else - next_state <= fetch_state; - end if; - - when pshu_ixl_state => - -- decrement up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - up_ctrl <= load_up; - -- write ix low - addr_ctrl <= pushu_ad; - dout_ctrl <= ix_lo_dout; - next_state <= pshu_ixh_state; - - when pshu_ixh_state => - -- decrement up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - if ea(3 downto 0) = "0000" then - up_ctrl <= latch_up; - else - up_ctrl <= load_up; - end if; - -- write ix hi - addr_ctrl <= pushu_ad; - dout_ctrl <= ix_hi_dout; - if ea(3) = '1' then - next_state <= pshu_dp_state; - elsif ea(2) = '1' then - next_state <= pshu_accb_state; - elsif ea(1) = '1' then - next_state <= pshu_acca_state; - elsif ea(0) = '1' then - next_state <= pshu_cc_state; - else - next_state <= fetch_state; - end if; - - when pshu_dp_state => - -- decrement up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - if ea(2 downto 0) = "000" then - up_ctrl <= latch_up; - else - up_ctrl <= load_up; - end if; - -- write dp - addr_ctrl <= pushu_ad; - dout_ctrl <= dp_dout; - if ea(2) = '1' then - next_state <= pshu_accb_state; - elsif ea(1) = '1' then - next_state <= pshu_acca_state; - elsif ea(0) = '1' then - next_state <= pshu_cc_state; - else - next_state <= fetch_state; - end if; - - when pshu_accb_state => - -- decrement up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - if ea(1 downto 0) = "00" then - up_ctrl <= latch_up; - else - up_ctrl <= load_up; - end if; - -- write accb - addr_ctrl <= pushu_ad; - dout_ctrl <= accb_dout; - if ea(1) = '1' then - next_state <= pshu_acca_state; - elsif ea(0) = '1' then - next_state <= pshu_cc_state; - else - next_state <= fetch_state; - end if; - - when pshu_acca_state => - -- decrement up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - if ea(0) = '0' then - up_ctrl <= latch_up; - else - up_ctrl <= load_up; - end if; - -- write acca - addr_ctrl <= pushu_ad; - dout_ctrl <= acca_dout; - if ea(0) = '1' then - next_state <= pshu_cc_state; - else - next_state <= fetch_state; - end if; - - when pshu_cc_state => - -- idle up - -- write cc - addr_ctrl <= pushu_ad; - dout_ctrl <= cc_dout; - next_state <= fetch_state; - - -- - -- enter here on PULU - -- ea hold register mask - -- - when pulu_state => - -- idle UP - -- idle bus - if ea(0) = '1' then - next_state <= pulu_cc_state; - elsif ea(1) = '1' then - next_state <= pulu_acca_state; - elsif ea(2) = '1' then - next_state <= pulu_accb_state; - elsif ea(3) = '1' then - next_state <= pulu_dp_state; - elsif ea(4) = '1' then - next_state <= pulu_ixh_state; - elsif ea(5) = '1' then - next_state <= pulu_iyh_state; - elsif ea(6) = '1' then - next_state <= pulu_sph_state; - elsif ea(7) = '1' then - next_state <= pulu_pch_state; - else - next_state <= fetch_state; - end if; - - when pulu_cc_state => - -- increment up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - up_ctrl <= load_up; - -- read cc - cc_ctrl <= pull_cc; - addr_ctrl <= pullu_ad; - if ea(1) = '1' then - next_state <= pulu_acca_state; - elsif ea(2) = '1' then - next_state <= pulu_accb_state; - elsif ea(3) = '1' then - next_state <= pulu_dp_state; - elsif ea(4) = '1' then - next_state <= pulu_ixh_state; - elsif ea(5) = '1' then - next_state <= pulu_iyh_state; - elsif ea(6) = '1' then - next_state <= pulu_sph_state; - elsif ea(7) = '1' then - next_state <= pulu_pch_state; - else - next_state <= fetch_state; - end if; - - when pulu_acca_state => - -- increment up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - up_ctrl <= load_up; - -- read acca - acca_ctrl <= pull_acca; - addr_ctrl <= pullu_ad; - if ea(2) = '1' then - next_state <= pulu_accb_state; - elsif ea(3) = '1' then - next_state <= pulu_dp_state; - elsif ea(4) = '1' then - next_state <= pulu_ixh_state; - elsif ea(5) = '1' then - next_state <= pulu_iyh_state; - elsif ea(6) = '1' then - next_state <= pulu_sph_state; - elsif ea(7) = '1' then - next_state <= pulu_pch_state; - else - next_state <= fetch_state; - end if; - - when pulu_accb_state => - -- increment up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - up_ctrl <= load_up; - -- read accb - accb_ctrl <= pull_accb; - addr_ctrl <= pullu_ad; - if ea(3) = '1' then - next_state <= pulu_dp_state; - elsif ea(4) = '1' then - next_state <= pulu_ixh_state; - elsif ea(5) = '1' then - next_state <= pulu_iyh_state; - elsif ea(6) = '1' then - next_state <= pulu_sph_state; - elsif ea(7) = '1' then - next_state <= pulu_pch_state; - else - next_state <= fetch_state; - end if; - - when pulu_dp_state => - -- increment up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - up_ctrl <= load_up; - -- read dp - dp_ctrl <= pull_dp; - addr_ctrl <= pullu_ad; - if ea(4) = '1' then - next_state <= pulu_ixh_state; - elsif ea(5) = '1' then - next_state <= pulu_iyh_state; - elsif ea(6) = '1' then - next_state <= pulu_sph_state; - elsif ea(7) = '1' then - next_state <= pulu_pch_state; - else - next_state <= fetch_state; - end if; - - when pulu_ixh_state => - -- increment up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - up_ctrl <= load_up; - -- read ix hi - ix_ctrl <= pull_hi_ix; - addr_ctrl <= pullu_ad; - next_state <= pulu_ixl_state; - - when pulu_ixl_state => - -- increment up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - up_ctrl <= load_up; - -- read ix low - ix_ctrl <= pull_lo_ix; - addr_ctrl <= pullu_ad; - if ea(5) = '1' then - next_state <= pulu_iyh_state; - elsif ea(6) = '1' then - next_state <= pulu_sph_state; - elsif ea(7) = '1' then - next_state <= pulu_pch_state; - else - next_state <= fetch_state; - end if; - - when pulu_iyh_state => - -- increment up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - up_ctrl <= load_up; - -- read iy hi - iy_ctrl <= pull_hi_iy; - addr_ctrl <= pullu_ad; - next_state <= pulu_iyl_state; - - when pulu_iyl_state => - -- increment up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - up_ctrl <= load_up; - -- read iy low - iy_ctrl <= pull_lo_iy; - addr_ctrl <= pullu_ad; - if ea(6) = '1' then - next_state <= pulu_sph_state; - elsif ea(7) = '1' then - next_state <= pulu_pch_state; - else - next_state <= fetch_state; - end if; - - when pulu_sph_state => - -- increment up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - up_ctrl <= load_up; - -- read sp hi - sp_ctrl <= pull_hi_sp; - addr_ctrl <= pullu_ad; - next_state <= pulu_spl_state; - - when pulu_spl_state => - -- increment up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - up_ctrl <= load_up; - -- read sp low - sp_ctrl <= pull_lo_sp; - addr_ctrl <= pullu_ad; - if ea(7) = '1' then - next_state <= pulu_pch_state; - else - next_state <= fetch_state; - end if; - - when pulu_pch_state => - -- increment up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - up_ctrl <= load_up; - -- pull pc hi - pc_ctrl <= pull_hi_pc; - addr_ctrl <= pullu_ad; - next_state <= pulu_pcl_state; - - when pulu_pcl_state => - -- increment up - left_ctrl <= up_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - up_ctrl <= load_up; - -- read pc low - pc_ctrl <= pull_lo_pc; - addr_ctrl <= pullu_ad; - next_state <= fetch_state; - - -- - -- pop the Condition codes - -- - when rti_cc_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read cc - cc_ctrl <= pull_cc; - addr_ctrl <= pulls_ad; - next_state <= rti_entire_state; - - -- - -- Added RTI cycle 11th July 2006 John Kent. - -- test the "Entire" Flag - -- that has just been popped off the stack - -- - when rti_entire_state => - -- - -- The Entire flag must be recovered from the stack - -- before testing. - -- - if cc(EBIT) = '1' then - next_state <= rti_acca_state; - else - next_state <= rti_pch_state; - end if; - - when rti_acca_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read acca - acca_ctrl <= pull_acca; - addr_ctrl <= pulls_ad; - next_state <= rti_accb_state; - - when rti_accb_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read accb - accb_ctrl <= pull_accb; - addr_ctrl <= pulls_ad; - next_state <= rti_dp_state; - - when rti_dp_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read dp - dp_ctrl <= pull_dp; - addr_ctrl <= pulls_ad; - next_state <= rti_ixh_state; - - when rti_ixh_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read ix hi - ix_ctrl <= pull_hi_ix; - addr_ctrl <= pulls_ad; - next_state <= rti_ixl_state; - - when rti_ixl_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read ix low - ix_ctrl <= pull_lo_ix; - addr_ctrl <= pulls_ad; - next_state <= rti_iyh_state; - - when rti_iyh_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read iy hi - iy_ctrl <= pull_hi_iy; - addr_ctrl <= pulls_ad; - next_state <= rti_iyl_state; - - when rti_iyl_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read iy low - iy_ctrl <= pull_lo_iy; - addr_ctrl <= pulls_ad; - next_state <= rti_uph_state; - - - when rti_uph_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read up hi - up_ctrl <= pull_hi_up; - addr_ctrl <= pulls_ad; - next_state <= rti_upl_state; - - when rti_upl_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- read up low - up_ctrl <= pull_lo_up; - addr_ctrl <= pulls_ad; - next_state <= rti_pch_state; - - when rti_pch_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- pull pc hi - pc_ctrl <= pull_hi_pc; - addr_ctrl <= pulls_ad; - next_state <= rti_pcl_state; - - when rti_pcl_state => - -- increment sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_add16; - sp_ctrl <= load_sp; - -- pull pc low - pc_ctrl <= pull_lo_pc; - addr_ctrl <= pulls_ad; - next_state <= fetch_state; - - -- - -- here on IRQ or NMI interrupt - -- pre decrement the sp - -- Idle bus cycle - -- - when int_nmiirq_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - next_state <= int_entire_state; - - -- - -- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI - -- clear Entire Flag on FIRQ - -- before stacking all registers - -- - when int_entire_state => - -- set entire flag - alu_ctrl <= alu_see; - cc_ctrl <= load_cc; - next_state <= int_pcl_state; - - -- - -- here on FIRQ interrupt - -- pre decrement the sp - -- Idle bus cycle - -- - when int_firq_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - next_state <= int_fast_state; - -- - -- clear Entire Flag on FIRQ - -- before stacking all registers - -- - when int_fast_state => - -- clear entire flag - alu_ctrl <= alu_cle; - cc_ctrl <= load_cc; - next_state <= int_pcl_state; - - when int_pcl_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write pc low - addr_ctrl <= pushs_ad; - dout_ctrl <= pc_lo_dout; - next_state <= int_pch_state; - - when int_pch_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write pc hi - addr_ctrl <= pushs_ad; - dout_ctrl <= pc_hi_dout; - if cc(EBIT) = '1' then - next_state <= int_upl_state; - else - next_state <= int_cc_state; - end if; - - when int_upl_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write up low - addr_ctrl <= pushs_ad; - dout_ctrl <= up_lo_dout; - next_state <= int_uph_state; - - when int_uph_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write ix hi - addr_ctrl <= pushs_ad; - dout_ctrl <= up_hi_dout; - next_state <= int_iyl_state; - - when int_iyl_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write ix low - addr_ctrl <= pushs_ad; - dout_ctrl <= iy_lo_dout; - next_state <= int_iyh_state; - - when int_iyh_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write ix hi - addr_ctrl <= pushs_ad; - dout_ctrl <= iy_hi_dout; - next_state <= int_ixl_state; - - when int_ixl_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write ix low - addr_ctrl <= pushs_ad; - dout_ctrl <= ix_lo_dout; - next_state <= int_ixh_state; - - when int_ixh_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write ix hi - addr_ctrl <= pushs_ad; - dout_ctrl <= ix_hi_dout; - next_state <= int_dp_state; - - when int_dp_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write accb - addr_ctrl <= pushs_ad; - dout_ctrl <= dp_dout; - next_state <= int_accb_state; - - when int_accb_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write accb - addr_ctrl <= pushs_ad; - dout_ctrl <= accb_dout; - next_state <= int_acca_state; - - when int_acca_state => - -- decrement sp - left_ctrl <= sp_left; - right_ctrl <= one_right; - alu_ctrl <= alu_sub16; - sp_ctrl <= load_sp; - -- write acca - addr_ctrl <= pushs_ad; - dout_ctrl <= acca_dout; - next_state <= int_cc_state; - - when int_cc_state => - -- write cc - addr_ctrl <= pushs_ad; - dout_ctrl <= cc_dout; - case iv is - when NMI_VEC => - next_state <= int_maskif_state; - when SWI_VEC => - next_state <= int_maskif_state; - when FIRQ_VEC => - next_state <= int_maskif_state; - when IRQ_VEC => - next_state <= int_maski_state; - when SWI2_VEC => - next_state <= vect_hi_state; - when SWI3_VEC => - next_state <= vect_hi_state; - when others => - if op_code = "00111100" then -- CWAI - next_state <= int_cwai_state; - else - next_state <= rti_cc_state; -- spurious interrupt, do a RTI - end if; - end case; - - -- - -- wait here for an inteerupt - -- - when int_cwai_state => - if (nmi_req = '1') and (nmi_ack='0') then - iv_ctrl <= nmi_iv; - nmi_ctrl <= set_nmi; - next_state <= int_maskif_state; - else - -- - -- nmi request is not cleared until nmi input goes low - -- - if (nmi_req = '0') and (nmi_ack='1') then - nmi_ctrl <= reset_nmi; - end if; - -- - -- FIRQ is level sensitive - -- - if (firq = '1') and (cc(FBIT) = '0') then - iv_ctrl <= firq_iv; - next_state <= int_maskif_state; - -- - -- IRQ is level sensitive - -- - elsif (irq = '1') and (cc(IBIT) = '0') then - iv_ctrl <= irq_iv; - next_state <= int_maski_state; - else - iv_ctrl <= reset_iv; - next_state <= int_cwai_state; - end if; - end if; - - when int_maski_state => - alu_ctrl <= alu_sei; - cc_ctrl <= load_cc; - next_state <= vect_hi_state; - - when int_maskif_state => - alu_ctrl <= alu_seif; - cc_ctrl <= load_cc; - next_state <= vect_hi_state; - - -- - -- According to the 6809 programming manual: - -- If an interrupt is received and is masked - -- or lasts for less than three cycles, the PC - -- will advance to the next instruction. - -- If an interrupt is unmasked and lasts - -- for more than three cycles, an interrupt - -- will be generated. - -- Note that I don't wait 3 clock cycles. - -- John Kent 11th July 2006 - -- - when sync_state => - if (nmi_req = '1') and (nmi_ack='0') then - iv_ctrl <= nmi_iv; - nmi_ctrl <= set_nmi; - next_state <= int_nmiirq_state; - else - -- - -- nmi request is not cleared until nmi input goes low - -- - if (nmi_req = '0') and (nmi_ack='1') then - iv_ctrl <= reset_iv; - nmi_ctrl <= reset_nmi; - end if; - -- - -- FIRQ is level sensitive - -- - if (firq = '1') then - if (cc(FBIT) = '0') then - iv_ctrl <= firq_iv; - next_state <= int_firq_state; - else - iv_ctrl <= reset_iv; - next_state <= fetch_state; - end if; - -- - -- IRQ is level sensitive - -- - elsif (irq = '1') then - if (cc(IBIT) = '0') then - iv_ctrl <= irq_iv; - next_state <= int_nmiirq_state; - else - iv_ctrl <= reset_iv; - next_state <= fetch_state; - end if; - else - iv_ctrl <= reset_iv; - next_state <= sync_state; - end if; - end if; - - - when halt_state => - if halt = '1' then - next_state <= halt_state; - else - next_state <= fetch_state; - end if; - - when others => -- halt on undefine states - next_state <= error_state; - end case; -end process; - -end rtl; - diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/README.md b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/README.md deleted file mode 100644 index 64469dad..00000000 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/README.md +++ /dev/null @@ -1,109 +0,0 @@ -# Cycle Accurate MC6809 Core - -## Details - -This is a Verilog implementation of the Motorola MC6809 and MC6809E microprocessors from late 1970s. It is intentionally implemented in a manner to make it as similar as possible to the original microprocessors. - -When this was implemented, other 6809 cores already had been written. These other cores were in use and had been verified. Although I've never used any of these cores, I'm confident that they're excellent replications of the instruction set. However, none (as far as I know) was verified to be cycle-accurate. Encouragement from several sources (particularly one very generous source) convinced me to invest the time. - -Beyond merely cycle-accurate, the goal was to attempt to preserve as much of the actual bus signals and protocols as possible. Signals such as DMABREQ, TSC, MRDY, and LIC, while infrequently used were still implemented. Bus traffic was identified with a Logic Analyzer and matched to the 6809's specs (and, truthfully, when the specs were vague, details captured from hard MC6809/MC6809E part behavior). The particulars in the Motorola specifications were replicated. - -The goal was cycle accuracy and that dictated much of the design. This was never intended to be a supercharged superset of a MC6809. If you're looking to mega-power your existing system, this might not be the best choice. (Read the section on What This Is Not for explanation.) - -## Purpose, License - -I invested the time in the desire that *people use it*. I haven't given away hardware designs or software since the 1980s. However, this seems like a worthwhile exception. - -While the source is completely available, this is *not* an "open-source *group* project". You may modify it as you see fit. If you find errors, notifying me would be appreciated. Still, this is **not** a group project. I don't intend that to come off as rude quite so much as frank. I may choose to modify the core in the future; many "open-source group projects" seem to me to become interesting social studies in design-by-commitee, and how much time is required just to manage multiple people with multiple inclinations becomes significant. I confess that this scenario is not something that appeals to me. [Outside of a day job, I prefer to work with a very small and fairly private group.] If you're enthusiastic or appreciative, use the core in a design and I'll be thrilled - tell me about it, and I'll explain to you how thrilled I am. - -Refer to the [licensing](./documentation/LICENSE.md) requirements if you choose to leverage this work. - -This isn't an attempt to deal with part scarcity. Any variant of 6809 is still quite easy to obtain (at darned cheap prices, too). In truth, *far cheaper* than an FPGA. - -The actual target are people who are reimplementing retro-devices (Arcade games, Computers) that have incorporated entire designs into an FPGA, but require cycle accuracy. The core's required space on an FPGA isn't overwhelming once you hit a certain range of parts and integration. (If you're looking at CPLDs, you might want to scale up a bit.) - -## Implementation - -The core was implemented using Motorola's original documentation. Particularly, **Figure 18** in the MC6809 and MC6809E datasheets. There is a very close mapping between those five pages of diagrams and the bus and cycle activity of the CPU. - -I have noticed that some repositories of HDL tend to be only slightly more organized than *people tossing HDL files "over the wall"*. Explanations of how they work, how you as a consumer of the HDL should deal with it, etc. tend to be lacking or totally non-existent. - -I do have an interest (outside of this project) in HDL education; not quite in tutorials, but in implementations of HDMI, USB, SATA, etc. and explaining clearly how an implementation works - along with the hardware standard at the same time. - -Please - if you're not experienced in an HDL already, this cpu core isn't likely very useful to you as a learning mechanism. There are wonderful tutorials out there already; I highly recommend learning, experimenting, and so forth *first*, before attempting to absorb this design. - -## Validation - -The design was validated in multiple fashions, including against a Vectrex from 1982, a TRS-80 Color Computer 3, A slew of Williams Arcade games, and another wave of Taito Arcade games. - -Literal bus compatibility was achieved using a [GODIL-40](http://www.oho-elektronik.de/) against the above scenarios. I can't say enough nice things about the [GODIL](http://www.oho-elektronik.de/) design. Slick, compact. It's darned nice work. The only bad thing is that they're in short supply. (Oh, and they're 10x-20x the price of a hard CPU. I wouldn't recommend replacing your daily-use CPUs with a soft CPU in a GODIL unless you have a strong reason for doing so.) - -Functional testing was against the list of platforms above. They all work. - -Actual instruction cycle testing was done with the frequent help of Erik Gavriluk, who donated his time, consideration, and even hardware to the project. In this case, MAME sports a cycle-accurate 6809 emulator; Erik generated code that ran (nearly) every instruction in every addressing mode, and then ran that through MAME and kept an absolute cycle count. I captured the soft core's bus on a GODIL running the exact same code and matched the cycle counts. To improve things, Erik provided me with the register contents after every instruction. I wrote a testbench to run the same code and validated that the registers changed after each instruction identically in each scenario and in the exact same number of cycles. The result was gratifying. (Ahem, once it worked. Believe me, the CoCo, the cycle testing, the GODIL - they *all* pointed me at problems. I won't claim that the design is flawless - nothing I've ever written truly is - but effort *has* been made to actually verify the thing, and I'll list each of the platforms and experiences. [I'll even grumpily point out that Stargate has illegal instructions in it that they're darned lucky the 6809 happened to walk over.] - -Precise control signal testing (Interrupts, /HALT) were primarily done on JROK's Williams board. The Williams arcade games had a blitter, and it used /HALT to gain the bus and take action. JROK had done some extensive timing validation to prove that his implementation of the Williams design was **accurate**. I contacted him and being as he's an incredibly nice person, he gave me some advice and access to his source + prebuilt binaries. I was quite thankful - I found bus timing errors (related to /HALT and related to /IRQ latency) in the same vein (how many cycles before the next-new-instruction does each have to be asserted in order to be serviced at the beginning of the next instruction?) as a result. A very worthwhile endeavor, as I'd been convinced that I was correct; however, his code led me to swap hard CPUs with my soft core on analyzer captures and to realize that despite my intention to match the documentation perfectly there were cases where the documentation left details unclear, requiring comparison between a hard CPU and my existing timing. - -## What This Is Not - -This isn't an attempt to deal with parts scarcity, nor prepare for it. I can't imagine that 6809s will become *hard to get* in the next decade or so. There isn't a ton of volume required and there are lots of warehouses from companies that make their entire businesses on out-of-production parts. - -This isn't an attempt to make a faster MC6809. The implementation would have been different had that been a goal. It has extensive 'dead' cycles on the bus to fit MC6809 specifications. If I conditionally remove them, it would be significantly more efficient than a real MC6809 (but once again, not cycle-accurate). - -This core does not include HD6309 instructions. I did check, and without the 'dead' cycles mentioned above (the things that make it cycle-accurate), every instruction is at least as efficient as the HD6309, and most are more efficient. (I do have advantages of 40 years of technology over the original MC6809 design team, and at least 30 years over the HD6309 design team.) New registers and instructions from the HD6309 aren't there. Once again, that wasn't the goal. [I may still enable a dynamic mechanism to switch between cycle-accurate and minimum-cycles-required as an instantiation parameter.] - -If your goal really is "a super 6809", I have [strong opinions](./documentation/super6809.md) on the topic. - -## Perfection? - -While I'd love to say that this is a perfect replica, logic-level details of the implementation of the CPU aren't available. The Motorola documentation is *excellent*, but still not complete. - -I know of inconsistencies - but inconsistencies that I expect are trivial. Anything deemed as serious has been dealt with as soon as I've been made aware of it. - -The instructions have been heavily validated, and I'm confident in their accuracy - but not quite so arrogant as to insist that there could not be an oversight. (I'm not a young man any longer; I've been wrong too many times to be as remotely as confident as I was when I was 16.) - -Should issues be discovered, expect transparency and fixes - even if it's an incredibly rare edge case. [If you're actively using `/DMABREQ`, please contact me. You're the first.] - -## How does it work? - -This isn't quite the same question as the next, but if you really want to dig in and grasp the implementation, I've written a summary of the design [here](./documentation/CoreDesign.md). - -## How Do I Use It? - -### Samples - -Application of the core in a GODIL is provided. With this, you can - although for what reason, I'm not sure - plug-replace a MC6809 or MC6809E in nearly any design (*note the oscillator in the Vectrex instead of the crystal*). This is intended to demonstrate compatibility. - -A sample implementation is provided against a cheap Xilinx Spartan 6 LX9 board from eBay (China), a cheap Altera Cyclone IV EP4CE6 board (also from eBay, China), and two Cyclone V boards from terasic. These aren't attempting to run at original speeds, so I set them to 25Mhz for no reason other than "I can". These are intended to demonstrate use of the core entirely internal to an FPGA. - -### General Guidelines - -A list of general guidelines is provided. They are likely worth reading if you consider using this core. - -## Documentation - -1. [Explanation of the CPU Core design.](./documentation/CoreDesign.md) -2. [Validation Efforts.](./documentation/Validation.md) -3. [Implementation Examples](./documentation/samples.md). - -## Who Am I? - -Despite a certain degree of desire to remain anonymous, that seems pointless in today's world. - -My name is Greg Miller; I learned assembly in 1981 on a 6809 in a TRS-80 Color Computer, leaving me *fond* of this CPU architecture. - -Not surprisingly, I work in the tech industry (although quite definitely not implementing legacy hardware in FPGAs), do not represent my employer in any capacity whatsoever here, and have a family and a mortgage. - -You can contact me via: - - gregmiller6809@gmail.com - - -## Final Thoughts - -I'll keep track of my [Final Thoughts](./documentation/FinalThoughts.md) on the project. - -## Acknowledgements - -[I do want to thank a few people](documentation/Acknowledgements.md). - diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809.v b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809.v deleted file mode 100644 index b19d1552..00000000 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809.v +++ /dev/null @@ -1,80 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 08:11:34 09/23/2016 -// Design Name: -// Module Name: mc6809e -// Project Name: -// Target Devices: -// Tool versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// -module mc6809( - input [7:0] D, - output [7:0] DOut, - output [15:0] ADDR, - output RnW, - output E, - output Q, - output BS, - output BA, - input nIRQ, - input nFIRQ, - input nNMI, - input EXTAL, - input XTAL, - input nHALT, - input nRESET, - input MRDY, - input nDMABREQ - - , output [111:0] RegData - - ); - -reg [1:0] clk_phase=2'b00; - -wire CLK; -assign CLK=EXTAL; - -wire LIC; -wire BUSY; -wire AVMA; -reg rE; -reg rQ; -assign E = rE; -assign Q = rQ; - -mc6809i cpucore(.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(E), .Q(Q), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ), - .nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nHALT(nHALT), .nRESET(nRESET), .nDMABREQ(nDMABREQ) - ,.RegData(RegData) - ); - -always @(negedge CLK) -begin - case (clk_phase) - 2'b00: - rE <= 0; - 2'b01: - rQ <= 1; - 2'b10: - rE <= 1; - 2'b11: - rQ <= 0; - endcase - - if (MRDY == 1'b1) - clk_phase <= clk_phase + 2'b01; -end - - -endmodule diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809e.v b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809e.v deleted file mode 100644 index 396a9fa3..00000000 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809e.v +++ /dev/null @@ -1,48 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 08:11:34 09/23/2016 -// Design Name: -// Module Name: mc6809e -// Project Name: -// Target Devices: -// Tool versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// -module mc6809e( - input [7:0] D, - output [7:0] DOut, - output [15:0] ADDR, - output RnW, - input E, - input Q, - output BS, - output BA, - input nIRQ, - input nFIRQ, - input nNMI, - output AVMA, - output BUSY, - output LIC, - input nHALT, - input nRESET - - ); - - - -mc6809i cpucore (.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(E), .Q(Q), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ), - .nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nHALT(nHALT), .nRESET(nRESET), .nDMABREQ(1) - ); - - -endmodule diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809i.v b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809i.v deleted file mode 100644 index 5725aab4..00000000 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809i.v +++ /dev/null @@ -1,4156 +0,0 @@ -`timescale 1ns / 1ns -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: Greg Miller -// Copyright (c) 2016, Greg Miller -// -// Create Date: 14:26:59 08/13/2016 -// Design Name: -// Module Name: mc6809 -// Project Name: Cycle-Accurate 6809 Core -// Target Devices: -// Tool versions: -// Description: -// -// Dependencies: Intended to be standalone Vanilla Verilog. -// -// Revision: -// Revision 1.0 - Initial Release -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -// -// The 6809 has incomplete instruction decoding. A collection of instructions, if met, end up actually behaving like -// a binary-adjacent neighbor. -// -// The soft core permits three different behaviors for this situation, controlled by the instantiation parameter -// ILLEGAL_INSTRUCTIONS -// -// "GHOST" - Mimic the 6809's incomplete decoding. This is as similar to a hard 6809 as is practical. [DEFAULT] -// -// "STOP" - Cause the soft core to cease execution, placing $DEAD on the address bus and R/W to 'read'. Interrupts, -// bus control (/HALT, /DMABREQ), etc. are ignored. The core intentionally seizes in this instance. -// (Frankly, this is useful when making changes to the core and you have a logic analyzer connected.) -// -// "IGNORE"- Cause the soft core to merely ignore illegal instructions. It will consider them 1-byte instructions and -// attempt to fetch and run an exception 1 byte later. -// - -module mc6809i -#( - parameter ILLEGAL_INSTRUCTIONS="GHOST" -) -( - - input [7:0] D, - output [7:0] DOut, - output [15:0] ADDR, - output RnW, - input E, - input Q, - output BS, - output BA, - input nIRQ, - input nFIRQ, - input nNMI, - output AVMA, - output BUSY, - output LIC, - input nHALT, - input nRESET, - input nDMABREQ, - output [111:0] RegData -); - -reg [7:0] DOutput; - -assign DOut = DOutput; - -reg RnWOut; // Combinatorial - -reg rLIC; -assign LIC = rLIC; - -reg rAVMA; -assign AVMA = rAVMA; - -reg rBUSY; -assign BUSY = rBUSY; - -// Bus control -// BS BA -// 0 0 normal (CPU running, CPU is master) -// 0 1 Interrupt Ack -// 1 0 Sync Ack -// 1 1 CPU has gone high-Z on A, D, R/W -// - -assign RnW = RnWOut; - - -///////////////////////////////////////////////// -// Vectors -`define RESET_VECTOR 16'HFFFE -`define NMI_VECTOR 16'HFFFC -`define SWI_VECTOR 16'HFFFA -`define IRQ_VECTOR 16'HFFF8 -`define FIRQ_VECTOR 16'HFFF6 -`define SWI2_VECTOR 16'HFFF4 -`define SWI3_VECTOR 16'HFFF2 -`define Reserved_VECTOR 16'HFFF0 - -////////////////////////////////////////////////////// -// Latched registers -// - -// The last-latched copy. -reg [7:0] a; -reg [7:0] b; -reg [15:0] x; -reg [15:0] y; -reg [15:0] u; -reg [15:0] s; -reg [15:0] pc; -reg [7:0] dp; -reg [7:0] cc; -reg [15:0] tmp; -reg [15:0] addr; -reg [15:0] ea; - - -// Debug ability to export register contents -assign RegData[7:0] = a; -assign RegData[15:8] = b; -assign RegData[31:16] = x; -assign RegData[47:32] = y; -assign RegData[63:48] = s; -assign RegData[79:64] = u; -assign RegData[87:80] = cc; -assign RegData[95:88] = dp; -assign RegData[111:96] = pc; - - - -// The values as being calculated -reg [7:0] a_nxt; -reg [7:0] b_nxt; -reg [15:0] x_nxt; -reg [15:0] y_nxt; -reg [15:0] u_nxt; -reg [15:0] s_nxt; -reg [15:0] pc_nxt; -reg [7:0] dp_nxt; -reg [7:0] cc_nxt; -reg [15:0] addr_nxt; -reg [15:0] ea_nxt; -reg [15:0] tmp_nxt; - -reg BS_nxt; -reg BA_nxt; - -// for ADDR, BS/BA, assign them to the flops -assign BS = BS_nxt; -assign BA = BA_nxt; -assign ADDR=addr_nxt; - -localparam CC_E= 8'H80; -localparam CC_F= 8'H40; -localparam CC_H= 8'H20; -localparam CC_I= 8'H10; -localparam CC_N= 8'H08; -localparam CC_Z= 8'H04; -localparam CC_V= 8'H02; -localparam CC_C= 8'H01; - -localparam CC_E_BIT= 3'd7; -localparam CC_F_BIT= 3'd6; -localparam CC_H_BIT= 3'd5; -localparam CC_I_BIT= 3'd4; -localparam CC_N_BIT= 3'd3; -localparam CC_Z_BIT= 3'd2; -localparam CC_V_BIT= 3'd1; -localparam CC_C_BIT= 3'd0; - -// Convenience calculations -reg [15:0] pc_p1; -reg [15:0] pc_p2; -reg [15:0] pc_p3; -reg [15:0] s_p1; -reg [15:0] s_m1; -reg [15:0] u_p1; -reg [15:0] u_m1; -reg [15:0] addr_p1; -reg [15:0] ea_p1; - -////////////////////////////////////////////////////// -// NMI Mask -// -// NMI is supposed to be masked - despite the name - until the 6809 loads a value into S. -// Frankly, I'm cheating slightly. If someone does a LDS #$0, it won't disable the mask. Pretty much anything else -// that changes the value of S from the default (which is currently $0) will clear the mask. A reset will set the mask again. -reg NMIMask; - -reg NMILatched; -reg NMISample; -reg NMISample2; -reg NMIClear; -reg NMIClear_nxt; -wire wNMIClear = NMIClear; - -reg IRQLatched; - -reg IRQSample; -reg IRQSample2; -reg FIRQLatched; -reg FIRQSample; -reg FIRQSample2; -reg HALTLatched; -reg HALTSample; -reg HALTSample2; -reg DMABREQLatched; -reg DMABREQSample; -reg DMABREQSample2; - -// Interrupt types -localparam INTTYPE_NMI = 3'H0 ; -localparam INTTYPE_IRQ = 3'H1 ; -localparam INTTYPE_FIRQ = 3'H2 ; -localparam INTTYPE_SWI = 3'H3 ; -localparam INTTYPE_SWI2 = 3'H4 ; -localparam INTTYPE_SWI3 = 3'H5 ; - -reg [2:0] IntType; -reg [2:0] IntType_nxt; - -////////////////////////////////////////////////////// -// Instruction Fetch Details -// -reg InstPage2; -reg InstPage3; -reg InstPage2_nxt; -reg InstPage3_nxt; - -reg [7:0] Inst1; -reg [7:0] Inst2; -reg [7:0] Inst3; -reg [7:0] Inst1_nxt; -reg [7:0] Inst2_nxt; -reg [7:0] Inst3_nxt; - - -localparam CPUSTATE_RESET = 7'd0; -localparam CPUSTATE_RESET0 = 7'd1; - -localparam CPUSTATE_RESET2 = 7'd3; -localparam CPUSTATE_FETCH_I1 = 7'd4; -localparam CPUSTATE_FETCH_I1V2 = 7'd5; -localparam CPUSTATE_FETCH_I2 = 7'd8; - -localparam CPUSTATE_LBRA_OFFSETLOW = 7'd17; -localparam CPUSTATE_LBRA_DONTCARE = 7'd18; -localparam CPUSTATE_LBRA_DONTCARE2 = 7'd19; - - - -localparam CPUSTATE_BRA_DONTCARE = 7'd20; - -localparam CPUSTATE_BSR_DONTCARE1 = 7'd21; -localparam CPUSTATE_BSR_DONTCARE2 = 7'd22; -localparam CPUSTATE_BSR_RETURNLOW = 7'd23; -localparam CPUSTATE_BSR_RETURNHIGH = 7'd24; - -localparam CPUSTATE_TFR_DONTCARE1 = 7'd26; -localparam CPUSTATE_TFR_DONTCARE2 = 7'd27; -localparam CPUSTATE_TFR_DONTCARE3 = 7'd28; -localparam CPUSTATE_TFR_DONTCARE4 = 7'd29; - -localparam CPUSTATE_EXG_DONTCARE1 = 7'd30; -localparam CPUSTATE_EXG_DONTCARE2 = 7'd31; -localparam CPUSTATE_EXG_DONTCARE3 = 7'd32; -localparam CPUSTATE_EXG_DONTCARE4 = 7'd33; -localparam CPUSTATE_EXG_DONTCARE5 = 7'd34; -localparam CPUSTATE_EXG_DONTCARE6 = 7'd35; - -localparam CPUSTATE_ABX_DONTCARE = 7'd36; - -localparam CPUSTATE_RTS_HI = 7'd38; -localparam CPUSTATE_RTS_LO = 7'd39; -localparam CPUSTATE_RTS_DONTCARE2 = 7'd40; - -localparam CPUSTATE_16IMM_LO = 7'd41; -localparam CPUSTATE_ALU16_DONTCARE = 7'd42; -localparam CPUSTATE_DIRECT_DONTCARE = 7'd43; - -localparam CPUSTATE_ALU_EA = 7'd44; - -localparam CPUSTATE_ALU_DONTCARE = 7'd46; -localparam CPUSTATE_ALU_WRITEBACK = 7'd47; - -localparam CPUSTATE_LD16_LO = 7'd48; - -localparam CPUSTATE_ST16_LO = 7'd49; -localparam CPUSTATE_ALU16_LO = 7'd50; - - - - -localparam CPUSTATE_JSR_DONTCARE = 7'd53; -localparam CPUSTATE_JSR_RETLO = 7'd54; -localparam CPUSTATE_JSR_RETHI = 7'd55; -localparam CPUSTATE_EXTENDED_ADDRLO = 7'd56; -localparam CPUSTATE_EXTENDED_DONTCARE = 7'd57; -localparam CPUSTATE_INDEXED_BASE = 7'd58; - - -localparam CPUSTATE_IDX_DONTCARE3 = 7'd60; - -localparam CPUSTATE_IDX_OFFSET_LO = 7'd61; -localparam CPUSTATE_IDX_16OFFSET_LO = 7'd62; - -localparam CPUSTATE_IDX_16OFF_DONTCARE0= 7'd63; -localparam CPUSTATE_IDX_16OFF_DONTCARE1= 7'd64; -localparam CPUSTATE_IDX_16OFF_DONTCARE2= 7'd65; -localparam CPUSTATE_IDX_16OFF_DONTCARE3= 7'd66; - -localparam CPUSTATE_IDX_DOFF_DONTCARE1 = 7'd68; -localparam CPUSTATE_IDX_DOFF_DONTCARE2 = 7'd69; -localparam CPUSTATE_IDX_DOFF_DONTCARE3 = 7'd70; -localparam CPUSTATE_IDX_PC16OFF_DONTCARE = 7'd71; - -localparam CPUSTATE_IDX_EXTIND_LO = 7'd72; -localparam CPUSTATE_IDX_EXTIND_DONTCARE = 7'd73; - -localparam CPUSTATE_INDIRECT_HI = 7'd74; -localparam CPUSTATE_INDIRECT_LO = 7'd75; -localparam CPUSTATE_INDIRECT_DONTCARE = 7'd76; -localparam CPUSTATE_MUL_ACTION = 7'd77; - -localparam CPUSTATE_PSH_DONTCARE1 = 7'd80; -localparam CPUSTATE_PSH_DONTCARE2 = 7'd81; -localparam CPUSTATE_PSH_DONTCARE3 = 7'd82; -localparam CPUSTATE_PSH_ACTION = 7'd83; - -localparam CPUSTATE_PUL_DONTCARE1 = 7'd84; -localparam CPUSTATE_PUL_DONTCARE2 = 7'd85; -localparam CPUSTATE_PUL_ACTION = 7'd86; - -localparam CPUSTATE_NMI_START = 7'd87; -localparam CPUSTATE_IRQ_DONTCARE = 7'd88; -localparam CPUSTATE_IRQ_START = 7'd89; -localparam CPUSTATE_IRQ_DONTCARE2 = 7'd90; -localparam CPUSTATE_IRQ_VECTOR_HI = 7'd91; -localparam CPUSTATE_IRQ_VECTOR_LO = 7'd92; -localparam CPUSTATE_FIRQ_START = 7'd93; -localparam CPUSTATE_CC_DONTCARE = 7'd94; -localparam CPUSTATE_SWI_START = 7'd95; - -localparam CPUSTATE_TST_DONTCARE1 = 7'd96; -localparam CPUSTATE_TST_DONTCARE2 = 7'd97; - -localparam CPUSTATE_DEBUG = 7'd98; - -localparam CPUSTATE_16IMM_DONTCARE = 7'd99; - -localparam CPUSTATE_HALTED = 7'd100; - -localparam CPUSTATE_HALT_EXIT2 = 7'd102; -localparam CPUSTATE_STOP = 7'd105; -localparam CPUSTATE_STOP2 = 7'd106; -localparam CPUSTATE_STOP3 = 7'd107; - - -localparam CPUSTATE_CWAI = 7'd108; -localparam CPUSTATE_CWAI_DONTCARE1 = 7'd109; -localparam CPUSTATE_CWAI_POST = 7'd110; - -localparam CPUSTATE_DMABREQ = 7'd111; -localparam CPUSTATE_DMABREQ_EXIT = 7'd112; -localparam CPUSTATE_SYNC = 7'd113; -localparam CPUSTATE_SYNC_EXIT = 7'd114; - -localparam CPUSTATE_INT_DONTCARE = 7'd115; - - -reg [6:0] CpuState = CPUSTATE_RESET; -reg [6:0] CpuState_nxt = CPUSTATE_RESET; - -reg [6:0] NextState = CPUSTATE_RESET; -reg [6:0] NextState_nxt = CPUSTATE_RESET; - -wire [6:0] PostIllegalState; - -// If we encounter something like an illegal addressing mode (an index mode that's illegal for instance) -// What state should we go to? -generate -if (ILLEGAL_INSTRUCTIONS=="STOP") -begin : postillegal - assign PostIllegalState = CPUSTATE_STOP; -end -else -begin - assign PostIllegalState = CPUSTATE_FETCH_I1; -end -endgenerate - - - -/////////////////////////////////////////////////////////////////////// - -// -// MapInstruction - Considering how the core was instantiated, this -// will either directly return D[7:0] *or* remap values from D[7:0] -// that relate to undefined instructions in the 6809 to the instructions -// that the 6809 actually executed when these were encountered, due to -// incomplete decoding. -// -// NEG, COM, LSR, DEC - these four instructions, in Direct, Inherent (A or B) -// Indexed, or Extended addressing do not actually decode bit 0 on the instruction. -// Thus, for instance, a $51 encountered will be executed as a $50, which is a NEGB. -// - -// Specifically, the input is an instruction; if it matches an unknown instruction that the -// 6809 is known to ghost to another instruction, the output of the function -// is the the instruction that actually gets executed. Otherwise, the output is the -// input. - -function [7:0] MapInstruction(input [7:0] i); -reg [3:0] topnyb; -reg [3:0] btmnyb; -reg [7:0] newinst; -begin - newinst = i; - - topnyb = i[7:4]; - btmnyb = i[3:0]; - - if ( (topnyb == 4'H0) || - (topnyb == 4'H4) || - (topnyb == 4'H5) || - (topnyb == 4'H6) || - (topnyb == 4'H7) - ) - begin - if (btmnyb == 4'H1) - newinst = {topnyb, 4'H0}; - if (btmnyb == 4'H2) - newinst = {topnyb, 4'H3}; - if (btmnyb == 4'H5) - newinst = {topnyb, 4'H4}; - if (btmnyb == 4'HB) - newinst = {topnyb, 4'HA}; - end - MapInstruction = newinst; -end -endfunction - - -wire [7:0] MappedInstruction; -generate -if (ILLEGAL_INSTRUCTIONS=="GHOST") -begin : ghost - assign MappedInstruction = MapInstruction(D); -end -else -begin - assign MappedInstruction = D; -end -endgenerate - - - -/////////////////////////////////////////////////////////////////////// - -function IllegalInstruction(input [7:0] i); -reg [3:0] hi; -reg [3:0] lo; -reg illegal; -begin - illegal = 1'b0; - hi = i[7:4]; - lo = i[3:0]; - if ( (hi == 4'H0) || (hi == 4'H4) || (hi == 4'H5) || (hi == 4'H6) || (hi == 4'H7) ) - begin - if ( (lo == 4'H1) || (lo == 4'H2) || (lo == 4'H5) || (lo == 4'HB) ) - illegal = 1'b1; - if (lo == 4'HE) - if ( (hi == 4'H4) || (hi == 4'H5) ) - illegal = 1'b1; - end - if (hi == 4'H3) - begin - if ( (lo == 4'H8) || (lo == 4'HE) ) - illegal = 1'b1; - end - if (hi == 4'H1) - begin - if ( (lo == 4'H4) || (lo == 4'H5) || (lo == 4'H8) || (lo == 4'HB) ) - illegal = 1'b1; - end - if ( (hi == 4'H8) || (hi == 4'HC) ) - begin - if ( (lo == 4'H7) || (lo == 4'HF) ) - illegal = 1'b1; - if ( lo == 4'HD ) - if (hi == 4'HC) - illegal = 1'b1; - end - IllegalInstruction = illegal; -end -endfunction - -wire IsIllegalInstruction; - -generate -if (ILLEGAL_INSTRUCTIONS=="GHOST") -begin : never_illegal - assign IsIllegalInstruction = 1'b0; -end -else -begin - assign IsIllegalInstruction = IllegalInstruction(Inst1); -end -endgenerate - -wire [6:0] IllegalInstructionState; -generate -if (ILLEGAL_INSTRUCTIONS=="IGNORE") -begin : illegal_state - assign IllegalInstructionState = CPUSTATE_FETCH_I1; -end -else if (ILLEGAL_INSTRUCTIONS=="STOP") -begin - assign IllegalInstructionState = CPUSTATE_STOP; -end -else -begin - assign IllegalInstructionState = 7'd0; -end -endgenerate - - -/////////////////////////////////////////////////////////////////////// - - -always @(negedge NMISample2 or posedge wNMIClear) -begin - if (wNMIClear == 1) - NMILatched <= 1; - else if (NMIMask == 0) - NMILatched <= 0; - else - NMILatched <= 1; -end - -// -// The 6809 specs say that the CPU control signals are sampled on the falling edge of Q. -// It also says that the interrupts require 1 cycle of synchronization time. -// That's vague, as it doesn't say where "1 cycle" starts or ends. Starting from the -// falling edge of Q, the next cycle notices an assertion. From checking a hard 6809 on -// an analyzer, what they really mean is that it's sampled on the falling edge of Q, -// but there's a one cycle delay from the falling edge of E (0.25 clocks from the falling edge of Q -// where the signals were sampled) before it can be noticed. -// So, SIGNALSample is the latched value at the falling edge of Q -// SIGNALSample2 is the latched value at the falling edge of E (0.25 clocks after the line above) -// SIGNALLatched is the latched value at the falling edge of E (1 cycle after the line above) -// -// /HALT and /DMABREQ are delayed one cycle less than interrupts. The 6809 specs infer these details, -// but don't list the point-of-reference they're written from (for instance, they say that an interrupt requires -// a cycle for synchronization; however, it isn't clear whether that's from the falling Q to the next falling Q, -// a complete intermediate cycle, the falling E to the next falling E, etc.) - which, in the end, required an -// analyzer on the 6809 to determine how many cycles before a new instruction an interrupt (or /HALT & /DMABREQ) -// had to be asserted to be noted instead of the next instruction running start to finish. -// -always @(negedge Q) -begin - NMISample <= nNMI; - - IRQSample <= nIRQ; - - FIRQSample <= nFIRQ; - - HALTSample <= nHALT; - - DMABREQSample <= nDMABREQ; - - -end - - -reg rnRESET=0; // The latched version of /RESET, useful 1 clock after it's latched -always @(negedge E) -begin - rnRESET <= nRESET; - - NMISample2 <= NMISample; - - IRQSample2 <= IRQSample; - IRQLatched <= IRQSample2; - - FIRQSample2 <= FIRQSample; - FIRQLatched <= FIRQSample2; - - HALTSample2 <= HALTSample; - HALTLatched <= HALTSample2; - - DMABREQSample2 <= DMABREQSample; - DMABREQLatched <= DMABREQSample2; - - - if (rnRESET == 1) - begin - CpuState <= CpuState_nxt; - - // Don't interpret this next item as "The Next State"; it's a special case 'after this - // generic state, go to this programmable state', so that a single state - // can be shared for many tasks. [Specifically, the stack push/pull code, which is used - // for PSH, PUL, Interrupts, RTI, etc. - NextState <= NextState_nxt; - - // CPU registers latch from the combinatorial circuit - a <= a_nxt; - b <= b_nxt; - x <= x_nxt; - y <= y_nxt; - s <= s_nxt; - u <= u_nxt; - cc <= cc_nxt; - dp <= dp_nxt; - pc <= pc_nxt; - tmp <= tmp_nxt; - addr <= addr_nxt; - ea <= ea_nxt; - - InstPage2 <= InstPage2_nxt; - InstPage3 <= InstPage3_nxt; - Inst1 <= Inst1_nxt; - Inst2 <= Inst2_nxt; - Inst3 <= Inst3_nxt; - NMIClear <= NMIClear_nxt; - - IntType <= IntType_nxt; - - if (s != s_nxt) // Once S changes at all (default is '0'), release the NMI Mask. - NMIMask <= 1'b0; - end - else - begin - CpuState <= CPUSTATE_RESET; - NMIMask <= 1'b1; // Mask NMI until S is loaded. - NMIClear <= 1'b0; // Mark us as not having serviced NMI - end -end - - -///////////////////////////////////////////////////////////////// -// Decode the Index byte - -localparam IDX_REG_X = 3'd0; -localparam IDX_REG_Y = 3'd1; -localparam IDX_REG_U = 3'd2; -localparam IDX_REG_S = 3'd3; -localparam IDX_REG_PC = 3'd4; - -localparam IDX_MODE_POSTINC1 = 4'd0; -localparam IDX_MODE_POSTINC2 = 4'd1; -localparam IDX_MODE_PREDEC1 = 4'd2; -localparam IDX_MODE_PREDEC2 = 4'd3; -localparam IDX_MODE_NOOFFSET = 4'd4; -localparam IDX_MODE_B_OFFSET = 4'd5; -localparam IDX_MODE_A_OFFSET = 4'd6; -localparam IDX_MODE_5BIT_OFFSET= 4'd7; // Special case, not bit pattern 7; the offset sits in the bit pattern -localparam IDX_MODE_8BIT_OFFSET= 4'd8; -localparam IDX_MODE_16BIT_OFFSET = 4'd9; -localparam IDX_MODE_D_OFFSET = 4'd11; -localparam IDX_MODE_8BIT_OFFSET_PC = 4'd12; -localparam IDX_MODE_16BIT_OFFSET_PC= 4'd13; -localparam IDX_MODE_EXTENDED_INDIRECT = 4'd15; - -// Return: -// Register base [3 bits] -// Indirect [1 bit] -// Mode [4 bits] - -function [7:0] IndexDecode(input [7:0] postbyte); -reg [2:0] regnum; -reg indirect; -reg [3:0] mode; -begin - indirect = 0; - mode = 0; - - if (postbyte[7] == 0) // 5-bit - begin - mode = IDX_MODE_5BIT_OFFSET; - end - else - begin - mode = postbyte[3:0]; - indirect = postbyte[4]; - end - if ((mode != IDX_MODE_8BIT_OFFSET_PC) && (mode != IDX_MODE_16BIT_OFFSET_PC)) - regnum[2:0] = postbyte[6:5]; - else - regnum[2:0] = IDX_REG_PC; - - IndexDecode = {indirect, mode, regnum}; -end -endfunction - -wire [3:0] IndexedMode; -wire IndexedIndirect; -wire [2:0] IndexedRegister; - -assign {IndexedIndirect, IndexedMode, IndexedRegister} = IndexDecode(Inst2); - -///////////////////////////////////////////////////////////////// -// Is this a JMP instruction? (irrespective of addressing mode) -function IsJMP(input [7:0] inst); -reg [3:0] hi; -reg [3:0] lo; -begin - hi = inst[7:4]; - lo = inst[3:0]; - - IsJMP = 0; - if ((hi == 4'H0) || (hi == 4'H6) || (hi == 4'H7)) - if (lo == 4'HE) - IsJMP = 1; -end -endfunction - -/////////////////////////////////////////////////////////////////// -// Is this an 8-bit Store? - -localparam ST8_REG_A = 1'b0; -localparam ST8_REG_B = 1'b1; - -function [1:0] IsST8(input [7:0] inst); -reg regnum; -reg IsStore; -begin - - IsStore = 1'b0; - regnum = 1'b1; - - if ( (Inst1 == 8'H97) || (Inst1 == 8'HA7) || (Inst1 == 8'HB7) ) - begin - IsStore = 1'b1; - regnum = 1'b0; - end - else if ( (Inst1 == 8'HD7) || (Inst1 == 8'HE7) || (Inst1 == 8'HF7) ) - begin - IsStore = 1'b1; - regnum = 1'b1; - end - IsST8 = {IsStore, regnum}; -end -endfunction - -wire IsStore8; -wire Store8RegisterNum; - -assign {IsStore8, Store8RegisterNum} = IsST8(Inst1); - - -///////////////////////////////////////////////////////////////// -// Is this a 16-bit Store? - -localparam ST16_REG_X = 3'd0; -localparam ST16_REG_Y = 3'd1; -localparam ST16_REG_U = 3'd2; -localparam ST16_REG_S = 3'd3; -localparam ST16_REG_D = 3'd4; - - -function [3:0] IsST16(input [7:0] inst); -reg [3:0] hi; -reg [3:0] lo; -reg [2:0] regnum; -reg IsStore; -begin - hi = inst[7:4]; - lo = inst[3:0]; - IsStore = 1'b0; - regnum = 3'b111; - - if ((inst == 8'H9F) || (inst == 8'HAF) || (inst == 8'HBF)) - begin - IsStore = 1; - if (~InstPage2) - regnum = ST16_REG_X; - else - regnum = ST16_REG_Y; - end - else if ((inst == 8'HDF) || (inst == 8'HEF) || (inst == 8'HFF)) - begin - IsStore = 1; - if (~InstPage2) - regnum = ST16_REG_U; - else - regnum = ST16_REG_S; - end - else if ((inst == 8'HDD) || (inst == 8'HED) || (inst == 8'HFD)) - begin - IsStore = 1; - regnum = ST16_REG_D; - end - - IsST16 = {IsStore, regnum}; -end -endfunction - -wire IsStore16; -wire [2:0] StoreRegisterNum; - -assign {IsStore16, StoreRegisterNum} = IsST16(Inst1); - -///////////////////////////////////////////////////////////////// -// Is this a special Immediate mode instruction, ala -// PSH, PUL, EXG, TFR, ANDCC, ORCC -function IsSpecialImm(input [7:0] inst); -reg is; -reg [3:0] hi; -reg [3:0] lo; -begin - hi = inst[7:4]; - lo = inst[3:0]; - is = 0; - - if (hi == 4'H1) - begin - if ( (lo == 4'HA) || (lo == 4'HC) || (lo == 4'HE) || (lo == 4'HF) ) // ORCC, ANDCC, EXG, TFR - is = 1; - end - else if (hi == 4'H3) - begin - if ( (lo >= 4'H3) && (lo <= 4'H7) ) // PSHS, PULS, PSHU, PULU - is = 1; - end - else - is = 0; - - IsSpecialImm = is; -end -endfunction -wire IsSpecialImmediate = IsSpecialImm(Inst1); - -///////////////////////////////////////////////////////////////// -// Is this a one-byte instruction? [The 6809 reads 2 bytes for every instruction, minimum (it can read more). On a one-byte, we have to ensure that we haven't skipped the PC ahead. -function IsOneByteInstruction(input [7:0] inst); -reg is; -reg [3:0] hi; -reg [3:0] lo; -begin - hi = inst[7:4]; - lo = inst[3:0]; - is = 1'b0; - - if ( (hi == 4'H4) || (hi == 4'H5) ) - is = 1'b1; - else if ( hi == 4'H1) - begin - if ( (lo == 4'H2) || (lo == 4'H3) || (lo == 4'H9) || (lo == 4'HD) ) - is = 1'b1; - end - else if (hi == 4'H3) - begin - if ( (lo >= 4'H9) && (lo != 4'HC) ) - is = 1'b1; - end - else - is = 1'b0; - - IsOneByteInstruction = is; -end -endfunction - -///////////////////////////////////////////////////////////////// -// ALU16 - Simpler than the 8 bit ALU - -localparam ALU16_REG_X = 3'd0; -localparam ALU16_REG_Y = 3'd1; -localparam ALU16_REG_U = 3'd2; -localparam ALU16_REG_S = 3'd3; -localparam ALU16_REG_D = 3'd4; - -function [2:0] ALU16RegFromInst(input Page2, input Page3, input [7:0] inst); -reg [2:0] srcreg; -begin - srcreg = 3'b111; // default - casex ({Page2, Page3, inst}) // Note pattern for the matching below - 10'b1010xx0011: // 1083, 1093, 10A3, 10B3 CMPD - srcreg = ALU16_REG_D; - 10'b1010xx1100: // 108C, 109C, 10AC, 10BC CMPY - srcreg = ALU16_REG_Y; - 10'b0110xx0011: // 1183, 1193, 11A3, 11B3 CMPU - srcreg = ALU16_REG_U; - 10'b0110xx1100: // 118C, 119C, 11AC, 11BC CMPS - srcreg = ALU16_REG_S; - 10'b0010xx1100: // 8C,9C,AC,BC CMPX - srcreg = ALU16_REG_X; - - 10'b0011xx0011: // C3, D3, E3, F3 ADDD - srcreg = ALU16_REG_D; - - 10'b0011xx1100: // CC, DC, EC, FC LDD - srcreg = ALU16_REG_D; - 10'b0010xx1110: // 8E LDX, 9E LDX, AE LDX, BE LDX - srcreg = ALU16_REG_X; - 10'b0011xx1110: // CE LDU, DE LDU, EE LDU, FE LDU - srcreg = ALU16_REG_U; - 10'b1010xx1110: // 108E LDY, 109E LDY, 10AE LDY, 10BE LDY - srcreg = ALU16_REG_Y; - 10'b1011xx1110: // 10CE LDS, 10DE LDS, 10EE LDS, 10FE LDS - srcreg = ALU16_REG_S; - 10'b0010xx0011: // 83, 93, A3, B3 SUBD - srcreg = ALU16_REG_D; - - 10'H03A: // 3A ABX - srcreg = ALU16_REG_X; - 10'H030: // 30 LEAX - srcreg = ALU16_REG_X; - 10'H031: // 31 LEAY - srcreg = ALU16_REG_Y; - 10'H032: // 32 LEAS - srcreg = ALU16_REG_S; - 10'H033: // 32 LEAU - srcreg = ALU16_REG_U; - default: - srcreg = 3'b111; - endcase - ALU16RegFromInst = srcreg; -end -endfunction - -wire [2:0] ALU16Reg = ALU16RegFromInst(InstPage2, InstPage3, Inst1); - -localparam ALUOP16_SUB = 3'H0; -localparam ALUOP16_ADD = 3'H1; -localparam ALUOP16_LD = 3'H2; -localparam ALUOP16_CMP = 3'H3; -localparam ALUOP16_LEA = 3'H4; -localparam ALUOP16_INVALID = 3'H7; - -function [3:0] ALU16OpFromInst(input Page2, input Page3, input [7:0] inst); -reg [2:0] aluop; -reg writeback; -begin - aluop = 3'b111; - writeback = 1'b1; - casex ({Page2, Page3, inst}) - 10'b1010xx0011: // 1083, 1093, 10A3, 10B3 CMPD - begin - aluop = ALUOP16_CMP; - writeback = 1'b0; - end - 10'b1010xx1100: // 108C, 109C, 10AC, 10BC CMPY - begin - aluop = ALUOP16_CMP; - writeback = 1'b0; - end - 10'b0110xx0011: // 1183, 1193, 11A3, 11B3 CMPU - begin - aluop = ALUOP16_CMP; - writeback = 1'b0; - end - 10'b0110xx1100: // 118C, 119C, 11AC, 11BC CMPS - begin - aluop = ALUOP16_CMP; - writeback = 1'b0; - end - 10'b0010xx1100: // 8C,9C,AC,BC CMPX - begin - aluop = ALUOP16_CMP; - writeback = 1'b0; - end - - 10'b0011xx0011: // C3, D3, E3, F3 ADDD - aluop = ALUOP16_ADD; - - 10'b0011xx1100: // CC, DC, EC, FC LDD - aluop = ALUOP16_LD; - 10'b001xxx1110: // 8E LDX, 9E LDX, AE LDX, BE LDX, CE LDU, DE LDU, EE LDU, FE LDU - aluop = ALUOP16_LD; - 10'b101xxx1110: // 108E LDY, 109E LDY, 10AE LDY, 10BE LDY, 10CE LDS, 10DE LDS, 10EE LDS, 10FE LDS - aluop = ALUOP16_LD; - - 10'b0010xx0011: // 83, 93, A3, B3 SUBD - aluop = ALUOP16_SUB; - - 10'H03A: // 3A ABX - aluop = ALUOP16_ADD; - - 10'b00001100xx: // $30-$33, LEAX, LEAY, LEAS, LEAU - aluop = ALUOP16_LEA; - - default: - aluop = ALUOP16_INVALID; - endcase - ALU16OpFromInst = {writeback, aluop}; -end -endfunction - -wire ALU16OpWriteback; -wire [2:0] ALU16Opcode; - -assign {ALU16OpWriteback, ALU16Opcode} = ALU16OpFromInst(InstPage2, InstPage3, Inst1); - -wire IsALU16Opcode = (ALU16Opcode != 3'b111); - -function [23:0] ALU16Inst(input [2:0] operation16, input [15:0] a_arg, input [15:0] b_arg, input [7:0] cc_arg); -reg [7:0] cc_out; -reg [15:0] ALUFn; -reg carry; -reg borrow; -begin - cc_out = cc_arg; - case (operation16) - ALUOP16_ADD: - begin - {cc_out[CC_C_BIT], ALUFn} = {1'b0, a_arg} + b_arg; - cc_out[CC_V_BIT] = (a_arg[15] & b_arg[15] & ~ALUFn[15]) | (~a_arg[15] & ~b_arg[15] & ALUFn[15]); - end - - ALUOP16_SUB: - begin - {cc_out[CC_C_BIT], ALUFn} = {1'b0, a_arg} - {1'b0, b_arg}; - cc_out[CC_V_BIT] = (a_arg[15] & ~b_arg[15] & ~ALUFn[15]) | (~a_arg[15] & b_arg[15] & ALUFn[15]); - end - - ALUOP16_LD: - begin - ALUFn = b_arg; - cc_out[CC_V_BIT] = 1'b0; - end - - ALUOP16_CMP: - begin - {cc_out[CC_C_BIT], ALUFn} = {1'b0, a_arg} - {1'b0, b_arg}; - cc_out[CC_V_BIT] = (a_arg[15] & ~b_arg[15] & ~ALUFn[15]) | (~a_arg[15] & b_arg[15] & ALUFn[15]); - end - - ALUOP16_LEA: - begin - ALUFn = a_arg; - end - - default: - ALUFn = 16'H0000; - - endcase - cc_out[CC_Z_BIT] = (ALUFn[15:0] == 16'H0000); - if (operation16 != ALUOP16_LEA) - cc_out[CC_N_BIT] = ALUFn[15]; - ALU16Inst = {cc_out, ALUFn}; -end -endfunction - -reg [2:0] ALU16_OP; -reg [15:0] ALU16_A; -reg [15:0] ALU16_B; -reg [7:0] ALU16_CC; - -// Top 8 bits == CC, bottom 8 bits = output value -wire [23:0] ALU16 = ALU16Inst(ALU16_OP, ALU16_A, ALU16_B, ALU16_CC); - - -///////////////////////////////////////////////////////////////// -// ALU - -// The ops are organized from the 4 low-order bits of the instructions for the first set of ops, then 16-31 are the second set - even though bit 4 isn't representative. -localparam ALUOP_NEG = 5'd0; -localparam ALUOP_COM = 5'd3; -localparam ALUOP_LSR = 5'd4; -localparam ALUOP_ROR = 5'd6; -localparam ALUOP_ASR = 5'd7; -localparam ALUOP_ASL = 5'd8; -localparam ALUOP_LSL = 5'd8; -localparam ALUOP_ROL = 5'd9; -localparam ALUOP_DEC = 5'd10; -localparam ALUOP_INC = 5'd12; -localparam ALUOP_TST = 5'd13; -localparam ALUOP_CLR = 5'd15; - -localparam ALUOP_SUB = 5'd16; -localparam ALUOP_CMP = 5'd17; -localparam ALUOP_SBC = 5'd18; -localparam ALUOP_AND = 5'd20; -localparam ALUOP_BIT = 5'd21; -localparam ALUOP_LD = 5'd22; -localparam ALUOP_EOR = 5'd24; -localparam ALUOP_ADC = 5'd25; -localparam ALUOP_OR = 5'd26; -localparam ALUOP_ADD = 5'd27; - -function [5:0] ALUOpFromInst(input [7:0] inst); -reg [4:0] op; -reg writeback; -begin - // Okay, this turned out to be simpler than I expected ... - op = {inst[7], inst[3:0]}; - case (op) - ALUOP_CMP: - writeback = 0; - ALUOP_TST: - writeback = 0; - ALUOP_BIT: - writeback = 0; - default: - writeback = 1; - endcase - ALUOpFromInst = {writeback, op}; -end -endfunction - -wire [4:0] ALU8Op; -wire ALU8Writeback; - -assign {ALU8Writeback, ALU8Op} = ALUOpFromInst(Inst1); - -reg [7:0] ALU_A; -reg [7:0] ALU_B; -reg [7:0] ALU_CC; -reg [4:0] ALU_OP; - - -function [15:0] ALUInst(input [4:0] operation, input [7:0] a_arg, input [7:0] b_arg, input [7:0] cc_arg); -reg [7:0] cc_out; -reg [7:0] ALUFn; -reg carry; -reg borrow; -begin - cc_out = cc_arg; - case (operation) - ALUOP_NEG: - begin - ALUFn[7:0] = ~a_arg + 1'b1; - cc_out[CC_C_BIT] = (ALUFn[7:0] != 8'H00); - cc_out[CC_V_BIT] = (a_arg == 8'H80); - end - - ALUOP_LSL: - begin - {cc_out[CC_C_BIT], ALUFn} = {a_arg, 1'b0}; - cc_out[CC_V_BIT] = a_arg[7] ^ a_arg[6]; - end - - ALUOP_LSR: - begin - {ALUFn, cc_out[CC_C_BIT]} = {1'b0, a_arg}; - end - - ALUOP_ASR: - begin - {ALUFn, cc_out[CC_C_BIT]} = {a_arg[7], a_arg}; - end - - ALUOP_ROL: - begin - {cc_out[CC_C_BIT], ALUFn} = {a_arg, cc_arg[CC_C_BIT]}; - cc_out[CC_V_BIT] = a_arg[7] ^ a_arg[6]; - end - - ALUOP_ROR: - begin - {ALUFn, cc_out[CC_C_BIT]} = {cc_arg[CC_C_BIT], a_arg}; - end - - ALUOP_OR: - begin - ALUFn[7:0] = (a_arg | b_arg); - cc_out[CC_V_BIT] = 1'b0; - end - - ALUOP_ADD: - begin - {cc_out[CC_C_BIT], ALUFn[7:0]} = {1'b0, a_arg} + {1'b0, b_arg}; - cc_out[CC_V_BIT] = (a_arg[7] & b_arg[7] & ~ALUFn[7]) | (~a_arg[7] & ~b_arg[7] & ALUFn[7]); - cc_out[CC_H_BIT] = a_arg[4] ^ b_arg[4] ^ ALUFn[4]; - end - - ALUOP_SUB: - begin - {cc_out[CC_C_BIT], ALUFn[7:0]} = {1'b0, a_arg} - {1'b0, b_arg}; - cc_out[CC_V_BIT] = (a_arg[7] & ~b_arg[7] & ~ALUFn[7]) | (~a_arg[7] & b_arg[7] & ALUFn[7]); - end - - ALUOP_AND: - begin - ALUFn[7:0] = (a_arg & b_arg); - cc_out[CC_V_BIT] = 1'b0; - end - - ALUOP_BIT: - begin - ALUFn[7:0] = (a_arg & b_arg); - cc_out[CC_V_BIT] = 1'b0; - end - - ALUOP_EOR: - begin - ALUFn[7:0] = (a_arg ^ b_arg); - cc_out[CC_V_BIT] = 1'b0; - end - - ALUOP_CMP: - begin - {cc_out[CC_C_BIT], ALUFn[7:0]} = {1'b0, a_arg} - {1'b0, b_arg}; - cc_out[CC_V_BIT] = (a_arg[7] & ~b_arg[7] & ~ALUFn[7]) | (~a_arg[7] & b_arg[7] & ALUFn[7]); - end - - ALUOP_COM: - begin - ALUFn[7:0] = ~a_arg; - cc_out[CC_V_BIT] = 1'b0; - cc_out[CC_C_BIT] = 1'b1; - end - - ALUOP_ADC: - begin - {cc_out[CC_C_BIT], ALUFn[7:0]} = {1'b0, a_arg} + {1'b0, b_arg} + cc_arg[CC_C_BIT]; - cc_out[CC_V_BIT] = (a_arg[7] & b_arg[7] & ~ALUFn[7]) | (~a_arg[7] & ~b_arg[7] & ALUFn[7]); - cc_out[CC_H_BIT] = a_arg[4] ^ b_arg[4] ^ ALUFn[4]; - end - - ALUOP_LD: - begin - ALUFn[7:0] = b_arg; - cc_out[CC_V_BIT] = 1'b0; - end - - ALUOP_INC: - begin - {carry, ALUFn} = {1'b0, a_arg} + 1'b1; - cc_out[CC_V_BIT] = (~a_arg[7] & ALUFn[7]); - end - - ALUOP_DEC: - begin - {carry, ALUFn[7:0]} = {1'b0, a_arg} - 1'b1; - cc_out[CC_V_BIT] = (a_arg[7] & ~ALUFn[7]); - end - - ALUOP_CLR: - begin - ALUFn[7:0] = 8'H00; - cc_out[CC_V_BIT] = 1'b0; - cc_out[CC_C_BIT] = 1'b0; - end - - ALUOP_TST: - begin - ALUFn[7:0] = a_arg; - cc_out[CC_V_BIT] = 1'b0; - end - - ALUOP_SBC: - begin - {cc_out[CC_C_BIT], ALUFn[7:0]} = {1'b0, a_arg} - {1'b0, b_arg} - cc_arg[CC_C_BIT]; - cc_out[CC_V_BIT] = (a_arg[7] & ~b_arg[7] & ~ALUFn[7]) | (~a_arg[7] & b_arg[7] & ALUFn[7]); - end - - default: - ALUFn = 8'H00; - - endcase - - cc_out[CC_N_BIT] = ALUFn[7]; - cc_out[CC_Z_BIT] = (ALUFn == 8'H00); - ALUInst = {cc_out[7:0], ALUFn[7:0]}; -end -endfunction - - -// Top 8 bits == CC, bottom 8 bits = output value -wire [15:0] ALU = ALUInst(ALU_OP, ALU_A, ALU_B, ALU_CC); - -//////////////////////////////////////////////////////////// - -localparam TYPE_INHERENT = 3'd0; -localparam TYPE_IMMEDIATE = 3'd1; -localparam TYPE_DIRECT = 3'd2; -localparam TYPE_RELATIVE = 3'd3; -localparam TYPE_INDEXED = 3'd4; -localparam TYPE_EXTENDED = 3'd5; - -localparam TYPE_INVALID = 3'd7; - -// Function to decode the addressing mode the instruction uses -function [2:0] addressing_mode_type(input [7:0] inst); -begin - casex (inst) - 8'b0000???? : addressing_mode_type = TYPE_DIRECT; - 8'b0001???? : - begin - casex (inst[3:0]) - 4'b0010: - addressing_mode_type = TYPE_INHERENT; - - 4'b0011: - addressing_mode_type = TYPE_INHERENT; - - 4'b1001: - addressing_mode_type = TYPE_INHERENT; - - 4'b1101: - addressing_mode_type = TYPE_INHERENT; - - 4'b0110: - addressing_mode_type = TYPE_RELATIVE; - - 4'b0111: - addressing_mode_type = TYPE_RELATIVE; - - 4'b1010: - addressing_mode_type = TYPE_IMMEDIATE; - - 4'b1100: - addressing_mode_type = TYPE_IMMEDIATE; - - 4'b1110: - addressing_mode_type = TYPE_IMMEDIATE; - - 4'b1111: - addressing_mode_type = TYPE_IMMEDIATE; - - default: - addressing_mode_type = TYPE_INVALID; - endcase - end - - 8'b0010????: addressing_mode_type = TYPE_RELATIVE; - 8'b0011????: - begin - casex(inst[3:0]) - 4'b00??: - addressing_mode_type = TYPE_INDEXED; - - 4'b01??: - addressing_mode_type = TYPE_IMMEDIATE; - - 4'b1001: - addressing_mode_type = TYPE_INHERENT; - - 4'b101?: - addressing_mode_type = TYPE_INHERENT; - - 4'b1100: - addressing_mode_type = TYPE_INHERENT; - - 4'b1101: - addressing_mode_type = TYPE_INHERENT; - - 4'b1111: - addressing_mode_type = TYPE_INHERENT; - - default: - addressing_mode_type = TYPE_INVALID; - endcase - end - - 8'b010?????: addressing_mode_type = TYPE_INHERENT; - - 8'b0110????: addressing_mode_type = TYPE_INDEXED; - - 8'b0111????: addressing_mode_type = TYPE_EXTENDED; - - 8'b1000????: - begin - casex (inst[3:0]) - 4'b0111: addressing_mode_type = TYPE_INVALID; - 4'b1111: addressing_mode_type = TYPE_INVALID; - 4'b1101: addressing_mode_type = TYPE_RELATIVE; - default: addressing_mode_type = TYPE_IMMEDIATE; - endcase - end - - 8'b1001????: addressing_mode_type = TYPE_DIRECT; - 8'b1010????: addressing_mode_type = TYPE_INDEXED; - 8'b1011????: addressing_mode_type = TYPE_EXTENDED; - 8'b1100????: addressing_mode_type = TYPE_IMMEDIATE; - 8'b1101????: addressing_mode_type = TYPE_DIRECT; - 8'b1110????: addressing_mode_type = TYPE_INDEXED; - 8'b1111????: addressing_mode_type = TYPE_EXTENDED; - - endcase -end -endfunction - -wire [2:0] AddrModeType = addressing_mode_type(Inst1); - -////////////////////////////////////////////////// - -// Individual opcodes that are the top of a column of states. - -localparam OPCODE_INH_ABX = 8'H3A; -localparam OPCODE_INH_RTS = 8'H39; -localparam OPCODE_INH_RTI = 8'H3B; -localparam OPCODE_INH_CWAI = 8'H3C; -localparam OPCODE_INH_MUL = 8'H3D; -localparam OPCODE_INH_SWI = 8'H3F; -localparam OPCODE_INH_SEX = 8'H1D; -localparam OPCODE_INH_NOP = 8'H12; -localparam OPCODE_INH_SYNC = 8'H13; -localparam OPCODE_INH_DAA = 8'H19; - -localparam OPCODE_IMM_ORCC = 8'H1A; -localparam OPCODE_IMM_ANDCC = 8'H1C; -localparam OPCODE_IMM_EXG = 8'H1E; -localparam OPCODE_IMM_TFR = 8'H1F; -localparam OPCODE_IMM_PSHS = 8'H34; -localparam OPCODE_IMM_PULS = 8'H35; -localparam OPCODE_IMM_PSHU = 8'H36; -localparam OPCODE_IMM_PULU = 8'H37; - -localparam OPCODE_IMM_SUBD = 8'H83; -localparam OPCODE_IMM_CMPX = 8'H8C; -localparam OPCODE_IMM_LDX = 8'H8E; -localparam OPCODE_IMM_ADDD = 8'HC3; -localparam OPCODE_IMM_LDD = 8'HCC; -localparam OPCODE_IMM_LDU = 8'HCE; -localparam OPCODE_IMM_CMPD = 8'H83; // Page2 -localparam OPCODE_IMM_CMPY = 8'H8C; // Page2 -localparam OPCODE_IMM_LDY = 8'H8E; // Page2 -localparam OPCODE_IMM_LDS = 8'HCE; // Page2 -localparam OPCODE_IMM_CMPU = 8'H83; // Page3 -localparam OPCODE_IMM_CMPS = 8'H8C; // Page3 - -localparam EXGTFR_REG_D = 4'H0; -localparam EXGTFR_REG_X = 4'H1; -localparam EXGTFR_REG_Y = 4'H2; -localparam EXGTFR_REG_U = 4'H3; -localparam EXGTFR_REG_S = 4'H4; -localparam EXGTFR_REG_PC = 4'H5; -localparam EXGTFR_REG_A = 4'H8; -localparam EXGTFR_REG_B = 4'H9; -localparam EXGTFR_REG_CC = 4'HA; -localparam EXGTFR_REG_DP = 4'HB; - -function IsALU8Set0(input [7:0] instr); -reg result; -reg [3:0] hi; -reg [3:0] lo; -begin - hi = instr[7:4]; - lo = instr[3:0]; - if ( (hi == 4'H0) || (hi == 4'H4) || (hi == 4'H5) || (hi == 4'H6) || (hi == 4'H7) ) - begin - if ( (lo != 4'H1) && (lo != 4'H2) && (lo != 4'H5) && (lo != 4'HB) && (lo != 4'HE) ) // permit NEG, COM, LSR, ROR, ASR, ASL/LSL, ROL, DEC, INC, TST, CLR - result = 1; - else - result = 0; - end - else - result = 0; - IsALU8Set0 = result; -end -endfunction - -function IsALU8Set1(input [7:0] instr); -reg result; -reg [3:0] hi; -reg [3:0] lo; -begin - hi = instr[7:4]; - lo = instr[3:0]; - if ( (hi >= 4'H8) ) - begin - if ( (lo <= 4'HB) && (lo != 4'H3) && (lo != 4'H7) ) // 8-bit SUB, CMP, SBC, AND, BIT, LD, EOR, ADC, OR, ADD - result = 1; - else - result = 0; - end - else - result = 0; - IsALU8Set1 = result; -end -endfunction - -// Determine if the instruction is performing an 8-bit op (ALU only) -function ALU8BitOp(input [7:0] instr); -begin - ALU8BitOp = IsALU8Set0(instr) | IsALU8Set1(instr); -end -endfunction - -wire Is8BitInst = ALU8BitOp(Inst1); - -function IsRegA(input [7:0] instr); -reg result; -reg [3:0] hi; -begin - hi = instr[7:4]; - if ((hi == 4'H4) || (hi == 4'H8) || (hi == 4'H9) || (hi == 4'HA) || (hi == 4'HB) ) - result = 1; - else - result = 0; - IsRegA = result; -end -endfunction - -wire IsTargetRegA = IsRegA(Inst1); - -// -// -// Decode -// 00-0F = DIRECT -// 10-1F = INHERENT, RELATIVE, IMMEDIATE -// 20-2F = RELATIVE -// 30-3F = INDEXED, IMMEDIATE (pus, pul), INHERENT -// 40-4F = INHERENT -// 50-5F = INHERENT -// 60-6F = INDEXED -// 70-7F = EXTENDED -// 80-8F = IMMEDIATE, RELATIVE (BSR) -// 90-9F = DIRECT -// A0-AF = INDEXED -// B0-BF = EXTENDED -// C0-CF = IMMEDIATE -// D0-DF = DIRECT -// E0-EF = INDEXED -// F0-FF = EXTENDED - -// DIRECT; 00-0F, 90-9F, D0-DF -// INHERENT; 10-1F (12, 13, 19, 1D), 30-3F (39-3F), 40-4F, 50-5F, -// RELATIVE: 10-1F (16, 17), 20-2F, 80-8F (8D) -// IMMEDIATE: 10-1F (1A, 1C, 1E, 1F), 30-3F (34-37), 80-8F (80-8C, 8E), C0-CF -// INDEXED: 60-6F, A0-AF, E0-EF -// EXTENDED: 70-7F, B0-Bf, F0-FF - -localparam INST_LBRA = 8'H16; // always -- shitty numbering, damnit -localparam INST_LBSR = 8'H17; // - -localparam INST_BRA = 8'H20; // always -localparam INST_BRN = 8'H21; // never -localparam INST_BHI = 8'H22; // CC.Z = 0 && CC.C = 0 -localparam INST_BLS = 8'H23; // CC.Z != 0 && CC.C != 0 -localparam INST_BCC = 8'H24; // CC.C = 0 -localparam INST_BHS = 8'H24; // same as BCC -localparam INST_BCS = 8'H25; // CC.C = 1 -localparam INST_BLO = 8'H25; // same as BCS -localparam INST_BNE = 8'H26; // CC.Z = 0 -localparam INST_BEQ = 8'H27; // CC.Z = 1 -localparam INST_BVC = 8'H28; // V = 1 -localparam INST_BVS = 8'H29; // V = 0 -localparam INST_BPL = 8'H2A; // CC.N = 0 -localparam INST_BMI = 8'H2B; // CC.N = 1 -localparam INST_BGE = 8'H2C; // CC.N = CC.V -localparam INST_BLT = 8'H2D; // CC.N != CC.V -localparam INST_BGT = 8'H2E; // CC.N = CC.V && CC.Z = 0 -localparam INST_BLE = 8'H2F; // CC.N != CC.V && CC.Z = 1 -localparam INST_BSR = 8'H8D; // always - -localparam NYB_BRA = 4'H0; // always -localparam NYB_BRN = 4'H1; // never -localparam NYB_BHI = 4'H2; // CC.Z = 0 && CC.C = 0 -localparam NYB_BLS = 4'H3; // CC.Z != 0 && CC.C != 0 -localparam NYB_BCC = 4'H4; // CC.C = 0 -localparam NYB_BHS = 4'H4; // same as BCC -localparam NYB_BCS = 4'H5; // CC.C = 1 -localparam NYB_BLO = 4'H5; // same as BCS -localparam NYB_BNE = 4'H6; // CC.Z = 0 -localparam NYB_BEQ = 4'H7; // CC.Z = 1 -localparam NYB_BVC = 4'H8; // V = 0 -localparam NYB_BVS = 4'H9; // V = 1 -localparam NYB_BPL = 4'HA; // CC.N = 0 -localparam NYB_BMI = 4'HB; // CC.N = 1 -localparam NYB_BGE = 4'HC; // CC.N = CC.V -localparam NYB_BLT = 4'HD; // CC.N != CC.V -localparam NYB_BGT = 4'HE; // CC.N = CC.V && CC.Z = 0 -localparam NYB_BLE = 4'HF; // CC.N != CC.V && CC.Z = 1 - - - -function take_branch(input [7:0] Inst1, input [7:0] cc); -begin - take_branch = 0; //default - if ( (Inst1 == INST_BSR) || (Inst1 == INST_LBSR) || (Inst1 == INST_LBRA) ) - take_branch = 1; - else - case (Inst1[3:0]) - NYB_BRA: - take_branch = 1; - NYB_BRN: - take_branch = 0; - NYB_BHI: - if ( ( cc[CC_Z_BIT] | cc[CC_C_BIT] ) == 0) - take_branch = 1; - NYB_BLS: - if ( cc[CC_Z_BIT] | cc[CC_C_BIT] ) - take_branch = 1; - NYB_BCC: - if ( cc[CC_C_BIT] == 0 ) - take_branch = 1; - NYB_BCS: - if ( cc[CC_C_BIT] == 1 ) - take_branch = 1; - NYB_BNE: - if ( cc[CC_Z_BIT] == 0 ) - take_branch = 1; - NYB_BEQ: - if ( cc[CC_Z_BIT] == 1 ) - take_branch = 1; - NYB_BVC: - if ( cc[CC_V_BIT] == 0) - take_branch = 1; - NYB_BVS: - if ( cc[CC_V_BIT] == 1) - take_branch = 1; - NYB_BPL: - if ( cc[CC_N_BIT] == 0 ) - take_branch = 1; - NYB_BMI: - if (cc[CC_N_BIT] == 1) - take_branch = 1; - NYB_BGE: - if ((cc[CC_N_BIT] ^ cc[CC_V_BIT]) == 0) - take_branch = 1; - NYB_BLT: - if ((cc[CC_N_BIT] ^ cc[CC_V_BIT]) == 1) - take_branch = 1; - NYB_BGT: - if ( ((cc[CC_N_BIT] ^ cc[CC_V_BIT]) == 0) & (cc[CC_Z_BIT] == 0) ) - take_branch = 1; - NYB_BLE: - if ( ((cc[CC_N_BIT] ^ cc[CC_V_BIT]) == 1) | (cc[CC_Z_BIT] == 1) ) - take_branch = 1; - endcase -end -endfunction - -wire TakeBranch = take_branch(Inst1, cc); - -///////////////////////////////////////////////////////////////////// -// Convenience function for knowing the contents for TFR, EXG -function [15:0] EXGTFRRegister(input [3:0] regid); -begin - case (regid) - EXGTFR_REG_D: - EXGTFRRegister = {a, b}; - EXGTFR_REG_X: - EXGTFRRegister = x; - EXGTFR_REG_Y: - EXGTFRRegister = y; - EXGTFR_REG_U: - EXGTFRRegister = u; - EXGTFR_REG_S: - EXGTFRRegister = s; - EXGTFR_REG_PC: - EXGTFRRegister = pc_p1; // For both EXG and TFR, this is used on the 2nd byte in the instruction's cycle. The PC intended to transfer is actually the next byte. - EXGTFR_REG_DP: - EXGTFRRegister = {8'HFF, dp}; - EXGTFR_REG_A: - EXGTFRRegister = {8'HFF, a}; - EXGTFR_REG_B: - EXGTFRRegister = {8'HFF, b}; - EXGTFR_REG_CC: - EXGTFRRegister = {8'HFF, cc}; - default: - EXGTFRRegister = 16'H0; - endcase -end -endfunction -wire [15:0] EXGTFRRegA = EXGTFRRegister(D[7:4]); -wire [15:0] EXGTFRRegB = EXGTFRRegister(D[3:0]); - -// CPU state machine -always @(*) -begin - rLIC = 1'b0; - rAVMA = 1'b1; - rBUSY = 1'b0; - - addr_nxt = 16'HFFFF; - pc_p1 = (pc+16'H1); - pc_p2 = (pc+16'H2); - pc_p3 = (pc+16'H3); - s_p1 = (s+16'H1); - s_m1 = (s-16'H1); - u_p1 = (u+16'H1); - u_m1 = (u-16'H1); - addr_p1 = (addr+16'H1); - ea_p1 = (ea+16'H1); - BS_nxt = 1'b0; - BA_nxt = 1'b0; - - // These may be overridden below, but the "next" version by default should be - // the last latched version. - IntType_nxt = IntType; - NMIClear_nxt = NMIClear; - NextState_nxt = NextState; - a_nxt = a; - b_nxt = b; - x_nxt = x; - y_nxt = y; - s_nxt = s; - u_nxt = u; - cc_nxt = cc; - dp_nxt = dp; - pc_nxt = pc; - tmp_nxt = tmp; - ea_nxt = ea; - - ALU_A = 8'H00; - ALU_B = 8'H00; - ALU_CC = 8'H00; - ALU_OP = 5'H00; - - ALU16_OP = 3'H0; - ALU16_A = 16'H0000; - ALU16_B = 16'H0000; - ALU16_CC = 8'H00; - - DOutput = 8'H00; - RnWOut = 1'b1; // read - - Inst1_nxt = Inst1; - Inst2_nxt = Inst2; - Inst3_nxt = Inst3; - InstPage2_nxt = InstPage2; - InstPage3_nxt = InstPage3; - - CpuState_nxt = CpuState; - - case (CpuState) - CPUSTATE_RESET: - begin - addr_nxt = 16'HFFFF; - a_nxt = 0; - b_nxt = 0; - x_nxt = 0; - y_nxt = 0; - s_nxt = 16'HFFFD; // Take care about removing the reset of S. There's logic depending on the delta between s and s_nxt to clear NMIMask. - u_nxt = 0; - cc_nxt = CC_F | CC_I; // reset disables interrupts - dp_nxt = 0; - ea_nxt = 16'HFFFF; - - RnWOut = 1; // read - rLIC = 1'b0; // Instruction incomplete - NMIClear_nxt= 1'b0; - IntType_nxt = 3'b111; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_RESET0; - end - - CPUSTATE_RESET0: - begin - addr_nxt = `RESET_VECTOR; - rBUSY = 1'b1; - pc_nxt[15:8] = D[7:0]; - BS_nxt = 1'b1; // ACK RESET - rAVMA = 1'b1; - rLIC = 1'b1; - CpuState_nxt = CPUSTATE_RESET2; - end - - CPUSTATE_RESET2: - begin - addr_nxt = addr_p1; - BS_nxt = 1'b1; // ACK RESET - pc_nxt[7:0] = D[7:0]; - rAVMA = 1'b1; - rLIC = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_FETCH_I1: - begin - if (~DMABREQLatched) - begin - addr_nxt = pc; - RnWOut = 1'b1; - rAVMA = 1'b0; - tmp_nxt = {tmp[15:4], 4'b1111}; - BS_nxt = 1'b1; - BA_nxt = 1'b1; - rLIC = 1'b1; - CpuState_nxt = CPUSTATE_DMABREQ; - end - else if (~HALTLatched) - begin - addr_nxt = pc; - RnWOut = 1'b1; - rAVMA = 1'b0; - BS_nxt = 1'b1; - BA_nxt = 1'b1; - rLIC = 1'b1; - CpuState_nxt = CPUSTATE_HALTED; - end - else // not halting, run the inst byte fetch - begin - addr_nxt = pc; // Set the address bus for the next instruction, first byte - pc_nxt = pc_p1; - RnWOut = 1; // Set for a READ - Inst1_nxt = MappedInstruction; - InstPage2_nxt = 0; - InstPage3_nxt = 0; - - // New instruction fetch; service interrupts pending - if (NMILatched == 0) - begin - pc_nxt = pc; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_NMI_START; - end - else if ((FIRQLatched == 0) && (cc[CC_F_BIT] == 0)) - begin - pc_nxt = pc; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FIRQ_START; - end - else if ((IRQLatched == 0) && (cc[CC_I_BIT] == 0)) - begin - pc_nxt = pc; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_IRQ_START; - end - - // The actual 1st byte checks - else if (Inst1_nxt == 8'H10) // Page 2 Note, like the 6809, $10 $10 $10 $10 has the same effect as a single $10. - begin - InstPage2_nxt = 1; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1V2; - end - else if (Inst1_nxt == 8'H11) // Page 3 - begin - InstPage3_nxt = 1; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1V2; - end - else - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I2; - end - end // if not halting - end - - CPUSTATE_FETCH_I1V2: - begin - addr_nxt = pc; // Set the address bus for the next instruction, first byte - pc_nxt = pc_p1; - RnWOut = 1; // Set for a READ - Inst1_nxt = MappedInstruction; - - if (Inst1_nxt == 8'H10) // Page 2 Note, like the 6809, $10 $10 $10 $10 has the same effect as a single $10. - begin - if (InstPage3 == 0) // $11 $11 $11 $11 ... $11 $10 still = Page 3 - InstPage2_nxt = 1; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1V2; - end - else if (Inst1_nxt == 8'H11) // Page 3 - begin - if (InstPage2 == 0) // $10 $10 ... $10 $11 still = Page 2 - InstPage3_nxt = 1; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1V2; - end - else - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I2; - end - end - - - CPUSTATE_FETCH_I2: // We've fetched the first byte. If a $10 or $11 (page select), mark those flags and fetch the next byte as instruction byte 1. - begin - addr_nxt = addr_p1; // Address bus++ - pc_nxt = pc_p1; - Inst2_nxt = D[7:0]; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - - if (IsIllegalInstruction) // Skip illegal instructions - begin - - rAVMA = 1'b1; - CpuState_nxt = IllegalInstructionState; - rLIC = 1'b1; - end - else - begin - // First byte Decode for this stage - case (AddrModeType) - TYPE_INDEXED: - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_INDEXED_BASE; - end - - - TYPE_EXTENDED: - begin - ea_nxt[15:8] = Inst2_nxt; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_EXTENDED_ADDRLO; - end - TYPE_DIRECT: - begin - ea_nxt = {dp, Inst2_nxt}; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_DIRECT_DONTCARE; - end - - TYPE_INHERENT: - begin - if (Inst1 == OPCODE_INH_NOP) - begin - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - else if (Inst1 == OPCODE_INH_DAA) // Bcd lunacy - begin - if ( ((cc[CC_C_BIT]) || (a[7:4] > 4'H9)) || - ((a[7:4] > 4'H8) && (a[3:0] > 4'H9)) ) - tmp_nxt[7:4] = 4'H6; - else - tmp_nxt[7:4] = 4'H0; - - if ((cc[CC_H_BIT]) || (a[3:0] > 4'H9)) - tmp_nxt[3:0] = 4'H6; - else - tmp_nxt[3:0] = 4'H0; - - // DAA handles carry in the weirdest way. - // If it's already set, it remains set, even if carry-out is 0. - // If it wasn't set, but the output of the operation is set, carry-out gets set. - {tmp_nxt[8], a_nxt} = {1'b0, a} + tmp_nxt[7:0]; - - cc_nxt[CC_C_BIT] = cc_nxt[CC_C_BIT] | tmp_nxt[8]; - - cc_nxt[CC_N_BIT] = a_nxt[7]; - cc_nxt[CC_Z_BIT] = (a_nxt == 8'H00); - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - else if (Inst1 == OPCODE_INH_SYNC) - begin - CpuState_nxt = CPUSTATE_SYNC; - rLIC = 1'b1; - rAVMA = 1'b0; - end - else if (Inst1 == OPCODE_INH_MUL) - begin - tmp_nxt = 16'H0000; - ea_nxt[15:8] = 8'H00; - ea_nxt[7:0] = a; - a_nxt = 8; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_MUL_ACTION; - end - else if (Inst1 == OPCODE_INH_RTS) - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_RTS_HI; - end - else if (Inst1 == OPCODE_INH_RTI) - begin - rAVMA = 1'b1; - tmp_nxt = 16'H1001; // Set tmp[12] to indicate an RTI being processed, and at least pull CC. - CpuState_nxt = CPUSTATE_PUL_ACTION; - NextState_nxt = CPUSTATE_FETCH_I1; - end - else if (Inst1 == OPCODE_INH_SWI) - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_SWI_START; - end - else if (Inst1 == OPCODE_INH_CWAI) - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_CWAI; - end - else if (Inst1 == OPCODE_INH_SEX) - begin - a_nxt = {8{b[7]}}; - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - else if (Inst1 == OPCODE_INH_ABX) - begin - x_nxt = x + b; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_ABX_DONTCARE; - end - else - begin - ALU_OP = ALU8Op; - if (IsTargetRegA) - ALU_A = a; - else - ALU_A = b; - - ALU_B = 0; - ALU_CC = cc; - cc_nxt = ALU[15:8]; - - if (ALU8Writeback) - begin - if (IsTargetRegA) - a_nxt = ALU[7:0]; - else - b_nxt = ALU[7:0]; - end - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - if (IsOneByteInstruction(Inst1)) // This check is probably superfluous. Every inherent instruction is 1 byte on the 6809. - pc_nxt = pc; // The 6809 auto-reads 2 bytes for every instruction. :( Adjust by not incrementing PC on the 2nd byte read. - end - - TYPE_IMMEDIATE: - begin - if (IsSpecialImmediate) - begin - if (Inst1 == OPCODE_IMM_ANDCC) - begin - pc_nxt = pc_p1; - cc_nxt = cc & D; //cc_nxt & Inst2_nxt; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_CC_DONTCARE; - end - else if (Inst1 == OPCODE_IMM_ORCC) - begin - pc_nxt = pc_p1; - cc_nxt = cc | D; //cc_nxt | Inst2_nxt; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_CC_DONTCARE; - end - else if ( (Inst1 == OPCODE_IMM_PSHS) | (Inst1 == OPCODE_IMM_PSHU) ) - begin - pc_nxt = pc_p1; - tmp_nxt[15] = 1'b0; - tmp_nxt[14] = Inst1[1]; // Mark whether to save to U or S. - tmp_nxt[13] = 1'b0; // Not pushing due to an interrupt. - tmp_nxt[13:8] = 6'H00; - tmp_nxt[7:0] = Inst2_nxt; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_PSH_DONTCARE1; - NextState_nxt = CPUSTATE_FETCH_I1; - end - else if ( (Inst1 == OPCODE_IMM_PULS) | (Inst1 == OPCODE_IMM_PULU) ) - begin - pc_nxt = pc_p1; - tmp_nxt[15] = 1'b0; - tmp_nxt[14] = Inst1[1]; // S (0) or U (1) stack in use. - tmp_nxt[13:8] = 6'H00; - tmp_nxt[7:0] = Inst2_nxt; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_PUL_DONTCARE1; - NextState_nxt = CPUSTATE_FETCH_I1; - end - else if (Inst1 == OPCODE_IMM_TFR) - begin - // The second byte lists the registers; Top nybble is reg #1, bottom is reg #2. - - case (Inst2_nxt[3:0]) - EXGTFR_REG_D: - {a_nxt,b_nxt} = EXGTFRRegA; - EXGTFR_REG_X: - x_nxt = EXGTFRRegA; - EXGTFR_REG_Y: - y_nxt = EXGTFRRegA; - EXGTFR_REG_U: - u_nxt = EXGTFRRegA; - EXGTFR_REG_S: - s_nxt = EXGTFRRegA; - EXGTFR_REG_PC: - pc_nxt = EXGTFRRegA; - EXGTFR_REG_DP: - dp_nxt = EXGTFRRegA[7:0]; - EXGTFR_REG_A: - a_nxt = EXGTFRRegA[7:0]; - EXGTFR_REG_B: - b_nxt = EXGTFRRegA[7:0]; - EXGTFR_REG_CC: - cc_nxt = EXGTFRRegA[7:0]; - default: - begin - end - endcase - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_TFR_DONTCARE1; - - end - else if (Inst1 == OPCODE_IMM_EXG) - begin - // The second byte lists the registers; Top nybble is reg #1, bottom is reg #2. - - case (Inst2_nxt[7:4]) - EXGTFR_REG_D: - {a_nxt,b_nxt} = EXGTFRRegB; - EXGTFR_REG_X: - x_nxt = EXGTFRRegB; - EXGTFR_REG_Y: - y_nxt = EXGTFRRegB; - EXGTFR_REG_U: - u_nxt = EXGTFRRegB; - EXGTFR_REG_S: - s_nxt = EXGTFRRegB; - EXGTFR_REG_PC: - pc_nxt = EXGTFRRegB; - EXGTFR_REG_DP: - dp_nxt = EXGTFRRegB[7:0]; - EXGTFR_REG_A: - a_nxt = EXGTFRRegB[7:0]; - EXGTFR_REG_B: - b_nxt = EXGTFRRegB[7:0]; - EXGTFR_REG_CC: - cc_nxt = EXGTFRRegB[7:0]; - default: - begin - end - endcase - case (Inst2_nxt[3:0]) - EXGTFR_REG_D: - {a_nxt,b_nxt} = EXGTFRRegA; - EXGTFR_REG_X: - x_nxt = EXGTFRRegA; - EXGTFR_REG_Y: - y_nxt = EXGTFRRegA; - EXGTFR_REG_U: - u_nxt = EXGTFRRegA; - EXGTFR_REG_S: - s_nxt = EXGTFRRegA; - EXGTFR_REG_PC: - pc_nxt = EXGTFRRegA; - EXGTFR_REG_DP: - dp_nxt = EXGTFRRegA[7:0]; - EXGTFR_REG_A: - a_nxt = EXGTFRRegA[7:0]; - EXGTFR_REG_B: - b_nxt = EXGTFRRegA[7:0]; - EXGTFR_REG_CC: - cc_nxt = EXGTFRRegA[7:0]; - default: - begin - end - endcase - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_EXG_DONTCARE1; - end - end - // Determine if this is an 8-bit ALU operation. - else if (Is8BitInst) - begin - ALU_OP = ALU8Op; - if (IsTargetRegA) - ALU_A = a; - else - ALU_A = b; - - ALU_B = Inst2_nxt; - ALU_CC = cc; - cc_nxt = ALU[15:8]; - - if (ALU8Writeback) - begin - if (IsTargetRegA) - a_nxt = ALU[7:0]; - else - b_nxt = ALU[7:0]; - end - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - else // Then it must be a 16 bit instruction - begin - // 83 SUBD - // 8C CMPX - // 8E LDX - // C3 ADDD - // CC LDD - // CE LDU - // 108E CMPD - // 108C CMPY - // 108E LDY - // 10CE LDS - // 1183 CMPU - // 118C CMPS - // Wow, they were just stuffing them in willy-nilly ... - - // LD* 16 bit immediate - if (IsALU16Opcode) - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_16IMM_LO; - end - // there's a dead zone here; I need an else to take us back to CPUSTATE_FETCHI1 if we want to ignore illegal instructions, to CPUSTATE_DEAD if we want to catch them. - - end - - end - - TYPE_RELATIVE: - begin - // Is this a LB** or a B**? - // If InstPage2 is set, it's a long branch; if clear, a normal branch. - if ( (InstPage2) || (Inst1 == INST_LBRA) || (Inst1 == INST_LBSR) ) - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_LBRA_OFFSETLOW; - end - else - begin - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_BRA_DONTCARE; - end - - end - default: - begin - CpuState_nxt = CPUSTATE_FETCH_I1; - end - endcase - end - end - - - CPUSTATE_LBRA_OFFSETLOW: - begin - addr_nxt = pc; - pc_nxt = pc_p1; - Inst3_nxt = D[7:0]; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_LBRA_DONTCARE; - end - - CPUSTATE_LBRA_DONTCARE: - begin - addr_nxt = 16'HFFFF; - if ( TakeBranch ) - begin - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_LBRA_DONTCARE2; - end - else - begin - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - end - - CPUSTATE_BRA_DONTCARE: - begin - addr_nxt = 16'HFFFF; - tmp_nxt = pc; - if (TakeBranch) - begin - pc_nxt = pc + { {8{Inst2[7]}}, Inst2[7:0]}; // Sign-extend the 8 bit offset to 16. - - if (Inst1 == INST_BSR) - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_BSR_DONTCARE1; - end - else - begin - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - end - else - begin - rLIC = 1'b1; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - end - - CPUSTATE_LBRA_DONTCARE2: - begin - tmp_nxt= pc; - addr_nxt = 16'HFFFF; - - // Take branch - pc_nxt = pc + {Inst2[7:0], Inst3[7:0]}; - if (Inst1 == INST_LBSR) - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_BSR_DONTCARE1; - end - else - begin - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - end - - CPUSTATE_BSR_DONTCARE1: - begin - addr_nxt = pc; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_BSR_DONTCARE2; - end - - CPUSTATE_BSR_DONTCARE2: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_BSR_RETURNLOW; - end - - CPUSTATE_BSR_RETURNLOW: - begin - addr_nxt = s_m1; - s_nxt = s_m1; - DOutput[7:0] = tmp[7:0]; - RnWOut = 0; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_BSR_RETURNHIGH; - end - - CPUSTATE_BSR_RETURNHIGH: - begin - addr_nxt = s_m1; - s_nxt = s_m1; - DOutput[7:0] = tmp[15:8]; - RnWOut = 0; - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; // after this, RnWOut must go to 1, and the bus needs the PC placed on it. - end - - CPUSTATE_TFR_DONTCARE1: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_TFR_DONTCARE2; - end - - CPUSTATE_TFR_DONTCARE2: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_TFR_DONTCARE3; - end - - CPUSTATE_TFR_DONTCARE3: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_TFR_DONTCARE4; - end - - CPUSTATE_TFR_DONTCARE4: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b1; - rLIC = 1'b1; // Instruction done! - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_EXG_DONTCARE1: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_EXG_DONTCARE2; - end - - CPUSTATE_EXG_DONTCARE2: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_EXG_DONTCARE3; - end - - CPUSTATE_EXG_DONTCARE3: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_EXG_DONTCARE4; - end - - CPUSTATE_EXG_DONTCARE4: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_EXG_DONTCARE5; - end - - CPUSTATE_EXG_DONTCARE5: - begin - rAVMA = 1'b0; - addr_nxt = 16'HFFFF; - CpuState_nxt = CPUSTATE_EXG_DONTCARE6; - end - - CPUSTATE_EXG_DONTCARE6: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b1; - rLIC = 1'b1; // Instruction done! - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_ABX_DONTCARE: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b1; - rLIC = 1'b1; // Instruction done! - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_RTS_HI: - begin - addr_nxt = s; - s_nxt = s_p1; - pc_nxt[15:8] = D[7:0]; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_RTS_LO; - end - - CPUSTATE_RTS_LO: - begin - addr_nxt = s; - s_nxt = s_p1; - pc_nxt[7:0] = D[7:0]; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_RTS_DONTCARE2; - end - - CPUSTATE_RTS_DONTCARE2: - begin - addr_nxt = 16'HFFFF; - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_16IMM_LO: - begin - addr_nxt = pc; - pc_nxt = pc_p1; - - ALU16_OP = ALU16Opcode; - ALU16_CC = cc; - ALU16_B = {Inst2, D[7:0]}; - - case (ALU16Reg) - ALU16_REG_X: - ALU16_A = x; - ALU16_REG_D: - ALU16_A = {a, b}; - ALU16_REG_Y: - ALU16_A = y; - ALU16_REG_U: - ALU16_A = u; - ALU16_REG_S: - ALU16_A = s; - default: - ALU16_A = 16'H0; - endcase - - if (ALU16OpWriteback) - begin - case (ALU16Reg) - ALU16_REG_X: - {cc_nxt, x_nxt} = ALU16; - ALU16_REG_D: - {cc_nxt, a_nxt, b_nxt} = ALU16; - ALU16_REG_Y: - {cc_nxt, y_nxt} = ALU16; - ALU16_REG_U: - {cc_nxt, u_nxt} = ALU16; - ALU16_REG_S: - {cc_nxt, s_nxt} = ALU16; - default: - begin - end - endcase - end - else - cc_nxt = ALU16[23:16]; - - if (ALU16_OP == ALUOP16_LD) - begin - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - else - begin - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_16IMM_DONTCARE; - end - end - - CPUSTATE_DIRECT_DONTCARE: - begin - addr_nxt = 16'HFFFF; - - if (IsJMP(Inst1)) - begin - pc_nxt = ea; - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - else - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_ALU_EA; - end - end - - CPUSTATE_ALU_EA: - begin - - // Is Figure 18/5 Column 2? JMP (not Immediate Mode) - // This actually isn't done here. All checks passing in to ALU_EA should check for a JMP; FIXME EVERYWHERE - - // Is Figure 18/5 Column 8? TST (not immediate mode) - // THIS IS BURIED IN THE COLUMN 3 section with comparisons to ALUOP_TST. - - // Is Figure 18/5 Column 3? - if (IsALU8Set1(Inst1)) - begin - addr_nxt = ea; - - ALU_OP = ALU8Op; - ALU_B = D[7:0]; - ALU_CC = cc; - - if (IsTargetRegA) - ALU_A = a; - else - ALU_A = b; - - cc_nxt = ALU[15:8]; - - if ( (ALU8Writeback) ) - begin - if (IsTargetRegA) - a_nxt = ALU[7:0]; - else - b_nxt = ALU[7:0]; - end - - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - // Is Figure 18/5 Column 4? (Store, 8 bits) - else if (IsStore8) - begin - addr_nxt = ea; - RnWOut = 0; // write - - ALU_OP = ALUOP_LD; // load has the same CC characteristics as store - ALU_A = 8'H00; - ALU_CC = cc; - - case (Store8RegisterNum) - ST8_REG_A: - begin - DOutput = a; - ALU_B = a; - end - ST8_REG_B: - begin - DOutput = b; - ALU_B = b; - end - - - endcase - - cc_nxt = ALU[15:8]; - - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - // Is Figure 18/5 Column 5? (Load, 16 bits) - else if (IsALU16Opcode & (ALU16Opcode == ALUOP16_LD)) - begin - addr_nxt = ea; - ea_nxt = ea_p1; - - case (ALU16Reg) - ALU16_REG_X: - x_nxt[15:8] = D[7:0]; - ALU16_REG_D: - a_nxt = D[7:0]; - ALU16_REG_Y: - y_nxt[15:8] = D[7:0]; - ALU16_REG_S: - s_nxt[15:8] = D[7:0]; - ALU16_REG_U: - u_nxt[15:8] = D[7:0]; - default: - begin - end - endcase - rAVMA = 1'b1; - rBUSY = 1'b1; - CpuState_nxt = CPUSTATE_LD16_LO; - - end - - // Is Figure 18/5 Column 6? (Store, 16 bits) - else if (IsStore16) - begin - addr_nxt = ea; - ea_nxt = ea_p1; - - ALU16_OP = ALUOP16_LD; // LD and ST have the same CC characteristics - ALU16_CC = cc; - ALU16_A = 8'H00; - - case (StoreRegisterNum) - ST16_REG_X: - begin - DOutput[7:0] = x[15:8]; - ALU16_B = x; - end - ST16_REG_Y: - begin - DOutput[7:0] = y[15:8]; - ALU16_B = y; - end - ST16_REG_U: - begin - DOutput[7:0] = u[15:8]; - ALU16_B = u; - end - ST16_REG_S: - begin - DOutput[7:0] = s[15:8]; - ALU16_B = s; - end - ST16_REG_D: - begin - DOutput[7:0] = a[7:0]; - ALU16_B = {a,b}; - end - default: - begin - end - endcase - - cc_nxt = ALU16[23:16]; - - RnWOut = 0; // Write - rAVMA = 1'b1; - rBUSY = 1'b1; - CpuState_nxt = CPUSTATE_ST16_LO; - end - - // Is Figure 18/5 Column 7? - else if (IsALU8Set0(Inst1)) - begin - // These are registerless instructions, ala - // ASL, ASR, CLR, COM, DEC, INC, (LSL), LSR, NEG, ROL, ROR - // and TST (special!) - // They require READ, Modify (the operation above), WRITE. Between the Read and the Write cycles, there's actually a /VMA - // cycle where the 6809 likely did the operation. We'll include a /VMA cycle for accuracy, but we'll do the work primarily in the first cycle. - addr_nxt = ea; - - ALU_OP = ALU8Op; - ALU_A = D[7:0]; - ALU_CC = cc; - tmp_nxt[15:8] = cc; // for debug only - tmp_nxt[7:0] = ALU[7:0]; - cc_nxt = ALU[15:8]; - if (ALU8Op == ALUOP_TST) - begin - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_TST_DONTCARE1; - end - else - begin - rAVMA = 1'b0; - rBUSY = 1'b1; - CpuState_nxt = CPUSTATE_ALU_DONTCARE; - end - - end - - // Is Figure 18/5 Column 8? TST - // NOTE: - // THIS IS BURIED IN THE COLUMN 3 section with comparisons to ALUOP_TST. [Directly above.] - - - // Is Figure 18/5 Column 9? (16-bit ALU ops, non-load) - else if (IsALU16Opcode && (ALU16Opcode != ALUOP16_LD) && ((Inst1 < 8'H30) || (Inst1 > 8'H33)) ) // 30-33 = LEAX, LEAY, LEAS, LEAU; don't include them here. - begin - addr_nxt = ea; - ea_nxt = ea_p1; - - tmp_nxt[15:8] = D[7:0]; - rAVMA = 1'b1; - rBUSY = 1'b1; - CpuState_nxt = CPUSTATE_ALU16_LO; - - end - - // Is Figure 18/5 Column 10? JSR (not Immediate Mode) - else if ((Inst1 == 8'H9D) || (Inst1 == 8'HAD) || (Inst1 == 8'HBD)) // JSR - begin - pc_nxt = ea; - addr_nxt = ea; - tmp_nxt = pc; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_JSR_DONTCARE; - end - // Is Figure 18/5 Column 11? LEA(X,Y,S,U) - else if ((Inst1 >= 8'H30) && (Inst1<= 8'H33)) - begin - addr_nxt = 16'HFFFF; // Ack, actually a valid cycle, this isn't a dontcare (/VMA) cycle! - - ALU16_OP = ALU16Opcode; - ALU16_CC = cc; - ALU16_A = ea; - - case (ALU16Reg) - ALU16_REG_X: - {cc_nxt, x_nxt} = ALU16; - ALU16_REG_Y: - {cc_nxt, y_nxt} = ALU16; - ALU16_REG_U: - u_nxt = ALU16[15:0]; - ALU16_REG_S: - s_nxt = ALU16[15:0]; - default: - begin - end - endcase - - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - - end - - end - - - CPUSTATE_ALU_DONTCARE: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b1; - rBUSY = 1'b1; // We do nothing here, but on the real 6809, they did the modify phase here. :| - CpuState_nxt = CPUSTATE_ALU_WRITEBACK; - end - - CPUSTATE_ALU_WRITEBACK: - begin - addr_nxt = ea; - RnWOut = 0; // Write - DOutput = tmp[7:0]; - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_LD16_LO: - begin - addr_nxt = ea; - - case (ALU16Reg) - ALU16_REG_X: - begin - x_nxt[7:0] = D[7:0]; - ALU16_B[15:8] = x[15:8]; - end - ALU16_REG_D: - begin - b_nxt = D[7:0]; - ALU16_B[15:8] = a; - end - ALU16_REG_Y: - begin - y_nxt[7:0] = D[7:0]; - ALU16_B[15:8] = y[15:8]; - end - ALU16_REG_S: - begin - s_nxt[7:0] = D[7:0]; - ALU16_B[15:8] = s[15:8]; - end - ALU16_REG_U: - begin - u_nxt[7:0] = D[7:0]; - ALU16_B[15:8] = u[15:8]; - end - default: - begin - end - - endcase - - ALU16_OP = ALU16Opcode; - ALU16_CC = cc; - ALU16_A = 8'H00; - ALU16_B[7:0] = D[7:0]; - cc_nxt = ALU16[23:16]; - - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_ST16_LO: - begin - addr_nxt = ea; - ea_nxt = ea_p1; - case (StoreRegisterNum) - ST16_REG_X: - DOutput[7:0] = x[7:0]; - ST16_REG_Y: - DOutput[7:0] = y[7:0]; - ST16_REG_U: - DOutput[7:0] = u[7:0]; - ST16_REG_S: - DOutput[7:0] = s[7:0]; - ST16_REG_D: - DOutput[7:0] = b[7:0]; - default: - begin - end - endcase - RnWOut = 0; // write - - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_ALU16_LO: - begin - addr_nxt = ea; - - ALU16_OP = ALU16Opcode; - ALU16_CC = cc; - - ALU16_B = {tmp[15:8], D[7:0]}; - - case (ALU16Reg) - ALU16_REG_X: - ALU16_A = x; - ALU16_REG_D: - ALU16_A = {a, b}; - ALU16_REG_Y: - ALU16_A = y; - ALU16_REG_S: - ALU16_A = s; - ALU16_REG_U: - ALU16_A = u; - default: - ALU16_A = 16'H0; - - endcase - - if (ALU16OpWriteback) - begin - case (ALU16Reg) - ALU16_REG_X: - {cc_nxt, x_nxt} = ALU16; - ALU16_REG_D: - {cc_nxt, a_nxt, b_nxt} = ALU16; - ALU16_REG_Y: - {cc_nxt, y_nxt} = ALU16; - ALU16_REG_U: - {cc_nxt, u_nxt} = ALU16; - ALU16_REG_S: - {cc_nxt, s_nxt} = ALU16; - default: - begin - end - endcase - end - else - cc_nxt = ALU16[23:16]; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_ALU16_DONTCARE; - end - - CPUSTATE_ALU16_DONTCARE: - begin - addr_nxt = 16'HFFFF; - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - - CPUSTATE_JSR_DONTCARE: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_JSR_RETLO; - end - - CPUSTATE_JSR_RETLO: - begin - addr_nxt = s_m1; - s_nxt = s_m1; - RnWOut = 0; - DOutput = tmp[7:0]; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_JSR_RETHI; - end - - CPUSTATE_JSR_RETHI: - begin - addr_nxt = s_m1; - s_nxt = s_m1; - RnWOut = 0; - DOutput = tmp[15:8]; - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_EXTENDED_ADDRLO: - begin - addr_nxt = pc; - pc_nxt = pc_p1; - ea_nxt[7:0] = D[7:0]; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_EXTENDED_DONTCARE; - end - - CPUSTATE_EXTENDED_DONTCARE: - begin - addr_nxt = 16'HFFFF; - if (IsJMP(Inst1)) - begin - pc_nxt = ea; - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - else - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_ALU_EA; - end - end - - CPUSTATE_INDEXED_BASE: - begin - addr_nxt = pc; - - Inst3_nxt = D[7:0]; - - case (IndexedRegister) - IDX_REG_X: - ALU16_A = x; - IDX_REG_Y: - ALU16_A = y; - IDX_REG_U: - ALU16_A = u; - IDX_REG_S: - ALU16_A = s; - IDX_REG_PC: - ALU16_A = pc_p1; - default: - ALU16_A = 16'H0; - endcase - ALU16_OP = ALUOP16_ADD; - - case (IndexedMode) - IDX_MODE_NOOFFSET: - begin - case (IndexedRegister) - IDX_REG_X: - ea_nxt = x; - IDX_REG_Y: - ea_nxt = y; - IDX_REG_U: - ea_nxt = u; - IDX_REG_S: - ea_nxt = s; - default: - ea_nxt = 16'H0; - endcase - - if (IndexedIndirect) - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_INDIRECT_HI; - end - else - begin - if (IsJMP(Inst1)) - begin - pc_nxt = ea_nxt; - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - else - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_ALU_EA; - end - end - end - - IDX_MODE_5BIT_OFFSET: - begin - // The offset is the bottom 5 bits of the Index Postbyte, which is Inst2 here. - // We'll sign-extend it to 16 bits. - ALU16_B = { {11{Inst2[4]}}, Inst2[4:0] }; - ea_nxt = ALU16[15:0]; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_IDX_DONTCARE3; - end - - - IDX_MODE_8BIT_OFFSET_PC: - begin - ALU16_B = { {8{D[7]}}, D[7:0] }; - pc_nxt = pc_p1; - ea_nxt = ALU16[15:0]; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_IDX_DONTCARE3; - end - - IDX_MODE_8BIT_OFFSET: - begin - ALU16_B = { {8{D[7]}}, D[7:0] }; - pc_nxt = pc_p1; - ea_nxt = ALU16[15:0]; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_IDX_DONTCARE3; - end - - IDX_MODE_A_OFFSET: - begin - ALU16_B = { {8{a[7]}}, a[7:0] }; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_IDX_DONTCARE3; - ea_nxt = ALU16[15:0]; - end - - IDX_MODE_B_OFFSET: - begin - ALU16_B = { {8{b[7]}}, b[7:0] }; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_IDX_DONTCARE3; - ea_nxt = ALU16[15:0]; - end - - IDX_MODE_D_OFFSET: - begin - ALU16_B = {a, b}; - - ea_nxt = ALU16[15:0]; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_IDX_DOFF_DONTCARE1; - end - - IDX_MODE_POSTINC1: - begin - ALU16_B = 16'H1; - ea_nxt = ALU16_A; - case (IndexedRegister) - IDX_REG_X: - x_nxt = ALU16[15:0]; - IDX_REG_Y: - y_nxt = ALU16[15:0]; - IDX_REG_U: - u_nxt = ALU16[15:0]; - IDX_REG_S: - s_nxt = ALU16[15:0]; - default: - begin - end - endcase - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_IDX_16OFF_DONTCARE2; - end - - IDX_MODE_POSTINC2: - begin - ALU16_B = 16'H2; - ea_nxt = ALU16_A; - case (IndexedRegister) - IDX_REG_X: - x_nxt = ALU16[15:0]; - IDX_REG_Y: - y_nxt = ALU16[15:0]; - IDX_REG_U: - u_nxt = ALU16[15:0]; - IDX_REG_S: - s_nxt = ALU16[15:0]; - default: - begin - end - endcase - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_IDX_16OFF_DONTCARE0; - end - - IDX_MODE_PREDEC1: - begin - ALU16_B = 16'HFFFF; // -1 - case (IndexedRegister) - IDX_REG_X: - x_nxt = ALU16[15:0]; - IDX_REG_Y: - y_nxt = ALU16[15:0]; - IDX_REG_U: - u_nxt = ALU16[15:0]; - IDX_REG_S: - s_nxt = ALU16[15:0]; - default: - begin - end - endcase - ea_nxt = ALU16[15:0]; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_IDX_16OFF_DONTCARE2; - end - - IDX_MODE_PREDEC2: - begin - ALU16_B = 16'HFFFE; // -2 - case (IndexedRegister) - IDX_REG_X: - x_nxt = ALU16[15:0]; - IDX_REG_Y: - y_nxt = ALU16[15:0]; - IDX_REG_U: - u_nxt = ALU16[15:0]; - IDX_REG_S: - s_nxt = ALU16[15:0]; - default: - begin - end - endcase - ea_nxt = ALU16[15:0]; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_IDX_16OFF_DONTCARE0; - end - - IDX_MODE_16BIT_OFFSET_PC: - begin - tmp_nxt[15:8] = D[7:0]; - pc_nxt = pc_p1; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_IDX_16OFFSET_LO; - end - - IDX_MODE_16BIT_OFFSET: - begin - tmp_nxt[15:8] = D[7:0]; - pc_nxt = pc_p1; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_IDX_16OFFSET_LO; - end - - IDX_MODE_EXTENDED_INDIRECT: - begin - ea_nxt[15:8] = D[7:0]; - pc_nxt = pc_p1; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_IDX_EXTIND_LO; - end - - default: - begin - rLIC = 1'b1; - CpuState_nxt = PostIllegalState; - end - - endcase - end - - CPUSTATE_IDX_OFFSET_LO: - begin - tmp_nxt[7:0] = D[7:0]; - addr_nxt = pc; - pc_nxt = pc_p1; - ALU16_B = tmp_nxt; - - case (IndexedRegister) - IDX_REG_X: - ALU16_A = x; - IDX_REG_Y: - ALU16_A = y; - IDX_REG_U: - ALU16_A = u; - IDX_REG_S: - ALU16_A = s; - IDX_REG_PC: - ALU16_A = pc; - default: - ALU16_A = 16'H0; - endcase - ALU16_OP = ALUOP16_ADD; - - ea_nxt = ALU16[15:0]; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_IDX_16OFF_DONTCARE1; - end - - - CPUSTATE_IDX_DONTCARE3: - begin - addr_nxt = 16'HFFFF; - if (IndexedIndirect) - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_INDIRECT_HI; - end - else - begin - if (IsJMP(Inst1)) - begin - pc_nxt = ea; - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - else - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_ALU_EA; - end - end - - end - - CPUSTATE_IDX_16OFFSET_LO: - begin - addr_nxt = pc; - pc_nxt = pc_p1; - - case (IndexedRegister) - IDX_REG_X: - ALU16_A = x; - IDX_REG_Y: - ALU16_A = y; - IDX_REG_U: - ALU16_A = u; - IDX_REG_S: - ALU16_A = s; - IDX_REG_PC: - ALU16_A = pc_nxt; // Whups; tricky; not part of the actual pattern - default: - ALU16_A = x; // Default to something - endcase - - ALU16_OP = ALUOP16_ADD; - - ALU16_B = {tmp[15:8], D[7:0]}; - - ea_nxt = ALU16[15:0]; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_IDX_16OFF_DONTCARE1; - end - - CPUSTATE_IDX_16OFF_DONTCARE1: - begin - addr_nxt = pc; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_IDX_16OFF_DONTCARE2; - end - - CPUSTATE_IDX_16OFF_DONTCARE0: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_IDX_16OFF_DONTCARE2; - end - - CPUSTATE_IDX_16OFF_DONTCARE2: - begin - addr_nxt = 16'HFFFF; - if (IndexedRegister == IDX_REG_PC) - begin - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_IDX_PC16OFF_DONTCARE; - end - else - begin - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_IDX_16OFF_DONTCARE3; - end - end - - CPUSTATE_IDX_PC16OFF_DONTCARE: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_IDX_16OFF_DONTCARE3; - end - - - CPUSTATE_IDX_16OFF_DONTCARE3: - begin - addr_nxt = 16'HFFFF; - if (IndexedIndirect) - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_INDIRECT_HI; - end - else - begin - if (IsJMP(Inst1)) - begin - pc_nxt = ea; - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - else - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_ALU_EA; - end - end - end - - CPUSTATE_IDX_DOFF_DONTCARE1: - begin - addr_nxt = pc_p1; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_IDX_DOFF_DONTCARE2; - end - - CPUSTATE_IDX_DOFF_DONTCARE2: - begin - addr_nxt = pc_p2; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_IDX_16OFF_DONTCARE2; - end - - CPUSTATE_IDX_DOFF_DONTCARE3: - begin - addr_nxt = pc_p3; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_IDX_DOFF_DONTCARE2; - end - - CPUSTATE_IDX_EXTIND_LO: - begin - ea_nxt[7:0] = D[7:0]; - addr_nxt = pc; - pc_nxt = pc_p1; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_IDX_EXTIND_DONTCARE; - end - - CPUSTATE_IDX_EXTIND_DONTCARE: - begin - addr_nxt = pc; - if (IndexedIndirect) - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_INDIRECT_HI; - end - else - begin - if (IsJMP(Inst1)) - begin - pc_nxt = ea; - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - else - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_ALU_EA; - end - end - end - - CPUSTATE_INDIRECT_HI: - begin - addr_nxt = ea; - tmp_nxt[15:8] = D[7:0]; - rAVMA = 1'b1; - rBUSY = 1'b1; - CpuState_nxt = CPUSTATE_INDIRECT_LO; - end - - CPUSTATE_INDIRECT_LO: - begin - addr_nxt = ea_p1; - ea_nxt[15:8] = tmp_nxt[15:8]; - ea_nxt[7:0] = D[7:0]; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_INDIRECT_DONTCARE; - end - - CPUSTATE_INDIRECT_DONTCARE: - begin - addr_nxt = 16'HFFFF; - if (IsJMP(Inst1)) - begin - pc_nxt = ea; - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - else - begin - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_ALU_EA; - end - end - - CPUSTATE_MUL_ACTION: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b0; - // tmp = result - // ea = additor (the shifted multiplicand) - // a = counter - // b is the multiplier (which gets shifted right) - if (a != 8'H00) - begin - if (b[0]) - begin - tmp_nxt = tmp + ea; - end - ea_nxt = {ea[14:0], 1'b0}; - b_nxt = {1'b0, b[7:1]}; - a_nxt = a - 8'H1; - end - else - begin - {a_nxt, b_nxt} = tmp; - - cc_nxt[CC_Z_BIT] = (tmp == 0); - cc_nxt[CC_C_BIT] = tmp[7]; - rLIC = 1'b1; // Instruction done! - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - end - - CPUSTATE_PSH_DONTCARE1: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_PSH_DONTCARE2; - end - - CPUSTATE_PSH_DONTCARE2: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_PSH_DONTCARE3; - end - - CPUSTATE_PSH_DONTCARE3: - begin - addr_nxt = (Inst1[1]) ? u : s; - - CpuState_nxt = CPUSTATE_PSH_ACTION; - end - - CPUSTATE_PSH_ACTION: - begin - rAVMA = 1'b1; - if (tmp[7] & ~(tmp[15])) // PC_LO - begin - addr_nxt = (tmp[14]) ? u_m1 : s_m1; - if (tmp[14]) - u_nxt = u_m1; - else - s_nxt = s_m1; - DOutput = pc[7:0]; - RnWOut = 1'b0; // write - tmp_nxt[15] = 1'b1; - end - else if (tmp[7] & (tmp[15])) // PC_HI - begin - addr_nxt = (tmp[14]) ? u_m1 : s_m1; - if (tmp[14]) - u_nxt = u_m1; - else - s_nxt = s_m1; - DOutput = pc[15:8]; - RnWOut = 1'b0; // write - tmp_nxt[7] = 1'b0; - tmp_nxt[15] = 1'b0; - end - else if (tmp[6] & ~(tmp[15])) // U/S_LO - begin - addr_nxt = (tmp[14]) ? u_m1 : s_m1; - if (tmp[14]) - u_nxt = u_m1; - else - s_nxt = s_m1; - DOutput = (tmp[14]) ? s[7:0] : u[7:0]; - RnWOut = 1'b0; // write - tmp_nxt[15] = 1'b1; - end - else if (tmp[6] & (tmp[15])) // U/S_HI - begin - addr_nxt = (tmp[14]) ? u_m1 : s_m1; - if (tmp[14]) - u_nxt = u_m1; - else - s_nxt = s_m1; - DOutput = (tmp[14]) ? s[15:8] : u[15:8]; - RnWOut = 1'b0; // write - tmp_nxt[6] = 1'b0; - tmp_nxt[15] = 1'b0; - end - else if (tmp[5] & ~(tmp[15])) // Y_LO - begin - addr_nxt = (tmp[14]) ? u_m1 : s_m1; - if (tmp[14]) - u_nxt = u_m1; - else - s_nxt = s_m1; - DOutput = y[7:0]; - RnWOut = 1'b0; // write - tmp_nxt[15] = 1'b1; - end - else if (tmp[5] & (tmp[15])) // Y_HI - begin - addr_nxt = (tmp[14]) ? u_m1 : s_m1; - if (tmp[14]) - u_nxt = u_m1; - else - s_nxt = s_m1; - DOutput = y[15:8]; - RnWOut = 1'b0; // write - tmp_nxt[5] = 1'b0; - tmp_nxt[15] = 1'b0; - end - else if (tmp[4] & ~(tmp[15])) // X_LO - begin - addr_nxt = (tmp[14]) ? u_m1 : s_m1; - if (tmp[14]) - u_nxt = u_m1; - else - s_nxt = s_m1; - DOutput = x[7:0]; - RnWOut = 1'b0; // write - tmp_nxt[15] = 1'b1; - end - else if (tmp[4] & (tmp[15])) // X_HI - begin - addr_nxt = (tmp[14]) ? u_m1 : s_m1; - if (tmp[14]) - u_nxt = u_m1; - else - s_nxt = s_m1; - DOutput = x[15:8]; - RnWOut = 1'b0; // write - tmp_nxt[4] = 1'b0; - tmp_nxt[15] = 1'b0; - end - else if (tmp[3]) // DP - begin - addr_nxt = (tmp[14]) ? u_m1 : s_m1; - if (tmp[14]) - u_nxt = u_m1; - else - s_nxt = s_m1; - DOutput = dp; - RnWOut = 1'b0; // write - tmp_nxt[3] = 1'b0; - end - else if (tmp[2]) // B - begin - addr_nxt = (tmp[14]) ? u_m1 : s_m1; - if (tmp[14]) - u_nxt = u_m1; - else - s_nxt = s_m1; - DOutput = b; - RnWOut = 1'b0; // write - tmp_nxt[2] = 1'b0; - end - else if (tmp[1]) // A - begin - addr_nxt = (tmp[14]) ? u_m1 : s_m1; - if (tmp[14]) - u_nxt = u_m1; - else - s_nxt = s_m1; - DOutput = a; - RnWOut = 1'b0; // write - tmp_nxt[1] = 1'b0; - end - else if (tmp[0]) // CC - begin - addr_nxt = (tmp[14]) ? u_m1 : s_m1; - if (tmp[14]) - u_nxt = u_m1; - else - s_nxt = s_m1; - DOutput = cc; - RnWOut = 1'b0; // write - tmp_nxt[0] = 1'b0; - end - if (tmp[13]) // Then we're pushing for an IRQ, and LIC is supposed to be set. - rLIC = 1'b1; - if (tmp_nxt[7:0] == 8'H00) - begin - if (NextState == CPUSTATE_FETCH_I1) - begin - rAVMA = 1'b1; - rLIC = 1'b1; - end - else - rAVMA = 1'b0; - CpuState_nxt = NextState; - end - end - - CPUSTATE_PUL_DONTCARE1: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_PUL_DONTCARE2; - end - - CPUSTATE_PUL_DONTCARE2: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_PUL_ACTION; - end - - CPUSTATE_PUL_ACTION: - begin - rAVMA = 1'b1; - if (tmp[0]) // CC - begin - addr_nxt = (tmp[14]) ? u : s; - if (tmp[14]) - u_nxt = u_p1; - else - s_nxt = s_p1; - cc_nxt = D[7:0]; - if (tmp[12] == 1'b1) // This pull is from an RTI, the E flag comes from the retrieved CC, and set the tmp_nxt accordingly, indicating what other registers to retrieve - begin - if (D[CC_E_BIT]) - tmp_nxt[7:0] = 8'HFE; // Retrieve all registers (ENTIRE) [CC is already retrieved] - else - tmp_nxt[7:0] = 8'H80; // Retrieve PC and CC [CC is already retrieved] - end - else - tmp_nxt[0] = 1'b0; - end - else if (tmp[1]) // A - begin - addr_nxt = (tmp[14]) ? u : s; - if (tmp[14]) - u_nxt = u_p1; - else - s_nxt = s_p1; - a_nxt = D[7:0]; - tmp_nxt[1] = 1'b0; - end - else if (tmp[2]) // B - begin - addr_nxt = (tmp[14]) ? u : s; - if (tmp[14]) - u_nxt = u_p1; - else - s_nxt = s_p1; - b_nxt = D[7:0]; - tmp_nxt[2] = 1'b0; - end - else if (tmp[3]) // DP - begin - addr_nxt = (tmp[14]) ? u : s; - if (tmp[14]) - u_nxt = u_p1; - else - s_nxt = s_p1; - dp_nxt = D[7:0]; - tmp_nxt[3] = 1'b0; - end - else if (tmp[4] & (~tmp[15])) // X_HI - begin - addr_nxt = (tmp[14]) ? u : s; - if (tmp[14]) - u_nxt = u_p1; - else - s_nxt = s_p1; - x_nxt[15:8] = D[7:0]; - tmp_nxt[15] = 1'b1; - end - else if (tmp[4] & tmp[15]) // X_LO - begin - addr_nxt = (tmp[14]) ? u : s; - if (tmp[14]) - u_nxt = u_p1; - else - s_nxt = s_p1; - x_nxt[7:0] = D[7:0]; - tmp_nxt[4] = 1'b0; - tmp_nxt[15] = 1'b0; - end - else if (tmp[5] & (~tmp[15])) // Y_HI - begin - addr_nxt = (tmp[14]) ? u : s; - if (tmp[14]) - u_nxt = u_p1; - else - s_nxt = s_p1; - y_nxt[15:8] = D[7:0]; - tmp_nxt[15] = 1'b1; - end - else if (tmp[5] & tmp[15]) // Y_LO - begin - addr_nxt = (tmp[14]) ? u : s; - if (tmp[14]) - u_nxt = u_p1; - else - s_nxt = s_p1; - y_nxt[7:0] = D[7:0]; - tmp_nxt[5] = 1'b0; - tmp_nxt[15] = 1'b0; - end - else if (tmp[6] & (~tmp[15])) // U/S_HI - begin - addr_nxt = (tmp[14]) ? u : s; - if (tmp[14]) - u_nxt = u_p1; - else - s_nxt = s_p1; - if (tmp[14]) - s_nxt[15:8] = D[7:0]; - else - u_nxt[15:8] = D[7:0]; - tmp_nxt[15] = 1'b1; - end - else if (tmp[6] & tmp[15]) // U/S_LO - begin - addr_nxt = (tmp[14]) ? u : s; - if (tmp[14]) - u_nxt = u_p1; - else - s_nxt = s_p1; - if (tmp[14]) - s_nxt[7:0] = D[7:0]; - else - u_nxt[7:0] = D[7:0]; - tmp_nxt[6] = 1'b0; - tmp_nxt[15] = 1'b0; - end - else if (tmp[7] & (~tmp[15])) // PC_HI - begin - addr_nxt = (tmp[14]) ? u : s; - if (tmp[14]) - u_nxt = u_p1; - else - s_nxt = s_p1; - pc_nxt[15:8] = D[7:0]; - tmp_nxt[15] = 1'b1; - end - else if (tmp[7] & tmp[15]) // PC_LO - begin - addr_nxt = (tmp[14]) ? u : s; - if (tmp[14]) - u_nxt = u_p1; - else - s_nxt = s_p1; - pc_nxt[7:0] = D[7:0]; - tmp_nxt[7] = 1'b0; - tmp_nxt[15] = 1'b0; - end - else - begin - addr_nxt = (tmp[14]) ? u : s; - if (NextState == CPUSTATE_FETCH_I1) - begin - rAVMA = 1'b1; - rLIC = 1'b1; - end - else - rAVMA = 1'b0; - CpuState_nxt = NextState; - end - end - - CPUSTATE_NMI_START: - begin - NMIClear_nxt = 1'b1; - addr_nxt = pc; - // tmp stands as the bits to push to the stack - tmp_nxt = 16'H20FF; // Save to the S stack, PC, U, Y, X, DP, B, A, CC; set LIC on every push - NextState_nxt = CPUSTATE_IRQ_DONTCARE2; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_IRQ_DONTCARE; - IntType_nxt = INTTYPE_NMI; - cc_nxt[CC_E_BIT] = 1'b1; - end - - CPUSTATE_IRQ_START: - begin - addr_nxt = pc; - tmp_nxt = 16'H20FF; // Save to the S stack, PC, U, Y, X, DP, B, A, CC; set LIC on every push - NextState_nxt = CPUSTATE_IRQ_DONTCARE2; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_IRQ_DONTCARE; - IntType_nxt = INTTYPE_IRQ; - cc_nxt[CC_E_BIT] = 1'b1; - end - - CPUSTATE_FIRQ_START: - begin - addr_nxt = pc; - tmp_nxt = 16'H2081; // Save to the S stack, PC, CC; set LIC on every push - NextState_nxt = CPUSTATE_IRQ_DONTCARE2; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_IRQ_DONTCARE; - IntType_nxt = INTTYPE_FIRQ; - cc_nxt[CC_E_BIT] = 1'b0; - end - - CPUSTATE_SWI_START: - begin - addr_nxt = pc; - tmp_nxt = 16'H00FF; // Save to the S stack, PC, U, Y, X, DP, B, A, CC - - NextState_nxt = CPUSTATE_IRQ_DONTCARE2; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_IRQ_DONTCARE; - if (InstPage3) - IntType_nxt = INTTYPE_SWI3; - if (InstPage2) - IntType_nxt = INTTYPE_SWI2; - else - IntType_nxt = INTTYPE_SWI; - - cc_nxt[CC_E_BIT] = 1'b1; - end - - CPUSTATE_IRQ_DONTCARE: - begin - NMIClear_nxt = 1'b0; - addr_nxt = 16'HFFFF; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_PSH_ACTION; - end - - - CPUSTATE_IRQ_DONTCARE2: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_IRQ_VECTOR_HI; - rLIC = 1'b1; - end - - CPUSTATE_IRQ_VECTOR_HI: - begin - case (IntType) - INTTYPE_NMI: - begin - addr_nxt = `NMI_VECTOR; - BS_nxt = 1'b1; // ACK Interrupt - end - INTTYPE_IRQ: - begin - addr_nxt = `IRQ_VECTOR; - BS_nxt = 1'b1; // ACK Interrupt - end - INTTYPE_SWI: - begin - addr_nxt = `SWI_VECTOR; - end - INTTYPE_FIRQ: - begin - addr_nxt = `FIRQ_VECTOR; - BS_nxt = 1'b1; // ACK Interrupt - end - INTTYPE_SWI2: - begin - addr_nxt = `SWI2_VECTOR; - end - INTTYPE_SWI3: - begin - addr_nxt = `SWI3_VECTOR; - end - default: // make the default an IRQ, even though it really should never happen - begin - addr_nxt = `IRQ_VECTOR; - BS_nxt = 1'b1; // ACK Interrupt - end - endcase - - pc_nxt[15:8] = D[7:0]; - rAVMA = 1'b1; - rBUSY = 1'b1; - rLIC = 1'b1; - CpuState_nxt = CPUSTATE_IRQ_VECTOR_LO; - - - end - - CPUSTATE_IRQ_VECTOR_LO: - begin - case (IntType) - INTTYPE_NMI: - begin - addr_nxt = `NMI_VECTOR+16'H1; - cc_nxt[CC_I_BIT] = 1'b1; - cc_nxt[CC_F_BIT] = 1'b1; - BS_nxt = 1'b1; // ACK Interrupt - end - INTTYPE_IRQ: - begin - addr_nxt = `IRQ_VECTOR+16'H1; - cc_nxt[CC_I_BIT] = 1'b1; - BS_nxt = 1'b1; // ACK Interrupt - end - INTTYPE_SWI: - begin - addr_nxt = `SWI_VECTOR+16'H1; - cc_nxt[CC_F_BIT] = 1'b1; - cc_nxt[CC_I_BIT] = 1'b1; - rLIC = 1'b1; - end - INTTYPE_FIRQ: - begin - addr_nxt = `FIRQ_VECTOR+16'H1; - cc_nxt[CC_F_BIT] = 1'b1; - cc_nxt[CC_I_BIT] = 1'b1; - BS_nxt = 1'b1; // ACK Interrupt - end - INTTYPE_SWI2: - begin - addr_nxt = `SWI2_VECTOR+16'H1; - rLIC = 1'b1; - end - INTTYPE_SWI3: - begin - addr_nxt = `SWI3_VECTOR+16'H1; - rLIC = 1'b1; - end - default: - begin - end - endcase - - pc_nxt[7:0] = D[7:0]; - rAVMA = 1'b1; - rLIC = 1'b1; - CpuState_nxt = CPUSTATE_INT_DONTCARE; - end - - CPUSTATE_INT_DONTCARE: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b1; - rLIC = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_CC_DONTCARE: - begin - addr_nxt = pc; - rLIC = 1'b1; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_TST_DONTCARE1: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_TST_DONTCARE2; - end - - CPUSTATE_TST_DONTCARE2: - begin - addr_nxt = 16'HFFFF; - rLIC = 1'b1; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_DEBUG: - begin - addr_nxt = tmp; - rLIC = 1'b1; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_16IMM_DONTCARE: - begin - addr_nxt = 16'HFFFF; - rLIC = 1'b1; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_SYNC: - begin - addr_nxt = 16'HFFFF; - BA_nxt = 1'b1; - rLIC = 1'b1; - rAVMA = 1'b0; - - if (~(NMILatched & FIRQLatched & IRQLatched)) - begin - CpuState_nxt = CPUSTATE_SYNC_EXIT; - end - end - - CPUSTATE_SYNC_EXIT: - begin - addr_nxt = 16'HFFFF; - BA_nxt = 1'b1; - rLIC = 1'b1; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - - CPUSTATE_DMABREQ: - begin - rAVMA = 1'b0; - addr_nxt = 16'HFFFF; - BS_nxt = 1'b1; - BA_nxt = 1'b1; - rLIC = 1'b1; - tmp_nxt[3:0] = tmp[3:0] - 1'b1; - if ( (tmp[3:0] == 4'H0) | (DMABREQSample2) ) - begin - CpuState_nxt = CPUSTATE_DMABREQ_EXIT; - end - end - - CPUSTATE_DMABREQ_EXIT: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_HALTED: - begin - rAVMA = 1'b0; - addr_nxt = 16'HFFFF; - BS_nxt = 1'b1; - BA_nxt = 1'b1; - rLIC = 1'b1; - if (HALTSample2) - begin - CpuState_nxt = CPUSTATE_HALT_EXIT2; - end - end - - - CPUSTATE_HALT_EXIT2: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_FETCH_I1; - end - - CPUSTATE_STOP: - begin - addr_nxt = 16'HDEAD; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_STOP2; - end - - CPUSTATE_STOP2: - begin - addr_nxt = pc; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_STOP3; - end - - CPUSTATE_STOP3: - begin - addr_nxt = 16'H0000; //{Inst1, Inst2}; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_STOP; - end - - // The otherwise critically useful Figure 18 in the 6809 datasheet contains an error; - // it lists that CWAI has a tri-stated bus while it waits for an interrupt. - // That is not true. SYNC tristates the bus, as do things like /HALT and /DMABREQ. - // CWAI does not. It waits with /VMA cycles on the bus until an interrupt occurs. - // The implementation here fits with the 6809 Programming Manual and other Motorola - // sources, not with that typo in Figure 18. - CPUSTATE_CWAI: - begin - addr_nxt = pc; - cc_nxt = {1'b1, (cc[6:0] & Inst2[6:0])}; // Set E flag, AND CC with CWAI argument - tmp_nxt = 16'H00FF; // Save to the S stack, PC, U, Y, X, DP, B, A, CC - - NextState_nxt = CPUSTATE_CWAI_POST; - rAVMA = 1'b0; - CpuState_nxt = CPUSTATE_CWAI_DONTCARE1; - end - - CPUSTATE_CWAI_DONTCARE1: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b1; - CpuState_nxt = CPUSTATE_PSH_ACTION; - end - - CPUSTATE_CWAI_POST: - begin - addr_nxt = 16'HFFFF; - rAVMA = 1'b0; - - CpuState_nxt = CPUSTATE_CWAI_POST; - - // Wait for an interrupt - if (NMILatched == 0) - begin - rAVMA = 1'b1; - IntType_nxt = INTTYPE_NMI; - cc_nxt[CC_F_BIT] = 1'b1; - cc_nxt[CC_I_BIT] = 1'b1; - CpuState_nxt = CPUSTATE_IRQ_VECTOR_HI; - end - else if ((FIRQLatched == 0) && (cc[CC_F_BIT] == 0)) - begin - rAVMA = 1'b1; - cc_nxt[CC_F_BIT] = 1'b1; - cc_nxt[CC_I_BIT] = 1'b1; - IntType_nxt = INTTYPE_FIRQ; - CpuState_nxt = CPUSTATE_IRQ_VECTOR_HI; - end - else if ((IRQLatched == 0) && (cc[CC_I_BIT] == 0)) - begin - rAVMA = 1'b1; - cc_nxt[CC_I_BIT] = 1'b1; - IntType_nxt = INTTYPE_IRQ; - CpuState_nxt = CPUSTATE_IRQ_VECTOR_HI; - end - end - - default: // Picky darned Verilog. - begin - CpuState_nxt = PostIllegalState; - end - - endcase -end - -endmodule - diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809s.v b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809s.v deleted file mode 100644 index 9c49239a..00000000 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809s.v +++ /dev/null @@ -1,82 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 09/18/2016 09:25:01 PM -// Design Name: -// Module Name: 6809 Superset module of MC6809 and MC6809E signals -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module mc6809s( - input [7:0] D, - output [7:0] DOut, - output [15:0] ADDR, - output RnW, - input CLK4, - output BS, - output BA, - input nIRQ, - input nFIRQ, - input nNMI, - output AVMA, - output BUSY, - output LIC, - input nRESET, - input nHALT, - input nDMABREQ, - output E, - output Q, - output reg [1:0] clk4_cnt, - output [111:0] RegData -); - - reg rE; - reg rQ; - assign E = rE; - assign Q = rQ; - reg nCoreRESET; - - mc6809i corecpu(.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(rE), .Q(rQ), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ), .nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nRESET(nCoreRESET), - .nDMABREQ(nDMABREQ), .nHALT(nHALT), .RegData(RegData) ); - - always @(posedge CLK4) - begin - clk4_cnt <= clk4_cnt+2'b01; - - if (nRESET == 0) - begin - clk4_cnt <= 0; - nCoreRESET <= 0; - end - - if ( clk4_cnt == 2'b00 ) // RISING EDGE OF E - rE <= 1; - - if (clk4_cnt == 2'b01) // RISING EDGE OF Q - rQ <= 1; - - if (clk4_cnt == 2'b10) // FALLING EDGE OF E - rE <= 0; - - if (clk4_cnt == 2'b11) // FALLING EDGE OF Q - begin - rQ <= 0; - nCoreRESET <= 1; - end - end - - -endmodule diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform.vhd deleted file mode 100644 index 90fd0984..00000000 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform.vhd +++ /dev/null @@ -1,567 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.pace_pkg.all; -use work.video_controller_pkg.all; -use work.sprite_pkg.all; -use work.platform_pkg.all; - -entity platform is - port - ( - -- clocking and reset - clkrst_i : in from_CLKRST_t; - vma : out std_logic; - -- controller inputs - inputs_p1 : in std_logic_vector(7 downto 0); - inputs_p2 : in std_logic_vector(7 downto 0); - inputs_sys : in std_logic_vector(7 downto 0); - inputs_dip1 : in std_logic_vector(7 downto 0); - inputs_dip2 : in std_logic_vector(7 downto 0); - - bitmap_i : in from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); - bitmap_o : out to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); - - tilemap_i : in from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); - tilemap_o : out to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); - - sprite_reg_o : out to_SPRITE_REG_t; - sprite_i : in from_SPRITE_CTL_t; - sprite_o : out to_SPRITE_CTL_t; - spr0_hit : in std_logic; - - -- various graphics information - graphics_i : in from_GRAPHICS_t; - graphics_o : out to_GRAPHICS_t; - - snd_i : in from_SOUND_t; - snd_o : out to_SOUND_t; - platform_i : in from_PLATFORM_IO_t; - platform_o : out to_PLATFORM_IO_t; - - cpu_rom_addr : out std_logic_vector(15 downto 0); - cpu_rom_do : in std_logic_vector(7 downto 0); - tile_rom_addr : out std_logic_vector(12 downto 0); - tile_rom_do : in std_logic_vector(15 downto 0) - ); - -end platform; - -architecture SYN of platform is - - alias clk_20M : std_logic is clkrst_i.clk(0); - alias rst_20M : std_logic is clkrst_i.rst(0); - alias clk_video : std_logic is clkrst_i.clk(1); - signal cpu_reset : std_logic; - - -- uP signals - signal clk_2M_en : std_logic; - signal cpu_clk_en : std_logic; - signal cpu_r_wn : std_logic; - signal cpu_a : std_logic_vector(15 downto 0); - signal cpu_d_i : std_logic_vector(7 downto 0); - signal cpu_d_o : std_logic_vector(7 downto 0); - signal cpu_irq : std_logic; - - -- ROM signals - signal rom_cs : std_logic; - - -- RAM signals - signal wram_cs : std_logic; - signal wram_wr : std_logic; - signal wram_d_o : std_logic_vector(7 downto 0); - signal vram_cs : std_logic; - signal vram_d_o : std_logic_vector(7 downto 0); - signal vram_wr : std_logic; - signal cram_cs : std_logic; - signal cram_d_o : std_logic_vector(7 downto 0); - signal cram_wr : std_logic; - signal sprite_cs : std_logic; - - -- I/O signals - signal scroll_cs : std_logic; - signal in0_cs : std_logic; - signal in1_cs : std_logic; - signal in2_cs : std_logic; - signal dsw1_cs : std_logic; - signal dsw2_cs : std_logic; - - signal rom4_d_o : std_logic_vector(7 downto 0); - signal rom8_d_o : std_logic_vector(7 downto 0); - signal romC_d_o : std_logic_vector(7 downto 0); - signal rom_d_o : std_logic_vector(7 downto 0); - - signal cpu_rn_w : std_logic; - - COMPONENT mc6809i - GENERIC ( ILLEGAL_INSTRUCTIONS : STRING := "GHOST" ); - PORT - ( - D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - DOut : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - RnW : OUT STD_LOGIC; - E : IN STD_LOGIC; - Q : IN STD_LOGIC; - BS : OUT STD_LOGIC; - BA : OUT STD_LOGIC; - nIRQ : IN STD_LOGIC; - nFIRQ : IN STD_LOGIC; - nNMI : IN STD_LOGIC; - AVMA : OUT STD_LOGIC; - BUSY : OUT STD_LOGIC; - LIC : OUT STD_LOGIC; - nHALT : IN STD_LOGIC; - nRESET : IN STD_LOGIC; - nDMABREQ : IN STD_LOGIC; - RegData : OUT STD_LOGIC_VECTOR(111 DOWNTO 0) - ); -END COMPONENT; - -begin - - wram_cs <= '1' when STD_MATCH(cpu_a, "0000------------") else '0';-- RAM $0000-$0FFF - vram_cs <= '1' when STD_MATCH(cpu_a, "000100----------") else '0';-- video ram $1000-$13FF - cram_cs <= '1' when STD_MATCH(cpu_a, "000101----------") else '0';-- colour ram $1400-$17FF - sprite_cs <= '1' when STD_MATCH(cpu_a, X"20"&"001-----") else - '1' when STD_MATCH(cpu_a, X"20"&"01------") else - '0';-- sprite 'ram' $2020-$207F - -- I/O - scroll_cs <= '1' when STD_MATCH(cpu_a, X"3000") else '0'; - in0_cs <= '1' when STD_MATCH(cpu_a, X"3002") else '0'; - in1_cs <= '1' when STD_MATCH(cpu_a, X"3003") else '0'; - in2_cs <= '1' when STD_MATCH(cpu_a, X"3004") else '0'; - dsw1_cs <= '1' when STD_MATCH(cpu_a, X"3005") else '0'; - dsw2_cs <= '1' when STD_MATCH(cpu_a, X"3006") else '0'; - rom_cs <= '1' when (cpu_a > X"3FFF") else '0'; - - -- memory block write enables - wram_wr <= wram_cs and clk_2M_en and not cpu_r_wn; - vram_wr <= vram_cs and clk_2M_en and not cpu_r_wn; - cram_wr <= cram_cs and clk_2M_en and not cpu_r_wn; - - -- memory read mux - cpu_d_i <= wram_d_o when wram_cs = '1' else - vram_d_o when vram_cs = '1' else - cram_d_o when cram_cs = '1' else - inputs_p1 when in0_cs = '1' else - inputs_p2 when in1_cs = '1' else - inputs_sys when in2_cs = '1' else - inputs_dip1 when dsw1_cs = '1' else - inputs_dip2 when dsw2_cs = '1' else - -- flip off, service off, coin A, 1C1C --- (X"80" or X"40" or X"10" or X"0F") when dsw1_cs = '1' else - -- freeze off, easy, 20K/80K/100K, 3 lives --- (X"80" or X"60" or X"08" or X"03") when dsw2_cs = '1' else - rom_d_o when rom_cs = '1' else --- cpu_rom_do when rom_cs = '1' else - (others => 'Z'); - - - -- system timing - process (clk_20M, rst_20M) - variable count : integer range 0 to 10-1; - begin - if rst_20M = '1' then - count := 0; - elsif rising_edge(clk_20M) then - clk_2M_en <= '0'; -- default - case count is - when 0 => - clk_2M_en <= '1'; - when others => - null; - end case; - if count = count'high then - count := 0; - else - count := count + 1; - end if; - end if; - end process; - - -- cpu09 core uses negative clock edge - --cpu_clk_en <= not (clk_2M_en and not platform_pause); - cpu_clk_en <= clk_2M_en; - - -- add game reset later - cpu_reset <= rst_20M; - --- cpu_inst : entity work.cpu09 - -- generic map - -- ( - -- CLK_POL => '1' - -- ) --- port map --- ( --- clk => clk_20M, - -- clk_en => cpu_clk_en, --- rst => cpu_reset, --- rw => cpu_r_wn, - -- vma => vma, - --ba => open, - --bs => open, - -- addr => cpu_a, --- data_in => cpu_d_i, --- data_out => cpu_d_o, --- halt => '0', --- hold => '0', --- irq => cpu_irq, --- firq => '0', ---- nmi => '0' --- ); - ---changed for test - cpu_inst : mc6809i - port map - ( - D => cpu_d_i, - DOut => cpu_d_o, - ADDR => cpu_a, - RnW => cpu_r_wn, - E => cpu_clk_en, - Q => clk_20M, - BS => open, - BA => open, - nIRQ => not cpu_irq, - nFIRQ => '1', - nNMI => '1', - AVMA => open, - BUSY => open, - LIC => open, - nHALT => '1', - nRESET => not cpu_reset, - nDMABREQ => '1', - RegData => open - ); - - - ---WRAm_cs - wram_inst : entity work.spram - generic map - ( - widthad_a => 12, - width_a => 8 - ) - port map - ( - address => cpu_a(11 downto 0), - clock => clk_20M, - data => cpu_d_o, - wren => wram_wr, - q => wram_d_o - ); - - -- irq vblank interrupt - process (clk_20M, rst_20M) - variable vblank_r : std_logic_vector(3 downto 0); - alias vblank_prev : std_logic is vblank_r(vblank_r'left); - alias vblank_um : std_logic is vblank_r(vblank_r'left-1); - begin - if rst_20M = '1' then - vblank_r := (others => '0'); - cpu_irq <= '0'; - elsif rising_edge(clk_20M) then - if vblank_um = '1' and vblank_prev = '0' then - cpu_irq <= '1'; - elsif vblank_um = '0' then - cpu_irq <= '0'; - end if; - -- numeta the vblank - vblank_r := vblank_r(vblank_r'left-1 downto 0) & graphics_i.vblank; - end if; - end process; - - -- scroll register - process (clk_20M, rst_20M) - begin - if rst_20M = '1' then - graphics_o.bit8(0) <= (others => '0'); - elsif rising_edge(clk_20M) then - if scroll_cs and clk_2M_en and not cpu_r_wn then - graphics_o.bit8(0) <= cpu_d_o; - end if; - end if; - end process; - - - rom_4000_inst : entity work.sprom - generic map - ( - init_file => "./roms/ss_01e.hex", - widthad_a => 14 - ) - port map - ( - clock => clk_20M, - address => cpu_a(13 downto 0), - q => rom4_d_o - ); - - rom_8000_inst : entity work.sprom - generic map - ( - init_file => "./roms/ss_02e.hex", - widthad_a => 14 - ) - port map - ( - clock => clk_20M, - address => cpu_a(13 downto 0), - q => rom8_d_o - ); - - rom_C000_inst : entity work.sprom - generic map - ( - init_file => "./roms/ss_03e.hex", - widthad_a => 14 - ) - port map - ( - clock => clk_20M, - address => cpu_a(13 downto 0), - q => romC_d_o - ); - - rom_d_o <= rom4_d_o when STD_MATCH(cpu_a, "01--------------") else - rom8_d_o when STD_MATCH(cpu_a, "10--------------") else - romC_d_o; - ---cpu_rom_addr <= cpu_a(15 downto 0); ---rom_d_o <= cpu_rom_do; - - -- wren_a *MUST* be GND for CYCLONEII_SAFE_WRITE=VERIFIED_SAFE - vram_inst : entity work.dpram - generic map - ( - init_file => "./roms/vram.hex", - widthad_a => 10 - ) - port map - ( - clock_b => clk_20M, - address_b => cpu_a(9 downto 0), - wren_b => vram_wr, - data_b => cpu_d_o, - q_b => vram_d_o, - - clock_a => clk_video, - address_a => tilemap_i(1).map_a(9 downto 0), - wren_a => '0', - data_a => (others => 'X'), - q_a => tilemap_o(1).map_d(7 downto 0) - ); - tilemap_o(1).map_d(tilemap_o(1).map_d'left downto 8) <= (others => 'Z'); - - -- wren_a *MUST* be GND for CYCLONEII_SAFE_WRITE=VERIFIED_SAFE - cram_inst : entity work.dpram - generic map - ( - init_file => "./roms/cram.hex", - widthad_a => 10 - ) - port map - ( - clock_b => clk_20M, - address_b => cpu_a(9 downto 0), - wren_b => cram_wr, - data_b => cpu_d_o, - q_b => cram_d_o, - - clock_a => clk_video, - address_a => tilemap_i(1).attr_a(9 downto 0), - wren_a => '0', - data_a => (others => 'X'), - q_a => tilemap_o(1).attr_d(7 downto 0) - ); - tilemap_o(1).attr_d(tilemap_o(1).attr_d'left downto 8) <= (others => 'Z'); - - --tile rom (bit 0) - ss_7_b6_inst : entity work.sprom - generic map - ( - init_file => "./roms/ss_7_b6.hex", - widthad_a => 13 - ) - port map - ( - clock => clk_video, - address => tilemap_i(1).tile_a(12 downto 0), - q => tilemap_o(1).tile_d(7 downto 0) - ); - - -- tile rom (bit 1)---will not fit in FPGA Block Ram - -- ss_8_b5_inst : entity work.sprom - -- generic map - -- ( - --- init_file => "./roms/ss_8_b5.hex", - -- widthad_a => 13 - -- ) - -- port map - -- ( - -- clock => clk_video, - -- address => tilemap_i(1).tile_a(12 downto 0), - -- q => tilemap_o(1).tile_d(15 downto 8) - -- ); - ---tile_rom_addr <= tilemap_i(1).tile_a(12 downto 0); ---tilemap_o(1).tile_d(15 downto 0) <= tile_rom_do; - - BLK_SPRITES : block---will not fit in FPGA Block Ram - signal bit0_1 : std_logic_vector(7 downto 0); -- offset 0 - signal bit0_2 : std_logic_vector(7 downto 0); -- offset 0 - signal bit0_3 : std_logic_vector(7 downto 0); -- offset 16 - signal bit0_4 : std_logic_vector(7 downto 0); -- offset 16 - signal bit1_1 : std_logic_vector(7 downto 0); - signal bit1_2 : std_logic_vector(7 downto 0); - signal bit1_3 : std_logic_vector(7 downto 0); - signal bit1_4 : std_logic_vector(7 downto 0); - signal bit2_1 : std_logic_vector(7 downto 0); - signal bit2_2 : std_logic_vector(7 downto 0); - signal bit2_3 : std_logic_vector(7 downto 0); - signal bit2_4 : std_logic_vector(7 downto 0); - - signal sprite_a_00 : std_logic_vector(12 downto 0); - signal sprite_a_16 : std_logic_vector(12 downto 0); - - begin - - -- registers - sprite_reg_o.clk <= clk_20M; - sprite_reg_o.clk_ena <= clk_2M_en; - sprite_reg_o.a <= cpu_a(sprite_reg_o.a'range); - sprite_reg_o.d <= cpu_d_o; - sprite_reg_o.wr <= sprite_cs and clk_2M_en and not cpu_r_wn; - - -- - sprite data consists of: - -- 16 consecutive bytes for the 1st half - -- then the next 16 bytes for the 2nd half - -- - because we need to fetch an entire row at once - -- use dual-port memory to access both halves of each row - - -- generate address for each port - -- sprite_a_00 <= sprite_i.a(12 downto 5) & '0' & sprite_i.a(3 downto 0); - -- sprite_a_16 <= sprite_i.a(12 downto 5) & '1' & sprite_i.a(3 downto 0); - - -- sprite rom (bit 0, part 1/2) - -- ss_9_m5_inst : entity work.dprom_2r - -- generic map - -- ( - -- init_file => "./roms/ss_9_m5.hex", - -- widthad_a => 13, - -- widthad_b => 13 - -- ) - -- port map - -- ( - -- clock => clk_video, - -- address_a => sprite_a_00, - -- q_a => bit0_1, - -- address_b => sprite_a_16, - -- q_b => bit0_3 - -- ); - - -- sprite rom (bit 0, part 2/2) - -- ss_10_m6_inst : entity work.dprom_2r - -- generic map - -- ( - -- init_file => "./roms/ss_10_m6.hex", - -- widthad_a => 13, - -- widthad_b => 13 - -- ) - -- port map - -- ( - -- clock => clk_video, - -- address_a => sprite_a_00, - --- q_a => bit0_2, - -- address_b => sprite_a_16, - -- q_b => bit0_4 - -- ); - --- sprite_o.d(15 downto 0) <= (bit0_1 & bit0_3) when sprite_i.a(13) = '0' else --- (bit0_2 & bit0_4); - - -- sprite rom (bit 1, part 1/2) - -- ss_11_m3_inst : entity work.dprom_2r - -- generic map - -- ( - -- init_file => "./roms/ss_11_m3.hex", - -- widthad_a => 13, - -- widthad_b => 13 - -- ) - -- port map - -- ( - -- clock => clk_video, - -- address_a => sprite_a_00, - -- q_a => bit1_1, - -- address_b => sprite_a_16, - -- q_b => bit1_3 --- ); - - -- sprite rom (bit 0, part 2/2) - -- ss_12_m4_inst : entity work.dprom_2r - -- generic map - -- ( - -- init_file => "./roms/ss_12_m4.hex", - -- widthad_a => 13, - -- widthad_b => 13 - -- ) - -- port map - -- ( - -- clock => clk_video, --- address_a => sprite_a_00, - -- q_a => bit1_2, - -- address_b => sprite_a_16, ---- q_b => bit1_4 - --- ); - - -- sprite_o.d(31 downto 16) <= (bit1_1 & bit1_3) when sprite_i.a(13) = '0' else --- (bit1_2 & bit1_4); - - -- sprite rom (bit 2, part 1/2) - -- ss_13_m1_inst : entity work.dprom_2r - -- generic map - -- ( - -- init_file => "./roms/ss_13_m1.hex", - -- widthad_a => 13, - -- widthad_b => 13 - -- ) - -- port map - -- ( - -- clock => clk_video, - -- address_a => sprite_a_00, - -- q_a => bit2_1, - -- address_b => sprite_a_16, - -- q_b => bit2_3 - -- ); - - -- sprite rom (bit 2, part 2/2) --- ss_14_m2_inst : entity work.dprom_2r --- generic map --- ( --- init_file => "./roms/ss_14_m2.hex", - -- widthad_a => 13, --- widthad_b => 13 - -- ) - -- port map - -- ( - -- clock => clk_video, - -- address_a => sprite_a_00, - -- q_a => bit2_2, - -- address_b => sprite_a_16, - -- q_b => bit2_4 - -- ); - - -- sprite_o.d(47 downto 32) <= (bit2_1 & bit2_3) when sprite_i.a(13) = '0' else - -- (bit2_2 & bit2_4); - - end block BLK_SPRITES; - - -- unused outputs - - graphics_o.bit16(0) <= (others => '0'); - -end SYN; diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.qip b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.qip deleted file mode 100644 index d4720390..00000000 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"] diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.vhd deleted file mode 100644 index faf66714..00000000 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.vhd +++ /dev/null @@ -1,429 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll_mist.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll_mist IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC - ); -END pll_mist; - - -ARCHITECTURE SYN OF pll_mist IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - self_reset_on_loss_lock : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - locked : OUT STD_LOGIC - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - locked <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 20, - clk0_phase_shift => "0", - clk1_divide_by => 27, - clk1_duty_cycle => 50, - clk1_multiply_by => 40, - clk1_phase_shift => "0", - clk2_divide_by => 50, - clk2_duty_cycle => 50, - clk2_multiply_by => 163, - clk2_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll_mist", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_USED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - self_reset_on_loss_lock => "OFF", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0, - locked => sub_wire2 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "50" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "88.019997" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "20" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "163" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "13.50000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "88.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "163" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson.zip b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson.zip deleted file mode 100644 index d5b6fc4012603342668293441d19c712aae3d7a4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 64728 zcmZ6xV~{XB&?P#adB(PF+qP}nwr$(CZQHhOoAF=AWr10ssKu2LJ&3Z*g*>rDrhd@q*G;UTb;dWf~I7H8YJ5d*UpF zEh>bjJMy2r$AzDZrpHH&5k`&>EkQ_PwV2V5*H5O9z`8k7jVKjdTwPTA>?|%KQ7ZIJ z*5o2A93T$irf;Y)G*s?wdF2Hr_1XUVx=r(Pef_QLdDXP~500{V5;0(RWfYff1@2YZ z{I(A&8GSReO}^)+c9_R%yDUiAW(IT(-)$YKBDPbW+~>q>tX})vZm;Jh_9WQkx*NK= zBALPCIypDrs>n=ty47kp=4HY+^t*MevBi*HUF7>V+xZ*~SINBdvY#ikZD*a>KkbvV zoN!cePUobhwQWEEXPK@{GgoNrJD&V(PMh&WlkQ6Y?baLJtS^vV+|;E5JHnZE8^TWWq+4(dIk<^m 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100644 index 34c3eda62e2ec20168735fc0cedbd718f1588657..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 256 zcmZ9_Sq=js3_s&N zx6u=_?6N-8Vk<@c)NF?4G1;Jgz??B-{9%5$zxkPq61)U+MQu;{$p|HKUJO&4e&@fN WA1mf!6?;q6r}c5e^B1PyYO)vIw*N$)yK2 a-~)&2?wH7Nk=94_!!xR&a$kPR=BK^ifCqU1 diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb4.b2 b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb4.b2 deleted file mode 100644 index 86660493089a1037ca33b3601f2e320dfcce4945..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 32 ocmZRW* cpu_di, - DOut => cpu_do, - ADDR => cpu_addr, - RnW => cpu_rw, - E => '1', - Q => clk_2, - BS => open, - BA => open, - nIRQ => not cpu_irq, - nFIRQ => '1', - nNMI => '1', - AVMA => open, - BUSY => open, - LIC => open, - nHALT => '1', - nRESET => not cpu_reset, - nDMABREQ => '1', - RegData => open - ); - - -cpu_prog_rom : entity work.sound_rom -port map( - clk => clk_2, - addr => cpu_addr(12 downto 0), - data => rom_do -); - -cpu_ram : entity work.spram - generic map( widthad_a => 11) -port map( - clock => clk_2, - wren => wram_we, - address => cpu_addr(11 downto 0), - data => cpu_do, - q => wram_do -); - -ay83910_inst1: YM2149 - port map ( - CLK => clk_1p5, - CE => '1', - RESET => reset, - A8 => '1', - A9_L => port2_data(4), - BDIR => port2_data(0), - BC => port2_data(2), - DI => port1_data, - DO => ay1_do, - CHANNEL_A => ay1_chan_a, - CHANNEL_B => ay1_chan_b, - CHANNEL_C => ay1_chan_c, - - SEL => '0', - MODE => '1', - - ACTIVE => open, - - IOA_in => (others => '0'),--select_sound_r, - IOA_out => open, - - IOB_in => (others => '0'), - IOB_out => ay1_port_b_do - ); - - ay1_audio <= "0000000000" + ay1_chan_a + ay1_chan_b + ay1_chan_c; - - ay83910_inst2: YM2149 - port map ( - CLK => clk_1p5, - CE => '1', - RESET => reset, - A8 => '1', - A9_L => port2_data(3), - BDIR => port2_data(0), - BC => port2_data(2), - DI => port1_data, - DO => ay2_do, - CHANNEL_A => ay2_chan_a, - CHANNEL_B => ay2_chan_b, - CHANNEL_C => ay2_chan_c, - - SEL => '0', - MODE => '1', - - ACTIVE => open, - - IOA_in => (others => '0'), - IOA_out => open, - - IOB_in => (others => '0'), - IOB_out => open - ); - - ay2_audio <= "0000000000" + ay2_chan_a + ay2_chan_b + ay2_chan_c; - - - - -end SYN; \ No newline at end of file diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/target_top.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/target_top.vhd deleted file mode 100644 index cfd9a682..00000000 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/target_top.vhd +++ /dev/null @@ -1,107 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; - -library work; -use work.pace_pkg.all; -use work.video_controller_pkg.all; -use work.platform_pkg.all; - -entity target_top is - port( - vma : out std_logic; - clk_sys : in std_logic; - clk_vid : in std_logic; - reset_in : in std_logic; - snd_l : out std_logic_vector(7 downto 0); - snd_r : out std_logic_vector(7 downto 0); - vid_hs : out std_logic; - vid_vs : out std_logic; - vid_hb : out std_logic; - vid_vb : out std_logic; - vid_r : out std_logic_vector(3 downto 0); - vid_g : out std_logic_vector(3 downto 0); - vid_b : out std_logic_vector(3 downto 0); - inputs_p1 : in std_logic_vector(7 downto 0); - inputs_p2 : in std_logic_vector(7 downto 0); - inputs_sys : in std_logic_vector(7 downto 0); - inputs_dip1 : in std_logic_vector(7 downto 0); - inputs_dip2 : in std_logic_vector(7 downto 0); - cpu_rom_addr : out std_logic_vector(15 downto 0); - cpu_rom_do : in std_logic_vector(7 downto 0); - tile_rom_addr : out std_logic_vector(12 downto 0); - tile_rom_do : in std_logic_vector(15 downto 0) - ); - -end target_top; - -architecture SYN of target_top is - - signal clkrst_i : from_CLKRST_t; - signal video_i : from_VIDEO_t; - signal video_o : to_VIDEO_t; - signal audio_i : from_AUDIO_t; - signal audio_o : to_AUDIO_t; - signal platform_i : from_PLATFORM_IO_t; - signal platform_o : to_PLATFORM_IO_t; - - -begin - -clkrst_i.clk(0) <=clk_sys; -clkrst_i.clk(1) <= clk_vid; -clkrst_i.arst <= reset_in; -clkrst_i.arst_n <= not clkrst_i.arst; - -video_i.clk <= clk_vid; -video_i.clk_ena <= '1'; -video_i.reset <= reset_in; - - GEN_RESETS : for i in 0 to 3 generate - - process (clkrst_i.clk(i), clkrst_i.arst) - variable rst_r : std_logic_vector(2 downto 0) := (others => '0'); - begin - if clkrst_i.arst = '1' then - rst_r := (others => '1'); - elsif rising_edge(clkrst_i.clk(i)) then - rst_r := rst_r(rst_r'left-1 downto 0) & '0'; - end if; - clkrst_i.rst(i) <= rst_r(rst_r'left); - end process; - - end generate GEN_RESETS; - -vid_r <= video_o.rgb.r(9 downto 6); -vid_g <= video_o.rgb.g(9 downto 6); -vid_b <= video_o.rgb.b(9 downto 6); -vid_hs <= video_o.hsync; -vid_vs <= video_o.vsync; -vid_hb <= video_o.hblank; -vid_vb <= video_o.vblank; -snd_l <= audio_o.ldata(15 downto 8); -snd_r <= audio_o.rdata(15 downto 8); - - pace_inst : entity work.pace - port map( - clkrst_i => clkrst_i, - vma => vma, - inputs_p1 => inputs_p1, - inputs_p2 => inputs_p2, - inputs_sys => inputs_sys, - inputs_dip1 => inputs_dip1, - inputs_dip2 => inputs_dip2, - video_i => video_i, - video_o => video_o, - audio_i => audio_i, - audio_o => audio_o, - platform_i => platform_i, - platform_o => platform_o, - cpu_rom_addr => cpu_rom_addr, - cpu_rom_do => cpu_rom_do, - tile_rom_addr => tile_rom_addr, - tile_rom_do => tile_rom_do - ); - -end SYN; diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller.vhd deleted file mode 100644 index 14da0c20..00000000 --- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller.vhd +++ /dev/null @@ -1,455 +0,0 @@ -library IEEE; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.video_controller_pkg.all; - -entity pace_video_controller is - generic - ( - CONFIG : PACEVideoController_t := PACE_VIDEO_NONE; - DELAY : integer := 1; - H_SIZE : integer; - V_SIZE : integer; - L_CROP : integer range 0 to 255; - R_CROP : integer range 0 to 255; - H_SCALE : integer; - V_SCALE : integer; - H_SYNC_POL : std_logic := '1'; - V_SYNC_POL : std_logic := '1'; - BORDER_RGB : RGB_t := RGB_BLACK - ); - port - ( - -- clocking etc - video_i : in from_VIDEO_t; - - -- register interface - reg_i : in VIDEO_REG_t; - - -- video input data - rgb_i : in RGB_t; - - -- control signals (out) - video_ctl_o : out from_VIDEO_CTL_t; - - -- video output control & data - video_o : out to_VIDEO_t - ); -end pace_video_controller; - -architecture SYN of pace_video_controller is - - constant SIM_DELAY : time := 2 ns; - - constant VIDEO_H_SIZE : integer := H_SIZE * H_SCALE; - constant VIDEO_V_SIZE : integer := V_SIZE * V_SCALE; - - subtype reg_t is integer range 0 to 2047; - - alias clk : std_logic is video_i.clk; - alias clk_ena : std_logic is video_i.clk_ena; - alias reset : std_logic is video_i.reset; - - -- registers - signal h_front_porch_r : reg_t := 0; - signal h_sync_r : reg_t := 0; - signal h_back_porch_r : reg_t := 0; - signal h_border_r : reg_t := 0; - signal h_video_r : reg_t := 0; - signal v_front_porch_r : reg_t := 0; - signal v_sync_r : reg_t := 0; - signal v_back_porch_r : reg_t := 0; - signal v_border_r : reg_t := 0; - signal v_video_r : reg_t := 0; - - signal border_rgb_r : RGB_t := ((others=>'0'), (others=>'0'), (others=>'0')); - - -- derived values - signal h_sync_start : reg_t := 0; - signal h_back_porch_start : reg_t := 0; - signal h_left_border_start : reg_t := 0; - signal h_video_start : reg_t := 0; - signal h_right_border_start : reg_t := 0; - signal h_line_end : reg_t := 0; - signal v_sync_start : reg_t := 0; - signal v_back_porch_start : reg_t := 0; - signal v_top_border_start : reg_t := 0; - signal v_video_start : reg_t := 0; - signal v_bottom_border_start : reg_t := 0; - signal v_screen_end : reg_t := 0; - - signal hsync_s : std_logic := '0'; - signal vsync_s : std_logic := '0'; - signal hactive_s : std_logic := '0'; - signal vactive_s : std_logic := '0'; - signal hblank_s : std_logic := '0'; - signal vblank_s : std_logic := '0'; - - subtype count_t is integer range 0 to 2047; - signal x_count : count_t := 0; - signal y_count : count_t := 0; - - signal x_s : unsigned(10 downto 0) := (others => '0'); - signal y_s : unsigned(10 downto 0) := (others => '0'); - - --signal extended_reset : std_logic := '1'; - alias extended_reset : std_logic is video_i.reset; - -begin - - -- registers - reg_proc: process (reset, clk) - - begin - --if reset = '1' then - case CONFIG is - - when PACE_VIDEO_VGA_240x320_60Hz => - -- P3M, clk=11.136MHz, clk_ena=5.568MHz - h_front_porch_r <= 272-240; - h_sync_r <= 5; - h_back_porch_r <= 22; - h_border_r <= (240-VIDEO_H_SIZE)/2; - v_front_porch_r <= 326-320; - v_sync_r <= 1; - v_back_porch_r <= 5; - v_border_r <= (320-VIDEO_V_SIZE)/2; - - when PACE_VIDEO_VGA_320x480_60Hz => - -- VGA, clk=12.588MHz - --# 320x240 @ 60 Hz, 31.5 kHz hsync, 4:3 aspect ratio - --Modeline "320x240" 12.588 320 336 384 400 240 245 246 262 Doublescan - h_front_porch_r <= 16; - h_sync_r <= 48; - h_back_porch_r <= 16; - h_border_r <= (320-VIDEO_H_SIZE)/2; - v_front_porch_r <= (5*2); - v_sync_r <= (1*2); - v_back_porch_r <= (16*2); - v_border_r <= (480-VIDEO_V_SIZE)/2; - - when PACE_VIDEO_VGA_640x480_60Hz => - -- VGA, clk=25.175MHz - h_front_porch_r <= 16; - h_sync_r <= 96; - h_back_porch_r <= 48; - h_border_r <= (640-VIDEO_H_SIZE)/2; - v_front_porch_r <= 10; - v_sync_r <= 2; - v_back_porch_r <= 33; - v_border_r <= (480-VIDEO_V_SIZE)/2; - - when PACE_VIDEO_VGA_800x600_60Hz => - -- SVGA, clk=40MHz - h_front_porch_r <= 40; - h_sync_r <= 128; - h_back_porch_r <= 88; - h_border_r <= (800-VIDEO_H_SIZE)/2; - v_front_porch_r <= 1; - v_sync_r <= 4; - v_back_porch_r <= 23; - v_border_r <= (600-VIDEO_V_SIZE)/2; - - when PACE_VIDEO_VGA_1024x768_60Hz => - -- XVGA, clk=65MHz - h_front_porch_r <= 24; - h_sync_r <= 136; - h_back_porch_r <= 160; - h_border_r <= (1024-VIDEO_H_SIZE)/2; - v_front_porch_r <= 3; - v_sync_r <= 6; - v_back_porch_r <= 29; - v_border_r <= (768-VIDEO_V_SIZE)/2; - - when PACE_VIDEO_VGA_1366x768_60Hz => - -- XVGA(NAVICO ROCKY), clk=72MHz - h_front_porch_r <= 88; --64; - h_sync_r <= 44; --112; - h_back_porch_r <= 148; --248; - h_border_r <= (1366-VIDEO_H_SIZE)/2; - v_front_porch_r <= 4; --3; - v_sync_r <= 5; --6; - v_back_porch_r <= 36; --18; - v_border_r <= (768-VIDEO_V_SIZE)/2; - - when PACE_VIDEO_VGA_1280x800_60Hz => - -- Sentinel Mode 36, clk=103.2MHz - h_front_porch_r <= 64; - h_sync_r <= 32; - h_back_porch_r <= 362-32-64; - h_border_r <= (1280-VIDEO_H_SIZE)/2; - v_front_porch_r <= 3; - v_sync_r <= 4; - v_back_porch_r <= 38-4-3; - v_border_r <= (800-VIDEO_V_SIZE)/2; - - when PACE_VIDEO_VGA_1280x1024_60Hz => - -- SXGA, clk=108MHz - h_front_porch_r <= 48; - h_sync_r <= 112; - h_back_porch_r <= 248; - h_border_r <= (1280-VIDEO_H_SIZE)/2; - v_front_porch_r <= 1; - v_sync_r <= 3; - v_back_porch_r <= 38; - v_border_r <= (1024-VIDEO_V_SIZE)/2; - - when PACE_VIDEO_VGA_1680x1050_60Hz => - -- WSXGA+, clk=147.14MHz - h_front_porch_r <= 104; - h_sync_r <= 184; - h_back_porch_r <= 288; - v_front_porch_r <= 1; - v_sync_r <= 3; - v_back_porch_r <= 33; - -- WSXGA+, clk=118MHz - --h_front_porch_r <= 48; - --h_sync_r <= 32; - --h_back_porch_r <= 80; - --v_front_porch_r <= 3; - --v_sync_r <= 6; - --v_back_porch_r <= 21; - h_border_r <= (1680-VIDEO_H_SIZE)/2; - v_border_r <= (1050-VIDEO_V_SIZE)/2; - - when PACE_VIDEO_ARCADE_STD_336x240_60Hz => - -- arcade standard resolution, clk=7.16MHz - h_front_porch_r <= 34; - h_sync_r <= 34; - h_back_porch_r <= 51; - h_border_r <= (336-VIDEO_H_SIZE)/2; - v_front_porch_r <= 3; - v_sync_r <= 3; - v_back_porch_r <= 16; - v_border_r <= (240-VIDEO_V_SIZE)/2; - - when PACE_VIDEO_ARCADE_STD_336x240_60Hz_28M64 => - -- arcade standard resolution, clk=28.64MHz - h_front_porch_r <= 4*34; - h_sync_r <= 4*34; - h_back_porch_r <= 4*51; - h_border_r <= 4*(336-VIDEO_H_SIZE)/2; - v_front_porch_r <= 3; - v_sync_r <= 3; - v_back_porch_r <= 16; - v_border_r <= (240-VIDEO_V_SIZE)/2; - - when PACE_VIDEO_CVBS_720x288p_50Hz => - -- generic composite, clk=13.5MHz - h_front_porch_r <= (8+12); - h_sync_r <= 64; - h_back_porch_r <= (144-64-(8+12)); - h_border_r <= (720-VIDEO_H_SIZE)/2; - v_front_porch_r <= 1; - v_sync_r <= 3; - v_back_porch_r <= 20; - v_border_r <= (288-VIDEO_V_SIZE)/2; - - when PACE_VIDEO_LCM_320x240_60Hz => - -- DE1/2, clk=18MHz - h_front_porch_r <= 59; - h_sync_r <= 1; - h_back_porch_r <= 151; - h_border_r <= (320-VIDEO_H_SIZE)*3/2; - v_front_porch_r <= 8; - v_sync_r <= 1; - v_back_porch_r <= 13; - v_border_r <= (240-VIDEO_V_SIZE)/2; - - when others => - null; - end case; - - h_video_r <= VIDEO_H_SIZE; - v_video_r <= VIDEO_V_SIZE; - border_rgb_r <= BORDER_RGB; - - --end if; - end process reg_proc; - - -- register some arithmetic - init_proc: process (reset, clk, clk_ena) - begin - if reset = '1' then - null; - elsif rising_edge(clk) then - h_sync_start <= h_front_porch_r - 1; - h_back_porch_start <= h_sync_start + h_sync_r; - h_left_border_start <= h_back_porch_start + h_back_porch_r; - h_video_start <= h_left_border_start + h_border_r; - h_right_border_start <= h_video_start + h_video_r; - h_line_end <= h_right_border_start + h_border_r; - v_sync_start <= v_front_porch_r - 1; - v_back_porch_start <= v_sync_start + v_sync_r; - v_top_border_start <= v_back_porch_start + v_back_porch_r; - v_video_start <= v_top_border_start + v_border_r; - v_bottom_border_start <= v_video_start + v_video_r; - v_screen_end <= v_bottom_border_start + v_border_r; - end if; - end process init_proc; - - reset_proc: process (reset, clk) - variable count_v : integer; - begin - if reset = '1' then - --extended_reset <= '1'; - count_v := 7; - elsif rising_edge(clk) then - if count_v = 0 then - --extended_reset <= '0'; - else - count_v := count_v - 1; - end if; - end if; - end process reset_proc; - - -- video control outputs - timer_proc: process (extended_reset, clk, clk_ena) - begin - if extended_reset = '1' then - hblank_s <= '1'; - vblank_s <= '1'; - hactive_s <= '0'; - vactive_s <= '0'; - hsync_s <= not H_SYNC_POL; - x_count <= 0; - y_count <= 0; - elsif rising_edge(clk) and clk_ena = '1' then - if x_count = h_line_end then - hblank_s <= '1'; - hactive_s <= '0'; -- for 0 borders - if y_count = v_screen_end then - vblank_s <= '1'; - vactive_s <= '0'; -- for 0 borders - y_count <= 0; - else - y_s <= y_s + 1; - if y_count = v_sync_start then - vsync_s <= V_SYNC_POL; - elsif y_count = v_back_porch_start then - vsync_s <= not V_SYNC_POL; - elsif y_count = v_video_start then - vblank_s <= '0'; -- for 0 borders - vactive_s <= '1'; - y_s <= (others => '0'); - -- check the borders last in case they're 0 - elsif y_count = v_top_border_start then - vblank_s <= '0'; - elsif y_count = v_bottom_border_start then - vactive_s <= '0'; - end if; - y_count <= y_count + 1; - end if; - x_count <= 0; - else - x_s <= x_s + 1; - if x_count = h_sync_start then - hsync_s <= H_SYNC_POL; - elsif x_count = h_back_porch_start then - hsync_s <= not H_SYNC_POL; - elsif x_count = h_video_start then - hblank_s <= '0'; -- for 0 borders - hactive_s <= '1'; - x_s <= (others => '0'); - -- check the borders last in case they're 0 - elsif x_count = h_left_border_start then - hblank_s <= '0'; - elsif x_count = h_right_border_start then - hactive_s <= '0'; - end if; - x_count <= x_count + 1; - end if; - end if; -- rising_edge(clk) and clk_ena = '1' - end process timer_proc; - - -- pass-through for tile/bitmap & sprite controllers - video_ctl_o.clk <= clk; - video_ctl_o.clk_ena <= clk_ena; - - -- for video DACs and TFT output - video_o.clk <= clk; - - BLK_VIDEO_O : block - - constant PIPELINE_DELAY : natural := DELAY+1; - - -- won't synthesize correctly under ISE if these are variables - signal hactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); - signal vactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); - - begin - - video_o_proc: process (extended_reset, clk, clk_ena) - variable hsync_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); - variable vsync_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); - --variable hactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); - --variable vactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); - variable hblank_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); - variable vblank_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); - alias hsync_v : std_logic is hsync_v_r(hsync_v_r'left); - alias vsync_v : std_logic is vsync_v_r(vsync_v_r'left); - alias hactive_v : std_logic is hactive_v_r(hactive_v_r'left); - alias vactive_v : std_logic is vactive_v_r(vactive_v_r'left); - alias hblank_v : std_logic is hblank_v_r(hblank_v_r'left); - alias vblank_v : std_logic is vblank_v_r(vblank_v_r'left); - variable stb_cnt_v : unsigned(3 downto 0); -- up to 16x scaling - begin - if extended_reset = '1' then - hsync_v_r := (others => not H_SYNC_POL); - vsync_v_r := (others => not V_SYNC_POL); - hactive_v_r <= (others => '0'); - vactive_v_r <= (others => '0'); - hblank_v_r := (others => '0'); - vblank_v_r := (others => '0'); - stb_cnt_v := (others => '1'); - elsif rising_edge(clk) and clk_ena = '1' then - - -- register control signals and handle scaling - video_ctl_o.hblank <= not hactive_s after SIM_DELAY; -- used only by the bitmap/tilemap/sprite controllers - video_ctl_o.vblank <= not vactive_s after SIM_DELAY; -- used only by the bitmap/tilemap/sprite controllers - -- handle scaling - video_ctl_o.stb <= stb_cnt_v(H_SCALE-1) after SIM_DELAY; - if hactive_s = '1' and vactive_s = '1' then - stb_cnt_v := stb_cnt_v + 2; - elsif hblank_s = '0' and vblank_s = '0' then - stb_cnt_v := (others => '1'); - end if; - video_ctl_o.x <= std_logic_vector(resize(x_s(x_s'left downto H_SCALE-1), video_ctl_o.x'length)) after SIM_DELAY; - video_ctl_o.y <= std_logic_vector(resize(y_s(y_s'left downto V_SCALE-1), video_ctl_o.y'length)) after SIM_DELAY; - - -- register video outputs - if hactive_v = '1' and vactive_v = '1' then - -- active video - if x_s(x_s'left downto H_SCALE-1) < (L_CROP + PIPELINE_DELAY) or - x_s(x_s'left downto H_SCALE-1) >= (H_SIZE - R_CROP + PIPELINE_DELAY) then - video_o.rgb <= RGB_BLACK after SIM_DELAY; - else - video_o.rgb <= rgb_i after SIM_DELAY; - end if; - elsif hblank_v = '0' and vblank_v = '0' then - -- border - video_o.rgb <= border_rgb_r after SIM_DELAY; - else - video_o.rgb.r <= (others => '0') after SIM_DELAY; - video_o.rgb.g <= (others => '0') after SIM_DELAY; - video_o.rgb.b <= (others => '0') after SIM_DELAY; - end if; - video_o.hsync <= hsync_v after SIM_DELAY; - video_o.vsync <= vsync_v after SIM_DELAY; - video_o.hblank <= hblank_v after SIM_DELAY; - video_o.vblank <= vblank_v after SIM_DELAY; - -- pipelined signals - hsync_v_r := hsync_v_r(hsync_v_r'left-1 downto 0) & hsync_s; - vsync_v_r := vsync_v_r(vsync_v_r'left-1 downto 0) & vsync_s; - hactive_v_r <= hactive_v_r(hactive_v_r'left-1 downto 0) & hactive_s; - vactive_v_r <= vactive_v_r(vactive_v_r'left-1 downto 0) & vactive_s; - hblank_v_r := hblank_v_r(hblank_v_r'left-1 downto 0) & hblank_s; - vblank_v_r := vblank_v_r(vblank_v_r'left-1 downto 0) & vblank_s; - end if; - end process video_o_proc; - - end block BLK_VIDEO_O; - -end SYN;