diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/Release/SilverLand.rbf b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/Release/SilverLand.rbf index cff435c6..8ccd9443 100644 Binary files a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/Release/SilverLand.rbf and b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/Release/SilverLand.rbf differ diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/SilverLand_mist.sv b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/SilverLand_mist.sv index 951000bf..0cd42967 100644 --- a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/SilverLand_mist.sv +++ b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/SilverLand_mist.sv @@ -21,6 +21,7 @@ module SilverLand_mist ( localparam CONF_STR = { "Silver Land;;", "O34,Scanlines,Off,25%,50%,75%;", + "O5,Pause,Off,On;", "T6,Reset;", "V,v1.20.",`BUILD_DATE }; @@ -54,6 +55,7 @@ wire [1:0] b; crazy_climber crazy_climber ( .clock_12(clock_12), + .pause(status[5]), .reset(status[0] | status[6] | buttons[1]), .video_r(r), .video_g(g), diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/build_id.sv b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/build_id.sv index 2a51bb36..b4a740ee 100644 --- a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/build_id.sv +++ b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/build_id.sv @@ -1,2 +1,2 @@ -`define BUILD_DATE "190831" -`define BUILD_TIME "201529" +`define BUILD_DATE "190901" +`define BUILD_TIME "150452" diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/crazy_climber.vhd b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/crazy_climber.vhd index 83c2b171..e7002afb 100644 --- a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/crazy_climber.vhd +++ b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/crazy_climber.vhd @@ -8,7 +8,8 @@ use ieee.numeric_std.all; entity crazy_climber is port( - clock_12 : in std_logic; + clock_12 : in std_logic; + pause : in std_logic; reset : in std_logic; video_r : out std_logic_vector(2 downto 0); video_g : out std_logic_vector(2 downto 0); @@ -21,13 +22,12 @@ port( start2 : in std_logic; start1 : in std_logic; coin1 : in std_logic; - right1 : in std_logic; - left1 : in std_logic; - fire1 : in std_logic; - right2 : in std_logic; - left2 : in std_logic; - fire2 : in std_logic - + right1 : in std_logic; + left1 : in std_logic; + fire1 : in std_logic; + right2 : in std_logic; + left2 : in std_logic; + fire2 : in std_logic ); end crazy_climber; @@ -118,6 +118,7 @@ signal video_mux : std_logic_vector(7 downto 0); -- Z80 interface signal cpu_clock : std_logic; +signal cpu_clk : std_logic; signal cpu_wr_n : std_logic; signal cpu_addr : std_logic_vector(15 downto 0); signal cpu_do : std_logic_vector(7 downto 0); @@ -627,12 +628,13 @@ port map ( data => do_big_sprite_palette ); +cpu_clk <= cpu_clock when pause = '0'; -- Z80 Z80 : entity work.T80s generic map(Mode => 0, T2Write => 1, IOWait => 1) port map( RESET_n => reset_n, - CLK_n => cpu_clock, + CLK_n => cpu_clk, WAIT_n => '1', INT_n => '1', NMI_n => cpu_int_n, diff --git a/Computer_MiST/Acorn - System1/rtl/pll.ppf b/Computer_MiST/Acorn - System1/rtl/pll.ppf deleted file mode 100644 index 71e6f03a..00000000 --- a/Computer_MiST/Acorn - System1/rtl/pll.ppf +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/Computer_MiST/OricInFPGA_MiST/rtl/OricAtmos_MiST.sv b/Computer_MiST/OricInFPGA_MiST/rtl/OricAtmos_MiST.sv index 34799218..7caa267c 100644 --- a/Computer_MiST/OricInFPGA_MiST/rtl/OricAtmos_MiST.sv +++ b/Computer_MiST/OricInFPGA_MiST/rtl/OricAtmos_MiST.sv @@ -37,8 +37,8 @@ wire ypbpr; wire scandoublerD; wire [31:0] status; wire [15:0] audio; -assign LED = 1'b1; -assign AUDIO_R = AUDIO_L; +assign LED = 1'b1; +assign AUDIO_R = AUDIO_L; pll pll ( .inclk0 (CLOCK_27 ), @@ -105,11 +105,12 @@ oricatmos oricatmos( dac #( .c_bits (16 )) -dac( +audiodac( .clk_i (clk_24 ), .res_n_i (1 ), .dac_i (audio ), .dac_o (AUDIO_L ) - ); + ); + endmodule diff --git a/Computer_MiST/OricInFPGA_MiST/rtl/oricatmos.vhd b/Computer_MiST/OricInFPGA_MiST/rtl/oricatmos.vhd index 942b8d08..a62fdd02 100644 --- a/Computer_MiST/OricInFPGA_MiST/rtl/oricatmos.vhd +++ b/Computer_MiST/OricInFPGA_MiST/rtl/oricatmos.vhd @@ -201,7 +201,7 @@ inst_ram : entity work.ram48k do => SRAM_DO ); -inst_rom : entity work.BASIC11 +inst_rom : entity work.BASIC22 port map ( clk => CLK_IN, addr => cpu_ad(13 downto 0), diff --git a/Computer_MiST/OricInFPGA_MiST/rtl/pll.v b/Computer_MiST/OricInFPGA_MiST/rtl/pll.v index 1aacac63..92259ca0 100644 --- a/Computer_MiST/OricInFPGA_MiST/rtl/pll.v +++ b/Computer_MiST/OricInFPGA_MiST/rtl/pll.v @@ -39,31 +39,23 @@ module pll ( inclk0, c0, - c1, - c2, locked); input inclk0; output c0; - output c1; - output c2; output locked; wire [4:0] sub_wire0; wire sub_wire2; - wire [0:0] sub_wire7 = 1'h0; - wire [2:2] sub_wire4 = sub_wire0[2:2]; - wire [0:0] sub_wire3 = sub_wire0[0:0]; - wire [1:1] sub_wire1 = sub_wire0[1:1]; - wire c1 = sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; wire locked = sub_wire2; - wire c0 = sub_wire3; - wire c2 = sub_wire4; - wire sub_wire5 = inclk0; - wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; altpll altpll_component ( - .inclk (sub_wire6), + .inclk (sub_wire4), .clk (sub_wire0), .locked (sub_wire2), .activeclock (), @@ -106,14 +98,6 @@ module pll ( altpll_component.clk0_duty_cycle = 50, altpll_component.clk0_multiply_by = 8, altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 9, - altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 16, - altpll_component.clk1_phase_shift = "0", - altpll_component.clk2_divide_by = 9, - altpll_component.clk2_duty_cycle = 50, - altpll_component.clk2_multiply_by = 16, - altpll_component.clk2_phase_shift = "-2500", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -147,8 +131,8 @@ module pll ( altpll_component.port_scanread = "PORT_UNUSED", altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", @@ -188,14 +172,8 @@ endmodule // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" -// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "48.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "48.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -216,34 +194,18 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16" -// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "16" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "48.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "48.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2500.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -266,17 +228,11 @@ endmodule // Retrieval info: PRIVATE: SPREAD_USE STRING "0" // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: USE_CLK1 STRING "1" -// Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -285,14 +241,6 @@ endmodule // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" -// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" -// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" -// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "16" -// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2500" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -325,8 +273,8 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" @@ -344,15 +292,11 @@ endmodule // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE