mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-02-02 23:00:55 +00:00
New Core WIP
This commit is contained in:
Marcel
@@ -197,7 +197,8 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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# end ENTITY(galaga_mist)
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# -----------------------
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set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/galaga_mist.sv
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||||
set_global_assignment -name VHDL_FILE rtl/galaga.vhd
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||||
set_global_assignment -name VHDL_FILE rtl/gen_video.vhd
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||||
@@ -225,5 +226,4 @@ set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
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set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
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@@ -208,10 +208,10 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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# end DESIGN_PARTITION(Top)
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# -------------------------
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# end ENTITY(CosmicAvenger)
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# -------------------------
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# -------------------------
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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Binary file not shown.
424
Arcade_MiST/Phoenix Hardware/Survival_MIST/Survival_MiST.qsf
Normal file
424
Arcade_MiST/Phoenix Hardware/Survival_MIST/Survival_MiST.qsf
Normal file
@@ -0,0 +1,424 @@
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# -------------------------------------------------------------------------- #
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#
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||||
# Copyright (C) 1991-2014 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
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||||
# -------------------------------------------------------------------------- #
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||||
#
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# Quartus II 64-Bit
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# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
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# Date created = 22:08:30 September 05, 2019
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# Survival_MiST_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
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||||
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# Project-Wide Assignments
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# ========================
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24 MAY 17, 2014"
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/Survival_MiST.sv
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set_global_assignment -name VHDL_FILE rtl/phoenix.vhd
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set_global_assignment -name VHDL_FILE rtl/phoenix_effect3.vhd
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set_global_assignment -name VHDL_FILE rtl/phoenix_effect2.vhd
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set_global_assignment -name VHDL_FILE rtl/phoenix_effect1.vhd
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set_global_assignment -name VHDL_FILE rtl/phoenix_video.vhd
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/ym2149.sv
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set_global_assignment -name VHDL_FILE rtl/ROM/survival_prog.vhd
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set_global_assignment -name VHDL_FILE rtl/ROM/prom_palette_ic41.vhd
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set_global_assignment -name VHDL_FILE rtl/ROM/prom_palette_ic40.vhd
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set_global_assignment -name VHDL_FILE rtl/ROM/prom_ic40.vhd
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set_global_assignment -name VHDL_FILE rtl/ROM/prom_ic39.vhd
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set_global_assignment -name VHDL_FILE rtl/ROM/prom_ic24.vhd
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set_global_assignment -name VHDL_FILE rtl/ROM/prom_ic23.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
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set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
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set_global_assignment -name VHDL_FILE rtl/pll.vhd
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set_global_assignment -name QIP_FILE "D:/Github/Mist_FPGA/common/mist/mist.qip"
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# Pin & Location Assignments
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# ==========================
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set_location_assignment PIN_7 -to LED
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set_location_assignment PIN_54 -to CLOCK_27
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set_location_assignment PIN_144 -to VGA_R[5]
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set_location_assignment PIN_143 -to VGA_R[4]
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set_location_assignment PIN_142 -to VGA_R[3]
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set_location_assignment PIN_141 -to VGA_R[2]
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set_location_assignment PIN_137 -to VGA_R[1]
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set_location_assignment PIN_135 -to VGA_R[0]
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set_location_assignment PIN_133 -to VGA_B[5]
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set_location_assignment PIN_132 -to VGA_B[4]
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set_location_assignment PIN_125 -to VGA_B[3]
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set_location_assignment PIN_121 -to VGA_B[2]
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set_location_assignment PIN_120 -to VGA_B[1]
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set_location_assignment PIN_115 -to VGA_B[0]
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set_location_assignment PIN_114 -to VGA_G[5]
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set_location_assignment PIN_113 -to VGA_G[4]
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set_location_assignment PIN_112 -to VGA_G[3]
|
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set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
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||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
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||||
set_location_assignment PIN_49 -to SDRAM_A[0]
|
||||
set_location_assignment PIN_44 -to SDRAM_A[1]
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||||
set_location_assignment PIN_42 -to SDRAM_A[2]
|
||||
set_location_assignment PIN_39 -to SDRAM_A[3]
|
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set_location_assignment PIN_4 -to SDRAM_A[4]
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set_location_assignment PIN_6 -to SDRAM_A[5]
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set_location_assignment PIN_8 -to SDRAM_A[6]
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set_location_assignment PIN_10 -to SDRAM_A[7]
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set_location_assignment PIN_11 -to SDRAM_A[8]
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set_location_assignment PIN_28 -to SDRAM_A[9]
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set_location_assignment PIN_50 -to SDRAM_A[10]
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set_location_assignment PIN_30 -to SDRAM_A[11]
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set_location_assignment PIN_32 -to SDRAM_A[12]
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set_location_assignment PIN_83 -to SDRAM_DQ[0]
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set_location_assignment PIN_79 -to SDRAM_DQ[1]
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set_location_assignment PIN_77 -to SDRAM_DQ[2]
|
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set_location_assignment PIN_76 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_72 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_71 -to SDRAM_DQ[5]
|
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set_location_assignment PIN_69 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_68 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_86 -to SDRAM_DQ[8]
|
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set_location_assignment PIN_87 -to SDRAM_DQ[9]
|
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set_location_assignment PIN_98 -to SDRAM_DQ[10]
|
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set_location_assignment PIN_99 -to SDRAM_DQ[11]
|
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set_location_assignment PIN_100 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_101 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_103 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_104 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_58 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_51 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_85 -to SDRAM_DQMH
|
||||
set_location_assignment PIN_67 -to SDRAM_DQML
|
||||
set_location_assignment PIN_60 -to SDRAM_nRAS
|
||||
set_location_assignment PIN_64 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_66 -to SDRAM_nWE
|
||||
set_location_assignment PIN_59 -to SDRAM_nCS
|
||||
set_location_assignment PIN_33 -to SDRAM_CKE
|
||||
set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
set_location_assignment PLL_1 -to "pll27:pll|altpll:altpll_component"
|
||||
|
||||
# Classic Timing Assignments
|
||||
# ==========================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY Survival_MiST
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
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set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
|
||||
# SignalTap II Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
|
||||
|
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# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# Advanced I/O Timing Assignments
|
||||
# ===============================
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
|
||||
# ---------------------------
|
||||
# start ENTITY(Survival_MiST)
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[15]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_BA[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_BA[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQML
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQMH
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nRAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nCAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nWE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nCS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_CKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_CLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_HS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_VS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_DO
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to CONF_DATA0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_L
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_R
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CONF_DATA0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQMH
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQML
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nRAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nCAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nWE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nCS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to CLOCK_27
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_DI
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SCK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SS2
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SS3
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(Survival_MiST)
|
||||
# -------------------------
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
30
Arcade_MiST/Phoenix Hardware/Survival_MIST/Survival_mist.qpf
Normal file
30
Arcade_MiST/Phoenix Hardware/Survival_MIST/Survival_mist.qpf
Normal file
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
# Date created = 02:40:30 January 25, 2017
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.1"
|
||||
DATE = "02:40:30 January 25, 2017"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "Survival_MiST"
|
||||
42
Arcade_MiST/Phoenix Hardware/Survival_MIST/Survival_mist.sdc
Normal file
42
Arcade_MiST/Phoenix Hardware/Survival_MIST/Survival_mist.sdc
Normal file
@@ -0,0 +1,42 @@
|
||||
#************************************************************
|
||||
# THIS IS A WIZARD-GENERATED FILE.
|
||||
#
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
|
||||
#
|
||||
#************************************************************
|
||||
|
||||
# Copyright (C) 1991-2014 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
# Clock constraints
|
||||
|
||||
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
|
||||
|
||||
# Automatically constrain PLL and other generated clocks
|
||||
derive_pll_clocks -create_base_clocks
|
||||
|
||||
# Automatically calculate clock uncertainty to jitter and other effects.
|
||||
derive_clock_uncertainty
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
|
||||
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}]
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}]
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}]
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}]
|
||||
|
||||
set_multicycle_path -to {VGA_*[*]} -setup 2
|
||||
set_multicycle_path -to {VGA_*[*]} -hold 1
|
||||
16
Arcade_MiST/Phoenix Hardware/Survival_MIST/clean.bat
Normal file
16
Arcade_MiST/Phoenix Hardware/Survival_MIST/clean.bat
Normal file
@@ -0,0 +1,16 @@
|
||||
@echo off
|
||||
del /s *.bak
|
||||
del /s *.orig
|
||||
del /s *.rej
|
||||
rmdir /s /q db
|
||||
rmdir /s /q incremental_db
|
||||
rmdir /s /q output_files
|
||||
rmdir /s /q simulation
|
||||
rmdir /s /q greybox_tmp
|
||||
del PLLJ_PLLSPE_INFO.txt
|
||||
del /s /q build_id.v
|
||||
del *.qws
|
||||
del *.ppf
|
||||
del *.qip
|
||||
del *.ddb
|
||||
pause
|
||||
150
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/ROM/prom_ic23.vhd
Normal file
150
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/ROM/prom_ic23.vhd
Normal file
@@ -0,0 +1,150 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity prom_ic23 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(10 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of prom_ic23 is
|
||||
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FE",X"FC",X"F8",X"F0",X"E0",X"C0",X"80",
|
||||
X"FF",X"7F",X"3F",X"1F",X"0F",X"07",X"03",X"01",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"C0",X"E0",X"F0",X"F8",X"FC",X"FE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"3F",X"7F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"7F",X"3F",X"1F",X"0F",X"07",
|
||||
X"01",X"03",X"07",X"1F",X"3F",X"7F",X"7F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
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|
||||
X"87",X"88",X"10",X"A0",X"E0",X"20",X"10",X"00",X"23",X"11",X"08",X"05",X"07",X"04",X"08",X"00",
|
||||
X"00",X"10",X"20",X"E0",X"A0",X"10",X"08",X"C4",X"00",X"08",X"04",X"07",X"05",X"08",X"11",X"E1",
|
||||
X"98",X"A0",X"C0",X"40",X"20",X"00",X"00",X"00",X"09",X"05",X"03",X"02",X"04",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"20",X"40",X"C0",X"A0",X"D0",X"00",X"00",X"00",X"04",X"02",X"03",X"04",X"1B",
|
||||
X"B0",X"C0",X"40",X"20",X"00",X"00",X"00",X"00",X"07",X"03",X"02",X"04",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"20",X"40",X"C0",X"E0",X"00",X"00",X"00",X"00",X"04",X"02",X"03",X"0E",
|
||||
X"E0",X"80",X"40",X"00",X"00",X"00",X"04",X"00",X"83",X"01",X"02",X"00",X"00",X"00",X"08",X"00",
|
||||
X"00",X"04",X"00",X"00",X"00",X"40",X"80",X"C1",X"00",X"10",X"00",X"00",X"00",X"02",X"01",X"07",
|
||||
X"7C",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"07",X"03",X"01",X"01",X"01",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"80",X"80",X"80",X"C0",X"E0",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"3D",
|
||||
X"F0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"01",X"01",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"0F",
|
||||
X"AC",X"F8",X"00",X"00",X"00",X"00",X"00",X"00",X"2D",X"18",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"18",
|
||||
X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
150
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/ROM/prom_ic24.vhd
Normal file
150
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/ROM/prom_ic24.vhd
Normal file
@@ -0,0 +1,150 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity prom_ic24 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(10 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of prom_ic24 is
|
||||
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F8",X"F8",X"F8",X"F8",X"F0",X"E0",X"C0",X"80",
|
||||
X"F8",X"7C",X"3E",X"1F",X"0F",X"07",X"03",X"01",X"F8",X"F8",X"F8",X"F8",X"F8",X"F8",X"F8",X"F8",
|
||||
X"00",X"00",X"00",X"80",X"C0",X"E0",X"F0",X"F8",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"F8",X"F8",X"F8",X"7F",X"3F",X"1F",X"0F",X"07",
|
||||
X"00",X"00",X"00",X"03",X"0F",X"1F",X"3F",X"FF",X"00",X"00",X"00",X"F8",X"F8",X"F8",X"F8",X"F8",
|
||||
X"F8",X"F8",X"F8",X"F8",X"F8",X"F8",X"F8",X"F8",X"00",X"00",X"00",X"F8",X"F8",X"F8",X"F8",X"F8",
|
||||
X"F8",X"F8",X"F8",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FE",X"FC",X"F8",X"F8",X"F8",X"F8",X"F8",
|
||||
X"00",X"00",X"00",X"01",X"03",X"87",X"CF",X"FF",X"00",X"00",X"00",X"FC",X"FE",X"FF",X"FF",X"FF",
|
||||
X"0F",X"07",X"03",X"01",X"00",X"00",X"00",X"00",X"7F",X"3F",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F8",X"C0",X"E0",X"F0",X"F8",X"FC",X"FE",X"FF",X"FF",
|
||||
X"F0",X"E0",X"C0",X"80",X"00",X"00",X"00",X"80",X"1F",X"3F",X"7F",X"FF",X"FF",X"FE",X"FC",X"F8",
|
||||
X"F8",X"F8",X"F8",X"F8",X"00",X"00",X"00",X"00",X"7F",X"3F",X"1F",X"0F",X"07",X"03",X"01",X"00",
|
||||
X"1F",X"3F",X"7F",X"FF",X"FF",X"FE",X"FF",X"FF",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"0F",
|
||||
X"00",X"00",X"00",X"F8",X"F8",X"F8",X"F8",X"F8",X"3F",X"7E",X"FC",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"00",X"00",X"00",X"01",X"03",X"07",X"0F",X"1F",X"3F",X"7E",X"FC",X"F8",X"F0",X"E0",X"C0",X"80",
|
||||
X"FC",X"7E",X"3F",X"1F",X"1F",X"0F",X"0F",X"1F",X"00",X"00",X"00",X"80",X"C0",X"E0",X"C0",X"80",
|
||||
X"24",X"24",X"24",X"24",X"00",X"00",X"00",X"00",X"04",X"08",X"11",X"02",X"04",X"00",X"00",X"00",
|
||||
X"00",X"00",X"0F",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"00",X"04",X"02",X"11",X"08",X"04",
|
||||
X"00",X"00",X"00",X"00",X"24",X"24",X"24",X"24",X"00",X"00",X"00",X"20",X"40",X"88",X"10",X"20",
|
||||
X"00",X"00",X"F0",X"00",X"00",X"F0",X"00",X"00",X"20",X"10",X"88",X"40",X"20",X"00",X"00",X"00",
|
||||
X"10",X"90",X"E0",X"C0",X"80",X"00",X"00",X"00",X"3F",X"4F",X"87",X"43",X"21",X"11",X"0A",X"04",
|
||||
X"00",X"28",X"24",X"52",X"89",X"07",X"08",X"10",X"00",X"00",X"00",X"00",X"03",X"04",X"0C",X"1E",
|
||||
X"36",X"36",X"F6",X"EE",X"1C",X"F8",X"F0",X"00",X"6C",X"6C",X"6F",X"77",X"38",X"1F",X"0F",X"00",
|
||||
X"00",X"F0",X"F8",X"1C",X"6E",X"76",X"36",X"36",X"00",X"0F",X"1F",X"38",X"76",X"6E",X"6C",X"6C",
|
||||
X"00",X"00",X"00",X"00",X"24",X"24",X"24",X"24",X"00",X"00",X"00",X"20",X"40",X"88",X"10",X"20",
|
||||
X"00",X"00",X"F0",X"00",X"00",X"F0",X"00",X"00",X"20",X"10",X"88",X"40",X"20",X"00",X"00",X"00",
|
||||
X"24",X"24",X"24",X"24",X"00",X"00",X"00",X"00",X"04",X"08",X"11",X"02",X"04",X"00",X"00",X"00",
|
||||
X"00",X"00",X"0F",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"00",X"04",X"02",X"11",X"08",X"04",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"81",X"42",X"24",X"18",X"18",X"24",X"42",X"81",
|
||||
X"00",X"78",X"7C",X"6C",X"6C",X"7C",X"78",X"00",X"00",X"18",X"18",X"7E",X"7E",X"18",X"18",X"00",
|
||||
X"FF",X"E7",X"E7",X"81",X"81",X"E7",X"E7",X"FF",X"3C",X"66",X"DB",X"BD",X"BD",X"DB",X"66",X"3C",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",
|
||||
X"03",X"00",X"00",X"00",X"08",X"04",X"80",X"80",X"01",X"00",X"00",X"00",X"10",X"20",X"00",X"00",
|
||||
X"00",X"00",X"04",X"08",X"00",X"00",X"00",X"80",X"01",X"01",X"20",X"10",X"00",X"00",X"00",X"C0",
|
||||
X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",
|
||||
X"03",X"00",X"00",X"00",X"08",X"04",X"80",X"80",X"00",X"00",X"00",X"00",X"10",X"20",X"00",X"00",
|
||||
X"00",X"00",X"04",X"08",X"00",X"00",X"00",X"00",X"01",X"01",X"20",X"10",X"00",X"00",X"00",X"C0",
|
||||
X"60",X"C0",X"80",X"80",X"00",X"00",X"00",X"00",X"07",X"03",X"01",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"E0",X"00",X"00",X"00",X"00",X"01",X"01",X"02",X"07",
|
||||
X"10",X"20",X"00",X"00",X"08",X"04",X"00",X"00",X"08",X"04",X"00",X"00",X"10",X"20",X"00",X"00",
|
||||
X"00",X"00",X"04",X"08",X"00",X"00",X"20",X"10",X"00",X"00",X"20",X"10",X"00",X"00",X"04",X"08",
|
||||
X"80",X"C0",X"C0",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"03",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"03",X"03",X"01",
|
||||
X"23",X"00",X"80",X"00",X"08",X"04",X"80",X"80",X"08",X"00",X"01",X"01",X"10",X"20",X"00",X"00",
|
||||
X"00",X"00",X"04",X"08",X"80",X"00",X"00",X"30",X"01",X"01",X"20",X"10",X"01",X"01",X"00",X"CC",
|
||||
X"F0",X"80",X"80",X"80",X"00",X"00",X"00",X"00",X"0F",X"01",X"00",X"01",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"80",X"80",X"80",X"D0",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"07",
|
||||
X"A3",X"20",X"40",X"80",X"08",X"04",X"80",X"80",X"05",X"04",X"02",X"01",X"00",X"20",X"00",X"00",
|
||||
X"00",X"00",X"04",X"00",X"80",X"40",X"20",X"A0",X"01",X"01",X"20",X"00",X"01",X"02",X"04",X"C5",
|
||||
X"34",X"94",X"48",X"30",X"00",X"00",X"00",X"00",X"2C",X"29",X"12",X"0C",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"30",X"48",X"94",X"34",X"00",X"00",X"00",X"00",X"0C",X"12",X"29",X"2C",
|
||||
X"80",X"30",X"78",X"78",X"30",X"04",X"00",X"00",X"01",X"0C",X"1E",X"1E",X"0C",X"20",X"00",X"00",
|
||||
X"00",X"00",X"04",X"30",X"78",X"78",X"30",X"80",X"00",X"00",X"20",X"0C",X"1E",X"1E",X"0C",X"01",
|
||||
X"10",X"10",X"88",X"40",X"28",X"00",X"00",X"00",X"08",X"08",X"11",X"02",X"14",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"28",X"40",X"88",X"10",X"10",X"00",X"00",X"00",X"14",X"02",X"11",X"08",X"08",
|
||||
X"C3",X"E0",X"40",X"00",X"08",X"04",X"80",X"80",X"03",X"07",X"02",X"00",X"10",X"20",X"00",X"00",
|
||||
X"00",X"00",X"04",X"08",X"00",X"40",X"E0",X"C0",X"01",X"01",X"20",X"10",X"00",X"02",X"07",X"C3",
|
||||
X"FE",X"88",X"EC",X"88",X"FC",X"AE",X"87",X"03",X"19",X"38",X"1D",X"1E",X"3F",X"75",X"E1",X"C0",
|
||||
X"03",X"87",X"AE",X"FC",X"88",X"EC",X"88",X"FE",X"C0",X"E1",X"75",X"3F",X"1E",X"1D",X"38",X"19",
|
||||
X"45",X"90",X"00",X"52",X"08",X"84",X"10",X"80",X"02",X"49",X"00",X"4A",X"10",X"20",X"0A",X"00",
|
||||
X"00",X"50",X"04",X"08",X"52",X"00",X"92",X"40",X"01",X"08",X"21",X"10",X"4A",X"00",X"09",X"A2",
|
||||
X"FE",X"98",X"DC",X"88",X"FC",X"AE",X"87",X"03",X"1D",X"38",X"1D",X"1B",X"3F",X"75",X"E1",X"C0",
|
||||
X"03",X"87",X"AE",X"FC",X"88",X"DC",X"98",X"FE",X"C0",X"E1",X"75",X"3F",X"1B",X"1D",X"38",X"1D",
|
||||
X"FE",X"C8",X"AC",X"88",X"FC",X"AC",X"8C",X"38",X"1D",X"38",X"1D",X"1B",X"3F",X"75",X"E1",X"C0",
|
||||
X"38",X"8C",X"AC",X"FC",X"88",X"AC",X"C8",X"FE",X"C0",X"E1",X"75",X"3F",X"1B",X"1D",X"38",X"1D",
|
||||
X"FE",X"88",X"AC",X"D8",X"FC",X"AC",X"0C",X"38",X"3D",X"78",X"3D",X"1B",X"BF",X"F3",X"00",X"00",
|
||||
X"38",X"0C",X"AC",X"FC",X"D8",X"AC",X"88",X"FE",X"00",X"00",X"F3",X"BF",X"1B",X"3D",X"78",X"3D",
|
||||
X"FC",X"40",X"58",X"90",X"F8",X"B0",X"70",X"40",X"19",X"08",X"5B",X"3F",X"0B",X"00",X"00",X"00",
|
||||
X"40",X"70",X"B0",X"F8",X"90",X"58",X"40",X"FC",X"00",X"00",X"00",X"0B",X"3F",X"5B",X"08",X"19",
|
||||
X"FC",X"00",X"58",X"90",X"F8",X"B8",X"04",X"02",X"19",X"08",X"1B",X"0F",X"13",X"20",X"40",X"00",
|
||||
X"02",X"04",X"B8",X"F8",X"90",X"58",X"00",X"FC",X"00",X"40",X"20",X"13",X"0F",X"1B",X"08",X"19",
|
||||
X"FC",X"40",X"58",X"90",X"F8",X"B0",X"70",X"40",X"19",X"08",X"5B",X"3F",X"0B",X"00",X"00",X"00",
|
||||
X"40",X"70",X"B0",X"F8",X"90",X"58",X"40",X"FC",X"00",X"00",X"00",X"0B",X"3F",X"5B",X"08",X"19",
|
||||
X"E0",X"50",X"98",X"B0",X"E0",X"60",X"C0",X"00",X"09",X"28",X"1B",X"07",X"00",X"00",X"00",X"00",
|
||||
X"00",X"C0",X"60",X"E0",X"B0",X"98",X"50",X"E0",X"00",X"00",X"00",X"00",X"07",X"1B",X"28",X"09",
|
||||
X"60",X"D0",X"10",X"60",X"80",X"00",X"00",X"00",X"09",X"08",X"10",X"01",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"80",X"60",X"10",X"D0",X"60",X"00",X"00",X"00",X"00",X"01",X"10",X"08",X"09",
|
||||
X"C0",X"40",X"60",X"40",X"80",X"00",X"00",X"00",X"09",X"0F",X"10",X"01",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"80",X"40",X"60",X"40",X"C0",X"00",X"00",X"00",X"00",X"01",X"10",X"0F",X"09",
|
||||
X"C0",X"40",X"60",X"40",X"20",X"10",X"00",X"00",X"09",X"0F",X"10",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"80",X"40",X"60",X"40",X"C0",X"00",X"00",X"00",X"00",X"01",X"10",X"0F",X"09",
|
||||
X"C0",X"40",X"60",X"40",X"20",X"10",X"00",X"00",X"09",X"0F",X"10",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"80",X"40",X"60",X"40",X"C0",X"00",X"00",X"00",X"00",X"01",X"10",X"0F",X"09",
|
||||
X"C0",X"40",X"60",X"40",X"24",X"18",X"00",X"00",X"09",X"0F",X"10",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"80",X"40",X"60",X"40",X"C0",X"00",X"00",X"00",X"00",X"01",X"10",X"0F",X"09",
|
||||
X"C0",X"40",X"40",X"80",X"80",X"00",X"00",X"00",X"05",X"0F",X"00",X"00",X"00",X"01",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"80",X"40",X"40",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"05",
|
||||
X"A0",X"40",X"00",X"10",X"08",X"00",X"00",X"00",X"05",X"02",X"00",X"08",X"10",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"08",X"10",X"00",X"40",X"A0",X"00",X"00",X"00",X"10",X"08",X"00",X"02",X"05",
|
||||
X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",
|
||||
X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"02",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"08",X"00",X"00",X"00",X"00",X"04",X"00",X"02",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"18",X"18",X"18",X"18",X"18",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"18",X"18",X"18",X"18",X"18",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"80",X"00",X"00",X"06",X"00",X"10",X"F0",X"E8",X"C4",X"E0",X"12",X"00",X"56",X"00",X"80",X"01",
|
||||
X"8A",X"44",X"28",X"10",X"A8",X"47",X"86",X"04",X"0F",X"07",X"02",X"01",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"80",X"C0",X"E0",X"D0",X"00",X"00",X"00",X"00",X"03",X"03",X"0F",X"0F",
|
||||
X"06",X"06",X"06",X"0E",X"1C",X"F8",X"F0",X"00",X"60",X"60",X"60",X"70",X"38",X"1F",X"0F",X"00",
|
||||
X"00",X"F0",X"F8",X"1C",X"0E",X"06",X"06",X"06",X"00",X"0F",X"1F",X"38",X"70",X"60",X"60",X"60",
|
||||
X"00",X"42",X"7E",X"7E",X"7E",X"7E",X"42",X"00",X"81",X"00",X"04",X"52",X"4A",X"20",X"00",X"81",
|
||||
X"2A",X"00",X"00",X"11",X"00",X"AA",X"00",X"20",X"04",X"00",X"85",X"10",X"84",X"00",X"84",X"10",
|
||||
X"00",X"00",X"00",X"55",X"AA",X"00",X"00",X"00",X"08",X"10",X"08",X"10",X"08",X"10",X"08",X"10",
|
||||
X"07",X"0E",X"1C",X"38",X"F0",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"81",X"FF",X"7E",X"00",
|
||||
X"30",X"18",X"0C",X"06",X"03",X"01",X"00",X"00",X"C0",X"C0",X"C0",X"C0",X"60",X"60",X"60",X"30",
|
||||
X"30",X"60",X"60",X"60",X"C0",X"C0",X"C0",X"C0",X"00",X"00",X"C0",X"F0",X"38",X"1C",X"0E",X"07",
|
||||
X"00",X"7E",X"FF",X"81",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"06",X"0C",X"18",X"30",
|
||||
X"03",X"03",X"03",X"06",X"06",X"1C",X"F8",X"E0",X"E0",X"F8",X"1C",X"06",X"06",X"03",X"03",X"03",
|
||||
X"F8",X"F0",X"E0",X"40",X"00",X"00",X"00",X"00",X"1F",X"0F",X"07",X"02",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"40",X"E0",X"F0",X"F8",X"00",X"00",X"00",X"00",X"02",X"07",X"0F",X"1F",
|
||||
X"E0",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"03",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"07",
|
||||
X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",
|
||||
X"80",X"00",X"00",X"00",X"00",X"08",X"00",X"00",X"41",X"00",X"00",X"00",X"00",X"04",X"08",X"00",
|
||||
X"00",X"04",X"08",X"00",X"00",X"00",X"00",X"82",X"00",X"00",X"08",X"00",X"00",X"00",X"00",X"01",
|
||||
X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",
|
||||
X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",
|
||||
X"F8",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"40",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"02");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
150
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/ROM/prom_ic39.vhd
Normal file
150
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/ROM/prom_ic39.vhd
Normal file
@@ -0,0 +1,150 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity prom_ic39 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(10 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of prom_ic39 is
|
||||
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"42",X"42",X"7E",X"00",X"00",
|
||||
X"00",X"3C",X"42",X"42",X"42",X"42",X"3C",X"00",X"00",X"00",X"7E",X"42",X"42",X"00",X"00",X"00",
|
||||
X"00",X"08",X"04",X"7E",X"04",X"08",X"00",X"00",X"00",X"40",X"40",X"40",X"40",X"40",X"40",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"08",X"08",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"A0",X"B0",X"B8",X"BC",X"BC",X"BE",X"FE",X"00",X"C0",X"F8",X"F4",X"EC",X"DC",X"BE",X"FE",
|
||||
X"FE",X"80",X"FE",X"FC",X"F8",X"F0",X"C0",X"00",X"FE",X"BE",X"DC",X"EC",X"F4",X"F8",X"C0",X"00",
|
||||
X"FE",X"BE",X"BC",X"BC",X"B8",X"B0",X"A0",X"00",X"7F",X"7D",X"3B",X"37",X"2F",X"1F",X"03",X"00",
|
||||
X"7F",X"01",X"7F",X"3F",X"1F",X"0F",X"03",X"00",X"00",X"03",X"1F",X"2F",X"37",X"3B",X"7D",X"7F",
|
||||
X"FE",X"FE",X"FC",X"FC",X"F8",X"F0",X"C0",X"00",X"7F",X"7F",X"3F",X"3F",X"1F",X"0F",X"03",X"00",
|
||||
X"00",X"C0",X"F0",X"F8",X"FC",X"FC",X"FE",X"FE",X"00",X"03",X"0F",X"1F",X"3F",X"3F",X"7F",X"7F",
|
||||
X"3C",X"6E",X"FF",X"BB",X"FF",X"EF",X"7E",X"3C",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"00",X"A0",X"B0",X"B8",X"BC",X"BC",X"AE",X"FE",X"00",X"C0",X"F8",X"F4",X"AC",X"DC",X"AE",X"FE",
|
||||
X"FE",X"80",X"FE",X"BC",X"F8",X"F0",X"C0",X"00",X"FE",X"AE",X"DC",X"AC",X"F4",X"F8",X"C0",X"00",
|
||||
X"FE",X"AE",X"BC",X"BC",X"B8",X"B0",X"A0",X"00",X"7F",X"75",X"3B",X"35",X"2F",X"1F",X"03",X"00",
|
||||
X"7F",X"01",X"7F",X"3D",X"1F",X"0F",X"03",X"00",X"00",X"03",X"1F",X"2F",X"35",X"3B",X"75",X"7F",
|
||||
X"FE",X"EE",X"FC",X"BC",X"F8",X"F0",X"C0",X"00",X"7F",X"77",X"3F",X"3D",X"1F",X"0F",X"03",X"00",
|
||||
X"00",X"C0",X"F0",X"F8",X"BC",X"FC",X"EE",X"FE",X"00",X"03",X"0F",X"1F",X"3D",X"3F",X"77",X"7F",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3C",X"7E",X"FF",X"FF",X"FF",X"FF",X"7E",X"3C",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3C",X"7E",X"FF",X"FF",X"FF",X"FF",X"7E",X"3C",
|
||||
X"00",X"00",X"00",X"C0",X"00",X"00",X"08",X"04",X"00",X"02",X"00",X"02",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"20",X"10",X"00",X"02",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"10",X"01",X"08",X"00",X"0A",X"01",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"0A",
|
||||
X"80",X"10",X"A0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"08",X"00",X"00",
|
||||
X"00",X"00",X"01",X"07",X"00",X"10",X"A0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"88",X"00",X"80",X"10",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"0C",
|
||||
X"00",X"00",X"00",X"00",X"03",X"06",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"30",X"00",X"00",X"00",X"00",
|
||||
X"04",X"04",X"08",X"60",X"00",X"00",X"00",X"60",X"00",X"00",X"00",X"02",X"00",X"02",X"00",X"02",
|
||||
X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"0C",X"08",X"08",X"00",X"00",X"00",X"00",
|
||||
X"01",X"0F",X"00",X"88",X"10",X"80",X"00",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"80",X"00",X"40",X"70",X"00",X"00",X"08",X"01",X"08",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"F0",X"10",X"00",X"01",X"08",X"00",
|
||||
X"20",X"20",X"30",X"10",X"00",X"00",X"00",X"00",X"0A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"70",X"00",X"01",X"0A",X"00",X"08",X"01",
|
||||
X"10",X"F8",X"F0",X"F8",X"10",X"F0",X"40",X"00",X"09",X"19",X"09",X"19",X"0D",X"0F",X"19",X"30",
|
||||
X"00",X"00",X"00",X"00",X"04",X"4C",X"E8",X"F8",X"00",X"00",X"00",X"00",X"00",X"07",X"0D",X"19",
|
||||
X"40",X"E0",X"C0",X"60",X"40",X"C0",X"00",X"00",X"27",X"67",X"27",X"66",X"37",X"3F",X"65",X"C0",
|
||||
X"00",X"00",X"00",X"00",X"10",X"30",X"A0",X"60",X"00",X"00",X"00",X"00",X"00",X"1D",X"37",X"66",
|
||||
X"7E",X"74",X"66",X"7A",X"D3",X"01",X"00",X"00",X"06",X"02",X"06",X"03",X"01",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"50",X"FC",X"74",X"66",X"7C",X"00",X"00",X"0C",X"06",X"03",X"03",X"06",X"02",
|
||||
X"4E",X"7C",X"7E",X"5C",X"4E",X"7C",X"D6",X"03",X"06",X"02",X"06",X"02",X"06",X"03",X"01",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"50",X"FC",X"5C",X"00",X"00",X"00",X"00",X"08",X"08",X"0D",X"07",
|
||||
X"10",X"F0",X"48",X"04",X"00",X"00",X"00",X"00",X"0D",X"07",X"01",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"40",X"E0",X"F0",X"10",X"F8",X"F0",X"F8",X"20",X"17",X"0D",X"19",X"09",X"19",X"09",X"19",
|
||||
X"5C",X"FC",X"57",X"01",X"00",X"00",X"00",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"D0",X"78",X"4C",X"5C",X"7E",X"7C",X"4E",X"0C",X"05",X"07",X"06",X"02",X"06",X"02",X"02",
|
||||
X"E0",X"C0",X"C0",X"80",X"80",X"00",X"00",X"00",X"67",X"25",X"24",X"77",X"5D",X"C0",X"00",X"00",
|
||||
X"00",X"00",X"10",X"30",X"E0",X"C0",X"E0",X"C0",X"00",X"00",X"00",X"05",X"1F",X"35",X"64",X"27",
|
||||
X"40",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"26",X"77",X"DD",X"80",X"00",X"00",X"00",X"00",
|
||||
X"30",X"20",X"E0",X"40",X"60",X"C0",X"E0",X"40",X"00",X"05",X"1F",X"37",X"66",X"27",X"67",X"27",
|
||||
X"10",X"F8",X"F0",X"F8",X"10",X"F0",X"40",X"00",X"09",X"19",X"09",X"19",X"0D",X"0F",X"19",X"30",
|
||||
X"00",X"00",X"00",X"00",X"04",X"4C",X"E8",X"F8",X"00",X"00",X"00",X"00",X"00",X"07",X"0D",X"19",
|
||||
X"40",X"E0",X"C0",X"60",X"40",X"C0",X"00",X"00",X"27",X"67",X"27",X"66",X"37",X"3F",X"65",X"C0",
|
||||
X"00",X"00",X"00",X"00",X"10",X"30",X"A0",X"60",X"00",X"00",X"00",X"00",X"00",X"1D",X"37",X"66",
|
||||
X"7E",X"74",X"66",X"7A",X"D3",X"01",X"00",X"00",X"06",X"02",X"06",X"03",X"01",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"50",X"FC",X"74",X"66",X"7C",X"00",X"00",X"0C",X"06",X"03",X"03",X"06",X"02",
|
||||
X"4E",X"7C",X"7E",X"5C",X"4E",X"7C",X"D6",X"03",X"06",X"02",X"06",X"02",X"06",X"03",X"01",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"50",X"FC",X"5C",X"00",X"00",X"00",X"00",X"08",X"08",X"0D",X"07",
|
||||
X"10",X"F0",X"48",X"04",X"00",X"00",X"00",X"00",X"0D",X"07",X"01",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"40",X"E0",X"F0",X"10",X"F8",X"F0",X"F8",X"20",X"17",X"0D",X"19",X"09",X"19",X"09",X"19",
|
||||
X"5C",X"FC",X"57",X"01",X"00",X"00",X"00",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"D0",X"78",X"4C",X"5C",X"7E",X"7C",X"4E",X"0C",X"05",X"07",X"06",X"02",X"06",X"02",X"02",
|
||||
X"E0",X"C0",X"C0",X"80",X"80",X"00",X"00",X"00",X"67",X"25",X"24",X"77",X"5D",X"C0",X"00",X"00",
|
||||
X"00",X"00",X"10",X"30",X"E0",X"C0",X"E0",X"C0",X"00",X"00",X"00",X"05",X"1F",X"35",X"64",X"27",
|
||||
X"40",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"26",X"77",X"DD",X"80",X"00",X"00",X"00",X"00",
|
||||
X"30",X"20",X"E0",X"40",X"60",X"C0",X"E0",X"40",X"00",X"05",X"1F",X"37",X"66",X"27",X"67",X"27",
|
||||
X"00",X"00",X"00",X"C0",X"00",X"00",X"08",X"04",X"00",X"02",X"00",X"02",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"20",X"10",X"00",X"02",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"10",X"01",X"08",X"00",X"0A",X"01",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"0A",
|
||||
X"80",X"10",X"A0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"08",X"00",X"00",
|
||||
X"00",X"00",X"01",X"07",X"00",X"10",X"A0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"88",X"00",X"80",X"10",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"0C",
|
||||
X"00",X"00",X"00",X"00",X"03",X"06",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"30",X"00",X"00",X"00",X"00",
|
||||
X"04",X"04",X"08",X"60",X"00",X"00",X"00",X"60",X"00",X"00",X"00",X"02",X"00",X"02",X"00",X"02",
|
||||
X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"0C",X"08",X"08",X"00",X"00",X"00",X"00",
|
||||
X"01",X"0F",X"00",X"88",X"10",X"80",X"00",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"80",X"00",X"40",X"70",X"00",X"00",X"08",X"01",X"08",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"F0",X"10",X"00",X"01",X"08",X"00",
|
||||
X"20",X"20",X"30",X"10",X"00",X"00",X"00",X"00",X"0A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"70",X"00",X"01",X"0A",X"00",X"08",X"01",
|
||||
X"DB",X"DB",X"DB",X"DB",X"DB",X"DB",X"DB",X"DB",X"FF",X"FF",X"00",X"FF",X"FF",X"00",X"FF",X"FF",
|
||||
X"DB",X"DB",X"DB",X"DB",X"DB",X"DB",X"DB",X"DB",X"FF",X"FF",X"00",X"FF",X"FF",X"00",X"FF",X"FF",
|
||||
X"DB",X"DB",X"1B",X"FB",X"F3",X"07",X"FE",X"FC",X"FC",X"FE",X"07",X"F3",X"FB",X"1B",X"DB",X"DB",
|
||||
X"DB",X"DB",X"D8",X"DF",X"CF",X"E0",X"7F",X"3F",X"3F",X"7F",X"E0",X"CF",X"DF",X"D8",X"DB",X"DB",
|
||||
X"DB",X"DB",X"1B",X"FB",X"F3",X"07",X"FE",X"FC",X"FC",X"FE",X"07",X"F3",X"FB",X"1B",X"DB",X"DB",
|
||||
X"DB",X"DB",X"D8",X"DF",X"CF",X"E0",X"7F",X"3F",X"3F",X"7F",X"E0",X"CF",X"DF",X"D8",X"DB",X"DB",
|
||||
X"7E",X"C3",X"81",X"A5",X"A5",X"99",X"C3",X"7E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"7E",X"04",X"08",X"08",X"04",X"7E",X"00",X"00",X"42",X"42",X"7E",X"42",X"42",X"00",X"00",
|
||||
X"00",X"24",X"42",X"42",X"42",X"42",X"3C",X"00",X"00",X"44",X"2A",X"1A",X"0A",X"0A",X"7E",X"00",
|
||||
X"00",X"3C",X"42",X"42",X"42",X"42",X"3C",X"00",X"00",X"02",X"02",X"7E",X"02",X"02",X"00",X"00",
|
||||
X"00",X"44",X"2A",X"1A",X"0A",X"0A",X"7E",X"00",X"00",X"7C",X"12",X"12",X"12",X"12",X"7C",X"00",
|
||||
X"00",X"42",X"42",X"7E",X"42",X"42",X"00",X"00",X"00",X"7E",X"20",X"10",X"08",X"04",X"7E",X"00",
|
||||
X"00",X"3C",X"42",X"66",X"66",X"5A",X"3C",X"00",X"00",X"8E",X"91",X"E6",X"00",X"76",X"89",X"76",
|
||||
X"00",X"7E",X"42",X"5A",X"5A",X"42",X"7E",X"00",X"FF",X"81",X"BD",X"A5",X"A5",X"BD",X"81",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"88",X"14",X"2A",X"49",X"BE",X"49",X"2A",X"14");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
150
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/ROM/prom_ic40.vhd
Normal file
150
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/ROM/prom_ic40.vhd
Normal file
@@ -0,0 +1,150 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity prom_ic40 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(10 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of prom_ic40 is
|
||||
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"7C",X"12",X"12",X"12",X"12",X"7C",X"00",
|
||||
X"00",X"34",X"4A",X"4A",X"4A",X"4A",X"7E",X"00",X"00",X"24",X"42",X"42",X"42",X"42",X"3C",X"00",
|
||||
X"00",X"3C",X"42",X"42",X"42",X"42",X"7E",X"00",X"00",X"42",X"4A",X"4A",X"4A",X"4A",X"7E",X"00",
|
||||
X"00",X"02",X"0A",X"0A",X"0A",X"0A",X"7E",X"00",X"00",X"34",X"52",X"52",X"42",X"42",X"3C",X"00",
|
||||
X"00",X"7E",X"08",X"08",X"08",X"08",X"7E",X"00",X"00",X"42",X"42",X"7E",X"42",X"42",X"00",X"00",
|
||||
X"00",X"02",X"3E",X"42",X"42",X"40",X"20",X"00",X"00",X"42",X"24",X"18",X"08",X"7E",X"00",X"00",
|
||||
X"00",X"40",X"40",X"40",X"40",X"40",X"7E",X"00",X"00",X"7E",X"04",X"08",X"08",X"04",X"7E",X"00",
|
||||
X"00",X"7E",X"20",X"10",X"08",X"04",X"7E",X"00",X"00",X"3C",X"42",X"42",X"42",X"42",X"3C",X"00",
|
||||
X"00",X"04",X"0A",X"0A",X"0A",X"0A",X"7E",X"00",X"80",X"7C",X"62",X"42",X"42",X"42",X"3C",X"00",
|
||||
X"00",X"44",X"2A",X"1A",X"0A",X"0A",X"7E",X"00",X"00",X"24",X"52",X"4A",X"4A",X"4A",X"24",X"00",
|
||||
X"00",X"02",X"02",X"7E",X"02",X"02",X"00",X"00",X"00",X"3E",X"40",X"40",X"40",X"40",X"3E",X"00",
|
||||
X"00",X"1E",X"20",X"40",X"40",X"20",X"1E",X"00",X"00",X"3E",X"40",X"3C",X"20",X"40",X"3E",X"00",
|
||||
X"00",X"42",X"24",X"18",X"18",X"24",X"42",X"00",X"00",X"02",X"04",X"78",X"04",X"02",X"00",X"00",
|
||||
X"00",X"42",X"46",X"4A",X"52",X"62",X"42",X"00",X"00",X"00",X"00",X"42",X"42",X"7E",X"00",X"00",
|
||||
X"00",X"3C",X"42",X"66",X"66",X"5A",X"3C",X"00",X"00",X"00",X"7E",X"42",X"42",X"00",X"00",X"00",
|
||||
X"00",X"08",X"04",X"7E",X"04",X"08",X"00",X"00",X"00",X"40",X"40",X"40",X"40",X"40",X"40",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"5E",X"00",X"00",X"00",
|
||||
X"00",X"00",X"06",X"00",X"06",X"00",X"00",X"00",X"00",X"24",X"7E",X"24",X"24",X"7E",X"24",X"00",
|
||||
X"00",X"24",X"52",X"FF",X"4A",X"24",X"00",X"00",X"00",X"00",X"06",X"09",X"09",X"06",X"00",X"00",
|
||||
X"00",X"50",X"24",X"5A",X"5A",X"24",X"00",X"00",X"00",X"00",X"00",X"0E",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"42",X"3C",X"00",X"00",X"00",X"00",X"00",X"00",X"3C",X"42",X"00",X"00",X"00",
|
||||
X"00",X"24",X"18",X"7E",X"18",X"24",X"00",X"00",X"00",X"08",X"08",X"3E",X"08",X"08",X"00",X"00",
|
||||
X"00",X"00",X"00",X"70",X"10",X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"08",X"08",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"60",X"60",X"00",X"00",X"00",X"02",X"04",X"08",X"10",X"20",X"40",X"00",
|
||||
X"00",X"3C",X"46",X"4A",X"52",X"62",X"3C",X"00",X"00",X"40",X"40",X"7E",X"42",X"44",X"00",X"00",
|
||||
X"00",X"44",X"4A",X"4A",X"52",X"52",X"64",X"00",X"00",X"34",X"4A",X"4A",X"4A",X"42",X"42",X"00",
|
||||
X"00",X"10",X"7E",X"12",X"14",X"18",X"10",X"00",X"00",X"32",X"4A",X"4A",X"4A",X"4A",X"2E",X"00",
|
||||
X"00",X"30",X"4A",X"4A",X"4A",X"4A",X"3C",X"00",X"00",X"02",X"06",X"0A",X"72",X"02",X"02",X"00",
|
||||
X"00",X"34",X"4A",X"4A",X"4A",X"4A",X"34",X"00",X"00",X"3C",X"52",X"52",X"52",X"52",X"0C",X"00",
|
||||
X"00",X"00",X"00",X"24",X"24",X"00",X"00",X"00",X"00",X"00",X"00",X"64",X"24",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"22",X"14",X"08",X"00",X"00",X"00",X"24",X"24",X"24",X"24",X"24",X"24",X"00",
|
||||
X"00",X"00",X"08",X"14",X"22",X"00",X"00",X"00",X"00",X"04",X"0A",X"0A",X"52",X"02",X"04",X"00",
|
||||
X"40",X"40",X"50",X"58",X"5C",X"5C",X"5E",X"1E",X"00",X"C0",X"F4",X"E8",X"D4",X"AC",X"5E",X"3E",
|
||||
X"00",X"7F",X"00",X"FC",X"F8",X"F0",X"C0",X"00",X"3E",X"5E",X"AC",X"D4",X"E8",X"F4",X"C0",X"00",
|
||||
X"1E",X"5E",X"5C",X"5C",X"58",X"50",X"40",X"40",X"7C",X"7A",X"35",X"2B",X"17",X"2F",X"03",X"00",
|
||||
X"00",X"FE",X"00",X"3F",X"1F",X"0F",X"03",X"00",X"00",X"03",X"2F",X"17",X"2B",X"35",X"7A",X"7C",
|
||||
X"FE",X"FE",X"FC",X"FC",X"F8",X"F0",X"C0",X"00",X"7F",X"7F",X"3F",X"3F",X"1F",X"0F",X"03",X"00",
|
||||
X"00",X"C0",X"F0",X"F8",X"FC",X"FC",X"FE",X"FE",X"00",X"03",X"0F",X"1F",X"3F",X"3F",X"7F",X"7F",
|
||||
X"3C",X"7E",X"FE",X"FE",X"FE",X"FE",X"7E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"40",X"40",X"50",X"58",X"5C",X"5C",X"5E",X"1E",X"00",X"C0",X"F4",X"E8",X"D4",X"AC",X"5E",X"3E",
|
||||
X"00",X"7F",X"00",X"FC",X"F8",X"F0",X"C0",X"00",X"3E",X"5E",X"AC",X"D4",X"E8",X"F4",X"C0",X"00",
|
||||
X"1E",X"5E",X"5C",X"5C",X"58",X"50",X"40",X"40",X"7C",X"7A",X"35",X"2B",X"17",X"2F",X"03",X"00",
|
||||
X"00",X"FE",X"00",X"3F",X"1F",X"0F",X"03",X"00",X"00",X"03",X"2F",X"17",X"2B",X"35",X"7A",X"7C",
|
||||
X"FE",X"FE",X"FC",X"FC",X"F8",X"F0",X"C0",X"00",X"7F",X"7F",X"3F",X"3F",X"1F",X"0F",X"03",X"00",
|
||||
X"00",X"C0",X"F0",X"F8",X"FC",X"FC",X"FE",X"FE",X"00",X"03",X"0F",X"1F",X"3F",X"3F",X"7F",X"7F",
|
||||
X"00",X"24",X"18",X"7E",X"18",X"24",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"3C",X"7E",X"FF",X"FF",X"FF",X"FF",X"7E",X"3C",X"3C",X"7E",X"FF",X"FF",X"FF",X"FF",X"7E",X"3C",
|
||||
X"10",X"F8",X"F0",X"38",X"10",X"F0",X"40",X"00",X"09",X"1B",X"09",X"1B",X"0D",X"0F",X"19",X"30",
|
||||
X"00",X"00",X"00",X"00",X"04",X"4C",X"E8",X"38",X"00",X"00",X"00",X"00",X"00",X"07",X"0D",X"1B",
|
||||
X"40",X"E0",X"C0",X"60",X"40",X"C0",X"00",X"00",X"26",X"6F",X"27",X"6C",X"36",X"3F",X"65",X"C0",
|
||||
X"00",X"00",X"00",X"00",X"10",X"30",X"A0",X"60",X"00",X"00",X"00",X"00",X"00",X"1D",X"37",X"6C",
|
||||
X"FE",X"64",X"C6",X"7A",X"D3",X"01",X"00",X"00",X"06",X"02",X"06",X"03",X"01",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"50",X"FC",X"64",X"C6",X"7C",X"00",X"00",X"0C",X"06",X"03",X"03",X"06",X"02",
|
||||
X"C6",X"7C",X"FE",X"4C",X"C6",X"7C",X"D6",X"03",X"06",X"02",X"06",X"02",X"06",X"03",X"01",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"50",X"FC",X"4C",X"00",X"00",X"00",X"00",X"08",X"08",X"0D",X"07",
|
||||
X"10",X"F0",X"48",X"04",X"00",X"00",X"00",X"00",X"0D",X"07",X"01",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"40",X"E0",X"90",X"10",X"F8",X"F0",X"98",X"20",X"17",X"0D",X"1B",X"09",X"1B",X"09",X"1B",
|
||||
X"4C",X"FC",X"57",X"01",X"00",X"00",X"00",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"D0",X"78",X"C4",X"4C",X"FE",X"7C",X"C6",X"0C",X"05",X"07",X"06",X"02",X"06",X"02",X"02",
|
||||
X"E0",X"C0",X"40",X"80",X"80",X"00",X"00",X"00",X"6F",X"24",X"2C",X"77",X"5D",X"C0",X"00",X"00",
|
||||
X"00",X"00",X"10",X"30",X"E0",X"C0",X"60",X"C0",X"00",X"00",X"00",X"05",X"1F",X"34",X"6C",X"27",
|
||||
X"40",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"2C",X"77",X"DD",X"80",X"00",X"00",X"00",X"00",
|
||||
X"30",X"20",X"E0",X"40",X"60",X"C0",X"E0",X"40",X"00",X"05",X"1F",X"36",X"6C",X"27",X"6F",X"26",
|
||||
X"00",X"00",X"00",X"C0",X"00",X"00",X"08",X"04",X"00",X"02",X"00",X"02",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"20",X"10",X"00",X"02",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"10",X"01",X"08",X"00",X"0A",X"01",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"0A",
|
||||
X"80",X"10",X"A0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"08",X"00",X"00",
|
||||
X"00",X"00",X"01",X"07",X"00",X"10",X"A0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"88",X"00",X"80",X"10",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"0C",
|
||||
X"00",X"00",X"00",X"00",X"03",X"06",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"30",X"00",X"00",X"00",X"00",
|
||||
X"04",X"04",X"08",X"60",X"00",X"00",X"00",X"60",X"00",X"00",X"00",X"02",X"00",X"02",X"00",X"02",
|
||||
X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"0C",X"08",X"08",X"00",X"00",X"00",X"00",
|
||||
X"01",X"0F",X"00",X"88",X"10",X"80",X"00",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"80",X"00",X"40",X"70",X"00",X"00",X"08",X"01",X"08",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"F0",X"10",X"00",X"01",X"08",X"00",
|
||||
X"20",X"20",X"30",X"10",X"00",X"00",X"00",X"00",X"0A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"70",X"00",X"01",X"0A",X"00",X"08",X"01",
|
||||
X"00",X"00",X"00",X"C0",X"00",X"00",X"08",X"04",X"00",X"02",X"00",X"02",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"20",X"10",X"00",X"02",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"10",X"01",X"08",X"00",X"0A",X"01",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"0A",
|
||||
X"80",X"10",X"A0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"08",X"00",X"00",
|
||||
X"00",X"00",X"01",X"07",X"00",X"10",X"A0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"88",X"00",X"80",X"10",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"0C",
|
||||
X"00",X"00",X"00",X"00",X"03",X"06",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"30",X"00",X"00",X"00",X"00",
|
||||
X"04",X"04",X"08",X"60",X"00",X"00",X"00",X"60",X"00",X"00",X"00",X"02",X"00",X"02",X"00",X"02",
|
||||
X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"0C",X"08",X"08",X"00",X"00",X"00",X"00",
|
||||
X"01",X"0F",X"00",X"88",X"10",X"80",X"00",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"80",X"00",X"40",X"70",X"00",X"00",X"08",X"01",X"08",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"F0",X"10",X"00",X"01",X"08",X"00",
|
||||
X"20",X"20",X"30",X"10",X"00",X"00",X"00",X"00",X"0A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"70",X"00",X"01",X"0A",X"00",X"08",X"01",
|
||||
X"10",X"F8",X"F0",X"F8",X"10",X"F0",X"40",X"00",X"09",X"19",X"09",X"19",X"0D",X"0F",X"19",X"30",
|
||||
X"00",X"00",X"00",X"00",X"04",X"4C",X"E8",X"F8",X"00",X"00",X"00",X"00",X"00",X"07",X"0D",X"19",
|
||||
X"40",X"E0",X"C0",X"60",X"40",X"C0",X"00",X"00",X"27",X"67",X"27",X"66",X"37",X"3F",X"65",X"C0",
|
||||
X"00",X"00",X"00",X"00",X"10",X"30",X"A0",X"60",X"00",X"00",X"00",X"00",X"00",X"1D",X"37",X"66",
|
||||
X"7E",X"74",X"66",X"7A",X"D3",X"01",X"00",X"00",X"06",X"02",X"06",X"03",X"01",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"50",X"FC",X"74",X"66",X"7C",X"00",X"00",X"0C",X"06",X"03",X"03",X"06",X"02",
|
||||
X"4E",X"7C",X"7E",X"5C",X"4E",X"7C",X"D6",X"03",X"06",X"02",X"06",X"02",X"06",X"03",X"01",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"50",X"FC",X"5C",X"00",X"00",X"00",X"00",X"08",X"08",X"0D",X"07",
|
||||
X"10",X"F0",X"48",X"04",X"00",X"00",X"00",X"00",X"0D",X"07",X"01",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"40",X"E0",X"F0",X"10",X"F8",X"F0",X"F8",X"20",X"17",X"0D",X"19",X"09",X"19",X"09",X"19",
|
||||
X"5C",X"FC",X"57",X"01",X"00",X"00",X"00",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"D0",X"78",X"4C",X"5C",X"7E",X"7C",X"4E",X"0C",X"05",X"07",X"06",X"02",X"06",X"02",X"02",
|
||||
X"E0",X"C0",X"C0",X"80",X"80",X"00",X"00",X"00",X"67",X"25",X"24",X"77",X"5D",X"C0",X"00",X"00",
|
||||
X"00",X"00",X"10",X"30",X"E0",X"C0",X"E0",X"C0",X"00",X"00",X"00",X"05",X"1F",X"35",X"64",X"27",
|
||||
X"40",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"26",X"77",X"DD",X"80",X"00",X"00",X"00",X"00",
|
||||
X"30",X"20",X"E0",X"40",X"60",X"C0",X"E0",X"40",X"00",X"05",X"1F",X"37",X"66",X"27",X"67",X"27",
|
||||
X"18",X"18",X"18",X"18",X"18",X"18",X"18",X"18",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00",X"00",
|
||||
X"18",X"18",X"18",X"18",X"18",X"18",X"18",X"18",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00",X"00",
|
||||
X"18",X"18",X"18",X"F8",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"F8",X"18",X"18",X"18",
|
||||
X"18",X"18",X"18",X"1F",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"1F",X"18",X"18",X"18",
|
||||
X"18",X"18",X"18",X"F8",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"F8",X"18",X"18",X"18",
|
||||
X"18",X"18",X"18",X"1F",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"1F",X"18",X"18",X"18",
|
||||
X"00",X"3C",X"42",X"66",X"66",X"5A",X"3C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"3C",X"42",X"42",X"42",X"42",X"3C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"FF",X"81",X"BD",X"A5",X"A5",X"BD",X"81",X"FF",X"00",X"7E",X"42",X"5A",X"5A",X"42",X"7E",X"00",
|
||||
X"DB",X"ED",X"F6",X"7B",X"BD",X"DE",X"6F",X"B7",X"08",X"14",X"22",X"41",X"80",X"41",X"22",X"14");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
@@ -0,0 +1,38 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity prom_palette_ic40 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(7 downto 0);
|
||||
data : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of prom_palette_ic40 is
|
||||
type rom is array(0 to 255) of std_logic_vector(3 downto 0);
|
||||
signal rom_data: rom := (
|
||||
"0000","0000","0000","0000","0000","0000","0000","0000","0000","0011","0000","0000","0000","0000","0001","0100",
|
||||
"0111","0111","0001","0111","0001","0000","0010","0001","0101","0001","0100","0000","0000","0000","0100","0111",
|
||||
"0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0001","0111","0010","0100","0001","0000",
|
||||
"0010","0101","0111","0001","0001","0001","0101","0111","0110","0010","0010","0101","0111","0111","0111","0000",
|
||||
"0000","0000","0000","0000","0000","0000","0000","0000","0000","0011","0000","0000","0000","0000","0001","0100",
|
||||
"0111","0111","0001","0111","0001","0000","0010","0001","0101","0001","0100","0000","0000","0000","0100","0111",
|
||||
"0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0001","0111","0010","0100","0001","0001",
|
||||
"0010","0101","0111","0001","0001","0001","0101","0111","0110","0010","0010","0101","0111","0111","0111","0000",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
@@ -0,0 +1,38 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity prom_palette_ic41 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(7 downto 0);
|
||||
data : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of prom_palette_ic41 is
|
||||
type rom is array(0 to 255) of std_logic_vector(3 downto 0);
|
||||
signal rom_data: rom := (
|
||||
"0000","0000","0000","0000","0000","0000","0000","0000","0001","0011","0110","0010","0001","0100","0001","0100",
|
||||
"0111","0111","0011","0111","0011","0010","0010","0001","0101","0001","0101","0110","0101","0001","0100","0111",
|
||||
"0000","0000","0000","0000","0000","0000","0000","0000","0100","0100","0001","0111","0010","0100","0001","0000",
|
||||
"0010","0101","0111","0001","0001","0001","0101","0111","0110","0010","0010","0101","0111","0111","0111","0110",
|
||||
"0000","0000","0000","0000","0000","0000","0000","0000","0001","0011","0110","0010","0001","0100","0001","0100",
|
||||
"0111","0111","0011","0111","0011","0010","0010","0001","0101","0001","0101","0110","0101","0001","0100","0111",
|
||||
"0000","0000","0000","0000","0000","0000","0000","0000","0100","0100","0001","0111","0010","0100","0001","0011",
|
||||
"0010","0101","0111","0001","0001","0001","0101","0111","0110","0010","0010","0101","0111","0111","0111","0110",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111",
|
||||
"1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
1046
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/ROM/survival_prog.vhd
Normal file
1046
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/ROM/survival_prog.vhd
Normal file
File diff suppressed because it is too large
Load Diff
183
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/Survival_MiST.sv
Normal file
183
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/Survival_MiST.sv
Normal file
@@ -0,0 +1,183 @@
|
||||
//============================================================================
|
||||
// Arcade: Survival
|
||||
//
|
||||
//-------------------------------------------------------------------------------
|
||||
// DE2-35 Top level for Phoenix by Dar (darfpga@aol.fr) (April 2016)
|
||||
// http://darfpga.blogspot.fr
|
||||
//
|
||||
//
|
||||
//-------------------------------------------------------------------------------
|
||||
|
||||
module Survival_MiST
|
||||
(
|
||||
output LED,
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output AUDIO_L,
|
||||
output AUDIO_R,
|
||||
input SPI_SCK,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
input SPI_SS2,
|
||||
input SPI_SS3,
|
||||
input CONF_DATA0,
|
||||
input CLOCK_27
|
||||
);
|
||||
|
||||
`include "rtl\build_id.v"
|
||||
|
||||
localparam CONF_STR = {
|
||||
"Survival;;",
|
||||
"O2,Rotate Controls,Off,On;",
|
||||
"O34,Scanlines,Off,25%,50%,75%;",
|
||||
"T6,Reset;",
|
||||
"V,v1.20.",`BUILD_DATE
|
||||
};
|
||||
|
||||
assign LED = 1;
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
|
||||
wire clk_sys, clk_28, clk_1p79;
|
||||
wire pll_locked;
|
||||
pll pll(
|
||||
.inclk0(CLOCK_27),
|
||||
.areset(0),
|
||||
.c0(clk_sys),//11
|
||||
.c1(clk_28),//28
|
||||
.c2(clk_1p79)//1.79
|
||||
);
|
||||
|
||||
wire [31:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
wire [7:0] joystick_0;
|
||||
wire [7:0] joystick_1;
|
||||
wire scandoublerD;
|
||||
wire ypbpr;
|
||||
wire [10:0] ps2_key;
|
||||
reg [7:0] audio;
|
||||
wire hb1, hb2, vb;
|
||||
wire blankn = ~((hb1 & hb2) | vb);
|
||||
wire ce_pix;
|
||||
wire hs, vs;
|
||||
wire [1:0] r,g,b;
|
||||
|
||||
phoenix phoenix(
|
||||
.clk(clk_sys),
|
||||
.clk_28(clk_28),
|
||||
.clk_1p79(clk_1p79),
|
||||
.reset(status[0] | status[6] | buttons[1]),
|
||||
.dip_switch(8'b00001111),
|
||||
.btn_coin(btn_coin),
|
||||
.btn_player_start1(~btn_coin),
|
||||
.btn_player_start2(~btn_coin),
|
||||
.btn_fire(m_fire),
|
||||
.btn_le(m_left),
|
||||
.btn_ri(m_right),
|
||||
.btn_up(m_up),
|
||||
.btn_dw(m_down),
|
||||
.video_r(r),
|
||||
.video_g(g),
|
||||
.video_b(b),
|
||||
.video_hs(hs),
|
||||
.video_vs(vs),
|
||||
.video_vblank(vb),
|
||||
.video_hblank_bg(hb1),
|
||||
.video_hblank_fg(hb2),
|
||||
.audio(audio)
|
||||
);
|
||||
|
||||
mist_video #(.COLOR_DEPTH(2)) mist_video(
|
||||
.clk_sys(clk_sys),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.SPI_SS3(SPI_SS3),
|
||||
.SPI_DI(SPI_DI),
|
||||
.R(blankn ? r : 0),
|
||||
.G(blankn ? g : 0),
|
||||
.B(blankn ? b : 0),
|
||||
.HSync(~hs),
|
||||
.VSync(~vs),
|
||||
.VGA_R(VGA_R),
|
||||
.VGA_G(VGA_G),
|
||||
.VGA_B(VGA_B),
|
||||
.VGA_VS(VGA_VS),
|
||||
.VGA_HS(VGA_HS),
|
||||
.ce_divider(1'b1),
|
||||
.rotate({1'b1,status[2]}),
|
||||
.scandoubler_disable(scandoublerD),
|
||||
.scanlines(scandoublerD ? 2'b00 : status[4:3]),
|
||||
.ypbpr(ypbpr)
|
||||
);
|
||||
|
||||
user_io #(
|
||||
.STRLEN(($size(CONF_STR)>>3)))
|
||||
user_io(
|
||||
.clk_sys (clk_sys ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_CLK (SPI_SCK ),
|
||||
.SPI_SS_IO (CONF_DATA0 ),
|
||||
.SPI_MISO (SPI_DO ),
|
||||
.SPI_MOSI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoubler_disable (scandoublerD ),
|
||||
.ypbpr (ypbpr ),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
.joystick_0 (joystick_0 ),
|
||||
.joystick_1 (joystick_1 ),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
dac #(
|
||||
.C_bits(16))
|
||||
dac(
|
||||
.clk_i(clk_sys),
|
||||
.res_n_i(1),
|
||||
.dac_i({audio,audio}),
|
||||
.dac_o(AUDIO_L)
|
||||
);
|
||||
// Rotated Normal
|
||||
//wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
|
||||
//wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
|
||||
wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
|
||||
wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
|
||||
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
|
||||
wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
|
||||
|
||||
reg btn_one_player = 0;
|
||||
reg btn_two_players = 0;
|
||||
reg btn_left = 0;
|
||||
reg btn_right = 0;
|
||||
reg btn_down = 0;
|
||||
reg btn_up = 0;
|
||||
reg btn_fire1 = 0;
|
||||
reg btn_fire2 = 0;
|
||||
reg btn_coin = 0;
|
||||
wire key_pressed;
|
||||
wire [7:0] key_code;
|
||||
wire key_strobe;
|
||||
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
if(key_strobe) begin
|
||||
case(key_code)
|
||||
'h75: btn_up <= key_pressed; // up
|
||||
'h72: btn_down <= key_pressed; // down
|
||||
'h6B: btn_left <= key_pressed; // left
|
||||
'h74: btn_right <= key_pressed; // right
|
||||
'h76: btn_coin <= key_pressed; // ESC
|
||||
'h05: btn_one_player <= key_pressed; // F1
|
||||
'h06: btn_two_players <= key_pressed; // F2
|
||||
'h29: btn_fire1 <= key_pressed; // Space
|
||||
'h11: btn_fire2 <= key_pressed; // Alt
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
1073
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/T80/T80.vhd
Normal file
1073
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/T80/T80.vhd
Normal file
File diff suppressed because it is too large
Load Diff
185
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/T80/T8080se.vhd
Normal file
185
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/T80/T8080se.vhd
Normal file
@@ -0,0 +1,185 @@
|
||||
--
|
||||
-- 8080 compatible microprocessor core, synchronous top level with clock enable
|
||||
-- Different timing than the original 8080
|
||||
-- Inputs needs to be synchronous and outputs may glitch
|
||||
--
|
||||
-- Version : 0242
|
||||
--
|
||||
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
-- STACK status output not supported
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0237 : First version
|
||||
--
|
||||
-- 0238 : Updated for T80 interface change
|
||||
--
|
||||
-- 0240 : Updated for T80 interface change
|
||||
--
|
||||
-- 0242 : Updated for T80 interface change
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.T80_Pack.all;
|
||||
|
||||
entity T8080se is
|
||||
generic(
|
||||
Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK : in std_logic;
|
||||
CLKEN : in std_logic;
|
||||
READY : in std_logic;
|
||||
HOLD : in std_logic;
|
||||
INT : in std_logic;
|
||||
INTE : out std_logic;
|
||||
DBIN : out std_logic;
|
||||
SYNC : out std_logic;
|
||||
VAIT : out std_logic;
|
||||
HLDA : out std_logic;
|
||||
WR_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T8080se;
|
||||
|
||||
architecture rtl of T8080se is
|
||||
|
||||
signal IntCycle_n : std_logic;
|
||||
signal NoRead : std_logic;
|
||||
signal Write : std_logic;
|
||||
signal IORQ : std_logic;
|
||||
signal INT_n : std_logic;
|
||||
signal HALT_n : std_logic;
|
||||
signal BUSRQ_n : std_logic;
|
||||
signal BUSAK_n : std_logic;
|
||||
signal DO_i : std_logic_vector(7 downto 0);
|
||||
signal DI_Reg : std_logic_vector(7 downto 0);
|
||||
signal MCycle : std_logic_vector(2 downto 0);
|
||||
signal TState : std_logic_vector(2 downto 0);
|
||||
signal One : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
INT_n <= not INT;
|
||||
BUSRQ_n <= HOLD;
|
||||
HLDA <= not BUSAK_n;
|
||||
SYNC <= '1' when TState = "001" else '0';
|
||||
VAIT <= '1' when TState = "010" else '0';
|
||||
One <= '1';
|
||||
|
||||
DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA
|
||||
DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n
|
||||
DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!!
|
||||
DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA
|
||||
DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT
|
||||
DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1
|
||||
DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP
|
||||
DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR
|
||||
|
||||
u0 : T80
|
||||
generic map(
|
||||
Mode => Mode,
|
||||
IOWait => 0)
|
||||
port map(
|
||||
CEN => CLKEN,
|
||||
M1_n => open,
|
||||
IORQ => IORQ,
|
||||
NoRead => NoRead,
|
||||
Write => Write,
|
||||
RFSH_n => open,
|
||||
HALT_n => HALT_n,
|
||||
WAIT_n => READY,
|
||||
INT_n => INT_n,
|
||||
NMI_n => One,
|
||||
RESET_n => RESET_n,
|
||||
BUSRQ_n => BUSRQ_n,
|
||||
BUSAK_n => BUSAK_n,
|
||||
CLK_n => CLK,
|
||||
A => A,
|
||||
DInst => DI,
|
||||
DI => DI_Reg,
|
||||
DO => DO_i,
|
||||
MC => MCycle,
|
||||
TS => TState,
|
||||
IntCycle_n => IntCycle_n,
|
||||
IntE => INTE);
|
||||
|
||||
process (RESET_n, CLK)
|
||||
begin
|
||||
if RESET_n = '0' then
|
||||
DBIN <= '0';
|
||||
WR_n <= '1';
|
||||
DI_Reg <= "00000000";
|
||||
elsif CLK'event and CLK = '1' then
|
||||
if CLKEN = '1' then
|
||||
DBIN <= '0';
|
||||
WR_n <= '1';
|
||||
if MCycle = "001" then
|
||||
if TState = "001" or (TState = "010" and READY = '0') then
|
||||
DBIN <= IntCycle_n;
|
||||
end if;
|
||||
else
|
||||
if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
|
||||
DBIN <= '1';
|
||||
end if;
|
||||
if T2Write = 0 then
|
||||
if TState = "010" and Write = '1' then
|
||||
WR_n <= '0';
|
||||
end if;
|
||||
else
|
||||
if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
|
||||
WR_n <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if TState = "010" and READY = '1' then
|
||||
DI_Reg <= DI;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
351
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/T80/T80_ALU.vhd
Normal file
351
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/T80/T80_ALU.vhd
Normal file
@@ -0,0 +1,351 @@
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0247
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
|
||||
--
|
||||
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
|
||||
--
|
||||
-- 0240 : Added GB operations
|
||||
--
|
||||
-- 0242 : Cleanup
|
||||
--
|
||||
-- 0247 : Cleanup
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_ALU is
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_ALU;
|
||||
|
||||
architecture rtl of T80_ALU is
|
||||
|
||||
procedure AddSub(A : std_logic_vector;
|
||||
B : std_logic_vector;
|
||||
Sub : std_logic;
|
||||
Carry_In : std_logic;
|
||||
signal Res : out std_logic_vector;
|
||||
signal Carry : out std_logic) is
|
||||
variable B_i : unsigned(A'length - 1 downto 0);
|
||||
variable Res_i : unsigned(A'length + 1 downto 0);
|
||||
begin
|
||||
if Sub = '1' then
|
||||
B_i := not unsigned(B);
|
||||
else
|
||||
B_i := unsigned(B);
|
||||
end if;
|
||||
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
|
||||
Carry <= Res_i(A'length + 1);
|
||||
Res <= std_logic_vector(Res_i(A'length downto 1));
|
||||
end;
|
||||
|
||||
-- AddSub variables (temporary signals)
|
||||
signal UseCarry : std_logic;
|
||||
signal Carry7_v : std_logic;
|
||||
signal Overflow_v : std_logic;
|
||||
signal HalfCarry_v : std_logic;
|
||||
signal Carry_v : std_logic;
|
||||
signal Q_v : std_logic_vector(7 downto 0);
|
||||
|
||||
signal BitMask : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
with IR(5 downto 3) select BitMask <= "00000001" when "000",
|
||||
"00000010" when "001",
|
||||
"00000100" when "010",
|
||||
"00001000" when "011",
|
||||
"00010000" when "100",
|
||||
"00100000" when "101",
|
||||
"01000000" when "110",
|
||||
"10000000" when others;
|
||||
|
||||
UseCarry <= not ALU_Op(2) and ALU_Op(0);
|
||||
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
|
||||
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
|
||||
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
|
||||
OverFlow_v <= Carry_v xor Carry7_v;
|
||||
|
||||
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
|
||||
variable Q_t : std_logic_vector(7 downto 0);
|
||||
variable DAA_Q : unsigned(8 downto 0);
|
||||
begin
|
||||
Q_t := "--------";
|
||||
F_Out <= F_In;
|
||||
DAA_Q := "---------";
|
||||
case ALU_Op is
|
||||
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_C) <= '0';
|
||||
case ALU_OP(2 downto 0) is
|
||||
when "000" | "001" => -- ADD, ADC
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_C) <= Carry_v;
|
||||
F_Out(Flag_H) <= HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "010" | "011" | "111" => -- SUB, SBC, CP
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_N) <= '1';
|
||||
F_Out(Flag_C) <= not Carry_v;
|
||||
F_Out(Flag_H) <= not HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "100" => -- AND
|
||||
Q_t(7 downto 0) := BusA and BusB;
|
||||
F_Out(Flag_H) <= '1';
|
||||
when "101" => -- XOR
|
||||
Q_t(7 downto 0) := BusA xor BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
when others => -- OR "110"
|
||||
Q_t(7 downto 0) := BusA or BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
end case;
|
||||
if ALU_Op(2 downto 0) = "111" then -- CP
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
else
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
end if;
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
if Z16 = '1' then
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
|
||||
end if;
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
case ALU_Op(2 downto 0) is
|
||||
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
|
||||
when others =>
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
end case;
|
||||
if Arith16 = '1' then
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
end if;
|
||||
when "1100" =>
|
||||
-- DAA
|
||||
F_Out(Flag_H) <= F_In(Flag_H);
|
||||
F_Out(Flag_C) <= F_In(Flag_C);
|
||||
DAA_Q(7 downto 0) := unsigned(BusA);
|
||||
DAA_Q(8) := '0';
|
||||
if F_In(Flag_N) = '0' then
|
||||
-- After addition
|
||||
-- Alow > 9 or H = 1
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if (DAA_Q(3 downto 0) > 9) then
|
||||
F_Out(Flag_H) <= '1';
|
||||
else
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q := DAA_Q + 6;
|
||||
end if;
|
||||
-- new Ahigh > 9 or C = 1
|
||||
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q + 96; -- 0x60
|
||||
end if;
|
||||
else
|
||||
-- After subtraction
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if DAA_Q(3 downto 0) > 5 then
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
|
||||
end if;
|
||||
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q - 352; -- 0x160
|
||||
end if;
|
||||
end if;
|
||||
F_Out(Flag_X) <= DAA_Q(3);
|
||||
F_Out(Flag_Y) <= DAA_Q(5);
|
||||
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
|
||||
Q_t := std_logic_vector(DAA_Q(7 downto 0));
|
||||
if DAA_Q(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= DAA_Q(7);
|
||||
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
|
||||
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
|
||||
when "1101" | "1110" =>
|
||||
-- RLD, RRD
|
||||
Q_t(7 downto 4) := BusA(7 downto 4);
|
||||
if ALU_Op(0) = '1' then
|
||||
Q_t(3 downto 0) := BusB(7 downto 4);
|
||||
else
|
||||
Q_t(3 downto 0) := BusB(3 downto 0);
|
||||
end if;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
when "1001" =>
|
||||
-- BIT
|
||||
Q_t(7 downto 0) := BusB and BitMask;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
F_Out(Flag_P) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
F_Out(Flag_P) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_H) <= '1';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= '0';
|
||||
F_Out(Flag_Y) <= '0';
|
||||
if IR(2 downto 0) /= "110" then
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
end if;
|
||||
when "1010" =>
|
||||
-- SET
|
||||
Q_t(7 downto 0) := BusB or BitMask;
|
||||
when "1011" =>
|
||||
-- RES
|
||||
Q_t(7 downto 0) := BusB and not BitMask;
|
||||
when "1000" =>
|
||||
-- ROT
|
||||
case IR(5 downto 3) is
|
||||
when "000" => -- RLC
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "010" => -- RL
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "001" => -- RRC
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(0);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "011" => -- RR
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "100" => -- SLA
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '0';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "110" => -- SLL (Undocumented) / SWAP
|
||||
if Mode = 3 then
|
||||
Q_t(7 downto 4) := BusA(3 downto 0);
|
||||
Q_t(3 downto 0) := BusA(7 downto 4);
|
||||
F_Out(Flag_C) <= '0';
|
||||
else
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '1';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
end if;
|
||||
when "101" => -- SRA
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when others => -- SRL
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := '0';
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
end case;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
if ISet = "00" then
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
Q <= Q_t;
|
||||
end process;
|
||||
|
||||
end;
|
||||
1934
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/T80/T80_MCode.vhd
Normal file
1934
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/T80/T80_MCode.vhd
Normal file
File diff suppressed because it is too large
Load Diff
208
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/T80/T80_Pack.vhd
Normal file
208
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/T80/T80_Pack.vhd
Normal file
@@ -0,0 +1,208 @@
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0242
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
package T80_Pack is
|
||||
|
||||
component T80
|
||||
generic(
|
||||
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
IORQ : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DInst : in std_logic_vector(7 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0);
|
||||
MC : out std_logic_vector(2 downto 0);
|
||||
TS : out std_logic_vector(2 downto 0);
|
||||
IntCycle_n : out std_logic;
|
||||
IntE : out std_logic;
|
||||
Stop : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_Reg
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_MCode
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
IR : in std_logic_vector(7 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
MCycle : in std_logic_vector(2 downto 0);
|
||||
F : in std_logic_vector(7 downto 0);
|
||||
NMICycle : in std_logic;
|
||||
IntCycle : in std_logic;
|
||||
MCycles : out std_logic_vector(2 downto 0);
|
||||
TStates : out std_logic_vector(2 downto 0);
|
||||
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
|
||||
Inc_PC : out std_logic;
|
||||
Inc_WZ : out std_logic;
|
||||
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
|
||||
Read_To_Reg : out std_logic;
|
||||
Read_To_Acc : out std_logic;
|
||||
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
|
||||
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
|
||||
ALU_Op : out std_logic_vector(3 downto 0);
|
||||
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
|
||||
Save_ALU : out std_logic;
|
||||
PreserveC : out std_logic;
|
||||
Arith16 : out std_logic;
|
||||
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
|
||||
IORQ : out std_logic;
|
||||
Jump : out std_logic;
|
||||
JumpE : out std_logic;
|
||||
JumpXY : out std_logic;
|
||||
Call : out std_logic;
|
||||
RstP : out std_logic;
|
||||
LDZ : out std_logic;
|
||||
LDW : out std_logic;
|
||||
LDSPHL : out std_logic;
|
||||
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
|
||||
ExchangeDH : out std_logic;
|
||||
ExchangeRp : out std_logic;
|
||||
ExchangeAF : out std_logic;
|
||||
ExchangeRS : out std_logic;
|
||||
I_DJNZ : out std_logic;
|
||||
I_CPL : out std_logic;
|
||||
I_CCF : out std_logic;
|
||||
I_SCF : out std_logic;
|
||||
I_RETN : out std_logic;
|
||||
I_BT : out std_logic;
|
||||
I_BC : out std_logic;
|
||||
I_BTR : out std_logic;
|
||||
I_RLD : out std_logic;
|
||||
I_RRD : out std_logic;
|
||||
I_INRC : out std_logic;
|
||||
SetDI : out std_logic;
|
||||
SetEI : out std_logic;
|
||||
IMode : out std_logic_vector(1 downto 0);
|
||||
Halt : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_ALU
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
end;
|
||||
105
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/T80/T80_Reg.vhd
Normal file
105
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/T80/T80_Reg.vhd
Normal file
@@ -0,0 +1,105 @@
|
||||
--
|
||||
-- T80 Registers, technology independent
|
||||
--
|
||||
-- Version : 0244
|
||||
--
|
||||
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t51/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0242 : Initial release
|
||||
--
|
||||
-- 0244 : Changed to single register file
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_Reg is
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_Reg;
|
||||
|
||||
architecture rtl of T80_Reg is
|
||||
|
||||
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
|
||||
signal RegsH : Register_Image(0 to 7);
|
||||
signal RegsL : Register_Image(0 to 7);
|
||||
|
||||
begin
|
||||
|
||||
process (Clk)
|
||||
begin
|
||||
if Clk'event and Clk = '1' then
|
||||
if CEN = '1' then
|
||||
if WEH = '1' then
|
||||
RegsH(to_integer(unsigned(AddrA))) <= DIH;
|
||||
end if;
|
||||
if WEL = '1' then
|
||||
RegsL(to_integer(unsigned(AddrA))) <= DIL;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DOAH <= RegsH(to_integer(unsigned(AddrA)));
|
||||
DOAL <= RegsL(to_integer(unsigned(AddrA)));
|
||||
DOBH <= RegsH(to_integer(unsigned(AddrB)));
|
||||
DOBL <= RegsL(to_integer(unsigned(AddrB)));
|
||||
DOCH <= RegsH(to_integer(unsigned(AddrC)));
|
||||
DOCL <= RegsL(to_integer(unsigned(AddrC)));
|
||||
|
||||
end;
|
||||
35
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/build_id.tcl
Normal file
35
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/build_id.tcl
Normal file
@@ -0,0 +1,35 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "rtl/build_id.v"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
82
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/gen_ram.vhd
Normal file
82
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/gen_ram.vhd
Normal file
@@ -0,0 +1,82 @@
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- Syntiac's generic VHDL support files.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
|
||||
-- http://www.syntiac.com/fpga64.html
|
||||
--
|
||||
-- Modified April 2016 by Dar (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
-- Remove address register when writing
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- gen_rwram.vhd
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- generic ram.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
entity gen_ram is
|
||||
generic (
|
||||
dWidth : integer := 8;
|
||||
aWidth : integer := 10
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
we : in std_logic;
|
||||
addr : in std_logic_vector((aWidth-1) downto 0);
|
||||
d : in std_logic_vector((dWidth-1) downto 0);
|
||||
q : out std_logic_vector((dWidth-1) downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
architecture rtl of gen_ram is
|
||||
subtype addressRange is integer range 0 to ((2**aWidth)-1);
|
||||
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
|
||||
signal ram: ramDef;
|
||||
|
||||
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
|
||||
signal qReg : std_logic_vector((dWidth-1) downto 0);
|
||||
begin
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Signals to entity interface
|
||||
-- -----------------------------------------------------------------------
|
||||
q <= qReg;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Memory write
|
||||
-- -----------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if we = '1' then
|
||||
ram(to_integer(unsigned(addr))) <= d;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Memory read
|
||||
-- -----------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- qReg <= ram(to_integer(unsigned(rAddrReg)));
|
||||
-- rAddrReg <= addr;
|
||||
qReg <= ram(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
|
||||
428
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/phoenix.vhd
Normal file
428
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/phoenix.vhd
Normal file
@@ -0,0 +1,428 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- DE2-35 Top level for Phoenix by Dar (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity phoenix is
|
||||
generic (
|
||||
C_test_picture: boolean := false;
|
||||
C_tile_rom: boolean := true; -- false: disable tile ROM to try game logic on small FPGA
|
||||
-- reduce ROMs: 14 is normal game, 13 will draw initial screen, 12 will repeatedly blink 1 line of garbage
|
||||
C_autofire: boolean := true;
|
||||
-- C_audio: boolean := true;
|
||||
C_prog_rom_addr_bits: integer range 12 to 14 := 14
|
||||
);
|
||||
port(
|
||||
clk : in std_logic; -- 11 MHz for TV, 25 MHz for VGA
|
||||
clk_28 : in std_logic;
|
||||
clk_1p79 : in std_logic;
|
||||
reset : in std_logic;
|
||||
ce_pix : out std_logic;
|
||||
|
||||
dip_switch : in std_logic_vector(7 downto 0);
|
||||
-- game controls, normal logic '1':pressed, '0':released
|
||||
|
||||
btn_coin: in std_logic;
|
||||
btn_player_start1: in std_logic;
|
||||
btn_player_start2: in std_logic;
|
||||
btn_fire, btn_le, btn_ri, btn_up, btn_dw: in std_logic;
|
||||
|
||||
video_r : out std_logic_vector(1 downto 0);
|
||||
video_g : out std_logic_vector(1 downto 0);
|
||||
video_b : out std_logic_vector(1 downto 0);
|
||||
video_vblank, video_hblank_bg, video_hblank_fg: out std_logic;
|
||||
video_hs : out std_logic;
|
||||
video_vs : out std_logic;
|
||||
|
||||
audio : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end phoenix;
|
||||
|
||||
architecture struct of phoenix is
|
||||
|
||||
signal reset_n: std_logic;
|
||||
|
||||
signal hcnt : std_logic_vector(9 downto 1);
|
||||
signal vcnt : std_logic_vector(8 downto 1);
|
||||
signal sync : std_logic;
|
||||
signal adrsel : std_logic;
|
||||
signal rdy : std_logic := '1';
|
||||
signal vblank : std_logic;
|
||||
signal hblank_bkgrd : std_logic;
|
||||
signal hblank_frgrd : std_logic;
|
||||
signal ce_pix1 : std_logic;
|
||||
|
||||
signal cpu_adr : std_logic_vector(15 downto 0);
|
||||
signal cpu_di : std_logic_vector( 7 downto 0);
|
||||
signal cpu_do : std_logic_vector( 7 downto 0);
|
||||
signal cpu_wr_n : std_logic;
|
||||
signal prog_do : std_logic_vector( 7 downto 0);
|
||||
signal S_prog_rom_addr : std_logic_vector(13 downto 0);
|
||||
|
||||
signal frgnd_horz_cnt : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal bkgnd_horz_cnt : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal vert_cnt : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
|
||||
signal frgnd_ram_adr: std_logic_vector(10 downto 0) := (others =>'0');
|
||||
signal bkgnd_ram_adr: std_logic_vector(10 downto 0) := (others =>'0');
|
||||
signal frgnd_ram_do : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
signal bkgnd_ram_do : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
signal frgnd_ram_we : std_logic := '0';
|
||||
signal bkgnd_ram_we : std_logic := '0';
|
||||
|
||||
signal frgnd_graph_adr : std_logic_vector(10 downto 0) := (others =>'0');
|
||||
signal bkgnd_graph_adr : std_logic_vector(10 downto 0) := (others =>'0');
|
||||
signal palette_adr : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
|
||||
signal frgnd_clk : std_logic;
|
||||
signal bkgnd_clk : std_logic;
|
||||
|
||||
signal frgnd_tile_id : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal bkgnd_tile_id : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
|
||||
signal frgnd_bit0_graph : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal frgnd_bit1_graph : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal bkgnd_bit0_graph : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal bkgnd_bit1_graph : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
|
||||
signal frgnd_bit0_graph_r : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal frgnd_bit1_graph_r : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal bkgnd_bit0_graph_r : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal bkgnd_bit1_graph_r : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
|
||||
signal fr_bit0 : std_logic;
|
||||
signal fr_bit1 : std_logic;
|
||||
signal bk_bit0 : std_logic;
|
||||
signal bk_bit1 : std_logic;
|
||||
signal fr_lin : std_logic_vector(2 downto 0);
|
||||
signal bk_lin : std_logic_vector(2 downto 0);
|
||||
|
||||
signal color_set : std_logic;
|
||||
signal color_id : std_logic_vector(5 downto 0);
|
||||
signal rgb_0 : std_logic_vector(3 downto 0);
|
||||
signal rgb_1 : std_logic_vector(3 downto 0);
|
||||
|
||||
signal player2 : std_logic := '0';
|
||||
signal pl2_cocktail : std_logic := '0';
|
||||
signal bkgnd_offset : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal sound_a : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal sound_b : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
|
||||
signal clk10 : std_logic;
|
||||
signal snd1 : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
signal snd2 : std_logic_vector( 1 downto 0) := (others =>'0');
|
||||
signal snd3 : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
signal song : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
signal mixed : std_logic_vector(11 downto 0) := (others =>'0');
|
||||
signal sound_string : std_logic_vector(31 downto 0);
|
||||
|
||||
signal coin : std_logic;
|
||||
signal player_start : std_logic_vector(1 downto 0);
|
||||
signal buttons : std_logic_vector(3 downto 0);
|
||||
signal R_autofire : std_logic_vector(21 downto 0);
|
||||
signal ay_do : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
signal protection : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
signal chanA : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
signal chanB : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
signal chanC : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
|
||||
COMPONENT ym2149
|
||||
PORT
|
||||
(
|
||||
CLK : IN STD_LOGIC;
|
||||
CE : IN STD_LOGIC;
|
||||
RESET : IN STD_LOGIC;
|
||||
BDIR : IN STD_LOGIC;
|
||||
BC : IN STD_LOGIC;
|
||||
DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
CHANNEL_A : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
CHANNEL_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
CHANNEL_C : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
SEL : IN STD_LOGIC;
|
||||
MODE : IN STD_LOGIC;
|
||||
IOA_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
IOA_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
IOB_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
IOB_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
begin
|
||||
|
||||
video: entity work.phoenix_video
|
||||
port map
|
||||
(
|
||||
clk11 => clk,
|
||||
ce_pix => ce_pix1,
|
||||
hcnt => hcnt,
|
||||
vcnt => vcnt,
|
||||
sync_hs => video_hs,
|
||||
sync_vs => video_vs,
|
||||
adrsel => adrsel, -- RAM address selector ('0')cpu / ('1')video_generator
|
||||
rdy => rdy, -- Ready ('1')cpu can access RAMs read/write
|
||||
vblank => vblank,
|
||||
hblank_frgrd => hblank_frgrd,
|
||||
hblank_bkgrd => hblank_bkgrd,
|
||||
reset => reset
|
||||
);
|
||||
reset_n <= not reset;
|
||||
ce_pix <= ce_pix1;
|
||||
|
||||
-- microprocessor 8085
|
||||
cpu8085 : entity work.T8080se
|
||||
generic map
|
||||
(
|
||||
Mode => 2,
|
||||
T2Write => 0
|
||||
)
|
||||
port map(
|
||||
RESET_n => reset_n,
|
||||
CLK => clk,
|
||||
CLKEN => '1', -- fixme: use it to make 5.5 MHz clock average
|
||||
READY => rdy,
|
||||
HOLD => '1',
|
||||
INT => '1',
|
||||
INTE => open,
|
||||
DBIN => open,
|
||||
SYNC => open,
|
||||
VAIT => open,
|
||||
HLDA => open,
|
||||
WR_n => cpu_wr_n,
|
||||
A => cpu_adr,
|
||||
DI => cpu_di,
|
||||
DO => cpu_do
|
||||
);
|
||||
|
||||
-- mux prog, ram, vblank, switch... to processor data bus in
|
||||
cpu_di <= prog_do when cpu_adr(14) = '0' else
|
||||
frgnd_ram_do when cpu_adr(13 downto 10) = 2#00_00# else
|
||||
bkgnd_ram_do when cpu_adr(13 downto 10) = 2#00_10# else
|
||||
ay_do when cpu_adr(13 downto 10) = 2#01_00# else
|
||||
btn_dw & btn_le & btn_ri & btn_up & btn_fire & btn_player_start2 & btn_player_start1 & coin when cpu_adr(13 downto 10) = 2#11_00# else
|
||||
not vblank & dip_switch(6 downto 0) when cpu_adr(13 downto 10) = 2#11_10# else
|
||||
prog_do;
|
||||
|
||||
-- write enable to RAMs from cpu
|
||||
frgnd_ram_we <= '1' when cpu_wr_n = '0' and cpu_adr(14 downto 10) = "10000" and adrsel = '0' else '0';
|
||||
bkgnd_ram_we <= '1' when cpu_wr_n = '0' and cpu_adr(14 downto 10) = "10010" and adrsel = '0' else '0';
|
||||
|
||||
-- RAMs address mux cpu/video_generator, bank0 for player1, bank1 for player2
|
||||
frgnd_ram_adr <= player2 & cpu_adr(9 downto 0) when adrsel ='0' else player2 & vert_cnt(7 downto 3) & frgnd_horz_cnt(7 downto 3);
|
||||
bkgnd_ram_adr <= player2 & cpu_adr(9 downto 0) when adrsel ='0' else player2 & vert_cnt(7 downto 3) & bkgnd_horz_cnt(7 downto 3);
|
||||
|
||||
-- demux cpu data to registers : background scrolling, sound control,
|
||||
-- player id (1/2), palette color set.
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if cpu_wr_n = '0' then
|
||||
case cpu_adr(14 downto 10) is
|
||||
when "10110" => bkgnd_offset <= cpu_do;
|
||||
when "11000" => sound_a <= cpu_do;--address_w
|
||||
-- when "11010" => sound_a <= cpu_do;--data_w
|
||||
when "10100" => player2 <= cpu_do(0);
|
||||
color_set <= cpu_do(1);
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- player2 and cocktail mode (flip horizontal/vertical)
|
||||
pl2_cocktail <= player2 and dip_switch(7);
|
||||
|
||||
-- horizontal scan video RAMs address background and foreground
|
||||
-- with flip and scroll offset
|
||||
frgnd_horz_cnt <= hcnt(8 downto 1) when pl2_cocktail = '0' else not hcnt(8 downto 1);
|
||||
bkgnd_horz_cnt <= frgnd_horz_cnt + bkgnd_offset;
|
||||
|
||||
-- vertical scan video RAMs address
|
||||
vert_cnt <= vcnt(8 downto 1) when pl2_cocktail = '0' else not (vcnt(8 downto 1) + X"30");
|
||||
|
||||
-- get tile_ids from RAMs
|
||||
frgnd_tile_id <= frgnd_ram_do;
|
||||
bkgnd_tile_id <= bkgnd_ram_do;
|
||||
|
||||
-- address graphix ROMs with tile_ids and line counter
|
||||
frgnd_graph_adr <= frgnd_tile_id & vert_cnt(2 downto 0);
|
||||
bkgnd_graph_adr <= bkgnd_tile_id & vert_cnt(2 downto 0);
|
||||
|
||||
-- latch foreground/background next graphix byte, high bit and low bit
|
||||
-- and palette_ids (fr_lin, bklin)
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if (pl2_cocktail = '0' and (frgnd_horz_cnt(2 downto 0) = "111")) or
|
||||
(pl2_cocktail = '1' and (frgnd_horz_cnt(2 downto 0) = "000")) then
|
||||
frgnd_bit0_graph_r <= frgnd_bit0_graph;
|
||||
frgnd_bit1_graph_r <= frgnd_bit1_graph;
|
||||
fr_lin <= frgnd_tile_id(7 downto 5);
|
||||
end if;
|
||||
if (pl2_cocktail = '0' and (bkgnd_horz_cnt(2 downto 0) = "111")) or
|
||||
(pl2_cocktail = '1' and (bkgnd_horz_cnt(2 downto 0) = "000")) then
|
||||
bkgnd_bit0_graph_r <= bkgnd_bit0_graph;
|
||||
bkgnd_bit1_graph_r <= bkgnd_bit1_graph;
|
||||
bk_lin <= bkgnd_tile_id(7 downto 5);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- demux background and foreground pixel bits (0/1) from graphix byte with horizontal counter
|
||||
-- and apply horizontal and vertical blanking
|
||||
fr_bit0 <= frgnd_bit0_graph_r(to_integer(unsigned(frgnd_horz_cnt(2 downto 0)))) when (vblank or hblank_frgrd)= '0' else '0';
|
||||
fr_bit1 <= frgnd_bit1_graph_r(to_integer(unsigned(frgnd_horz_cnt(2 downto 0)))) when (vblank or hblank_frgrd)= '0' else '0';
|
||||
bk_bit0 <= bkgnd_bit0_graph_r(to_integer(unsigned(bkgnd_horz_cnt(2 downto 0)))) when (vblank or hblank_bkgrd)= '0' else '0';
|
||||
bk_bit1 <= bkgnd_bit1_graph_r(to_integer(unsigned(bkgnd_horz_cnt(2 downto 0)))) when (vblank or hblank_bkgrd)= '0' else '0';
|
||||
|
||||
-- select pixel bits and palette_id with foreground priority
|
||||
color_id <= (fr_bit0 or fr_bit1) & fr_bit1 & fr_bit0 & fr_lin when (fr_bit0 or fr_bit1) = '1' else
|
||||
(fr_bit0 or fr_bit1) & bk_bit1 & bk_bit0 & bk_lin;
|
||||
|
||||
-- address palette with pixel bits color and color set
|
||||
palette_adr <= '0' & color_set & color_id;
|
||||
|
||||
-- output video to top level
|
||||
process(clk) begin
|
||||
if rising_edge(clk) then
|
||||
if ce_pix1='1' then
|
||||
video_vblank <= vblank;
|
||||
video_hblank_fg <= hblank_frgrd;
|
||||
video_hblank_bg <= hblank_bkgrd;
|
||||
if hcnt>=192 then
|
||||
video_r <= rgb_1(0) & rgb_0(0);
|
||||
video_g <= rgb_1(2) & rgb_0(2);
|
||||
video_b <= rgb_1(1) & rgb_0(1);
|
||||
else
|
||||
video_r <= "00";
|
||||
video_g <= "00";
|
||||
video_b <= "00";
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
G_yes_tile_rom: if C_tile_rom generate
|
||||
-- foreground graphix ROM bit0
|
||||
frgnd_bit0 : entity work.prom_ic39
|
||||
port map(
|
||||
clk => clk,
|
||||
addr => frgnd_graph_adr,
|
||||
data => frgnd_bit0_graph
|
||||
);
|
||||
|
||||
-- foreground graphix ROM bit1
|
||||
frgnd_bit1 : entity work.prom_ic40
|
||||
port map(
|
||||
clk => clk,
|
||||
addr => frgnd_graph_adr,
|
||||
data => frgnd_bit1_graph
|
||||
);
|
||||
|
||||
-- background graphix ROM bit0
|
||||
bkgnd_bit0 : entity work.prom_ic23
|
||||
port map(
|
||||
clk => clk,
|
||||
addr => bkgnd_graph_adr,
|
||||
data => bkgnd_bit0_graph
|
||||
);
|
||||
|
||||
-- background graphix ROM bit1
|
||||
bkgnd_bit1 : entity work.prom_ic24
|
||||
port map(
|
||||
clk => clk,
|
||||
addr => bkgnd_graph_adr,
|
||||
data => bkgnd_bit1_graph
|
||||
);
|
||||
|
||||
-- color palette ROM RBG low intensity
|
||||
palette_0 : entity work.prom_palette_ic40
|
||||
port map(
|
||||
clk => clk,
|
||||
addr => palette_adr,
|
||||
data => rgb_0
|
||||
);
|
||||
|
||||
-- color palette ROM RBG high intensity
|
||||
palette_1 : entity work.prom_palette_ic41
|
||||
port map(
|
||||
clk => clk,
|
||||
addr => palette_adr,
|
||||
data => rgb_1
|
||||
);
|
||||
end generate;
|
||||
|
||||
G_no_tile_rom: if not C_tile_rom generate
|
||||
-- dummy replacement for missing tile ROMs
|
||||
frgnd_bit0_graph <= frgnd_graph_adr(10 downto 3);
|
||||
frgnd_bit1_graph <= "00000000";
|
||||
bkgnd_bit0_graph <= bkgnd_graph_adr(10 downto 3);
|
||||
bkgnd_bit1_graph <= "00000000";
|
||||
rgb_0 <= palette_adr(2 downto 0);
|
||||
rgb_1 <= palette_adr(2 downto 0);
|
||||
end generate;
|
||||
|
||||
-- Program PROM
|
||||
S_prog_rom_addr(C_prog_rom_addr_bits-1 downto 0) <= cpu_adr(C_prog_rom_addr_bits-1 downto 0);
|
||||
prog : entity work.survival_prog
|
||||
port map(
|
||||
clk => clk,
|
||||
addr => S_prog_rom_addr,
|
||||
data => prog_do
|
||||
);
|
||||
|
||||
-- foreground RAM 0x4000-0x433F
|
||||
-- cpu working area 0x4340-0x43FF
|
||||
frgnd_ram : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 11)
|
||||
port map(
|
||||
clk => clk,
|
||||
we => frgnd_ram_we,
|
||||
addr => frgnd_ram_adr,
|
||||
d => cpu_do,
|
||||
q => frgnd_ram_do
|
||||
);
|
||||
|
||||
-- background RAM 0x4800-0x4B3F
|
||||
-- cpu working area 0x4B40-0x4BFF
|
||||
-- stack pointer downward from 0x4BFF
|
||||
bkgnd_ram : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 11)
|
||||
port map(
|
||||
clk => clk,
|
||||
we => bkgnd_ram_we,
|
||||
addr => bkgnd_ram_adr,
|
||||
d => cpu_do,
|
||||
q => bkgnd_ram_do
|
||||
);
|
||||
|
||||
|
||||
music: YM2149
|
||||
port map(
|
||||
-- data bus
|
||||
DI => cpu_do,
|
||||
DO => open,--?
|
||||
BDIR => cpu_wr_n,--?
|
||||
BC => cpu_adr(0),--?
|
||||
SEL => '0',--?
|
||||
MODE => '1',--AY8910
|
||||
CHANNEL_A => chanA,
|
||||
CHANNEL_B => chanB,
|
||||
CHANNEL_C => chanC,
|
||||
IOA_in => (others => '0'),
|
||||
IOA_out => open,
|
||||
IOB_in => (others => '0'),
|
||||
IOB_out => ay_do,--protection
|
||||
CE => clk_1p79,--2.75
|
||||
RESET => not reset_n,
|
||||
CLK => clk
|
||||
);
|
||||
|
||||
audio <= chanA + chanB + chanC;
|
||||
|
||||
end struct;
|
||||
@@ -0,0 +1,230 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Phoenix sound effect1 by Dar (darfpga@aol.fr) (April 2016)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
-- this module generates sound how the birds fly
|
||||
-- how they burn and the ship's barrier activation sound
|
||||
-- it is most often heard module througut all levels of the game
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
entity phoenix_effect1 is
|
||||
generic(
|
||||
-- Command
|
||||
Cmd_Fs: real := 11.0; -- MHz
|
||||
Cmd_V: real := 12.0; -- V
|
||||
Cmd_Vd: real := 0.46; -- V
|
||||
Cmd_Vce: real := 0.2; -- V
|
||||
Cmd_R1: real := 100.0; -- k
|
||||
Cmd_R2: real := 33.0; -- k
|
||||
Cmd_R3: real := 0.47; -- k
|
||||
Cmd_C: real := 6.8; -- uF
|
||||
Cmd_Div2n: integer := 8; -- bits divisor
|
||||
Cmd_bits: integer := 16; -- bits counter
|
||||
-- Oscillator
|
||||
Osc_Fs: real := 11.0; -- MHz
|
||||
Osc_Vb: real := 5.0; -- V
|
||||
Osc_Vce: real := 0.2; -- V
|
||||
Osc_R1: real := 47.0; -- k
|
||||
Osc_R2: real := 47.0; -- k
|
||||
Osc_C: real := 0.001; -- uF
|
||||
Osc_Div2n: integer := 7; -- bits divisor
|
||||
Osc_bits: integer := 6; -- bits counter
|
||||
-- Filter
|
||||
Filt_Fs: real := 11.0; -- MHz
|
||||
Filt_V1: real := 5.0; -- V
|
||||
Filt_V2: real := 0.0; -- V
|
||||
Filt_R1: real := 100.0; -- k
|
||||
Filt_R2: real := 10.0; -- k
|
||||
Filt_C: real := 0.047; -- uF
|
||||
Filt_Div2n: integer := 7; -- bits divisor
|
||||
Filt_bits: integer := 8; -- bits counter
|
||||
|
||||
Vmax: real := 5.0; -- V
|
||||
Vmax_bits: integer := 16 -- number of bits to represent vmax
|
||||
);
|
||||
port(
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
trigger : in std_logic;
|
||||
filter : in std_logic;
|
||||
divider : in std_logic_vector(3 downto 0);
|
||||
snd : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end phoenix_effect1;
|
||||
|
||||
architecture struct of phoenix_effect1 is
|
||||
|
||||
-- integer representation of voltage, full range
|
||||
constant IVmax: integer := integer(2**Vmax_bits)-1;
|
||||
-- command --
|
||||
constant Cmd_div: integer := integer(2**Cmd_Div2n);
|
||||
-- command charge
|
||||
constant Cmd_VFc: real := (Cmd_V*Cmd_R2 + Cmd_Vd*Cmd_R1)/(Cmd_R1 + Cmd_R2); -- V
|
||||
constant Cmd_RCc: real := Cmd_R1*Cmd_R2/(Cmd_R1 + Cmd_R2)*Cmd_C/1000.0; -- s
|
||||
constant Cmd_ikc: integer := integer(Cmd_Fs * 1.0E6 * Cmd_RCc / 2.0**Cmd_Div2n);
|
||||
constant Cmd_iVFc: integer := integer(Cmd_VFc * real(IVmax)/Vmax);
|
||||
-- command discharge
|
||||
constant Cmd_VFd: real := (Cmd_V/Cmd_R1+Cmd_Vd/Cmd_R2+(Cmd_Vd+Cmd_Vce)/Cmd_R3)/(1.0/Cmd_R1+1.0/Cmd_R2+1.0/Cmd_R3); -- V
|
||||
constant Cmd_RCd: real := 1.0/(1.0/Cmd_R1+1.0/Cmd_R2+1.0/Cmd_R3)*Cmd_C/1000.0; -- s
|
||||
constant Cmd_ikd: integer := integer(Cmd_Fs * 1.0E6 * Cmd_RCd / 2.0**Cmd_Div2n);
|
||||
constant Cmd_iVFd: integer := integer(Cmd_VFd * real(IVmax)/Vmax);
|
||||
|
||||
-- oscillator
|
||||
constant Osc_div: integer := integer(2**Osc_Div2n);
|
||||
-- oscillator charge
|
||||
constant Osc_VFc: real := Osc_Vb; -- V
|
||||
constant Osc_RCc: real := (Osc_R1+Osc_R2)*Osc_C/1000.0; -- s
|
||||
constant Osc_ikc: integer := integer(Osc_Fs * 1.0E6 * Osc_RCc / 2.0**Osc_Div2n);
|
||||
constant Osc_iVFc: integer := integer(Osc_VFc * real(IVmax)/Vmax);
|
||||
-- oscillator discharge
|
||||
constant Osc_VFd: real := Osc_Vce; -- V
|
||||
constant Osc_RCd: real := Osc_R2*Osc_C/1000.0; -- s
|
||||
constant Osc_ikd: integer := integer(Osc_Fs * 1.0E6 * Osc_RCd / 2.0**Osc_Div2n);
|
||||
constant Osc_iVFd: integer := integer(Osc_VFd * real(IVmax)/Vmax);
|
||||
|
||||
-- filter
|
||||
constant Filt_div: integer := integer(2**Filt_Div2n);
|
||||
-- filter charge
|
||||
constant Filt_VFc: real := Filt_V1; -- V
|
||||
constant Filt_RCc: real := 1.0/(1.0/Filt_R1+1.0/Filt_R2)*Filt_C/1000.0; -- s
|
||||
constant Filt_ikc: integer := integer(Filt_Fs * 1.0E6 * Filt_RCc / 2.0**Filt_Div2n);
|
||||
constant Filt_iVFc: integer := integer(Filt_VFc * real(IVmax)/Vmax);
|
||||
-- filter discharge
|
||||
constant Filt_VFd: real := Filt_V2; -- V
|
||||
constant Filt_RCd: real := Filt_RCc; -- s
|
||||
constant Filt_ikd: integer := integer(Filt_Fs * 1.0E6 * Filt_RCd / 2.0**Filt_Div2n);
|
||||
constant Filt_iVFd: integer := integer(Filt_VFd * real(IVmax)/Vmax);
|
||||
|
||||
function imax(x,y: integer) return integer is begin
|
||||
if x > y then
|
||||
return x;
|
||||
else
|
||||
return y;
|
||||
end if;
|
||||
end imax;
|
||||
|
||||
signal u_c1 : unsigned(15 downto 0) := (others => '0');
|
||||
signal u_c2 : unsigned(15 downto 0) := (others => '0');
|
||||
signal flip : std_logic := '0';
|
||||
|
||||
signal u_cf : unsigned(15 downto 0) := (others => '0');
|
||||
signal sound : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
-- Commande
|
||||
-- R1 = 100k, R2 = 33k, R3 = 0.47k C=6.8e-6 SR=10MHz
|
||||
-- Charge : VF1 = 43559, k1 = 6591 (R1//R2)
|
||||
-- Decharge : VF2 = 9300, k2 = 123 (R1//R2//R3)
|
||||
-- Div = 2^8
|
||||
|
||||
process (clk)
|
||||
variable cnt: integer range 0 to imax(Cmd_ikc,Cmd_ikd) := 0;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset = '1' then
|
||||
cnt := 0;
|
||||
u_c1 <= (others => '0');
|
||||
else
|
||||
cnt := cnt + 1;
|
||||
if trigger = '1' then
|
||||
if cnt = Cmd_ikc then
|
||||
cnt := 0;
|
||||
u_c1 <= u_c1 + (Cmd_iVFc - u_c1)/Cmd_div;
|
||||
end if;
|
||||
else
|
||||
if cnt = Cmd_ikd then
|
||||
cnt := 0;
|
||||
u_c1 <= u_c1 - (u_c1 - Cmd_iVFd)/Cmd_div;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Oscillateur
|
||||
-- R1 = 47k, R2 = 47k, C=0.001e-6 SR=50MHz
|
||||
-- Charge : VF1 = 65535, k1 = 37 (R1+R2)
|
||||
-- Decharge : VF2 = 2621, k2 = 18 (R2)
|
||||
-- Div = 2^7
|
||||
|
||||
-- Diviseur
|
||||
-- LS163 : Count up, Sync load when 0xF (no toggle sound if divider = 0xF)
|
||||
-- LS74 : Divide by 2
|
||||
|
||||
process (clk)
|
||||
variable cnt: integer range 0 to imax(Osc_ikc,Osc_ikd) := 0;
|
||||
variable cnt2: unsigned(3 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset = '1' then
|
||||
cnt := 0;
|
||||
u_c2 <= (others => '0');
|
||||
flip <= '0';
|
||||
else
|
||||
if u_c2 > u_c1 then flip <= '0'; end if;
|
||||
if u_c2 < u_c1/2 then
|
||||
flip <= '1';
|
||||
if flip = '0' then
|
||||
cnt2 := cnt2 + 1;
|
||||
if cnt2 = "0000" then
|
||||
cnt2 := unsigned(divider);
|
||||
if divider /= "1111" then sound <= not sound; end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
cnt := cnt + 1;
|
||||
if flip = '1' then
|
||||
if cnt = Osc_ikc then
|
||||
cnt := 0;
|
||||
u_c2 <= u_c2 + (Osc_iVFc - u_c2)/Osc_div;
|
||||
end if;
|
||||
else
|
||||
if cnt = Osc_ikd then
|
||||
cnt := 0;
|
||||
u_c2 <= u_c2 - (u_c2 - Osc_iVFd)/Osc_div;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- filter
|
||||
-- R1 = 10k, R2 = 100k, C=0.047e-6, SR=10MHz
|
||||
-- Charge : VF1= 65535, k1 = 33 (R1//R2)
|
||||
-- Decharge : VF2= 0 , k2 = 33 (R1//R2)
|
||||
-- Div = 2^7
|
||||
|
||||
process (clk)
|
||||
variable cnt: integer range 0 to imax(Filt_ikc,Filt_ikd) := 0;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset = '1' then
|
||||
cnt := 0;
|
||||
u_cf <= (others => '0');
|
||||
else
|
||||
cnt := cnt + 1;
|
||||
if sound = '1' then
|
||||
if cnt = Filt_ikc then
|
||||
cnt := 0;
|
||||
u_cf <= u_cf + (Filt_iVFc - u_cf)/Filt_div;
|
||||
end if;
|
||||
else
|
||||
if cnt = Filt_ikd then
|
||||
cnt := 0;
|
||||
u_cf <= u_cf - (u_cf - Filt_iVFd)/Filt_div;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
with filter select snd <= std_logic_vector(u_cf(15 downto 8)) when '1', sound&"0000000" when others;
|
||||
|
||||
end struct;
|
||||
@@ -0,0 +1,387 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Phoenix sound effect2 by Dar (darfpga@aol.fr) (April 2016)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
-- this module outputs sound of mothership's descend
|
||||
-- it could be heard at beginning of level 5
|
||||
-- the prrrrr...vioooouuuuu sound
|
||||
-- fixme:
|
||||
-- the VCO control levels are too coarse (quantized)
|
||||
-- frequency transitions are heard in large steps
|
||||
-- instead of continous sweep
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
entity phoenix_effect2 is
|
||||
generic(
|
||||
-- Oscillator 1
|
||||
Osc1_Fs: real := 11.0; -- MHz
|
||||
Osc1_Vb: real := 5.0; -- V
|
||||
Osc1_Vce: real := 0.2; -- V
|
||||
Osc1_R1: real := 47.0; -- k
|
||||
Osc1_R2: real := 100.0; -- k
|
||||
Osc1_C1: real := 0.01; -- uF
|
||||
Osc1_C2: real := 0.47; -- uF
|
||||
Osc1_C3: real := 1.0; -- uF
|
||||
Osc1_Div2n: integer := 8; -- bits divisor
|
||||
Osc1_bits: integer := 16; -- bits counter
|
||||
-- Oscillator 2
|
||||
Osc2_Fs: real := 11.0; -- MHz
|
||||
Osc2_Vb: real := 5.0; -- V
|
||||
Osc2_Vce: real := 0.2; -- V
|
||||
Osc2_R1: real := 510.0; -- k
|
||||
Osc2_R2: real := 510.0; -- k
|
||||
Osc2_C: real := 1.0; -- uF
|
||||
Osc2_Div2n: integer := 8; -- bits divisor
|
||||
Osc2_bits: integer := 17; -- bits counter
|
||||
-- Filter 2
|
||||
Filt2_Fs: real := 11.0; -- MHz
|
||||
Filt2_V: real := 5.0; -- V
|
||||
Filt2_R1: real := 10.0; -- k
|
||||
Filt2_R2: real := 5.1; -- k
|
||||
Filt2_R3: real := 5.1; -- k
|
||||
Filt2_R4: real := 5.0; -- k
|
||||
Filt2_R5: real := 10.0; -- k
|
||||
Filt2_C: real := 100.0; -- uF
|
||||
Filt2_Div2n: integer := 8; -- bits divisor
|
||||
Filt2_bits: integer := 16; -- bits counter
|
||||
-- Oscillator 3
|
||||
Osc3_Fs: real := 11.0; -- MHz
|
||||
Osc3_Vb: real := 5.0; -- V
|
||||
Osc3_Vce: real := 0.2; -- V
|
||||
Osc3_R1: real := 20.0; -- k
|
||||
Osc3_R2: real := 20.0; -- k
|
||||
Osc3_C: real := 0.001; -- uF
|
||||
Osc3_Div2n: integer := 6; -- bits divisor
|
||||
Osc3_bits: integer := 6; -- bits counter
|
||||
|
||||
C_flip1_0: integer := 22020;
|
||||
C_flip1_1: integer := 33063;
|
||||
C_flip1_scale: integer := 84; -- ??
|
||||
|
||||
|
||||
Vmax: real := 5.0; -- V
|
||||
Vmax_bits: integer := 16 -- number of bits to represent Vmax
|
||||
);
|
||||
|
||||
port(
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
trigger1 : in std_logic;
|
||||
trigger2 : in std_logic;
|
||||
divider : in std_logic_vector(3 downto 0);
|
||||
snd : out std_logic_vector(1 downto 0)
|
||||
);
|
||||
end phoenix_effect2;
|
||||
|
||||
architecture struct of phoenix_effect2 is
|
||||
|
||||
function imax(x,y: integer) return integer is begin
|
||||
if x > y then
|
||||
return x;
|
||||
else
|
||||
return y;
|
||||
end if;
|
||||
end imax;
|
||||
|
||||
-- integer representation of voltage, full range
|
||||
constant IVmax: integer := integer(2**Vmax_bits)-1;
|
||||
-- Oscillator1 --
|
||||
constant Osc1_div: integer := integer(2**Osc1_Div2n);
|
||||
-- Oscillator1 charge/discharge voltages
|
||||
constant Osc1_VFc: real := Osc1_Vb; -- V
|
||||
constant Osc1_iVFc: integer := integer(Osc1_VFc * real(IVmax)/Vmax);
|
||||
constant Osc1_VFd: real := Osc1_Vce; -- V
|
||||
constant Osc1_iVFd: integer := integer(Osc1_VFd * real(IVmax)/Vmax);
|
||||
-- Oscillator1 charge/discharge time constants
|
||||
constant Osc1_T0_RCc: real := (Osc1_R1+Osc1_R2)*Osc1_C1/1000.0; -- s
|
||||
constant Osc1_T0_ikc: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T0_RCc / 2.0**Osc1_Div2n);
|
||||
constant Osc1_T0_RCd: real := Osc1_R2*Osc1_C1/1000.0; -- s
|
||||
constant Osc1_T0_ikd: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T0_RCd / 2.0**Osc1_Div2n);
|
||||
|
||||
constant Osc1_T1_RCc: real := (Osc1_R1+Osc1_R2)*(Osc1_C1+Osc1_C2)/1000.0; -- s
|
||||
constant Osc1_T1_ikc: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T1_RCc / 2.0**Osc1_Div2n);
|
||||
constant Osc1_T1_RCd: real := Osc1_R2*(Osc1_C1+Osc1_C2)/1000.0; -- s
|
||||
constant Osc1_T1_ikd: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T1_RCd / 2.0**Osc1_Div2n);
|
||||
|
||||
constant Osc1_T2_RCc: real := (Osc1_R1+Osc1_R2)*(Osc1_C1+Osc1_C3)/1000.0; -- s
|
||||
constant Osc1_T2_ikc: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T2_RCc / 2.0**Osc1_Div2n);
|
||||
constant Osc1_T2_RCd: real := Osc1_R2*(Osc1_C1+Osc1_C3)/1000.0; -- s
|
||||
constant Osc1_T2_ikd: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T2_RCd / 2.0**Osc1_Div2n);
|
||||
|
||||
constant Osc1_T3_RCc: real := (Osc1_R1+Osc1_R2)*(Osc1_C1+Osc1_C2+Osc1_C3)/1000.0; -- s
|
||||
constant Osc1_T3_ikc: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T3_RCc / 2.0**Osc1_Div2n);
|
||||
constant Osc1_T3_RCd: real := Osc1_R2*(Osc1_C1+Osc1_C2+Osc1_C3)/1000.0; -- s
|
||||
constant Osc1_T3_ikd: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T3_RCd / 2.0**Osc1_Div2n);
|
||||
|
||||
constant Osc1_ik_max: integer := imax( imax(Osc1_T1_ikc,Osc1_T1_ikd), imax(Osc1_T3_ikc,Osc1_T3_ikd));
|
||||
|
||||
-- Oscillator2 --
|
||||
constant Osc2_div: integer := integer(2**Osc2_Div2n);
|
||||
-- Oscillator2 charge/discharge voltages
|
||||
constant Osc2_VFc: real := Osc2_Vb; -- V
|
||||
constant Osc2_iVFc: integer := integer(Osc2_VFc * real(IVmax)/Vmax);
|
||||
constant Osc2_VFd: real := Osc2_Vce; -- V
|
||||
constant Osc2_iVFd: integer := integer(Osc2_VFd * real(IVmax)/Vmax);
|
||||
-- Oscillator2 charge/discharge time constants
|
||||
constant Osc2_RCc: real := (Osc2_R1+Osc2_R2)*Osc2_C/1000.0; -- s
|
||||
constant Osc2_ikc: integer := integer(Osc2_Fs * 1.0E6 * Osc2_RCc / 2.0**Osc2_Div2n);
|
||||
constant Osc2_RCd: real := Osc2_R2*Osc2_C/1000.0; -- s
|
||||
constant Osc2_ikd: integer := integer(Osc2_Fs * 1.0E6 * Osc2_RCd / 2.0**Osc2_Div2n);
|
||||
|
||||
-- Filter2 --
|
||||
constant Filt2_div: integer := integer(2**Filt2_Div2n);
|
||||
constant Filt2_R4p: real := 1.0/(1.0/Filt2_R1+1.0/Filt2_R4); -- k
|
||||
constant Filt2_R5p: real := 1.0/(1.0/Filt2_R1+1.0/Filt2_R5); -- k
|
||||
constant Filt2_Rp: real := 1.0/(1.0/Filt2_R3+1.0/Filt2_R4+1.0/Filt2_R5p); -- k
|
||||
constant Filt2_Rs: real := 1.0/(1.0/Filt2_R2+1.0/Filt2_R3-Filt2_Rp/(Filt2_R3**2)); -- k
|
||||
constant Filt2_RC: real := Filt2_Rs*Filt2_C/1000.0; -- s
|
||||
constant Filt2_ik: integer := integer(Filt2_Fs*1.0E6*Filt2_RC / 2.0**Filt2_Div2n);
|
||||
-- Filter2 voltages
|
||||
constant Filt2_V0: real := Filt2_V*Filt2_Rp*Filt2_Rs/(Filt2_R3*Filt2_R4); -- V
|
||||
constant Filt2_iV0: integer := integer(Filt2_V0 * real(IVmax)/Vmax);
|
||||
constant Filt2_V1: real := Filt2_V*Filt2_Rp*Filt2_Rs/(Filt2_R4p*Filt2_R3); -- V
|
||||
constant Filt2_iV1: integer := integer(Filt2_V1 * real(IVmax)/Vmax);
|
||||
constant Filt2_V2: real := Filt2_V*Filt2_Rp*Filt2_Rs/(Filt2_R3*Filt2_R4)+Filt2_V*Filt2_Rs/Filt2_R2; -- V
|
||||
constant Filt2_iV2: integer := integer(Filt2_V2 * real(IVmax)/Vmax);
|
||||
constant Filt2_V3: real := Filt2_V*Filt2_Rp*Filt2_Rs/(Filt2_R3*Filt2_R4p)+Filt2_V*Filt2_Rs/Filt2_R2; -- V
|
||||
constant Filt2_iV3: integer := integer(Filt2_V3 * real(IVmax)/Vmax);
|
||||
|
||||
-- Oscillator3 --
|
||||
constant Osc3_div: integer := integer(2**Osc3_Div2n);
|
||||
-- Oscillator3 charge/discharge voltages
|
||||
constant Osc3_VFc: real := Osc3_Vb; -- V
|
||||
constant Osc3_iVFc: integer := integer(Osc3_VFc * real(IVmax)/Vmax);
|
||||
constant Osc3_VFd: real := Osc3_Vce; -- V
|
||||
constant Osc3_iVFd: integer := integer(Osc3_VFd * real(IVmax)/Vmax);
|
||||
-- Oscillator3 charge/discharge time constants
|
||||
constant Osc3_RCc: real := (Osc3_R1+Osc3_R2)*Osc3_C/1000.0; -- s
|
||||
constant Osc3_ikc: integer := integer(Osc3_Fs * 1.0E6 * Osc3_RCc / 2.0**Osc3_Div2n);
|
||||
constant Osc3_RCd: real := Osc3_R2*Osc3_C/1000.0; -- s
|
||||
constant Osc3_ikd: integer := integer(Osc3_Fs * 1.0E6 * Osc3_RCd / 2.0**Osc3_Div2n);
|
||||
|
||||
signal u_c1 : unsigned(15 downto 0) := (others => '0');
|
||||
signal u_c2 : unsigned(15 downto 0) := (others => '0');
|
||||
signal u_c3 : unsigned(16 downto 0) := (others => '0');
|
||||
signal flip1 : std_logic := '0';
|
||||
signal flip2 : std_logic := '0';
|
||||
signal flip3 : std_logic := '0';
|
||||
|
||||
signal triggers : std_logic_vector(1 downto 0) := "00";
|
||||
--signal kc : unsigned(15 downto 0) := (others =>'0');
|
||||
--signal kd : unsigned(15 downto 0) := (others =>'0');
|
||||
signal kc : integer range 0 to Osc1_ik_max;
|
||||
signal kd : integer range 0 to Osc1_ik_max;
|
||||
|
||||
signal u_cf : unsigned(15 downto 0) := (others => '0');
|
||||
signal flips : std_logic_vector(1 downto 0) := "00";
|
||||
signal vf : unsigned(15 downto 0) := (others =>'0');
|
||||
|
||||
signal u_cf_scaled : unsigned(23 downto 0) := (others => '0');
|
||||
signal u_ctrl : unsigned(15 downto 0) := (others => '0');
|
||||
|
||||
signal sound: std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
-- Oscillateur1
|
||||
-- R1 = 47k, R2 = 100k, C1=0.01e-6, C2=0.047e-6, C3=1.000e-6 SR=10MHz
|
||||
-- Div = 2^8
|
||||
|
||||
-- trigger = 00
|
||||
-- Charge : VF1 = 65535, k1 = 57 (R1+R2, C1)
|
||||
-- Decharge : VF2 = 2621, k2 = 39 (R2, C1)
|
||||
-- trigger = 01
|
||||
-- Charge : VF1 = 65535, k1 = 2756 (R1+R2, C1+C2)
|
||||
-- Decharge : VF2 = 2621, k2 = 1875 (R2, C1+C2)
|
||||
-- trigger = 10
|
||||
-- Charge : VF1 = 65535, k1 = 5800 (R1+R2, C1+C3)
|
||||
-- Decharge : VF2 = 2621, k2 = 3945 (R2, C1+C3)
|
||||
-- trigger = 11
|
||||
-- Charge : VF1 = 65535, k1 = 8498 (R1+R2, C1+C2+C3)
|
||||
-- Decharge : VF2 = 2621, k2 = 5781 (R2, C1+C2+C3)
|
||||
|
||||
triggers <= trigger2 & trigger1;
|
||||
|
||||
with triggers select
|
||||
kc <= Osc1_T0_ikc when "00",
|
||||
Osc1_T1_ikc when "01",
|
||||
Osc1_T2_ikc when "10",
|
||||
Osc1_T3_ikc when others;
|
||||
|
||||
with triggers select
|
||||
kd <= Osc1_T0_ikd when "00",
|
||||
Osc1_T1_ikd when "01",
|
||||
Osc1_T2_ikd when "10",
|
||||
Osc1_T3_ikd when others;
|
||||
|
||||
process (clk)
|
||||
variable cnt: integer range 0 to Osc1_ik_max := 0;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset = '1' then
|
||||
cnt := 0;
|
||||
u_c1 <= (others => '0');
|
||||
else
|
||||
if u_c1 > X"AAAA" then flip1 <= '0'; end if;
|
||||
if u_c1 < X"5555" then flip1 <= '1'; end if;
|
||||
cnt := cnt + 1;
|
||||
if flip1 = '1' then
|
||||
if cnt = kc then
|
||||
cnt := 0;
|
||||
u_c1 <= u_c1 + (Osc1_iVFc - u_c1)/Osc1_div;
|
||||
end if;
|
||||
else
|
||||
if cnt = kd then
|
||||
cnt := 0;
|
||||
u_c1 <= u_c1 - (u_c1 - Osc1_iVFd)/Osc1_div;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Oscillateur2
|
||||
-- R1 = 510k, R2 = 510k, C=1.000e-6, SR=10MHz
|
||||
-- Charge : VF1 = 65535, k1 = 39844 (R1+R2, C)
|
||||
-- Decharge : VF2 = 2621, k2 = 19922 (R2, C)
|
||||
-- Div = 2^8
|
||||
|
||||
process (clk)
|
||||
variable cnt: integer range 0 to imax(Osc2_ikc,Osc2_ikd) := 0;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset = '1' then
|
||||
cnt := 0;
|
||||
u_c2 <= (others => '0');
|
||||
else
|
||||
if u_c2 > X"AAAA" then flip2 <= '0'; end if;
|
||||
if u_c2 < X"5555" then flip2 <= '1'; end if;
|
||||
cnt := cnt + 1;
|
||||
if flip2 = '1' then
|
||||
if cnt = Osc2_ikc then
|
||||
cnt := 0;
|
||||
u_c2 <= u_c2 + (Osc2_iVFc - u_c2)/Osc2_div;
|
||||
end if;
|
||||
else
|
||||
if cnt = Osc2_ikd then
|
||||
cnt := 0;
|
||||
u_c2 <= u_c2 - (u_c2 - Osc2_iVFd)/Osc2_div;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Filtre
|
||||
-- V1 = 5V
|
||||
-- R1 = 10k, R2 = 5.1k, R3 = 5.1k, R4 = 5k, R5 = 10k, C=100.0e-6, SR=10MHz
|
||||
-- Rp = R3//R4//R4//R1 = 1.68k
|
||||
-- Rs = 1/(1/R2 + 1/R3 - Rp/(R3*R3)) = 3.05k
|
||||
-- k = 11922 (Rs*C)
|
||||
-- Div = 2^8
|
||||
|
||||
-- VF00 = 13159 (V*Rp*Rs)/(R4*R3)
|
||||
-- VF01 = 19738 (V*Rp*Rs)/(R4p*R3)
|
||||
-- VF10 = 52377 (V*Rp*Rs)/(R4*R3) + V*Rs/R2
|
||||
-- VF11 = 58957 (V*Rp*Rs)/(R4p*R3) + V*Rs/R2
|
||||
|
||||
flips <= flip2 & flip1;
|
||||
|
||||
with flips select
|
||||
|
||||
vf <= to_unsigned(Filt2_iV0,16) when "00",
|
||||
to_unsigned(Filt2_iV1,16) when "01",
|
||||
to_unsigned(Filt2_iV2,16) when "10",
|
||||
to_unsigned(Filt2_iV3,16) when others;
|
||||
|
||||
process (clk)
|
||||
variable cnt: integer range 0 to Filt2_ik := 0;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset = '1' then
|
||||
cnt := 0;
|
||||
u_cf <= (others => '0');
|
||||
else
|
||||
cnt := cnt + 1;
|
||||
if vf > u_cf then
|
||||
if cnt = Filt2_ik then
|
||||
cnt := 0;
|
||||
u_cf <= u_cf + (vf - u_cf)/Filt2_div;
|
||||
end if;
|
||||
else
|
||||
if cnt = Filt2_ik then
|
||||
cnt := 0;
|
||||
u_cf <= u_cf - (u_cf - vf)/Filt2_div;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- U_CTRL
|
||||
|
||||
-- flip1 = 0 u_ctrl = 5V*Rp/R4 + u_cf*Rp/R3 # 22020 + u_cf*84/256
|
||||
-- flip1 = 1 u_ctrl = 5V*Rp/R4p + u_cf*Rp/R3 # 33063 + u_cf*84/256
|
||||
|
||||
u_cf_scaled <= u_cf*to_unsigned(C_flip1_scale,8);
|
||||
|
||||
with flip1 select
|
||||
u_ctrl <= to_unsigned(C_flip1_0,16)+u_cf_scaled(23 downto 8) when '0',
|
||||
to_unsigned(C_flip1_1,16)+u_cf_scaled(23 downto 8) when others;
|
||||
|
||||
-- Oscillateur3
|
||||
-- R1 = 20k, R2 = 20k, C=0.001e-6 SR=50MHz
|
||||
-- Charge : VF1 = 65535, k1 = 31 (R1+R2)
|
||||
-- Decharge : VF2 = 2621, k2 = 16 (R2)
|
||||
-- Div = 2^6
|
||||
|
||||
-- Diviseur
|
||||
-- LS163 : Count up, Sync load when 0xF (no toggle sound if divider = 0xF)
|
||||
-- LS74 : Divide by 2
|
||||
|
||||
process (clk)
|
||||
variable cnt: integer range 0 to imax(Osc3_ikc,Osc3_ikd) := 0;
|
||||
variable cnt2: unsigned(3 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset = '1' then
|
||||
cnt := 0;
|
||||
u_c3 <= (others => '0');
|
||||
flip3 <= '0';
|
||||
else
|
||||
if u_c3 > u_ctrl then flip3 <= '0'; end if;
|
||||
if u_c3 < u_ctrl/2 then
|
||||
flip3 <= '1';
|
||||
if flip3 = '0' then
|
||||
cnt2 := cnt2 + 1;
|
||||
if cnt2 = "0000" then
|
||||
cnt2 := unsigned(divider);
|
||||
if divider /= "1111" then sound <= not sound; end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
cnt := cnt + 1;
|
||||
if flip3 = '1' then
|
||||
if cnt = Osc3_ikc then
|
||||
cnt := 0;
|
||||
u_c3 <= u_c3 + (Osc3_iVFc - u_c3)/Osc3_div;
|
||||
end if;
|
||||
else
|
||||
if cnt = Osc3_ikd then
|
||||
cnt := 0;
|
||||
u_c3 <= u_c3 - (u_c3 - Osc3_iVFd)/Osc3_div;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
with trigger2 select snd <= '0'&sound when '1', sound&'0' when others;
|
||||
|
||||
end struct;
|
||||
@@ -0,0 +1,290 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Phoenix sound effect3 (noise) by Dar (darfpga@aol.fr) (April 2016)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
-- this module generates noisy sound of ship missile shooting
|
||||
-- ship explosions and enemy mothership explosion
|
||||
-- it is often head throught all the levels of the game
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity phoenix_effect3 is
|
||||
generic(
|
||||
-- Command 1
|
||||
Cmd1_Fs: real := 11.0; -- MHz
|
||||
Cmd1_V: real := 5.0; -- V
|
||||
Cmd1_Vd: real := 0.46; -- V
|
||||
Cmd1_Vce: real := 0.2; -- V
|
||||
Cmd1_R1: real := 1.0; -- k
|
||||
Cmd1_R2: real := 0.33; -- k
|
||||
Cmd1_R3: real := 20.0; -- k
|
||||
Cmd1_C: real := 6.8; -- uF
|
||||
Cmd1_Div2n: integer := 8; -- bits divisor
|
||||
--Cmd1_bits: integer := 16; -- bits counter
|
||||
-- Command 2
|
||||
Cmd2_Fs: real := 11.0; -- MHz
|
||||
Cmd2_V: real := 5.0; -- V
|
||||
Cmd2_Vd: real := 0.46; -- V
|
||||
Cmd2_Vce: real := 0.2; -- V
|
||||
Cmd2_R1: real := 1.0; -- k
|
||||
Cmd2_R2: real := 0.33; -- k
|
||||
Cmd2_R3: real := 47.0; -- k
|
||||
Cmd2_C: real := 6.8; -- uF
|
||||
Cmd2_Div2n: integer := 8; -- bits divisor
|
||||
--Cmd2_bits: integer := 16; -- bits counter
|
||||
-- Oscillator
|
||||
Osc_Fs: real := 11.0; -- MHz
|
||||
Osc_Vb: real := 5.0; -- V
|
||||
Osc_Vce: real := 0.2; -- V
|
||||
Oscmin_R1a: real := 47.0; -- k
|
||||
Oscmin_R2: real := 0.33; -- k
|
||||
Oscmin_C: real := 0.05; -- uF
|
||||
Oscmin_bits: integer := 16; -- bits counter
|
||||
Oscmax_R1a: real := 2.553; -- k
|
||||
Oscmax_R2: real := 1.0; -- k
|
||||
Oscmax_C: real := 0.05; -- uF
|
||||
Osc_Div2n: integer := 7; -- bits divisor
|
||||
--Osc_bits: integer := 16; -- bits counter
|
||||
|
||||
C_commande2_chop_k: integer := 62500;
|
||||
|
||||
Vmax: real := 5.0; -- V
|
||||
Vmax_bits: integer := 16 -- number of bits to represent Vmax
|
||||
);
|
||||
port(
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
trigger1 : in std_logic;
|
||||
trigger2 : in std_logic;
|
||||
snd : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end phoenix_effect3;
|
||||
|
||||
architecture struct of phoenix_effect3 is
|
||||
|
||||
-- integer representation of voltage, full range
|
||||
constant IVmax: integer := integer(2**Vmax_bits)-1;
|
||||
-- Command1 --
|
||||
constant Cmd1_div: integer := integer(2**Cmd1_Div2n);
|
||||
-- Command1 charge/discharge voltages
|
||||
constant Cmd1_VFc: real := Cmd1_V-Cmd1_Vd; -- V
|
||||
constant Cmd1_iVFc: integer := integer(Cmd1_VFc * real(IVmax)/Vmax);
|
||||
constant Cmd1_VFd: real := Cmd1_Vce+Cmd1_Vd; -- V
|
||||
constant Cmd1_iVFd: integer := integer(Cmd1_VFd * real(IVmax)/Vmax);
|
||||
-- Command1 charge/discharge time constants
|
||||
constant Cmd1_RCc: real := (Cmd1_R1+Cmd1_R2+Cmd1_R3)*Cmd1_C/1000.0; -- s
|
||||
constant Cmd1_ikc: integer := integer(Cmd1_Fs * 1.0E6 * Cmd1_RCc / 2.0**Cmd1_Div2n);
|
||||
constant Cmd1_RCd: real := Cmd1_R2*Cmd1_C/1000.0; -- s
|
||||
constant Cmd1_ikd: integer := integer(Cmd1_Fs * 1.0E6 * Cmd1_RCd / 2.0**Cmd1_Div2n);
|
||||
-- Command2 --
|
||||
constant Cmd2_div: integer := integer(2**Cmd2_Div2n);
|
||||
-- Command2 charge/discharge voltages
|
||||
constant Cmd2_VFc: real := (Cmd2_V-Cmd2_Vd)*Cmd2_R3/(Cmd2_R1+Cmd2_R2+Cmd2_R3); -- V
|
||||
constant Cmd2_iVFc: integer := integer(Cmd2_VFc * real(IVmax)/Vmax);
|
||||
constant Cmd2_VFd: real := 0.0; -- V
|
||||
constant Cmd2_iVFd: integer := integer(Cmd2_VFd * real(IVmax)/Vmax);
|
||||
-- Command2 charge/discharge time constants
|
||||
constant Cmd2_RCc: real := (Cmd2_R1+Cmd2_R2)*Cmd2_R3/(Cmd2_R1+Cmd2_R2+Cmd2_R3)*Cmd2_C/1000.0; -- s
|
||||
constant Cmd2_ikc: integer := integer(Cmd2_Fs * 1.0E6 * Cmd2_RCc / 2.0**Cmd2_Div2n);
|
||||
constant Cmd2_RCd: real := Cmd2_R3*Cmd2_C/1000.0; -- s
|
||||
constant Cmd2_ikd: integer := integer(Cmd2_Fs * 1.0E6 * Cmd2_RCd / 2.0**Cmd2_Div2n);
|
||||
-- Oscillator --
|
||||
constant Osc_div: integer := integer(2**Osc_Div2n);
|
||||
-- Oscillator charge/discharge voltages
|
||||
constant Osc_VFc: real := Osc_Vb; -- V
|
||||
constant Osc_iVFc: integer := integer(Osc_VFc * real(IVmax)/Vmax);
|
||||
constant Osc_VFd: real := Osc_Vce; -- V
|
||||
constant Osc_iVFd: integer := integer(Osc_VFd * real(IVmax)/Vmax);
|
||||
-- Oscillator min charge/discharge time constants
|
||||
constant Oscmin_RCc: real := (Oscmin_R1a+Oscmin_R2)*Oscmin_C/1000.0; -- s
|
||||
constant Oscmin_ikc: integer := integer(Osc_Fs * 1.0E6 * Oscmin_RCc / 2.0**Osc_Div2n);
|
||||
constant Oscmin_RCd: real := Oscmin_R2*Oscmin_C/1000.0; -- s
|
||||
constant Oscmin_ikd: integer := integer(Osc_Fs * 1.0E6 * Oscmin_RCd / 2.0**Osc_Div2n);
|
||||
-- Oscillator max charge/discharge time constants
|
||||
constant Oscmax_RCc: real := (Oscmax_R1a+Oscmax_R2)*Oscmax_C/1000.0; -- s
|
||||
constant Oscmax_ikc: integer := integer(Osc_Fs * 1.0E6 * Oscmax_RCc / 2.0**Osc_Div2n);
|
||||
constant Oscmax_RCd: real := Oscmax_R2*Oscmax_C/1000.0; -- s
|
||||
constant Oscmax_ikd: integer := integer(Osc_Fs * 1.0E6 * Oscmax_RCd / 2.0**Osc_Div2n);
|
||||
|
||||
function imax(x,y: integer) return integer is begin
|
||||
if x > y then
|
||||
return x;
|
||||
else
|
||||
return y;
|
||||
end if;
|
||||
end imax;
|
||||
|
||||
signal u_c1 : unsigned(15 downto 0) := (others => '0');
|
||||
signal u_c2 : unsigned(15 downto 0) := (others => '0');
|
||||
signal u_c3 : unsigned(15 downto 0) := (others => '0');
|
||||
signal flip3 : std_logic := '0';
|
||||
|
||||
signal k_ch : unsigned(25 downto 0) := (others =>'0');
|
||||
|
||||
signal u_ctrl1 : unsigned(15 downto 0) := (others => '0');
|
||||
signal u_ctrl2 : unsigned(15 downto 0) := (others => '0');
|
||||
signal u_ctrl1_f : unsigned( 7 downto 0) := (others => '0');
|
||||
signal u_ctrl2_f : unsigned( 7 downto 0) := (others => '0');
|
||||
signal sound : unsigned( 7 downto 0) := (others => '0');
|
||||
|
||||
signal shift_reg : std_logic_vector(17 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
-- Commande1
|
||||
-- R1 = 1k, R2 = 0.33k, R3 = 20k C=6.8e-6 SR=10MHz
|
||||
-- Charge : VF1 = 59507, k1 = 5666 (R1+R2+R3)
|
||||
-- Decharge : VF2 = 8651, k2 = 88 (R2)
|
||||
-- Div = 2^8
|
||||
|
||||
process (clk)
|
||||
-- variable cnt : unsigned(15 downto 0) := (others => '0');
|
||||
variable cnt: integer range 0 to imax(Cmd1_ikc,Cmd1_ikd)*2 := 0;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset = '1' then
|
||||
cnt := 0;
|
||||
u_c1 <= (others => '0');
|
||||
else
|
||||
cnt := cnt + 1;
|
||||
if trigger1 = '1' then
|
||||
-- if cnt > C_commande1_k1 then
|
||||
if cnt > Cmd1_ikc then
|
||||
cnt := 0;
|
||||
-- u_c1 <= u_c1 + (C_commande1_VF1 - u_c1)/256;
|
||||
u_c1 <= u_c1 + (Cmd1_iVFc - u_c1)/Cmd1_div;
|
||||
end if;
|
||||
else
|
||||
-- if cnt > C_commande1_k2 then
|
||||
if cnt > Cmd1_ikd then
|
||||
cnt := 0;
|
||||
-- u_c1 <= u_c1 - (u_c1 - C_commande1_VF2)/256;
|
||||
u_c1 <= u_c1 - (u_c1 - Cmd1_iVFd)/Cmd1_div;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Commande2
|
||||
-- R1 = 1k, R2 = 0.33k, R3 = 47k C=6.8e-6 SR=10MHz
|
||||
-- Charge : VF1 = 57869, k1 = 344 (R1+R2)//R3
|
||||
-- Decharge : VF2 = 0, k2 = 12484 (R3)
|
||||
-- Div = 2^8
|
||||
|
||||
process (clk)
|
||||
-- variable cnt : unsigned(15 downto 0) := (others => '0');
|
||||
variable cnt: integer range 0 to imax(Cmd2_ikc,Cmd2_ikd)*2 := 0;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset = '1' then
|
||||
-- cnt := (others => '0');
|
||||
cnt := 0;
|
||||
u_c2 <= (others => '0');
|
||||
else
|
||||
cnt := cnt + 1;
|
||||
if trigger2 = '1' then
|
||||
-- if cnt > C_commande2_k1 then
|
||||
if cnt > Cmd2_ikc then
|
||||
-- cnt := (others => '0');
|
||||
cnt := 0;
|
||||
-- u_c2 <= u_c2 + (C_commande2_VF1 - u_c2)/256;
|
||||
u_c2 <= u_c2 + (Cmd2_iVFc - u_c2)/Cmd2_div;
|
||||
end if;
|
||||
else
|
||||
-- if cnt > C_commande2_k2 then
|
||||
if cnt > Cmd2_ikd then
|
||||
-- cnt := (others => '0');
|
||||
cnt := 0;
|
||||
-- u_c2 <= u_c2 - (u_c2 - C_commande2_VF2)/256;
|
||||
u_c2 <= u_c2 - (u_c2 - Cmd2_iVFd)/Cmd2_div;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- control voltage from command1 is R3 voltage (not u_c1 voltage)
|
||||
with trigger1 select
|
||||
-- u_ctrl1 <= (to_unsigned(C_commande1_VF1,16) - u_c1) when '1', (others=>'0') when others;
|
||||
u_ctrl1 <= (to_unsigned(Cmd1_iVFc,16) - u_c1) when '1', (others=>'0') when others;
|
||||
|
||||
-- control voltage from command2 is u_c2 voltage
|
||||
u_ctrl2 <= u_c2;
|
||||
|
||||
-- sum up and scaled both control voltages to vary R1 resistor of oscillator
|
||||
-- k_ch <= shift_right(((u_ctrl1/2 + u_ctrl2/2) * to_unsigned(C_oscillateur_min_k1-C_oscillateur_max_k1,10)),15) + C_oscillateur_max_k1;
|
||||
k_ch <= shift_right(((u_ctrl1/2 + u_ctrl2/2) * to_unsigned(Oscmin_ikc-Oscmax_ikc,10)),15) + Oscmax_ikc;
|
||||
|
||||
-- Oscillateur
|
||||
-- R1 = 47k..2.533k, R2 = 1k, C=0.05e-6, SR=50MHz
|
||||
-- Charge : VF1 = 65536, k_ch = 938..69 (R1+R2, C)
|
||||
-- Decharge : VF2 = 2621, k2 = 20 (R2, C)
|
||||
-- Div = 2^7
|
||||
|
||||
-- noise generator triggered by oscillator output
|
||||
|
||||
process (clk)
|
||||
variable cnt: integer range 0 to imax(imax(Oscmin_ikc,Oscmin_ikd), imax(Oscmax_ikc,Oscmax_ikd))+256 := 0;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset = '1' then
|
||||
cnt := 0;
|
||||
u_c3 <= (others => '0');
|
||||
else
|
||||
if u_c3 > X"AAAA" then flip3 <= '0'; end if;
|
||||
if u_c3 < X"5555" then
|
||||
flip3 <= '1';
|
||||
if flip3 = '0' then
|
||||
shift_reg <= shift_reg(16 downto 0) & not(shift_reg(17) xor shift_reg(16));
|
||||
end if;
|
||||
end if;
|
||||
cnt := cnt + 1;
|
||||
if flip3 = '1' then
|
||||
if cnt > k_ch then
|
||||
cnt := 0;
|
||||
u_c3 <= u_c3 + (Osc_iVFc - u_c3)/Osc_div;
|
||||
end if;
|
||||
else
|
||||
if cnt > Oscmax_ikd then
|
||||
cnt := 0;
|
||||
u_c3 <= u_c3 - (u_c3 - Osc_iVFd)/Osc_div;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- modulated (chop) command1 voltage with noise generator output
|
||||
with shift_reg(17) xor shift_reg(16) select
|
||||
u_ctrl1_f <= u_ctrl1(15 downto 8)/2 when '0', (others => '0') when others;
|
||||
|
||||
|
||||
-- modulated (chop) command2 voltage with noise generator output
|
||||
-- and add 400Hz filter (raw sub-sampling)
|
||||
-- f=10 MHz, k = 25000
|
||||
process (clk)
|
||||
variable cnt : unsigned(15 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
cnt := cnt + 1;
|
||||
if cnt > C_commande2_chop_k then
|
||||
cnt := (others => '0');
|
||||
if (shift_reg(17) xor shift_reg(16)) = '0' then
|
||||
u_ctrl2_f <= u_ctrl2(15 downto 8)/2;
|
||||
else
|
||||
u_ctrl2_f <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- mix modulated noises 1 and 2
|
||||
sound <= u_ctrl1_f + u_ctrl2_f;
|
||||
snd <= std_logic_vector(sound);
|
||||
|
||||
end struct;
|
||||
309
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/phoenix_mist.vhd
Normal file
309
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/phoenix_mist.vhd
Normal file
@@ -0,0 +1,309 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- DE2-35 Top level for Phoenix by Dar (darfpga@aol.fr) (April 2016)
|
||||
-- http://darfpga.blogspot.fr
|
||||
--
|
||||
-- Main features
|
||||
-- PS2 keyboard input
|
||||
-- wm8731 sound output
|
||||
-- NO board SRAM used
|
||||
--
|
||||
-- sw 0: on/off hdmi-audio
|
||||
--
|
||||
-- Board switch : ---- todo fixme switches note
|
||||
-- 1 - 4 : dip switch
|
||||
-- 0-1 : lives 3-6
|
||||
-- 3-2 : bonus life 30K-60K
|
||||
-- 4 : coin 1-2
|
||||
-- 6-5 : unkonwn
|
||||
-- 7 : upright-cocktail
|
||||
-- 8 -10 : sound_select
|
||||
-- 0XX : all mixed (normal)
|
||||
-- 100 : sound1 only
|
||||
-- 101 : sound2 only
|
||||
-- 110 : sound3 only
|
||||
-- 111 : melody only
|
||||
-- Board key :
|
||||
-- 0 : reset
|
||||
--
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity phoenix_mist is
|
||||
port
|
||||
(
|
||||
CLOCK_27 : in std_logic;
|
||||
LED : out std_logic;
|
||||
VGA_R : out std_logic_vector(5 downto 0);
|
||||
VGA_G : out std_logic_vector(5 downto 0);
|
||||
VGA_B : out std_logic_vector(5 downto 0);
|
||||
VGA_HS : out std_logic;
|
||||
VGA_VS : out std_logic;
|
||||
SPI_SCK : in std_logic;
|
||||
SPI_DI : in std_logic;
|
||||
SPI_DO : out std_logic;
|
||||
SPI_SS2 : in std_logic;
|
||||
SPI_SS3 : in std_logic;
|
||||
CONF_DATA0 : in std_logic;
|
||||
AUDIO_L : out std_logic;
|
||||
AUDIO_R : out std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
architecture struct of phoenix_mist is
|
||||
|
||||
signal clk : std_logic;
|
||||
signal clk_88m : std_logic;
|
||||
signal reset : std_logic;
|
||||
signal clock_stable : std_logic;
|
||||
|
||||
signal audio : std_logic_vector(11 downto 0);
|
||||
signal video_r, video_g, video_b: std_logic_vector(1 downto 0);
|
||||
signal vsync, hsync : std_logic;
|
||||
|
||||
signal dip_switch : std_logic_vector(7 downto 0);-- := (others => '0');
|
||||
signal status : std_logic_vector(31 downto 0);
|
||||
signal buttons : std_logic_vector(1 downto 0);
|
||||
signal scandoubler_disable : std_logic;
|
||||
signal ypbpr : std_logic;
|
||||
signal ce_pix : std_logic;
|
||||
|
||||
signal scanlines : std_logic_vector(1 downto 0);
|
||||
signal hq2x : std_logic;
|
||||
|
||||
signal coin : std_logic;
|
||||
signal player_start : std_logic_vector(1 downto 0);
|
||||
signal button_left, button_right, button_protect, button_fire: std_logic;
|
||||
signal joy0 : std_logic_vector(7 downto 0);
|
||||
signal joy1 : std_logic_vector(7 downto 0);
|
||||
signal ps2Clk : std_logic;
|
||||
signal ps2Data : std_logic;
|
||||
signal kbd_joy : std_logic_vector(7 downto 0);
|
||||
signal upjoyL : std_logic;
|
||||
signal upjoyR : std_logic;
|
||||
signal upjoyB : std_logic;
|
||||
-- config string used by the io controller to fill the OSD
|
||||
constant CONF_STR : string := "PHOENIX;;O4,Screen Direction,Upright,Normal;O67,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;T5,Reset;V,v1.1;";
|
||||
|
||||
function to_slv(s: string) return std_logic_vector is
|
||||
constant ss: string(1 to s'length) := s;
|
||||
variable rval: std_logic_vector(1 to 8 * s'length);
|
||||
variable p: integer;
|
||||
variable c: integer;
|
||||
begin
|
||||
for i in ss'range loop
|
||||
p := 8 * i;
|
||||
c := character'pos(ss(i));
|
||||
rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8));
|
||||
end loop;
|
||||
return rval;
|
||||
end function;
|
||||
|
||||
component mist_io
|
||||
generic ( STRLEN : integer := 0 );
|
||||
port (
|
||||
clk_sys :in std_logic;
|
||||
SPI_SCK, CONF_DATA0, SPI_DI :in std_logic;
|
||||
SPI_DO : out std_logic;
|
||||
conf_str : in std_logic_vector(8*STRLEN-1 downto 0);
|
||||
buttons : out std_logic_vector(1 downto 0);
|
||||
joystick_0 : out std_logic_vector(7 downto 0);
|
||||
joystick_1 : out std_logic_vector(7 downto 0);
|
||||
status : out std_logic_vector(31 downto 0);
|
||||
scandoubler_disable, ypbpr : out std_logic;
|
||||
ps2_kbd_clk : out std_logic;
|
||||
ps2_kbd_data : out std_logic
|
||||
);
|
||||
end component mist_io;
|
||||
|
||||
component video_mixer
|
||||
generic ( LINE_LENGTH : integer := 352; HALF_DEPTH : integer := 1 );
|
||||
port (
|
||||
clk_sys, ce_pix, ce_pix_actual : in std_logic;
|
||||
SPI_SCK, SPI_SS3, SPI_DI : in std_logic;
|
||||
scanlines : in std_logic_vector(1 downto 0);
|
||||
scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic;
|
||||
rotate : in std_logic_vector(1 downto 0);
|
||||
R, G, B : in std_logic_vector(2 downto 0);
|
||||
HSync, VSync, line_start, mono : in std_logic;
|
||||
|
||||
VGA_R,VGA_G, VGA_B : out std_logic_vector(5 downto 0);
|
||||
VGA_VS, VGA_HS : out std_logic
|
||||
);
|
||||
end component video_mixer;
|
||||
|
||||
component keyboard
|
||||
PORT(
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
ps2_kbd_clk : in std_logic;
|
||||
ps2_kbd_data : in std_logic;
|
||||
joystick : out std_logic_vector (7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- SWITCH 1: SWITCH 2: NUMBER OF SPACESHIPS:
|
||||
-- --------- --------- ---------------------
|
||||
-- OFF OFF 6
|
||||
-- ON OFF 5
|
||||
-- OFF ON 4
|
||||
-- ON ON 3
|
||||
-- FIRST FREE SECOND FREE
|
||||
-- SWITCH 3: SWITCH 4: SHIP SCORE: SHIP SCORE:
|
||||
-- --------- --------- ----------- -----------
|
||||
-- OFF OFF 6,000 60,000
|
||||
-- ON OFF 5,000 50,000
|
||||
-- OFF ON 4,000 40,000
|
||||
-- ON ON 3,000 30,000
|
||||
|
||||
--Cocktail,Factory,Factory,Factory,Bonus2,Bonus1,Ships2,Ships1
|
||||
dip_switch <= "00001111";
|
||||
|
||||
mist_io_inst : mist_io
|
||||
generic map (STRLEN => CONF_STR'length)
|
||||
port map (
|
||||
clk_sys => clk,
|
||||
SPI_SCK => SPI_SCK,
|
||||
CONF_DATA0 => CONF_DATA0,
|
||||
SPI_DI => SPI_DI,
|
||||
SPI_DO => SPI_DO,
|
||||
conf_str => to_slv(CONF_STR),
|
||||
buttons => buttons,
|
||||
scandoubler_disable => scandoubler_disable,
|
||||
ypbpr => ypbpr,
|
||||
joystick_1 => joy1,
|
||||
joystick_0 => joy0,
|
||||
status => status,
|
||||
ps2_kbd_clk => ps2Clk,
|
||||
ps2_kbd_data => ps2Data
|
||||
);
|
||||
|
||||
--
|
||||
-- Audio
|
||||
--
|
||||
u_dac1 : entity work.dac
|
||||
port map(
|
||||
clk_i => clk_88m,
|
||||
res_n_i => not reset,
|
||||
dac_i => audio,
|
||||
dac_o => AUDIO_L
|
||||
);
|
||||
|
||||
u_dac2 : entity work.dac
|
||||
port map(
|
||||
clk_i => clk_88m,
|
||||
res_n_i => not reset,
|
||||
dac_i => audio,
|
||||
dac_o => AUDIO_R
|
||||
);
|
||||
|
||||
|
||||
pll: entity work.pll27
|
||||
port map(
|
||||
inclk0 => CLOCK_27,
|
||||
c0 => clk_88m,
|
||||
c1 => clk,
|
||||
locked => clock_stable
|
||||
);
|
||||
|
||||
reset <= status(0) or status(5) or buttons(1) or not clock_stable;
|
||||
|
||||
u_keyboard : keyboard
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
ps2_kbd_clk => ps2Clk,
|
||||
ps2_kbd_data => ps2Data,
|
||||
joystick => kbd_joy
|
||||
);
|
||||
|
||||
process(clk_88m)
|
||||
variable cnt: integer range 0 to 6000000 := 0;
|
||||
begin
|
||||
if rising_edge(clk_88m) then
|
||||
if status(3 downto 1) /= "000" then
|
||||
cnt := 0;
|
||||
coin <= status(1);
|
||||
player_start <= status(3 downto 2);
|
||||
else
|
||||
if cnt < 6000000 then
|
||||
cnt := cnt + 1;
|
||||
else
|
||||
coin <= '0';
|
||||
player_start <= "00";
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
upjoyB <= joy0(2) or joy1(2) when status(4) = '0' else joy0(0) or joy1(0);
|
||||
upjoyL <= joy0(1) or joy1(1) or kbd_joy(6) when status(4) = '0' else joy0(2) or joy1(2) or kbd_joy(5);
|
||||
upjoyR <= joy0(0) or joy1(0) or kbd_joy(7) when status(4) = '0' else joy0(3) or joy1(3) or kbd_joy(4);
|
||||
|
||||
phoenix : entity work.phoenix
|
||||
port map
|
||||
(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
ce_pix => ce_pix,
|
||||
dip_switch => dip_switch,
|
||||
btn_coin => kbd_joy(3) or coin,--ESC
|
||||
btn_player_start(0) => kbd_joy(1) or player_start(0),--1
|
||||
btn_player_start(1) => kbd_joy(2) or player_start(1),--2
|
||||
btn_left => upjoyL,
|
||||
btn_right => upjoyR,
|
||||
btn_barrier => upjoyB or kbd_joy(2),--TAB
|
||||
btn_fire => joy0(4) or joy1(4) or kbd_joy(0),--space
|
||||
video_r => video_r,
|
||||
video_g => video_g,
|
||||
video_b => video_b,
|
||||
video_hs => hsync,
|
||||
video_vs => vsync,
|
||||
audio_select => "000",
|
||||
audio => audio
|
||||
);
|
||||
|
||||
scanlines(0) <= '1' when status(7 downto 6) = "10" else '0';
|
||||
scanlines(1) <= '1' when status(7 downto 6) = "11" else '0';
|
||||
hq2x <= '1' when status(7 downto 6) = "01" else '0';
|
||||
|
||||
vmixer : video_mixer
|
||||
port map (
|
||||
clk_sys => clk_88m,
|
||||
ce_pix => ce_pix,
|
||||
ce_pix_actual => ce_pix,
|
||||
|
||||
SPI_SCK => SPI_SCK,
|
||||
SPI_SS3 => SPI_SS3,
|
||||
SPI_DI => SPI_DI,
|
||||
rotate => '1' & not status(4),
|
||||
scanlines => scanlines,
|
||||
scandoubler_disable => scandoubler_disable,
|
||||
hq2x => hq2x,
|
||||
ypbpr => ypbpr,
|
||||
ypbpr_full => '1',
|
||||
|
||||
R => video_r & video_r(1),
|
||||
G => video_g & video_g(1),
|
||||
B => video_b & video_b(1),
|
||||
HSync => hsync,
|
||||
VSync => vsync,
|
||||
line_start => '0',
|
||||
mono => '0',
|
||||
|
||||
VGA_R => VGA_R,
|
||||
VGA_G => VGA_G,
|
||||
VGA_B => VGA_B,
|
||||
VGA_VS => VGA_VS,
|
||||
VGA_HS => VGA_HS
|
||||
);
|
||||
|
||||
LED <= '1';
|
||||
|
||||
end struct;
|
||||
241
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/phoenix_music.vhd
Normal file
241
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/phoenix_music.vhd
Normal file
@@ -0,0 +1,241 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Phoenix music by Dar (darfpga@aol.fr) (April 2016)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
entity phoenix_music is
|
||||
generic(
|
||||
C_clk_freq: real := 11.0 -- MHz
|
||||
);
|
||||
port(
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
trigger : in std_logic;
|
||||
sel_song : in std_logic;
|
||||
snd : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end phoenix_music;
|
||||
|
||||
architecture struct of phoenix_music is
|
||||
|
||||
constant C_voice_attack: integer := integer(230.0 * C_clk_freq); -- larger value is faster
|
||||
constant C_song0_tempo: integer := integer(2200.0 * C_clk_freq); -- larger value is faster
|
||||
constant C_song1_tempo: integer := integer(1700.0 * C_clk_freq); -- larger value is faster
|
||||
constant C_voice_down_rate: integer := integer(4000.0 / C_clk_freq); -- larger value is slower
|
||||
|
||||
type voice_array is array (0 to 94) of integer range 0 to 127;
|
||||
-- main voice1 (Jeux Interdits)
|
||||
constant voice1 : voice_array := (
|
||||
32,96,32,96,32,96,32,96,26,90,24,88,24,88,23,87,21,85,21,85,24,88,32,96,37,101,101,101,101,101,37,101,35,99,33,97,33,97,32,96,26,90,26,90,32,96,33,97,32,96,33,97,32,96,36,100,33,97,32,96,32,96,26,90,24,88,24,88,23,87,21,85,23,87,23,87,23,87,23,87,24,88,23,87,21,85,24,88,32,96,37,101,101,101,101);
|
||||
-- accompagnement voice1
|
||||
constant voice2 : voice_array := (
|
||||
5,69,69,69,69,69,16,80,80,80,80,80,8,72,8,72,8,72,16,80,80,80,80,80,5,69,5,8,16,21,5,69,69,69,69,69,17,81,81,81,81,81,10,74,74,74,74,74,16,80,80,80,80,80,16,80,80,80,80,80,8,72,72,72,72,72,5,69,69,69,69,69,7,71,71,71,71,71,17,81,81,81,8,72,5,69,16,80,8,72,5,69,69,69,69);
|
||||
|
||||
-- voice1, voice2 and voice3 value description
|
||||
-- bit3-bit0 : tone from 0(La/A) to 11(Sol/G#)
|
||||
-- bit5-bit4 : octave from 0(220Hz)to 2(880Hz)
|
||||
-- bit6 : 0 = strike (restart) the tone, 1 = don't strike (hold) the tone
|
||||
|
||||
type voice_array2 is array (0 to 45) of integer range 0 to 127;
|
||||
-- main voice3 (La lettre a Elise)
|
||||
constant voice3 : voice_array2 := (
|
||||
37,36,37,36,37,32,35,33,26,5,10,17,21,26,32,5,16,21,25,32,33,5,10,17,37,36,37,36,37,32,35,33,26,5,10,17,21,26,32,5,16,21,33,32,26,90);
|
||||
|
||||
type period_array is array (0 to 11) of integer range 0 to 65535;
|
||||
-- Octave 220Hz @ 10MHz
|
||||
constant tone_period : period_array := (
|
||||
45455, -- ton 0 La (A )
|
||||
42903, -- ton 1 La# (A#)
|
||||
40495, -- ton 2 Si (B )
|
||||
38223, -- ton 3 Do (C )
|
||||
36077, -- ton 4 Do# (C#)
|
||||
34052, -- ton 5 Re (D )
|
||||
32141, -- ton 6 Re# (D#)
|
||||
30337, -- ton 7 Mi (E )
|
||||
28635, -- ton 8 Fa (F )
|
||||
27027, -- ton 9 Fa# (F#)
|
||||
25511, -- ton 10 Sol (G )
|
||||
24079 -- ton 11 Sol# (G#)
|
||||
);
|
||||
|
||||
signal tempo_period : integer range 0 to C_song0_tempo := C_song1_tempo; --0.19s @ 100kHz
|
||||
|
||||
signal voice1_tone : integer range 0 to 65535 := 0;
|
||||
signal voice1_tone_div : integer range 0 to 65535 := 0;
|
||||
signal voice1_code : unsigned(6 downto 0) := "0000000";
|
||||
signal voice1_vol : unsigned(7 downto 0) := "00000000";
|
||||
signal voice1_snd : std_logic := '0';
|
||||
|
||||
signal voice2_tone : integer range 0 to 65535 := 0;
|
||||
signal voice2_tone_div : integer range 0 to 65535 := 0;
|
||||
signal voice2_code : unsigned(6 downto 0) := "0000000";
|
||||
signal voice2_vol : unsigned(7 downto 0) := "00000000";
|
||||
signal voice2_snd : std_logic := '0';
|
||||
|
||||
signal snd1 : unsigned(7 downto 0) := "00000000";
|
||||
signal snd2 : unsigned(7 downto 0) := "00000000";
|
||||
|
||||
signal trigger_r : std_logic := '0';
|
||||
signal max_step : integer range 0 to 94 := 94;
|
||||
signal sel_song_r: std_logic := '1';
|
||||
|
||||
begin
|
||||
|
||||
process (clk)
|
||||
variable cnt : integer range 0 to 127 := 0;
|
||||
variable step : integer range 0 to 94 := 94;
|
||||
variable tempo : integer range 0 to C_song0_tempo := 0;
|
||||
variable voice1_code_v : unsigned(6 downto 0) := "0000000";
|
||||
variable voice2_code_v : unsigned(6 downto 0) := "0000000";
|
||||
variable voice1_down_rate : integer range 0 to C_voice_down_rate := 0;
|
||||
variable voice2_down_rate : integer range 0 to C_voice_down_rate := 0;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
trigger_r <= trigger;
|
||||
|
||||
if reset = '1' then
|
||||
cnt := 0;
|
||||
step := 94;
|
||||
voice1_vol <= X"00";
|
||||
voice2_vol <= X"00";
|
||||
elsif trigger ='1' and trigger_r ='0' and step = 94 then -- restart music on edge trigger if not already playing
|
||||
cnt := 0;
|
||||
step := 0;
|
||||
voice1_vol <= X"00";
|
||||
voice2_vol <= X"00";
|
||||
sel_song_r <= sel_song;
|
||||
if sel_song = '1' then
|
||||
max_step <= 94;
|
||||
tempo_period <= C_song1_tempo;
|
||||
else
|
||||
max_step <= 46;
|
||||
tempo_period <= C_song0_tempo;
|
||||
end if;
|
||||
else
|
||||
cnt := cnt +1;
|
||||
if cnt >= 100 then
|
||||
cnt := 0;
|
||||
tempo := tempo +1;
|
||||
if tempo >= tempo_period then -- next beat
|
||||
tempo := 0;
|
||||
if step < max_step then -- if not end of music get next note
|
||||
if sel_song_r = '1' then
|
||||
voice1_code_v := to_unsigned(voice1(step),7);
|
||||
voice2_code_v := to_unsigned(voice2(step),7);
|
||||
else
|
||||
voice1_code_v := to_unsigned(voice3(step),7);
|
||||
voice2_code_v := to_unsigned(voice3(step),7);
|
||||
end if;
|
||||
voice1_code <= voice1_code_v;
|
||||
voice2_code <= voice2_code_v;
|
||||
step := step + 1;
|
||||
else -- if end cut-off volume
|
||||
voice1_vol <= X"00";
|
||||
voice2_vol <= X"00";
|
||||
step := 94;
|
||||
end if;
|
||||
end if;
|
||||
if (step < 94) then -- if not end of music
|
||||
-- manage voice1 volume
|
||||
-- ramp up fast to xF0 at begining of beat when new strike
|
||||
if (tempo < C_voice_attack) and (voice1_code_v(6)='0') then
|
||||
if voice1_vol < X"F0" then voice1_vol <= voice1_vol + X"01"; end if;
|
||||
voice1_down_rate := 0;
|
||||
-- ramp down slowly after a while, down to x80
|
||||
else
|
||||
if voice1_vol > X"80" then
|
||||
voice1_down_rate := voice1_down_rate+1;
|
||||
if voice1_down_rate >= C_voice_down_rate then
|
||||
voice1_down_rate := 0;
|
||||
voice1_vol <= voice1_vol - X"01";
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
-- manage voice2 volume
|
||||
if (tempo < C_voice_attack) and (voice2_code_v(6)='0') then
|
||||
if voice2_vol < X"F0" then voice2_vol <= voice2_vol + X"01"; end if;
|
||||
voice2_down_rate := 0;
|
||||
else
|
||||
if voice2_vol > X"80" then
|
||||
voice2_down_rate := voice2_down_rate+1;
|
||||
if voice2_down_rate >= C_voice_down_rate then
|
||||
voice2_down_rate := 0;
|
||||
voice2_vol <= voice2_vol - X"01";
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- get voice1 raw tone
|
||||
voice1_tone <= tone_period(to_integer(voice1_code(3 downto 0)));
|
||||
|
||||
-- get voice1 tone w.r.t octave
|
||||
with voice1_code(5 downto 4) select
|
||||
voice1_tone_div <= voice1_tone when "00",
|
||||
voice1_tone/2 when "01",
|
||||
voice1_tone/4 when others;
|
||||
|
||||
-- generate voice1 frequency
|
||||
voice1_frequency: process (clk)
|
||||
variable cnt : integer range 0 to 65535 := 0;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset = '1' then
|
||||
cnt := 0;
|
||||
else
|
||||
cnt := cnt+1;
|
||||
if cnt >= voice1_tone_div then
|
||||
cnt := 0;
|
||||
voice1_snd <= not voice1_snd;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- get voice2 raw tone
|
||||
voice2_tone <= tone_period(to_integer(voice2_code(3 downto 0)));
|
||||
|
||||
-- get voice2 tone w.r.t octave
|
||||
with voice2_code(5 downto 4) select
|
||||
voice2_tone_div <= voice2_tone when "00",
|
||||
voice2_tone/2 when "01",
|
||||
voice2_tone/4 when others;
|
||||
|
||||
-- generate voice2 frequency
|
||||
voice2_frequency: process (clk)
|
||||
variable cnt : integer range 0 to 65535 := 0;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset = '1' then
|
||||
cnt := 0;
|
||||
else
|
||||
cnt := cnt+1;
|
||||
if cnt >= voice2_tone_div then
|
||||
cnt := 0;
|
||||
voice2_snd <= not voice2_snd;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- modulate voice1 volume with voice1 frequency
|
||||
with voice1_snd select snd1 <= voice1_vol when '1', X"00" when others;
|
||||
|
||||
-- modulate voice2 volume with voice2 frequency
|
||||
with voice2_snd select snd2 <= voice2_vol when '1', X"00" when others;
|
||||
|
||||
-- mix voice1 and voice 2
|
||||
snd <= std_logic_vector(('0'&snd1(7 downto 1)) + ('0'&snd2(7 downto 1)));
|
||||
|
||||
end struct;
|
||||
|
||||
1046
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/phoenix_prog.vhd
Normal file
1046
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/phoenix_prog.vhd
Normal file
File diff suppressed because it is too large
Load Diff
160
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/phoenix_video.vhd
Normal file
160
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/phoenix_video.vhd
Normal file
@@ -0,0 +1,160 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Phoenix video generator by Dar (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity phoenix_video is
|
||||
port(
|
||||
clk11 : in std_logic;
|
||||
reset : in std_logic;
|
||||
ce_pix : out std_logic;
|
||||
hcnt : out std_logic_vector(9 downto 1);
|
||||
vcnt : out std_logic_vector(8 downto 1);
|
||||
sync_hs : out std_logic;
|
||||
sync_vs : out std_logic;
|
||||
adrsel : out std_logic;
|
||||
rdy : out std_logic;
|
||||
vblank : out std_logic;
|
||||
hblank_frgrd : out std_logic;
|
||||
hblank_bkgrd : out std_logic
|
||||
);
|
||||
end phoenix_video;
|
||||
|
||||
architecture struct of phoenix_video is
|
||||
signal hclk_i : std_logic := '0';
|
||||
signal hstb_i : std_logic := '0';
|
||||
signal hcnt_i : unsigned(9 downto 1) := (others=>'0');
|
||||
signal vcnt_i : unsigned(9 downto 1) := (others=>'0');
|
||||
signal vcnt2 : std_logic_vector(8 downto 1) := (others=>'0');
|
||||
signal vblank_n : std_logic := '0';
|
||||
|
||||
signal rdy1_i : std_logic;
|
||||
signal rdy2_i : std_logic;
|
||||
signal j1 : std_logic;
|
||||
signal k1 : std_logic;
|
||||
signal q1 : std_logic;
|
||||
signal j2 : std_logic;
|
||||
signal k2 : std_logic;
|
||||
signal q2 : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- horizontal counter clock (pixel clock)
|
||||
process(clk11) begin
|
||||
if falling_edge(clk11) then
|
||||
hclk_i <= not hclk_i;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- horizontal counter from 0x0A0 to 0x1FF : 352 pixels
|
||||
process(clk11) begin
|
||||
if rising_edge(clk11) then
|
||||
if hclk_i = '1' then
|
||||
if reset = '1' then
|
||||
hcnt_i <= (others=>'0');
|
||||
vcnt_i <= (others=>'0');
|
||||
else
|
||||
hcnt_i <= hcnt_i +1;
|
||||
if hcnt_i = 511 then
|
||||
hcnt_i <= to_unsigned(160,9);
|
||||
vcnt_i <= vcnt_i +1;
|
||||
if vcnt_i = 261 then
|
||||
vcnt_i <= to_unsigned(0,9);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- vertical counter clock (line clock) = hblank
|
||||
process(clk11) begin
|
||||
if rising_edge(clk11) then
|
||||
if hclk_i = '1' then
|
||||
if (hcnt_i(3) and hcnt_i(2) and hcnt_i(1)) = '1' then hstb_i <= not hcnt_i(9); end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- vertical blanking
|
||||
vblank_n <=
|
||||
not(vcnt2(8) and vcnt2(7))
|
||||
or
|
||||
( not
|
||||
( not (vcnt2(8) and vcnt2(7) and not vcnt2(6) and not vcnt2(5) and not vcnt2(4))
|
||||
and
|
||||
not (vcnt2(8) and vcnt2(7) and not vcnt2(6) and not vcnt2(5) and vcnt2(4))
|
||||
)
|
||||
);
|
||||
|
||||
-- ready signal for microprocessor
|
||||
rdy1_i <= not( not(hcnt_i(9)) and not hcnt_i(7) and hcnt_i(6) and not hcnt_i(5));
|
||||
rdy2_i <= not( not(hcnt_i(9)) and hcnt_i(7) and hcnt_i(6) and hcnt_i(5));
|
||||
|
||||
-- background horizontal blanking
|
||||
j1 <= hcnt_i(6) and hcnt_i(4);
|
||||
k1 <= hstb_i;
|
||||
|
||||
process(clk11) begin
|
||||
if rising_edge(clk11) then
|
||||
if hclk_i = '1' then
|
||||
if (j1 xor k1) = '1' then
|
||||
q1 <= j1;
|
||||
elsif j1 = '1' then
|
||||
q1 <= not q1;
|
||||
else
|
||||
q1 <= q1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
j2 <= not hcnt_i(6) and hcnt_i(5);
|
||||
k2 <= hcnt_i(8) and hcnt_i(7) and hcnt_i(6) and hcnt_i(4);
|
||||
|
||||
process(clk11) begin
|
||||
if rising_edge(clk11) then
|
||||
if hclk_i = '1' then
|
||||
if (j2 xor k2) = '1' then
|
||||
q2 <= j2;
|
||||
elsif j2 = '1' then
|
||||
q2 <= not q2;
|
||||
else
|
||||
q2 <= q2;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- output
|
||||
ce_pix <= hclk_i;
|
||||
hcnt <= std_logic_vector(hcnt_i);
|
||||
vcnt2 <= std_logic_vector(vcnt_i(8 downto 1)) when vcnt_i < 255 else "11111111";
|
||||
vcnt <= vcnt2;
|
||||
--sync <= not(sync1_i xor sync2_i) ; original syncs
|
||||
rdy <= not(vblank_n and (not (rdy1_i and rdy2_i and not hcnt_i(9))));
|
||||
adrsel <= vblank_n and hcnt_i(9);
|
||||
|
||||
vblank <= not vblank_n;
|
||||
hblank_frgrd <= hstb_i;
|
||||
hblank_bkgrd <= not(hcnt_i(9) and q1) and not(hcnt_i(9) and (q2));
|
||||
|
||||
process(clk11) begin
|
||||
if rising_edge(clk11) then
|
||||
if hclk_i = '1' then
|
||||
if hcnt_i = 191 then
|
||||
sync_hs <= '1';
|
||||
if vcnt_i = 230 then sync_vs <= '1'; end if;
|
||||
if vcnt_i = 237 then sync_vs <= '0'; end if;
|
||||
end if;
|
||||
if hcnt_i = 217 then sync_hs <= '0'; end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end struct;
|
||||
4
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/pll.qip
Normal file
4
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/pll.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
|
||||
419
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/pll.vhd
Normal file
419
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/pll.vhd
Normal file
@@ -0,0 +1,419 @@
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: pll.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2014 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY pll IS
|
||||
PORT
|
||||
(
|
||||
areset : IN STD_LOGIC := '0';
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
c2 : OUT STD_LOGIC
|
||||
);
|
||||
END pll;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF pll IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC ;
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altpll
|
||||
GENERIC (
|
||||
bandwidth_type : STRING;
|
||||
clk0_divide_by : NATURAL;
|
||||
clk0_duty_cycle : NATURAL;
|
||||
clk0_multiply_by : NATURAL;
|
||||
clk0_phase_shift : STRING;
|
||||
clk1_divide_by : NATURAL;
|
||||
clk1_duty_cycle : NATURAL;
|
||||
clk1_multiply_by : NATURAL;
|
||||
clk1_phase_shift : STRING;
|
||||
clk2_divide_by : NATURAL;
|
||||
clk2_duty_cycle : NATURAL;
|
||||
clk2_multiply_by : NATURAL;
|
||||
clk2_phase_shift : STRING;
|
||||
compensate_clock : STRING;
|
||||
inclk0_input_frequency : NATURAL;
|
||||
intended_device_family : STRING;
|
||||
lpm_hint : STRING;
|
||||
lpm_type : STRING;
|
||||
operation_mode : STRING;
|
||||
pll_type : STRING;
|
||||
port_activeclock : STRING;
|
||||
port_areset : STRING;
|
||||
port_clkbad0 : STRING;
|
||||
port_clkbad1 : STRING;
|
||||
port_clkloss : STRING;
|
||||
port_clkswitch : STRING;
|
||||
port_configupdate : STRING;
|
||||
port_fbin : STRING;
|
||||
port_inclk0 : STRING;
|
||||
port_inclk1 : STRING;
|
||||
port_locked : STRING;
|
||||
port_pfdena : STRING;
|
||||
port_phasecounterselect : STRING;
|
||||
port_phasedone : STRING;
|
||||
port_phasestep : STRING;
|
||||
port_phaseupdown : STRING;
|
||||
port_pllena : STRING;
|
||||
port_scanaclr : STRING;
|
||||
port_scanclk : STRING;
|
||||
port_scanclkena : STRING;
|
||||
port_scandata : STRING;
|
||||
port_scandataout : STRING;
|
||||
port_scandone : STRING;
|
||||
port_scanread : STRING;
|
||||
port_scanwrite : STRING;
|
||||
port_clk0 : STRING;
|
||||
port_clk1 : STRING;
|
||||
port_clk2 : STRING;
|
||||
port_clk3 : STRING;
|
||||
port_clk4 : STRING;
|
||||
port_clk5 : STRING;
|
||||
port_clkena0 : STRING;
|
||||
port_clkena1 : STRING;
|
||||
port_clkena2 : STRING;
|
||||
port_clkena3 : STRING;
|
||||
port_clkena4 : STRING;
|
||||
port_clkena5 : STRING;
|
||||
port_extclk0 : STRING;
|
||||
port_extclk1 : STRING;
|
||||
port_extclk2 : STRING;
|
||||
port_extclk3 : STRING;
|
||||
width_clock : NATURAL
|
||||
);
|
||||
PORT (
|
||||
areset : IN STD_LOGIC ;
|
||||
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire6_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
|
||||
sub_wire3 <= sub_wire0(2);
|
||||
sub_wire2 <= sub_wire0(0);
|
||||
sub_wire1 <= sub_wire0(1);
|
||||
c1 <= sub_wire1;
|
||||
c0 <= sub_wire2;
|
||||
c2 <= sub_wire3;
|
||||
sub_wire4 <= inclk0;
|
||||
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
|
||||
|
||||
altpll_component : altpll
|
||||
GENERIC MAP (
|
||||
bandwidth_type => "AUTO",
|
||||
clk0_divide_by => 27,
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 11,
|
||||
clk0_phase_shift => "0",
|
||||
clk1_divide_by => 55,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 57,
|
||||
clk1_phase_shift => "0",
|
||||
clk2_divide_by => 560,
|
||||
clk2_duty_cycle => 50,
|
||||
clk2_multiply_by => 57,
|
||||
clk2_phase_shift => "0",
|
||||
compensate_clock => "CLK0",
|
||||
inclk0_input_frequency => 37037,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_hint => "CBX_MODULE_PREFIX=pll",
|
||||
lpm_type => "altpll",
|
||||
operation_mode => "NORMAL",
|
||||
pll_type => "AUTO",
|
||||
port_activeclock => "PORT_UNUSED",
|
||||
port_areset => "PORT_USED",
|
||||
port_clkbad0 => "PORT_UNUSED",
|
||||
port_clkbad1 => "PORT_UNUSED",
|
||||
port_clkloss => "PORT_UNUSED",
|
||||
port_clkswitch => "PORT_UNUSED",
|
||||
port_configupdate => "PORT_UNUSED",
|
||||
port_fbin => "PORT_UNUSED",
|
||||
port_inclk0 => "PORT_USED",
|
||||
port_inclk1 => "PORT_UNUSED",
|
||||
port_locked => "PORT_UNUSED",
|
||||
port_pfdena => "PORT_UNUSED",
|
||||
port_phasecounterselect => "PORT_UNUSED",
|
||||
port_phasedone => "PORT_UNUSED",
|
||||
port_phasestep => "PORT_UNUSED",
|
||||
port_phaseupdown => "PORT_UNUSED",
|
||||
port_pllena => "PORT_UNUSED",
|
||||
port_scanaclr => "PORT_UNUSED",
|
||||
port_scanclk => "PORT_UNUSED",
|
||||
port_scanclkena => "PORT_UNUSED",
|
||||
port_scandata => "PORT_UNUSED",
|
||||
port_scandataout => "PORT_UNUSED",
|
||||
port_scandone => "PORT_UNUSED",
|
||||
port_scanread => "PORT_UNUSED",
|
||||
port_scanwrite => "PORT_UNUSED",
|
||||
port_clk0 => "PORT_USED",
|
||||
port_clk1 => "PORT_USED",
|
||||
port_clk2 => "PORT_USED",
|
||||
port_clk3 => "PORT_UNUSED",
|
||||
port_clk4 => "PORT_UNUSED",
|
||||
port_clk5 => "PORT_UNUSED",
|
||||
port_clkena0 => "PORT_UNUSED",
|
||||
port_clkena1 => "PORT_UNUSED",
|
||||
port_clkena2 => "PORT_UNUSED",
|
||||
port_clkena3 => "PORT_UNUSED",
|
||||
port_clkena4 => "PORT_UNUSED",
|
||||
port_clkena5 => "PORT_UNUSED",
|
||||
port_extclk0 => "PORT_UNUSED",
|
||||
port_extclk1 => "PORT_UNUSED",
|
||||
port_extclk2 => "PORT_UNUSED",
|
||||
port_extclk3 => "PORT_UNUSED",
|
||||
width_clock => 5
|
||||
)
|
||||
PORT MAP (
|
||||
areset => areset,
|
||||
inclk => sub_wire5,
|
||||
clk => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "55"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "560"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "11.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "27.981817"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "2.748214"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "22"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "57"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "57"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "11.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "2.75000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "11"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "55"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "57"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "560"
|
||||
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "57"
|
||||
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
293
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/ym2149.sv
Normal file
293
Arcade_MiST/Phoenix Hardware/Survival_MIST/rtl/ym2149.sv
Normal file
@@ -0,0 +1,293 @@
|
||||
module ym2149
|
||||
(
|
||||
input CLK, // Global clock
|
||||
input CE, // PSG Clock enable
|
||||
input RESET, // Chip RESET (set all Registers to '0', active hi)
|
||||
input BDIR, // Bus Direction (0 - read , 1 - write)
|
||||
input BC, // Bus control
|
||||
input [7:0] DI, // Data In
|
||||
output [7:0] DO, // Data Out
|
||||
output [7:0] CHANNEL_A, // PSG Output channel A
|
||||
output [7:0] CHANNEL_B, // PSG Output channel B
|
||||
output [7:0] CHANNEL_C, // PSG Output channel C
|
||||
|
||||
input SEL,
|
||||
input MODE,
|
||||
|
||||
input [7:0] IOA_in,
|
||||
output [7:0] IOA_out,
|
||||
|
||||
input [7:0] IOB_in,
|
||||
output [7:0] IOB_out
|
||||
);
|
||||
|
||||
assign IOA_out = ymreg[14];
|
||||
assign IOB_out = ymreg[15];
|
||||
|
||||
reg ena_div;
|
||||
reg ena_div_noise;
|
||||
reg [3:0] addr;
|
||||
reg [7:0] ymreg[16];
|
||||
reg env_ena;
|
||||
reg [4:0] env_vol;
|
||||
|
||||
wire [7:0] volTableAy[16] =
|
||||
'{8'h00, 8'h03, 8'h04, 8'h06,
|
||||
8'h0a, 8'h0f, 8'h15, 8'h22,
|
||||
8'h28, 8'h41, 8'h5b, 8'h72,
|
||||
8'h90, 8'hb5, 8'hd7, 8'hff
|
||||
};
|
||||
|
||||
wire [7:0] volTableYm[32] =
|
||||
'{8'h00, 8'h01, 8'h01, 8'h02,
|
||||
8'h02, 8'h03, 8'h03, 8'h04,
|
||||
8'h06, 8'h07, 8'h09, 8'h0a,
|
||||
8'h0c, 8'h0e, 8'h11, 8'h13,
|
||||
8'h17, 8'h1b, 8'h20, 8'h25,
|
||||
8'h2c, 8'h35, 8'h3e, 8'h47,
|
||||
8'h54, 8'h66, 8'h77, 8'h88,
|
||||
8'ha1, 8'hc0, 8'he0, 8'hff
|
||||
};
|
||||
|
||||
// Read from AY
|
||||
assign DO = dout;
|
||||
reg [7:0] dout;
|
||||
always_comb begin
|
||||
case(addr)
|
||||
0: dout = ymreg[0];
|
||||
1: dout = {4'b0000, ymreg[1][3:0]};
|
||||
2: dout = ymreg[2];
|
||||
3: dout = {4'b0000, ymreg[3][3:0]};
|
||||
4: dout = ymreg[4];
|
||||
5: dout = {4'b0000, ymreg[5][3:0]};
|
||||
6: dout = {3'b000, ymreg[6][4:0]};
|
||||
7: dout = ymreg[7];
|
||||
8: dout = {3'b000, ymreg[8][4:0]};
|
||||
9: dout = {3'b000, ymreg[9][4:0]};
|
||||
10: dout = {3'b000, ymreg[10][4:0]};
|
||||
11: dout = ymreg[11];
|
||||
12: dout = ymreg[12];
|
||||
13: dout = {4'b0000, ymreg[13][3:0]};
|
||||
14: dout = (ymreg[7][6] ? ymreg[14] : IOA_in);
|
||||
15: dout = (ymreg[7][7] ? ymreg[15] : IOB_in);
|
||||
endcase
|
||||
end
|
||||
|
||||
// p_divider
|
||||
always @(posedge CLK) begin
|
||||
reg [3:0] cnt_div;
|
||||
reg noise_div;
|
||||
|
||||
if(CE) begin
|
||||
ena_div <= 0;
|
||||
ena_div_noise <= 0;
|
||||
if(!cnt_div) begin
|
||||
cnt_div <= {SEL, 3'b111};
|
||||
ena_div <= 1;
|
||||
|
||||
noise_div <= (~noise_div);
|
||||
if (noise_div) ena_div_noise <= 1;
|
||||
end else begin
|
||||
cnt_div <= cnt_div - 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg [16:0] poly17;
|
||||
wire [4:0] noise_gen_comp = ymreg[6][4:0] ? ymreg[6][4:0] - 1'd1 : 5'd0;
|
||||
|
||||
// p_noise_gen
|
||||
always @(posedge CLK) begin
|
||||
reg [4:0] noise_gen_cnt;
|
||||
|
||||
if(CE) begin
|
||||
if (ena_div_noise) begin
|
||||
if (noise_gen_cnt >= noise_gen_comp) begin
|
||||
noise_gen_cnt <= 0;
|
||||
poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]};
|
||||
end else begin
|
||||
noise_gen_cnt <= noise_gen_cnt + 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [11:0] tone_gen_freq[1:3];
|
||||
assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]};
|
||||
assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]};
|
||||
assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]};
|
||||
|
||||
wire [11:0] tone_gen_comp[1:3];
|
||||
assign tone_gen_comp[1] = tone_gen_freq[1] ? tone_gen_freq[1] - 1'd1 : 12'd0;
|
||||
assign tone_gen_comp[2] = tone_gen_freq[2] ? tone_gen_freq[2] - 1'd1 : 12'd0;
|
||||
assign tone_gen_comp[3] = tone_gen_freq[3] ? tone_gen_freq[3] - 1'd1 : 12'd0;
|
||||
|
||||
reg [3:1] tone_gen_op;
|
||||
|
||||
//p_tone_gens
|
||||
always @(posedge CLK) begin
|
||||
integer i;
|
||||
reg [11:0] tone_gen_cnt[1:3];
|
||||
|
||||
if(CE) begin
|
||||
// looks like real chips count up - we need to get the Exact behaviour ..
|
||||
|
||||
for (i = 1; i <= 3; i = i + 1) begin
|
||||
if(ena_div) begin
|
||||
if (tone_gen_cnt[i] >= tone_gen_comp[i]) begin
|
||||
tone_gen_cnt[i] <= 0;
|
||||
tone_gen_op[i] <= (~tone_gen_op[i]);
|
||||
end else begin
|
||||
tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0;
|
||||
|
||||
//p_envelope_freq
|
||||
always @(posedge CLK) begin
|
||||
reg [15:0] env_gen_cnt;
|
||||
|
||||
if(CE) begin
|
||||
env_ena <= 0;
|
||||
if(ena_div) begin
|
||||
if (env_gen_cnt >= env_gen_comp) begin
|
||||
env_gen_cnt <= 0;
|
||||
env_ena <= 1;
|
||||
end else begin
|
||||
env_gen_cnt <= (env_gen_cnt + 1'd1);
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire is_bot = (env_vol == 5'b00000);
|
||||
wire is_bot_p1 = (env_vol == 5'b00001);
|
||||
wire is_top_m1 = (env_vol == 5'b11110);
|
||||
wire is_top = (env_vol == 5'b11111);
|
||||
|
||||
always @(posedge CLK) begin
|
||||
reg old_BDIR;
|
||||
reg env_reset;
|
||||
reg env_hold;
|
||||
reg env_inc;
|
||||
|
||||
// envelope shapes
|
||||
// C AtAlH
|
||||
// 0 0 x x \___
|
||||
//
|
||||
// 0 1 x x /___
|
||||
//
|
||||
// 1 0 0 0 \\\\
|
||||
//
|
||||
// 1 0 0 1 \___
|
||||
//
|
||||
// 1 0 1 0 \/\/
|
||||
// ___
|
||||
// 1 0 1 1 \
|
||||
//
|
||||
// 1 1 0 0 ////
|
||||
// ___
|
||||
// 1 1 0 1 /
|
||||
//
|
||||
// 1 1 1 0 /\/\
|
||||
//
|
||||
// 1 1 1 1 /___
|
||||
|
||||
if(RESET) begin
|
||||
ymreg[0] <= 0;
|
||||
ymreg[1] <= 0;
|
||||
ymreg[2] <= 0;
|
||||
ymreg[3] <= 0;
|
||||
ymreg[4] <= 0;
|
||||
ymreg[5] <= 0;
|
||||
ymreg[6] <= 0;
|
||||
ymreg[7] <= 255;
|
||||
ymreg[8] <= 0;
|
||||
ymreg[9] <= 0;
|
||||
ymreg[10] <= 0;
|
||||
ymreg[11] <= 0;
|
||||
ymreg[12] <= 0;
|
||||
ymreg[13] <= 0;
|
||||
ymreg[14] <= 0;
|
||||
ymreg[15] <= 0;
|
||||
addr <= 0;
|
||||
env_vol <= 0;
|
||||
end else begin
|
||||
old_BDIR <= BDIR;
|
||||
if(~old_BDIR & BDIR) begin
|
||||
if(BC) addr <= DI[3:0];
|
||||
else begin
|
||||
ymreg[addr] <= DI;
|
||||
env_reset <= (addr == 13);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if(CE) begin
|
||||
if(env_reset) begin
|
||||
env_reset <= 0;
|
||||
// load initial state
|
||||
if(!ymreg[13][2]) begin // attack
|
||||
env_vol <= 5'b11111;
|
||||
env_inc <= 0; // -1
|
||||
end else begin
|
||||
env_vol <= 5'b00000;
|
||||
env_inc <= 1; // +1
|
||||
end
|
||||
env_hold <= 0;
|
||||
end else begin
|
||||
|
||||
if (env_ena) begin
|
||||
if (!env_hold) begin
|
||||
if (env_inc) env_vol <= (env_vol + 5'b00001);
|
||||
else env_vol <= (env_vol + 5'b11111);
|
||||
end
|
||||
|
||||
// envelope shape control.
|
||||
if(!ymreg[13][3]) begin
|
||||
if(!env_inc) begin // down
|
||||
if(is_bot_p1) env_hold <= 1;
|
||||
end else if (is_top) env_hold <= 1;
|
||||
end else if(ymreg[13][0]) begin // hold = 1
|
||||
if(!env_inc) begin // down
|
||||
if(ymreg[13][1]) begin // alt
|
||||
if(is_bot) env_hold <= 1;
|
||||
end else if(is_bot_p1) env_hold <= 1;
|
||||
end else if(ymreg[13][1]) begin // alt
|
||||
if(is_top) env_hold <= 1;
|
||||
end else if(is_top_m1) env_hold <= 1;
|
||||
end else if(ymreg[13][1]) begin // alternate
|
||||
if(env_inc == 1'b0) begin // down
|
||||
if(is_bot_p1) env_hold <= 1;
|
||||
if(is_bot) begin
|
||||
env_hold <= 0;
|
||||
env_inc <= 1;
|
||||
end
|
||||
end else begin
|
||||
if(is_top_m1) env_hold <= 1;
|
||||
if(is_top) begin
|
||||
env_hold <= 0;
|
||||
env_inc <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [4:0] A = ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | poly17[0])) ? 5'd0 : ymreg[8][4] ? env_vol[4:0] : { ymreg[8][3:0], ymreg[8][3]};
|
||||
wire [4:0] B = ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | poly17[0])) ? 5'd0 : ymreg[9][4] ? env_vol[4:0] : { ymreg[9][3:0], ymreg[9][3]};
|
||||
wire [4:0] C = ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | poly17[0])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]};
|
||||
|
||||
assign CHANNEL_A = MODE ? volTableAy[A[4:1]] : volTableYm[A];
|
||||
assign CHANNEL_B = MODE ? volTableAy[B[4:1]] : volTableYm[B];
|
||||
assign CHANNEL_C = MODE ? volTableAy[C[4:1]] : volTableYm[C];
|
||||
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user