diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/gen/psurge.zip b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/gen/psurge.zip deleted file mode 100644 index a428e0ea..00000000 Binary files a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/gen/psurge.zip and /dev/null differ diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/README.txt b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/README.txt similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/README.txt rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/README.txt diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/clean.bat b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/clean.bat similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/clean.bat rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/clean.bat diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.qpf b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/pooyan_mist.qpf similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.qpf rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/pooyan_mist.qpf diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.qsf b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/pooyan_mist.qsf similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.qsf rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/pooyan_mist.qsf diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.sdc b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/pooyan_mist.sdc similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.sdc rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/pooyan_mist.sdc diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/build_id.tcl b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/build_id.tcl similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/build_id.tcl rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/build_id.tcl diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/gen_ram.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/gen_ram.vhd rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/gen_ram.vhd diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/gen_video.vhd b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/gen_video.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/gen_video.vhd rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/gen_video.vhd diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pll.qip b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/pll.qip similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pll.qip rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/pll.qip diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pll.v b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/pll.v similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pll.v rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/pll.v diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan.vhd b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/pooyan.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan.vhd rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/pooyan.vhd diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan_mist.sv b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/pooyan_mist.sv similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan_mist.sv rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/pooyan_mist.sv diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan_sound_board.vhd b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/pooyan_sound_board.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan_sound_board.vhd rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/pooyan_sound_board.vhd diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_char_color_lut.vhd b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_char_color_lut.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_char_color_lut.vhd rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_char_color_lut.vhd diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_char_grphx1.vhd b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_char_grphx1.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_char_grphx1.vhd rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_char_grphx1.vhd diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_char_grphx2.vhd b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_char_grphx2.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_char_grphx2.vhd rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_char_grphx2.vhd diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_palette.vhd b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_palette.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_palette.vhd rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_palette.vhd diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_sound_prog.vhd b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_sound_prog.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_sound_prog.vhd rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_sound_prog.vhd diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_sprite_color_lut.vhd b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_sprite_color_lut.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_sprite_color_lut.vhd rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_sprite_color_lut.vhd diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_sprite_grphx1.vhd b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_sprite_grphx1.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_sprite_grphx1.vhd rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_sprite_grphx1.vhd diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_sprite_grphx2.vhd b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_sprite_grphx2.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/rom/pooyan_sprite_grphx2.vhd rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/rom/pooyan_sprite_grphx2.vhd diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/sdram.sv b/Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/sdram.sv similarity index 100% rename from Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/sdram.sv rename to Arcade_MiST/Konami Pooyan/Pooyan_MiST/rtl/sdram.sv diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.qpf b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/Power_Surge.qpf similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.qpf rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/Power_Surge.qpf diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.qsf b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/Power_Surge.qsf similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.qsf rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/Power_Surge.qsf diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.sdc b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/Power_Surge.sdc similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.sdc rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/Power_Surge.sdc diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/README.txt b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/README.txt similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/README.txt rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/README.txt diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/clean.bat b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/clean.bat similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/clean.bat rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/clean.bat diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/Power_Surge_MiST.sv b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/Power_Surge_MiST.sv similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/Power_Surge_MiST.sv rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/Power_Surge_MiST.sv diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/build_id.tcl b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/build_id.tcl similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/build_id.tcl rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/build_id.tcl diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/gen_ram.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/gen_ram.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/gen_ram.vhd diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/gen_video.vhd b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/gen_video.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/gen_video.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/gen_video.vhd diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/pll.v b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/pll.v similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/pll.v rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/pll.v diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/power_surge.vhd b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/power_surge.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/power_surge.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/power_surge.vhd diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/gen/make_power_surge_proms.bat b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/gen/make_power_surge_proms.bat similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/gen/make_power_surge_proms.bat rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/gen/make_power_surge_proms.bat diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/gen/make_vhdl_prom.exe b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/gen/make_vhdl_prom.exe similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/gen/make_vhdl_prom.exe rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/gen/make_vhdl_prom.exe diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_char_color_lut.vhd b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_char_color_lut.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_char_color_lut.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_char_color_lut.vhd diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_char_grphx.vhd b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_char_grphx.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_char_grphx.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_char_grphx.vhd diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_palette_blue_green.vhd b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_palette_blue_green.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_palette_blue_green.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_palette_blue_green.vhd diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_palette_green_red.vhd b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_palette_green_red.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_palette_green_red.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_palette_green_red.vhd diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_prog.vhd b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_prog.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_prog.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_prog.vhd diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_sound_prog.vhd b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_sound_prog.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_sound_prog.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_sound_prog.vhd diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_sprite_color_lut.vhd b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_sprite_color_lut.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_sprite_color_lut.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_sprite_color_lut.vhd diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_sprite_grphx.vhd b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_sprite_grphx.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/rom/power_surge_sprite_grphx.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_sprite_grphx.vhd diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/sdram.sv b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/sdram.sv similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/sdram.sv rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/sdram.sv diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_sound_board.vhd b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/time_pilot_sound_board.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_sound_board.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/time_pilot_sound_board.vhd diff --git a/Arcade_MiST/Konami Classic/ReadMe.txt b/Arcade_MiST/Konami Timepilot Hardware/ReadMe.txt similarity index 100% rename from Arcade_MiST/Konami Classic/ReadMe.txt rename to Arcade_MiST/Konami Timepilot Hardware/ReadMe.txt diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/README.txt b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/README.txt similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/README.txt rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/README.txt diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/clean.bat b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/clean.bat similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/clean.bat rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/clean.bat diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/TimePilot_MiST.sv b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/TimePilot_MiST.sv similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/TimePilot_MiST.sv rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/TimePilot_MiST.sv diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/build_id.tcl b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/build_id.tcl similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/build_id.tcl rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/build_id.tcl diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/gen_ram.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/gen_ram.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/gen_ram.vhd diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/gen_video.vhd b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/gen_video.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/gen_video.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/gen_video.vhd diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.qip b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/pll.qip similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.qip rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/pll.qip diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.v b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/pll.v similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.v rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/pll.v diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/rom/time_pilot_char_color_lut.vhd b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_char_color_lut.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/rom/time_pilot_char_color_lut.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_char_color_lut.vhd diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/rom/time_pilot_char_grphx.vhd b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_char_grphx.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/rom/time_pilot_char_grphx.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_char_grphx.vhd diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/rom/time_pilot_palette_blue_green.vhd b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_palette_blue_green.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/rom/time_pilot_palette_blue_green.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_palette_blue_green.vhd diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/rom/time_pilot_palette_green_red.vhd b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_palette_green_red.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/rom/time_pilot_palette_green_red.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_palette_green_red.vhd diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/rom/time_pilot_sound_prog.vhd b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_sound_prog.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/rom/time_pilot_sound_prog.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_sound_prog.vhd diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/rom/time_pilot_sprite_color_lut.vhd b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_sprite_color_lut.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/rom/time_pilot_sprite_color_lut.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_sprite_color_lut.vhd diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/rom/time_pilot_sprite_grphx.vhd b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_sprite_grphx.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/rom/time_pilot_sprite_grphx.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_sprite_grphx.vhd diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/sdram.sv b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/sdram.sv similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/sdram.sv rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/sdram.sv diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot.vhd b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/time_pilot.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/time_pilot.vhd diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sound_board.vhd b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/time_pilot_sound_board.vhd similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sound_board.vhd rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/time_pilot_sound_board.vhd diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qpf b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/time_pilot_mist.qpf similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qpf rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/time_pilot_mist.qpf diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qsf b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/time_pilot_mist.qsf similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qsf rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/time_pilot_mist.qsf diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.sdc b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/time_pilot_mist.sdc similarity index 100% rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.sdc rename to Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/time_pilot_mist.sdc diff --git a/Console_MiST/ChannelF_MiST/ChannelF.qpf b/Console_MiST/ChannelF_MiST/ChannelF.qpf new file mode 100644 index 00000000..fff2f0ed --- /dev/null +++ b/Console_MiST/ChannelF_MiST/ChannelF.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 14:59:16 November 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "14:59:16 November 16, 2017" + +# Revisions + +PROJECT_REVISION = "ChannelF" \ No newline at end of file diff --git a/Console_MiST/ChannelF_MiST/ChannelF.qsf b/Console_MiST/ChannelF_MiST/ChannelF.qsf new file mode 100644 index 00000000..bc025bcd --- /dev/null +++ b/Console_MiST/ChannelF_MiST/ChannelF.qsf @@ -0,0 +1,159 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 19:28:53 March 07, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Centipede_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY CannelF_MiST +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ----------------------- +# start ENTITY(Centipede) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Centipede) +# --------------------- +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/cent.stp +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name SYSTEMVERILOG_FILE rtl/CannelF_MiST.sv +set_global_assignment -name VHDL_FILE rtl/channel_f.vhd +set_global_assignment -name VHDL_FILE rtl/f8_cpu.vhd +set_global_assignment -name VHDL_FILE rtl/f8_psu.vhd +set_global_assignment -name VHDL_FILE rtl/f8_pack.vhd +set_global_assignment -name VHDL_FILE rtl/base_pack.vhd +set_global_assignment -name VHDL_FILE rtl/rom_pack.vhd +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name QIP_FILE ../../common/mist/mist.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Console_MiST/ChannelF_MiST/ChannelF.sdc b/Console_MiST/ChannelF_MiST/ChannelF.sdc new file mode 100644 index 00000000..1d0f7c84 --- /dev/null +++ b/Console_MiST/ChannelF_MiST/ChannelF.sdc @@ -0,0 +1,127 @@ +## Generated SDC file "vectrex_MiST.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +## DATE "Sun Jun 24 12:53:00 2018" + +## +## DEVICE "EP3C25E144C8" +## + +# Clock constraints + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +# tsu/th constraints + +# tco constraints + +# tpd constraints + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +#************************************************************** +# Create Generated Clock +#************************************************************** + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[4]}] 1.000 [get_ports {AUDIO_L}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[4]}] 1.000 [get_ports {AUDIO_R}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] +set_clock_groups -asynchronous -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[4]}] + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/Console_MiST/ChannelF_MiST/clean.bat b/Console_MiST/ChannelF_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Console_MiST/ChannelF_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Console_MiST/ChannelF_MiST/rtl/base_pack.vhd b/Console_MiST/ChannelF_MiST/rtl/base_pack.vhd new file mode 100644 index 00000000..7eb371fd --- /dev/null +++ b/Console_MiST/ChannelF_MiST/rtl/base_pack.vhd @@ -0,0 +1,631 @@ +-------------------------------------------------------------------------------- +-- BASE +-- Definitions +-------------------------------------------------------------------------------- +-- DO 3/2009 +-------------------------------------------------------------------------------- +-- Base +-------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +PACKAGE base_pack IS + -------------------------------------- + SUBTYPE uv IS unsigned; + SUBTYPE sv IS signed; + + SUBTYPE uv1_0 IS unsigned(1 DOWNTO 0); + SUBTYPE uv0_1 IS unsigned(0 TO 1); + SUBTYPE uv3_0 IS unsigned(3 DOWNTO 0); + SUBTYPE uv0_3 IS unsigned(0 TO 3); + SUBTYPE uv7_0 IS unsigned(7 DOWNTO 0); + SUBTYPE uv0_7 IS unsigned(0 TO 7); + + SUBTYPE uv2 IS unsigned(1 DOWNTO 0); + SUBTYPE uv3 IS unsigned(2 DOWNTO 0); + SUBTYPE uv4 IS unsigned(3 DOWNTO 0); + SUBTYPE uv5 IS unsigned(4 DOWNTO 0); + SUBTYPE uv6 IS unsigned(5 DOWNTO 0); + SUBTYPE uv7 IS unsigned(6 DOWNTO 0); + SUBTYPE uv8 IS unsigned(7 DOWNTO 0); + SUBTYPE uv9 IS unsigned(8 DOWNTO 0); + SUBTYPE uv10 IS unsigned(9 DOWNTO 0); + SUBTYPE uv11 IS unsigned(10 DOWNTO 0); + SUBTYPE uv12 IS unsigned(11 DOWNTO 0); + SUBTYPE uv13 IS unsigned(12 DOWNTO 0); + SUBTYPE uv14 IS unsigned(13 DOWNTO 0); + SUBTYPE uv15 IS unsigned(14 DOWNTO 0); + SUBTYPE uv16 IS unsigned(15 DOWNTO 0); + SUBTYPE uv17 IS unsigned(16 DOWNTO 0); + SUBTYPE uv18 IS unsigned(17 DOWNTO 0); + SUBTYPE uv19 IS unsigned(18 DOWNTO 0); + SUBTYPE uv20 IS unsigned(19 DOWNTO 0); + SUBTYPE uv21 IS unsigned(20 DOWNTO 0); + SUBTYPE uv22 IS unsigned(21 DOWNTO 0); + SUBTYPE uv23 IS unsigned(22 DOWNTO 0); + SUBTYPE uv24 IS unsigned(23 DOWNTO 0); + SUBTYPE uv25 IS unsigned(24 DOWNTO 0); + SUBTYPE uv26 IS unsigned(25 DOWNTO 0); + SUBTYPE uv27 IS unsigned(26 DOWNTO 0); + SUBTYPE uv28 IS unsigned(27 DOWNTO 0); + SUBTYPE uv29 IS unsigned(28 DOWNTO 0); + SUBTYPE uv30 IS unsigned(29 DOWNTO 0); + SUBTYPE uv31 IS unsigned(30 DOWNTO 0); + SUBTYPE uv32 IS unsigned(31 DOWNTO 0); + SUBTYPE uv64 IS unsigned(63 DOWNTO 0); + SUBTYPE uv128 IS unsigned(127 DOWNTO 0); + + SUBTYPE sv2 IS signed(1 DOWNTO 0); + SUBTYPE sv4 IS signed(3 DOWNTO 0); + SUBTYPE sv8 IS signed(7 DOWNTO 0); + SUBTYPE sv16 IS signed(15 DOWNTO 0); + SUBTYPE sv32 IS signed(31 DOWNTO 0); + SUBTYPE sv64 IS signed(63 DOWNTO 0); + SUBTYPE sv128 IS signed(127 DOWNTO 0); + + TYPE arr_uv0_3 IS ARRAY(natural RANGE <>) OF uv0_3; + TYPE arr_uv0_7 IS ARRAY(natural RANGE <>) OF uv0_7; + + TYPE arr_uv4 IS ARRAY(natural RANGE <>) OF uv4; + TYPE arr_uv8 IS ARRAY(natural RANGE <>) OF uv8; + TYPE arr_uv16 IS ARRAY(natural RANGE <>) OF uv16; + TYPE arr_uv32 IS ARRAY(natural RANGE <>) OF uv32; + TYPE arr_uv64 IS ARRAY(natural RANGE <>) OF uv64; + + SUBTYPE uint1 IS natural RANGE 0 TO 1; + SUBTYPE uint2 IS natural RANGE 0 TO 3; + SUBTYPE uint3 IS natural RANGE 0 TO 7; + SUBTYPE uint4 IS natural RANGE 0 TO 15; + SUBTYPE uint5 IS natural RANGE 0 TO 31; + SUBTYPE uint6 IS natural RANGE 0 TO 63; + SUBTYPE uint7 IS natural RANGE 0 TO 127; + SUBTYPE uint8 IS natural RANGE 0 TO 255; + SUBTYPE uint9 IS natural RANGE 0 TO 511; + SUBTYPE uint10 IS natural RANGE 0 TO 1023; + SUBTYPE uint11 IS natural RANGE 0 TO 2047; + SUBTYPE uint12 IS natural RANGE 0 TO 4095; + SUBTYPE uint13 IS natural RANGE 0 TO 8191; + SUBTYPE uint14 IS natural RANGE 0 TO 16383; + SUBTYPE uint15 IS natural RANGE 0 TO 32767; + SUBTYPE uint16 IS natural RANGE 0 TO 65535; + SUBTYPE uint24 IS natural RANGE 0 TO 16777215; + + SUBTYPE int2 IS integer RANGE -2 TO 1; + SUBTYPE int3 IS integer RANGE -4 TO 3; + SUBTYPE int4 IS integer RANGE -8 TO 7; + SUBTYPE int5 IS integer RANGE -16 TO 15; + SUBTYPE int6 IS integer RANGE -32 TO 31; + SUBTYPE int7 IS integer RANGE -64 TO 63; + SUBTYPE int8 IS integer RANGE -128 TO 127; + SUBTYPE int9 IS integer RANGE -256 TO 255; + SUBTYPE int10 IS integer RANGE -512 TO 511; + SUBTYPE int11 IS integer RANGE -1024 TO 1023; + SUBTYPE int12 IS integer RANGE -2048 TO 2047; + SUBTYPE int13 IS integer RANGE -4096 TO 4095; + SUBTYPE int14 IS integer RANGE -8192 TO 8191; + SUBTYPE int15 IS integer RANGE -16384 TO 16383; + SUBTYPE int16 IS integer RANGE -32768 TO 32767; + SUBTYPE int17 IS integer RANGE -65536 TO 65535; + + + ------------------------------------------------------------- + FUNCTION v_or (CONSTANT v : unsigned) RETURN std_logic; + FUNCTION v_and (CONSTANT v : unsigned) RETURN std_logic; + FUNCTION vv (CONSTANT s : std_logic; + CONSTANT N : natural) RETURN unsigned; + + -------------------------------------- + FUNCTION to_std_logic (a : boolean) RETURN std_logic; + -------------------------------------- + FUNCTION mux ( + s : std_logic; + a : unsigned; + b : unsigned) RETURN unsigned; + -------------------------------------- + FUNCTION mux ( + s : boolean; + a : unsigned; + b : unsigned) RETURN unsigned; + -------------------------------------- + FUNCTION mux ( + s : std_logic; + a : std_logic; + b : std_logic) RETURN std_logic; + -------------------------------------- + FUNCTION mux ( + s : boolean; + a : std_logic; + b : std_logic) RETURN std_logic; + -------------------------------------- + FUNCTION mux ( + s : boolean; + a : boolean; + b : boolean) RETURN boolean; + -------------------------------------- + FUNCTION mux ( + s : boolean; + a : integer; + b : integer) RETURN integer; + -------------------------------------- + FUNCTION mux ( + s : std_logic; + a : character; + b : character) RETURN character; + -------------------------------------- + FUNCTION mux ( + s : boolean; + a : character; + b : character) RETURN character; + -------------------------------------- + FUNCTION sext ( + e : unsigned; + l : natural) RETURN unsigned; + -------------------------------------- + FUNCTION sext ( + e : std_logic; + l : natural) RETURN unsigned; + -------------------------------------- + FUNCTION uext ( + e : unsigned; + l : natural) RETURN unsigned; + -------------------------------------- + FUNCTION uext ( + e : std_logic; + l : natural) RETURN unsigned; + -------------------------------------- + PROCEDURE wure ( + SIGNAL clk : IN std_logic; + CONSTANT n : IN natural:=1); + -------------------------------------- + PROCEDURE wufe ( + SIGNAL clk : IN std_logic; + CONSTANT n : IN natural:=1); + -------------------------------------- + FUNCTION To_HString (v : unsigned) RETURN string; + FUNCTION To_String (v : unsigned) RETURN string; + -------------------------------------- + FUNCTION To_Upper (c : character) RETURN character; + FUNCTION To_Upper (s : string) RETURN string; + FUNCTION To_String (i : natural; b : integer) RETURN string; + FUNCTION To_Natural (s : string; b : integer) RETURN natural; + + FUNCTION ilog2 (CONSTANT v : natural) RETURN natural; + +END PACKAGE base_pack; + +-------------------------------------------------------------------------------- + +PACKAGE BODY base_pack IS + + ------------------------------------------------------------- + FUNCTION vv (CONSTANT s : std_logic; + CONSTANT N : natural) RETURN unsigned IS + VARIABLE v : unsigned(N-1 DOWNTO 0); + BEGIN + v:=(OTHERS => s); + RETURN v; + END FUNCTION vv; + + ------------------------------------------------------------- + -- Vector OR (reduce) + FUNCTION v_or (CONSTANT v : unsigned) RETURN std_logic IS + VARIABLE r : std_logic := '0'; + VARIABLE Z : unsigned(v'range) := (OTHERS =>'0'); + BEGIN +--pragma synthesis_off + IF 1=1 THEN + FOR I IN v'range LOOP + r:=r OR v(I); + END LOOP; + RETURN r; + ELSE +--pragma synthesis_on + IF v/=Z THEN + RETURN '1'; + ELSE + RETURN '0'; + END IF; +--pragma synthesis_off + END IF; +--pragma synthesis_on + END FUNCTION v_or; + + ------------------------------------------------------------- + -- Vector AND (reduce) + FUNCTION v_and (CONSTANT v : unsigned) RETURN std_logic IS + VARIABLE r : std_logic := '1'; + VARIABLE U : unsigned(v'range) := (OTHERS =>'1'); + BEGIN +--pragma synthesis_off + IF 1=1 THEN + FOR I IN v'range LOOP + r:=r AND v(I); + END LOOP; + RETURN r; + ELSE +--pragma synthesis_on + IF v/=U THEN + RETURN '0'; + ELSE + RETURN '1'; + END IF; +--pragma synthesis_off + END IF; +--pragma synthesis_on + END FUNCTION v_and; + + -------------------------------------- + FUNCTION to_std_logic (a : boolean) RETURN std_logic IS + BEGIN + IF a THEN RETURN '1'; + ELSE RETURN '0'; + END IF; + END FUNCTION to_std_logic; + + -------------------------------------- + -- Sélection/Multiplexage s=1:a, s=0:b + FUNCTION mux ( + s : std_logic; + a : unsigned; + b : unsigned) RETURN unsigned IS + VARIABLE x : unsigned(a'range) :=(OTHERS => 'X'); + BEGIN + ASSERT a'length=b'length + REPORT "mux(): Different lengths" SEVERITY failure; + IF s='1' THEN + RETURN a; + ELSIF s='0' THEN + RETURN b; + ELSE + RETURN x; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=true:a, s=false:b + FUNCTION mux ( + s : boolean; + a : unsigned; + b : unsigned) RETURN unsigned IS + BEGIN + ASSERT a'length=b'length + REPORT "mux(): Different lengths" SEVERITY failure; + IF s THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=1:a, s=0:b + FUNCTION mux ( + s : std_logic; + a : std_logic; + b : std_logic) + RETURN std_logic IS + BEGIN + RETURN (S AND A) OR (NOT S AND B); + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=true:a, s=false:b + FUNCTION mux ( + s : boolean; + a : std_logic; + b : std_logic) + RETURN std_logic IS + BEGIN + IF s THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=true:a, s=false:b + FUNCTION mux ( + s : boolean; + a : boolean; + b : boolean) + RETURN boolean IS + BEGIN + IF s THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=1:a, s=0:b + FUNCTION mux ( + s : boolean; + a : integer; + b : integer) + RETURN integer IS + BEGIN + IF s THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=true:a, s=false:b + FUNCTION mux ( + s : std_logic; + a : character; + b : character) + RETURN character IS + BEGIN + IF s='1' THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=true:a, s=false:b + FUNCTION mux ( + s : boolean; + a : character; + b : character) + RETURN character IS + BEGIN + IF s THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Étend un vecteur avec extension de signe + FUNCTION sext ( + e : unsigned; + l : natural) RETURN unsigned IS + VARIABLE t : unsigned(l-1 DOWNTO 0); + BEGIN + -- Vérifier numeric_std.resize ... + t:=(OTHERS => e(e'left)); + t(e'length-1 DOWNTO 0):=e; + RETURN t; + END FUNCTION sext; + + -------------------------------------- + -- Étend un vecteur avec extension de signe + FUNCTION sext ( + e : std_logic; + l : natural) RETURN unsigned IS + VARIABLE t : unsigned(l-1 DOWNTO 0); + BEGIN + -- Vérifier numeric_std.resize ... + t:=(OTHERS => e); + RETURN t; + END FUNCTION sext; + + -------------------------------------- + -- Étend un vecteur sans extension de signe + FUNCTION uext ( + e : unsigned; + l : natural) RETURN unsigned IS + VARIABLE t : unsigned(l-1 DOWNTO 0); + BEGIN + -- Vérifier numeric_std.resize ... + t:=(OTHERS => '0'); + t(e'length-1 DOWNTO 0):=e; + RETURN t; + END FUNCTION uext; + + -------------------------------------- + -- Étend un vecteur sans extension de signe + FUNCTION uext ( + e : std_logic; + l : natural) RETURN unsigned IS + VARIABLE t : unsigned(l-1 DOWNTO 0); + BEGIN + -- Vérifier numeric_std.resize ... + t:=(OTHERS => '0'); + t(0):=e; + RETURN t; + END FUNCTION uext; + + -------------------------------------- + -- Wait Until Rising Edge + PROCEDURE wure( + SIGNAL clk : IN std_logic; + CONSTANT n : IN natural:=1) IS + BEGIN + FOR i IN 1 TO n LOOP + WAIT UNTIL rising_edge(clk); + END LOOP; + END PROCEDURE wure; + + -------------------------------------- + -- Wait Until Rising Edge + PROCEDURE wufe( + SIGNAL clk : IN std_logic; + CONSTANT n : IN natural:=1) IS + BEGIN + FOR i IN 1 TO n LOOP + WAIT UNTIL falling_edge(clk); + END LOOP; + END PROCEDURE wufe; + + -------------------------------------- + CONSTANT HexString : string(1 TO 16):="0123456789ABCDEF"; + + -- Conversion unsigned -> Chaîne hexadécimale + FUNCTION To_HString(v : unsigned) RETURN string IS + VARIABLE r : string(1 TO ((v'length)+3)/4); + VARIABLE x : unsigned(1 TO v'length); + VARIABLE i,j : integer; + BEGIN + x:=v; + i:=1; + j:=1; + r:=(OTHERS =>' '); + WHILE i Chaîne binaire + FUNCTION To_String(v : unsigned) RETURN string IS + VARIABLE r : string(1 TO v'length); + VARIABLE x : unsigned(1 TO v'length); + BEGIN + x:=v; + FOR i IN 1 TO v'length LOOP + CASE x(i) IS + WHEN '0' => r(i):='0'; + WHEN '1' => r(i):='1'; + WHEN 'X' => r(i):='X'; + WHEN 'Z' => r(i):='Z'; + WHEN 'U' => r(i):='U'; + WHEN 'H' => r(i):='H'; + WHEN 'L' => r(i):='L'; + WHEN '-' => r(i):='-'; + WHEN 'W' => r(i):='W'; + END CASE; + -- r(i):=std_logic'image(x(i))(1); + END LOOP; + RETURN r; + END FUNCTION To_String; + + -------------------------------------- + -- Conversion majuscules caractère + FUNCTION To_Upper(c : character) RETURN character IS + VARIABLE r : character; + BEGIN + CASE c IS + WHEN 'a' => r := 'A'; + WHEN 'b' => r := 'B'; + WHEN 'c' => r := 'C'; + WHEN 'd' => r := 'D'; + WHEN 'e' => r := 'E'; + WHEN 'f' => r := 'F'; + WHEN 'g' => r := 'G'; + WHEN 'h' => r := 'H'; + WHEN 'i' => r := 'I'; + WHEN 'j' => r := 'J'; + WHEN 'k' => r := 'K'; + WHEN 'l' => r := 'L'; + WHEN 'm' => r := 'M'; + WHEN 'n' => r := 'N'; + WHEN 'o' => r := 'O'; + WHEN 'p' => r := 'P'; + WHEN 'q' => r := 'Q'; + WHEN 'r' => r := 'R'; + WHEN 's' => r := 'S'; + WHEN 't' => r := 'T'; + WHEN 'u' => r := 'U'; + WHEN 'v' => r := 'V'; + WHEN 'w' => r := 'W'; + WHEN 'x' => r := 'X'; + WHEN 'y' => r := 'Y'; + WHEN 'z' => r := 'Z'; + WHEN OTHERS => r := c; + END CASE; + RETURN r; + END To_Upper; + + -------------------------------------- + -- Conversion majuscules chaîne + FUNCTION To_Upper(s: string) RETURN string IS + VARIABLE r: string (s'range); + BEGIN + FOR i IN s'range LOOP + r(i):= to_upper(s(i)); + END LOOP; + RETURN r; + END To_Upper; + + -------------------------------------- + -- Conversion entier -> chaîne + FUNCTION To_String(i: natural; b: integer) RETURN string IS + VARIABLE r : string(1 TO 10); + VARIABLE j,k : natural; + VARIABLE t : character; + BEGIN + j:=i; + k:=10; + WHILE j>=b LOOP + r(k):=HexString(j MOD b); + j:=j/b; + k:=k-1; + END LOOP; + + RETURN r(k TO 10); + END FUNCTION To_String; + + -------------------------------------- + -- Conversion chaîne -> entier + FUNCTION To_Natural (s : string; b : integer) RETURN natural IS + VARIABLE v,r : natural; + BEGIN + r:=0; + FOR i IN s'range LOOP + CASE s(i) IS + WHEN '0' => v:=0; + WHEN '1' => v:=1; + WHEN '2' => v:=2; + WHEN '3' => v:=3; + WHEN '4' => v:=4; + WHEN '5' => v:=5; + WHEN '6' => v:=6; + WHEN '7' => v:=7; + WHEN '8' => v:=8; + WHEN '9' => v:=9; + WHEN 'a' | 'A' => v:=10; + WHEN 'b' | 'B' => v:=11; + WHEN 'c' | 'C' => v:=12; + WHEN 'd' | 'D' => v:=13; + WHEN 'e' | 'E' => v:=14; + WHEN 'f' | 'F' => v:=15; + WHEN OTHERS => + v:=1000; + END CASE; + ASSERT vr LOOP + n:=n+1; + r:=r*2; + END LOOP; + RETURN n; + END FUNCTION ilog2; + +END PACKAGE BODY base_pack; diff --git a/Console_MiST/ChannelF_MiST/rtl/build_id.tcl b/Console_MiST/ChannelF_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Console_MiST/ChannelF_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Console_MiST/ChannelF_MiST/rtl/channel_f.vhd b/Console_MiST/ChannelF_MiST/rtl/channel_f.vhd new file mode 100644 index 00000000..36be2294 --- /dev/null +++ b/Console_MiST/ChannelF_MiST/rtl/channel_f.vhd @@ -0,0 +1,439 @@ +-------------------------------------------------------------------------------- +-- Fairchild Channel F console +-------------------------------------------------------------------------------- +-- DO 8/2020 +-------------------------------------------------------------------------------- +-- With help from MAME F8 model + +-- 0000 : ROM : sl90025.rom ou sl31253.rom +-- 0400 : ROM : sl31254.rom +-- 0800+ : CART + +-- COLOR = P[126 + Y*128][2] & P[125 + Y*128][2] & P[X + Y*128][1:0] + +-- F3850 : PORT 0 : 7 : NC +-- 6 : OUT : ENABLE IN BTN +-- 5 : OUT : ARM WRT +-- 4 : NC +-- 3 : IN : "START" +-- 2 : IN : "HOLD" +-- 1 : IN : "MODE" +-- 0 : IN : "TIME" +-- PORT 1 : 7 : IN : "RIGHT G.DOWN" OUT : WRITE DATA1 +-- 6 : IN : "RIGHT G.UP OUT : WRITE DATA0 +-- 5 : IN : "RIGHT CW" OUT : +-- 4 : IN : "RIGHT CCW" OUT : +-- 3 : IN : "RIGHT UP" OUT : +-- 2 : IN : "RIGHT DOWN" OUT : +-- 1 : IN : "RIGHT LEFT" OUT : +-- 0 : IN : "RIGHT RIGHT" OUT : + +-- F3851 : PORT 4 : 7 : IN : "LEFT G.DOWN" OUT : +-- SL31253 6 : IN : "LEFT G.UP" OUT : HORIZ BUS 6 +-- 5 : IN : "LEFT CW" OUT : HORIZ BUS 5 +-- 4 : IN : "LEFT CCW" OUT : HORIZ BUS 4 +-- 3 : IN : "LEFT UP" OUT : HORIZ BUS 3 +-- 2 : IN : "LEFT DOWN" OUT : HORIZ BUS 2 +-- 1 : IN : "LEFT LEFT" OUT : HORIZ BUS 1 +-- 0 : IN : "LEFT RIGHT" OUT : HORIZ BUS 0 +-- PORT 5 : 7 : IN : OUT : TONE BN +-- 6 : IN : OUT : TONE AN +-- 5 : IN : OUT : VERT BUS 5 +-- 4 : IN : OUT : VERT BUS 4 +-- 3 : IN : OUT : VERT BUS 3 +-- 2 : IN : OUT : VERT BUS 2 +-- 1 : IN : OUT : VERT BUS 1 +-- 0 : IN : OUT : VERT BUS 0 +-- +-- F3851 : No IO +-- SL31254 + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.numeric_std.all; + +--USE std.textio.ALL; + +LIBRARY work; +USE work.base_pack.ALL; +USE work.rom_pack.ALL; + +ENTITY channel_f IS + PORT ( + clk : IN std_logic; + reset_na : IN std_logic; + -- VGA + vga_clk : OUT std_logic; + vga_ce : OUT std_logic; + vga_r : OUT std_logic_vector(7 DOWNTO 0); + vga_g : OUT std_logic_vector(7 DOWNTO 0); + vga_b : OUT std_logic_vector(7 DOWNTO 0); + vga_hs : OUT std_logic; -- positive pulse! + vga_vs : OUT std_logic; -- positive pulse! + vga_de : OUT std_logic; -- = not (VBlank or HBlank) + -- HPS IO + joystick_0 : IN unsigned(31 DOWNTO 0); + joystick_1 : IN unsigned(31 DOWNTO 0); + iTIME : IN std_logic; -- TIME + iMODE : IN std_logic; -- MODE + iHOLD : IN std_logic; -- HOLD + iSTART : IN std_logic; -- START + --ROM LOAD + rom_addr : IN std_logic_vector(10 DOWNTO 0); + rom_do : IN std_logic_vector(7 DOWNTO 0); + rom_wr : IN std_logic; + -- AUDIO + audio : OUT std_logic_vector(15 DOWNTO 0) + ); + +END channel_f; + +ARCHITECTURE struct OF channel_f IS + + SIGNAL ioctl_wait_l,ioctl_download2,ioctl_wr2 : std_logic; + SIGNAL adrs : uv17; + + ---------------------------------------------------------- + SIGNAL dr,dr0,dr1,dr2,dr3,dw_cpu : uv8; + SIGNAL dv0,dv1,dv2,dv3,dv_cpu : std_logic; + SIGNAL romc : uv5; + SIGNAL phase : uint4; + SIGNAL ce : std_logic :='0'; + + SIGNAL pi0,po0,pi1,po1,pi4,po4,pi5,po5 : uv8; + SIGNAL load_a : uv10; + SIGNAL load_d : uv8; + SIGNAL load_wr0,load_wr1 : std_logic; + SIGNAL tick : std_logic; +-- SIGNAL reset_na : std_logic; + + ---------------------------------------------------------- + CONSTANT INIT_ZERO : arr_uv8(0 TO 1023) := (OTHERS => x"00"); + + CONSTANT HDISP : natural :=208; + CONSTANT HSYNCSTART : natural :=212; + CONSTANT HSYNCEND : natural :=220; + CONSTANT HTOTAL : natural :=228; + + CONSTANT VDISP : natural :=232; + CONSTANT VSYNCSTART : natural :=242; + CONSTANT VSYNCEND : natural :=246; + CONSTANT VTOTAL : natural :=262; + + -- BLACK WHITE RED GREEN BLUE LTGRAY LTGREEN LTBLUE + CONSTANT PAL_R : arr_uv8(0 TO 7) := + (x"10",x"FD",x"FF",x"02",x"4B",x"E0",x"91",x"CE"); + CONSTANT PAL_G : arr_uv8(0 TO 7) := + (x"10",x"FD",x"31",x"CC",x"3F",x"E0",x"FF",x"D0"); + CONSTANT PAL_B : arr_uv8(0 TO 7) := + (x"10",x"FD",x"53",x"5D",x"F3",x"E0",x"A6",x"FF"); + + TYPE arr_uint3 IS ARRAY(natural RANGE <>) OF uint3; + CONSTANT CMAP : arr_uint3(0 TO 15) := + (0,1,1,1,7,4,2,3,5,4,2,3,6,4,2,3); + + TYPE arr_uv2 IS ARRAY(natural RANGE <>) OF uv2; + SIGNAL vram : arr_uv2(0 TO 128*64-1); -- Pixels + + SIGNAL vram_a : uint13; + SIGNAL vram_h : uint7; + SIGNAL vram_v : uint6; + SIGNAL vram_dw : uv2; + SIGNAL vram_wr : std_logic; + + SIGNAL v125 : std_logic_vector(0 TO 63); + SIGNAL v126 : std_logic_vector(0 TO 63); + + SIGNAL p125,p125p,p126,p126p : std_logic; + SIGNAL hpos,hposp : uint8; + SIGNAL vpos,vposp : uint9; + SIGNAL pos : uint13; + SIGNAL pix : uv2; + + SIGNAL vdiv : uv16; + SIGNAL tone : uv2; + +BEGIN + + ---------------------------------------------------------- + -- CPU + + -- CPUCLK = VIDEOCLK / 2 + ce <='1'; --NOT ce WHEN rising_edge(clk); + + i_cpu: ENTITY work.f8_cpu + PORT MAP ( + dr => dr, + dw => dw_cpu, + dv => dv_cpu, + romc => romc, + tick => tick, + phase => phase, + po_a => po0, + pi_a => pi0, + po_b => po1, + pi_b => pi1, + clk => clk, + ce => ce, + reset_na => reset_na + ); + + -- PSU SL31253 + i_psu0:ENTITY work.f8_psu + GENERIC MAP ( + PAGE => "000000", -- 0x0000 + IOPAGE => "000001", -- Not used + IVEC => x"FFFF", -- Not used + ROM => arr_uv8(INIT_SL31253)) + PORT MAP ( + dw => dr, + dr => dr0, + dv => dv0, + romc => romc, + tick => tick, + phase => phase, + ext_int => '0', + int_req => OPEN, + pri_o => OPEN, + pri_i => '1', + po_a => po4, + pi_a => pi4, + po_b => po5, + pi_b => pi5, + load_a => load_a, + load_d => load_d, + load_wr => '0', + clk => clk, + ce => ce, + reset_na => reset_na + ); + + -- PSU SL31254 + i_psu1:ENTITY work.f8_psu + GENERIC MAP ( + PAGE => "000001", -- 0x0400 + IOPAGE => "111111", -- Not used + IVEC => x"FFFF", -- Not used + ROM => arr_uv8(INIT_SL31254)) + PORT MAP ( + dw => dr, + dr => dr1, + dv => dv1, + romc => romc, + tick => tick, + phase => phase, + ext_int => '0', + int_req => OPEN, + pri_o => OPEN, + pri_i => '1', + po_a => OPEN, + pi_a => x"FF", + po_b => OPEN, + pi_b => x"FF", + load_a => load_a, + load_d => load_d, + load_wr => '0', + clk => clk, + ce => ce, + reset_na => reset_na + ); + + -- CARTRIDGE + i_psu2:ENTITY work.f8_psu + GENERIC MAP ( + PAGE => "000010", -- 0x0800 + IOPAGE => "111110", -- Not used + IVEC => x"FFFF", -- Not used + ROM => INIT_ZERO) + PORT MAP ( + dw => dr, + dr => dr2, + dv => dv2, + romc => romc, + tick => tick, + phase => phase, + ext_int => '0', + int_req => OPEN, + pri_o => OPEN, + pri_i => '1', + po_a => OPEN, + pi_a => x"FF", + po_b => OPEN, + pi_b => x"FF", + load_a => load_a, + load_d => load_d, + load_wr => load_wr0, + clk => clk, + ce => ce, + reset_na => reset_na + ); + + -- CARTRIDGE + i_psu3:ENTITY work.f8_psu + GENERIC MAP ( + PAGE => "000011", -- 0x0C00 + IOPAGE => "111101", -- Not used + IVEC => x"FFFF", -- Not used + ROM => INIT_ZERO) + PORT MAP ( + dw => dr, + dr => dr3, + dv => dv3, + romc => romc, + tick => tick, + phase => phase, + ext_int => '0', + int_req => OPEN, + pri_o => OPEN, + pri_i => '1', + po_a => OPEN, + pi_a => x"FF", + po_b => OPEN, + pi_b => x"FF", + load_a => load_a, + load_d => load_d, + load_wr => load_wr1, + clk => clk, + ce => ce, + reset_na => reset_na + ); + + dr <= dr0 WHEN dv0='1' ELSE + dr1 WHEN dv1='1' ELSE + dr2 WHEN dv2='1' ELSE + dr3 WHEN dv3='1' ELSE + dw_cpu; + + --------------------------------------------------------- + + -- CARTRIDGE LOAD + + PROCESS (clk) IS + BEGIN + IF rising_edge(clk) THEN + load_a <=unsigned(rom_addr(9 DOWNTO 0)); + load_wr0<=NOT rom_addr(10) AND rom_wr; + load_wr1<= rom_addr(10) AND rom_wr; + load_d <=unsigned(rom_do); + END IF; + END PROCESS; + + + -- VIDEO + vram_h <= to_integer(NOT po4(6 DOWNTO 0)); + vram_v <= to_integer(NOT po5(5 DOWNTO 0)); + vram_dw<= NOT po1(7 DOWNTO 6); + vram_wr<= po0(5); + + vram_a <= vram_h + vram_v * 128; + + PROCESS(clk) IS + BEGIN + IF rising_edge(clk) THEN + IF vram_wr='1' THEN + vram(vram_a)<=vram_dw; + END IF; + IF vram_wr='1' AND vram_h=125 THEN + v125(vram_v)<=vram_dw(1); + END IF; + IF vram_wr='1' AND vram_h=126 THEN + v126(vram_v)<=vram_dw(1); + END IF; + END IF; + END PROCESS; + + -- VIDEO SWEEP + PROCESS (clk) IS + BEGIN + IF rising_edge(clk) THEN + IF ce='1' THEN + hpos<=hpos+1; + IF hpos=HTOTAL-1 THEN + hpos<=0; + vpos<=vpos+1; + IF vpos=VTOTAL-1 THEN + vpos<=0; + END IF; + END IF; + + pos<=((vpos/4) MOD 64) * 128 + ((hpos/2) MOD 128); + vposp<=vpos; + hposp<=hpos; + + pix <=vram(pos); + p125<=v125((vposp/4) MOD 64); + p126<=v126((vposp/4) MOD 64); + + vga_r<=std_logic_vector(PAL_R(CMAP(to_integer(p125 & p126 & pix)))); + vga_g<=std_logic_vector(PAL_G(CMAP(to_integer(p125 & p126 & pix)))); + vga_b<=std_logic_vector(PAL_B(CMAP(to_integer(p125 & p126 & pix)))); + vga_de<=to_std_logic(vposp<=VDISP AND hposp=HSYNCSTART AND hposp<=HSYNCEND); + vga_vs<=to_std_logic(vposp>=VSYNCSTART AND vposp<=VSYNCEND); + END IF; + END IF; + END PROCESS; + + vga_clk<=clk; + vga_ce<=ce; + + -- 128 x 64 pixels => 102 x 58 visible => 95 x 58 visible + -- CPU : F video / 2 + -- 1.7897725MHz (NTSC) + -- 2.0000000MHz (PAL GEN 1) + -- 1.7734475MHz (PAL GEN 2) + + ---------------------------------------------------------- + -- Joysticks / Buttons + pi0(7 DOWNTO 4)<= "1111"; + pi0(0) <= NOT (joystick_0(4) OR joystick_1(4) OR iTIME); -- TIME + pi0(1) <= NOT (joystick_0(5) OR joystick_1(5) OR iMODE); -- MODE + pi0(2) <= NOT (joystick_0(6) OR joystick_1(6) OR iHOLD); -- HOLD + pi0(3) <= NOT (joystick_0(7) OR joystick_1(7) OR iSTART); -- START + + pi1(7) <= NOT joystick_0(8); -- RIGHT G.DOWN + pi1(6) <= NOT joystick_0(9); -- RIGHT G.UP + pi1(5) <= NOT joystick_0(10); -- RIGHT CW + pi1(4) <= NOT joystick_0(11); -- RIGHT CCW + pi1(3) <= NOT joystick_0(3); -- RIGHT UP + pi1(2) <= NOT joystick_0(2); -- RIGHT DOWN + pi1(1) <= NOT joystick_0(1); -- RIGHT LEFT + pi1(0) <= NOT joystick_0(0); -- RIGHT RIGHT + + pi4(7) <= NOT joystick_1(8); -- LEFT G.DOWN + pi4(6) <= NOT joystick_1(9); -- LEFT G.UP + pi4(5) <= NOT joystick_1(10); -- LEFT CW + pi4(4) <= NOT joystick_1(11); -- LEFT CCW + pi4(3) <= NOT joystick_1(3); -- LEFT UP + pi4(2) <= NOT joystick_1(2); -- LEFT DOWN + pi4(1) <= NOT joystick_1(1); -- LEFT LEFT + pi4(0) <= NOT joystick_1(0); -- LEFT RIGHT + + pi5<=x"FF"; + + ---------------------------------------------------------- + -- Audio + -- 00 : Silence + -- 01 : 1kHz + -- 10 : 500Hz + -- 11 : 120Hz + + tone <=po5(7 DOWNTO 6); + PROCESS (clk) IS + VARIABLE s_v : std_logic; + BEGIN + IF rising_edge(clk) THEN + vdiv<=vdiv + 1; + CASE tone IS + WHEN "00" => s_v:='0'; + WHEN "01" => s_v:=vdiv(10); + WHEN "10" => s_v:=vdiv(9); + WHEN OTHERS => s_v:=vdiv(7); + END CASE; + audio<=(OTHERS =>s_v); + END IF; + END PROCESS; + + +END struct; \ No newline at end of file diff --git a/Console_MiST/ChannelF_MiST/rtl/f8_cpu.vhd b/Console_MiST/ChannelF_MiST/rtl/f8_cpu.vhd new file mode 100644 index 00000000..c0525af7 --- /dev/null +++ b/Console_MiST/ChannelF_MiST/rtl/f8_cpu.vhd @@ -0,0 +1,250 @@ +-------------------------------------------------------------------------------- +-- Fairchild F8 F3850 CPU +-------------------------------------------------------------------------------- +-- DO 8/2020 +-------------------------------------------------------------------------------- +-- With help from MAME F8 model + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +USE std.textio.ALL; + +LIBRARY work; +USE work.base_pack.ALL; +USE work.f8_pack.ALL; + +ENTITY f8_cpu IS + PORT ( + dr : IN uv8; -- Data Read + dw : OUT uv8; -- Data Write / Address + dv : OUT std_logic; + + romc : OUT uv5; + tick : OUT std_logic; -- 1/4 or 1/6 cycle lenght + phase : OUT uint4; + + po_a : OUT uv8; + pi_a : IN uv8; + po_b : OUT uv8; + pi_b : IN uv8; + + clk : IN std_logic; + ce : IN std_logic; + reset_na : IN std_logic + ); +END ENTITY; + +ARCHITECTURE rtl OF f8_cpu IS + + SIGNAL phase_l : uint4; + + SIGNAL madrs : uint11; -- 256 * 8 = 2048 microcode entries + SIGNAL opcode : uv8; + SIGNAL mop : type_microcode; + SIGNAL acc : uv8; + SIGNAL visar : uv6; + ALIAS visarl : uv3 IS visar(2 DOWNTO 0); + + SIGNAL rs,rd : uint6; + SIGNAL scratch_regs : arr_uv8(0 TO 63); -- Scratch regs + SIGNAL sreg_ra,sreg_wa : uint6; + SIGNAL sreg_rd,sreg_wd : uv8; + SIGNAL sreg_wr : std_logic; + + SIGNAL iozcs : uv5; + + SIGNAL op : enum_op; + + SIGNAL poa_l,pob_l : uv8; + SIGNAL alu : uv8; + SIGNAL test,bcc,testp,bccp,dstm : std_logic; + + SIGNAL txt : string(1 TO 12); + +BEGIN + + phase<=phase_l; + po_a<=poa_l; + po_b<=pob_l; + + ---------------------------------------------------------- + romc<=ROMC_01 WHEN (bcc='1' AND test='1') OR + (opcode=x"8F" AND isarl/=7 AND mop.romc=ROMC_03) ELSE + ROMC_03 WHEN (bcc='1' AND test='0') OR + (opcode=x"8F" AND isarl=7 AND mop.romc=ROMC_03) ELSE + mop.romc; + + sreg_ra<=mop.rs WHEN mop.rs<16 ELSE + mop.rd WHEN mop.rd<16 ELSE + to_integer(visar); + + sreg_rd<=scratch_regs(sreg_ra) WHEN rising_edge(clk); + + PROCESS(clk) IS + BEGIN + IF rising_edge(clk) THEN + IF sreg_wr='1' THEN + scratch_regs(sreg_wa)<=sreg_wd; + END IF; + END IF; + END PROCESS; + + ---------------------------------------------------------- + PROCESS(clk,reset_na) IS + VARIABLE len_v : enum_len; + VARIABLE rs1_v,rs2_v,rd_v : uv8; + VARIABLE dstm_v,test_v : std_logic; + VARIABLE iozcs_v : uv5; + BEGIN + IF rising_edge(clk) THEN + IF ce='1' THEN + mop<=MICROCODE(madrs); + sreg_wr<='0'; + + ----------------------------------------- + len_v:=mop.len; + IF (bcc='1' AND test='1') OR (opcode=x"8F" AND visarl=7) THEN + len_v:=L; + ELSIF (bcc='1' AND test='0') OR (opcode=x"8F" AND visarl/=7) THEN + len_v:=S; + ELSE + len_v:=mop.len; + END IF; + + IF phase_l=7 AND len_v=S THEN + phase_l<=0; + ELSIF phase_l=11 AND len_v=L THEN + phase_l<=0; + ELSE + phase_l<=phase_l+1; + END IF; + + ----------------------------------------- + CASE phase_l IS + WHEN 0 => + test<=testp; + bcc<=bccp; + + WHEN 1 => + NULL; + WHEN 2 => + NULL; -- + + WHEN 3 => + CASE mop.rd IS + WHEN RACC => rs1_v:=acc; + WHEN R0 | R1 | R2 | R3 | R4 | R5 | R6 | R7 | + R8 | R9 | R10 | R11 | R12 | R13 | R14 | R15 => + rs1_v:=sreg_rd; + WHEN RISAR | RISARP | RISARM => + rs1_v:=sreg_rd; + WHEN DATA => + rs1_v:=dr; + WHEN OTHERS => + rs1_v:=acc; + END CASE; + CASE mop.rs IS + WHEN PORT0 => rs2_v:=pi_a; + WHEN PORT1 => rs2_v:=pi_b; + WHEN RACC => rs2_v:=acc; + WHEN R0 | R1 | R2 | R3 | R4 | R5 | R6 | R7 | + R8 | R9 | R10 | R11 | R12 | R13 | R14 | R15 => + rs2_v:=sreg_rd; + WHEN RISAR | RISARP | RISARM => + rs2_v:=sreg_rd; + WHEN WREG => + rs2_v:="000" & iozcs; + WHEN ISAR => + rs2_v:="00" & visar; + WHEN DATA => + rs2_v:=dr; + WHEN OTHERS => + rs2_v:=acc; + END CASE; + + aluop(mop.op,opcode,rs1_v,rs2_v,iozcs,rd_v,dstm_v,iozcs_v,test_v); + dstm<=dstm_v; + iozcs<=iozcs_v; + alu<=rd_v; + testp<=test_v; + bccp <=to_std_logic(mop.op=OP_TST8 OR mop.op=OP_TST9); + + WHEN 4 => + dv<='0'; + IF dstm='1' THEN + CASE mop.rd IS + WHEN RACC => acc<=alu; + WHEN PORT0 => poa_l<=alu; + WHEN PORT1 => pob_l<=alu; + WHEN WREG => iozcs<=alu(4 DOWNTO 0); + WHEN ISARU => visar(5 DOWNTO 3)<=alu(2 DOWNTO 0); + WHEN ISARL => visar(2 DOWNTO 0)<=alu(2 DOWNTO 0); + WHEN ISAR => visar<=alu(5 DOWNTO 0); + WHEN R0 | R1 | R2 | R3 | R4 | R5 | R6 | R7 | + R8 | R9 | R10 | R11 | R12 | R13 | R14 | R15 => + sreg_wd<=alu; + sreg_wa<=mop.rd; + sreg_wr<='1'; + WHEN RISAR | RISARP | RISARM => + sreg_wd<=alu; + sreg_wa<=to_integer(visar); + sreg_wr<='1'; + WHEN DATA => + dw<=alu; + dv<='1'; + WHEN OTHERS => NULL; + END CASE; + END IF; + + WHEN 5 => + IF mop.rs=RISARP OR mop.rd=RISARP THEN + visar(2 DOWNTO 0)<=visar(2 DOWNTO 0)+1; + END IF; + IF mop.rs=RISARM OR mop.rd=RISARM THEN + visar(2 DOWNTO 0)<=visar(2 DOWNTO 0)-1; + END IF; + + WHEN 7 => + IF len_v=S THEN + IF mop.romc=ROMC_00 THEN -- IFETCH + opcode<=dr; + txt<=OPTXT(to_integer(dr)); + madrs<=to_integer(dr)*8; + ELSE + madrs<=madrs+1; + END IF; + END IF; + + WHEN 11 => + IF len_v=L THEN + IF mop.romc=ROMC_00 THEN -- IFETCH + opcode<=dr; + txt<=OPTXT(to_integer(dr)); + madrs<=to_integer(dr)*8; + ELSE + madrs<=madrs+1; + END IF; + END IF; + + WHEN OTHERS => + NULL; + + END CASE; + + IF reset_na='0' THEN + opcode<=OP_RESET; + txt<=OPTXT(to_integer(OP_RESET)); + madrs<=to_integer(OP_RESET)*8; + phase_l<=0; + iozcs<="00000"; + END IF; + + END IF; + + END IF; + END PROCESS; + +END ARCHITECTURE rtl; + diff --git a/Console_MiST/ChannelF_MiST/rtl/f8_pack.vhd b/Console_MiST/ChannelF_MiST/rtl/f8_pack.vhd new file mode 100644 index 00000000..235ac5f0 --- /dev/null +++ b/Console_MiST/ChannelF_MiST/rtl/f8_pack.vhd @@ -0,0 +1,902 @@ +-------------------------------------------------------------------------------- +-- Fairchild F8 CPU +-------------------------------------------------------------------------------- +-- DO 8/2020 +-------------------------------------------------------------------------------- +-- With help from MAME F8 model + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY work; +USE work.base_pack.ALL; + +PACKAGE f8_pack IS + + TYPE type_rom IS ARRAY(0 TO 1023) OF uv8; + + -------------------------------------- + FUNCTION test_bf(op : uv4; + iozcs : uv5) RETURN boolean; + FUNCTION test_bt(op : uv3; + iozcs : uv5) RETURN boolean; + + TYPE enum_len IS (S,L); + TYPE enum_int IS (I0,IX,IY); + TYPE enum_op IS ( + OP_NOP,OP_MOV, + OP_ADD,OP_ADDD,OP_AND,OP_OR ,OP_XOR,OP_CMP, + OP_SR1,OP_SL1,OP_SR4, OP_SL4, + OP_COM,OP_LNK,OP_EDI, + OP_INC,OP_DEC,OP_LIS,OP_TST8,OP_TST9); + + PROCEDURE aluop(op : IN enum_op; -- ALU operation + code : IN uv8; -- OPCODE + src1 : IN uv8; -- Source Reg 1 + src2 : IN uv8; -- Source Reg 2 + iozcs_i : IN uv5; -- Flags before + dst : OUT uv8; -- Result + dstm : OUT std_logic; -- Modified result reg + iozcs_o : OUT uv5; -- Flags after + test : OUT std_logic); -- Contitional branch test result + + -------------------------------------- + CONSTANT R0 : uint5 := 0; + CONSTANT R1 : uint5 := 1; + CONSTANT R2 : uint5 := 2; + CONSTANT R3 : uint5 := 3; + CONSTANT R4 : uint5 := 4; + CONSTANT R5 : uint5 := 5; + CONSTANT R6 : uint5 := 6; + CONSTANT R7 : uint5 := 7; + CONSTANT R8 : uint5 := 8; + CONSTANT R9 : uint5 := 9; + CONSTANT R10 : uint5 := 10; + CONSTANT R11 : uint5 := 11; + CONSTANT R12 : uint5 := 12; + CONSTANT R13 : uint5 := 13; + CONSTANT R14 : uint5 := 14; + CONSTANT R15 : uint5 := 15; + + CONSTANT RACC : uint5 := 16; + + CONSTANT WREG : uint5 := 17; + CONSTANT ISARU : uint5 := 18; + CONSTANT ISARL : uint5 := 19; + CONSTANT ISAR : uint5 := 20; + + CONSTANT RISAR : uint5 := 21; + CONSTANT RISARP : uint5 := 22; + CONSTANT RISARM : uint5 := 23; + + CONSTANT PORT0 : uint5 := 24; + CONSTANT PORT1 : uint5 := 25; + + CONSTANT DATA : uint5 := 31; + + TYPE type_microcode IS RECORD + romc : uv5; + len : enum_len; + last : uint1; + int : enum_int; + op : enum_op; + rd : uint5; + rs : uint5; + END RECORD; + TYPE arr_microcode IS ARRAY(natural RANGE <>) OF type_microcode; + + CONSTANT OP_RESET : uv8 := x"2F"; + CONSTANT OP_INTERRUPT : uv8 := x"2E"; + + CONSTANT ROMC_00 : uv5 :="00000"; + CONSTANT ROMC_01 : uv5 :="00001"; + CONSTANT ROMC_02 : uv5 :="00010"; + CONSTANT ROMC_03 : uv5 :="00011"; -- or 01 for cond. branches + CONSTANT ROMC_04 : uv5 :="00100"; + CONSTANT ROMC_05 : uv5 :="00101"; + CONSTANT ROMC_06 : uv5 :="00110"; + CONSTANT ROMC_07 : uv5 :="00111"; + CONSTANT ROMC_08 : uv5 :="01000"; + CONSTANT ROMC_09 : uv5 :="01001"; + CONSTANT ROMC_0A : uv5 :="01010"; + CONSTANT ROMC_0B : uv5 :="01011"; + CONSTANT ROMC_0C : uv5 :="01100"; + CONSTANT ROMC_0D : uv5 :="01101"; + CONSTANT ROMC_0E : uv5 :="01110"; + CONSTANT ROMC_0F : uv5 :="01111"; + CONSTANT ROMC_10 : uv5 :="10000"; + CONSTANT ROMC_11 : uv5 :="10001"; + CONSTANT ROMC_12 : uv5 :="10010"; + CONSTANT ROMC_13 : uv5 :="10011"; + CONSTANT ROMC_14 : uv5 :="10100"; + CONSTANT ROMC_15 : uv5 :="10101"; + CONSTANT ROMC_16 : uv5 :="10110"; + CONSTANT ROMC_17 : uv5 :="10111"; + CONSTANT ROMC_18 : uv5 :="11000"; + CONSTANT ROMC_19 : uv5 :="11001"; + CONSTANT ROMC_1A : uv5 :="11010"; + CONSTANT ROMC_1B : uv5 :="11011"; + CONSTANT ROMC_1C : uv5 :="11100"; + CONSTANT ROMC_1D : uv5 :="11101"; + CONSTANT ROMC_1E : uv5 :="11110"; + CONSTANT ROMC_1F : uv5 :="11111"; + + CONSTANT ZZ : type_microcode := (ROMC_00,S,1,I0,OP_NOP,RACC,RACC); + + -- ROMC / cycles / op / rdest / rsrc + CONSTANT MICROCODE : arr_microcode(0 TO 256*8-1) := ( + -- ROMC CYC LAST INT ALUOP RDEST RSRC + -- 6 2 1 2 4 5 5 + (ROMC_00,S,1,I0,OP_MOV,RACC,R12), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 00 : A <= r12 : LR A,KU : Load r12 + (ROMC_00,S,1,I0,OP_MOV,RACC,R13), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 01 : A <= r13 : LR A,KL : Load r13 + (ROMC_00,S,1,I0,OP_MOV,RACC,R14), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 02 : A <= r14 : LR A,QU : Load r14 + (ROMC_00,S,1,I0,OP_MOV,RACC,R15), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 03 : A <= r15 : LR A,QL : Load r15 + (ROMC_00,S,1,I0,OP_MOV,R12,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 04 : r12 <= A : LR KU,A : Store r12 + (ROMC_00,S,1,I0,OP_MOV,R13,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 05 : r13 <= A : LR KL,A : Store r13 + (ROMC_00,S,1,I0,OP_MOV,R14,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 06 : r14 <= A : LR QU,A : Store r14 + (ROMC_00,S,1,I0,OP_MOV,R15,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 07 : r15 <= A : LR QL,A : Store r15 + (ROMC_07,L,0,I0,OP_MOV,R12,DATA), -- 08 : r12 <= data <= PC1U : LR K,P : Store stack reg. + (ROMC_0B,L,0,I0,OP_MOV,R13,DATA), -- r13 <= data <= PC1L + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_15,L,0,I0,OP_MOV,DATA,R12), -- 09 : PC1U <= data <= r12 : LR P,K : Load stack reg. + (ROMC_18,L,0,I0,OP_MOV,DATA,R13), -- PC1L <= data <= r13 + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_00,S,1,I0,OP_MOV,RACC,ISAR), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 0A : ACC <= ISAR : LR A,IS : Store ISAR + (ROMC_00,S,1,I0,OP_MOV,ISAR,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 0B : ISAR <= ACC : LR IS,A : Load ISAR + (ROMC_12,L,0,I0,OP_MOV,DATA,R13), -- 0C : PC1 <= PC0 PC0L <= data <= R13 : PK : Call subroutine + (ROMC_14,L,0,I0,OP_MOV,DATA,R12), -- PC0U <= data <= R12 + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_17,L,0,I0,OP_MOV,DATA,R15), -- 0D : PC0L <= data <= R15 : LR : Load Program Counter + (ROMC_14,L,0,I0,OP_MOV,DATA,R14), -- PC0U <= data <= R14 + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_06,L,0,I0,OP_MOV,R14,DATA), -- 0E : R14 <= data <= DC0U : LR Q,DC : Store d count r14/15 + (ROMC_09,L,0,I0,OP_MOV,R15,DATA), -- R15 <= data <= DC0L + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_16,L,0,I0,OP_MOV,DATA,R14), -- 0F : DC0U <= data <= R14 : LR DC,Q : Load d count r14/15 + (ROMC_19,L,0,I0,OP_MOV,DATA,R15), -- DC0L <= data <= R15 + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_16,L,0,I0,OP_MOV,DATA,R10), -- 10 : DC0U <= data <= R10 : LR DC,H : Load d count r10/11 + (ROMC_19,L,0,I0,OP_MOV,DATA,R11), -- DC0L <= data <= R11 + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_06,L,0,I0,OP_MOV,R10,DATA), -- 11 : R10 <= data <= DC0U : LR H,DC : Store d count r10/11 + (ROMC_09,L,0,I0,OP_MOV,R11,DATA), -- R11 <= data <= DC0L + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_00,S,1,I0,OP_SR1,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 12 : ACC <= ACC >> 1 : SR 1 : Shift right one + (ROMC_00,S,1,I0,OP_SL1,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 13 : ACC <= ACC << 1 : SL 1 : Shift left one + (ROMC_00,S,1,I0,OP_SR4,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 14 : ACC <= ACC >> 4 : SR 4 : Shift right four + (ROMC_00,S,1,I0,OP_SL4,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 15 : ACC <= ACC << 4 : SL 4 : Shift left four + (ROMC_02,L,0,I0,OP_MOV,RACC,DATA), -- 16 : ACC <= DATA <= [DC0] : LM : LOAD mem DC0 + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_05,L,0,I0,OP_MOV,DATA,RACC), -- 17 : [DC] <= DATA <= ACC : ST : STORE mem DC0 + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_00,S,1,I0,OP_COM,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 18 : ACC <= !ACC : COM : Complement acc. + (ROMC_00,S,1,I0,OP_LNK,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 19 : ACC <= ACC + carry : LNK : Add Carry acc. + (ROMC_1C,S,0,IY,OP_EDI,RACC,RACC), -- 1A : Clear ICB : DI : Disable Interrupt + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_EDI,RACC,RACC), -- 1B : Set ICB : EI : Enable Interrupt + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_04,S,0,I0,OP_NOP,RACC,RACC), -- 1C : PC0 <= PC1 : POP : Return from sub + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_MOV,WREG,R9), -- 1D : W <= R9 statusreg : LR W,J : Load Status reg r9 + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_00,S,1,I0,OP_MOV,R9,WREG), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 1E : R9 <= W statusreg : LR J,W : Store Status reg r9 + (ROMC_00,S,1,I0,OP_INC,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 1F : ACC <= ACC + 1 : INC : Increment + (ROMC_03,L,0,I0,OP_MOV,RACC,DATA), -- 20 II : ACC <= IMM : LI ii : LOAD immediate acc. + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_03,L,0,I0,OP_AND,RACC,DATA), -- 21 II : ACC <= ACC & IMM : NI ii : AND immediate acc. + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_03,L,0,I0,OP_OR ,RACC,DATA), -- 22 II : ACC <= ACC | IMM : OI ii : OR immediate acc. + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_03,L,0,I0,OP_XOR,RACC,DATA), -- 23 II : ACC <= ACC ^ IMM : XI ii : XOR immediate acc. + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_03,L,0,I0,OP_ADD,RACC,DATA), -- 24 II : ACC <= ACC + IMM : AI ii : ADD immediate acc. + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_03,L,0,I0,OP_CMP,RACC,DATA), -- 25 II : CMP (ACC,IMM) : CI ii : CMP immediate acc. + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_03,L,0,I0,OP_NOP,RACC,RACC), -- 26 II : (fetch operand) : IN aa : Input port aa + (ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- ACC <= IOport[DB] + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_03,L,0,I0,OP_NOP,RACC,RACC), -- 27 II : (fetch operand) : OUT aa : Output port aa + (ROMC_1A,L,0,I0,OP_MOV,DATA,RACC), -- IOport[DB] <= ACC + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_03,L,0,I0,OP_MOV,RACC,DATA), -- 28 AAAA : ACC <= DATA (immediate) : PI aaaa : Call Subroutine + (ROMC_0D,S,0,I0,OP_NOP,RACC,RACC), -- PC1 <= PC0 + 1 + (ROMC_0C,L,0,I0,OP_MOV,DATA,DATA), -- PC0L <= DATA (immediate) + (ROMC_14,L,0,I0,OP_MOV,DATA,RACC), -- PC0U <= DATA <= ACC + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ, + (ROMC_03,L,0,I0,OP_MOV,RACC,DATA), -- 29 AAAA : ACC <= DATA (immediate) : JMP aaaa : JUMP + (ROMC_0C,L,0,I0,OP_MOV,DATA,DATA), -- PC0L <= DATA (immediate) + (ROMC_14,L,0,I0,OP_MOV,DATA,RACC), -- PC0U <= DATA <= ACC + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ, + (ROMC_11,L,0,I0,OP_MOV,DATA,DATA), -- 2A AAAA : DC0U <= DATA (immediate) : DCI aaaa : Load DC imm. + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- PC0 ++ + (ROMC_0E,L,0,I0,OP_MOV,DATA,DATA), -- DC0L <= DATA (immediate) + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- PC0 ++ + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ, + + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 2B : No Operation : NOP + + (ROMC_1D,S,1,I0,OP_NOP,RACC,RACC), -- 2C : DC0 <=> DC1 : XDC + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 2D : Undefined ? : NOP + + -- INTERRUPT (undef opcode) --------------------------- + (ROMC_1C,L,0,I0,OP_NOP,RACC,RACC), -- 2E : : + (ROMC_0F,L,0,I0,OP_NOP,RACC,RACC), -- PC0L <= int vect low, PC1 <= PC0 + (ROMC_13,L,0,IY,OP_NOP,RACC,RACC), -- PC0U <= int vect high + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ, + + -- RESET (undef opcode) ------------------------------- + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- 2F : + (ROMC_08,L,0,IY,OP_NOP,RACC,RACC), -- PC0 <= 0 PC1 <= PC0 + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + + (ROMC_00,L,1,I0,OP_DEC,R0 ,R0 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 30 : R0 -- : DS R0 : Decrement R0 + (ROMC_00,L,1,I0,OP_DEC,R1 ,R1 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 31 : R1 -- : DS R1 : Decrement R1 + (ROMC_00,L,1,I0,OP_DEC,R2 ,R2 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 32 : R2 -- : DS R2 : Decrement R2 + (ROMC_00,L,1,I0,OP_DEC,R3 ,R3 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 33 : R3 -- : DS R3 : Decrement R3 + (ROMC_00,L,1,I0,OP_DEC,R4 ,R4 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 34 : R4 -- : DS R4 : Decrement R4 + (ROMC_00,L,1,I0,OP_DEC,R5 ,R5 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 35 : R5 -- : DS R5 : Decrement R5 + (ROMC_00,L,1,I0,OP_DEC,R6 ,R6 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 36 : R6 -- : DS R6 : Decrement R6 + (ROMC_00,L,1,I0,OP_DEC,R7 ,R7 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 37 : R7 -- : DS R7 : Decrement R7 + (ROMC_00,L,1,I0,OP_DEC,R8 ,R8 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 38 : R8 -- : DS R8 : Decrement R8 + (ROMC_00,L,1,I0,OP_DEC,R9 ,R9 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 39 : R9 -- : DS R9 : Decrement R9 + (ROMC_00,L,1,I0,OP_DEC,R10,R10), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 3A : R10-- : DS R10 : Decrement R10 + (ROMC_00,L,1,I0,OP_DEC,R11,R11), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 3B : R11-- : DS R11 : Decrement R11 + (ROMC_00,L,1,I0,OP_DEC,RISAR,RISAR), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 3C : (ISAR)-- : DS (ISAR) : Decrement (ISAR) + (ROMC_00,L,1,I0,OP_DEC,RISARP,RISARP), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 3D : (ISAR++)-- : DS (ISAR+) : Decrement (ISAR++) + (ROMC_00,L,1,I0,OP_DEC,RISARM,RISARM), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 3E : (ISAR++)-- : DS (ISAR-) : Decrement (ISAR--) + (ROMC_00,L,1,I0,OP_DEC,R15,R15), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 3F : R15-- : DS R15 : Decrement R15 + + (ROMC_00,S,1,I0,OP_MOV,RACC,R0 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 40 : ACC <= R0 : LR A,R0 : LOAD R0 + (ROMC_00,S,1,I0,OP_MOV,RACC,R1 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 41 : ACC <= R1 : LR A,R1 : LOAD R1 + (ROMC_00,S,1,I0,OP_MOV,RACC,R2 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 42 : ACC <= R2 : LR A,R2 : LOAD R2 + (ROMC_00,S,1,I0,OP_MOV,RACC,R3 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 43 : ACC <= R3 : LR A,R3 : LOAD R3 + (ROMC_00,S,1,I0,OP_MOV,RACC,R4 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 44 : ACC <= R4 : LR A,R4 : LOAD R4 + (ROMC_00,S,1,I0,OP_MOV,RACC,R5 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 45 : ACC <= R5 : LR A,R5 : LOAD R5 + (ROMC_00,S,1,I0,OP_MOV,RACC,R6 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 46 : ACC <= R6 : LR A,R6 : LOAD R6 + (ROMC_00,S,1,I0,OP_MOV,RACC,R7 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 47 : ACC <= R7 : LR A,R7 : LOAD R7 + (ROMC_00,S,1,I0,OP_MOV,RACC,R8 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 48 : ACC <= R8 : LR A,R8 : LOAD R8 + (ROMC_00,S,1,I0,OP_MOV,RACC,R9 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 49 : ACC <= R9 : LR A,R9 : LOAD R9 + (ROMC_00,S,1,I0,OP_MOV,RACC,R10), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 4A : ACC <= R10 : LR A,R10 : LOAD R10 + (ROMC_00,S,1,I0,OP_MOV,RACC,R11), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 4B : ACC <= R11 : LR A,R11 : LOAD R11 + (ROMC_00,S,1,I0,OP_MOV,RACC,RISAR), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 4C : ACC <= (ISAR) : LR A,(ISAR) : LOAD (ISAR) + (ROMC_00,S,1,I0,OP_MOV,RACC,RISARP), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 4D : ACC <= (ISAR++) : LR A,(ISAR+) : LOAD (ISAR++) + (ROMC_00,S,1,I0,OP_MOV,RACC,RISARM), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 4E : ACC <= (ISAR--) : LR A,(ISAR-) : LOAD (ISAR--) + (ROMC_00,S,1,I0,OP_MOV,RACC,R15), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 4F : ACC <= R15- : LR A,R15 : LOAD R15 + + (ROMC_00,S,1,I0,OP_MOV,R0 ,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 50 : R0 <= ACC : LR R0 ,A : STORE R0 + (ROMC_00,S,1,I0,OP_MOV,R1 ,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 51 : R1 <= ACC : LR R1 ,A : STORE R1 + (ROMC_00,S,1,I0,OP_MOV,R2 ,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 52 : R2 <= ACC : LR R2 ,A : STORE R2 + (ROMC_00,S,1,I0,OP_MOV,R3 ,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 53 : R3 <= ACC : LR R3 ,A : STORE R3 + (ROMC_00,S,1,I0,OP_MOV,R4 ,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 54 : R4 <= ACC : LR R4 ,A : STORE R4 + (ROMC_00,S,1,I0,OP_MOV,R5 ,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 55 : R5 <= ACC : LR R5 ,A : STORE R5 + (ROMC_00,S,1,I0,OP_MOV,R6 ,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 56 : R6 <= ACC : LR R6 ,A : STORE R6 + (ROMC_00,S,1,I0,OP_MOV,R7 ,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 57 : R7 <= ACC : LR R7 ,A : STORE R7 + (ROMC_00,S,1,I0,OP_MOV,R8 ,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 58 : R8 <= ACC : LR R8 ,A : STORE R8 + (ROMC_00,S,1,I0,OP_MOV,R9 ,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 59 : R9 <= ACC : LR R9 ,A : STORE R9 + (ROMC_00,S,1,I0,OP_MOV,R10,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 5A : R10 <= ACC : LR R10,A : STORE R10 + (ROMC_00,S,1,I0,OP_MOV,R11,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 5B : R11 <= ACC : LR R11,A : STORE R11 + (ROMC_00,S,1,I0,OP_MOV,RISAR,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 5C : (ISAR) <= ACC : LR (ISAR),A : STORE (ISAR) + (ROMC_00,S,1,I0,OP_MOV,RISARP,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 5D : (ISAR++) <= ACC : LR (ISAR+),A : STORE (ISAR++) + (ROMC_00,S,1,I0,OP_MOV,RISARM,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 5E : (ISAR--) <= ACC : LR (ISAR-),A : STORE (ISAR--) + (ROMC_00,S,1,I0,OP_MOV,R15,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 5F : R15 <= ACC : LR R15,A : STORE R15 + + (ROMC_00,S,1,I0,OP_LIS,ISARU,R0), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 60 : ISARU <= 0 : LISU 0 : Load ISAR upper + (ROMC_00,S,1,I0,OP_LIS,ISARU,R1), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 61 : ISARU <= 1 : LISU 1 : Load ISAR upper + (ROMC_00,S,1,I0,OP_LIS,ISARU,R2), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 62 : ISARU <= 2 : LISU 2 : Load ISAR upper + (ROMC_00,S,1,I0,OP_LIS,ISARU,R3), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 63 : ISARU <= 3 : LISU 3 : Load ISAR upper + (ROMC_00,S,1,I0,OP_LIS,ISARU,R4), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 64 : ISARU <= 4 : LISU 4 : Load ISAR upper + (ROMC_00,S,1,I0,OP_LIS,ISARU,R5), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 65 : ISARU <= 5 : LISU 5 : Load ISAR upper + (ROMC_00,S,1,I0,OP_LIS,ISARU,R6), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 66 : ISARU <= 6 : LISU 6 : Load ISAR upper + (ROMC_00,S,1,I0,OP_LIS,ISARU,R7), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 67 : ISARU <= 7 : LISU 7 : Load ISAR upper + + (ROMC_00,S,1,I0,OP_LIS,ISARL,R0), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 68 : ISARL <= 0 : LISL 0 : Load ISAR lower + (ROMC_00,S,1,I0,OP_LIS,ISARL,R1), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 69 : ISARL <= 1 : LISL 1 : Load ISAR lower + (ROMC_00,S,1,I0,OP_LIS,ISARL,R2), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 6A : ISARL <= 2 : LISL 2 : Load ISAR lower + (ROMC_00,S,1,I0,OP_LIS,ISARL,R3), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 6B : ISARL <= 3 : LISL 3 : Load ISAR lower + (ROMC_00,S,1,I0,OP_LIS,ISARL,R4), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 6C : ISARL <= 4 : LISL 4 : Load ISAR lower + (ROMC_00,S,1,I0,OP_LIS,ISARL,R5), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 6D : ISARL <= 5 : LISL 5 : Load ISAR lower + (ROMC_00,S,1,I0,OP_LIS,ISARL,R6), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 6E : ISARL <= 6 : LISL 6 : Load ISAR lower + (ROMC_00,S,1,I0,OP_LIS,ISARL,R7), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 6F : ISARL <= 7 : LISL 7 : Load ISAR lower + + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 70 : ACC <= 0 : LIS 0 : Load ACC 0 / CLR ACC + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 71 : ACC <= 1 : LIS 1 : Load ACC 1 + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 72 : ACC <= 2 : LIS 2 : Load ACC 2 + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 73 : ACC <= 3 : LIS 3 : Load ACC 3 + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 74 : ACC <= 4 : LIS 4 : Load ACC 4 + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 75 : ACC <= 5 : LIS 5 : Load ACC 5 + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 76 : ACC <= 6 : LIS 6 : Load ACC 6 + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 77 : ACC <= 7 : LIS 7 : Load ACC 7 + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 78 : ACC <= 8 : LIS 8 : Load ACC 8 + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 79 : ACC <= 9 : LIS 9 : Load ACC 9 + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 7A : ACC <= 10 : LIS 10 : Load ACC 10 + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 7B : ACC <= 11 : LIS 11 : Load ACC 11 + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 7C : ACC <= 12 : LIS 12 : Load ACC 12 + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 7D : ACC <= 13 : LIS 13 : Load ACC 13 + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 7E : ACC <= 14 : LIS 14 : Load ACC 14 + (ROMC_00,S,1,I0,OP_LIS,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- 7F : ACC <= 15 : LIS 15 : Load ACC 15 + + (ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 80 : Test 0 : Bcc 0 : Branch cond. + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 81 : Test 1 : Bcc 1 : Branch cond. + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 82 : Test 2 : Bcc 2 : Branch cond. + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 83 : Test 3 : Bcc 3 : Branch cond. + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 84 : Test 4 : Bcc 4 : Branch cond. + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 85 : Test 5 : Bcc 5 : Branch cond. + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 86 : Test 6 : Bcc 6 : Branch cond. + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST8,RACC,RACC), -- 87 : Test 7 : Bcc 7 : Branch cond. + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + + (ROMC_02,L,0,I0,OP_ADD,RACC,DATA), -- 88 : ACC = ACC + [DC0] , DC0++ : AM : Add Binary mem + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_02,L,0,I0,OP_ADDD,RACC,DATA), -- 89 : ACC = ACC +D [DC0] , DC0++ : AMD : Add Decimal mem + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_02,L,0,I0,OP_AND,RACC,DATA), -- 8A : ACC = ACC AND [DC0] , DC0++ : NM : AND mem + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_02,L,0,I0,OP_OR ,RACC,DATA), -- 8B : ACC = ACC OR [DC0] , DC0++ : OM : OR mem + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_02,L,0,I0,OP_XOR,RACC,DATA), -- 8C : ACC = ACC XOR [DC0] , DC0++ : XM : XOR mem + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_02,L,0,I0,OP_CMP,RACC,DATA), -- 8D : CMP(ACC,[DC0]) , DC0++ : CM : CMP mem + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_0A,L,0,I0,OP_MOV,DATA,RACC), -- 8E : DC = DC + ACC (signed) : ADC : Add Data counter + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- 8F aa : Selon ISARL, PC +2 ou +imm : BR7 aa : Branch if ISARlo/=7 + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 90 aa : : BF 0 : Branch if negative + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 91 aa : : BF 1 : Branch if no carry + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 92 aa : : BF 2 : Branch if + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 93 aa : : BF 3 : Branch if + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 94 aa : : BF 4 : Branch if + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 95 aa : : BF 5 : Branch if + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 96 aa : : BF 6 : Branch if + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 97 aa : : BF 7 : Branch if + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 98 aa : : BF 8 : Branch if + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 99 aa : : BF 9 : Branch if + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 9A aa : : BF A : Branch if + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 9B aa : : BF B : Branch if + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 9C aa : : BF C : Branch if + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 9D aa : : BF D : Branch if + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 9E aa : : BF E : Branch if + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_TST9,RACC,RACC), -- 9F aa : : BF F : Branch if + (ROMC_03,S,0,I0,OP_NOP,RACC,RACC), -- Selon test, change PC0 + 2 ou +imm + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + + (ROMC_1C,S,0,I0,OP_MOV,RACC,PORT0), -- A0 : ACC <= IOPORT[0] : INS 0 : Input port 0 + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_MOV,RACC,PORT1), -- A1 : ACC <= IOPORT[1] : INS 1 : Input port 1 + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + + (ROMC_1C,L,0,I0,OP_LIS,DATA,R2), -- A2 : DATA <= IOPPORTNUM : INS 2 : Input port 2 + (ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + + (ROMC_1C,L,0,I0,OP_LIS,DATA,R3), -- A3 : DATA <= IOPPORTNUM : INS 3 : Input port 3 + (ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R4), -- A4 : DATA <= IOPPORTNUM : INS 4 : Input port 4 + (ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R5), -- A5 : DATA <= IOPPORTNUM : INS 5 : Input port 5 + (ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R6), -- A6 : DATA <= IOPPORTNUM : INS 6 : Input port 6 + (ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R7), -- A7 : DATA <= IOPPORTNUM : INS 7 : Input port 7 + (ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R8), -- A8 : DATA <= IOPPORTNUM : INS 8 : Input port 8 + (ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R9), -- A9 : DATA <= IOPPORTNUM : INS 9 : Input port 9 + (ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R10), -- AA : DATA <= IOPPORTNUM : INS 10 : Input port 10 + (ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R11), -- AB : DATA <= IOPPORTNUM : INS 11 : Input port 11 + (ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R12), -- AC : DATA <= IOPPORTNUM : INS 12 : Input port 12 + (ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R13), -- AD : DATA <= IOPPORTNUM : INS 13 : Input port 13 + (ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R14), -- AE : DATA <= IOPPORTNUM : INS 14 : Input port 14 + (ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R15), -- AF : DATA <= IOPPORTNUM : INS 15 : Input port 15 + (ROMC_1B,L,0,I0,OP_MOV,RACC,DATA), -- DB <= DATA ioport + (ROMC_00,S,1,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + + (ROMC_1C,S,0,I0,OP_MOV,PORT0,RACC), -- B0 : IOPORT[0] <= ACC : OUTS 0 : Output port 0 + (ROMC_00,S,0,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_MOV,PORT1,RACC), -- B1 : IOPORT[1] <= ACC : OUTS 1 : Output port 1 + (ROMC_00,S,0,I0,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R2), -- B2 : DATA <= IOPPORTNUM : OUTS 2 : Output port 2 + (ROMC_1A,L,0,I0,OP_MOV,DATA,RACC), -- DATA ioport <= DB + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R3), -- B3 : DATA <= IOPPORTNUM : OUTS 3 : Output port 3 + (ROMC_1A,L,0,I0,OP_MOV,DATA,RACC), -- DATA ioport <= DB + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R4), -- B4 : DATA <= IOPPORTNUM : OUTS 4 : Output port 4 + (ROMC_1A,L,0,I0,OP_MOV,DATA,RACC), -- DATA ioport <= DB + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R5), -- B5 : DATA <= IOPPORTNUM : OUTS 5 : Output port 5 + (ROMC_1A,L,0,I0,OP_MOV,DATA,RACC), -- DATA ioport <= DB + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R6), -- B6 : DATA <= IOPPORTNUM : OUTS 6 : Output port 6 + (ROMC_1A,L,0,I0,OP_MOV,DATA,RACC), -- DATA ioport <= DB + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R7), -- B7 : DATA <= IOPPORTNUM : OUTS 7 : Output port 7 + (ROMC_1A,L,0,I0,OP_MOV,DATA,RACC), -- DATA ioport <= DB + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R8), -- B8 : DATA <= IOPPORTNUM : OUTS 8 : Output port 8 + (ROMC_1A,L,0,I0,OP_MOV,DATA,RACC), -- DATA ioport <= DB + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R9), -- B9 : DATA <= IOPPORTNUM : OUTS 9 : Output port 9 + (ROMC_1A,L,0,I0,OP_MOV,DATA,RACC), -- DATA ioport <= DB + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R10), -- BA : DATA <= IOPPORTNUM : OUTS 10 : Output port 10 + (ROMC_1A,L,0,I0,OP_MOV,DATA,RACC), -- DATA ioport <= DB + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R11), -- BB : DATA <= IOPPORTNUM : OUTS 11 : Output port 11 + (ROMC_1A,L,0,I0,OP_MOV,DATA,RACC), -- DATA ioport <= DB + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R12), -- BC : DATA <= IOPPORTNUM : OUTS 12 : Output port 12 + (ROMC_1A,L,0,I0,OP_MOV,DATA,RACC), -- DATA ioport <= DB + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R13), -- BD : DATA <= IOPPORTNUM : OUTS 13 : Output port 13 + (ROMC_1A,L,0,I0,OP_MOV,DATA,RACC), -- DATA ioport <= DB + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R14), -- BE : DATA <= IOPPORTNUM : OUTS 14 : Output port 14 + (ROMC_1A,L,0,I0,OP_MOV,DATA,RACC), -- DATA ioport <= DB + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,L,0,I0,OP_LIS,DATA,R15), -- BF : DATA <= IOPPORTNUM : OUTS 15 : Output port 15 + (ROMC_1A,L,0,I0,OP_MOV,DATA,RACC), -- DATA ioport <= DB + (ROMC_00,S,1,IX,OP_NOP,RACC,RACC), ZZ,ZZ,ZZ,ZZ,ZZ, + + (ROMC_00,S,1,I0,OP_ADD,RACC,R0 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- C0 : ACC <= ACC + R0 : AS R0 : ADD binary R0 + (ROMC_00,S,1,I0,OP_ADD,RACC,R1 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- C1 : ACC <= ACC + R1 : AS R1 : ADD binary R1 + (ROMC_00,S,1,I0,OP_ADD,RACC,R2 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- C2 : ACC <= ACC + R2 : AS R2 : ADD binary R2 + (ROMC_00,S,1,I0,OP_ADD,RACC,R3 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- C3 : ACC <= ACC + R3 : AS R3 : ADD binary R3 + (ROMC_00,S,1,I0,OP_ADD,RACC,R4 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- C4 : ACC <= ACC + R4 : AS R4 : ADD binary R4 + (ROMC_00,S,1,I0,OP_ADD,RACC,R5 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- C5 : ACC <= ACC + R5 : AS R5 : ADD binary R5 + (ROMC_00,S,1,I0,OP_ADD,RACC,R6 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- C6 : ACC <= ACC + R6 : AS R6 : ADD binary R6 + (ROMC_00,S,1,I0,OP_ADD,RACC,R7 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- C7 : ACC <= ACC + R7 : AS R7 : ADD binary R7 + (ROMC_00,S,1,I0,OP_ADD,RACC,R8 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- C8 : ACC <= ACC + R8 : AS R8 : ADD binary R8 + (ROMC_00,S,1,I0,OP_ADD,RACC,R9 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- C9 : ACC <= ACC + R9 : AS R9 : ADD binary R9 + (ROMC_00,S,1,I0,OP_ADD,RACC,R10), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- CA : ACC <= ACC + R10 : AS R10 : ADD binary R10 + (ROMC_00,S,1,I0,OP_ADD,RACC,R11), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- CB : ACC <= ACC + R11 : AS R11 : ADD binary R11 + (ROMC_00,S,1,I0,OP_ADD,RACC,RISAR), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- CC : ACC <= ACC + (ISAR) : AS R12 : ADD binary (ISAR) + (ROMC_00,S,1,I0,OP_ADD,RACC,RISARP), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- CD : ACC <= ACC + (ISAR++) : AS R13 : ADD binary (ISAR++) + (ROMC_00,S,1,I0,OP_ADD,RACC,RISARM), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- CE : ACC <= ACC + (ISAR--) : AS R14 : ADD binary (ISAR--) + (ROMC_00,S,1,I0,OP_ADD,RACC,R15), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- CF : ACC <= ACC + R15 : AS R15 : Invalid + + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- D0 : ACC <= ACC + R0 : ASD R0 : ADD decimal R0 + (ROMC_00,S,1,I0,OP_ADDD,RACC,R0 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- D1 : ACC <= ACC + R1 : ASD R1 : ADD decimal R1 + (ROMC_00,S,1,I0,OP_ADDD,RACC,R1 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- D2 : ACC <= ACC + R2 : ASD R2 : ADD decimal R2 + (ROMC_00,S,1,I0,OP_ADDD,RACC,R2 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- D3 : ACC <= ACC + R3 : ASD R3 : ADD decimal R3 + (ROMC_00,S,1,I0,OP_ADDD,RACC,R3 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- D4 : ACC <= ACC + R4 : ASD R4 : ADD decimal R4 + (ROMC_00,S,1,I0,OP_ADDD,RACC,R4 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- D5 : ACC <= ACC + R5 : ASD R5 : ADD decimal R5 + (ROMC_00,S,1,I0,OP_ADDD,RACC,R5 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- D6 : ACC <= ACC + R6 : ASD R6 : ADD decimal R6 + (ROMC_00,S,1,I0,OP_ADDD,RACC,R6 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- D7 : ACC <= ACC + R7 : ASD R7 : ADD decimal R7 + (ROMC_00,S,1,I0,OP_ADDD,RACC,R7 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- D8 : ACC <= ACC + R8 : ASD R8 : ADD decimal R8 + (ROMC_00,S,1,I0,OP_ADDD,RACC,R8 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- D9 : ACC <= ACC + R9 : ASD R9 : ADD decimal R9 + (ROMC_00,S,1,I0,OP_ADDD,RACC,R9 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- DA : ACC <= ACC + R10 : ASD R10 : ADD decimal R10 + (ROMC_00,S,1,I0,OP_ADDD,RACC,R10), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- DB : ACC <= ACC + R11 : ASD R11 : ADD decimal R11 + (ROMC_00,S,1,I0,OP_ADDD,RACC,R11), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- DC : ACC <= ACC + (ISAR) : ASD R12 : ADD decimal (ISAR) + (ROMC_00,S,1,I0,OP_ADDD,RACC,RISAR), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- DD : ACC <= ACC + (ISAR++) : ASD R13 : ADD decimal (ISAR++) + (ROMC_00,S,1,I0,OP_ADDD,RACC,RISARP), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- DE : ACC <= ACC + (ISAR--) : ASD R14 : ADD decimal (ISAR--) + (ROMC_00,S,1,I0,OP_ADDD,RACC,RISARM), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + (ROMC_1C,S,0,I0,OP_NOP,RACC,RACC), -- DF : ACC <= ACC + R15 : ASD R15 : Invalid + (ROMC_00,S,1,I0,OP_ADDD,RACC,R15), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, + + (ROMC_00,S,1,I0,OP_XOR,RACC,R0 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- E0 : ACC <= ACC XOR R0 : XS R0 : XOR R0 + (ROMC_00,S,1,I0,OP_XOR,RACC,R1 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- E1 : ACC <= ACC XOR R1 : XS R1 : XOR R1 + (ROMC_00,S,1,I0,OP_XOR,RACC,R2 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- E2 : ACC <= ACC XOR R2 : XS R2 : XOR R2 + (ROMC_00,S,1,I0,OP_XOR,RACC,R3 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- E3 : ACC <= ACC XOR R3 : XS R3 : XOR R3 + (ROMC_00,S,1,I0,OP_XOR,RACC,R4 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- E4 : ACC <= ACC XOR R4 : XS R4 : XOR R4 + (ROMC_00,S,1,I0,OP_XOR,RACC,R5 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- E5 : ACC <= ACC XOR R5 : XS R5 : XOR R5 + (ROMC_00,S,1,I0,OP_XOR,RACC,R6 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- E6 : ACC <= ACC XOR R6 : XS R6 : XOR R6 + (ROMC_00,S,1,I0,OP_XOR,RACC,R7 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- E7 : ACC <= ACC XOR R7 : XS R7 : XOR R7 + (ROMC_00,S,1,I0,OP_XOR,RACC,R8 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- E8 : ACC <= ACC XOR R8 : XS R8 : XOR R8 + (ROMC_00,S,1,I0,OP_XOR,RACC,R9 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- E9 : ACC <= ACC XOR R9 : XS R9 : XOR R9 + (ROMC_00,S,1,I0,OP_XOR,RACC,R10), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- EA : ACC <= ACC XOR R10 : XS R10 : XOR R10 + (ROMC_00,S,1,I0,OP_XOR,RACC,R11), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- EB : ACC <= ACC XOR R11 : XS R11 : XOR R11 + (ROMC_00,S,1,I0,OP_XOR,RACC,RISAR), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- EC : ACC <= ACC XOR (ISAR) : XS R12 : XOR (ISAR) + (ROMC_00,S,1,I0,OP_XOR,RACC,RISARP), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- ED : ACC <= ACC XOR (ISAR++) : XS R13 : XOR (ISAR++) + (ROMC_00,S,1,I0,OP_XOR,RACC,RISARM), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- EE : ACC <= ACC XOR (ISAR--) : XS R14 : XOR (ISAR--) + (ROMC_00,S,1,I0,OP_XOR,RACC,R15), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- EF : ACC <= ACC XOR R15 : XS R15 : Invalid + + (ROMC_00,S,1,I0,OP_AND,RACC,R0 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- F0 : ACC <= ACC AND R0 : NS R0 : AND R0 + (ROMC_00,S,1,I0,OP_AND,RACC,R1 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- F1 : ACC <= ACC AND R1 : NS R1 : AND R1 + (ROMC_00,S,1,I0,OP_AND,RACC,R2 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- F2 : ACC <= ACC AND R2 : NS R2 : AND R2 + (ROMC_00,S,1,I0,OP_AND,RACC,R3 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- F3 : ACC <= ACC AND R3 : NS R3 : AND R3 + (ROMC_00,S,1,I0,OP_AND,RACC,R4 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- F4 : ACC <= ACC AND R4 : NS R4 : AND R4 + (ROMC_00,S,1,I0,OP_AND,RACC,R5 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- F5 : ACC <= ACC AND R5 : NS R5 : AND R5 + (ROMC_00,S,1,I0,OP_AND,RACC,R6 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- F6 : ACC <= ACC AND R6 : NS R6 : AND R6 + (ROMC_00,S,1,I0,OP_AND,RACC,R7 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- F7 : ACC <= ACC AND R7 : NS R7 : AND R7 + (ROMC_00,S,1,I0,OP_AND,RACC,R8 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- F8 : ACC <= ACC AND R8 : NS R8 : AND R8 + (ROMC_00,S,1,I0,OP_AND,RACC,R9 ), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- F9 : ACC <= ACC AND R9 : NS R9 : AND R9 + (ROMC_00,S,1,I0,OP_AND,RACC,R10), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- FA : ACC <= ACC AND R10 : NS R10 : AND R10 + (ROMC_00,S,1,I0,OP_AND,RACC,R11), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- FB : ACC <= ACC AND R11 : NS R11 : AND R11 + (ROMC_00,S,1,I0,OP_AND,RACC,RISAR), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- FC : ACC <= ACC AND (ISAR) : NS R12 : AND (ISAR) + (ROMC_00,S,1,I0,OP_AND,RACC,RISARP), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- FD : ACC <= ACC AND (ISAR++) : NS R13 : AND (ISAR++) + (ROMC_00,S,1,I0,OP_AND,RACC,RISARM), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ, -- FE : ACC <= ACC AND (ISAR--) : NS R14 : AND (ISAR--) + (ROMC_00,S,1,I0,OP_AND,RACC,R15), ZZ,ZZ,ZZ,ZZ,ZZ,ZZ,ZZ -- FF : ACC <= ACC AND R15 : NS R15 : Invalid + ); + + TYPE arr_string12 IS ARRAY(natural RANGE <>) OF string(1 TO 12); + CONSTANT OPTXT : arr_string12(0 TO 255) :=( + "LR A,KU ", "LR A,KL ", "LR A,QU ", "LR A,QL ", -- 00 + "LR KU,A ", "LR KL,A ", "LR QU,A ", "LR QL,A ", + "LR K,P ", "LR P,K ", "LR A,IS ", "LR IS,A ", + "PK ", "LR ", "LR Q,DC ", "LR DC,Q ", + "LR DC,H ", "LR H,DC ", "SR 1 ", "SL 1 ", -- 10 + "SR 4 ", "SL 4 ", "LM ", "ST ", + "COM ", "LNK ", "DI ", "EI ", + "POP ", "LR W,J ", "LR J,W ", "INC ", + "LI ii ", "NI ii ", "OI ii ", "XI ii ", -- 20 + "AI ii ", "CI ii ", "IN aa ", "OUT aa ", + "PI aaaa ", "JMP aaaa ", "DCI aaaa ", "NOP ", + "XDC ", "NOP ", " ", " ", + "DEC R0 ", "DEC R1 ", "DEC R2 ", "DEC R3 ", -- 30 + "DEC R4 ", "DEC R5 ", "DEC R6 ", "DEC R7 ", + "DEC R8 ", "DEC R9 ", "DEC R10 ", "DEC R11 ", + "DEC (ISAR) ", "DEC (ISAR++)", "DEC (ISAR--)", "Invalid ", + "LR A,R0 ", "LR A,R1 ", "LR A,R2 ", "LR A,R3 ", -- 40 + "LR A,R4 ", "LR A,R5 ", "LR A,R6 ", "LR A,R7 ", + "LR A,R8 ", "LR A,R9 ", "LR A,R10 ", "LR A,R11 ", + "LR A,(ISAR) ", "LR A,(ISAR+)", "LR A,(ISAR-)", "Invalid ", + "LR R0 ,A ", "LR R1 ,A ", "LR R2 ,A ", "LR R3 ,A ", -- 50 + "LR R4 ,A ", "LR R5 ,A ", "LR R6 ,A ", "LR R7 ,A ", + "LR R8 ,A ", "LR R9 ,A ", "LR R10,A ", "LR R11,A ", + "LR (ISAR),A ", "LR (ISAR+),A", "LR (ISAR-),A", "Invalid ", + "LISU 0 ", "LISU 1 ", "LISU 2 ", "LISU 3 ", -- 60 + "LISU 4 ", "LISU 5 ", "LISU 6 ", "LISU 7 ", + "LISL 0 ", "LISL 1 ", "LISL 2 ", "LISL 3 ", + "LISL 4 ", "LISL 5 ", "LISL 6 ", "LISL 7 ", + "LIS 0 ", "LIS 1 ", "LIS 2 ", "LIS 3 ", -- 70 + "LIS 4 ", "LIS 5 ", "LIS 6 ", "LIS 7 ", + "LIS 8 ", "LIS 9 ", "LIS 10 ", "LIS 11 ", + "LIS 12 ", "LIS 13 ", "LIS 14 ", "LIS 15 ", + "BT 0 ", "BT 1 ", "BT 2 ", "BT 3 ", -- 80 + "BT 4 ", "BT 5 ", "BT 6 ", "BT 7 ", + "AM ", "AMD ", "NM ", "OM ", + "XM ", "CM ", "ADC ", "BR7 aa ", + "BF 0 ", "BF 1 ", "BF 2 ", "BF 3 ", -- 90 + "BF 4 ", "BF 5 ", "BF 6 ", "BF 7 ", + "BF 8 ", "BF 9 ", "BF A ", "BF B ", + "BF C ", "BF D ", "BF E ", "BF F ", + "INS 0 ", "INS 1 ", "INS 2 ", "INS 3 ", -- A0 + "INS 4 ", "INS 5 ", "INS 6 ", "INS 7 ", + "INS 8 ", "INS 9 ", "INS 10 ", "INS 11 ", + "INS 12 ", "INS 13 ", "INS 14 ", "INS 15 ", + "OUTS 0 ", "OUTS 1 ", "OUTS 2 ", "OUTS 3 ", -- B0 + "OUTS 4 ", "OUTS 5 ", "OUTS 6 ", "OUTS 7 ", + "OUTS 8 ", "OUTS 9 ", "OUTS 10 ", "OUTS 11 ", + "OUTS 12 ", "OUTS 13 ", "OUTS 14 ", "OUTS 15 ", + "AS R0 ", "AS R1 ", "AS R2 ", "AS R3 ", -- C0 + "AS R4 ", "AS R5 ", "AS R6 ", "AS R7 ", + "AS R8 ", "AS R9 ", "AS R10 ", "AS R11 ", + "AS (ISAR) ", "AS (ISAR++) ", "AS (ISAR--) ", "Invalid ", + "ASD R0 ", "ASD R1 ", "ASD R2 ", "ASD R3 ", -- D0 + "ASD R4 ", "ASD R5 ", "ASD R6 ", "ASD R7 ", + "ASD R8 ", "ASD R9 ", "ASD R10 ", "ASD R11 ", + "ASD (ISAR) ", "ASD (ISAR++)", "ASD (ISAR--)", "Invalid ", + "XOR R0 ", "XOR R1 ", "XOR R2 ", "XOR R3 ", -- E0 + "XOR R4 ", "XOR R5 ", "XOR R6 ", "XOR R7 ", + "XOR R8 ", "XOR R9 ", "XOR R10 ", "XOR R11 ", + "XOR (ISAR) ", "XOR (ISAR++)", "XOR (ISAR--)", "Invalid ", + "AND R0 ", "AND R1 ", "AND R2 ", "AND R3 ", -- F0 + "AND R4 ", "AND R5 ", "AND R6 ", "AND R7 ", + "AND R8 ", "AND R9 ", "AND R10 ", "AND R11 ", + "AND (ISAR) ", "AND (ISAR++)", "AND (ISAR--)", "Invalid "); + +END PACKAGE; + +--############################################################################## +PACKAGE BODY f8_pack IS + FUNCTION test_bf(op : uv4; + iozcs : uv5) RETURN boolean IS + BEGIN + CASE op IS + WHEN "0000" => -- Unconditional Branch + RETURN true; + WHEN "0001" => -- Branch on negative + RETURN (iozcs(0)='0'); + WHEN "0010" => -- Branch if no carry + RETURN (iozcs(1)='0'); + WHEN "0011" => -- Branch if no carry & negative + RETURN (iozcs(1)='0' AND iozcs(0)='0'); + WHEN "0100" => -- Branch if not zero + RETURN (iozcs(2)='0'); + WHEN "0101" => -- Same as T=1 + RETURN (iozcs(0)='0'); + WHEN "0110" => -- Branch if no carry & no zero + RETURN (iozcs(1)='0' AND iozcs(2)='0'); + WHEN "0111" => -- Same as T=3 + RETURN (iozcs(1)='0' AND iozcs(0)='0'); + WHEN "1000" => -- Branch if no overflow + RETURN (iozcs(3)='0'); + WHEN "1001" => -- Branch if negative & no overflow + RETURN (iozcs(3)='0' AND iozcs(0)='0'); + WHEN "1010" => -- Branch if no overflow and no carry + RETURN (iozcs(3)='0' AND iozcs(1)='0'); + WHEN "1011" => -- Branch if no overflow, no carry and negative + RETURN (iozcs(3)='0' AND iozcs(1)='0' AND iozcs(0)='0'); + WHEN "1100" => -- Branch if no overflow and no zero + RETURN (iozcs(3)='0' AND iozcs(2)='0'); + WHEN "1101" => -- Same as T=9 + RETURN (iozcs(3)='0' AND iozcs(0)='0'); + WHEN "1110" => -- Branch if no overflow no carry and not zero + RETURN (iozcs(3)='0' AND iozcs(1)='0' AND iozcs(0)='0'); + WHEN OTHERS => -- Same as T=B + RETURN (iozcs(3)='0' AND iozcs(1)='0' AND iozcs(0)='0'); + END CASE; + END FUNCTION; + + FUNCTION test_bt(op : uv3; + iozcs : uv5) RETURN boolean IS + BEGIN + CASE op IS + WHEN "000" => -- No branch + RETURN false; + WHEN "001" => -- Branch if positive + RETURN (iozcs(0)='1'); + WHEN "010" => -- Branch if carry + RETURN (iozcs(1)='1'); + WHEN "011" => -- Branch if positive or carry + RETURN (iozcs(0)='1' OR iozcs(1)='1'); + WHEN "100" => -- Branch if zero + RETURN (iozcs(2)='1'); + WHEN "101" => -- Same as T=1 + RETURN (iozcs(0)='1'); + WHEN "110" => -- Branch if zero or carry + RETURN (iozcs(2)='1' OR iozcs(1)='1'); + WHEN OTHERS => -- Same as T=3 + RETURN (iozcs(0)='1' OR iozcs(1)='1'); + END CASE; + END FUNCTION; + + + PROCEDURE aluop(op : IN enum_op; -- ALU operation + code : IN uv8; -- OPCODE + src1 : IN uv8; -- Source Reg 1 / Destination reg + src2 : IN uv8; -- Source Reg 2 + iozcs_i : IN uv5; -- Flags before + dst : OUT uv8; -- Result + dstm : OUT std_logic; -- Modified result reg + iozcs_o : OUT uv5; -- Flags after + test : OUT std_logic) IS -- Contitional branch test result + VARIABLE dst_v : uv8; + VARIABLE dst9_v : uv9; + VARIABLE tc_v,tic_v : boolean; + BEGIN + + iozcs_o:=iozcs_i; + dstm:='0'; + test:='0'; + + CASE op IS + WHEN OP_ADD => -- Binary Add + dst9_v:=('0' & src1) + ('0' & src2); + iozcs_o(0):=NOT dst9_v(7); + iozcs_o(1):=dst9_v(8); + iozcs_o(2):=to_std_logic(dst9_v(7 DOWNTO 0)=x"00"); + iozcs_o(3):=(src1(7) XOR dst9_v(7)) AND (src2(7) XOR dst9_v(7)); + dstm:='1'; + dst_v:=dst9_v(7 DOWNTO 0); + + WHEN OP_ADDD => -- Decimal Add + dst9_v:=('0' & src1) + ('0' & src2); + iozcs_o(0):=NOT dst9_v(7); + iozcs_o(1):=dst9_v(8); + iozcs_o(2):=to_std_logic(dst9_v(7 DOWNTO 0)=x"00"); + iozcs_o(3):=(src1(7) XOR dst9_v(7)) AND (src2(7) XOR dst9_v(7)); + + tc_v :=(((('0' & src1) + ('0' & src2)) AND "111110000") > "011110000"); + tic_v:=(('0' & src1(3 DOWNTO 0)) + ('0' & src2(3 DOWNTO 0))> "01111"); + + dst_v:=src1 + src2; + IF NOT tc_v AND NOT tic_v THEN + dst_v:=((dst_v + x"A0") AND x"F0") + ((dst_v + x"0A") AND x"0F"); + ELSIF NOT tc_v AND tic_v THEN + dst_v:=((dst_v + x"A0") AND x"F0") + (dst_v AND x"0F"); + ELSIF tc_v AND NOT tic_v THEN + dst_v:=(dst_v AND x"F0") + ((dst_v + x"0A") AND x"0F"); + END IF; + dstm:='1'; + + WHEN OP_CMP => -- Compare + dst9_v:=(('0' & NOT src1) + ('0' & src2)) + 1; + iozcs_o(0):=NOT dst9_v(7); + iozcs_o(1):=dst9_v(8); + iozcs_o(2):=to_std_logic(dst9_v(7 DOWNTO 0)=x"00"); + iozcs_o(3):=(NOT src1(7) XOR dst9_v(7)) AND (src2(7) XOR dst9_v(7)); + dstm:='0'; + + WHEN OP_AND => -- AND + dst_v:=src1 AND src2; + iozcs_o(0):=NOT dst_v(7); + iozcs_o(1):='0'; + iozcs_o(2):=to_std_logic(dst_v=x"00"); + iozcs_o(3):='0'; + dstm:='1'; + + WHEN OP_OR => -- OR + dst_v:=src1 OR src2; + iozcs_o(0):=NOT dst_v(7); + iozcs_o(1):='0'; + iozcs_o(2):=to_std_logic(dst_v=x"00"); + iozcs_o(3):='0'; + dstm:='1'; + + WHEN OP_XOR => -- XOR + dst_v:=src1 XOR src2; + iozcs_o(0):=NOT dst_v(7); + iozcs_o(1):='0'; + iozcs_o(2):=to_std_logic(dst_v=x"00"); + iozcs_o(3):='0'; + dstm:='1'; + + WHEN OP_DEC => -- DECREMENT : ADD FF + dst9_v:=('0' & src1) + ('0' & x"FF"); + iozcs_o(0):=NOT dst9_v(7); + iozcs_o(1):=dst9_v(8); + iozcs_o(2):=to_std_logic(dst9_v(7 DOWNTO 0)=x"00"); + iozcs_o(3):=(src1(7) XOR dst9_v(7)) AND (NOT dst9_v(7)); + dstm:='1'; + dst_v:=dst9_v(7 DOWNTO 0); + + WHEN OP_SL1 => -- SHIFT LEFT 1 + dst_v:=src1(6 DOWNTO 0) & '0'; + iozcs_o(0):=NOT dst_v(7); + iozcs_o(1):='0'; + iozcs_o(2):=to_std_logic(dst_v=x"00"); + iozcs_o(3):='0'; + dstm:='1'; + + WHEN OP_SL4 => -- SHIFT LEFT 4 + dst_v:=src1(3 DOWNTO 0) & x"0"; + iozcs_o(0):=NOT dst_v(7); + iozcs_o(1):='0'; + iozcs_o(2):=to_std_logic(dst_v=x"00"); + iozcs_o(3):='0'; + dstm:='1'; + + WHEN OP_SR1 => -- SHIFT RIGHT 1 + dst_v:='0' & src1(7 DOWNTO 1); + iozcs_o(0):=NOT dst_v(7); + iozcs_o(1):='0'; + iozcs_o(2):=to_std_logic(dst_v=x"00"); + iozcs_o(3):='0'; + dstm:='1'; + + WHEN OP_SR4 => -- SHIFT RIGHT 4 + dst_v:=x"0" & src1(7 DOWNTO 4); + iozcs_o(0):=NOT dst_v(7); + iozcs_o(1):='0'; + iozcs_o(2):=to_std_logic(dst_v=x"00"); + iozcs_o(3):='0'; + dstm:='1'; + + WHEN OP_COM => -- COM. Complement + dst_v:=NOT src1; + iozcs_o(0):=NOT dst_v(7); + iozcs_o(1):='0'; + iozcs_o(2):=to_std_logic(dst_v=x"00"); + iozcs_o(3):='0'; + dstm:='1'; + + WHEN OP_LNK => -- LNK. Add carry to acc. + dst9_v:=('0' & src1) + ('0' & iozcs_i(1)); + iozcs_o(0):=NOT dst9_v(7); + iozcs_o(1):=dst9_v(8); + iozcs_o(2):=to_std_logic(dst9_v(7 DOWNTO 0)=x"00"); + iozcs_o(3):=(src1(7) XOR dst9_v(7)) AND dst9_v(7); + dstm:='1'; + dst_v:=dst9_v(7 DOWNTO 0); + + WHEN OP_INC => -- INC Increment + dst9_v:=('0' & src1) + 1; + iozcs_o(0):=NOT dst9_v(7); + iozcs_o(1):=dst9_v(8); + iozcs_o(2):=to_std_logic(dst9_v(7 DOWNTO 0)=x"00"); + iozcs_o(3):=(src1(7) XOR dst9_v(7)) AND dst9_v(7); + dstm:='1'; + dst_v:=dst9_v(7 DOWNTO 0); + + WHEN OP_EDI => -- Enable / Disable ICB + iozcs_o(4):=code(0); + + WHEN OP_LIS => -- Load immediate acc. + dst_v:=x"0" & code(3 DOWNTO 0); + dstm:='1'; + + WHEN OP_TST8 => -- 8x conditional branches + test:=to_std_logic(test_bt(code(2 DOWNTO 0),iozcs_i)); + + WHEN OP_TST9 => -- 9x conditional branches + test:=to_std_logic(test_bf(code(3 DOWNTO 0),iozcs_i)); + dstm:='0'; + + WHEN OP_NOP => + dstm:='0'; + + WHEN OP_MOV => + dst_v:=src2; + dstm:='1'; + + END CASE; + + dst:=dst_v; + END PROCEDURE; + + +END PACKAGE BODY; diff --git a/Console_MiST/ChannelF_MiST/rtl/f8_psu.vhd b/Console_MiST/ChannelF_MiST/rtl/f8_psu.vhd new file mode 100644 index 00000000..cbf2f6e3 --- /dev/null +++ b/Console_MiST/ChannelF_MiST/rtl/f8_psu.vhd @@ -0,0 +1,492 @@ +-------------------------------------------------------------------------------- +-- Fairchild F8 F351 PSU +-------------------------------------------------------------------------------- +-- DO 8/2020 +-------------------------------------------------------------------------------- +-- With help from MAME F8 model + +-- - 1kB ROM +-- - 2 8bits IO port +-- - Programmable timer +-- - Interrupts + +-- MASK OPTIONS +-- - 1k ROM +-- - 6bits page select +-- - 6bits IO port address select +-- - 16bits interrupt address vector +-- - IO port output option + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +USE std.textio.ALL; + +LIBRARY work; +USE work.base_pack.ALL; +USE work.f8_pack.ALL; + +ENTITY f8_psu IS + GENERIC ( + PAGE : uv6; + IOPAGE : uv6; + IVEC : uv16; + ROM : arr_uv8(0 TO 1023) + ); + PORT ( + dw : IN uv8; -- Data Write + dr : OUT uv8; -- Data Read + dv : OUT std_logic; + + romc : IN uv5; + tick : IN std_logic; -- 1/8 or 1/12 cycle lenght + phase : IN uint4; + + ext_int : IN std_logic; + int_req : OUT std_logic; + + pri_o : OUT std_logic; + pri_i : IN std_logic; + + po_a : OUT uv8; -- IO port A + pi_a : IN uv8; + + po_b : OUT uv8; -- IO port B + pi_b : IN uv8; + + load_a : IN uv10; + load_d : IN uv8; + load_wr : IN std_logic; + + clk : IN std_logic; + ce : IN std_logic; + reset_na : IN std_logic + ); +END ENTITY f8_psu; + +ARCHITECTURE rtl OF f8_psu IS + + SIGNAL dc0,dc1 : uv16; + SIGNAL pc0,pc1 : uv16; + + SIGNAL mem : arr_uv8(0 TO 1023) :=ROM; + SIGNAL mem_a : uv16; + SIGNAL mem_dr,mem_dw : uv8; + + SIGNAL io_wr,io_rd : std_logic; + SIGNAL io_port,io_dr,io_dw : uv8; + SIGNAL po_a_l,po_b_l : uv8; + SIGNAL tim : uv8; + SIGNAL tdiv : uint5; + SIGNAL icr : uv2; + + SIGNAL ext_int_d,tim_int_d,tim_int : std_logic; + SIGNAL inta,inta_set,inta_clr : std_logic; + SIGNAL int_req_l : std_logic; + +BEGIN + + mem_a<=dc0 WHEN romc="00010" OR romc="00101" ELSE pc0; + + ---------------------------------------------------------- + -- ROMC BUS + PROCESS(clk,reset_na) IS + FUNCTION pchk(A : uv16) RETURN std_logic IS + BEGIN + RETURN to_std_logic(A(15 DOWNTO 10)=PAGE); + END FUNCTION; + BEGIN + IF rising_edge(clk) THEN + IF ce='1' THEN + --dv<='0'; + inta_clr<='0'; + IF phase=2 THEN + dv<='0'; + END IF; + + io_wr<='0'; + + CASE romc IS + WHEN "00000" => + -- S,L : Instruction fetch. The device whose address space includes + -- the content of the PC0 register must place on the data bus + -- the op code addressed by PC0. Then all devices increment + -- the contents of PC0. + IF phase=2 THEN + dr <= mem_dr; + dv <= pchk(pc0); + END IF; + IF phase=6 THEN + pc0<= pc0 + 1; + END IF; + + WHEN "00001" => + -- L : The device whose address space includes the contents of + -- the PC0 register must place on the data bus the contents of + -- the memory location addressed by PC0. Then all devices add the + -- 8-bit value on the data bus, as a signed binary number, to PC0. + IF phase=2 THEN + dr <= mem_dr; + dv <= pchk(pc0); + END IF; + IF phase=6 THEN + pc0<= pc0 + sext(dw,16); + END IF; + + WHEN "00010" => + -- L : The device whose DC0 addresses a memory word within the + -- address space of that device must place on the data bus the + -- contents of the memory location addressed by + -- DC0. Then all devices increment DC0. + IF phase=2 THEN + dr <= mem_dr; + dv <= pchk(dc0); + END IF; + IF phase=6 THEN + dc0<= dc0 + 1; + END IF; + + WHEN "00011" => + -- L,S : Similar to 00, except that it is used for Immediate Operand + -- fetches (using PC0) instead of instruction fetches. + IF phase=2 THEN + dr <= mem_dr; + dv <= pchk(pc0); + END IF; + IF phase=6 THEN + pc0<= pc0 + 1; + io_port<=dw; + END IF; + + WHEN "00100" => + -- S : Copy the contents of PC1 into PC0. + IF phase=6 THEN + pc0<= pc1; + END IF; + + WHEN "00101" => + -- L : Store the data bus contents into the memory + -- location pointed to by DC0. Increment DC0. + -- + --mem_a<=dc0; + --IF phase=4 AND pchk(dc0)='1' THEN + -- mem_wr<='1'; + --END IF; + --IF phase=6 THEN + -- dc0<=dc0 + 1; + --END IF; + + WHEN "00110" => + -- L : Place the high order byte of DC0 on the data bus. + dr <=dc0(15 DOWNTO 8); + IF phase=2 THEN + dv <='1'; + END IF; + + WHEN "00111" => + -- L : Place the high order byte of PC1 on the data bus. + IF phase=2 THEN + dr <=pc1(15 DOWNTO 8); + dv <='1'; + END IF; + + WHEN "01000" => + -- L : All devices copy the contents of PC0 into PC1. The CPU + -- outputs zero on the data bus in this ROMC state. Load the + -- data bus into both halves of PC0 thus clearing the register. + IF phase=6 THEN + pc1<=pc0; + pc0<=x"0000"; + END IF; + + WHEN "01001" => + -- The device whose address space includes the contents of the DC0 + -- register must place the low order byte of DC0 onto the data bus. + IF phase=2 THEN + dr <=dc0(7 DOWNTO 0); + dv <=pchk(dc0); + END IF; + + WHEN "01010" => + -- L : All devices add the 8-bit value on the data bus, treated + -- as a signed binary number, to the Data Counter. + IF phase=6 THEN + dc0<=dc0 + sext(dw,16); + END IF; + + WHEN "01011" => + -- L : The device whose address space includes the value in PC1 + -- must place the low order byte of PC1 on the data bus. + IF phase=2 THEN + dr <=pc1(7 DOWNTO 0); + dv <=pchk(pc1); + END IF; + + WHEN "01100" => + -- L : The device whose address space includes the contents of + -- the PC0 register must place the contents of the memory word + -- addressed by PC0 onto the data bus. Then all devices move the + -- value which has just been placed on the data bus into the low + -- order byte of PC0. + IF phase=2 THEN + dr <= mem_dr; + dv <= pchk(pc0); + END IF; + IF phase=6 THEN + pc0(7 DOWNTO 0)<= dw; + END IF; + + WHEN "01101" => + -- S : All devices store in PC1 the current contents of PC0, + -- incremented by 1. PC0 is unaltered. + pc1 <= pc0 +1; + + WHEN "01110" => + -- L : The device whose address space includes the contents of + -- PC0 must place the contents of the word addressed by PC0 + -- onto the data bus. The value on the data bus is then + -- moved to the low order byte of DC0 by all devices + IF phase=2 THEN + dr <= mem_dr; + dv <= pchk(pc0); + END IF; + IF phase=6 THEN + dc0(7 DOWNTO 0)<= dw; + END IF; + + WHEN "01111" => + -- L : The interrupting device with highest priority must place + -- the low order byte of the interrupt vector on the data bus. + -- All devices must copy the contents of PC0 into PC1. + -- All devices must move the contents of the data bus into + -- the low order byte of PC0. + IF phase=2 THEN + dr <=IVEC(7 DOWNTO 0); + dv <=int_req_l; + END IF; + IF phase=6 THEN + pc1 <= pc0; + pc0(7 DOWNTO 0) <= dw; + END IF; + + WHEN "10000" => + -- L : Inhibit any modification to the interrupt priority logic. + -- + + WHEN "10001" => + -- L : The device whose memory space includes the contents of + -- PC0 must place the contents of the addressed memory word + -- on the data bus. All devices must then move the contents + -- of the data bus to the upper byte of DC0. + IF phase=2 THEN + dr <=mem_dr; + dv <=pchk(pc0); + END IF; + IF phase=6 THEN + dc0(15 DOWNTO 8)<=dw; + END IF; + + WHEN "10010" => + -- L : All devices copy the contents of PC0 into PC1. All + -- devices then move the contents of the data bus into + -- the low order byte of PC0. + IF phase=6 THEN + pc1<=pc0; + pc0(7 DOWNTO 0)<=dw; + END IF; + + WHEN "10011" => + -- L : The interrupting device with highest priority must move + -- the high order half of the interrupt vector onto the data bus. + -- All devices must move the contents of the data bus into the + -- high order byte of PC0. The interrupting device will request + -- its interrupt circuitry (so that it is no longer requesting CPU + -- servicing and can respond to another interrupt). + IF phase=2 THEN + dr <=IVEC(15 DOWNTO 8); + dv <=int_req_l; + END IF; + IF phase=6 THEN + pc0(15 DOWNTO 8) <= dw; + inta_clr<=int_req_l; + END IF; + + WHEN "10100" => + -- L : All devices move the contents of the data bus into the + -- high order byte of PC0. + IF phase=6 THEN + pc0(15 DOWNTO 8)<=dw; + END IF; + + WHEN "10101" => + -- L : All devices move contents of the data bus into the + -- high order byte of PC1. + IF phase=6 THEN + pc1(15 DOWNTO 8)<=dw; + END IF; + + WHEN "10110" => + -- L : All devices move the contents of the data bus into the + -- high order byte of DC0. + IF phase=6 THEN + dc0(15 DOWNTO 8)<=dw; + END IF; + + WHEN "10111" => + -- L : All devices move the contents of the data bus into the + -- low order byte of PC0. + IF phase=6 THEN + pc0(7 DOWNTO 0)<=dw; + END IF; + + WHEN "11000" => + -- L : All devices move contents of the data bus into the low + -- order byte of PC1. + IF phase=6 THEN + pc1(7 DOWNTO 0)<=dw; + END IF; + + WHEN "11001" => + -- L : All devices move contents of the data bus into the low + -- order byte of DC0. + IF phase=6 THEN + dc0(7 DOWNTO 0)<=dw; + END IF; + + WHEN "11010" => + -- L : During the prior cycle an I/O port timer or interrupt + -- control register was addressed, The device containing + -- the addressed port must move the current contents of + -- the data bus into the addressed port. + IF phase=6 THEN + io_dw<=dw; + io_wr<=to_std_logic(io_port(7 DOWNTO 2)=IOPAGE); + END IF; + + WHEN "11011" => + -- L : During the prior cycle the data bus specified the + -- address of an I/O port. The device containing the + -- addressed I/O port must place the contents of the I/O + -- port on the data bus. (Note that the contents of timer + -- and interrupt control retgisters cannot be read back onto + -- the data bus.) + IF phase=6 THEN + io_rd<=to_std_logic(io_port(7 DOWNTO 2)=IOPAGE); + dr<=io_dr; + dv<=to_std_logic(io_port(7 DOWNTO 2)=IOPAGE); + END IF; + + WHEN "11100" => + -- L/S : None. Before IO port access + IF phase=6 THEN + io_port<=dw; + END IF; + + WHEN "11101" => + -- S : Devices with DC0 and DC1 registers must switch registers. + -- Devices without a DC1 register perform no operation. + IF phase=6 THEN + dc0<=dc1; + dc1<=dc0; + END IF; + + WHEN "11110" => + -- L : The device whose address space includes the contents of + -- PC0 must place the low order byte of PC0 onto the data bus. + IF phase=2 THEN + dr <=pc0(7 DOWNTO 0); + dv <=pchk(pc0); + END IF; + + WHEN "11111" => + -- L : The device whose address space includes the contents of + -- PC0 must place the high order byte of PC0 on the data bus. + IF phase=2 THEN + dr <=pc0(15 DOWNTO 8); + dv <=pchk(pc0); + END IF; + + WHEN OTHERS => + NULL; + + END CASE; + END IF; + END IF; + END PROCESS; + + ---------------------------------------------------------- + -- ROM READ + + PROCESS(clk) IS + BEGIN + IF rising_edge(clk) THEN + IF ce='1' THEN + mem_dr<=mem(to_integer(mem_a(9 DOWNTO 0))); + END IF; + + IF load_wr='1' THEN + mem(to_integer(load_a))<=load_d; + END IF; + END IF; + END PROCESS; + + ---------------------------------------------------------- + -- IO PORTS + + po_a<=po_a_l; + po_b<=po_b_l; + int_req<=int_req_l; + + PROCESS(clk,reset_na) IS + BEGIN + IF rising_edge(clk) THEN + IF ce='1' THEN + ------------------------------- + -- LFSR TIMER + tdiv<=(tdiv+1) MOD 32; + IF tdiv=0 THEN + tim(0)<=(tim(3) XOR tim(4)) XNOR (tim(5) XOR tim(7)); + tim(7 DOWNTO 1)<=tim(6 DOWNTO 0); + END IF; + tim_int<=to_std_logic(tim=x"FE"); + tim_int_d<=tim_int; + + -- Interrupts + ext_int_d<=ext_int; + + inta_set<=(NOT ext_int_d AND ext_int AND to_std_logic(icr="01")) OR + (NOT tim_int_d AND tim_int AND to_std_logic(icr="11")); + + inta <=(inta OR inta_set) AND NOT inta_clr; + + int_req_l<=inta AND pri_i; + pri_o<=pri_i AND NOT inta; + + ------------------------------- + CASE io_port(1 DOWNTO 0) IS + WHEN "00" => -- IO PORT A READ + io_dr<=pi_a AND po_a_l; + WHEN "01" => -- IO PORT B READ + io_dr<=pi_b AND po_b_l; + WHEN "10" => -- Interrupt control bits + io_dr<=x"00"; -- + WHEN OTHERS => -- Timer + io_dr<=x"00"; -- + END CASE; + + IF io_wr='1' THEN + CASE io_port(1 DOWNTO 0) IS + WHEN "00" => po_a_l<=io_dw; + WHEN "01" => po_b_l<=io_dw; + WHEN "10" => tim<=io_dw; + WHEN OTHERS => icr<=io_dw(1 DOWNTO 0); + END CASE; + END IF; + + ------------------------------- + END IF; + END IF; + END PROCESS; + +END ARCHITECTURE rtl; diff --git a/Console_MiST/ChannelF_MiST/rtl/ovo.vhd b/Console_MiST/ChannelF_MiST/rtl/ovo.vhd new file mode 100644 index 00000000..2130eac8 --- /dev/null +++ b/Console_MiST/ChannelF_MiST/rtl/ovo.vhd @@ -0,0 +1,180 @@ +-------------------------------------------------------------------------------- +-- Overlay +-------------------------------------------------------------------------------- +-- DO 10/2017 +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY work; +USE work.base_pack.ALL; + +ENTITY ovo IS + GENERIC ( + COLS : natural :=32; + LINES : natural :=2; + RGB : unsigned(23 DOWNTO 0) :=x"FFFFFF"); + PORT ( + -- VGA IN + i_r : IN uv8; + i_g : IN uv8; + i_b : IN uv8; + i_hs : IN std_logic; + i_vs : IN std_logic; + i_de : IN std_logic; + i_en : IN std_logic; + i_clk : IN std_logic; + + -- VGA_OUT + o_r : OUT uv8; + o_g : OUT uv8; + o_b : OUT uv8; + o_hs : OUT std_logic; + o_vs : OUT std_logic; + o_de : OUT std_logic; + + -- Control + ena : IN std_logic; -- Overlay ON/OFF + + -- Probes + in0 : IN unsigned(0 TO COLS*5-1); + in1 : IN unsigned(0 TO COLS*5-1) + ); +END ENTITY ovo; + +--############################################################################## + +ARCHITECTURE rtl OF ovo IS + TYPE arr_slv8 IS ARRAY (natural RANGE <>) OF uv8; + CONSTANT chars : arr_slv8 :=( + x"3E", x"63", x"73", x"7B", x"6F", x"67", x"3E", x"00", -- 0 + x"0C", x"0E", x"0C", x"0C", x"0C", x"0C", x"3F", x"00", -- 1 + x"1E", x"33", x"30", x"1C", x"06", x"33", x"3F", x"00", -- 2 + x"1E", x"33", x"30", x"1C", x"30", x"33", x"1E", x"00", -- 3 + x"38", x"3C", x"36", x"33", x"7F", x"30", x"78", x"00", -- 4 + x"3F", x"03", x"1F", x"30", x"30", x"33", x"1E", x"00", -- 5 + x"1C", x"06", x"03", x"1F", x"33", x"33", x"1E", x"00", -- 6 + x"3F", x"33", x"30", x"18", x"0C", x"0C", x"0C", x"00", -- 7 + x"1E", x"33", x"33", x"1E", x"33", x"33", x"1E", x"00", -- 8 + x"1E", x"33", x"33", x"3E", x"30", x"18", x"0E", x"00", -- 9 + x"0C", x"1E", x"33", x"33", x"3F", x"33", x"33", x"00", -- A + x"3F", x"66", x"66", x"3E", x"66", x"66", x"3F", x"00", -- B + x"3C", x"66", x"03", x"03", x"03", x"66", x"3C", x"00", -- C + x"1F", x"36", x"66", x"66", x"66", x"36", x"1F", x"00", -- D + x"7F", x"46", x"16", x"1E", x"16", x"46", x"7F", x"00", -- E + x"7F", x"46", x"16", x"1E", x"16", x"06", x"0F", x"00", -- F + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", --' ' 10 + x"00", x"00", x"3F", x"00", x"00", x"3F", x"00", x"00", -- = 11 + x"00", x"0C", x"0C", x"3F", x"0C", x"0C", x"00", x"00", -- + 12 + x"00", x"00", x"00", x"3F", x"00", x"00", x"00", x"00", -- - 13 + x"18", x"0C", x"06", x"03", x"06", x"0C", x"18", x"00", -- < 14 + x"06", x"0C", x"18", x"30", x"18", x"0C", x"06", x"00", -- > 15 + x"08", x"1C", x"36", x"63", x"41", x"00", x"00", x"00", -- ^ 16 + x"08", x"1C", x"36", x"63", x"41", x"00", x"00", x"00", -- v 17 + x"18", x"0C", x"06", x"06", x"06", x"0C", x"18", x"00", -- ( 18 + x"06", x"0C", x"18", x"18", x"18", x"0C", x"06", x"00", -- ) 19 + x"00", x"0C", x"0C", x"00", x"00", x"0C", x"0C", x"00", -- : 1A + x"00", x"00", x"00", x"00", x"00", x"0C", x"0C", x"00", -- . 1B + x"00", x"00", x"00", x"00", x"00", x"0C", x"0C", x"06", -- , 1C + x"1E", x"33", x"30", x"18", x"0C", x"00", x"0C", x"00", -- ? 1D + x"18", x"18", x"18", x"00", x"18", x"18", x"18", x"00", -- | 1E + x"36", x"36", x"7F", x"36", x"7F", x"36", x"36", x"00"); -- # 1F + + SIGNAL vcpt,hcpt,hcpt2 : natural RANGE 0 TO 4095; + SIGNAL vin0,vin1 : unsigned(0 TO COLS*5-1); + + SIGNAL t_r,t_g,t_b : uv8; + SIGNAL t_hs,t_vs,t_de : std_logic; + + SIGNAL col : uv8; + SIGNAL de : std_logic; + + SIGNAL in0s,in1s : unsigned(in0'range); +BEGIN + + in0s<=in0 WHEN rising_edge(i_clk); + in1s<=in1 WHEN rising_edge(i_clk); + + ---------------------------------------------------------- + Megamix:PROCESS(i_clk) IS + VARIABLE vin_v : unsigned(0 TO 32*5-1); + VARIABLE char_v : unsigned(4 DOWNTO 0); + BEGIN + IF rising_edge(i_clk) THEN + IF i_en='1' THEN + ---------------------------------- + -- Propagate VGA signals. 2 cycles delay + t_r<=i_r; + t_g<=i_g; + t_b<=i_b; + t_hs<=i_hs; + t_vs<=i_vs; + t_de<=i_de; + + o_r<=t_r; + o_g<=t_g; + o_b<=t_b; + o_hs<=t_hs; + o_vs<=t_vs; + o_de<=t_de; + + ---------------------------------- + -- Latch sampled values during vertical sync + IF i_vs='1' THEN + vin0<=in0s; + vin1<=in1s; + END IF; + + ---------------------------------- + IF i_vs='1' THEN + vcpt<=0; + de<='0'; + ELSIF i_hs='1' AND t_hs='0' AND de='1' THEN + vcpt<=(vcpt+1) MOD 4096; + END IF; + + ---------------------------------- + IF (vcpt/8) MOD 2=0 THEN + vin_v:=vin0; + ELSE + vin_v:=vin1; + END IF; + + IF i_hs='1' THEN + hcpt<=0; + ELSIF i_de='1' THEN + hcpt<=(hcpt+1) MOD 4096; + de<='1'; + END IF; + hcpt2<=hcpt; + + ---------------------------------- + -- Pick characters + IF hcpt) OF unsigned(7 DOWNTO 0); + + CONSTANT INIT_SL31253 : arr8 := ( + x"70",x"0B",x"70",x"5C",x"0A",x"1F",x"25",x"40",x"94",x"F8",x"67",x"6B",x"20",x"28",x"5C",x"2A", + x"08",x"00",x"16",x"25",x"55",x"94",x"04",x"29",x"08",x"02",x"20",x"D6",x"53",x"28",x"00",x"D0", + x"20",x"4A",x"50",x"28",x"00",x"99",x"63",x"6C",x"74",x"5C",x"44",x"6F",x"5C",x"25",x"03",x"91", + x"F0",x"28",x"01",x"35",x"28",x"02",x"24",x"28",x"00",x"88",x"28",x"02",x"DA",x"28",x"00",x"88", + x"28",x"02",x"E8",x"28",x"00",x"88",x"21",x"04",x"84",x"07",x"28",x"03",x"8C",x"28",x"03",x"99", + x"28",x"06",x"58",x"28",x"04",x"67",x"28",x"03",x"D3",x"63",x"6F",x"4C",x"25",x"02",x"94",x"04", + x"28",x"04",x"47",x"64",x"6F",x"4C",x"1F",x"5C",x"70",x"B0",x"A0",x"21",x"04",x"94",x"04",x"28", + x"02",x"24",x"63",x"6C",x"2A",x"00",x"83",x"4C",x"12",x"8E",x"16",x"55",x"28",x"00",x"8F",x"70", + x"B5",x"90",x"B5",x"22",x"13",x"07",x"03",x"03",x"64",x"6E",x"4E",x"51",x"4C",x"50",x"1C",x"20", + x"FF",x"56",x"36",x"94",x"FE",x"35",x"94",x"F8",x"1C",x"08",x"28",x"01",x"07",x"20",x"33",x"51", + x"20",x"13",x"52",x"28",x"06",x"79",x"20",x"8B",x"50",x"28",x"06",x"79",x"28",x"00",x"C1",x"20", + x"33",x"51",x"20",x"13",x"52",x"7D",x"50",x"28",x"06",x"79",x"28",x"06",x"79",x"28",x"01",x"1E", + x"0C",x"A0",x"18",x"21",x"0F",x"84",x"FB",x"54",x"20",x"FF",x"55",x"35",x"94",x"FE",x"90",x"C0", + x"08",x"28",x"01",x"07",x"70",x"52",x"20",x"7E",x"51",x"43",x"22",x"10",x"50",x"28",x"06",x"79", + x"75",x"51",x"7D",x"50",x"28",x"06",x"79",x"31",x"41",x"25",x"70",x"81",x"F6",x"42",x"24",x"05", + x"52",x"63",x"6F",x"73",x"FC",x"84",x"08",x"42",x"25",x"30",x"81",x"DB",x"70",x"53",x"42",x"25", + x"40",x"81",x"D4",x"28",x"01",x"1E",x"0C",x"0A",x"57",x"67",x"6B",x"4C",x"0B",x"00",x"5C",x"0A", + x"1F",x"0B",x"01",x"5C",x"0A",x"1F",x"0B",x"0A",x"67",x"6B",x"5C",x"47",x"0B",x"1C",x"0A",x"57", + x"67",x"6B",x"4C",x"24",x"FF",x"0B",x"4C",x"05",x"0A",x"24",x"FF",x"0B",x"4C",x"04",x"0A",x"67", + x"6B",x"5C",x"47",x"0B",x"1C",x"08",x"28",x"01",x"07",x"63",x"6F",x"4C",x"64",x"6D",x"25",x"01", + x"84",x"0E",x"20",x"53",x"5D",x"7C",x"5E",x"20",x"D0",x"53",x"28",x"00",x"D0",x"90",x"2F",x"20", + x"17",x"5D",x"20",x"FF",x"5C",x"20",x"D6",x"53",x"28",x"00",x"D0",x"20",x"11",x"51",x"78",x"52", + x"28",x"01",x"F6",x"20",x"11",x"51",x"20",x"25",x"52",x"28",x"01",x"F6",x"20",x"5C",x"51",x"78", + x"52",x"28",x"01",x"F6",x"20",x"5C",x"51",x"20",x"25",x"52",x"28",x"01",x"F6",x"20",x"14",x"51", + x"76",x"52",x"28",x"02",x"0E",x"20",x"14",x"51",x"20",x"2E",x"52",x"28",x"02",x"0E",x"20",x"99", + x"62",x"6E",x"5D",x"5C",x"28",x"02",x"AC",x"28",x"02",x"B5",x"64",x"6A",x"72",x"5C",x"90",x"05", + x"08",x"28",x"01",x"07",x"62",x"68",x"20",x"17",x"5C",x"6B",x"5C",x"20",x"1C",x"51",x"20",x"1A", + x"52",x"20",x"B0",x"50",x"28",x"06",x"79",x"20",x"38",x"51",x"20",x"1B",x"52",x"20",x"55",x"50", + x"28",x"06",x"79",x"20",x"52",x"51",x"20",x"1A",x"52",x"20",x"71",x"50",x"28",x"06",x"79",x"64", + x"6D",x"4C",x"13",x"81",x"06",x"28",x"04",x"47",x"90",x"19",x"20",x"11",x"51",x"20",x"1A",x"52", + x"20",x"B2",x"50",x"28",x"06",x"79",x"20",x"5E",x"51",x"20",x"1A",x"52",x"20",x"73",x"50",x"28", + x"06",x"79",x"28",x"01",x"1E",x"0C",x"08",x"28",x"01",x"07",x"78",x"53",x"20",x"81",x"50",x"28", + x"06",x"79",x"41",x"24",x"FA",x"51",x"42",x"1F",x"52",x"33",x"94",x"F1",x"90",x"E5",x"08",x"28", + x"01",x"07",x"20",x"46",x"53",x"20",x"92",x"50",x"28",x"06",x"79",x"41",x"24",x"FB",x"51",x"33", + x"94",x"F4",x"90",x"CF",x"08",x"28",x"01",x"07",x"20",x"85",x"50",x"28",x"00",x"99",x"44",x"25", + x"08",x"94",x"05",x"28",x"01",x"1E",x"0C",x"25",x"02",x"94",x"0D",x"20",x"8E",x"50",x"28",x"00", + x"99",x"63",x"6C",x"44",x"5C",x"90",x"E2",x"25",x"01",x"94",x"DE",x"20",x"8C",x"50",x"28",x"00", + x"99",x"2A",x"02",x"6C",x"44",x"12",x"8E",x"16",x"67",x"69",x"5D",x"70",x"5C",x"66",x"6F",x"7F", + x"5C",x"28",x"02",x"71",x"64",x"6D",x"4C",x"22",x"20",x"5C",x"90",x"BD",x"02",x"05",x"10",x"10", + x"20",x"08",x"28",x"01",x"07",x"67",x"6A",x"4E",x"54",x"4C",x"53",x"14",x"22",x"80",x"50",x"20", + x"2A",x"51",x"20",x"33",x"52",x"28",x"06",x"79",x"43",x"21",x"0F",x"22",x"80",x"50",x"28",x"06", + x"79",x"20",x"91",x"50",x"28",x"06",x"79",x"44",x"14",x"22",x"80",x"50",x"28",x"06",x"79",x"44", + x"21",x"0F",x"22",x"80",x"50",x"28",x"06",x"79",x"28",x"01",x"1E",x"0C",x"08",x"28",x"01",x"07", + x"6E",x"20",x"17",x"90",x"08",x"08",x"28",x"01",x"07",x"6F",x"20",x"50",x"62",x"51",x"20",x"33", + x"52",x"71",x"24",x"66",x"DC",x"5C",x"14",x"22",x"40",x"50",x"28",x"06",x"79",x"4C",x"21",x"0F", + x"22",x"40",x"50",x"28",x"06",x"79",x"28",x"01",x"1E",x"0C",x"08",x"28",x"01",x"07",x"20",x"B0", + x"54",x"62",x"69",x"70",x"B4",x"A4",x"90",x"0D",x"08",x"28",x"01",x"07",x"20",x"71",x"54",x"62", + x"6C",x"70",x"B1",x"A1",x"18",x"F1",x"50",x"4D",x"51",x"4C",x"52",x"71",x"F0",x"84",x"05",x"41", + x"24",x"02",x"51",x"72",x"F0",x"84",x"05",x"41",x"24",x"FE",x"51",x"74",x"F0",x"84",x"05",x"42", + x"24",x"02",x"52",x"78",x"F0",x"84",x"05",x"42",x"24",x"FE",x"52",x"63",x"6F",x"4C",x"25",x"02", + x"91",x"36",x"94",x"17",x"71",x"F4",x"94",x"0B",x"41",x"25",x"2D",x"81",x"04",x"20",x"2D",x"51", + x"90",x"09",x"41",x"25",x"3D",x"91",x"04",x"20",x"3D",x"51",x"41",x"25",x"52",x"81",x"04",x"20", + x"52",x"51",x"25",x"1A",x"91",x"04",x"20",x"1A",x"51",x"42",x"25",x"2B",x"81",x"04",x"20",x"2B", + x"52",x"25",x"09",x"91",x"03",x"79",x"52",x"64",x"6F",x"4C",x"21",x"03",x"25",x"03",x"94",x"24", + x"62",x"68",x"71",x"F4",x"84",x"02",x"6B",x"20",x"10",x"F0",x"84",x"02",x"3C",x"20",x"20",x"F0", + x"84",x"04",x"4C",x"1F",x"5C",x"4C",x"25",x"16",x"94",x"03",x"20",x"1D",x"25",x"1E",x"94",x"03", + x"20",x"17",x"5C",x"44",x"50",x"28",x"06",x"79",x"28",x"01",x"1E",x"0C",x"08",x"28",x"01",x"07", + x"68",x"20",x"B2",x"53",x"70",x"B4",x"A4",x"90",x"0C",x"08",x"28",x"01",x"07",x"6A",x"20",x"73", + x"53",x"70",x"B1",x"A1",x"18",x"50",x"63",x"4D",x"51",x"4C",x"52",x"40",x"21",x"80",x"84",x"05", + x"42",x"24",x"02",x"52",x"40",x"21",x"40",x"84",x"03",x"32",x"32",x"42",x"25",x"14",x"91",x"04", + x"20",x"14",x"52",x"25",x"20",x"81",x"04",x"20",x"20",x"52",x"43",x"50",x"28",x"06",x"79",x"28", + x"01",x"1E",x"0C",x"08",x"28",x"01",x"07",x"64",x"68",x"4D",x"51",x"4D",x"52",x"4D",x"53",x"4D", + x"54",x"4C",x"25",x"00",x"84",x"0D",x"70",x"5C",x"43",x"13",x"C3",x"C3",x"53",x"44",x"13",x"C4", + x"C4",x"54",x"41",x"C3",x"51",x"42",x"C4",x"52",x"64",x"6D",x"20",x"44",x"FC",x"84",x"3D",x"28"); + + CONSTANT INIT_SL31254 : arr8 := ( + x"04",x"9C",x"64",x"6A",x"41",x"50",x"25",x"5C",x"81",x"07",x"28",x"04",x"3F",x"20",x"5C",x"51", + x"41",x"50",x"25",x"14",x"91",x"07",x"28",x"04",x"3F",x"20",x"14",x"51",x"6B",x"42",x"50",x"25", + x"08",x"91",x"07",x"28",x"04",x"3F",x"20",x"09",x"52",x"42",x"50",x"25",x"2E",x"81",x"07",x"28", + x"04",x"3F",x"20",x"2E",x"52",x"20",x"55",x"50",x"28",x"06",x"79",x"28",x"01",x"1E",x"0C",x"4C", + x"18",x"1F",x"5C",x"20",x"40",x"B5",x"1C",x"08",x"28",x"01",x"07",x"20",x"36",x"51",x"7A",x"52", + x"75",x"54",x"20",x"81",x"50",x"28",x"06",x"79",x"41",x"24",x"FA",x"51",x"42",x"24",x"08",x"52", + x"34",x"94",x"F0",x"28",x"01",x"1E",x"0C",x"08",x"28",x"01",x"07",x"67",x"68",x"4C",x"22",x"00", + x"84",x"27",x"70",x"5C",x"6A",x"71",x"50",x"18",x"DC",x"24",x"66",x"D0",x"5C",x"25",x"99",x"94", + x"15",x"20",x"59",x"5E",x"71",x"50",x"18",x"DC",x"24",x"66",x"D0",x"25",x"99",x"94",x"06",x"28", + x"02",x"24",x"90",x"05",x"5C",x"28",x"02",x"71",x"28",x"01",x"1E",x"0C",x"08",x"28",x"01",x"07", + x"64",x"6F",x"71",x"FC",x"84",x"13",x"62",x"6C",x"28",x"05",x"FC",x"30",x"84",x"3B",x"62",x"69", + x"28",x"05",x"FC",x"30",x"84",x"30",x"90",x"11",x"62",x"69",x"28",x"05",x"FC",x"30",x"84",x"26", + x"62",x"6C",x"28",x"05",x"FC",x"30",x"84",x"21",x"64",x"6D",x"4C",x"21",x"04",x"94",x"04",x"29", + x"05",x"9D",x"63",x"68",x"28",x"05",x"FC",x"30",x"84",x"7C",x"63",x"6A",x"28",x"05",x"FC",x"30", + x"84",x"78",x"29",x"05",x"88",x"68",x"90",x"02",x"6B",x"62",x"4D",x"54",x"4D",x"4C",x"57",x"64", + x"6D",x"4C",x"13",x"44",x"81",x"21",x"2A",x"05",x"0E",x"77",x"54",x"37",x"37",x"44",x"C7",x"53", + x"42",x"18",x"1F",x"C3",x"84",x"04",x"34",x"81",x"F5",x"44",x"8E",x"16",x"90",x"0B",x"04",x"04", + x"05",x"06",x"00",x"01",x"02",x"03",x"24",x"E9",x"2A",x"05",x"47",x"13",x"8E",x"16",x"55",x"16", + x"56",x"64",x"6A",x"4C",x"22",x"00",x"91",x"13",x"45",x"18",x"1F",x"55",x"6D",x"4C",x"13",x"6A", + x"91",x"05",x"46",x"18",x"1F",x"56",x"41",x"24",x"02",x"51",x"45",x"5D",x"46",x"5D",x"72",x"5C", + x"20",x"80",x"B5",x"28",x"01",x"1E",x"0C",x"02",x"00",x"02",x"01",x"02",x"02",x"01",x"02",x"01", + x"FE",x"02",x"FE",x"02",x"FF",x"71",x"53",x"90",x"03",x"72",x"53",x"64",x"6A",x"4C",x"33",x"84", + x"07",x"22",x"00",x"81",x"07",x"90",x"08",x"22",x"00",x"81",x"04",x"18",x"1F",x"5C",x"20",x"80", + x"B5",x"6B",x"4C",x"22",x"00",x"94",x"10",x"62",x"69",x"4C",x"21",x"01",x"84",x"04",x"72",x"90", + x"03",x"20",x"FE",x"64",x"6B",x"5C",x"90",x"6C",x"42",x"25",x"14",x"81",x"0E",x"25",x"24",x"91", + x"0A",x"41",x"25",x"14",x"81",x"14",x"25",x"5C",x"91",x"10",x"29",x"05",x"43",x"41",x"25",x"14", + x"81",x"08",x"25",x"5C",x"91",x"04",x"29",x"05",x"43",x"64",x"6A",x"4D",x"13",x"91",x"05",x"24", + x"02",x"90",x"03",x"24",x"FE",x"C1",x"51",x"6B",x"4C",x"C2",x"52",x"20",x"55",x"50",x"28",x"06", + x"79",x"64",x"6B",x"70",x"5C",x"64",x"68",x"4C",x"25",x"30",x"91",x"06",x"28",x"02",x"B5",x"90", + x"04",x"28",x"02",x"AC",x"20",x"FF",x"55",x"28",x"00",x"8F",x"63",x"6F",x"4C",x"25",x"02",x"94", + x"10",x"62",x"6E",x"4D",x"25",x"15",x"84",x"06",x"4C",x"25",x"15",x"94",x"04",x"28",x"02",x"24", + x"28",x"01",x"A0",x"28",x"01",x"1E",x"28",x"01",x"1E",x"29",x"00",x"37",x"08",x"28",x"01",x"07", + x"4C",x"18",x"1F",x"C1",x"91",x"0B",x"4C",x"24",x"05",x"56",x"41",x"18",x"1F",x"CC",x"81",x"17", + x"4C",x"18",x"1F",x"56",x"41",x"24",x"02",x"C6",x"91",x"36",x"41",x"24",x"02",x"18",x"1F",x"56", + x"4C",x"24",x"05",x"C6",x"91",x"2A",x"4D",x"4C",x"18",x"1F",x"56",x"42",x"C6",x"91",x"0B",x"42", + x"18",x"1F",x"56",x"4C",x"24",x"05",x"C6",x"81",x"1D",x"4C",x"18",x"1F",x"56",x"42",x"24",x"02", + x"C6",x"91",x"0D",x"42",x"24",x"02",x"18",x"1F",x"56",x"4C",x"24",x"05",x"C6",x"81",x"07",x"70", + x"50",x"28",x"01",x"1E",x"0C",x"71",x"90",x"F9",x"2A",x"06",x"74",x"64",x"6D",x"4C",x"21",x"20", + x"84",x"12",x"66",x"6F",x"3C",x"94",x"0D",x"63",x"6C",x"4C",x"12",x"8E",x"16",x"66",x"6F",x"5D", + x"67",x"71",x"5C",x"1C",x"09",x"0D",x"15",x"1C",x"1C",x"2A",x"07",x"67",x"08",x"28",x"01",x"07", + x"0A",x"66",x"6C",x"5D",x"43",x"5D",x"44",x"5C",x"75",x"54",x"20",x"C0",x"F0",x"53",x"20",x"3F", + x"F0",x"50",x"25",x"15",x"94",x"1F",x"64",x"68",x"72",x"54",x"28",x"06",x"EC",x"20",x"15",x"50", + x"28",x"07",x"18",x"41",x"24",x"06",x"51",x"66",x"6D",x"4D",x"53",x"4C",x"54",x"6C",x"4C",x"0B", + x"28",x"01",x"1E",x"0C",x"25",x"30",x"94",x"0B",x"62",x"69",x"28",x"06",x"EC",x"68",x"4D",x"50", + x"90",x"DF",x"25",x"31",x"94",x"0B",x"62",x"6C",x"28",x"06",x"EC",x"6B",x"4D",x"50",x"90",x"D1", + x"25",x"32",x"94",x"0B",x"63",x"68",x"28",x"06",x"EC",x"20",x"14",x"50",x"90",x"C3",x"25",x"33", + x"94",x"BF",x"63",x"6A",x"28",x"06",x"EC",x"20",x"14",x"50",x"90",x"B5",x"08",x"28",x"01",x"07", + x"4C",x"E1",x"94",x"06",x"4D",x"4E",x"E2",x"84",x"1C",x"41",x"55",x"42",x"56",x"4C",x"51",x"45", + x"5D",x"4C",x"52",x"46",x"5E",x"7D",x"50",x"2A",x"07",x"67",x"28",x"07",x"18",x"2A",x"07",x"67", + x"4D",x"51",x"4E",x"52",x"28",x"01",x"1E",x"0C",x"40",x"13",x"8E",x"C0",x"8E",x"20",x"40",x"B0", + x"44",x"56",x"55",x"16",x"57",x"42",x"24",x"00",x"18",x"21",x"3F",x"58",x"A5",x"21",x"C0",x"C8", + x"B5",x"41",x"24",x"FC",x"18",x"B4",x"47",x"22",x"00",x"43",x"91",x"02",x"70",x"18",x"B1",x"47", + x"13",x"57",x"20",x"60",x"B0",x"20",x"50",x"B0",x"41",x"1F",x"51",x"74",x"58",x"38",x"94",x"FE", + x"35",x"94",x"DF",x"42",x"1F",x"52",x"44",x"18",x"1F",x"C1",x"51",x"44",x"36",x"94",x"C4",x"44", + x"18",x"1F",x"C2",x"52",x"70",x"B0",x"1C",x"F8",x"88",x"88",x"88",x"F8",x"20",x"20",x"20",x"20", + x"20",x"F8",x"08",x"F8",x"80",x"F8",x"F8",x"08",x"F8",x"08",x"F8",x"88",x"88",x"F8",x"08",x"08", + x"F8",x"80",x"F8",x"08",x"F8",x"F8",x"80",x"F8",x"88",x"F8",x"F8",x"08",x"10",x"10",x"10",x"F8", + x"88",x"F8",x"88",x"F8",x"F8",x"88",x"F8",x"08",x"F8",x"F8",x"80",x"98",x"88",x"F8",x"F8",x"08", + x"38",x"00",x"20",x"F8",x"20",x"20",x"20",x"20",x"00",x"00",x"00",x"00",x"00",x"F8",x"A8",x"A8", + x"A8",x"A8",x"88",x"50",x"20",x"50",x"88",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"20",x"00",x"20", + x"00",x"00",x"00",x"F8",x"00",x"00",x"50",x"50",x"50",x"50",x"50",x"A0",x"A0",x"A0",x"A0",x"A0", + x"C0",x"C0",x"00",x"00",x"00",x"08",x"08",x"08",x"08",x"08",x"20",x"20",x"20",x"20",x"20",x"10", + x"10",x"20",x"40",x"40",x"08",x"10",x"20",x"40",x"80",x"00",x"18",x"20",x"C0",x"00",x"00",x"C0", + x"20",x"18",x"00",x"80",x"40",x"20",x"10",x"08",x"40",x"40",x"20",x"10",x"10",x"00",x"00",x"00"); + +END PACKAGE; \ No newline at end of file diff --git a/common/Amiga/pla_8721.sv b/common/Amiga/pla_8721.sv index 074c1040..d08fdd4d 100644 --- a/common/Amiga/pla_8721.sv +++ b/common/Amiga/pla_8721.sv @@ -44,243 +44,146 @@ module pla_8721( output ioacc, output gwe, output colram, - output charom); + output charom + ); -wire p0; -wire p1; -wire p2; -wire p3; -wire p4; -wire p5; -wire p6; -wire p7; -wire p8; -wire p9; -wire p10; -wire p11; -wire p12; -wire p13; -wire p14; -wire p15; -wire p16; -wire p17; -wire p18; -wire p19; -wire p20; -wire p21; -wire p22; -wire p23; -wire p24; -wire p25; -wire p26; -wire p27; -wire p28; -wire p29; -wire p30; -wire p31; -wire p32; -wire p33; -wire p34; -wire p35; -wire p36; -wire p37; -wire p38; -wire p39; -wire p40; -wire p41; -wire p42; -wire p43; -wire p44; -wire p45; -wire p46; -wire p47; -wire p48; -wire p49; -wire p50; -wire p51; -wire p52; -wire p53; -wire p54; -wire p55; -wire p56; -wire p57; -wire p58; -wire p59; -wire p60; -wire p61; -wire p62; -wire p63; -wire p64; -wire p65; -wire p66; -wire p67; -wire p68; -wire p69; -wire p70; -wire p71; -wire p72; -wire p73; -wire p74; -wire p75; -wire p76; -wire p77; -wire p78; -wire p79; -wire p80; -wire p81; -wire p82; -wire p83; -wire p84; -wire p85; -wire p86; -wire p87; -wire p88; -wire p89; -wire casenb_int; -wire casenb_latch; +wire p0 = charen & hiram & ba & !ms3 & game & rw & aec & a12 & !a13 & a14 & a15; +wire p1 = charen & hiram & !ms3 & game & !rw & aec & a12 & !a13 & a14 & a15; +wire p2 = charen & loram & ba & !ms3 & game & rw & aec & a12 & !a13 & a14 & a15; +wire p3 = charen & loram & !ms3 & game & !rw & aec & a12 & !a13 & a14 & a15; +wire p4 = charen & hiram & ba & !ms3 & !exrom & !game & rw & aec & a12 & !a13 & a14 & a15; +wire p5 = charen & hiram & !ms3 & !exrom & !game & !rw & aec & a12 & !a13 & a14 & a15; +wire p6 = charen & loram & ba & !ms3 & !exrom & !game & rw & aec & a12 & !a13 & a14 & a15; +wire p7 = charen & loram & !ms3 & !exrom & !game & !rw & aec & a12 & !a13 & a14 & a15; -/* Product terms */ +wire p8 = ba & !ms3 & exrom & !game & rw & aec & a13 & !a13 & a14 & a15; +wire p9 = !ms3 & exrom & !game & rw & aec & a12 & !a13 & a14 & a15; +wire p10 = ba & !ms2 & ms3 & rw & aec & a12 & !a13 & a14 & a15; +wire p11 = !ms2 & ms3 & !rw & aec & a12 & !a13 & a14 & a15; +wire p12 = charen & hiram & ba & !ms3 & game & rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; +wire p13 = charen & hiram & !ms3 & game & !rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; +wire p14 = charen & loram & ba & !ms3 & game & rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; +wire p15 = charen & loram & !ms3 & game & !rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; -assign p0 = charen & hiram & ba & !ms3 & game & rw & aec & a12 & !a13 & a14 & a15; -assign p1 = charen & hiram & !ms3 & game & !rw & aec & a12 & !a13 & a14 & a15; -assign p2 = charen & loram & ba & !ms3 & game & rw & aec & a12 & !a13 & a14 & a15; -assign p3 = charen & loram & !ms3 & game & !rw & aec & a12 & !a13 & a14 & a15; +wire p16 = charen & hiram & ba & !ms3 & !exrom & !game & rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; +wire p17 = charen & hiram & !ms3 & !exrom & !game & !rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; +wire p18 = charen & loram & ba & !ms3 & !exrom & !game & rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; +wire p19 = charen & loram & !ms3 & !exrom & !game & !rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; -assign p4 = charen & hiram & ba & !ms3 & !exrom & !game & rw & aec & a12 & !a13 & a14 & a15; -assign p5 = charen & hiram & !ms3 & !exrom & !game & !rw & aec & a12 & !a13 & a14 & a15; -assign p6 = charen & loram & ba & !ms3 & !exrom & !game & rw & aec & a12 & !a13 & a14 & a15; -assign p7 = charen & loram & !ms3 & !exrom & !game & !rw & aec & a12 & !a13 & a14 & a15; +wire p20 = ba & !ms3 & exrom & !game & rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; +wire p21 = !ms3 & exrom & !game & rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; -assign p8 = ba & !ms3 & exrom & !game & rw & aec & a13 & !a13 & a14 & a15; -assign p9 = !ms3 & exrom & !game & rw & aec & a12 & !a13 & a14 & a15; +wire p22 = ba & !ms2 & ms3 & rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; +wire p23 = !ms2 & ms3 & !rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; -assign p10 = ba & !ms2 & ms3 & rw & aec & a12 & !a13 & a14 & a15; -assign p11 = !ms2 & ms3 & !rw & aec & a12 & !a13 & a14 & a15; +wire p24 = charen & hiram & ba & !ms3 & game & rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; +wire p25 = charen & hiram & !ms3 & game & !rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; +wire p26 = charen & loram & ba & !ms3 & game & rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; +wire p27 = charen & loram & !ms3 & game & !rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; -assign p12 = charen & hiram & ba & !ms3 & game & rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; -assign p13 = charen & hiram & !ms3 & game & !rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; -assign p14 = charen & loram & ba & !ms3 & game & rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; -assign p15 = charen & loram & !ms3 & game & !rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; +wire p28 = charen & hiram & ba & !ms3 & !exrom & !game & rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; +wire p29 = charen & hiram & !ms3 & !exrom & !game & !rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; +wire p30 = charen & loram & ba & !ms3 & !exrom & !game & rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; +wire p31 = charen & loram & !ms3 & !exrom & !game & !rw & aec & !a10 & a11 & a12 & !a13 & a15; -assign p16 = charen & hiram & ba & !ms3 & !exrom & !game & rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; -assign p17 = charen & hiram & !ms3 & !exrom & !game & !rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; -assign p18 = charen & loram & ba & !ms3 & !exrom & !game & rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; -assign p19 = charen & loram & !ms3 & !exrom & !game & !rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; +wire p32 = ba & !ms3 & exrom & !game & rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; +wire p33 = !ms3 & exrom & !game & rw & aec & !a10 & a11 & a12 & !a13 & a15; -assign p20 = ba & !ms3 & exrom & !game & rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; -assign p21 = !ms3 & exrom & !game & rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; +wire p34 = ba & !ms2 & ms3 & rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; +wire p35 = !ms2 & ms3 & !rw & aec & !a10 & a11 & a12 & !a13 & a15; -assign p22 = ba & !ms2 & ms3 & rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; -assign p23 = !ms2 & ms3 & !rw & aec & !a10 & !a11 & a12 & !a13 & a14 & a15; +wire p36 = !aec; +wire p37 = !rw & aec & !a10 & a11 & a12 & !a13 & a15; -assign p24 = charen & hiram & ba & !ms3 & game & rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; -assign p25 = charen & hiram & !ms3 & game & !rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; -assign p26 = charen & loram & ba & !ms3 & game & rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; -assign p27 = charen & loram & !ms3 & game & !rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; +wire p39 = !charen & hiram & !ms3 & game & rw & aec & a12 & !a13 & a14 & a15; +wire p40 = !charen & loram & !ms3 & game & rw & aec & a12 & !a13 & a14 & a15; +wire p41 = !charen & hiram & !ms3 & !exrom & !game & rw & aec & a12 & !a13 & a14 & a15; -assign p28 = charen & hiram & ba & !ms3 & !exrom & !game & rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; -assign p29 = charen & hiram & !ms3 & !exrom & !game & !rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; -assign p30 = charen & loram & ba & !ms3 & !exrom & !game & rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; -assign p31 = charen & loram & !ms3 & !exrom & !game & !rw & aec & !a10 & a11 & a12 & !a13 & a15; +wire p42 = va14 & !vma5 & vma4 & !ms3 & game & !aec; +wire p43 = va14 & !vma5 & vma4 & !ms3 & !exrom & !game & !aec; -assign p32 = ba & !ms3 & exrom & !game & rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; -assign p33 = !ms3 & exrom & !game & rw & aec & !a10 & a11 & a12 & !a13 & a15; +wire p44 = !ms0 & !ms1 & ms2 &ms3 & z80en & rw & aec & a12 & !a13 & a14 & a15; +wire p45 = hiram & loram & !ms3 & !exrom & rw & aec & !a13 & !a14 & a15; -assign p34 = ba & !ms2 & ms3 & rw & aec & !a10 & a11 & a12 & !a13 & a14 & a15; -assign p35 = !ms2 & ms3 & !rw & aec & !a10 & a11 & a12 & !a13 & a15; +wire p46 = !ms3 & exrom & !game & aec & !a13 & !a14 & a15; +wire p47 = ms0 & !ms1 & ms3 & exrom & !game & aec & !a14 & a15; +wire p48 = !ms0 & ms1 & ms3 & aec & !a14 & a15; -assign p36 = !aec; -assign p37 = !rw & aec & !a10 & a11 & a12 & !a13 & a15; +wire p49 = hiram & !ms3 & !exrom & !game & aec & a13 & !a14 & a15; +wire p50 = ms3 & exrom & !game & aec & a13 & !a14 & a15; -assign p39 = !charen & hiram & !ms3 & game & rw & aec & a12 & !a13 & a14 & a15; -assign p40 = !charen & loram & !ms3 & game & rw & aec & a12 & !a13 & a14 & a15; -assign p41 = !charen & hiram & !ms3 & !exrom & !game & rw & aec & a12 & !a13 & a14 & a15; +wire p51 = vma5 & vma4 & !ms3 & exrom & !game & !aec; +wire p52 = ms0 & !ms1 & ms3 & rw & aec & !a12 & !a13 & a14 & a15; +wire p53 = !ms0 & ms1 & ms3 & rw & aec & !a12 & !a13 & a14 & a15; +wire p54 = !ms0 & !ms1 & ms3 & rw & aec & !a12 & !a13 & a14 & a15; -assign p42 = va14 & !vma5 & vma4 & !ms3 & game & !aec; -assign p43 = va14 & !vma5 & vma4 & !ms3 & !exrom & !game & !aec; +wire p55 = !ms0 & !ms1 & z80io & !z80en & rw & aec & !a12 & !a13 & !a14 & !a15; +wire p56 = !ms0 & !ms1 & ms3 & rw & aec & !a14 & a15; +wire p57 = !ms0 & !ms1 & ms3 & rw & aec & a14 & !a15; -assign p44 = !ms0 & !ms1 & ms2 &ms3 & z80en & rw & aec & a12 & !a13 & a14 & a15; -assign p45 = hiram & loram & !ms3 & !exrom & rw & aec & !a13 & !a14 & a15; +wire p58 = hiram & !ms3 & game & rw & aec & a13 & a14 & a15; +wire p59 = hiram & !ms3 & !exrom & !game & rw & aec & a13 & a14 & a15; +wire p60 = hiram & loram & !ms3 & game & rw & aec & a13 & !a14 & a15; -assign p46 = !ms3 & exrom & !game & aec & !a13 & !a14 & a15; -assign p47 = ms0 & !ms1 & ms3 & exrom & !game & aec & !a14 & a15; -assign p48 = !ms0 & ms1 & ms3 & aec & !a14 & a15; +wire p61 = !z80io & !z80en & aec & !a10 & !a11 & !a13 & a14 & a15; +wire p62 = !z80io & !z80en & aec & a12 & !a13 & a14 & a15; +wire p63 = !z80io & !z80en & aec & !a10 & a11 & a12 & !a13 & a14 & a15; -assign p49 = hiram & !ms3 & !exrom & !game & aec & a13 & !a14 & a15; -assign p50 = ms3 & exrom & !game & aec & a13 & !a14 & a15; +wire p64 = !rw & aec; +wire p65 = rw & aec; +wire p66 = !aec; -assign p51 = vma5 & vma4 & !ms3 & exrom & !game & !aec; -assign p52 = ms0 & !ms1 & ms3 & rw & aec & !a12 & !a13 & a14 & a15; -assign p53 = !ms0 & ms1 & ms3 & rw & aec & !a12 & !a13 & a14 & a15; -assign p54 = !ms0 & !ms1 & ms3 & rw & aec & !a12 & !a13 & a14 & a15; +wire p67 = !ms2 & !z80en & aec & !a10 & !a11 & a12 & !a13 & !a14 & !a15; +wire p68 = !ms2 & !z80en & !rw & aec & !a10 & !a11 & a12 & !a13 & !a14 & !a15; -assign p55 = !ms0 & !ms1 & z80io & !z80en & rw & aec & !a12 & !a13 & !a14 & !a15; -assign p56 = !ms0 & !ms1 & ms3 & rw & aec & !a14 & a15; -assign p57 = !ms0 & !ms1 & ms3 & rw & aec & a14 & !a15; +wire p69 = !charen & !vma5 & vma4 & ms3 & aec; -assign p58 = hiram & !ms3 & game & rw & aec & a13 & a14 & a15; -assign p59 = hiram & !ms3 & !exrom & !game & rw & aec & a13 & a14 & a15; -assign p60 = hiram & loram & !ms3 & game & rw & aec & a13 & !a14 & a15; +wire p70 = !rom_256 & !ms0 & !ms1 & ms3 & rw & aec & a14 & !a15; +wire p71 = !rom_256 & !ms0 & !ms1 & ms3 & rw & aec & !a12 & !a13 & a14 & a15; +wire p72 = !rom_256 & !ms0 & !ms1 & z80io & !z80en & rw & aec & !a12 & !a13 & !a14 & !a15; -assign p61 = !z80io & !z80en & aec & !a10 & !a11 & !a13 & a14 & a15; -assign p62 = !z80io & !z80en & aec & a12 & !a13 & a14 & a15; -assign p63 = !z80io & !z80en & aec & !a10 & a11 & a12 & !a13 & a14 & a15; +wire p73 = clk; +wire p74 = rw & !aec & vicfix; -assign p64 = !rw & aec; -assign p65 = rw & aec; -assign p66 = !aec; +wire p75 = !ms0 & !ms1 & ms3 & rw & aec & a13 & a14 & a15; +wire p76 = !rom_256 & !ms0 & !ms1 & ms3 & rw & aec & a13 & a14 & a15; +wire p77 = !ms0 & ms1 & ms3 & rw & aec & a13 & a14 & a15; +wire p78 = !ms0 & ms1 & ms2 & ms3 & rw & aec & a12 & !a13 & a14 & a15; +wire p79 = ms0 & !ms1 & ms3 & rw & aec & a13 & a14 & a15; +wire p80 = ms0 & !ms1 & ms2 & ms3 & rw & aec & a12 & !a13 & a14 & a15; -assign p67 = !ms2 & !z80en & aec & !a10 & !a11 & a12 & !a13 & !a14 & !a15; -assign p68 = !ms2 & !z80en & !rw & aec & !a10 & !a11 & a12 & !a13 & !a14 & !a15; +wire p81 = !ms3 & exrom & !game & aec & a12 & !a14 & !a15; +wire p82 = !ms3 & exrom & !game & aec & a13 & !a14; +wire p83 = !ms3 & exrom & !game & aec & a14; +wire p84 = !ms3 & exrom & !game & aec & !a12 & !a13 & a14 & a15; -assign p69 = !charen & !vma5 & vma4 & ms3 & aec; - -assign p70 = !rom_256 & !ms0 & !ms1 & ms3 & rw & aec & a14 & !a15; -assign p71 = !rom_256 & !ms0 & !ms1 & ms3 & rw & aec & !a12 & !a13 & a14 & a15; -assign p72 = !rom_256 & !ms0 & !ms1 & z80io & !z80en & rw & aec & !a12 & !a13 & !a14 & !a15; - -assign p73 = clk; -assign p74 = rw & !aec & vicfix; - -assign p75 = !ms0 & !ms1 & ms3 & rw & aec & a13 & a14 & a15; -assign p76 = !rom_256 & !ms0 & !ms1 & ms3 & rw & aec & a13 & a14 & a15; -assign p77 = !ms0 & ms1 & ms3 & rw & aec & a13 & a14 & a15; -assign p78 = !ms0 & ms1 & ms2 & ms3 & rw & aec & a12 & !a13 & a14 & a15; -assign p79 = ms0 & !ms1 & ms3 & rw & aec & a13 & a14 & a15; -assign p80 = ms0 & !ms1 & ms2 & ms3 & rw & aec & a12 & !a13 & a14 & a15; - -assign p81 = !ms3 & exrom & !game & aec & a12 & !a14 & !a15; -assign p82 = !ms3 & exrom & !game & aec & a13 & !a14; -assign p83 = !ms3 & exrom & !game & aec & a14; -assign p84 = !ms3 & exrom & !game & aec & !a12 & !a13 & a14 & a15; - -assign p85 = !loram & ms3 & aec; -assign p86 = !hiram & ms3 & !aec; +wire p85 = !loram & ms3 & aec; +wire p86 = !hiram & ms3 & !aec; /* outputs */ -assign sden = p42 || p43 || p66 || p69; -assign roml = p45 || p46 || p47; -assign romh = p49 || p50 || p51 || p52 || p79 || p80; -assign clrbnk = p85 || p86; -assign from = p48 || p53 || p77 || p78; -assign rom4 = p54 || p55 || p75; -assign rom3 = p56 || p70; -assign rom2 = p57; -assign rom1 = p58 || p59 || p60 || p71 || p71 || p76; -assign iocs = p0 || p1 || p2 || p3 || p4 || p5 || p6 || p7 || p8 || p9 || p10 || p11 || p62; -assign dir = p12 || p14 || p16 || p18 || p20 || p22 || p24 || p26 || p28 || p30 || p32 || p34 || p39 || p40 || p41 || p44 || p65; -assign vic = p12 || p13 || p14 || p15 || p16 || p17 || p18 || p19 || p20 || p21 || p22 || p23 || p61; -assign ioacc = p0 || p1 || p2 || p3 || p4 || p5 || p6 || p7 || p8 || p9 || p10 || p11 || +wire sden = p42 || p43 || p66 || p69; +wire roml = p45 || p46 || p47; +wire romh = p49 || p50 || p51 || p52 || p79 || p80; +wire clrbnk = p85 || p86; +wire from = p48 || p53 || p77 || p78; +wire rom4 = p54 || p55 || p75; +wire rom3 = p56 || p70; +wire rom2 = p57; +wire rom1 = p58 || p59 || p60 || p71 || p71 || p76; +wire iocs = p0 || p1 || p2 || p3 || p4 || p5 || p6 || p7 || p8 || p9 || p10 || p11 || p62; +wire dir = p12 || p14 || p16 || p18 || p20 || p22 || p24 || p26 || p28 || p30 || p32 || p34 || p39 || p40 || p41 || p44 || p65; +wire vic = p12 || p13 || p14 || p15 || p16 || p17 || p18 || p19 || p20 || p21 || p22 || p23 || p61; +wire ioacc = p0 || p1 || p2 || p3 || p4 || p5 || p6 || p7 || p8 || p9 || p10 || p11 || p12 || p13 || p14 || p15 || p16 || p17 || p18 || p19 || p20 || p21 || p22 || p61 || p62; -assign gwe = p37; -assign colram = p24 || p25 || p26 || p27 || p28 || p29 || p30 || p31 || p32 || p33 || p34 || p35 || p36 || p63 || p67; -assign charrom = p39 || p40 || p41 || p42 || p43 || p44 || p69; +wire gwe = p37; +wire colram = p24 || p25 || p26 || p27 || p28 || p29 || p30 || p31 || p32 || p33 || p34 || p35 || p36 || p63 || p67; +wire charrom = p39 || p40 || p41 || p42 || p43 || p44 || p69; -assign casenb_latch = p73 || p74; +wire casenb_latch = p73 || p74; -assign casenb_int = p0 || p1 || p2 || p3 || p4 || p5 || p6 || p7 || p8 || p9 +wire casenb_int = p0 || p1 || p2 || p3 || p4 || p5 || p6 || p7 || p8 || p9 || p10 || p11 || p12 || p13 || p14 || p15 || p16 || p17 || p18 || p19 || p20 || p21 || p22 || p23 || p39 || p40 || p41 || p42 || p43 || p44 || p45 || p46 || p47 || p48 || p49 || p50 || p51 || p52 || p53 || p54 @@ -298,4 +201,4 @@ always @ (casenb_latch or casenb_int) if (casenb_latch) casenb <= casenb_int; -endmodule \ No newline at end of file +endmodule \ No newline at end of file diff --git a/common/CPU/8088/eu_rom.v b/common/CPU/8088/eu_rom.v index b1ad6a05..a00d6b9a 100644 --- a/common/CPU/8088/eu_rom.v +++ b/common/CPU/8088/eu_rom.v @@ -12,4 +12,4 @@ initial $readmemb("microcode.mem", memory); always @(posedge clka) douta <= memory[addra]; -endmodule \ No newline at end of file +endmodule \ No newline at end of file diff --git a/common/CPU/8088/mcl86_eu_core.v b/common/CPU/8088/mcl86_eu_core.v index f3a31419..c7e9bbb6 100644 --- a/common/CPU/8088/mcl86_eu_core.v +++ b/common/CPU/8088/mcl86_eu_core.v @@ -326,7 +326,7 @@ assign eu_biu_req = eu_biu_command[9]; assign intr_asserted = BIU_INTR & intr_enable_delayed; -assign new_instruction = (eu_rom_address[12:8]==5'h01) ? 1'b1 : 1'b0; +wire new_instruction = (eu_rom_address[12:8]==5'h01) ? 1'b1 : 1'b0; //------------------------------------------------------------------------------------------