From dd8ef75e04f868c95d11d7dbe7c40a3783273017 Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Tue, 15 Jun 2021 00:11:16 +0200 Subject: [PATCH] Nova2001: add Nova2001 --- .../NinjaKun_MiST/NinjaKun_MiST.sdc | 2 +- .../NinjaKun_MiST/meta/Nova 2001.mra | 62 +++++++++++++++++++ .../NinjaKun_MiST/rtl/NinjaKun_MiST.sv | 36 +++++++---- .../NinjaKun_MiST/rtl/defs.v | 3 + .../NinjaKun_MiST/rtl/ninjakun_adec.v | 35 +++++++---- .../NinjaKun_MiST/rtl/ninjakun_input.v | 44 ++++++------- .../NinjaKun_MiST/rtl/ninjakun_io_video.v | 20 +++--- .../NinjaKun_MiST/rtl/ninjakun_main.v | 44 +++++++------ .../NinjaKun_MiST/rtl/ninjakun_psg.v | 41 ++++++++---- .../NinjaKun_MiST/rtl/ninjakun_sadec.v | 21 ++++++- .../NinjaKun_MiST/rtl/ninjakun_top.v | 58 +++++++++-------- .../NinjaKun_MiST/rtl/ninjakun_video.v | 32 ++++++---- .../Nova2001_Hardware/NinjaKun_MiST/rtl/pll.v | 52 ++++++++++++---- .../NinjaKun_MiST/rtl/sdram.sv | 13 ++-- 14 files changed, 323 insertions(+), 140 deletions(-) create mode 100644 Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/meta/Nova 2001.mra create mode 100644 Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/defs.v diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.sdc b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.sdc index 80fe5371..33ffd42f 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.sdc +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.sdc @@ -53,7 +53,7 @@ set_time_format -unit ns -decimal_places 3 create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] -set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]" +set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]" set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]" #************************************************************** # Create Generated Clock diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/meta/Nova 2001.mra b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/meta/Nova 2001.mra new file mode 100644 index 00000000..28e66588 --- /dev/null +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/meta/Nova 2001.mra @@ -0,0 +1,62 @@ + + Nova 2001 + + no + no + + + + + 1984 + UPL + Taito + Platform - Climb + + nova2001 + ninjakun + 0220 + ninjakun + + 15kHz + horizontal + + + 2 (alternating) + 2-way horizontal + + 2 + + + + + + + + + + + + + + 2 + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/NinjaKun_MiST.sv b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/NinjaKun_MiST.sv index 453f5af3..cc17a5c4 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/NinjaKun_MiST.sv +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/NinjaKun_MiST.sv @@ -27,7 +27,8 @@ module NinjaKun_MiST ( output SDRAM_CKE ); -`include "rtl\build_id.v" +`include "rtl/build_id.v" +`include "rtl/defs.v" localparam CONF_STR = { "NINJAKUN;;", @@ -42,7 +43,7 @@ localparam CONF_STR = { assign LED = ~ioctl_downl; assign AUDIO_R = AUDIO_L; -assign SDRAM_CLK = CLOCK_48; +assign SDRAM_CLK = CLOCK_96; assign SDRAM_CKE = 1; wire rotate = status[2]; @@ -51,23 +52,29 @@ wire blend = status[5]; wire service = status[6]; wire [6:0] core_mod; -wire RAIDERS5 = core_mod == 1; +wire [1:0] hwtype = core_mod[1:0]; -reg [7:0] CTR1, CTR2; +reg [7:0] CTR1, CTR2, CTR3; always @(*) begin CTR1 = ~{2'b11, m_one_player, 1'b0, m_fireA, m_fireB, m_right, m_left }; CTR2 = ~{~(m_coin1 | m_coin2), ~service, m_two_players, 1'b0, m_fire2A, m_fire2B, m_right2, m_left2 }; - if (RAIDERS5) begin + CTR3 = 0; + if (hwtype == `HW_RAIDERS5) begin CTR1 = ~{1'b0, 1'b0, m_one_player, m_fireA, m_up, m_down, m_right, m_left }; CTR2 = ~{(m_coin1 | m_coin2), service, m_two_players, m_fire2A, m_up2, m_down2, m_right2, m_left2}; + end else if (hwtype == `HW_NOVA2001) begin + CTR1 = ~{m_fireA, m_fireB, 2'b00, m_right, m_left, m_down, m_up}; + CTR2 = ~{m_fire2A, m_fire2B, 2'b00, m_right2, m_left2, m_down2, m_up2}; + CTR3 = ~{5'b00000, m_two_players, m_one_player, m_coin1 | m_coin2}; end end -wire CLOCK_48, pll_locked; +wire CLOCK_96, CLOCK_48, pll_locked; pll pll( .inclk0(CLOCK_27), - .c0(CLOCK_48), + .c0(CLOCK_96), + .c1(CLOCK_48), .locked(pll_locked) ); @@ -125,10 +132,10 @@ wire [31:0] fg_rom_do; wire [12:0] bg_rom_addr; wire [31:0] bg_rom_do; -sdram sdram( +sdram #(96) sdram( .*, .init_n ( pll_locked ), - .clk ( CLOCK_48 ), + .clk ( CLOCK_96 ), // port1 used for main + aux CPU .port1_req ( port1_req ), @@ -191,11 +198,12 @@ wire [11:0] POUT; ninjakun_top ninjakun_top( .RESET(reset), .MCLK(CLOCK_48), - .RAIDERS5(RAIDERS5), + .HWTYPE(hwtype), .CTR1(CTR1), .CTR2(CTR2), + .CTR3(CTR3), .DSW1(status[15:8]), - .DSW2(status[23:16]), + .DSW2({(hwtype == `HW_NOVA2001 ? ~service : status[23]), status[22:16]}), .PH(HPOS), .PV(VPOS), .PCLK_EN(PCLK_EN), @@ -211,7 +219,11 @@ ninjakun_top ninjakun_top( .fg_rom_addr(fg_rom_addr), .fg_rom_data(fg_rom_do), .bg_rom_addr(bg_rom_addr), - .bg_rom_data(bg_rom_do) + .bg_rom_data(bg_rom_do), + .PALADR(ioctl_addr[4:0]), + .PALWR(ioctl_addr[23:5] == {16'h0180, 3'b000} && ioctl_wr), + .PALDAT(ioctl_dout) + ); wire [7:0] oPIX; diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/defs.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/defs.v new file mode 100644 index 00000000..8b7912bb --- /dev/null +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/defs.v @@ -0,0 +1,3 @@ +`define HW_NINJAKUN 2'd0 +`define HW_RAIDERS5 2'd1 +`define HW_NOVA2001 2'd2 diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_adec.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_adec.v index c017d17a..42a9455c 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_adec.v +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_adec.v @@ -1,22 +1,24 @@ module ninjakun_adec ( - input RAIDERS5, - input [15:0] CP0AD, - input CP0WR, + input [1:0] HWTYPE, + input [15:0] CP0AD, + input CP0WR, - input [15:0] CP1AD, - input CP1WR, + input [15:0] CP1AD, + input CP1WR, - output CS_IN0, - output CS_IN1, + output CS_IN0, + output CS_IN1, - output CS_SH0, - output CS_SH1, + output CS_SH0, + output CS_SH1, - output SYNWR0, - output SYNWR1 + output SYNWR0, + output SYNWR1 ); +`include "rtl/defs.v" + always @(*) begin CS_IN0 = (CP0AD[15:2] == 14'b1010_0000_0000_00); CS_IN1 = (CP1AD[15:2] == 14'b1010_0000_0000_00); @@ -27,13 +29,22 @@ always @(*) begin SYNWR0 = CS_IN0 & (CP0AD[1:0]==2) & CP0WR; SYNWR1 = CS_IN1 & (CP1AD[1:0]==2) & CP1WR; - if (RAIDERS5) begin + if (HWTYPE == `HW_RAIDERS5) begin CS_IN0 = 0; CS_IN1 = 0; CS_SH0 = (CP0AD[15:11] == 5'b1110_0); CS_SH1 = (CP1AD[15:11] == 5'b1010_0); + SYNWR0 = 0; + SYNWR1 = 0; + end else if (HWTYPE == `HW_NOVA2001) begin + CS_IN0 = (CP0AD[15:4] == 12'hC00 && (CP0AD[3:1] == 3'b011 || CP0AD[3:1] == 3'b111)); + CS_IN1 = 0; + + CS_SH0 = (CP0AD[15:11] == 5'b1110_0); + CS_SH1 = 0; + SYNWR0 = 0; SYNWR1 = 0; end diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_input.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_input.v index 5bd6fa87..b9f9de79 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_input.v +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_input.v @@ -2,28 +2,29 @@ module ninjakun_input ( - input MCLK, - input RESET, + input MCLK, + input RESET, + input [1:0] HWTYPE, - input [7:0] CTR1i, // Control Panel (Negative Logic) - input [7:0] CTR2i, + input [7:0] CTR1i, // Control Panel (Negative Logic) + input [7:0] CTR2i, + input [7:0] CTR3i, + input VBLK, - input VBLK, + input [1:0] AD0, + input [1:0] OD0, + input WR0, - input [1:0] AD0, - input [1:0] OD0, - input WR0, + input [1:0] AD1, + input [1:0] OD1, + input WR1, - input [1:0] AD1, - input [1:0] OD1, - input WR1, - - output [7:0] INPD0, - output [7:0] INPD1 + output [7:0] INPD0, + output [7:0] INPD1 ); reg [1:0] SYNCFLG; -reg [7:0] CTR1,CTR2; +reg [7:0] CTR1,CTR2,CTR3; always @( posedge MCLK or posedge RESET ) begin if (RESET) begin SYNCFLG = 0; @@ -31,6 +32,7 @@ always @( posedge MCLK or posedge RESET ) begin else begin CTR1 <= CTR1i; CTR2 <= CTR2i; + CTR3 <= CTR3i; if (WR0) begin if (OD0[1]) SYNCFLG[0] = 1; if (OD0[0]) SYNCFLG[1] = 0; @@ -44,14 +46,14 @@ end wire [7:0] INPORT0 = CTR1; wire [7:0] INPORT1 = CTR2; -wire [7:0] INPORT2 = { 4'b0000, SYNCFLG, ~VBLK,1'b0 }; +wire [7:0] INPORT2 = HWTYPE[1] ? {~VBLK, CTR3[6:0]} : { 4'b0000, SYNCFLG, ~VBLK,1'b0 }; assign INPD0 = ( AD0 == 0 ) ? INPORT0 : - ( AD0 == 1 ) ? INPORT1 : - ( AD0 == 2 ) ? INPORT2 : 8'hFF; + ( AD0 == 1 ) ? INPORT1 : + ( AD0 == 2 ) ? INPORT2 : 8'hFF; assign INPD1 = ( AD1 == 0 ) ? INPORT0 : - ( AD1 == 1 ) ? INPORT1 : - ( AD1 == 2 ) ? INPORT2 : 8'hFF; + ( AD1 == 1 ) ? INPORT1 : + ( AD1 == 2 ) ? INPORT2 : 8'hFF; -endmodule \ No newline at end of file +endmodule diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_io_video.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_io_video.v index 074a158d..6ac4e152 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_io_video.v +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_io_video.v @@ -3,7 +3,7 @@ module ninjakun_io_video ( input MCLK, - input RAIDERS5, + input [1:0] HWTYPE, input PCLK_EN, input RESET, input [8:0] PH, @@ -27,15 +27,21 @@ module ninjakun_io_video output [12:0] fg_rom_addr, input [31:0] fg_rom_data, output [12:0] bg_rom_addr, - input [31:0] bg_rom_data + input [31:0] bg_rom_data, + input [4:0] PALADR, + input PALWR, + input [7:0] PALDAT ); +`include "rtl/defs.v" + wire [9:0] FGVAD; wire [15:0] FGVDT; wire [9:0] BGVAD; wire [15:0] BGVDT; wire [10:0] SPAAD; wire [7:0] SPADT; +wire RAIDERS5 = HWTYPE == `HW_RAIDERS5; wire [7:0] SCRPX = RAIDERS5 ? SCRPX_CPU : SCRPX_PSG, SCRPY = RAIDERS5 ? SCRPY_CPU : SCRPY_PSG; wire [7:0] SCRPX_PSG, SCRPY_PSG; reg [7:0] SCRPX_CPU, SCRPY_CPU; @@ -45,7 +51,7 @@ NINJAKUN_VIDEO video ( .RESET(RESET), .MCLK(MCLK), .PCLK_EN(PCLK_EN), - .RAIDERS5(RAIDERS5), + .HWTYPE(HWTYPE), .PH(PH), .PV(PV), .PALAD(PALET), // Pixel Output (Palet Index) @@ -70,7 +76,7 @@ NINJAKUN_VIDEO video ( wire CS_SCRX, CS_SCRY, CS_PSG, CS_FGV, CS_BGV, CS_SPA, CS_PAL; ninjakun_sadec sadec( - .RAIDERS5(RAIDERS5), + .HWTYPE(HWTYPE), .CPADR(CPADR), .CPSEL(CPSEL), .CS_SCRX(CS_SCRX), @@ -94,14 +100,14 @@ end wire [7:0] PSDAT, FGDAT = CPADR[10] ? FGDAT16[15:8] : FGDAT16[7:0], BGDAT = CPADR[10] ? BGDAT16[15:8] : BGDAT16[7:0], SPDAT, PLDAT; wire [15:0] FGDAT16, BGDAT16; wire [9:0] BGOFS = CPADR[9:0]+{SCRPY[7:3],SCRPX[7:3]}; -wire [10:0] BGADR = {CPADR[10],BGOFS}; +wire [10:0] BGADR = HWTYPE[1] ? CPADR : {CPADR[10],BGOFS}; dpram #(8,10) fgv_lo(MCLK, CS_FGV & CPWRT & ~CPADR[10], CPADR[9:0], CPODT, FGDAT16[ 7:0], MCLK, 1'b0, FGVAD, 8'd0, FGVDT[ 7:0]); dpram #(8,10) fgv_hi(MCLK, CS_FGV & CPWRT & CPADR[10], CPADR[9:0], CPODT, FGDAT16[15:8], MCLK, 1'b0, FGVAD, 8'd0, FGVDT[15:8]); dpram #(8,10) bgv_lo(MCLK, CS_BGV & CPWRT & ~BGADR[10], BGADR[9:0], CPODT, BGDAT16[ 7:0], MCLK, 1'b0, BGVAD, 8'd0, BGVDT[ 7:0]); dpram #(8,10) bgv_hi(MCLK, CS_BGV & CPWRT & BGADR[10], BGADR[9:0], CPODT, BGDAT16[15:8], MCLK, 1'b0, BGVAD, 8'd0, BGVDT[15:8]); dpram #(8,11) spa (MCLK, CS_SPA & CPWRT, CPADR[10:0], CPODT, SPDAT, ~MCLK, 1'b0, SPAAD, 8'h0, SPADT); -dpram #(8,9) pal (MCLK, CS_PAL & CPWRT, CPADR[8:0], CPODT, PLDAT, MCLK, 1'b0, PALET, 8'h0, POUT); +dpram #(8,9) pal (MCLK, CS_PAL & CPWRT, CPADR[8:0], CPODT, PLDAT, MCLK, PALWR, PALWR ? PALADR : PALET, PALDAT, POUT); assign CPIDT = CS_PSG ? PSDAT : CS_FGV ? FGDAT : @@ -112,7 +118,7 @@ assign CPIDT = CS_PSG ? PSDAT : ninjakun_psg psg( .MCLK(MCLK), - .RAIDERS5(RAIDERS5), + .HWTYPE(HWTYPE), .ADR(CPADR[1:0]), .CS(CS_PSG), .WR(CPWRT), diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_main.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_main.v index 8bba4e06..9cc0f50a 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_main.v +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_main.v @@ -1,25 +1,27 @@ module ninjakun_main( - input RESET, - input MCLK, - input RAIDERS5, - input VBLK, + input RESET, + input MCLK, + input [1:0] HWTYPE, + input VBLK, - input [7:0] CTR1, - input [7:0] CTR2, + input [7:0] CTR1, + input [7:0] CTR2, + input [7:0] CTR3, - output [15:0] CPADR, - output [7:0] CPODT, - input [7:0] CPIDT, - output CPRED, - output CPWRT, - output CPSEL, + output [15:0] CPADR, + output [7:0] CPODT, + input [7:0] CPIDT, + output CPRED, + output CPWRT, + output CPSEL, - output [14:0] CPU1ADDR, - input [7:0] CPU1DT, - output [14:0] CPU2ADDR, - input [7:0] CPU2DT + output [14:0] CPU1ADDR, + input [7:0] CPU1DT, + output [14:0] CPU2ADDR, + input [7:0] CPU2DT ); +`include "rtl/defs.v" wire CP0IQ, CP0IQA; wire CP1IQ, CP1IQA; @@ -54,7 +56,7 @@ Z80IP cpu0( ); Z80IP cpu1( - .reset_in(RESET), + .reset_in(RESET | HWTYPE[1]), .clk(MCLK), .clken_p(CP1CE_P), .clken_n(CP1CE_N), @@ -94,7 +96,7 @@ ninjakun_cpumux ioshare( wire CS_SH0, CS_SH1, CS_IN0, CS_IN1; wire SYNWR0, SYNWR1; ninjakun_adec adec( - .RAIDERS5(RAIDERS5), + .HWTYPE(HWTYPE), .CP0AD(CP0AD), .CP0WR(CP0WR), .CP1AD(CP1AD), @@ -115,6 +117,7 @@ assign CPU2ADDR = CP1AD[14:0]; assign ROM1D = CPU2DT; wire [7:0] SHDT0, SHDT1; +wire RAIDERS5 = HWTYPE == `HW_RAIDERS5; dpram #(8,11) shmem( MCLK, CS_SH0 & CP0WR, { CP0AD[10] ,CP0AD[9:0]}, CP0OD, SHDT0, @@ -124,10 +127,13 @@ wire [7:0] INPD0, INPD1; ninjakun_input inps( .MCLK(MCLK), .RESET(RESET), + .HWTYPE(HWTYPE), .CTR1i(CTR1), // Control Panel (Negative Logic) .CTR2i(CTR2), + .CTR3i(CTR3), .VBLK(VBLK), - .AD0(CP0AD[1:0]), +// .AD0(CP0AD[1:0]), + .AD0({HWTYPE[1] ? CP0AD[3] : CP0AD[1], CP0AD[0]}), .OD0(CP0OD[7:6]), .WR0(SYNWR0), .AD1(CP1AD[1:0]), diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_psg.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_psg.v index f0992b2f..911f2917 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_psg.v +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_psg.v @@ -1,7 +1,7 @@ module ninjakun_psg ( input MCLK, - input RAIDERS5, + input [1:0] HWTYPE, input [1:0] ADR, input CS, input WR, @@ -19,17 +19,27 @@ module ninjakun_psg output [15:0] SNDO ); +`include "rtl/defs.v" + wire [7:0] OD0, OD1; -assign OD = ADR[1] ? OD1 : OD0; +assign OD = psg1cs ? OD1 : OD0; reg [7:0] SA0, SB0, SC0; wire [7:0] S0x; wire [1:0] S0c; reg [7:0] SA1, SB1, SC1; wire [7:0] S1x; wire [1:0] S1c; -reg [2:0] encnt; +reg [3:0] encnt; reg ENA; always @(posedge MCLK) begin ENA <= (encnt==0); encnt <= encnt+1'd1; + case (HWTYPE) + `HW_NINJAKUN, `HW_RAIDERS5: + if (encnt == 7) encnt <= 0; // 6 MHz + `HW_NOVA2001: + if (encnt == 11) encnt <= 0; // 4 MHz + default: ; + endcase + case (S0c) 2'd0: SA0 <= S0x; 2'd1: SB0 <= S0x; @@ -44,15 +54,20 @@ always @(posedge MCLK) begin endcase end -wire psgxad = ~ADR[0]; -wire psg0cs = CS & (~ADR[1]); +wire psgxad = HWTYPE == `HW_NOVA2001 ? ADR[1] : ~ADR[0]; +wire psg0cs = CS & (HWTYPE == `HW_NOVA2001 ? ~ADR[0] : ~ADR[1]); wire psg0bd = psg0cs & (WR|psgxad); wire psg0bc = psg0cs & ((~WR)|psgxad); -wire psg1cs = CS & ADR[1]; +wire psg1cs = CS & (HWTYPE == `HW_NOVA2001 ? ADR[0] : ADR[1]); wire psg1bd = psg1cs & (WR|psgxad); wire psg1bc = psg1cs & ((~WR)|psgxad); +wire [7:0] IOA_PSG0, IOB_PSG0; +wire [7:0] IOA_PSG1, IOB_PSG1; +assign SCRPX = HWTYPE == `HW_NOVA2001 ? IOA_PSG0 : IOA_PSG1; +assign SCRPY = HWTYPE == `HW_NOVA2001 ? IOB_PSG0 : IOB_PSG1; + YM2149 psg0( .I_DA(ID), .O_DA(OD0), @@ -64,8 +79,10 @@ YM2149 psg0( .I_SEL_L(1'b0), .O_AUDIO(S0x), .O_CHAN(S0c), - .I_IOA(RAIDERS5 ? {~VBLK, CTR1[6:0]} : DSW1), - .I_IOB(RAIDERS5 ? CTR2 : DSW2), + .I_IOA(HWTYPE == `HW_RAIDERS5 ? {~VBLK, CTR1[6:0]} : DSW1), + .I_IOB(HWTYPE == `HW_RAIDERS5 ? CTR2 : DSW2), + .O_IOA(IOA_PSG0), + .O_IOB(IOB_PSG0), .ENA(ENA), .RESET_L(~RESET), .CLK(MCLK) @@ -82,10 +99,10 @@ YM2149 psg1( .I_SEL_L(1'b0), .O_AUDIO(S1x), .O_CHAN(S1c), - .I_IOA(RAIDERS5 ? DSW1 : 8'd0), - .I_IOB(RAIDERS5 ? DSW2 : 8'd0), - .O_IOA(SCRPX), - .O_IOB(SCRPY), + .I_IOA(HWTYPE == `HW_NINJAKUN ? 8'd0 : DSW1), + .I_IOB(HWTYPE == `HW_NINJAKUN ? 8'd0 : DSW2), + .O_IOA(IOA_PSG1), + .O_IOB(IOB_PSG1), .ENA(ENA), .RESET_L(~RESET), .CLK(MCLK) diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sadec.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sadec.v index 91080b45..329e1084 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sadec.v +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sadec.v @@ -2,7 +2,7 @@ module ninjakun_sadec ( - input RAIDERS5, + input [1:0] HWTYPE, input [15:0] CPADR, input CPSEL, output CS_SCRX, @@ -14,6 +14,8 @@ module ninjakun_sadec output CS_PAL ); +`include "rtl/defs.v" + always @(*) begin CS_PSG = ( CPADR[15: 2] == 14'b1000_0000_0000_00 ); CS_FGV = ( CPADR[15:11] == 5'b1100_0 ); @@ -23,7 +25,7 @@ always @(*) begin CS_SCRX = 0; CS_SCRY = 0; - if (RAIDERS5) begin + if (HWTYPE == `HW_RAIDERS5) begin if (CPSEL) begin CS_SCRX = ( CPADR == 16'he000 ); CS_SCRY = ( CPADR == 16'he001 ); @@ -41,6 +43,21 @@ always @(*) begin CS_SPA = ( CPADR[15:11] == 5'b1000_0 ); CS_PAL = ( CPADR[15:11] == 5'b1101_0 ); end + end else if (HWTYPE == `HW_NOVA2001) begin + CS_SCRX = 0; + CS_SCRY = 0; + CS_PAL = 0; + if (CPSEL) begin + CS_PSG = 0; + CS_FGV = 0; + CS_BGV = 0; + CS_SPA = 0; + end else begin + CS_PSG = ( CPADR[15: 2] == 14'b1100_0000_0000_00 ); + CS_FGV = ( CPADR[15:11] == 5'b1010_0 ); + CS_BGV = ( CPADR[15:11] == 5'b1010_1 ); + CS_SPA = ( CPADR[15:11] == 5'b1011_0 ); + end end end diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_top.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_top.v index b530b3e5..2155ead8 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_top.v +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_top.v @@ -9,29 +9,33 @@ module ninjakun_top ( - input RESET, // RESET - input MCLK, // Master Clock (48.0MHz) - input RAIDERS5, - input [7:0] CTR1, // Control Panel - input [7:0] CTR2, - input [7:0] DSW1, // DipSW - input [7:0] DSW2, - input [8:0] PH, // PIXEL H - input [8:0] PV, // PIXEL V - output PCLK_EN, // PIXEL CLOCK ENABLE - output [7:0] POUT, // PIXEL OUT - output [15:0] SNDOUT, // Sound Output (LPCM unsigned 16bits) - output [14:0] CPU1ADDR, - input [7:0] CPU1DT, - output [14:0] CPU2ADDR, - input [7:0] CPU2DT, - output [12:0] sp_rom_addr, - input [31:0] sp_rom_data, + input RESET, // RESET + input MCLK, // Master Clock (48.0MHz) + input [1:0] HWTYPE, + input [7:0] CTR1, // Control Panel + input [7:0] CTR2, + input [7:0] CTR3, + input [7:0] DSW1, // DipSW + input [7:0] DSW2, + input [8:0] PH, // PIXEL H + input [8:0] PV, // PIXEL V + output PCLK_EN, // PIXEL CLOCK ENABLE + output [7:0] POUT, // PIXEL OUT + output [15:0] SNDOUT, // Sound Output (LPCM unsigned 16bits) + output [14:0] CPU1ADDR, + input [7:0] CPU1DT, + output [14:0] CPU2ADDR, + input [7:0] CPU2DT, + output [12:0] sp_rom_addr, + input [31:0] sp_rom_data, input sp_rdy, - output [12:0] fg_rom_addr, - input [31:0] fg_rom_data, - output [12:0] bg_rom_addr, - input [31:0] bg_rom_data + output [12:0] fg_rom_addr, + input [31:0] fg_rom_data, + output [12:0] bg_rom_addr, + input [31:0] bg_rom_data, + input [4:0] PALADR, + input PALWR, + input [7:0] PALDAT ); reg [3:0] CLKDIV; @@ -47,10 +51,11 @@ wire CPRED, CPWRT, VBLK; ninjakun_main ninjakun_main( .RESET(RESET), .MCLK(MCLK), - .RAIDERS5(RAIDERS5), + .HWTYPE(HWTYPE), .VBLK(VBLK), .CTR1(CTR1), .CTR2(CTR2), + .CTR3(CTR3), .CPADR(CPADR), .CPODT(CPODT), .CPIDT(CPIDT), @@ -72,7 +77,7 @@ wire [8:0] PALET; wire [7:0] SCRPX, SCRPY; ninjakun_io_video ninjakun_io_video( .MCLK(MCLK), - .RAIDERS5(RAIDERS5), + .HWTYPE(HWTYPE), .PCLK_EN(PCLK_EN), .RESET(RESET), .PH(PH), @@ -96,7 +101,10 @@ ninjakun_io_video ninjakun_io_video( .fg_rom_addr(fg_rom_addr), .fg_rom_data(fg_rom_data), .bg_rom_addr(bg_rom_addr), - .bg_rom_data(bg_rom_data) + .bg_rom_data(bg_rom_data), + .PALADR(PALADR), + .PALWR(PALWR), + .PALDAT(PALDAT) ); endmodule \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_video.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_video.v index a73eeed4..f57075e5 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_video.v +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_video.v @@ -5,8 +5,8 @@ module NINJAKUN_VIDEO input RESET, input MCLK, input PCLK_EN, - input RAIDERS5, - + input [1:0] HWTYPE, + input [8:0] PH, input [8:0] PV, @@ -35,6 +35,10 @@ module NINJAKUN_VIDEO input [31:0] bg_rom_data ); +`include "rtl/defs.v" + +wire RAIDERS5 = HWTYPE == `HW_RAIDERS5; + assign VBLK = (PV>=193); // ROMs @@ -64,7 +68,7 @@ assign BGCDT = bg_rom_data; wire FGPRI; wire [8:0] FGOUT; NINJAKUN_FG fg( - MCLK, PCLK_EN, RAIDERS5, + MCLK, PCLK_EN, HWTYPE, PH, PV, FGVAD, FGVDT, FGCAD, FGCDT, @@ -77,7 +81,7 @@ wire FGPPQ = FGOPQ & (~FGPRI); wire [8:0] BGOUT; NINJAKUN_BG bg( - MCLK, PCLK_EN, RAIDERS5, + MCLK, PCLK_EN, HWTYPE, PH, PV, BGSCX, BGSCY, BGVAD, BGVDT, @@ -114,7 +118,7 @@ module NINJAKUN_FG ( input MCLK, input PCLK_EN, - input RAIDERS5, + input [1:0] HWTYPE, input [8:0] PH, // CRTC input [8:0] PV, @@ -131,7 +135,7 @@ module NINJAKUN_FG wire [8:0] POSH = PH+9'd8+9'd1; wire [8:0] POSV = PV+9'd32; -wire [9:0] CHRNO = RAIDERS5 ? {2'b00, FGVDT[7:0]} : {1'b0,FGVDT[13],FGVDT[7:0]}; +wire [9:0] CHRNO = (HWTYPE == `HW_RAIDERS5 || HWTYPE == `HW_NOVA2001) ? {2'b00, FGVDT[7:0]} : {1'b0,FGVDT[13],FGVDT[7:0]}; reg [31:0] CDT; reg [4:0] PAL; @@ -139,7 +143,7 @@ reg [3:0] OUT; always @( posedge MCLK ) begin if (PCLK_EN) case(POSH[2:0]) - 0: begin OUT <= CDT[7:4] ; PAL <= RAIDERS5 ? {1'b0, FGVDT[15:12]} : FGVDT[12:8]; end + 0: begin OUT <= CDT[7:4] ; PAL <= HWTYPE == `HW_RAIDERS5 ? {1'b0, FGVDT[15:12]} : FGVDT[12:8]; end 1: begin OUT <= CDT[3:0] ; FGVAD <= {POSV[7:3],POSH[7:3]}; end 2: begin OUT <= CDT[15:12]; end 3: begin OUT <= CDT[11:8] ; end @@ -150,7 +154,7 @@ always @( posedge MCLK ) begin endcase end -assign FGOUT = { PAL[4], 1'b0, PAL[3:0], OUT }; +assign FGOUT = HWTYPE == `HW_NOVA2001 ? (OUT == 4'h1 ? PAL : { PAL[4], OUT }) : { PAL[4], 1'b0, PAL[3:0], OUT }; endmodule @@ -160,7 +164,7 @@ module NINJAKUN_BG ( input MCLK, input PCLK_EN, - input RAIDERS5, + input [1:0] HWTYPE, input [8:0] PH, // CRTC input [8:0] PV, @@ -177,10 +181,12 @@ module NINJAKUN_BG output [8:0] BGOUT // OUTPUT ); -wire [8:0] POSH = PH+BGSCX+9'd2; +wire [8:0] POSH = PH+BGSCX+(HWTYPE == `HW_NOVA2001 ? 9'd9 : 9'd2) /* synthesis keep */; wire [8:0] POSV = PV+BGSCY+9'd32; -wire [9:0] CHRNO = RAIDERS5 ? {1'b0, BGVDT[8:0]} : {BGVDT[15:14],BGVDT[7:0]}; +wire [9:0] CHRNO = HWTYPE == `HW_RAIDERS5 ? {1'b0, BGVDT[8:0]} : + HWTYPE == `HW_NOVA2001 ? {2'b10, BGVDT[7:0]}: + {BGVDT[15:14],BGVDT[7:0]}; reg [31:0] CDT; reg [3:0] PAL; @@ -188,7 +194,7 @@ reg [3:0] OUT; always @( posedge MCLK ) begin if (PCLK_EN) case(POSH[2:0]) - 0: begin OUT <= CDT[7:4] ; PAL <= RAIDERS5 ? BGVDT[15:12] : BGVDT[11:8]; end + 0: begin OUT <= CDT[7:4] ; PAL <= HWTYPE == `HW_RAIDERS5 ? BGVDT[15:12] : BGVDT[11:8]; end 1: begin OUT <= CDT[3:0] ; BGVAD <= {POSV[7:3],POSH[7:3]}; end 2: begin OUT <= CDT[15:12]; end 3: begin OUT <= CDT[11:8] ; end @@ -199,6 +205,6 @@ always @( posedge MCLK ) begin endcase end -assign BGOUT = { 1'b1, PAL, OUT }; +assign BGOUT = HWTYPE == `HW_NOVA2001 ? {1'b1, (OUT == 4'h1 ? PAL : OUT)} : { 1'b1, PAL, OUT }; endmodule diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/pll.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/pll.v index 2ce015c4..fb6269e6 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/pll.v +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/pll.v @@ -39,23 +39,27 @@ module pll ( inclk0, c0, + c1, locked); input inclk0; output c0; + output c1; output locked; wire [4:0] sub_wire0; wire sub_wire2; - wire [0:0] sub_wire5 = 1'h0; - wire [0:0] sub_wire1 = sub_wire0[0:0]; - wire c0 = sub_wire1; + wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; wire locked = sub_wire2; - wire sub_wire3 = inclk0; - wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + wire c0 = sub_wire3; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; altpll altpll_component ( - .inclk (sub_wire4), + .inclk (sub_wire5), .clk (sub_wire0), .locked (sub_wire2), .activeclock (), @@ -96,8 +100,12 @@ module pll ( altpll_component.bandwidth_type = "AUTO", altpll_component.clk0_divide_by = 9, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 16, + altpll_component.clk0_multiply_by = 32, altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 9, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 16, + altpll_component.clk1_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -131,7 +139,7 @@ module pll ( altpll_component.port_scanread = "PORT_UNUSED", altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk1 = "PORT_USED", altpll_component.port_clk2 = "PORT_UNUSED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", @@ -172,8 +180,11 @@ endmodule // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "48.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -194,18 +205,26 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "96.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "48.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -228,19 +247,26 @@ endmodule // Retrieval info: PRIVATE: SPREAD_USE STRING "0" // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -273,7 +299,7 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" @@ -292,11 +318,13 @@ endmodule // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/sdram.sv b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/sdram.sv index ed64b325..60ad31c7 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/sdram.sv +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/sdram.sv @@ -65,9 +65,11 @@ module sdram ( output reg [31:0] fg_q, input [16:2] sp_addr, output reg [31:0] sp_q, - output reg sp_rdy + output sp_rdy ); +parameter MHZ = 80; // 80 MHz default clock, adjust to calculate the refresh rate correctly + localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8 localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved @@ -78,7 +80,7 @@ localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single acc localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; // 64ms/8192 rows = 7.8us -> 842 cycles@108MHz -localparam RFRSH_CYCLES = 10'd842; +localparam RFRSH_CYCLES = 16'd78*MHZ/10; // --------------------------------------------------------------------- // ------------------------ cycle state machine ------------------------ @@ -222,6 +224,9 @@ always @(*) begin end end +assign sp_rdy = |sp_rdy_r; +reg [1:0] sp_rdy_r; + always @(posedge clk) begin // permanently latch ram data to reduce delays @@ -231,7 +236,7 @@ always @(posedge clk) begin sd_cmd <= CMD_NOP; // default: idle refresh_cnt <= refresh_cnt + 1'd1; - sp_rdy <= 0; + sp_rdy_r <= {sp_rdy_r[0], 1'b0}; if(init) begin // initialization takes place at the end of the reset phase @@ -357,7 +362,7 @@ always @(posedge clk) begin PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end PORT_FG : begin fg_q[31:16] <= sd_din; end PORT_BG : begin bg_q[31:16] <= sd_din; end - PORT_SP : begin sp_q[31:16] <= sd_din; sp_rdy <= 1; end + PORT_SP : begin sp_q[31:16] <= sd_din; sp_rdy_r <= 2'b11; end default: ; endcase; end