diff --git a/Arcade_MiST/Konami Green Beret Hardware/GBeret.qpf b/Arcade_MiST/Konami Green Beret Hardware/GBeret.qpf
deleted file mode 100644
index bb23c1b4..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/GBeret.qpf
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 16:52:48 September 16, 2019
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "16:52:48 September 16, 2019"
-
-# Revisions
-
-PROJECT_REVISION = "GBeret"
diff --git a/Arcade_MiST/Konami Green Beret Hardware/GBeret.qsf b/Arcade_MiST/Konami Green Beret Hardware/GBeret.qsf
deleted file mode 100644
index 1d2a910f..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/GBeret.qsf
+++ /dev/null
@@ -1,219 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 17:51:13 September 16, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# GBeret_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PIN_49 -to SDRAM_A[0]
-set_location_assignment PIN_44 -to SDRAM_A[1]
-set_location_assignment PIN_42 -to SDRAM_A[2]
-set_location_assignment PIN_39 -to SDRAM_A[3]
-set_location_assignment PIN_4 -to SDRAM_A[4]
-set_location_assignment PIN_6 -to SDRAM_A[5]
-set_location_assignment PIN_8 -to SDRAM_A[6]
-set_location_assignment PIN_10 -to SDRAM_A[7]
-set_location_assignment PIN_11 -to SDRAM_A[8]
-set_location_assignment PIN_28 -to SDRAM_A[9]
-set_location_assignment PIN_50 -to SDRAM_A[10]
-set_location_assignment PIN_30 -to SDRAM_A[11]
-set_location_assignment PIN_32 -to SDRAM_A[12]
-set_location_assignment PIN_83 -to SDRAM_DQ[0]
-set_location_assignment PIN_79 -to SDRAM_DQ[1]
-set_location_assignment PIN_77 -to SDRAM_DQ[2]
-set_location_assignment PIN_76 -to SDRAM_DQ[3]
-set_location_assignment PIN_72 -to SDRAM_DQ[4]
-set_location_assignment PIN_71 -to SDRAM_DQ[5]
-set_location_assignment PIN_69 -to SDRAM_DQ[6]
-set_location_assignment PIN_68 -to SDRAM_DQ[7]
-set_location_assignment PIN_86 -to SDRAM_DQ[8]
-set_location_assignment PIN_87 -to SDRAM_DQ[9]
-set_location_assignment PIN_98 -to SDRAM_DQ[10]
-set_location_assignment PIN_99 -to SDRAM_DQ[11]
-set_location_assignment PIN_100 -to SDRAM_DQ[12]
-set_location_assignment PIN_101 -to SDRAM_DQ[13]
-set_location_assignment PIN_103 -to SDRAM_DQ[14]
-set_location_assignment PIN_104 -to SDRAM_DQ[15]
-set_location_assignment PIN_58 -to SDRAM_BA[0]
-set_location_assignment PIN_51 -to SDRAM_BA[1]
-set_location_assignment PIN_85 -to SDRAM_DQMH
-set_location_assignment PIN_67 -to SDRAM_DQML
-set_location_assignment PIN_60 -to SDRAM_nRAS
-set_location_assignment PIN_64 -to SDRAM_nCAS
-set_location_assignment PIN_66 -to SDRAM_nWE
-set_location_assignment PIN_59 -to SDRAM_nCS
-set_location_assignment PIN_33 -to SDRAM_CKE
-set_location_assignment PIN_43 -to SDRAM_CLK
-
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
-
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name TOP_LEVEL_ENTITY "gberet_mist"
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name ENABLE_SIGNALTAP OFF
-set_global_assignment -name USE_SIGNALTAP_FILE output_files/gberet.stp
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/gberet_mist.sv
-set_global_assignment -name VERILOG_FILE rtl/FPGA_GreenBeret.v
-set_global_assignment -name VERILOG_FILE rtl/GreenBeret_MAIN.v
-set_global_assignment -name VERILOG_FILE rtl/GreenBeret_VIDEO.v
-set_global_assignment -name VERILOG_FILE rtl/GreenBeret_SOUND.v
-set_global_assignment -name VERILOG_FILE rtl/SN76496.v
-set_global_assignment -name VERILOG_FILE rtl/hvgen.v
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VERILOG_FILE rtl/pll.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
-set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
-set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Konami Green Beret Hardware/GBeret.sdc b/Arcade_MiST/Konami Green Beret Hardware/GBeret.sdc
deleted file mode 100644
index 80fe5371..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/GBeret.sdc
+++ /dev/null
@@ -1,134 +0,0 @@
-## Generated SDC file "vectrex_MiST.out.sdc"
-
-## Copyright (C) 1991-2013 Altera Corporation
-## Your use of Altera Corporation's design tools, logic functions
-## and other software and tools, and its AMPP partner logic
-## functions, and any output files from any of the foregoing
-## (including device programming or simulation files), and any
-## associated documentation or information are expressly subject
-## to the terms and conditions of the Altera Program License
-## Subscription Agreement, Altera MegaCore Function License
-## Agreement, or other applicable license agreement, including,
-## without limitation, that your use is for the sole purpose of
-## programming logic devices manufactured by Altera and sold by
-## Altera or its authorized distributors. Please refer to the
-## applicable agreement for further details.
-
-
-## VENDOR "Altera"
-## PROGRAM "Quartus II"
-## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-
-## DATE "Sun Jun 24 12:53:00 2018"
-
-##
-## DEVICE "EP3C25E144C8"
-##
-
-# Clock constraints
-
-# Automatically constrain PLL and other generated clocks
-derive_pll_clocks -create_base_clocks
-
-# Automatically calculate clock uncertainty to jitter and other effects.
-derive_clock_uncertainty
-
-# tsu/th constraints
-
-# tco constraints
-
-# tpd constraints
-
-#**************************************************************
-# Time Information
-#**************************************************************
-
-set_time_format -unit ns -decimal_places 3
-
-
-
-#**************************************************************
-# Create Clock
-#**************************************************************
-
-create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
-
-set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
-set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
-#**************************************************************
-# Create Generated Clock
-#**************************************************************
-
-
-#**************************************************************
-# Set Clock Latency
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Clock Uncertainty
-#**************************************************************
-
-#**************************************************************
-# Set Input Delay
-#**************************************************************
-
-set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
-set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
-set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
-set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
-set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
-set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
-
-set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
-set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
-
-#**************************************************************
-# Set Output Delay
-#**************************************************************
-
-set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
-set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
-set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
-set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
-set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
-
-set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
-set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
-
-#**************************************************************
-# Set Clock Groups
-#**************************************************************
-
-set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
-
-#**************************************************************
-# Set False Path
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Multicycle Path
-#**************************************************************
-
-set_multicycle_path -to {VGA_*[*]} -setup 2
-set_multicycle_path -to {VGA_*[*]} -hold 1
-
-#**************************************************************
-# Set Maximum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Minimum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Input Transition
-#**************************************************************
-
diff --git a/Arcade_MiST/Konami Green Beret Hardware/README.txt b/Arcade_MiST/Konami Green Beret Hardware/README.txt
deleted file mode 100644
index 848ece36..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/README.txt
+++ /dev/null
@@ -1,87 +0,0 @@
--- Arcade: Rush'n Attack (Green Beret) port to MiST by Slingshot
---
--- Usage:
--- - Create ROM and ARC files from the MRA files in the meta directory
--- using the MRA utility.
--- Example: mra -A -z /path/to/mame/roms "Green Beret.mra"
--- - Copy the ROM files to the root of the SD Card
--- - Copy the RBF and ARC files to the same folder on the SD Card
---
--- MRA utility: https://github.com/sebdel/mra-tools-c/
---
--- Keyboard inputs :
---
--- ESC : Coin
--- F2 : Start 2 players
--- F1 : Start 1 player
--- UP,DOWN,LEFT,RIGHT arrows : Movements
--- SPACE : Trig1
--- Left Alt : Trig2
---
----------------------------------------------------------------------------------
---
--- Arcade: Rush'n Attack (Green Beret) port to MiSTer by MiSTer-X
--- 14 December 2019
--- https://github.com/MrX-8B/MiSTer-Arcade-GreenBeret
---
----------------------------------------------------------------------------------
--- FPGA Mr.GOEMON for XILINX Spartan-6
-------------------------------------------------
--- Copyright (c) 2013 MiSTer-X
----------------------------------------------------------------------------------
--- T80/T80s - Version : 0247
-------------------------------
--- Z80 compatible microprocessor core
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
----------------------------------------------------------------------------------
---
---
--- Keyboard inputs :
---
--- F2 : Coin + Start 2 players
--- F1 : Coin + Start 1 player
--- UP,DOWN,LEFT,RIGHT arrows : Movements
--- SPACE : Trig1
--- Ctrl : Trig2
---
--- MAME/IPAC/JPAC Style Keyboard inputs:
--- 5 : Coin 1
--- 6 : Coin 2
--- 1 : Start 1 Player
--- 2 : Start 2 Players
--- R,F,D,G : Player 2 Movements
--- A : Trig1
--- S : Trig2
---
--- Joystick support.
---
---
----------------------------------------------------------------------------------
-
- *** Attention ***
-
-ROM is not included. In order to use this arcade, you need to provide a correct ROM file.
-
-Find this zip file somewhere. You need to find the file exactly as required.
-Do not rename other zip files even if they also represent the same game - they are not compatible!
-The name of zip is taken from M.A.M.E. project, so you can get more info about
-hashes and contained files there.
-
-To generate the ROM using Windows:
-1) Copy the zip into "releases" directory
-2) Execute bat file - it will show the name of zip file containing required files.
-3) Put required zip into the same directory and execute the bat again.
-4) If everything will go without errors or warnings, then you will get the a.*.rom file.
-5) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
-
-To generate the ROM using Linux/MacOS:
-1) Copy the zip into "releases" directory
-2) Execute build_rom.sh
-3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
-
-To generate the ROM using MiSTer:
-1) scp "releases" directory along with the zip file onto MiSTer:/media/fat/
-2) Using OSD execute build_rom.sh
-3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
-
diff --git a/Arcade_MiST/Konami Green Beret Hardware/clean.bat b/Arcade_MiST/Konami Green Beret Hardware/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/clean.bat
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Konami Green Beret Hardware/meta/Green Beret.mra b/Arcade_MiST/Konami Green Beret Hardware/meta/Green Beret.mra
deleted file mode 100644
index d08e94df..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/meta/Green Beret.mra
+++ /dev/null
@@ -1,30 +0,0 @@
-
- Green Beret
- 0216
- gberet
- 201911270000
- 1985
- Konami
- Army / Fighter
- gberet
-
- 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Arcade_MiST/Konami Green Beret Hardware/meta/JailBreak.mra b/Arcade_MiST/Konami Green Beret Hardware/meta/JailBreak.mra
deleted file mode 100644
index bfe3d576..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/meta/JailBreak.mra
+++ /dev/null
@@ -1,25 +0,0 @@
-
- Jail Break
- 0216
- jailbrekb
- 202004180000
- 1985
- Konami
- Army / Fighter
- jailbrekb
-
- 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Arcade_MiST/Konami Green Beret Hardware/meta/Mr. Goemon.mra b/Arcade_MiST/Konami Green Beret Hardware/meta/Mr. Goemon.mra
deleted file mode 100644
index 53baa131..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/meta/Mr. Goemon.mra
+++ /dev/null
@@ -1,26 +0,0 @@
-
- Mr. Goemon
- 0216
- mrgoemon
- 201911270000
- 1985
- Konami
- Army / Fighter
- gberet
-
- 2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Arcade_MiST/Konami Green Beret Hardware/meta/Rush'n Attack (US).mra b/Arcade_MiST/Konami Green Beret Hardware/meta/Rush'n Attack (US).mra
deleted file mode 100644
index 09c5f0b9..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/meta/Rush'n Attack (US).mra
+++ /dev/null
@@ -1,27 +0,0 @@
-
- Rush'n Attack (US)
- 0216
- rushatck
- 201911270000
- 1985
- Konami
- Army / Fighter
- gberet
-
- 1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Arcade_MiST/Konami Green Beret Hardware/rtl/FPGA_GreenBeret.v b/Arcade_MiST/Konami Green Beret Hardware/rtl/FPGA_GreenBeret.v
deleted file mode 100644
index 494cefd7..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/rtl/FPGA_GreenBeret.v
+++ /dev/null
@@ -1,124 +0,0 @@
-/*******************************************************
- FPGA Implimentation of "Green Beret" (Top Module)
-********************************************************/
-// Copyright (c) 2013,19 MiSTer-X
-// Converted to single clock with clock enables and SDRAM
-// external ROM storage by (c) 2019 Slingshot
-
-module FPGA_GreenBeret
-(
- input clk48M,
- input reset,
-
- input [5:0] INP0, // Control Panel
- input [5:0] INP1,
- input [2:0] INP2,
-
- input [7:0] DSW0, // DipSWs
- input [7:0] DSW1,
- input [7:0] DSW2,
-
-
- input [8:0] PH, // PIXEL H
- input [8:0] PV, // PIXEL V
- output PCLK, // PIXEL CLOCK (to VGA encoder)
- output PCLK_EN,
- output [11:0] POUT, // PIXEL OUT
-
- output [7:0] SND, // Sound Out
-
- output [15:0] CPU_ROMA,
- input [7:0] CPU_ROMDT,
-
- output [15:1] SP_ROMA,
- input [15:0] SP_ROMD,
-
- input ROMCL, // Downloaded ROM image
- input [17:0] ROMAD,
- input [7:0] ROMDT,
- input ROMEN
-);
-
-// Clocks
-wire clk6M, clk3M_en, clk6M_en;
-CLKGEN clks( clk48M, clk6M, clk3M_en, clk6M_en );
-
-wire VCLKx8 = clk48M;
-wire VCLK = clk6M;
-
-wire CPUCLK_EN = clk3M_en;
-wire VCLK_EN = clk6M_en;
-
-// Main
-wire CPUMX, CPUWR, VIDDV;
-wire [7:0] CPUWD, VIDRD;
-wire [15:0] CPUAD;
-
-
-MAIN cpu
-(
- clk48M, CPUCLK_EN, reset,
- PH,PV,
- INP0,INP1,INP2,
- DSW0,DSW1,DSW2,
-
- CPUMX, CPUAD,
- CPUWR, CPUWD,
- VIDDV, VIDRD,
-
- CPU_ROMA, CPU_ROMDT,
- ROMCL,ROMAD,ROMDT,ROMEN
-);
-
-
-// Video
-VIDEO vid
-(
- VCLKx8, VCLK, VCLK_EN,
- PH, PV, 1'b0, 1'b0,
- PCLK, PCLK_EN, POUT,
-
- CPUMX, CPUAD,
- CPUWR, CPUWD,
- VIDDV, VIDRD,
-
- SP_ROMA, SP_ROMD,
- ROMCL,ROMAD,ROMDT,ROMEN
-);
-
-
-// Sound
-SOUND snd
-(
- clk48M, reset,
- SND,
-
- CPUMX, CPUAD,
- CPUWR, CPUWD
-);
-
-endmodule
-
-
-//----------------------------------
-// Clock Generator
-//----------------------------------
-module CLKGEN
-(
- input clk48M,
-
- output clk6M,
- output clk3M_en,
- output clk6M_en
-);
-
-reg [3:0] clkdiv;
-always @( posedge clk48M ) clkdiv <= clkdiv+4'd1;
-
-assign clk6M = clkdiv[2];
-assign clk3M_en = clkdiv[3:0] == 4'b0111;
-assign clk6M_en = clkdiv[2:0] == 4'b011;
-
-endmodule
-
-
diff --git a/Arcade_MiST/Konami Green Beret Hardware/rtl/GreenBeret_MAIN.v b/Arcade_MiST/Konami Green Beret Hardware/rtl/GreenBeret_MAIN.v
deleted file mode 100644
index cd76b0c8..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/rtl/GreenBeret_MAIN.v
+++ /dev/null
@@ -1,215 +0,0 @@
-/******************************************************
- FPGA Implimentation of "Green Beret" (Main Part)
-*******************************************************/
-// Copyright (c) 2013,19 MiSTer-X
-
-module MAIN
-(
- input MCLK,
- input CLKEN,
- input RESET,
-
- input [8:0] PH,
- input [8:0] PV,
-
- input [5:0] INP0,
- input [5:0] INP1,
- input [2:0] INP2,
-
- input [7:0] DSW0,
- input [7:0] DSW1,
- input [7:0] DSW2,
-
- output CPUMX,
- output [15:0] CPUAD,
- output CPUWR,
- output [7:0] CPUWD,
-
- input VIDDV,
- input [7:0] VIDRD,
-
- output [15:0] ROMA,
- input [7:0] ROMDT,
-
- input DLCL,
- input [17:0] DLAD,
- input [7:0] DLDT,
- input DLEN
-);
-
-//
-// Z80 SoftCore
-//
-wire [7:0] CPUID;
-wire cpu_irq, cpu_nmi;
-wire iCPUMX,iCPUWR;
-
-T80se z80(
- .CLK_n(MCLK),
- .CLKEN(CLKEN),
- .RESET_n(~RESET),
- .A(CPUAD),
- .DI(CPUID),
- .DO(CPUWD),
- .INT_n(~cpu_irq),
- .NMI_n(~cpu_nmi),
- .MREQ_n(iCPUMX),
- .WR_n(iCPUWR),
- .BUSRQ_n(1'b1),
- .WAIT_n(1'b1)
-);
-
-assign CPUMX = ~iCPUMX;
-assign CPUWR = ~iCPUWR;
-
-
-//
-// Instruction ROMs (Banked)
-//
-wire [2:0] ROMBK;
-//wire [7:0] ROMDT;
-wire ROMDV;
-
-wire [14:0] AD1 = (CPUAD[15:11] == 5'b11111) ? {1'b1,ROMBK,CPUAD[10:0]} : {1'b0,CPUAD[13:0]};
-
-//wire [7:0] DT0, DT1;
-//DLROM #(15,8) r0(CL,AD[14:0],DT0, DLCL,DLAD,DLDT,DLEN & (DLAD[17:15]==3'b00_0));
-//DLROM #(15,8) r1(CL, AD1,DT1, DLCL,DLAD,DLDT,DLEN & (DLAD[17:15]==3'b00_1));
-//assign ROMDT = CPUAD[15] ? DT1 : DT0;
-
-assign ROMDV = ((CPUAD[15:11] == 5'b11111)|(CPUAD[15:14] != 2'b11)) & CPUMX;
-assign ROMA = CPUAD[15] ? {1'b1, AD1} : {1'b0, CPUAD[14:0]};
-//
-//
-// Input Ports (HID & DIPSWs)
-//
-wire CS_ISYS = (CPUAD[15:0] == 16'hF603) & CPUMX;
-wire CS_IP01 = (CPUAD[15:0] == 16'hF602) & CPUMX;
-wire CS_IP02 = (CPUAD[15:0] == 16'hF601) & CPUMX;
-wire CS_DSW2 = (CPUAD[15:0] == 16'hF600) & CPUMX;
-wire CS_DSW0 = (CPUAD[15:8] == 8'hF2 ) & CPUMX;
-wire CS_DSW1 = (CPUAD[15:8] == 8'hF4 ) & CPUMX;
-
-`include "HIDDEF.i"
-wire [7:0] ISYS = ~{`none,`none,`none,`P2ST,`P1ST,`none,`none,`COIN};
-wire [7:0] IP01 = ~{`none,`none,`P1TB,`P1TA,`P1DW,`P1UP,`P1RG,`P1LF};
-wire [7:0] IP02 = ~{`none,`none,`P2TB,`P2TA,`P2DW,`P2UP,`P2RG,`P2LF};
-
-//
-// CPU Input Data Selector
-//
-DSEL9 dsel(
- CPUID,
- VIDDV,VIDRD,
- ROMDV,ROMDT,
- CS_ISYS,ISYS,
- CS_IP01,IP01,
- CS_IP02,IP02,
- CS_DSW0,DSW0,
- CS_DSW1,DSW1,
- CS_DSW2,DSW2
-);
-
-
-//
-// Interrupt Generator & ROM Bank Selector
-//
-IRQGEN irqg(
- RESET,PH,PV,
- MCLK,CLKEN,CPUAD,CPUWD,CPUMX & CPUWR,
- cpu_irq,cpu_nmi,
- ROMBK
-);
-
-
-endmodule
-
-
-module IRQGEN
-(
- input RESET,
- input [8:0] PH,
- input [8:0] PV,
-
- input MCLK,
- input CLKEN,
- input [15:0] CPUAD,
- input [7:0] CPUWD,
- input CPUWE,
-
- output reg cpu_irq,
- output reg cpu_nmi,
-
- output reg [2:0] ROMBK
-);
-
-
-wire CS_FSCW = (CPUAD[15:0] == 16'hE044) & CPUWE;
-wire CS_CCTW = (CPUAD[15:0] == 16'hF000) & CPUWE;
-
-reg [2:0] irqmask;
-reg [8:0] tick;
-wire [8:0] irqs = (~tick) & (tick+9'd1);
-reg [8:0] pPV;
-reg sync;
-
-always @( posedge MCLK ) begin
- if (RESET) begin
- ROMBK <= 0;
- irqmask <= 0;
- cpu_nmi <= 0;
- cpu_irq <= 0;
- tick <= 0;
- pPV <= 1;
- sync <= 1;
- end
- else if (CLKEN) begin
- if ( CS_CCTW ) ROMBK <= CPUWD[7:5];
- if ( CS_FSCW ) begin
- irqmask <= CPUWD[2:0];
- if (~CPUWD[0]) cpu_nmi <= 0;
- if (~CPUWD[1]) cpu_irq <= 0;
- else if (~CPUWD[2]) cpu_irq <= 0;
- end
- else if (pPV != PV) begin
- if (PV[3:0]==0) begin
- if (sync & (PV==9'd0)) begin tick <= 9'd0; sync <= 0; end
- else tick <= (tick+9'd1);
- cpu_nmi <= irqs[0] & irqmask[0];
- cpu_irq <=(irqs[3] & irqmask[1]) | (irqs[4] & irqmask[2]);
- pPV <= PV;
- end
- end
- end
-end
-
-endmodule
-
-
-module DSEL9
-(
- output [7:0] out,
- input en0, input [7:0] in0,
- input en1, input [7:0] in1,
- input en2, input [7:0] in2,
- input en3, input [7:0] in3,
- input en4, input [7:0] in4,
- input en5, input [7:0] in5,
- input en6, input [7:0] in6,
- input en7, input [7:0] in7,
- input en8, input [7:0] in8
-);
-
-assign out = en0 ? in0 :
- en1 ? in1 :
- en2 ? in2 :
- en3 ? in3 :
- en4 ? in4 :
- en5 ? in5 :
- en6 ? in6 :
- en7 ? in7 :
- en8 ? in8 :
- 8'h00;
-
-endmodule
-
diff --git a/Arcade_MiST/Konami Green Beret Hardware/rtl/GreenBeret_SOUND.v b/Arcade_MiST/Konami Green Beret Hardware/rtl/GreenBeret_SOUND.v
deleted file mode 100644
index e31024d9..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/rtl/GreenBeret_SOUND.v
+++ /dev/null
@@ -1,53 +0,0 @@
-/********************************************************
- FPGA Implimentation of "Green Beret" (Sound Part)
-*********************************************************/
-// Copyright (c) 2013 MiSTer-X
-
-module SOUND
-(
- input MCLK,
- input reset,
-
- output [7:0] SNDOUT,
-
- input CPUMX,
- input [15:0] CPUAD,
- input CPUWR,
- input [7:0] CPUWD
-);
-
-wire CS_SNDLC = ( CPUAD[15:8] == 8'hF2 ) & CPUMX & CPUWR;
-wire CS_SNDWR = ( CPUAD[15:8] == 8'hF4 ) & CPUMX;
-
-reg [7:0] SNDLATCH;
-always @( posedge MCLK or posedge reset ) begin
- if (reset) SNDLATCH <= 0;
- else begin
- if ( CS_SNDLC ) SNDLATCH <= CPUWD;
- end
-end
-
-wire sndclk, sndclk_en;
-sndclkgen scgen( MCLK, sndclk, sndclk_en );
-
-SN76496 sgn( MCLK, sndclk_en, reset, CS_SNDWR, CPUWR, SNDLATCH, 4'b1111, SNDOUT );
-
-endmodule
-
-
-/*
- Clock Generator
- in: 50000000Hz -> out: 1600000Hz
-*/
-module sndclkgen( input in, output reg out, output reg out_en );
-reg [6:0] count;
-always @( posedge in ) begin
- out_en <= 0;
- if (count > 7'd117) begin
- count <= count - 7'd117;
- out <= ~out;
- if (~out) out_en <= 1;
- end
- else count <= count + 7'd8;
-end
-endmodule
diff --git a/Arcade_MiST/Konami Green Beret Hardware/rtl/GreenBeret_VIDEO.v b/Arcade_MiST/Konami Green Beret Hardware/rtl/GreenBeret_VIDEO.v
deleted file mode 100644
index d4bb272b..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/rtl/GreenBeret_VIDEO.v
+++ /dev/null
@@ -1,295 +0,0 @@
-/*******************************************************
- FPGA Implimentation of "Green Beret" (Video Part)
-********************************************************/
-// Copyright (c) 2013,19 MiSTer-X
-
-module VIDEO
-(
- input VCLKx8,
- input VCLK,
- input VCLK_EN,
-
- input [8:0] HP,
- input [8:0] VP,
-
- input PALD,
- input CPUD,
-
- output PCLK,
- output PCLK_EN,
- output [11:0] POUT,
-
- input CPUMX,
- input [15:0] CPUAD,
- input CPUWR,
- input [7:0] CPUWD,
- output CPUDV,
- output [7:0] CPURD,
-
- output [15:1] SP_ROMA,
- input [15:0] SP_ROMD,
-
- input DLCL,
- input [17:0] DLAD,
- input [7:0] DLDT,
- input DLEN
-);
-
-// Video RAMs
-wire CS_CRAM = ( CPUAD[15:11] == 5'b1100_0 ) & CPUMX; // $C000-$C7FF
-wire CS_VRAM = ( CPUAD[15:11] == 5'b1100_1 ) & CPUMX; // $C800-$CFFF
-wire CS_MRAM = ( CPUAD[15:12] == 4'b1101 ) & CPUMX; // $D000-$DFFF
-wire CS_ZRM0 = ( CPUAD[15: 5] == 11'b1110_0000_000 ) & CPUMX; // $E000-$E01F
-wire CS_ZRM1 = ( CPUAD[15: 5] == 11'b1110_0000_001 ) & CPUMX; // $E020-$E03F
-wire CS_SPRB = ( CPUAD[15: 0] == 16'b1110_0000_0100_0011 ) & CPUMX; // $E043
-
-wire [7:0] OD_CRAM, OD_VRAM;
-wire [7:0] OD_MRAM;
-wire [7:0] OD_ZRM0, OD_ZRM1;
-
-assign CPUDV = CS_CRAM | CS_VRAM | CS_MRAM | CS_ZRM0 | CS_ZRM1 ;
-
-assign CPURD = CS_CRAM ? OD_CRAM :
- CS_VRAM ? OD_VRAM :
- CS_MRAM ? OD_MRAM :
- CS_ZRM0 ? OD_ZRM0 :
- CS_ZRM1 ? OD_ZRM1 :
- 8'h0;
-
-
-wire [10:0] BGVA;
-wire [7:0] BGCR, BGVR;
-
-reg SPRB;
-wire [7:0] SATA;
-wire [7:0] SATD;
-wire [11:0] SAAD = {3'b000,SPRB,SATA};
-always @( posedge VCLKx8 ) if ( CS_SPRB & CPUWR ) SPRB <= ~CPUWD[3];
-
-wire [4:0] ZRMA;
-wire [7:0] ZRM0, ZRM1;
-wire [15:0] ZRMD = {ZRM1,ZRM0};
-
-dpram #(8,11) cram (.clk_a(VCLKx8), .we_a(CS_CRAM & CPUWR), .addr_a(CPUAD[10:0]), .d_a(CPUWD), .q_a(OD_CRAM), .clk_b(VCLKx8), .addr_b(BGVA), .q_b(BGCR));
-dpram #(8,11) vram (.clk_a(VCLKx8), .we_a(CS_VRAM & CPUWR), .addr_a(CPUAD[10:0]), .d_a(CPUWD), .q_a(OD_VRAM), .clk_b(VCLKx8), .addr_b(BGVA), .q_b(BGVR));
-dpram #(8,12) mram (.clk_a(VCLKx8), .we_a(CS_MRAM & CPUWR), .addr_a(CPUAD[11:0]), .d_a(CPUWD), .q_a(OD_MRAM), .clk_b(VCLKx8), .addr_b(SAAD), .q_b(SATD));
-dpram #(8, 5) zrm0 (.clk_a(VCLKx8), .we_a(CS_ZRM0 & CPUWR), .addr_a(CPUAD[ 4:0]), .d_a(CPUWD), .q_a(OD_ZRM0), .clk_b(VCLKx8), .addr_b(ZRMA), .q_b(ZRM0));
-dpram #(8, 5) zrm1 (.clk_a(VCLKx8), .we_a(CS_ZRM1 & CPUWR), .addr_a(CPUAD[ 4:0]), .d_a(CPUWD), .q_a(OD_ZRM1), .clk_b(VCLKx8), .addr_b(ZRMA), .q_b(ZRM1));
-
-// BG Scanline Generator
-wire [8:0] BGVP = VP+9'd16;
-wire [8:0] BGHP = HP+9'd8+(ZRMD[8:0]);
-
-assign ZRMA = BGVP[7:3];
-assign BGVA = {BGVP[7:3],BGHP[8:3]};
-wire [8:0] BGCH = {BGCR[6],BGVR};
-wire [3:0] BGCL = BGCR[3:0];
-wire [1:0] BGFL = BGCR[5:4];
-
-wire [2:0] BGHH = BGHP[2:0]^{3{BGFL[0]}};
-wire [2:0] BGVV = BGVP[2:0]^{3{BGFL[1]}};
-wire [13:0] BGCA = {BGCH,BGVV[2:0],BGHH[2:1]};
-wire [0:7] BGCD;
-dpram #(8,14) bgchip(.clk_a(DLCL), .we_a(DLEN && DLAD[17:14]==4'b10_00), .addr_a(DLAD[13:0]), .d_a(DLDT), .clk_b(VCLKx8), .addr_b(BGCA), .q_b(BGCD));
-
-wire [7:0] BGCT = {BGCL,(BGHH[0] ? BGCD[4:7]:BGCD[0:3])};
-wire [3:0] BGPT;
-dpram #(8,8) bgclut(.clk_a(DLCL), .we_a(DLEN && DLAD[17:8]==10'b10_0100_0001), .addr_a(DLAD[7:0]), .d_a(DLDT), .clk_b(VCLKx8), .addr_b(BGCT), .q_b(BGPT));
-
-reg BGHI;
-always @(posedge VCLKx8) if (VCLK_EN) BGHI <= ~BGCR[7];
-
-
-// Sprite Scanline Generator
-wire [8:0] SPHP = HP+9'd9;
-wire [8:0] SPVP = VP+9'd18;
-wire [3:0] SPPT;
-SPRRENDER spr( VCLKx8,VCLK_EN, SPHP,SPVP,SATA,SATD, SPPT, SP_ROMA, SP_ROMD,DLCL,DLAD,DLDT,DLEN );
-
-
-// Color Mixer
-wire [4:0] COLMIX = (BGHI & (|BGPT)) ? {1'b1,BGPT} : (|SPPT) ? {1'b0,SPPT} : {1'b1,BGPT};
-
-
-// Palette
-reg [4:0] PALIN;
-wire [7:0] PALET;
-always @(posedge VCLKx8) if (VCLK_EN) PALIN <= PALD ? VP[6:2] : COLMIX;
-dpram #(8,5) palet(.clk_a(DLCL), .we_a(DLAD[17:5]==13'b10_0100_0010_000), .addr_a(DLAD[7:0]), .d_a(DLDT), .clk_b(VCLKx8), .addr_b(PALIN), .q_b(PALET));
-wire [7:0] PALOT = PALD ? ( (|VP[8:7]) ? 8'h0 : PALET ) : PALET;
-
-
-// Pixel Output
-assign PCLK = ~VCLK;
-assign PCLK_EN = VCLK_EN;
-assign POUT = {PALOT[7:6],2'b00,PALOT[5:3],1'b0,PALOT[2:0],1'b0};
-
-endmodule
-
-
-//----------------------------------
-// Sprite Render
-//----------------------------------
-module SPRRENDER
-(
- input VCLKx8,
- input VCLK_EN,
-
- input [8:0] SPHP,
- input [8:0] SPVP,
-
- output [7:0] SATA,
- input [7:0] SATD,
-
- output reg [3:0] SPPT,
-
- output [15:1] SP_ROMA,
- input [15:0] SP_ROMD,
-
- input DLCL,
- input [17:0] DLAD,
- input [7:0] DLDT,
- input DLEN
-);
-
-reg [3:0] memwait;
-reg [5:0] sano;
-reg [1:0] saof;
-reg [7:0] sat0, sat1, sat2, sat3;
-
-reg [3:0] phase;
-
-wire [8:0] px = {1'b0,sat2} - {sat1[7],8'h0};
-wire [7:0] py = (phase==2) ? SATD : sat3;
-wire fx = sat1[4];
-wire fy = sat1[5];
-wire [8:0] code = {sat1[6],sat0};
-wire [3:0] color = sat1[3:0];
-
-wire [8:0] ht = {1'b0,py}-SPVP;
-wire hy = (py!=0) & (ht[8:4]==5'b11111);
-
-reg [4:0] xcnt;
-wire [3:0] lx = xcnt[3:0]^{4{ fx}};
-wire [3:0] ly = ht[3:0]^{4{~fy}};
-
-wire [15:0] SPCA = {code,ly[3],lx[3],ly[2:0],lx[2:1]};
-wire [0:7] SPCD;
-assign SP_ROMA = SPCA[15:1];
-assign SPCD = SPCA[0] ? SP_ROMD[15:8] : SP_ROMD[7:0];
-//SPCHIP_ROM spchip( ~VCLKx8, SPCA, SPCD, DLCL,DLAD,DLDT,DLEN );
-
-wire [7:0] pix = {color,(lx[0] ? SPCD[4:7]:SPCD[0:3])};
-
-`define SPRITES 8'h30
-
-always @( posedge VCLKx8 ) begin
- if (SPHP==0) begin
- xcnt <= 0;
- wre <= 0;
- sano <= 0;
- saof <= 3;
- phase <= 2;
- end
- else case (phase)
- 0: /* empty */ ;
-
- 1: phase <= phase + 1'd1;
-
- 2: begin
- if (sano >= `SPRITES) phase <= 0;
- else begin
- if (hy) begin
- sat3 <= SATD;
- saof <= 2;
- phase <= phase+1'd1;
- end else begin
- sano <= sano+1'd1;
- phase <= 4'd1;
- end
- end
- end
-
- 3: phase <= phase+1'd1;
-
- 4: begin
- sat2 <= SATD;
- saof <= 1;
- phase <= phase+1'd1;
- end
-
- 5: phase <= phase+1'd1;
-
- 6: begin
- sat1 <= SATD;
- saof <= 0;
- phase <= phase+1'd1;
- end
-
- 7: phase <= phase+1'd1;
-
- 8: begin
- sat0 <= SATD;
- saof <= 3;
- sano <= sano+1'd1;
- xcnt <= 0;
- wre <= 0;
- phase <= phase+1'd1;
- memwait <= 0;
- end
-
- 9: begin
- memwait <= memwait + 1'd1;
- if (&memwait) begin
- phase <= phase + 1'd1;
- wre <= 1;
- end
- end
-
- 10: begin
- xcnt <= xcnt+1'd1;
- if (xcnt[1:0] == 2'b11) begin
- wre <= 0;
- phase <= (xcnt[3:0] == 4'hf) ? 4'd1 : 4'd9;
- end
- end
-
- default:;
- endcase
-end
-
-assign SATA = {sano,saof};
-
-
-reg wre; // write enable to line buffer
-wire sid = SPVP[0];
-wire [8:0] wpx = px+xcnt[3:0];
-
-// CLUT
-reg [9:0] lbad;
-reg [3:0] lbdt;
-reg lbwe;
-always @(posedge VCLKx8) begin
- lbad <= {~sid,wpx};
- lbwe <= wre;
-end
-wire [3:0] opix;
-
-dpram #(8,8) spclut(.clk_a(DLCL), .we_a(DLEN && DLAD[17:8]==10'b10_0100_0000), .addr_a(DLAD[7:0]), .d_a(DLDT), .clk_b(VCLKx8), .addr_b(pix), .q_b(opix));
-
-// Line-Buffer
-reg [9:0] radr0=0,radr1=1;
-wire [3:0] ispt;
-
-always @(posedge VCLKx8) begin
- radr0 <= {sid,SPHP};
- if (VCLK_EN) begin
- if (radr0!=radr1) SPPT <= ispt;
- radr1 <= radr0;
- end
-end
-
-dpram #(4,10) lbuf(.clk_a(VCLKx8), .we_a(lbwe & (opix!=0)), .addr_a(lbad), .d_a(opix), .clk_b(VCLKx8), .addr_b(radr0), .we_b(radr0==radr1), .q_b(ispt));
-
-endmodule
-
diff --git a/Arcade_MiST/Konami Green Beret Hardware/rtl/HIDDEF.i b/Arcade_MiST/Konami Green Beret Hardware/rtl/HIDDEF.i
deleted file mode 100644
index 28189de3..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/rtl/HIDDEF.i
+++ /dev/null
@@ -1,31 +0,0 @@
-// Copyright (c) 2019 MiSTer-X
-
-`ifndef __HID_DEFINITION
-`define __HID_DEFINITION
-/*
- wire [5:0] INP0 = { m_trig12, m_trig11, {m_left1, m_down1, m_right1, m_up1} };
- wire [5:0] INP1 = { m_trig22, m_trig22, {m_left2, m_down2, m_right2, m_up2} };
- wire [2:0] INP2 = { (m_coin1|m_coin2), m_start2, m_start1 };
-*/
-`define none 1'b0
-
-`define COIN INP2[2]
-`define P1ST INP2[0]
-`define P2ST INP2[1]
-
-`define P1UP INP0[0]
-`define P1DW INP0[2]
-`define P1LF INP0[3]
-`define P1RG INP0[1]
-`define P1TA INP0[4]
-`define P1TB INP0[5]
-
-`define P2UP INP1[0]
-`define P2DW INP1[2]
-`define P2LF INP1[3]
-`define P2RG INP1[1]
-`define P2TA INP1[4]
-`define P2TB INP1[5]
-
-`endif
-
diff --git a/Arcade_MiST/Konami Green Beret Hardware/rtl/SN76496.v b/Arcade_MiST/Konami Green Beret Hardware/rtl/SN76496.v
deleted file mode 100644
index 0f92ad94..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/rtl/SN76496.v
+++ /dev/null
@@ -1,174 +0,0 @@
-// Copyright (c) 2010 MiSTer-X
-
-module SN76496
-(
- input clk,
- input clken,
- input reset,
- input ce,
- input we,
- input [7:0] data,
- input [3:0] chmsk,
- output reg [7:0] sndout,
- output reg [3:0] chactv,
- output reg [2:0] lreg
-);
-
-`define RNGINI 16'h0F35
-`define RNGFB0 16'h4000
-`define RNGFB1 16'h8100
-
-function [5:0] voltbl;
-input [3:0] idx;
- case (idx)
- 4'h0: voltbl = 63;
- 4'h1: voltbl = 50;
- 4'h2: voltbl = 40;
- 4'h3: voltbl = 32;
- 4'h4: voltbl = 25;
- 4'h5: voltbl = 20;
- 4'h6: voltbl = 16;
- 4'h7: voltbl = 13;
- 4'h8: voltbl = 10;
- 4'h9: voltbl = 8;
- 4'hA: voltbl = 6;
- 4'hB: voltbl = 5;
- 4'hC: voltbl = 4;
- 4'hD: voltbl = 3;
- 4'hE: voltbl = 2;
- 4'hF: voltbl = 0;
- endcase
-endfunction
-
-reg [3:0] clks;
-
-reg [2:0] nzc;
-reg [9:0] fq0, fq1, fq2;
-reg [9:0] fc0, fc1, fc2;
-reg [5:0] fv0, fv1, fv2, fv3;
-reg [5:0] _fv0,_fv1,_fv2,_fv3;
-reg fo0, fo1, fo2;
-
-reg [15:0] rng = `RNGINI;
-wire [15:0] rfb = rng[0] ? ( nzc[2] ? `RNGFB1 : `RNGFB0 ) : 16'h0;
-
-wire [1:0] nfq = nzc[1:0];
-wire [10:0] fq3 = ( nfq == 2'b00 ) ? 11'd64 :
- ( nfq == 2'b01 ) ? 11'd128 :
- ( nfq == 2'b10 ) ? 11'd256 : fq2;
-reg [10:0] fc3;
-wire fo3 = rng[0];
-
-wire [7:0] o0 = ( fo0 & chmsk[0] ) ? { 1'b0, fv0, 1'b0 } : 8'h0;
-wire [7:0] o1 = ( fo1 & chmsk[1] ) ? { 1'b0, fv1, 1'b0 } : 8'h0;
-wire [7:0] o2 = ( fo2 & chmsk[2] ) ? { 1'b0, fv2, 1'b0 } : 8'h0;
-wire [7:0] o3 = ( fo3 & chmsk[3] ) ? { 1'b0, fv3, 1'b0 } : 8'h0;
-
-wire [8:0] sndmix = o0 + o1 + o2 + o3;
-
-always @( posedge clk or posedge reset ) begin
- if ( reset ) begin
- lreg <= 0;
- _fv0 <= 0;
- _fv1 <= 0;
- _fv2 <= 0;
- _fv3 <= 0;
- fq0 <= 0;
- fq1 <= 0;
- fq2 <= 0;
- nzc <= 0;
- chactv <= 0;
- end
- else begin
- // Register write
- if ( ce & we ) begin
- if ( data[7] ) begin
- lreg <= data[6:4];
- case ( data[6:4] )
- 3'h0: fq0[3:0] <= data[3:0];
- 3'h2: fq1[3:0] <= data[3:0];
- 3'h4: fq2[3:0] <= data[3:0];
- 3'h1: begin _fv0 <= voltbl(data[3:0]); chactv[0] <= (~data[3]); end
- 3'h3: begin _fv1 <= voltbl(data[3:0]); chactv[1] <= (~data[3]); end
- 3'h5: begin _fv2 <= voltbl(data[3:0]); chactv[2] <= (~data[3]); end
- 3'h7: begin _fv3 <= voltbl(data[3:0]); chactv[3] <= (~data[3]); end
- 3'h6: begin nzc <= data[2:0]; end
- endcase
- end
- else begin
- case ( lreg )
- 3'h0: fq0[9:4] <= data[5:0];
- 3'h2: fq1[9:4] <= data[5:0];
- 3'h4: fq2[9:4] <= data[5:0];
- default: begin end
- endcase
- end
- end
- end
-end
-
-
-always @( posedge clk or posedge reset ) begin
- // Reset
- if ( reset ) begin
- sndout <= 0;
- fv0 <= 0;
- fv1 <= 0;
- fv2 <= 0;
- fv3 <= 0;
- fc0 <= 0;
- fc1 <= 0;
- fc2 <= 0;
- fc3 <= 0;
- fo0 <= 0;
- fo1 <= 0;
- fo2 <= 0;
- clks <= 0;
- rng <= `RNGINI;
- end
- else if (clken) begin
-
- // OSCs update
- clks <= clks+3'd1;
- if ( clks == 0 ) begin
-
- fv0 <= _fv0;
- fv1 <= _fv1;
- fv2 <= _fv2;
- fv3 <= _fv3;
-
- if ( fc0 == 0 ) begin
- fc0 <= fq0;
- fo0 <= ~fo0;
- end
- else fc0 <= fc0-10'd1;
-
- if ( fc1 == 0 ) begin
- fc1 <= fq1;
- fo1 <= ~fo1;
- end
- else fc1 <= fc1-10'd1;
-
- if ( fc2 == 0 ) begin
- fc2 <= fq2;
- fo2 <= ~fo2;
- end
- else fc2 <= fc2-10'd1;
-
- // NoiseGen update
- if ( fc3 == 0 ) begin
- fc3 <= fq3;
- rng <= { 1'b0, rng[15:1] } ^ rfb;
- end
- else fc3 <= fc3-11'd1;
-
- // Sound update
- sndout <= {8{sndmix[8]}}|(sndmix[7:0]);
-
- end
-
- end
-
-end
-
-endmodule
diff --git a/Arcade_MiST/Konami Green Beret Hardware/rtl/build_id.tcl b/Arcade_MiST/Konami Green Beret Hardware/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/rtl/build_id.tcl
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
- # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
- set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
- set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
- # Create a Verilog file for output
- set outputFileName "rtl/build_id.v"
- set outputFile [open $outputFileName "w"]
-
- # Output the Verilog source
- puts $outputFile "`define BUILD_DATE \"$buildDate\""
- puts $outputFile "`define BUILD_TIME \"$buildTime\""
- close $outputFile
-
- # Send confirmation message to the Messages window
- post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
- post_message "Date: $buildDate"
- post_message "Time: $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Konami Green Beret Hardware/rtl/dpram.vhd b/Arcade_MiST/Konami Green Beret Hardware/rtl/dpram.vhd
deleted file mode 100644
index 284194c5..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/rtl/dpram.vhd
+++ /dev/null
@@ -1,81 +0,0 @@
--- -----------------------------------------------------------------------
---
--- Syntiac's generic VHDL support files.
---
--- -----------------------------------------------------------------------
--- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
--- http://www.syntiac.com/fpga64.html
---
--- Modified April 2016 by Dar (darfpga@aol.fr)
--- http://darfpga.blogspot.fr
--- Remove address register when writing
---
--- -----------------------------------------------------------------------
---
--- dpram.vhd
---
--- -----------------------------------------------------------------------
---
--- generic ram.
---
--- -----------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
--- -----------------------------------------------------------------------
-
-entity dpram is
- generic (
- dWidth : integer := 8;
- aWidth : integer := 10
- );
- port (
- clk_a : in std_logic;
- we_a : in std_logic := '0';
- addr_a : in std_logic_vector((aWidth-1) downto 0);
- d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
- q_a : out std_logic_vector((dWidth-1) downto 0);
-
- clk_b : in std_logic;
- we_b : in std_logic := '0';
- addr_b : in std_logic_vector((aWidth-1) downto 0);
- d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
- q_b : out std_logic_vector((dWidth-1) downto 0)
- );
-end entity;
-
--- -----------------------------------------------------------------------
-
-architecture rtl of dpram is
- subtype addressRange is integer range 0 to ((2**aWidth)-1);
- type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
- signal ram: ramDef;
- signal addr_a_reg: std_logic_vector((aWidth-1) downto 0);
- signal addr_b_reg: std_logic_vector((aWidth-1) downto 0);
-begin
-
--- -----------------------------------------------------------------------
- process(clk_a)
- begin
- if rising_edge(clk_a) then
- if we_a = '1' then
- ram(to_integer(unsigned(addr_a))) <= d_a;
- end if;
- q_a <= ram(to_integer(unsigned(addr_a)));
- end if;
- end process;
-
- process(clk_b)
- begin
- if rising_edge(clk_b) then
- if we_b = '1' then
- ram(to_integer(unsigned(addr_b))) <= d_b;
- end if;
- q_b <= ram(to_integer(unsigned(addr_b)));
- end if;
- end process;
-
-end architecture;
-
diff --git a/Arcade_MiST/Konami Green Beret Hardware/rtl/gberet_mist.sv b/Arcade_MiST/Konami Green Beret Hardware/rtl/gberet_mist.sv
deleted file mode 100644
index e08e3279..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/rtl/gberet_mist.sv
+++ /dev/null
@@ -1,283 +0,0 @@
-// Green Beret (Rusn'n Attack) MiST top-level
-
-module gberet_mist (
- output LED,
- output [5:0] VGA_R,
- output [5:0] VGA_G,
- output [5:0] VGA_B,
- output VGA_HS,
- output VGA_VS,
- output AUDIO_L,
- output AUDIO_R,
- input SPI_SCK,
- output SPI_DO,
- input SPI_DI,
- input SPI_SS2,
- input SPI_SS3,
- input CONF_DATA0,
- input CLOCK_27,
- output [12:0] SDRAM_A,
- inout [15:0] SDRAM_DQ,
- output SDRAM_DQML,
- output SDRAM_DQMH,
- output SDRAM_nWE,
- output SDRAM_nCAS,
- output SDRAM_nRAS,
- output SDRAM_nCS,
- output [1:0] SDRAM_BA,
- output SDRAM_CLK,
- output SDRAM_CKE
-
-);
-
-`include "rtl\build_id.v"
-
-`define CORE_NAME "GBERET"
-
-localparam CONF_STR = {
- `CORE_NAME, ";ROM;",
- "O2,Rotate Controls,Off,On;",
- "O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
- "O5,Blend,Off,On;",
- "O89,Lives,2,3,5,7;",
- "OAB,Extend,20k/ev.60k,30k/ev.70k,40k/ev.80k,50k/ev.90k;",
- "OCD,Difficulty,Easy,Medium,Hard,Hardest;",
- "OE,Demo Sound,Off,On;",
- "T0,Reset;",
- "V,v1.00.",`BUILD_DATE
-};
-
-wire rotate = status[2];
-wire [1:0] scanlines = status[4:3];
-wire blend = status[5];
-
-wire [1:0] dsLives = ~status[9:8];
-wire [1:0] dsExtend = ~status[11:10];
-wire [1:0] dsDiff = ~status[13:12];
-wire dsDemoSnd = ~status[14];
-
-wire [6:0] core_mod;
-
-assign LED = ~ioctl_downl;
-assign AUDIO_R = AUDIO_L;
-assign SDRAM_CLK = clock_48;
-assign SDRAM_CKE = 1;
-
-wire clock_48, pll_locked;
-pll pll(
- .inclk0(CLOCK_27),
- .c0(clock_48),
- .locked(pll_locked)
- );
-
-wire [31:0] status;
-wire [1:0] buttons;
-wire [1:0] switches;
-wire [7:0] joystick_0;
-wire [7:0] joystick_1;
-wire scandoublerD;
-wire ypbpr;
-wire no_csync;
-wire key_strobe;
-wire key_pressed;
-wire [7:0] key_code;
-
-user_io #(.STRLEN($size(CONF_STR)>>3))user_io(
- .clk_sys ( clock_48 ),
- .conf_str ( CONF_STR ),
- .SPI_CLK ( SPI_SCK ),
- .SPI_SS_IO ( CONF_DATA0 ),
- .SPI_MISO ( SPI_DO ),
- .SPI_MOSI ( SPI_DI ),
- .buttons ( buttons ),
- .switches ( switches ),
- .scandoubler_disable ( scandoublerD ),
- .ypbpr ( ypbpr ),
- .no_csync ( no_csync ),
- .core_mod ( core_mod ),
- .key_strobe ( key_strobe ),
- .key_pressed ( key_pressed ),
- .key_code ( key_code ),
- .joystick_0 ( joystick_0 ),
- .joystick_1 ( joystick_1 ),
- .status ( status )
- );
-
-wire [15:0] rom_addr;
-wire [15:0] rom_do;
-wire [15:1] spr_addr;
-wire [15:0] spr_do;
-
-wire ioctl_downl;
-wire [7:0] ioctl_index;
-wire ioctl_wr;
-wire [24:0] ioctl_addr;
-wire [7:0] ioctl_dout;
-
-// Don't delete!
-// ROM structure
-// 00000 - 0FFFF - maincpu - 64k - 10c+8c+7c+7c
-// 10000 - 1FFFF - gfx2 - 64k - 5e+4e+4f+3e
-// 20000 - 23FFF - gfx1 - 16k - 3f
-// 24000 - 240FF - sprites - 256b - 5f
-// 24100 - 241FF - chars - 256b - 6f
-// 24200 - 2421F - pal - 32b - 2f
-
-data_io data_io(
- .clk_sys ( clock_48 ),
- .SPI_SCK ( SPI_SCK ),
- .SPI_SS2 ( SPI_SS2 ),
- .SPI_DI ( SPI_DI ),
- .ioctl_download( ioctl_downl ),
- .ioctl_index ( ioctl_index ),
- .ioctl_wr ( ioctl_wr ),
- .ioctl_addr ( ioctl_addr ),
- .ioctl_dout ( ioctl_dout )
-);
-
-wire [24:0] bg_ioctl_addr = ioctl_addr - 17'h10000;
-
-reg port1_req, port2_req;
-sdram sdram(
- .*,
- .init_n ( pll_locked ),
- .clk ( clock_48 ),
-
- .port1_req ( port1_req ),
- .port1_ack ( ),
- .port1_a ( ioctl_addr[23:1] ),
- .port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
- .port1_we ( ioctl_downl ),
- .port1_d ( {ioctl_dout, ioctl_dout} ),
- .port1_q ( ),
-
- .cpu1_addr ( ioctl_downl ? 16'hffff : {1'b0, rom_addr[15:1]} ),
- .cpu1_q ( rom_do ),
-
- // port2 for sprite graphics
- .port2_req ( port2_req ),
- .port2_ack ( ),
- .port2_a ( bg_ioctl_addr[23:1] ),
- .port2_ds ( {bg_ioctl_addr[0], ~bg_ioctl_addr[0]} ),
- .port2_we ( ioctl_downl ),
- .port2_d ( {ioctl_dout, ioctl_dout} ),
- .port2_q ( ),
-
- .spr_addr ( ioctl_downl ? 15'h7fff : spr_addr ),
- .spr_q ( spr_do )
-);
-
-// ROM download controller
-always @(posedge clock_48) begin
- reg ioctl_wr_last = 0;
-
- ioctl_wr_last <= ioctl_wr;
- if (ioctl_downl) begin
- if (~ioctl_wr_last && ioctl_wr) begin
- port1_req <= ~port1_req;
- port2_req <= ~port2_req;
- end
- end
-end
-
-reg reset = 1;
-reg rom_loaded = 0;
-always @(posedge clock_48) begin
- reg ioctl_downlD;
- ioctl_downlD <= ioctl_downl;
- if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
- reset <= status[0] | buttons[1] | ioctl_downl | ~rom_loaded;
-end
-
-//////////////////////////////////////////////
-wire [7:0] audio;
-wire hs, vs;
-wire hb, vb;
-wire blankn = ~(hb | vb);
-wire [3:0] r, g, b;
-
-wire PCLK;
-wire PCLK_EN;
-wire [8:0] HPOS,VPOS;
-wire [11:0] POUT;
-
-HVGEN hvgen
-(
- .HPOS(HPOS),.VPOS(VPOS),.CLK(clock_48),.PCLK_EN(PCLK_EN),.iRGB(POUT),
- .oRGB({b,g,r}),.HBLK(hb),.VBLK(vb),.HSYN(hs),.VSYN(vs)
-);
-
-wire [5:0] INP0 = { m_fireB, m_fireA, m_left, m_down, m_right, m_up };
-wire [5:0] INP1 = { m_fire2B, m_fire2A, m_left2, m_down2, m_right2, m_up2 };
-wire [2:0] INP2 = { m_coin1 | m_coin2, m_two_players, m_one_player };
-
-wire [7:0] DSW0 = {dsDemoSnd,dsDiff,dsExtend,1'b0,dsLives};
-wire [7:0] DSW1 = 8'hFF;
-wire [7:0] DSW2 = 8'hFF;
-
-FPGA_GreenBeret GameCore (
- .reset(reset),.clk48M(clock_48),
- .INP0(INP0),.INP1(INP1),.INP2(INP2),
- .DSW0(DSW0),.DSW1(DSW1),.DSW2(DSW2),
-
- .PH(HPOS),.PV(VPOS),.PCLK(PCLK),.PCLK_EN(PCLK_EN),.POUT(POUT),
- .SND(audio),
-
- .CPU_ROMA(rom_addr), .CPU_ROMDT(rom_addr[0] ? rom_do[15:8] : rom_do[7:0]),
- .SP_ROMA(spr_addr), .SP_ROMD(spr_do),
- .ROMCL(clock_48),.ROMAD(ioctl_addr),.ROMDT(ioctl_dout),.ROMEN(ioctl_wr)
-);
-
-//////////////////////////////////////////////
-
-mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video(
- .clk_sys ( clock_48 ),
- .SPI_SCK ( SPI_SCK ),
- .SPI_SS3 ( SPI_SS3 ),
- .SPI_DI ( SPI_DI ),
- .R ( blankn ? r : 0 ),
- .G ( blankn ? g : 0 ),
- .B ( blankn ? b : 0 ),
- .HSync ( hs ),
- .VSync ( vs ),
- .VGA_R ( VGA_R ),
- .VGA_G ( VGA_G ),
- .VGA_B ( VGA_B ),
- .VGA_VS ( VGA_VS ),
- .VGA_HS ( VGA_HS ),
- .rotate ( { 1'b1, rotate } ),
- .scandoubler_disable( scandoublerD ),
- .blend ( blend ),
- .scanlines ( scanlines ),
- .no_csync ( no_csync ),
- .ypbpr ( ypbpr )
- );
-
-dac #(8) dac(
- .clk_i(clock_48),
- .res_n_i(1),
- .dac_i(audio),
- .dac_o(AUDIO_L)
- );
-
-wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
-wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
-wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
-
-arcade_inputs inputs (
- .clk ( clock_48 ),
- .key_strobe ( key_strobe ),
- .key_pressed ( key_pressed ),
- .key_code ( key_code ),
- .joystick_0 ( joystick_0 ),
- .joystick_1 ( joystick_1 ),
- .rotate ( rotate ),
- .orientation ( 2'b10 ),
- .joyswap ( 1'b0 ),
- .oneplayer ( 1'b1 ),
- .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
- .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
- .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
-);
-
-endmodule
diff --git a/Arcade_MiST/Konami Green Beret Hardware/rtl/hvgen.v b/Arcade_MiST/Konami Green Beret Hardware/rtl/hvgen.v
deleted file mode 100644
index c4233060..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/rtl/hvgen.v
+++ /dev/null
@@ -1,44 +0,0 @@
-module HVGEN
-(
- output [8:0] HPOS,
- output [8:0] VPOS,
- input CLK,
- input PCLK_EN,
- input [11:0] iRGB,
-
- output reg [11:0] oRGB,
- output reg HBLK = 1,
- output reg VBLK = 1,
- output reg HSYN = 1,
- output reg VSYN = 1
-);
-
-reg [8:0] hcnt = 0;
-reg [8:0] vcnt = 0;
-
-assign HPOS = hcnt-9'd24;
-assign VPOS = vcnt;
-
-always @(posedge CLK) begin
- if (PCLK_EN) begin
- case (hcnt)
- 24: begin HBLK <= 0; hcnt <= hcnt+9'd1; end
- 265: begin HBLK <= 1; hcnt <= hcnt+9'd1; end
- 311: begin HSYN <= 0; hcnt <= hcnt+9'd1; end
- 342: begin HSYN <= 1; hcnt <= 9'd471; end
- 511: begin hcnt <= 0;
- case (vcnt)
- 223: begin VBLK <= 1; vcnt <= vcnt+9'd1; end
- 226: begin VSYN <= 0; vcnt <= vcnt+9'd1; end
- 233: begin VSYN <= 1; vcnt <= 9'd483; end
- 511: begin VBLK <= 0; vcnt <= 0; end
- default: vcnt <= vcnt+9'd1;
- endcase
- end
- default: hcnt <= hcnt+9'd1;
- endcase
- oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB;
- end
-end
-
-endmodule
diff --git a/Arcade_MiST/Konami Green Beret Hardware/rtl/pll.v b/Arcade_MiST/Konami Green Beret Hardware/rtl/pll.v
deleted file mode 100644
index bd27baf2..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/rtl/pll.v
+++ /dev/null
@@ -1,309 +0,0 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll
-
-// ============================================================
-// File Name: pll.v
-// Megafunction Name(s):
-// altpll
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2014 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, Altera MegaCore Function License
-//Agreement, or other applicable license agreement, including,
-//without limitation, that your use is for the sole purpose of
-//programming logic devices manufactured by Altera and sold by
-//Altera or its authorized distributors. Please refer to the
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module pll (
- inclk0,
- c0,
- locked);
-
- input inclk0;
- output c0;
- output locked;
-
- wire [4:0] sub_wire0;
- wire sub_wire2;
- wire [0:0] sub_wire5 = 1'h0;
- wire [0:0] sub_wire1 = sub_wire0[0:0];
- wire c0 = sub_wire1;
- wire locked = sub_wire2;
- wire sub_wire3 = inclk0;
- wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
-
- altpll altpll_component (
- .inclk (sub_wire4),
- .clk (sub_wire0),
- .locked (sub_wire2),
- .activeclock (),
- .areset (1'b0),
- .clkbad (),
- .clkena ({6{1'b1}}),
- .clkloss (),
- .clkswitch (1'b0),
- .configupdate (1'b0),
- .enable0 (),
- .enable1 (),
- .extclk (),
- .extclkena ({4{1'b1}}),
- .fbin (1'b1),
- .fbmimicbidir (),
- .fbout (),
- .fref (),
- .icdrclk (),
- .pfdena (1'b1),
- .phasecounterselect ({4{1'b1}}),
- .phasedone (),
- .phasestep (1'b1),
- .phaseupdown (1'b1),
- .pllena (1'b1),
- .scanaclr (1'b0),
- .scanclk (1'b0),
- .scanclkena (1'b1),
- .scandata (1'b0),
- .scandataout (),
- .scandone (),
- .scanread (1'b0),
- .scanwrite (1'b0),
- .sclkout0 (),
- .sclkout1 (),
- .vcooverrange (),
- .vcounderrange ());
- defparam
- altpll_component.bandwidth_type = "AUTO",
- altpll_component.clk0_divide_by = 9,
- altpll_component.clk0_duty_cycle = 50,
- altpll_component.clk0_multiply_by = 16,
- altpll_component.clk0_phase_shift = "0",
- altpll_component.compensate_clock = "CLK0",
- altpll_component.inclk0_input_frequency = 37037,
- altpll_component.intended_device_family = "Cyclone III",
- altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
- altpll_component.lpm_type = "altpll",
- altpll_component.operation_mode = "NORMAL",
- altpll_component.pll_type = "AUTO",
- altpll_component.port_activeclock = "PORT_UNUSED",
- altpll_component.port_areset = "PORT_UNUSED",
- altpll_component.port_clkbad0 = "PORT_UNUSED",
- altpll_component.port_clkbad1 = "PORT_UNUSED",
- altpll_component.port_clkloss = "PORT_UNUSED",
- altpll_component.port_clkswitch = "PORT_UNUSED",
- altpll_component.port_configupdate = "PORT_UNUSED",
- altpll_component.port_fbin = "PORT_UNUSED",
- altpll_component.port_inclk0 = "PORT_USED",
- altpll_component.port_inclk1 = "PORT_UNUSED",
- altpll_component.port_locked = "PORT_USED",
- altpll_component.port_pfdena = "PORT_UNUSED",
- altpll_component.port_phasecounterselect = "PORT_UNUSED",
- altpll_component.port_phasedone = "PORT_UNUSED",
- altpll_component.port_phasestep = "PORT_UNUSED",
- altpll_component.port_phaseupdown = "PORT_UNUSED",
- altpll_component.port_pllena = "PORT_UNUSED",
- altpll_component.port_scanaclr = "PORT_UNUSED",
- altpll_component.port_scanclk = "PORT_UNUSED",
- altpll_component.port_scanclkena = "PORT_UNUSED",
- altpll_component.port_scandata = "PORT_UNUSED",
- altpll_component.port_scandataout = "PORT_UNUSED",
- altpll_component.port_scandone = "PORT_UNUSED",
- altpll_component.port_scanread = "PORT_UNUSED",
- altpll_component.port_scanwrite = "PORT_UNUSED",
- altpll_component.port_clk0 = "PORT_USED",
- altpll_component.port_clk1 = "PORT_UNUSED",
- altpll_component.port_clk2 = "PORT_UNUSED",
- altpll_component.port_clk3 = "PORT_UNUSED",
- altpll_component.port_clk4 = "PORT_UNUSED",
- altpll_component.port_clk5 = "PORT_UNUSED",
- altpll_component.port_clkena0 = "PORT_UNUSED",
- altpll_component.port_clkena1 = "PORT_UNUSED",
- altpll_component.port_clkena2 = "PORT_UNUSED",
- altpll_component.port_clkena3 = "PORT_UNUSED",
- altpll_component.port_clkena4 = "PORT_UNUSED",
- altpll_component.port_clkena5 = "PORT_UNUSED",
- altpll_component.port_extclk0 = "PORT_UNUSED",
- altpll_component.port_extclk1 = "PORT_UNUSED",
- altpll_component.port_extclk2 = "PORT_UNUSED",
- altpll_component.port_extclk3 = "PORT_UNUSED",
- altpll_component.self_reset_on_loss_lock = "OFF",
- altpll_component.width_clock = 5;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
-// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf
-// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Konami Green Beret Hardware/rtl/sdram.sv b/Arcade_MiST/Konami Green Beret Hardware/rtl/sdram.sv
deleted file mode 100644
index d41c3b98..00000000
--- a/Arcade_MiST/Konami Green Beret Hardware/rtl/sdram.sv
+++ /dev/null
@@ -1,323 +0,0 @@
-//
-// sdram.v
-//
-// sdram controller implementation for the MiST board
-// https://github.com/mist-devel/mist-board
-//
-// Copyright (c) 2013 Till Harbaum
-// Copyright (c) 2019 Gyorgy Szombathelyi
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program. If not, see .
-//
-
-module sdram (
-
- // interface to the MT48LC16M16 chip
- inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
- output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
- output reg SDRAM_DQML, // two byte masks
- output reg SDRAM_DQMH, // two byte masks
- output reg [1:0] SDRAM_BA, // two banks
- output SDRAM_nCS, // a single chip select
- output SDRAM_nWE, // write enable
- output SDRAM_nRAS, // row address select
- output SDRAM_nCAS, // columns address select
-
- // cpu/chipset interface
- input init_n, // init signal after FPGA config to initialize RAM
- input clk, // sdram clock
-
- input port1_req,
- output reg port1_ack,
- input port1_we,
- input [23:1] port1_a,
- input [1:0] port1_ds,
- input [15:0] port1_d,
- output [15:0] port1_q,
-
- input [15:1] cpu1_addr,
- output reg [15:0] cpu1_q,
-
- input port2_req,
- output reg port2_ack,
- input port2_we,
- input [23:1] port2_a,
- input [1:0] port2_ds,
- input [15:0] port2_d,
- output [15:0] port2_q,
-
- input [15:1] spr_addr,
- output reg [15:0] spr_q
-);
-
-localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
-localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
-localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
-localparam CAS_LATENCY = 3'd2; // 2/3 allowed
-localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
-localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
-
-localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
-
-// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
-localparam RFRSH_CYCLES = 10'd842;
-
-// ---------------------------------------------------------------------
-// ------------------------ cycle state machine ------------------------
-// ---------------------------------------------------------------------
-
-/*
- SDRAM state machine for 2 bank interleaved access
- 1 word burst, CL2
-cmd issued registered
- 0 RAS0 cas1
- 1 ras0
- 2 CAS0 data1 returned
- 3 RAS1 cas0
- 4 ras1
- 5 CAS1 data0 returned
-*/
-
-localparam STATE_RAS0 = 3'd0; // first state in cycle
-localparam STATE_RAS1 = 3'd3; // Second ACTIVE command after RAS0 + tRRD (15ns)
-localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 3
-localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 5
-localparam STATE_READ0 = 3'd0; //STATE_CAS0 + CAS_LATENCY + 1'd1; // 7
-localparam STATE_READ1 = 3'd3;
-localparam STATE_LAST = 3'd5;
-
-reg [2:0] t;
-
-always @(posedge clk) begin
- t <= t + 1'd1;
- if (t == STATE_LAST) t <= STATE_RAS0;
-end
-
-// ---------------------------------------------------------------------
-// --------------------------- startup/reset ---------------------------
-// ---------------------------------------------------------------------
-
-// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
-// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
-reg [4:0] reset;
-reg init = 1'b1;
-always @(posedge clk, negedge init_n) begin
- if(!init_n) begin
- reset <= 5'h1f;
- init <= 1'b1;
- end else begin
- if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
- init <= !(reset == 0);
- end
-end
-
-// ---------------------------------------------------------------------
-// ------------------ generate ram control signals ---------------------
-// ---------------------------------------------------------------------
-
-// all possible commands
-localparam CMD_INHIBIT = 4'b1111;
-localparam CMD_NOP = 4'b0111;
-localparam CMD_ACTIVE = 4'b0011;
-localparam CMD_READ = 4'b0101;
-localparam CMD_WRITE = 4'b0100;
-localparam CMD_BURST_TERMINATE = 4'b0110;
-localparam CMD_PRECHARGE = 4'b0010;
-localparam CMD_AUTO_REFRESH = 4'b0001;
-localparam CMD_LOAD_MODE = 4'b0000;
-
-reg [3:0] sd_cmd; // current command sent to sd ram
-reg [15:0] sd_din;
-// drive control signals according to current command
-assign SDRAM_nCS = sd_cmd[3];
-assign SDRAM_nRAS = sd_cmd[2];
-assign SDRAM_nCAS = sd_cmd[1];
-assign SDRAM_nWE = sd_cmd[0];
-
-reg [24:1] addr_latch[2];
-reg [24:1] addr_latch_next[2];
-reg [15:1] addr_last[2];
-reg [15:1] addr_last2[2];
-reg [15:0] din_latch[2];
-reg [1:0] oe_latch;
-reg [1:0] we_latch;
-reg [1:0] ds[2];
-
-localparam PORT_NONE = 2'd0;
-localparam PORT_CPU1 = 2'd1;
-localparam PORT_REQ = 2'd2;
-
-localparam PORT_SPR = 2'd1;
-
-reg [2:0] next_port[2];
-reg [2:0] port[2];
-
-reg refresh;
-reg [10:0] refresh_cnt;
-wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
-
-// PORT1: bank 0,1
-always @(*) begin
- if (refresh) begin
- next_port[0] = PORT_NONE;
- addr_latch_next[0] = addr_latch[0];
- end else if (port1_req ^ port1_ack) begin
- next_port[0] = PORT_REQ;
- addr_latch_next[0] = { 1'b0, port1_a };
- end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
- next_port[0] = PORT_CPU1;
- addr_latch_next[0] = { 9'd0, cpu1_addr };
- end else begin
- next_port[0] = PORT_NONE;
- addr_latch_next[0] = addr_latch[0];
- end
-end
-
-// PORT2: bank 2,3
-always @(*) begin
- if (port2_req ^ port2_ack) begin
- next_port[1] = PORT_REQ;
- addr_latch_next[1] = { 1'b1, port2_a };
- end else if (spr_addr != addr_last2[PORT_SPR]) begin
- next_port[1] = PORT_SPR;
- addr_latch_next[1] = { 1'b1, 8'd0, spr_addr };
- end else begin
- next_port[1] = PORT_NONE;
- addr_latch_next[1] = addr_latch[1];
- end
-end
-
-always @(posedge clk) begin
-
- // permanently latch ram data to reduce delays
- sd_din <= SDRAM_DQ;
- SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
- { SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
- sd_cmd <= CMD_NOP; // default: idle
- refresh_cnt <= refresh_cnt + 1'd1;
-
- if(init) begin
- // initialization takes place at the end of the reset phase
- if(t == STATE_RAS0) begin
-
- if(reset == 15) begin
- sd_cmd <= CMD_PRECHARGE;
- SDRAM_A[10] <= 1'b1; // precharge all banks
- end
-
- if(reset == 10 || reset == 8) begin
- sd_cmd <= CMD_AUTO_REFRESH;
- end
-
- if(reset == 2) begin
- sd_cmd <= CMD_LOAD_MODE;
- SDRAM_A <= MODE;
- SDRAM_BA <= 2'b00;
- end
- end
- end else begin
- // RAS phase
- // bank 0,1
- if(t == STATE_RAS0) begin
- addr_latch[0] <= addr_latch_next[0];
- port[0] <= next_port[0];
- { oe_latch[0], we_latch[0] } <= 2'b00;
-
- if (next_port[0] != PORT_NONE) begin
- sd_cmd <= CMD_ACTIVE;
- SDRAM_A <= addr_latch_next[0][22:10];
- SDRAM_BA <= addr_latch_next[0][24:23];
- addr_last[next_port[0]] <= addr_latch_next[0][15:1];
- if (next_port[0] == PORT_REQ) begin
- { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
- ds[0] <= port1_ds;
- din_latch[0] <= port1_d;
- end else begin
- { oe_latch[0], we_latch[0] } <= 2'b10;
- ds[0] <= 2'b11;
- end
- end
- end
-
- // bank 2,3
- if(t == STATE_RAS1) begin
- refresh <= 1'b0;
- addr_latch[1] <= addr_latch_next[1];
- { oe_latch[1], we_latch[1] } <= 2'b00;
- port[1] <= next_port[1];
-
- if (next_port[1] != PORT_NONE) begin
- sd_cmd <= CMD_ACTIVE;
- SDRAM_A <= addr_latch_next[1][22:10];
- SDRAM_BA <= addr_latch_next[1][24:23];
- addr_last2[next_port[1]] <= addr_latch_next[1][15:1];
- if (next_port[1] == PORT_REQ) begin
- { oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we };
- ds[1] <= port2_ds;
- din_latch[1] <= port2_d;
- end else begin
- { oe_latch[1], we_latch[1] } <= 2'b10;
- ds[1] <= 2'b11;
- end
- end
-
- if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
- refresh <= 1'b1;
- refresh_cnt <= 0;
- sd_cmd <= CMD_AUTO_REFRESH;
- end
- end
-
- // CAS phase
- if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
- sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
- { SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
- if (we_latch[0]) begin
- SDRAM_DQ <= din_latch[0];
- port1_ack <= port1_req;
- end
- SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
- SDRAM_BA <= addr_latch[0][24:23];
- end
-
- if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
- sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
- { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
- if (we_latch[1]) begin
- SDRAM_DQ <= din_latch[1];
- port2_ack <= port2_req;
- end
- SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
- SDRAM_BA <= addr_latch[1][24:23];
- end
-
- // Data returned
- if(t == STATE_READ0 && oe_latch[0]) begin
- case(port[0])
- PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
- PORT_CPU1: begin cpu1_q <= sd_din; end
- default: ;
- endcase;
- end
- if(t == STATE_READ1 && oe_latch[1]) begin
- case(port[1])
- PORT_REQ: begin port2_q <= sd_din; port2_ack <= port2_req; end
- PORT_SPR: begin spr_q <= sd_din; end
- default: ;
- endcase;
- end
- end
-end
-
-endmodule
diff --git a/Arcade_MiST/Konami Jailbreak/Jailbrek.qsf b/Arcade_MiST/Konami Jailbreak/Jailbrek.qsf
index 0c7d3935..572d8249 100644
--- a/Arcade_MiST/Konami Jailbreak/Jailbrek.qsf
+++ b/Arcade_MiST/Konami Jailbreak/Jailbrek.qsf
@@ -253,6 +253,7 @@ set_global_assignment -name VHDL_FILE rtl/VLM5030/vlm5030_pack.vhd
set_global_assignment -name VHDL_FILE rtl/VLM5030/vlm5030_gl.vhd
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
+set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
set_global_assignment -name VERILOG_FILE ../../common/CPU/MC6809/mc6809is.v
set_global_assignment -name QIP_FILE ../../common/Sound/sn76489/sn76489.qip
set_global_assignment -name SIGNALTAP_FILE output_files/sdram.stp
diff --git a/Arcade_MiST/Konami Jailbreak/README.md b/Arcade_MiST/Konami Jailbreak/README.md
index 92b3397b..6674a53e 100644
--- a/Arcade_MiST/Konami Jailbreak/README.md
+++ b/Arcade_MiST/Konami Jailbreak/README.md
@@ -2,6 +2,8 @@
https://github.com/MiSTer-devel/Arcade-Jailbreak_MiSTer
+Green Beret/Mr. Goemon added by Slingshot
+
## Usage
- Create ROM and ARC files from the MRA files using the MRA utility.
diff --git a/Arcade_MiST/Konami Jailbreak/meta/Green Beret.mra b/Arcade_MiST/Konami Jailbreak/meta/Green Beret.mra
new file mode 100644
index 00000000..8d338801
--- /dev/null
+++ b/Arcade_MiST/Konami Jailbreak/meta/Green Beret.mra
@@ -0,0 +1,42 @@
+
+ Green Beret
+ 0216
+ gberet
+ 201911270000
+ 1985
+ Konami
+ Army / Fighter
+ jailbrek
+
+
+
+
+
+
+
+
+
+
+
+
+ 1
+
+
+
+
+
+
+ FF
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Arcade_MiST/Konami Jailbreak/meta/Jailbreak.mra b/Arcade_MiST/Konami Jailbreak/meta/Jailbreak.mra
old mode 100755
new mode 100644
index 86af1f2b..bbe63bae
--- a/Arcade_MiST/Konami Jailbreak/meta/Jailbreak.mra
+++ b/Arcade_MiST/Konami Jailbreak/meta/Jailbreak.mra
@@ -44,13 +44,17 @@
+
+
+
+
-
+
diff --git a/Arcade_MiST/Konami Jailbreak/meta/Manhattan 24 Bunsyo (J).mra b/Arcade_MiST/Konami Jailbreak/meta/Manhattan 24 Bunsyo (J).mra
old mode 100755
new mode 100644
index 19236281..15344ac2
--- a/Arcade_MiST/Konami Jailbreak/meta/Manhattan 24 Bunsyo (J).mra
+++ b/Arcade_MiST/Konami Jailbreak/meta/Manhattan 24 Bunsyo (J).mra
@@ -44,13 +44,18 @@
+
+
+
+
-
+
+
diff --git a/Arcade_MiST/Konami Jailbreak/meta/Mr. Goemon.mra b/Arcade_MiST/Konami Jailbreak/meta/Mr. Goemon.mra
new file mode 100644
index 00000000..dda08a65
--- /dev/null
+++ b/Arcade_MiST/Konami Jailbreak/meta/Mr. Goemon.mra
@@ -0,0 +1,37 @@
+
+ Mr. Goemon
+ 0216
+ mrgoemon
+ 201911270000
+ 1985
+ Konami
+ jailbrek
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Arcade_MiST/Konami Jailbreak/meta/Rush'n Attack (US).mra b/Arcade_MiST/Konami Jailbreak/meta/Rush'n Attack (US).mra
new file mode 100644
index 00000000..332d6e0e
--- /dev/null
+++ b/Arcade_MiST/Konami Jailbreak/meta/Rush'n Attack (US).mra
@@ -0,0 +1,42 @@
+
+ Rush'n Attack (US)
+ 0216
+ rushatck
+ 201911270000
+ 1985
+ Konami
+ Army / Fighter
+ jailbrek
+
+
+
+
+
+
+
+
+
+
+
+
+ 1
+
+
+
+
+
+
+ FF
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Arcade_MiST/Konami Jailbreak/rtl/Jailbreak.sv b/Arcade_MiST/Konami Jailbreak/rtl/Jailbreak.sv
index d25927ad..93d76220 100644
--- a/Arcade_MiST/Konami Jailbreak/rtl/Jailbreak.sv
+++ b/Arcade_MiST/Konami Jailbreak/rtl/Jailbreak.sv
@@ -32,7 +32,9 @@ module Jailbreak
input [1:0] btn_start, //1 = Player 2, 0 = Player 1
input [3:0] p1_joystick, p2_joystick, //3 = up, 2 = down, 1 = right, 0 = left
input [1:0] p1_buttons, p2_buttons, //2 buttons per player
-
+
+ input gberet, // Z80 board variant
+
input [19:0] dipsw,
//This input serves to select a fractional divider to acheive 3.072MHz for the YM2203 depending on whether Scooter Shooter
@@ -150,7 +152,7 @@ jtframe_frac_cen sn76489_cen
.cen({1'bZ, cen_1m5_adjust})
);
-//------------------------------------------------------------ CPU -------------------------------------------------------------//
+//------------------------------------------------------------ CPU (KONAMI-1) ----------------------------------------------------------//
//CPU - KONAMI-1 custom encrypted MC6809E (uses synchronous version of Greg Miller's cycle-accurate MC6809E made by
//Sorgelig with a wrapper to decrypt XOR/XNOR-encrypted opcodes and a further modification to Greg's MC6809E to directly
@@ -171,36 +173,105 @@ KONAMI1 u18F
.nFIRQ(firq),
.nNMI(nmi),
.nHALT(~pause),
- .nRESET(reset)
+ .nRESET(reset & !gberet)
);
//Address decoding for KONAMI-1
-wire cs_dip2 = ~n_iocs & (k1_A[10:8] == 3'b001) & k1_rw;
-wire cs_dip3 = ~n_iocs & (k1_A[10:8] == 3'b010) & k1_rw;
-wire cs_controls_dip1 = ~n_iocs & (k1_A[10:8] == 3'b011) & k1_rw;
-wire cs_snlatch = ~n_iocs & (k1_A[10:8] == 3'b001) & ~k1_rw;
-wire cs_sn76489 = ~n_iocs & (k1_A[10:8] == 3'b010) & ~k1_rw;
-wire cs_k005849 = (k1_A[15:14] == 2'b00);
-wire cs_vlm5030_busy = (k1_A[15:12] == 4'b0110);
-wire cs_rom1 = (k1_A[15:14] == 2'b10) & k1_rw;
-wire cs_rom2 = (k1_A[15:14] == 2'b11) & k1_rw;
+wire cs_k1_dip2 = ~n_iocs & (k1_A[10:8] == 3'b001) & k1_rw;
+wire cs_k1_dip3 = ~n_iocs & (k1_A[10:8] == 3'b010) & k1_rw;
+wire cs_k1_controls_dip1 = ~n_iocs & (k1_A[10:8] == 3'b011) & k1_rw;
+wire cs_k1_snlatch = ~n_iocs & (k1_A[10:8] == 3'b001) & ~k1_rw;
+wire cs_k1_sn76489 = ~n_iocs & (k1_A[10:8] == 3'b010) & ~k1_rw;
+wire cs_k1_k005849 = (k1_A[15:14] == 2'b00);
+wire cs_k1_vlm5030_busy = (k1_A[15:12] == 4'b0110);
+wire cs_k1_rom1 = (k1_A[15:14] == 2'b10) & k1_rw;
+wire cs_k1_rom2 = (k1_A[15:14] == 2'b11) & k1_rw;
//Multiplex data inputs to KONAMI-1
-wire [7:0] k1_Din = cs_dip2 ? dipsw[15:8]:
- cs_dip3 ? {4'hF, dipsw[19:16]}:
- cs_controls_dip1 ? controls_dip1:
- (cs_k005849 & n_iocs & k1_rw) ? k005849_D:
- cs_vlm5030_busy ? {7'h7F, vlm5030_busy}:
- cs_rom1 ? eprom1_D:
- cs_rom2 ? eprom2_D:
+wire [7:0] k1_Din = cs_k1_dip2 ? dipsw[15:8]:
+ cs_k1_dip3 ? {4'hF, dipsw[19:16]}:
+ cs_k1_controls_dip1 ? controls_k1_dip1:
+ (cs_k1_k005849 & n_iocs & k1_rw) ? k005849_D:
+ cs_k1_vlm5030_busy ? {7'h7F, vlm5030_busy}:
+ cs_k1_rom1 ? eprom1_D:
+ cs_k1_rom2 ? eprom2_D:
8'hFF;
-//KONAMI-1 ROMs
+//------------------------------------------------------------ CPU (Z80) ----------------------------------------------------------//
+wire z80_n_m1, z80_n_mreq, z80_n_iorq, z80_n_rfsh, z80_n_rd, z80_n_wr;
+wire [15:0] z80_A;
+wire [7:0] z80_Dout;
+T80s u9A
+(
+ .RESET_n(reset & gberet),
+ .CLK(clk_49m),
+ .CEN(cen_3m & ~pause),
+ .INT_n(z80_n_int),
+ .NMI_n(z80_n_nmi),
+ .MREQ_n(z80_n_mreq),
+ .IORQ_n(z80_n_iorq),
+ .RD_n(z80_n_rd),
+ .WR_n(z80_n_wr),
+ .M1_n(z80_n_m1),
+ .RFSH_n(z80_n_rfsh),
+ .A(z80_A),
+ .DI(z80_Din),
+ .DO(z80_Dout)
+);
+//Address decoding for Z80
+wire z80_decode_en = (z80_n_rfsh & ~z80_n_mreq);
+wire cs_z80_dip2 = ~n_iocs & (z80_A[10:8] == 3'b010) & ~z80_n_rd;
+wire cs_z80_dip3 = ~n_iocs & (z80_A[10:8] == 3'b100) & ~z80_n_rd;
+wire cs_z80_controls_dip1 = ~n_iocs & (z80_A[10:8] == 3'b110) & ~z80_n_rd;
+wire cs_z80_snlatch = ~n_iocs & (z80_A[10:8] == 3'b010) & ~z80_n_wr;
+wire cs_z80_sn76489 = ~n_iocs & (z80_A[10:8] == 3'b100) & ~z80_n_wr;
+wire cs_z80_bankw = ~n_iocs & (z80_A[10:8] == 3'b000) & ~z80_n_wr;
+wire cs_z80_k005849 = z80_decode_en & (z80_A[15:14] == 2'b11) & ~cs_z80_rom4;
+wire cs_z80_rom1 = z80_decode_en & (z80_A[15:14] == 2'b00);
+wire cs_z80_rom2 = z80_decode_en & (z80_A[15:14] == 2'b01);
+wire cs_z80_rom3 = z80_decode_en & (z80_A[15:14] == 2'b10);
+wire cs_z80_rom4 = z80_decode_en & (z80_A[15:11] == 5'b11111);
+
+//Multiplex data inputs to Z80
+wire [7:0] z80_Din = cs_z80_dip2 ? dipsw[15:8]:
+ cs_z80_dip3 ? {4'hF, dipsw[19:16]}:
+ cs_z80_controls_dip1 ? controls_z80_dip1:
+ (cs_z80_k005849 & n_iocs & ~z80_n_rd) ? k005849_D:
+ cs_z80_rom1 ? eprom1_D:
+ cs_z80_rom2 ? eprom2_D:
+ cs_z80_rom3 ? eprom3_D:
+ cs_z80_rom4 ? eprom4_D:
+ 8'hFF;
+
+wire z80_n_nmi = nmi;
+wire z80_n_int = firq & irq;
+
+reg [2:0] z80_bank;
+always_ff @(posedge clk_49m)
+ if (cs_z80_bankw) z80_bank <= z80_Dout[7:5];
+
+// --------------------------------------------CPU BUS Selector----------------------------------------------------------//
+wire cs_snlatch = gberet ? cs_z80_snlatch : cs_k1_snlatch;
+wire cs_sn76489 = gberet ? cs_z80_sn76489 : cs_k1_sn76489;
+wire cs_k005849 = gberet ? cs_z80_k005849 : cs_k1_k005849;
+wire [15:0] cpu_A = gberet ? z80_A : k1_A;
+wire [7:0] cpu_Dout = gberet ? z80_Dout : k1_Dout;
+wire cpu_rw = gberet ? z80_n_wr : k1_rw;
+
+// ----------------------------------------------------------------------------------------------------------------------//
+//CPU ROMs (first 16k)
`ifdef EXT_ROM
always_ff @(posedge clk_49m)
- if (k1_A[15] & k1_rw)
- main_cpu_rom_addr <= k1_A[14:0];
+ if (gberet) begin
+ if (z80_A[15:14] != 2'b11 & z80_decode_en & ~z80_n_rd) main_cpu_rom_addr <= z80_A;
+ if (z80_A[15:11] == 5'b11111 & z80_decode_en & ~z80_n_rd) main_cpu_rom_addr <= {2'b11, z80_bank, z80_A[10:0]};
+ end
+ else begin
+ if (k1_A[15] & k1_rw) main_cpu_rom_addr <= k1_A[14:0];
+ end
wire [7:0] eprom1_D = main_cpu_rom_do;
wire [7:0] eprom2_D = main_cpu_rom_do;
+//wire [7:0] eprom3_D = main_cpu_rom_do;
+wire [7:0] eprom4_D = main_cpu_rom_do;
`else
//ROM 1/2
wire [7:0] eprom1_D;
@@ -232,19 +303,23 @@ eprom_2 u9D
//Sound latch
reg [7:0] sound_data = 8'd0;
-always_ff @(posedge clk_49m) begin
- if(cen_3m && cs_snlatch)
- sound_data <= k1_Dout;
-end
+always_ff @(posedge clk_49m)
+ if(cs_snlatch) sound_data <= cpu_Dout;
//--------------------------------------------------- Controls & DIP switches --------------------------------------------------//
//Multiplex player inputs and DIP switch bank 1
-wire [7:0] controls_dip1 = (k1_A[1:0] == 2'b00) ? {3'b111, btn_start, btn_service, coin}:
- (k1_A[1:0] == 2'b01) ? {2'b11, p1_buttons, p1_joystick}:
- (k1_A[1:0] == 2'b10) ? {2'b11, p2_buttons, p2_joystick}:
- (k1_A[1:0] == 2'b11) ? dipsw[7:0]:
- 8'hFF;
+wire [7:0] controls_k1_dip1 = (k1_A[1:0] == 2'b00) ? {3'b111, btn_start, btn_service, coin}:
+ (k1_A[1:0] == 2'b01) ? {2'b11, p1_buttons, p1_joystick}:
+ (k1_A[1:0] == 2'b10) ? {2'b11, p2_buttons, p2_joystick}:
+ (k1_A[1:0] == 2'b11) ? dipsw[7:0]:
+ 8'hFF;
+
+wire [7:0] controls_z80_dip1 = (z80_A[1:0] == 2'b11) ? {3'b111, btn_start, btn_service, coin}:
+ (z80_A[1:0] == 2'b10) ? {2'b11, p1_buttons, p1_joystick}:
+ (z80_A[1:0] == 2'b01) ? {2'b11, p2_buttons, p2_joystick}:
+ (z80_A[1:0] == 2'b00) ? dipsw[7:0]:
+ 8'hFF;
//--------------------------------------------------- Video timing & graphics --------------------------------------------------//
@@ -260,9 +335,9 @@ k005849 u8E
(
.CK49(clk_49m),
.RES(reset),
- .READ(~k1_rw),
- .A(k1_A[13:0]),
- .DBi(k1_Dout),
+ .READ(~cpu_rw),
+ .A(cpu_A[13:0]),
+ .DBi(cpu_Dout),
.DBo(k005849_D),
.VCF(tilemap_lut_A[7:4]),
.VCB(tilemap_lut_A[3:0]),
@@ -290,7 +365,7 @@ k005849 u8E
.SD(spriterom_D),
.HCTR(h_center),
.VCTR(v_center),
- .SPFL(1),
+ .SPFL(gberet),
.hs_address(hs_address),
.hs_data_out(hs_data_out),
@@ -303,22 +378,11 @@ k005849 u8E
`ifdef EXT_ROM
assign sp1_rom_addr = spriterom_A[15:1];
wire [7:0] spriterom_D = spriterom_A[0] ? sp1_rom_do[15:8] : sp1_rom_do[7:0];
-assign char1_rom_addr = tilerom_A[14:1];
+assign char1_rom_addr = {gberet ? 1'b1 : tilerom_A[14], tilerom_A[13:1]};
wire [7:0] tilerom_D = tilerom_A[0] ? char1_rom_do[15:8] : char1_rom_do[7:0];
`else
-wire [7:0] eprom3_D, eprom4_D, eprom5_D, eprom6_D, eprom7_D, eprom8_D;
-eprom_3 u4F
-(
- .ADDR(tilerom_A[13:0]),
- .CLK(clk_49m),
- .DATA(eprom3_D),
- .ADDR_DL(ioctl_addr),
- .CLK_DL(clk_49m),
- .DATA_IN(ioctl_data),
- .CS_DL(ep3_cs_i),
- .WR(ioctl_wr)
-);
-eprom_4 u5F
+wire [7:0] eprom4_D, eprom5_D, eprom6_D, eprom7_D, eprom8_D, eprom9_D;
+eprom_4 u4F
(
.ADDR(tilerom_A[13:0]),
.CLK(clk_49m),
@@ -329,10 +393,10 @@ eprom_4 u5F
.CS_DL(ep4_cs_i),
.WR(ioctl_wr)
);
-eprom_5 u3E
+eprom_5 u5F
(
- .ADDR(spriterom_A[13:0]),
- .CLK(~clk_49m),
+ .ADDR(tilerom_A[13:0]),
+ .CLK(clk_49m),
.DATA(eprom5_D),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
@@ -340,7 +404,7 @@ eprom_5 u3E
.CS_DL(ep5_cs_i),
.WR(ioctl_wr)
);
-eprom_6 u4E
+eprom_6 u3E
(
.ADDR(spriterom_A[13:0]),
.CLK(~clk_49m),
@@ -351,7 +415,7 @@ eprom_6 u4E
.CS_DL(ep6_cs_i),
.WR(ioctl_wr)
);
-eprom_7 u5E
+eprom_7 u4E
(
.ADDR(spriterom_A[13:0]),
.CLK(~clk_49m),
@@ -362,7 +426,7 @@ eprom_7 u5E
.CS_DL(ep7_cs_i),
.WR(ioctl_wr)
);
-eprom_8 u3F
+eprom_8 u5E
(
.ADDR(spriterom_A[13:0]),
.CLK(~clk_49m),
@@ -373,15 +437,26 @@ eprom_8 u3F
.CS_DL(ep8_cs_i),
.WR(ioctl_wr)
);
+eprom_9 u3F
+(
+ .ADDR(spriterom_A[13:0]),
+ .CLK(~clk_49m),
+ .DATA(eprom9_D),
+ .ADDR_DL(ioctl_addr),
+ .CLK_DL(clk_49m),
+ .DATA_IN(ioctl_data),
+ .CS_DL(ep9_cs_i),
+ .WR(ioctl_wr)
+);
//Multiplex tilemap ROMs
-wire [7:0] tilerom_D = tilerom_A[14] ? eprom4_D : eprom3_D;
+wire [7:0] tilerom_D = (gberet | tilerom_A[14]) ? eprom5_D : eprom4_D;
//Multiplex sprite ROMs
-wire [7:0] spriterom_D = (spriterom_A[15:14] == 2'b00) ? eprom5_D:
- (spriterom_A[15:14] == 2'b01) ? eprom6_D:
- (spriterom_A[15:14] == 2'b10) ? eprom7_D:
- (spriterom_A[15:14] == 2'b11) ? eprom8_D:
+wire [7:0] spriterom_D = (spriterom_A[15:14] == 2'b00) ? eprom6_D:
+ (spriterom_A[15:14] == 2'b01) ? eprom7_D:
+ (spriterom_A[15:14] == 2'b10) ? eprom8_D:
+ (spriterom_A[15:14] == 2'b11) ? eprom9_D:
8'hFF;
`endif
@@ -457,17 +532,17 @@ vlm5030_gl u6A
.o_audio(vlm5030_raw)
);
-//VLM5030 ROM
-wire [7:0] eprom9_D;
-eprom_9 u8C
+//VLM5030 ROM (8000-bfff CPU ROM on Greeb Beret/Mr.Goemon)
+wire [7:0] eprom3_D;
+eprom_3 u8C
(
- .ADDR(vlm5030_rom_A),
+ .ADDR(gberet ? cpu_A[13:0] : vlm5030_rom_A),
.CLK(clk_49m),
- .DATA(eprom9_D),
+ .DATA(eprom3_D),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
.DATA_IN(ioctl_data),
- .CS_DL(ep9_cs_i),
+ .CS_DL(ep3_cs_i),
.WR(ioctl_wr)
);
@@ -496,17 +571,22 @@ end
//Multiplex data inputs from the ROM and KONAMI-1 to the VLM5030's data input
wire [7:0] vlm5030_Din = vlm5030_enable ? vlm5030_sound_D:
- ~n_vlm5030_rom_en ? eprom9_D:
+ ~n_vlm5030_rom_en ? eprom3_D:
8'hFF;
//----------------------------------------------------- Final video output -----------------------------------------------------//
//Jailbreak's final video output consists of two PROMs addressed by the 005849 custom tilemap generator
+wire [7:0] prom1_d, prom2_d;
+assign video_r = gberet ? {prom1_d[2:0], prom1_d[2]} : prom1_d[3:0];
+assign video_g = gberet ? {prom1_d[5:3], prom1_d[5]} : prom1_d[7:4];
+assign video_b = gberet ? {prom1_d[7:6], prom1_d[7:6]} : prom2_d[3:0];
+
color_prom_1 u1F
(
.ADDR(color_A),
.CLK(clk_49m),
- .DATA({video_g, video_r}),
+ .DATA(prom1_d),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
.DATA_IN(ioctl_data),
@@ -518,7 +598,7 @@ color_prom_2 u2F
(
.ADDR(color_A),
.CLK(clk_49m),
- .DATA(video_b),
+ .DATA(prom2_d),
.ADDR_DL(ioctl_addr),
.CLK_DL(clk_49m),
.DATA_IN(ioctl_data),
diff --git a/Arcade_MiST/Konami Jailbreak/rtl/Jailbreak_MiST.sv b/Arcade_MiST/Konami Jailbreak/rtl/Jailbreak_MiST.sv
index ce2529ff..83f5b117 100644
--- a/Arcade_MiST/Konami Jailbreak/rtl/Jailbreak_MiST.sv
+++ b/Arcade_MiST/Konami Jailbreak/rtl/Jailbreak_MiST.sv
@@ -52,6 +52,7 @@ wire pause = status[1];
wire [1:0] orientation = 2'b10;
wire [23:0] dip_sw = ~status[31:8];
+wire gberet = core_mod[0];
assign LED = ~ioctl_downl;
assign SDRAM_CLK = clock_98;
@@ -124,7 +125,7 @@ data_io data_io(
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
-wire [24:0] bg_ioctl_addr = ioctl_addr - 16'h8000;
+wire [24:0] bg_ioctl_addr = ioctl_addr - 16'hc000;
reg port1_req, port2_req;
sdram #(98) sdram(
@@ -211,7 +212,9 @@ Jailbreak Jailbreak_inst
.p2_joystick({~m_down2 | m_up2, ~m_up2, ~m_right2 | m_left2, ~m_left2}),
.p1_buttons({~m_fireB, ~m_fireA}),
.p2_buttons({~m_fire2B, ~m_fire2A}),
-
+
+ .gberet(gberet),
+
.dipsw(dip_sw), // input [24:0] dipsw
.sound(audio), // output [15:0] sound
diff --git a/Arcade_MiST/Konami Jailbreak/rtl/k005849.sv b/Arcade_MiST/Konami Jailbreak/rtl/k005849.sv
index 70458ede..8acecbf7 100644
--- a/Arcade_MiST/Konami Jailbreak/rtl/k005849.sv
+++ b/Arcade_MiST/Konami Jailbreak/rtl/k005849.sv
@@ -148,23 +148,21 @@ reg hblank = 0;
reg vblank = 0;
reg frame_odd_even = 0;
-reg hmask = 0;
always_ff @(posedge CK49) begin
if(cen_6m) begin
case(h_cnt)
5: begin
- hblank <= 0;
+ hblank <= hmask_en;
h_cnt <= h_cnt + 9'd1;
end
13: begin
- hmask <= 0;
+ hblank <= 0;
h_cnt <= h_cnt + 9'd1;
end
//Blank the left-most and right-most 8 lines when the 005849's horizontal mask register bit
//(register 3 bit 7) is active
253: begin
- if(hmask_en)
- hmask <= 1;
+ hblank <= hmask_en;
h_cnt <= h_cnt + 9'd1;
end
261: begin
@@ -205,9 +203,9 @@ assign SYNC = HSYC ^ VSYC;
//------------------------------------------------------------- IRQs -----------------------------------------------------------//
//Edge detection for VBlank and vertical counter bit 5 for IRQ generation
-reg old_vblank, old_vcnt5;
+reg old_vblank, old_vcnt4;
always_ff @(posedge CK49) begin
- old_vcnt5 <= v_cnt[5];
+ old_vcnt4 <= v_cnt[4];
old_vblank <= vblank;
end
@@ -228,7 +226,7 @@ always_ff @(posedge CK49) begin
if(!RES || !nmi_mask)
nmi <= 1;
else begin
- if(old_vcnt5 && !v_cnt[5])
+ if(old_vcnt4 && !v_cnt[4])
nmi <= 0;
end
end
@@ -410,14 +408,17 @@ dpram_dc #(.widthad_a(12)) VRAM_SPR_SHADOW
//-------------------------------------------------------- Tilemap layer -------------------------------------------------------//
-//**The following code is the original tilemap renderer from MiSTerX's Green Beret core with some minor tweaks**//
+//**The following code id based on the original tilemap renderer from MiSTerX's Green Beret core with some minor tweaks**//
+//**Added proper pipelining of external ROM data //**
+
//XOR horizontal and vertical counter bits with flipscreen bit
wire [8:0] hcnt_x = h_cnt ^ {9{flipscreen}};
wire [8:0] vcnt_x = v_cnt ^ {9{flipscreen}};
//Generate tilemap position - horizontal position is the sum of the horizontal counter, vertical position is the vertical counter
//
-wire [8:0] tilemap_hpos = {h_cnt[8], hcnt_x[7:0]} + (~zram_scroll_dir ? {zram1_D[0], zram0_D} : 9'd0);
+wire [8:0] xscroll = (~zram_scroll_dir ? {zram1_D[0], zram0_D} : 9'd0);
+wire [8:0] tilemap_hpos = {h_cnt[8], hcnt_x[7:0]} + xscroll;
wire [8:0] tilemap_vpos = vcnt_x + (zram_scroll_dir ? {zram1_D[0], zram0_D} : 9'd0);
//Address output to tile section of VRAM
@@ -431,7 +432,7 @@ wire [10:0] tile_index = {tilemap_bank, tileram_attrib_D[7:6], tileram_code_D};
wire [3:0] tile_color = tileram_attrib_D[3:0];
reg [3:0] tile_color_r, tile_color_rr;
reg tile_attrib7_r, tile_attrib7_rr;
-reg tile_hflip_r;
+reg tile_hflip_r, tile_hflip_rr;
reg [7:0] RD_r;
//Tile flip attributes are stored in bits 4 (horizontal) and 5 (vertical)
@@ -445,37 +446,37 @@ always_ff @(posedge CK49) begin
R <= {tile_index, (tilemap_vpos[2:0] ^ {3{tile_vflip}}), (tilemap_hpos[2:1] ^ {2{tile_hflip}})};
// Apply appropriate delay to flags
tile_hflip_r <= tile_hflip;
+ tile_hflip_rr <= tile_hflip_r;
tile_color_r <= tile_color;
tile_color_rr <= tile_color_r;
tile_attrib7_r <= tileram_attrib_D[7];
tile_attrib7_rr <= tile_attrib7_r;
+ // latch tile ROM output
RD_r <= RD;
end
end
end
//Multiplex tilemap ROM data down from 8 bits to 4 using bit 0 of the horizontal position
-wire [3:0] tile_pixel = (tilemap_hpos[0] ^ tile_hflip_r) ? RD_r[3:0] : RD_r[7:4];
+wire [3:0] tile_pixel = (hcnt_x[0] ^ tile_hflip_rr) ? RD_r[3:0] : RD_r[7:4];
//Retrieve tilemap select bit from the NOR of bit 7 of the tile attributes with the priority override bit
-reg tilemap_en = 0;
-always_ff @(posedge CK49) begin
- if(cen_6m) begin
- tilemap_en <= ~(tile_attrib7_rr | tile_priority_override);
- end
-end
+wire tilemap_force = ~(tile_attrib7_rr | tile_priority_override) & |tilemap_D;
//Address output to tilemap LUT PROM
assign VCF = tile_color_rr;
assign VCB = tile_pixel;
+reg [3:0] pix0, pix1;
-//Delay tilemap data by one horizontal line
-reg [3:0] tilemap_D = 4'd0;
always_ff @(posedge CK49) begin
- if(cen_6m)
- tilemap_D <= VCD;
+ if(cen_6m) begin
+ pix0 <= VCD;
+ pix1 <= pix0;
+ end
end
+wire [3:0] tilemap_D = xscroll[0] ? pix1 : pix0;
+
//-------------------------------------------------------- Sprite layer --------------------------------------------------------//
//The following code is the original sprite renderer from MiSTerX's Green Beret core with additional screen flipping support and
@@ -506,14 +507,14 @@ always_ff @(posedge CK49) begin
sprite_fsm_state <= 0;
//When the sprite Y attribute is set to 0, skip the current sprite, otherwise obtain the sprite Y attribute
//and scan out the other sprite attributes
- else begin
- if(hy) begin
- sprite_attrib3 <= spriteram_D;
- sprite_offset <= 2;
- sprite_fsm_state <= sprite_fsm_state + 3'd1;
- end
- else sprite_index <= sprite_index + 6'd1;
+ else begin
+ if(hy) begin
+ sprite_attrib3 <= spriteram_D;
+ sprite_offset <= 2;
+ sprite_fsm_state <= sprite_fsm_state + 3'd1;
end
+ else sprite_index <= sprite_index + 6'd1;
+ end
end
2: begin
sprite_attrib2 <= spriteram_D;
@@ -536,7 +537,8 @@ always_ff @(posedge CK49) begin
5: if (S_req == S_ack) begin
xcnt <= xcnt + 5'd1;
sprite_fsm_state <= wre ? sprite_fsm_state : 3'd1;
- S_req <= (wre & xcnt[0]) ? !S_req : S_req;
+ // request external memory access in every 4 pixels (16 bits)
+ S_req <= (wre & xcnt[1:0] == 2'b11) ? !S_req : S_req;
end
default:;
endcase
@@ -544,7 +546,7 @@ end
//Subtract sprite attribute byte 2 with bit 7 of sprite attribute byte 1 to obtain sprite X position and XOR with the
//flipscreen bit
-wire [8:0] sprite_x = ({1'b0, sprite_attrib2} - {sprite_attrib1[7], 8'h00}) ^ {9{flipscreen}};
+wire [8:0] sprite_x = ({1'b0, sprite_attrib2} - {sprite_attrib1[7], 8'h00} + 3'd5) ^ {9{flipscreen}};
//If the sprite state machine is in state 1, obtain sprite Y position directly from sprite RAM, otherwise obtain it from
//sprite attribute byte 3 and XOR with the flipscreen bit
@@ -573,18 +575,7 @@ assign S = {sprite_code, ly[3], lx[3], ly[2:0], lx[2:1]};
//Multiplex sprite ROM data down from 8 bits to 4 using bit 0 of the horizontal position
wire [3:0] sprite_pixel = lx[0] ? SD[3:0] : SD[7:4];
-//Latch the sprite bank from bit 3 of register 3 on the rising edge of VSync and XNOR with the added SPFL signal to flip this bit
-//for Green Beret
-//TODO: Find the actual internal register bit (if any) on the 005849 to properly handle this
-reg sprite_bank = 0;
-reg old_vsync;
-always_ff @(posedge CK49) begin
- old_vsync <= VSYC;
- if(!VSYC)
- sprite_bank <= 0;
- else if(!old_vsync && VSYC)
- sprite_bank <= ~(reg3[3] ^ SPFL);
-end
+wire sprite_bank = reg3[3] ^ SPFL;
wire [11:0] spriteram_A = {3'b000, sprite_bank, sprite_index, sprite_offset};
@@ -654,17 +645,17 @@ end
//--------------------------------------------------------- Color mixer --------------------------------------------------------//
//Multiplex tile and sprite data, then output the final result
-wire tile_sprite_sel = (tilemap_en | ~(|sprite_D));
-wire [3:0] tile_sprite_D = tile_sprite_sel ? tilemap_D : sprite_D;
+wire tile_bg_sel = tilemap_force | ~(|sprite_D);
+wire [3:0] tile_pix_D = tile_bg_sel ? tilemap_D : sprite_D;
//Latch and output pixel data
reg [4:0] pixel_D;
always_ff @(posedge CK49) begin
if(cen_6m)
- pixel_D <= {tile_sprite_sel, tile_sprite_D};
+ pixel_D <= {tile_bg_sel, tile_pix_D};
end
//If the horizontal mask is active, black out the left-most and right-most 8 columns to limit the display area to 240x224, otherwise
//output the full 256x224
-assign COL = hmask ? 5'd0 : pixel_D;
+assign COL = pixel_D;
endmodule
diff --git a/common/Sound/sn76489/sn76489_latch_ctrl.vhd b/common/Sound/sn76489/sn76489_latch_ctrl.vhd
index 4ebc8082..2fcf5bbc 100644
--- a/common/Sound/sn76489/sn76489_latch_ctrl.vhd
+++ b/common/Sound/sn76489/sn76489_latch_ctrl.vhd
@@ -91,6 +91,7 @@ begin
reg_q <= (others => '0');
we_q <= false;
ready_q <= '0';
+ we_n_d <= '1';
elsif clock_i'event and clock_i = '1' then
if clk_en_i then