From e8444ed8282331145c950bc77a30b70105f4bcc3 Mon Sep 17 00:00:00 2001 From: Marcel Date: Sat, 16 Mar 2019 15:12:27 +0100 Subject: [PATCH] (+) --- .../rtl/address_decoder.sv | 37 - .../rtl/image_storage_ram.sv | 61 -- .../rtl/programm_memory.sv | 133 ---- .../rtl/rom/Neuer Ordner/hra2b-1 | 1 - .../rtl/rom/Neuer Ordner/hrl11d-1 | Bin 1024 -> 0 bytes .../rtl/rom/Neuer Ordner/hrl14h-1 | 1 - .../rtl/rom/Neuer Ordner/hrl5c-1 | 1 - .../rtl/rom/Neuer Ordner/stl6d-1 | 1 - .../Exidy-6502 Hardware/rtl/rom/hrl10a_1.bin | Bin 2048 -> 0 bytes .../Exidy-6502 Hardware/rtl/rom/hrl10a_1.hex | 129 ---- .../Exidy-6502 Hardware/rtl/rom/hrl6a_1.bin | Bin 2048 -> 0 bytes .../Exidy-6502 Hardware/rtl/rom/hrl6a_1.hex | 129 ---- .../Exidy-6502 Hardware/rtl/rom/hrl7a_1.bin | Bin 2048 -> 0 bytes .../Exidy-6502 Hardware/rtl/rom/hrl7a_1.hex | 129 ---- .../Exidy-6502 Hardware/rtl/rom/hrl8a_1.bin | Bin 2048 -> 0 bytes .../Exidy-6502 Hardware/rtl/rom/hrl8a_1.hex | 129 ---- .../Exidy-6502 Hardware/rtl/rom/hrl9a_1.bin | Bin 2048 -> 0 bytes .../Exidy-6502 Hardware/rtl/rom/hrl9a_1.hex | 129 ---- .../Exidy-6502 Hardware/rtl/rom/prom5c.bin | 1 - .../Exidy-6502 Hardware/rtl/rom/prom5c.hex | 17 - .../Exidy-6502 Hardware/rtl/rom/swap.exe | Bin 57344 -> 0 bytes .../Jupiter Cantab - JupiterACE_MiST/ace.qsf | 2 +- .../ace_assignment_defaults.qdf | 692 ++++++++++++++++++ .../rtl/mist_io.v | 35 +- .../rtl/osd.v | 39 +- .../rtl/{ => roms}/ace.hex | 0 .../rtl/{ => roms}/ace.mif | 0 .../rtl/{ => roms}/ace.rom | Bin .../rtl/video_mixer.sv | 25 +- 29 files changed, 756 insertions(+), 935 deletions(-) delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/address_decoder.sv delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/image_storage_ram.sv delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/programm_memory.sv delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/hra2b-1 delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/hrl11d-1 delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/hrl14h-1 delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/hrl5c-1 delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/stl6d-1 delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/hrl10a_1.bin delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/hrl10a_1.hex delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/hrl6a_1.bin delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/hrl6a_1.hex delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/hrl7a_1.bin delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/hrl7a_1.hex delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/hrl8a_1.bin delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/hrl8a_1.hex delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/hrl9a_1.bin delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/hrl9a_1.hex delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/prom5c.bin delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/prom5c.hex delete mode 100644 Arcade_MiST/Exidy-6502 Hardware/rtl/rom/swap.exe create mode 100644 Computer_MiST/Jupiter Cantab - JupiterACE_MiST/ace_assignment_defaults.qdf rename Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/{ => roms}/ace.hex (100%) rename Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/{ => roms}/ace.mif (100%) rename Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/{ => roms}/ace.rom (100%) diff --git a/Arcade_MiST/Exidy-6502 Hardware/rtl/address_decoder.sv b/Arcade_MiST/Exidy-6502 Hardware/rtl/address_decoder.sv deleted file mode 100644 index 4a8888e5..00000000 --- a/Arcade_MiST/Exidy-6502 Hardware/rtl/address_decoder.sv +++ /dev/null @@ -1,37 +0,0 @@ -module address_decoder( -input [15:0] addr, -input clk, -output reg absel_n, -output reg iosel_n, -output reg misel_n, -output reg vsel_n, -output reg romsel_n, -output reg ramsel_n, -output reg bbsel_n -); - -reg [3:0]prom_do; -sprom #( - .init_file("./rom/prom5c.hex"), - .widthad_a(7), - .width_a(4)) -c5C( - .address(addr[15:9]), - .clock(clk), - .q(prom_do) - ); - -wire spare1, spare2; -ttl_74ls138 c3D( - .a(prom_do[1]), - .b(prom_do[2]), - .c(prom_do[3]), - .g1(prom_do[0]), - .g2a_n(1'b0), - .g2b_n(1'b0), - .y_n({spare2, spare1, absel_n, iosel_n, misel_n, vsel_n, romsel_n, ramsel_n}), - ); - -assign bbsel_n = romsel_n & ramsel_n; - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Exidy-6502 Hardware/rtl/image_storage_ram.sv b/Arcade_MiST/Exidy-6502 Hardware/rtl/image_storage_ram.sv deleted file mode 100644 index 60a0059b..00000000 --- a/Arcade_MiST/Exidy-6502 Hardware/rtl/image_storage_ram.sv +++ /dev/null @@ -1,61 +0,0 @@ -module image_storage_ram( -input clock, -input [9:0] addr, -input cs_cg1, -input cs_cg2, -input gs_wr_n, -input [7:0] vd_in, -output [7:0] vd_out -); -wire [7:0] ram1, ram2; -always @(clock) - vd_out <= cs_cg1 ? ram1 : - cs_cg2 ? ram2 : 8'b00000000; -spram #( - .widthad_a(10), - .width_a(4)) -c13C( - .address(addr[9:0]), - .clken(cs_cg1), - .clock(clock), - .data(vd_in[7:4]), - .wren(~gs_wr_n), - .q(ram1[7:4]) - ); - -spram #( - .widthad_a(10), - .width_a(4)) -c11C( - .address(addr[9:0]), - .clken(cs_cg1), - .clock(clock), - .data(vd_in[3:0]), - .wren(~gs_wr_n), - .q(ram1[3:0]) - ); - -spram #( - .widthad_a(10), - .width_a(4)) -c14C( - .address(addr[9:0]), - .clken(cs_cg2), - .clock(clock), - .data(vd_in[7:4]), - .wren(~gs_wr_n), - .q(ram2[7:4]) - ); - -spram #( - .widthad_a(10), - .width_a(4)) -c12C( - .address(addr[9:0]), - .clken(cs_cg2), - .clock(clock), - .data(vd_in[3:0]), - .wren(~gs_wr_n), - .q(ram2[3:0]) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Exidy-6502 Hardware/rtl/programm_memory.sv b/Arcade_MiST/Exidy-6502 Hardware/rtl/programm_memory.sv deleted file mode 100644 index 2cc11a7a..00000000 --- a/Arcade_MiST/Exidy-6502 Hardware/rtl/programm_memory.sv +++ /dev/null @@ -1,133 +0,0 @@ -module programm_memory( -input [15:0] addr, -input clk, -input write_n, -input pup3, -input romsel_n, -output [7:0] rom_do -); - -wire [7:0]pcs; - -always @(clk) - rom_do <= pcs[0] ? rom1_do : - pcs[1] ? rom2_do : - pcs[2] ? rom3_do : - pcs[3] ? rom4_do : - pcs[4] ? rom5_do : - pcs[5] ? rom6_do : - pcs[6] ? rom7_do : - pcs[7] ? rom8_do : - 8'b00000000; - -wire [7:0]rom1_do; -wire [7:0]rom2_do; -wire [7:0]rom3_do; -wire [7:0]rom4_do; -wire [7:0]rom5_do; -wire [7:0]rom6_do; -wire [7:0]rom7_do; -wire [7:0]rom8_do; - -sprom #( - .init_file("./rom/hrl6a_1.hex"), - .widthad_a(10), - .width_a(8)) -c13A( - .address(addr[9:0]), - .clock(clk),//pcs[0] - .q(rom1_do) - ); - -sprom #( - .init_file("./rom/hrl7a_1.hex"), - .widthad_a(10), - .width_a(8)) -c12A( - .address(addr[9:0]), - .clock(clk),//pcs[1] - .q(rom2_do) - ); - -sprom #( - .init_file("./rom/hrl8a_1.hex"), - .widthad_a(10), - .width_a(8)) -c11A( - .address(addr[9:0]), - .clock(clk),//pcs[2] - .q(rom3_do) - ); - -sprom #( - .init_file("./rom/hrl9a_1.hex"), - .widthad_a(10), - .width_a(8)) -c10A( - .address(addr[9:0]), - .clock(clk),//pcs[3] - .q(rom4_do) - ); - -sprom #( - .init_file("./rom/hrl10a_1.hex"), - .widthad_a(10), - .width_a(8)) -c9A( - .address(addr[9:0]), - .clock(clk),//pcs[4] - .q(rom5_do) - ); - -`ifdef targ -sprom #( - .init_file(""), - .widthad_a(10), - .width_a(8)) -c8A( - .address(addr[9:0]), - .clock(clk),//pcs[5] - .q(rom6_do) - ); - -sprom #( - .init_file(""), - .widthad_a(10), - .width_a(8)) -c7A( - .address(addr[9:0]), - .clock(clk),//pcs[6] - .q(rom7_do) - ); - -sprom #( - .init_file(""), - .widthad_a(10), - .width_a(8)) -c6A( - .address(addr[9:0]), - .clock(clk),//pcs[7] - .q(rom8_do) - ); -`endif - -//targ -`ifdef targ -wire A = addr[11]; -wire B = addr[12]; -wire C = addr[13]; -wire pap19 = 1'b1; -wire pap20 = addr[10]; -wire pap21 = 1'b0; -`endif - -ttl_74ls138 c5B( - .a(A), - .b(B), - .c(C), - .g1(pup3), - .g2a_n(romsel_n), - .g2b_n(romsel_n), - .y_n(pcs), - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/hra2b-1 b/Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/hra2b-1 deleted file mode 100644 index 8614e2bb..00000000 --- a/Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/hra2b-1 +++ /dev/null @@ -1 +0,0 @@ -ååííååííççïïççïïÁáÉéÅåÍíÃãËëÇçÏï \ No newline at end of file diff --git a/Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/hrl11d-1 b/Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/hrl11d-1 deleted file mode 100644 index a400bc052b57e2731770591a5cbeaed6bfa5baa6..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1024 zcmcCn`hTy@-v4_UZ~&kbP|NZ;_E0yDtXOI8_8x@?= z3@SDt6}aUY671{}@JKVT)zq-zlLyMNGqbZZBNR0p`0(Jth6V?SE)EtU4pw$$NhTH! z0icM0f`Woe2g8FIZVC(?EFdL}%>45F^7h=!j1UbB4mUm=`0?Svf(EcGuY8SZzPWr= ztvWv|1B1ecAA4@pth@8#-oKa^2OJm}nDzhtN-#`+{4%(p%3fCDz=JQ_Y~+ree|GNi zGJdr`1`JFL0xSUx%8U#ii~=kS0t`$OSQJnEwC&{s6&0uzAROLGi=X2Gjems_jn& JM9T<{e*phOvvU9d diff --git a/Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/hrl14h-1 b/Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/hrl14h-1 deleted file mode 100644 index a37d623b..00000000 --- a/Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/hrl14h-1 +++ /dev/null @@ -1 +0,0 @@ -ÎÎÎÎËËËËÍÍÍÍÇÇÇÇðÜãÏðÜãÏðÜãÏðÜãÏ \ No newline at end of file diff --git a/Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/hrl5c-1 b/Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/hrl5c-1 deleted file mode 100644 index 438ed0e4..00000000 --- a/Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/hrl5c-1 +++ /dev/null @@ -1 +0,0 @@ -  \ No newline at end of file diff --git a/Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/stl6d-1 b/Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/stl6d-1 deleted file mode 100644 index d8ae3b0f..00000000 --- a/Arcade_MiST/Exidy-6502 Hardware/rtl/rom/Neuer Ordner/stl6d-1 +++ /dev/null @@ -1 +0,0 @@ -88XX88XX88XX88XXoioi¶°ÖÐøøøøøøøø \ No newline at end of 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zvdfn*cXoa|PUp^@+pu9-?u6~~wZ&mle{J#QM2@&iySgYP#=|g{BSvAlbvdSl)Y*69 zmO@Htt6KON)z6 zvN*DAUgB8Zb!jnDSR7fFOZ(1 zE3YKxX`m~vt@>A2iKRf(7fG+h9i#TL^|-zhBTw3noyY$TG9QUu{qyZ@OP+`?zNY%> zcdN4G8#Y8IRaaNseVG4S>DrR5V-?8grk)3C>)3nTc7?}8OHi=xbQ>1Xc|9chOVk62 ztvAEp41NjFE;q%0}RUjIHO>?V}uB{jp%izqRgD{wM3)sZ-BkB(wR<^Eqhu z<}(8-cHj2=0OcJUZQ%GG_YmpPMnr43qo9XME9l0J)" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone IV GX" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name SYNTHESIS_SEED 1 +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE Standard +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN On +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name VREF_MODE EXTERNAL +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto +set_global_assignment -name AUTO_PACKED_REGISTERS Off +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO +set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_LARGE_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/mist_io.v b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/mist_io.v index 40ced8f8..2f41221f 100644 --- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/mist_io.v +++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/mist_io.v @@ -48,13 +48,16 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) output SPI_DO, input SPI_DI, - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, +// output reg [31:0] joystick_2, +// output reg [31:0] joystick_3, +// output reg [31:0] joystick_4, output reg [15:0] joystick_analog_0, output reg [15:0] joystick_analog_1, output [1:0] buttons, output [1:0] switches, - output scandoubler_disable, + output scandoublerD, output ypbpr, output reg [31:0] status, @@ -98,18 +101,18 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) output reg [7:0] ioctl_index, // menu index used to upload the file output reg ioctl_wr = 0, output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout, - input ioctl_wait + output reg [7:0] ioctl_dout ); reg [7:0] but_sw; reg [2:0] stick_idx; + reg [1:0] mount_strobe = 0; assign img_mounted = mount_strobe; assign buttons = but_sw[1:0]; assign switches = but_sw[3:2]; -assign scandoubler_disable = but_sw[4]; +assign scandoublerD = but_sw[4]; assign ypbpr = but_sw[5]; // this variant of user_io is for 8 bit cores (type == a4) only @@ -168,9 +171,9 @@ always@(posedge SPI_SCK or posedge CONF_DATA0) begin spi_data_out <= sd_cmd; sd_lba_r <= sd_lba; drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin + end else if (byte_cnt == 1) begin spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; + end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; // reading sd card write data 8'h18: spi_data_out <= sd_buff_din; @@ -233,7 +236,11 @@ always@(posedge clk_sys) begin 8'h01: but_sw <= spi_data_in; 8'h02: joystick_0 <= spi_data_in; 8'h03: joystick_1 <= spi_data_in; - +// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; +// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; +// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; +// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; +// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; // store incoming ps2 mouse bytes 8'h04: begin got_ps2 <= 1; @@ -475,7 +482,11 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin if((cmd == UIO_FILE_TX) && (cnt == 15)) begin // prepare if(SPI_DI) begin - addr <= 25'h080000; + case(ioctl_index[4:0]) + 1: addr <= 25'h200000; // TRD buffer at 2MB + 2: addr <= 25'h400000; // tape buffer at 4MB + default: addr <= 25'h150000; // boot rom + endcase rdownload <= 1; end else begin addr_w <= addr; @@ -501,7 +512,7 @@ end always@(posedge clk_sys) begin reg rclkD, rclkD2; - if(ioctl_ce& ~ioctl_wait) begin + if(ioctl_ce) begin ioctl_download <= rdownload; rclkD <= rclk; @@ -516,4 +527,4 @@ always@(posedge clk_sys) begin end end -endmodule +endmodule \ No newline at end of file diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/osd.v b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/osd.v index c62c10af..b9181763 100644 --- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/osd.v +++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/osd.v @@ -11,13 +11,15 @@ module osd ( input SPI_SS3, input SPI_DI, + input [1:0] rotate, //[0] - rotate [1] - left or right + // VGA signals coming from core input [5:0] R_in, input [5:0] G_in, input [5:0] B_in, input HSync, input VSync, - + // VGA signals going to video connector output [5:0] R_out, output [5:0] G_out, @@ -59,7 +61,7 @@ always@(posedge SPI_SCK, posedge SPI_SS3) begin if(cnt == 7) begin cmd <= {sbuf[6:0], SPI_DI}; - + // lower three command bits are line address bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; @@ -91,7 +93,7 @@ reg [9:0] vs_low, vs_high; wire vs_pol = vs_high < vs_low; wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; -wire doublescan = (dsp_height>350); +wire doublescan = (dsp_height>350); reg ce_pix; always @(negedge clk_sys) begin @@ -124,13 +126,13 @@ always @(posedge clk_sys) begin hsD2 <= hsD; // falling edge of HSync - if(!hsD && hsD2) begin + if(!hsD && hsD2) begin h_cnt <= 0; hs_high <= h_cnt; end // rising edge of HSync - else if(hsD && !hsD2) begin + else if(hsD && !hsD2) begin h_cnt <= 0; hs_low <= h_cnt; v_cnt <= v_cnt + 1'd1; @@ -142,13 +144,13 @@ always @(posedge clk_sys) begin vsD2 <= vsD; // falling edge of VSync - if(!vsD && vsD2) begin + if(!vsD && vsD2) begin v_cnt <= 0; vs_high <= v_cnt; end // rising edge of VSync - else if(vsD && !vsD2) begin + else if(vsD && !vsD2) begin v_cnt <= 0; vs_low <= v_cnt; end @@ -160,17 +162,30 @@ wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); -reg [7:0] osd_byte; -always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; +reg [10:0] osd_buffer_addr; +wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; +reg osd_pixel; -wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; +always @(posedge clk_sys) begin + if(ce_pix) begin + osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], + rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : + (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : + {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; + + osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : + osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + end +end assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace.hex b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/roms/ace.hex similarity index 100% rename from Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace.hex rename to Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/roms/ace.hex diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace.mif b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/roms/ace.mif similarity index 100% rename from Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace.mif rename to Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/roms/ace.mif diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace.rom b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/roms/ace.rom similarity index 100% rename from Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace.rom rename to Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/roms/ace.rom diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/video_mixer.sv b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/video_mixer.sv index ec953e53..79d8ca03 100644 --- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/video_mixer.sv +++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/video_mixer.sv @@ -20,10 +20,10 @@ module video_mixer #( - parameter LINE_LENGTH = 768, - parameter HALF_DEPTH = 0, + parameter LINE_LENGTH = 480, + parameter HALF_DEPTH = 1, - parameter OSD_COLOR = 3'd7, + parameter OSD_COLOR = 3'd4, parameter OSD_X_OFFSET = 10'd0, parameter OSD_Y_OFFSET = 10'd0 ) @@ -50,7 +50,7 @@ module video_mixer input [1:0] scanlines, // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoubler_disable, + input scandoublerD, // High quality 2x scaling input hq2x, @@ -60,7 +60,7 @@ module video_mixer // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) input ypbpr_full, - + input [1:0] rotate, //[0] - rotate [1] - left or right // color input [DWIDTH:0] R, input [DWIDTH:0] G, @@ -113,9 +113,9 @@ scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler .b_out(B_sd) ); -wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); -wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); -wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); +wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); +wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); +wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); generate if(HALF_DEPTH) begin @@ -129,8 +129,8 @@ generate end endgenerate -wire hs = (scandoubler_disable ? HSync : hs_sd); -wire vs = (scandoubler_disable ? VSync : vs_sd); +wire hs = (scandoublerD ? HSync : hs_sd); +wire vs = (scandoublerD ? VSync : vs_sd); reg scanline = 0; always @(posedge clk_sys) begin @@ -182,6 +182,7 @@ osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd .B_in(b_out), .HSync(hs), .VSync(vs), + .rotate(rotate), .R_out(red), .G_out(green), @@ -236,7 +237,7 @@ wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[1 assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; +assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; endmodule