From e8b3af1e6b322df8bc01d778d0218d9c8bd20b14 Mon Sep 17 00:00:00 2001 From: Marcel Date: Sun, 22 Feb 2026 16:57:18 +0100 Subject: [PATCH] Some Work still WIP --- Arcade_MiST/Konami Tutankham/Tutankham.qsf | 164 +++++++++--------- .../Konami Tutankham/rtl/TimePilot_SND.sv | 9 +- Arcade_MiST/Konami Tutankham/rtl/Tutankham.sv | 36 ++-- .../Konami Tutankham/rtl/Tutankham_CPU.sv | 63 ++++++- .../Konami Tutankham/rtl/Tutankham_TOP.sv | 9 +- Arcade_MiST/Konami Tutankham/rtl/blitter.sv | 151 ++++++++++++++++ 6 files changed, 331 insertions(+), 101 deletions(-) create mode 100644 Arcade_MiST/Konami Tutankham/rtl/blitter.sv diff --git a/Arcade_MiST/Konami Tutankham/Tutankham.qsf b/Arcade_MiST/Konami Tutankham/Tutankham.qsf index 2225797e..59d3fbc6 100644 --- a/Arcade_MiST/Konami Tutankham/Tutankham.qsf +++ b/Arcade_MiST/Konami Tutankham/Tutankham.qsf @@ -1,6 +1,6 @@ # -------------------------------------------------------------------------- # # -# Copyright (C) 1991-2014 Altera Corporation +# Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing @@ -17,15 +17,15 @@ # -------------------------------------------------------------------------- # # # Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 21:36:26 March 08, 2019 +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 16:55:52 February 22, 2026 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: -# xevious_MiST_assignment_defaults.qdf +# Tutankham_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # @@ -44,6 +44,24 @@ set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:59:05 MARCH 16, 2017 set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Tutankham.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Tutankham_TOP.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Tutankham_CPU.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/TimePilot_SND.sv +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/rom_loader.sv +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd +set_global_assignment -name VERILOG_FILE rtl/jtframe_frac_cen.v +set_global_assignment -name VHDL_FILE rtl/dpram_dc.vhd +set_global_assignment -name QIP_FILE rtl/custom/tut_custom.qip +set_global_assignment -name SYSTEMVERILOG_FILE rtl/blitter.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv +set_global_assignment -name QIP_FILE ../../common/CPU/MC6809/mc6809.qip +set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip +set_global_assignment -name QIP_FILE ../../common/Sound/JT49/jt49.qip +set_global_assignment -name QIP_FILE ../../common/Sound/JT49/filter/jt49_filters.qip +set_global_assignment -name QIP_FILE ../../common/mist/mist.qip # Pin & Location Assignments # ========================== @@ -119,13 +137,13 @@ set_location_assignment PIN_33 -to SDRAM_CKE set_location_assignment PIN_43 -to SDRAM_CLK set_location_assignment PIN_31 -to UART_RX set_location_assignment PIN_46 -to UART_TX - - +set_location_assignment PLL_1 -to pll|altpll_component|auto_generated|pll1 # Classic Timing Assignments # ========================== set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON # Analysis & Synthesis Assignments # ================================ @@ -136,6 +154,9 @@ set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF set_global_assignment -name TOP_LEVEL_ENTITY Tutankham +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF # Fitter Assignments # ================== @@ -150,6 +171,15 @@ set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF # EDA Netlist Writer Assignments # ============================== @@ -160,6 +190,11 @@ set_global_assignment -name EDA_SIMULATION_TOOL "" set_global_assignment -name USE_CONFIGURATION_DEVICE OFF set_global_assignment -name GENERATE_RBF_FILE ON +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/custom.stp + # Power Estimation Assignments # ============================ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" @@ -177,90 +212,63 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # EDA Netlist Writer Assignments # ============================== -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation + set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation # end EDA_TOOL_SETTINGS(eda_simulation) # ------------------------------------- -# ------------------------- -# start ENTITY(xevious_mist) +# ----------------------- +# start ENTITY(Tutankham) + + # Pin & Location Assignments + # ========================== + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS + set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] + set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] + + # Fitter Assignments + # ================== + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*] + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*] + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*] + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*] + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*] + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*] + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS + set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L + set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R + set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO # start DESIGN_PARTITION(Top) # --------------------------- # Incremental Compilation Assignments # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- -# end ENTITY(xevious_mist) -# ----------------------- -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/custom.stp -set_location_assignment PLL_1 -to pll|altpll_component|auto_generated|pll1 -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Tutankham.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Tutankham_TOP.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Tutankham_CPU.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/TimePilot_SND.sv -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/rom_loader.sv -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VERILOG_FILE rtl/jtframe_frac_cen.v -set_global_assignment -name VHDL_FILE rtl/dpram_dc.vhd -set_global_assignment -name QIP_FILE rtl/custom/tut_custom.qip -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv -set_global_assignment -name QIP_FILE ../../common/CPU/MC6809/mc6809.qip -set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip -set_global_assignment -name QIP_FILE ../../common/Sound/JT49/jt49.qip -set_global_assignment -name QIP_FILE ../../common/Sound/JT49/filter/jt49_filters.qip -set_global_assignment -name QIP_FILE ../../common/mist/mist.qip -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO +# end ENTITY(Tutankham) +# --------------------- set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Konami Tutankham/rtl/TimePilot_SND.sv b/Arcade_MiST/Konami Tutankham/rtl/TimePilot_SND.sv index 6efe211b..15589ee0 100644 --- a/Arcade_MiST/Konami Tutankham/rtl/TimePilot_SND.sv +++ b/Arcade_MiST/Konami Tutankham/rtl/TimePilot_SND.sv @@ -47,8 +47,8 @@ module TimePilot_SND input underclock, input ep7_cs_i, - output reg [15:0] sound_A, - input [7:0] eprom7_D, + output [12:0] Sound_Rom_Addr, + input [7:0] Sound_Rom_Data, input [24:0] ioctl_addr, input [7:0] ioctl_data, input ioctl_wr @@ -90,7 +90,7 @@ jtframe_frac_cen #(10) sound_cen //------------------------------------------------------------ CPU -------------------------------------------------------------// //Sound CPU - Zilog Z80 (uses T80s version of the T80 soft core) -//wire [15:0] sound_A; +wire [15:0] sound_A; wire [7:0] sound_Dout; wire n_m1, n_mreq, n_iorq, n_rd, n_wr, n_rfsh; T80s C8 @@ -126,7 +126,8 @@ wire [7:0] sound_Din = 8'hFF; //Sound ROM -//wire [7:0] eprom7_D; +assign Sound_Rom_Addr = sound_A[12:0]; +wire [7:0] eprom7_D = Sound_Rom_Data; //eprom_7 A6 //( // .ADDR(sound_A[12:0]), diff --git a/Arcade_MiST/Konami Tutankham/rtl/Tutankham.sv b/Arcade_MiST/Konami Tutankham/rtl/Tutankham.sv index 22ae336c..9848da68 100644 --- a/Arcade_MiST/Konami Tutankham/rtl/Tutankham.sv +++ b/Arcade_MiST/Konami Tutankham/rtl/Tutankham.sv @@ -36,6 +36,9 @@ localparam CONF_STR = { "O2,Rotate Controls,Off,On;", "O34,Scanlines,Off,25%,50%,75%;", "O5,Blend,Off,On;", + + "O6,Service,Off,On;", + "OOR,CRT H adjust,0,+1,+2,+3,+4,+5,+6,+7,-8,-7,-6,-5,-4,-3,-2,-1;", "OSV,CRT V adjust,0,+1,+2,+3,+4,+5,+6,+7,-8,-7,-6,-5,-4,-3,-2,-1;", "DIP;", @@ -72,7 +75,7 @@ wire no_csync; wire key_strobe; wire key_pressed; wire [7:0] key_code; -wire [6:0] core_mod; +wire [6:0] core_mod;// for Juno First(later) user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io( .clk_sys (clk_sys ), @@ -100,6 +103,8 @@ wire [7:0] ioctl_index; wire ioctl_wr; wire [24:0] ioctl_addr; wire [7:0] ioctl_dout; +wire [12:0] Sound_Rom_Addr; +wire [7:0] Sound_Rom_Data; data_io data_io( .clk_sys ( clk_sys ), @@ -128,9 +133,9 @@ sdram #(49) sdram( .port1_q ( ), .cpu1_addr ( 16'hffff),//ioctl_downl ? 16'hffff : {2'b00, main_rom_addr[14:1]} ), - .cpu1_q ( main_rom_do ), - .cpu2_addr ( 16'hffff),//ioctl_downl ? 16'hffff : sub_rom_addr[12:1] + 16'h3000 ), - .cpu2_q ( sub_rom_do ), + .cpu1_q ( ), + .cpu2_addr ( 16'hffff),//ioctl_downl ? 16'hffff : Sound_Rom_Addr[12:1] + 16'h3000 ), + .cpu2_q ( Sound_Rom_Data ), .cpu3_addr ( 16'hffff),//), .cpu3_q ( ), @@ -179,9 +184,10 @@ assign { voffset, hoffset } = status[31:24]; Tutankham_TOP Tutankham_TOP_inst ( .reset(~reset), - .clk_49m(clk_sys) , // input clk_49m_sig -// .coin(coin_sig) , // input [1:0] coin_sig -// .start_buttons(start_buttons_sig) , // input [1:0] start_buttons_sig + .clk_49m(clk_sys), +// .juno(), + .coin({m_coin2, m_coin1}), + .start_buttons({m_two_players, m_one_player}), // .p1_joystick(p1_joystick_sig) , // input [3:0] p1_joystick_sig // .p2_joystick(p2_joystick_sig) , // input [3:0] p2_joystick_sig // .p1_fire(p1_fire_sig) , // input p1_fire_sig @@ -192,7 +198,8 @@ Tutankham_TOP Tutankham_TOP_inst // .m_fire2_l(m_fire2_l_sig) , // input m_fire2_l_sig // .m_fire2_r(m_fire2_r_sig) , // input m_fire2_r_sig // .m_flash2(m_flash2_sig) , // input m_flash2_sig -// .btn_service(btn_service_sig) , // input btn_service_sig + + .btn_service(status[6]), // .dip_sw(dip_sw_sig) , // input [15:0] dip_sw_sig .video_hsync(hs), .video_vsync(vs), @@ -204,16 +211,19 @@ Tutankham_TOP Tutankham_TOP_inst .video_g(g), .video_b(b), .sound(audio), - .h_center (hoffset), - .v_center (voffset), + .h_center(hoffset), + .v_center(voffset), +//Rom Data // .cpu_A(cpu_A_sig) , // output [15:0] cpu_A_sig // .mainrom_D(mainrom_D_sig) , // input [7:0] mainrom_D_sig -// .sound_A(sound_A_sig) , // output [15:0] sound_A_sig - .eprom7_D(eprom7_D_sig), + .Sound_Rom_Addr(Sound_Rom_Addr), + .Sound_Rom_Data(Sound_Rom_Data), + .ioctl_addr(ioctl_addr), - .ioctl_data(ioctl_data), + .ioctl_data(ioctl_dout), .ioctl_wr(ioctl_wr), .ioctl_index(ioctl_index), + .pause(0), .underclock(0), .hs_address(), diff --git a/Arcade_MiST/Konami Tutankham/rtl/Tutankham_CPU.sv b/Arcade_MiST/Konami Tutankham/rtl/Tutankham_CPU.sv index 2b5cf512..62fd7d48 100644 --- a/Arcade_MiST/Konami Tutankham/rtl/Tutankham_CPU.sv +++ b/Arcade_MiST/Konami Tutankham/rtl/Tutankham_CPU.sv @@ -175,7 +175,7 @@ end //------------------------------------------------------------ CPUs ------------------------------------------------------------// -//Primary CPU - Motorola MC6809E +//Primary CPU - Motorola MC6809E ( Konami1 for Juno First) //wire [15:0] cpu_A; wire [7:0] cpu_Dout; wire cpu_RnW; @@ -200,6 +200,43 @@ mc6809e E3 ); //------------------------------------------------------ Address decoding ------------------------------------------------------// +// tutankham +// +// -- DIPS2 $8160 +// dip2_cs <= '1' when STD_MATCH(cpu_a, X"816"&"----") else '0'; +// -- IN0 $8180 +// in0_cs <= '1' when STD_MATCH(cpu_a, X"818"&"----") else '0'; +// -- IN1 $81A0 +// in1_cs <= '1' when STD_MATCH(cpu_a, X"81A"&"----") else '0'; +// -- IN2 $81C0 +// in2_cs <= '1' when STD_MATCH(cpu_a, X"81C"&"----") else '0'; +// -- DIPS1 $81E0 +// dip1_cs <= '1' when STD_MATCH(cpu_a, X"81E"&"----") else '0'; +// -- Interrupt Enable $8200 +// intena_cs <= '1' when STD_MATCH(cpu_a, X"8200") else '0'; +// -- RAM $8800-$8FFF +// wram_cs <= '1' when STD_MATCH(cpu_a, X"8"&"1-----------") else '0'; +// + + +// junofrst +// +// -- DIPS2 $8010 +// dip2_cs <= '1' when STD_MATCH(cpu_a, X"8010") else '0'; +// -- IN0 $8020 +// in0_cs <= '1' when STD_MATCH(cpu_a, X"8020") else '0'; +// -- IN1 $8024 +// in1_cs <= '1' when STD_MATCH(cpu_a, X"8024") else '0'; +// -- IN2 $8028 +// in2_cs <= '1' when STD_MATCH(cpu_a, X"8028") else '0'; +// -- DIPS1 $802C +// dip1_cs <= '1' when STD_MATCH(cpu_a, X"802C") else '0'; +// -- Interrupt Enable $8030 +// intena_cs <= '1' when STD_MATCH(cpu_a, X"8030") else '0'; +// -- blitter +// blitter_cs <= '1' when STD_MATCH(cpu_a, X"807" & "00--") else '0'; +// -- RAM $8100-$8FFF +// wram_cs <= '1' when STD_MATCH(cpu_a, X"8"&"------------") else '0'; //Tutankham memory map wire n_cs_videoram = ~(cpu_A[15] == 1'b0); // 0x0000-0x7FFF (32KB video RAM) @@ -224,7 +261,7 @@ wire cs_in1 = (cpu_A[15:4] == 12'h81A); // 0x81A0 (IN1: P1 co wire cs_in2 = (cpu_A[15:4] == 12'h81C); // 0x81C0 (IN2: P2 controls) wire cs_dsw1 = (cpu_A[15:4] == 12'h81E); // 0x81E0 (DIP SW1) wire cs_mainlatch = (cpu_A[15:3] == 13'h1040) & ~cpu_RnW; // 0x8200-0x8207 (main latch) -wire cs_banksel_wr = (cpu_A[15:8] == 8'h83) & ~cpu_RnW; // 0x8300 (bank select) +wire cs_banksel_wr = (cpu_A[15:8] == 8'h83) & ~cpu_RnW; // 0x8300 (bank select) (8060 for Juno First) wire cs_soundon = (cpu_A[15:8] == 8'h86) & ~cpu_RnW; // 0x8600 (sound enable) wire cs_soundcmd = (cpu_A[15:8] == 8'h87) & ~cpu_RnW; // 0x8700 (sound command) @@ -336,6 +373,28 @@ eprom_4k bank7 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(bank7_D), eprom_4k bank8 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(bank8_D), .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data), .CS_DL(bank8_cs_i), .WR(ioctl_wr)); + +//Blitter ToDo + +//blitter blitter_inst +//( +// .clk_30M(clk_30M_sig) , // input clk_30M_sig +// .rst_30M(rst_30M_sig) , // input rst_30M_sig +// .clk_1M5_en(clk_1M5_en_sig) , // input clk_1M5_en_sig +// .blitter_cs(blitter_cs_sig) , // input blitter_cs_sig +// .cpu_a(cpu_a_sig) , // input [1:0] cpu_a_sig +// .cpu_d_o(cpu_d_o_sig) , // input [7:0] cpu_d_o_sig +// .cpu_rw(cpu_rw_sig) , // input cpu_rw_sig +// .cpu_ba(cpu_ba_sig) , // input cpu_ba_sig +// .cpu_bs(cpu_bs_sig) , // input cpu_bs_sig +// .vram_cs(vram_cs_sig) , // input vram_cs_sig +// .blitter_copy(blitter_copy_sig) , // input blitter_copy_sig +// .blitter_d_o(blitter_d_o_sig) , // input [7:0] blitter_d_o_sig +// .cpu_halt(cpu_halt_sig) , // output cpu_halt_sig +// .vram_a(vram_a_sig) , // output [15:0] vram_a_sig +// .vram_d_i(vram_d_i_sig) , // output [7:0] vram_d_i_sig +// .vram_wr(vram_wr_sig) // output [1:0] vram_wr_sig +//); //------------------------------------------------------------ RAM ------------------------------------------------------------// diff --git a/Arcade_MiST/Konami Tutankham/rtl/Tutankham_TOP.sv b/Arcade_MiST/Konami Tutankham/rtl/Tutankham_TOP.sv index e109fd17..838b0299 100644 --- a/Arcade_MiST/Konami Tutankham/rtl/Tutankham_TOP.sv +++ b/Arcade_MiST/Konami Tutankham/rtl/Tutankham_TOP.sv @@ -49,8 +49,9 @@ module Tutankham_TOP output [15:0] cpu_A, input [7:0] mainrom_D, // input [7:0] bank_rom_D, - output [15:0] sound_A,//13bit used - input [7:0] eprom7_D, + + output [12:0] Sound_Rom_Addr, + input [7:0] Sound_Rom_Data, input [24:0] ioctl_addr, input [7:0] ioctl_data, input ioctl_wr, @@ -196,8 +197,8 @@ TimePilot_SND sound_pcb .underclock(underclock), .ep7_cs_i(ep7_cs_i), - .sound_A(sound_A), - .eprom7_D(eprom7_D), + .Sound_Rom_Addr(Sound_Rom_Addr), + .Sound_Rom_Data(Sound_Rom_Data), .ioctl_addr(ioctl_addr), .ioctl_wr(ioctl_wr_snd), .ioctl_data(ioctl_data) diff --git a/Arcade_MiST/Konami Tutankham/rtl/blitter.sv b/Arcade_MiST/Konami Tutankham/rtl/blitter.sv new file mode 100644 index 00000000..31495473 --- /dev/null +++ b/Arcade_MiST/Konami Tutankham/rtl/blitter.sv @@ -0,0 +1,151 @@ +module blitter ( + input wire clk_30M, + input wire rst_30M, + input wire clk_1M5_en, + input wire blitter_cs, + input wire [1:0] cpu_a, + input wire [7:0] cpu_d_o, + input wire cpu_rw, + input wire cpu_ba, + input wire cpu_bs, + input wire vram_cs, + input wire blitter_copy, + input wire [7:0] blitter_d_o, // VRAM data output + output reg cpu_halt, + output wire [15:0] vram_a, + output wire [7:0] vram_d_i, + output wire [1:0] vram_wr +); + + // Blitter Registers + reg [15:0] blitter_src_r; + reg [15:0] blitter_dst_r; + reg blitter_go; + + // Internal SM signals + reg blitting; + reg [1:0] blitter_wr; + reg [15:0] blitter_src; + reg [15:0] blitter_dst; + reg [3:0] blitter_d_i; + + integer x, y; + + // State Encoding + localparam S_IDLE = 3'd0, + S_HALTING = 3'd1, + S_BLIT_0 = 3'd2, + S_BLIT = 3'd3, + S_INC_0 = 3'd4, + S_INC = 3'd5; + reg [2:0] state; + + // Blitter Register Process + always @(posedge clk_30M or posedge rst_30M) begin + if (rst_30M) begin + blitter_src_r <= 16'h0; + blitter_dst_r <= 16'h0; + blitter_go <= 1'b0; + end else begin + blitter_go <= 1'b0; // Pulse default + if (clk_1M5_en) begin + if (blitter_cs && !cpu_rw) begin + case (cpu_a[1:0]) + 2'b00: blitter_dst_r[15:8] <= cpu_d_o; + 2'b01: blitter_dst_r[7:0] <= cpu_d_o; + 2'b10: blitter_src_r[15:8] <= cpu_d_o; + 2'b11: begin + blitter_src_r[7:0] <= cpu_d_o; + blitter_go <= 1'b1; + end + endcase + end + end + end + end + + // Blitter State Machine Process + always @(posedge clk_30M or posedge rst_30M) begin + if (rst_30M) begin + cpu_halt <= 1'b0; + blitting <= 1'b0; + blitter_wr <= 2'b00; + state <= S_IDLE; + x <= 0; y <= 0; + end else begin + case (state) + S_IDLE: begin + blitting <= 1'b0; + if (blitter_go) begin + cpu_halt <= 1'b1; + state <= S_HALTING; + end + end + + S_HALTING: begin + if (cpu_ba && cpu_bs) begin + blitting <= 1'b1; + // VHDL logic: (src[15:2] & "00") + 1 + blitter_src <= {blitter_src_r[15:2], 2'b00} + 16'd1; + blitter_dst <= blitter_dst_r; + y <= 0; + x <= 0; + state <= S_BLIT_0; + end + end + + S_BLIT_0: begin + blitter_d_i <= blitter_src[0] ? blitter_d_o[7:4] : blitter_d_o[3:0]; + state <= S_BLIT; + end + + S_BLIT: begin + if (blitter_d_i != 4'h0) begin + if (blitter_dst[0]) blitter_wr[1] <= 1'b1; + else blitter_wr[0] <= 1'b1; + end + state <= S_INC_0; + end + + S_INC_0: begin + blitter_wr <= 2'b00; + state <= S_INC; + end + + S_INC: begin + blitter_src <= blitter_src + 1'b1; + blitter_wr <= 2'b00; + if (x == 15) begin + if (y == 15) begin + cpu_halt <= 1'b0; + state <= S_IDLE; + end else begin + x <= 0; + y <= y + 1; + blitter_dst <= blitter_dst + 16'd241; + state <= S_BLIT_0; + end + end else begin + x <= x + 1; + blitter_dst <= blitter_dst + 16'd1; + state <= S_BLIT_0; + end + end + + default: begin + cpu_halt <= 1'b0; + state <= S_IDLE; + end + endcase + end + end + + // Video RAM Data Muxing + assign vram_a = (!blitting) ? cpu_a : blitter_dst[16:1]; + + assign vram_d_i = (!blitting) ? cpu_d_o : + (!blitter_copy) ? 8'h00 : {blitter_d_i, blitter_d_i}; + + assign vram_wr = (!blitting) ? {2{(vram_cs && clk_1M5_en && !cpu_rw)}} : blitter_wr; + +endmodule