diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/DottoriKun.qsf b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/DottoriKun.qsf index 34caa0bf..fc97dbfb 100644 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/DottoriKun.qsf +++ b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/DottoriKun.qsf @@ -43,24 +43,6 @@ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:44:34 AUGUST 14, 2017" set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name SYSTEMVERILOG_FILE rtl/DottoriKun_MiST.sv -set_global_assignment -name VERILOG_FILE rtl/dottori.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/RAM.v -set_global_assignment -name VERILOG_FILE rtl/pll.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_reg.v -set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_mcode.v -set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_core.v -set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_alu.v -set_global_assignment -name VERILOG_FILE rtl/tv80/cpu_z80.v -set_global_assignment -name VERILOG_FILE rtl/ROM1.v -set_global_assignment -name VERILOG_FILE rtl/ROM2.v -set_global_assignment -name VERILOG_FILE rtl/ROM3.v -set_global_assignment -name VERILOG_FILE rtl/ROM4.v # Pin & Location Assignments # ========================== @@ -182,4 +164,15 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # end ENTITY(DottoriKun_MiST) # --------------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name SYSTEMVERILOG_FILE rtl/DottoriKun_MiST.sv +set_global_assignment -name VERILOG_FILE rtl/dottori.v +set_global_assignment -name VERILOG_FILE rtl/ROM1.v +set_global_assignment -name VERILOG_FILE rtl/ROM2.v +set_global_assignment -name VERILOG_FILE rtl/ROM3.v +set_global_assignment -name VERILOG_FILE rtl/ROM4.v +set_global_assignment -name VERILOG_FILE rtl/RAM.v +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name VERILOG_FILE rtl/cpu_z80.v +set_global_assignment -name QIP_FILE ../../../common/CPU/tv80/TV80.qip +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip \ No newline at end of file diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/DottoriKun_MiST.sv b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/DottoriKun_MiST.sv index 5a36a599..82a12465 100644 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/DottoriKun_MiST.sv +++ b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/DottoriKun_MiST.sv @@ -16,26 +16,17 @@ module DottoriKun_MiST( input CLOCK_27 ); -`include "rtl\build_id.sv" +`include "rtl\build_id.v" localparam CONF_STR = { "DottoriKun;;", "O12,ROM ,ORIG,ORIG,MINE,PACM;", - "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;", + "O5,Blend,Off,On;", "T6,Reset;", "V,v1.00.",`BUILD_DATE }; - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [9:0] kbjoy; -wire [7:0] joy0, joy1; -wire scandoubler_disable; -wire ypbpr; -wire ps2_kbd_clk, ps2_kbd_data; -wire [7:0] audio; -wire video; +assign LED = 1; wire clk_32, clk_8, clk_4; pll pll @@ -46,6 +37,15 @@ pll pll .c2(clk_4) ); +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] joystick_0, joystick_1; +wire scandoublerD; +wire ypbpr; +wire r, g, b; +wire hs, vs; + dottori dottori ( .CLK_4M(clk_4), .RED(r), @@ -55,72 +55,89 @@ dottori dottori ( .vSYNC(vs), .hSYNC(hs), .nRESET(~(status[0] | status[6] | buttons[1])), - .BUTTONS({ ~(kbjoy[5]), //Test Mode - ~(kbjoy[6]), //Start - ~(joy0[5] | joy1[5] | kbjoy[7]), //Button 2 - Pause - ~(joy0[4] | joy1[4] | kbjoy[4]), //Button 1 - ~(joy0[0] | joy1[0] | kbjoy[0]), //Right - ~(joy0[1] | joy1[1] | kbjoy[1]), //Left - ~(joy0[2] | joy1[2] | kbjoy[2]), //Down - ~(joy0[3] | joy1[3] | kbjoy[3])})//Up + .BUTTONS(~{btn_one_player, btn_coin, m_bomb, m_fire, m_right, m_left, m_down, m_up}) ); -wire hs; -wire vs; - -video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer -( - .clk_sys(clk_32), - .ce_pix(clk_8), - .ce_pix_actual(clk_8), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({r,r,r}), - .G({g,g,g}), - .B({b,b,b}), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .scandoubler_disable(scandoubler_disable), - .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), - .hq2x(status[4:3]==1), - .ypbpr_full(1), - .line_start(0), - .mono(0) -); - -mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io -( - .clk_sys (clk_32 ), +mist_video #(.COLOR_DEPTH(1), .SD_HCNT_WIDTH(10)) mist_video( + .clk_sys ( clk_32 ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R ( r ), + .G ( g ), + .B ( b ), + .HSync ( hs ), + .VSync ( vs ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ), + .rotate ( 2'b00 ), + .ce_divider ( 1'b1 ), + .blend ( status[5] ), + .scandoubler_disable(scandoublerD ), + .scanlines ( status[4:3] ), + .ypbpr ( ypbpr ) + ); + +user_io #( + .STRLEN(($size(CONF_STR)>>3))) +user_io( + .clk_sys (clk_32 ), .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), .buttons (buttons ), - .switches (switches ), - .scandoubler_disable(scandoubler_disable), + .switches (switches ), + .scandoubler_disable (scandoublerD ), .ypbpr (ypbpr ), - .ps2_kbd_clk (ps2_kbd_clk ), - .ps2_kbd_data (ps2_kbd_data ), - .joystick_0 (joy0 ), - .joystick_1 (joy1 ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), .status (status ) -); - -keyboard keyboard( - .clk(clk_32), - .reset(), - .ps2_kbd_clk(ps2_kbd_clk), - .ps2_kbd_data(ps2_kbd_data), - .joystick(kbjoy) ); +wire m_up = btn_up | joystick_0[3] | joystick_1[3]; +wire m_down = btn_down | joystick_0[2] | joystick_1[2]; +wire m_left = btn_left | joystick_0[1] | joystick_1[1]; +wire m_right = btn_right | joystick_0[0] | joystick_1[0]; +wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; +wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; -endmodule +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +reg btn_fire2 = 0; +reg btn_fire3 = 0; +reg btn_coin = 0; +wire key_strobe; +wire key_pressed; +wire [7:0] key_code; + +always @(posedge clk_32) begin + if(key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 + 'h14: btn_fire3 <= key_pressed; // ctrl + 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/ROM1.qip b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/ROM1.qip deleted file mode 100644 index f7215077..00000000 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/ROM1.qip +++ /dev/null @@ -1,3 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ROM1.v"] diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/ROM2.qip b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/ROM2.qip deleted file mode 100644 index 4a53daf3..00000000 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/ROM2.qip +++ /dev/null @@ -1,3 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ROM2.v"] diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/ROM3.qip b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/ROM3.qip deleted file mode 100644 index f2d0a08b..00000000 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/ROM3.qip +++ /dev/null @@ -1,3 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ROM3.v"] diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/build_id.sv b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/build_id.sv deleted file mode 100644 index 6efa26c3..00000000 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/build_id.sv +++ /dev/null @@ -1,2 +0,0 @@ -`define BUILD_DATE "180816" -`define BUILD_TIME "200421" diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/build_id.tcl b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/build_id.tcl index 189e97c8..481e9ebf 100644 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/build_id.tcl +++ b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/build_id.tcl @@ -17,7 +17,7 @@ proc generateBuildID_Verilog {} { set buildTime [ clock format [ clock seconds ] -format %H%M%S ] # Create a Verilog file for output - set outputFileName "sys/build_id.sv" + set outputFileName "sys/build_id.v" set outputFile [open $outputFileName "w"] # Output the Verilog source diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/tv80/cpu_z80.v b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/cpu_z80.v similarity index 98% rename from Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/tv80/cpu_z80.v rename to Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/cpu_z80.v index cf6c6811..d8a15f3b 100644 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/tv80/cpu_z80.v +++ b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/cpu_z80.v @@ -26,6 +26,8 @@ module cpu_z80( tv80_core TV80( , IORQ, NO_READ, WRITE, , , , ADDRESS, DATA_OUT, M_CYCLE, T_STATE, nINTCYCLE, , , nRESET, CLK, 1'b1, 1'b1, nINT, nNMI, 1'b1, DATA_IN, DATA_IN_REG); + + always @(posedge CLK) begin diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/hq2x.sv b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/hq2x.sv deleted file mode 100644 index 564b3f1c..00000000 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - casex({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/keyboard.sv b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/keyboard.sv deleted file mode 100644 index 01625319..00000000 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/keyboard.sv +++ /dev/null @@ -1,79 +0,0 @@ - - -module keyboard -( - input clk, - input reset, - input ps2_kbd_clk, - input ps2_kbd_data, - - output reg[7:0] joystick -); - -reg [11:0] shift_reg = 12'hFFF; -wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; -wire [7:0] kcode = kdata[9:2]; -reg release_btn = 0; - -reg [7:0] code; -reg input_strobe = 0; - -always @(negedge clk) begin - reg old_reset = 0; - - old_reset <= reset; - - if(~old_reset & reset)begin - joystick <= 0; - end - - if(input_strobe) begin - case(code) - 'h75: joystick[3] <= ~release_btn; // arrow up - 'h72: joystick[2] <= ~release_btn; // arrow down - 'h6B: joystick[1] <= ~release_btn; // arrow left - 'h74: joystick[0] <= ~release_btn; // arrow right - - 'h29: joystick[4] <= ~release_btn; // Space - 'h05: joystick[5] <= ~release_btn; // F1 - 'h06: joystick[6] <= ~release_btn; // F2 - 'h76: joystick[7] <= ~release_btn; // Escape - endcase - end -end - -always @(posedge clk) begin - reg [3:0] prev_clk = 0; - reg old_reset = 0; - reg action = 0; - - old_reset <= reset; - input_strobe <= 0; - - if(~old_reset & reset)begin - prev_clk <= 0; - shift_reg <= 12'hFFF; - end else begin - prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; - if(prev_clk == 1) begin - if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin - shift_reg <= 12'hFFF; - if (kcode == 8'he0) ; - // Extended key code follows - else if (kcode == 8'hf0) - // Release code follows - action <= 1; - else begin - // Cancel extended/release flags for next time - action <= 0; - release_btn <= action; - code <= kcode; - input_strobe <= 1; - end - end else begin - shift_reg <= kdata; - end - end - end -end -endmodule diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/mist_io.v b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/osd.v b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/scandoubler.v b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/scandoubler.v deleted file mode 100644 index e85cba43..00000000 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,183 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/tv80/tv80_alu.v b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/tv80/tv80_alu.v deleted file mode 100644 index f90bc70a..00000000 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/tv80/tv80_alu.v +++ /dev/null @@ -1,442 +0,0 @@ -// -// TV80 8-Bit Microprocessor Core -// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) -// -// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a -// copy of this software and associated documentation files (the "Software"), -// to deal in the Software without restriction, including without limitation -// the rights to use, copy, modify, merge, publish, distribute, sublicense, -// and/or sell copies of the Software, and to permit persons to whom the -// Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included -// in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -module tv80_alu (/*AUTOARG*/ - // Outputs - Q, F_Out, - // Inputs - Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In - ); - - parameter Mode = 0; - parameter Flag_C = 0; - parameter Flag_N = 1; - parameter Flag_P = 2; - parameter Flag_X = 3; - parameter Flag_H = 4; - parameter Flag_Y = 5; - parameter Flag_Z = 6; - parameter Flag_S = 7; - - input Arith16; - input Z16; - input [3:0] ALU_Op ; - input [5:0] IR; - input [1:0] ISet; - input [7:0] BusA; - input [7:0] BusB; - input [7:0] F_In; - output [7:0] Q; - output [7:0] F_Out; - reg [7:0] Q; - reg [7:0] F_Out; - - function [4:0] AddSub4; - input [3:0] A; - input [3:0] B; - input Sub; - input Carry_In; - begin - AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {4'h0,Carry_In}; - end - endfunction // AddSub4 - - function [3:0] AddSub3; - input [2:0] A; - input [2:0] B; - input Sub; - input Carry_In; - begin - AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {3'h0,Carry_In}; - end - endfunction // AddSub4 - - function [1:0] AddSub1; - input A; - input B; - input Sub; - input Carry_In; - begin - AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {1'h0,Carry_In}; - end - endfunction // AddSub4 - - // AddSub variables (temporary signals) - reg UseCarry; - reg Carry7_v; - reg OverFlow_v; - reg HalfCarry_v; - reg Carry_v; - reg [7:0] Q_v; - - reg [7:0] BitMask; - - - always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR) - begin - case (IR[5:3]) - 3'b000 : BitMask = 8'b00000001; - 3'b001 : BitMask = 8'b00000010; - 3'b010 : BitMask = 8'b00000100; - 3'b011 : BitMask = 8'b00001000; - 3'b100 : BitMask = 8'b00010000; - 3'b101 : BitMask = 8'b00100000; - 3'b110 : BitMask = 8'b01000000; - default: BitMask = 8'b10000000; - endcase // case(IR[5:3]) - - UseCarry = ~ ALU_Op[2] && ALU_Op[0]; - { HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) ); - { Carry7_v, Q_v[6:4] } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v); - { Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v); - OverFlow_v = Carry_v ^ Carry7_v; - end // always @ * - - reg [7:0] Q_t; - reg [8:0] DAA_Q; - - always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB - or Carry_v or F_In or HalfCarry_v or IR or ISet - or OverFlow_v or Q_v or Z16) - begin - Q_t = 8'hxx; - DAA_Q = {9{1'bx}}; - - F_Out = F_In; - case (ALU_Op) - 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 : - begin - F_Out[Flag_N] = 1'b0; - F_Out[Flag_C] = 1'b0; - - case (ALU_Op[2:0]) - - 3'b000, 3'b001 : // ADD, ADC - begin - Q_t = Q_v; - F_Out[Flag_C] = Carry_v; - F_Out[Flag_H] = HalfCarry_v; - F_Out[Flag_P] = OverFlow_v; - end - - 3'b010, 3'b011, 3'b111 : // SUB, SBC, CP - begin - Q_t = Q_v; - F_Out[Flag_N] = 1'b1; - F_Out[Flag_C] = ~ Carry_v; - F_Out[Flag_H] = ~ HalfCarry_v; - F_Out[Flag_P] = OverFlow_v; - end - - 3'b100 : // AND - begin - Q_t[7:0] = BusA & BusB; - F_Out[Flag_H] = 1'b1; - end - - 3'b101 : // XOR - begin - Q_t[7:0] = BusA ^ BusB; - F_Out[Flag_H] = 1'b0; - end - - default : // OR 3'b110 - begin - Q_t[7:0] = BusA | BusB; - F_Out[Flag_H] = 1'b0; - end - - endcase // case(ALU_OP[2:0]) - - if (ALU_Op[2:0] == 3'b111 ) - begin // CP - F_Out[Flag_X] = BusB[3]; - F_Out[Flag_Y] = BusB[5]; - end - else - begin - F_Out[Flag_X] = Q_t[3]; - F_Out[Flag_Y] = Q_t[5]; - end - - if (Q_t[7:0] == 8'b00000000 ) - begin - F_Out[Flag_Z] = 1'b1; - if (Z16 == 1'b1 ) - begin - F_Out[Flag_Z] = F_In[Flag_Z]; // 16 bit ADC,SBC - end - end - else - begin - F_Out[Flag_Z] = 1'b0; - end // else: !if(Q_t[7:0] == 8'b00000000 ) - - F_Out[Flag_S] = Q_t[7]; - case (ALU_Op[2:0]) - 3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP - ; - - default : - F_Out[Flag_P] = ~(^Q_t); - endcase // case(ALU_Op[2:0]) - - if (Arith16 == 1'b1 ) - begin - F_Out[Flag_S] = F_In[Flag_S]; - F_Out[Flag_Z] = F_In[Flag_Z]; - F_Out[Flag_P] = F_In[Flag_P]; - end - end // case: 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 - - 4'b1100 : - begin - // DAA - F_Out[Flag_H] = F_In[Flag_H]; - F_Out[Flag_C] = F_In[Flag_C]; - DAA_Q[7:0] = BusA; - DAA_Q[8] = 1'b0; - if (F_In[Flag_N] == 1'b0 ) - begin - // After addition - // Alow > 9 || H == 1 - if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) - begin - if ((DAA_Q[3:0] > 9) ) - begin - F_Out[Flag_H] = 1'b1; - end - else - begin - F_Out[Flag_H] = 1'b0; - end - DAA_Q = DAA_Q + 6; - end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) - - // new Ahigh > 9 || C == 1 - if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 ) - begin - DAA_Q = DAA_Q + 96; // 0x60 - end - end - else - begin - // After subtraction - if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) - begin - if (DAA_Q[3:0] > 5 ) - begin - F_Out[Flag_H] = 1'b0; - end - DAA_Q[7:0] = DAA_Q[7:0] - 6; - end - if (BusA > 153 || F_In[Flag_C] == 1'b1 ) - begin - DAA_Q = DAA_Q - 352; // 0x160 - end - end // else: !if(F_In[Flag_N] == 1'b0 ) - - F_Out[Flag_X] = DAA_Q[3]; - F_Out[Flag_Y] = DAA_Q[5]; - F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8]; - Q_t = DAA_Q[7:0]; - - if (DAA_Q[7:0] == 8'b00000000 ) - begin - F_Out[Flag_Z] = 1'b1; - end - else - begin - F_Out[Flag_Z] = 1'b0; - end - - F_Out[Flag_S] = DAA_Q[7]; - F_Out[Flag_P] = ~ (^DAA_Q); - end // case: 4'b1100 - - 4'b1101, 4'b1110 : - begin - // RLD, RRD - Q_t[7:4] = BusA[7:4]; - if (ALU_Op[0] == 1'b1 ) - begin - Q_t[3:0] = BusB[7:4]; - end - else - begin - Q_t[3:0] = BusB[3:0]; - end - F_Out[Flag_H] = 1'b0; - F_Out[Flag_N] = 1'b0; - F_Out[Flag_X] = Q_t[3]; - F_Out[Flag_Y] = Q_t[5]; - if (Q_t[7:0] == 8'b00000000 ) - begin - F_Out[Flag_Z] = 1'b1; - end - else - begin - F_Out[Flag_Z] = 1'b0; - end - F_Out[Flag_S] = Q_t[7]; - F_Out[Flag_P] = ~(^Q_t); - end // case: when 4'b1101, 4'b1110 - - 4'b1001 : - begin - // BIT - Q_t[7:0] = BusB & BitMask; - F_Out[Flag_S] = Q_t[7]; - if (Q_t[7:0] == 8'b00000000 ) - begin - F_Out[Flag_Z] = 1'b1; - F_Out[Flag_P] = 1'b1; - end - else - begin - F_Out[Flag_Z] = 1'b0; - F_Out[Flag_P] = 1'b0; - end - F_Out[Flag_H] = 1'b1; - F_Out[Flag_N] = 1'b0; - F_Out[Flag_X] = 1'b0; - F_Out[Flag_Y] = 1'b0; - if (IR[2:0] != 3'b110 ) - begin - F_Out[Flag_X] = BusB[3]; - F_Out[Flag_Y] = BusB[5]; - end - end // case: when 4'b1001 - - 4'b1010 : - // SET - Q_t[7:0] = BusB | BitMask; - - 4'b1011 : - // RES - Q_t[7:0] = BusB & ~ BitMask; - - 4'b1000 : - begin - // ROT - case (IR[5:3]) - 3'b000 : // RLC - begin - Q_t[7:1] = BusA[6:0]; - Q_t[0] = BusA[7]; - F_Out[Flag_C] = BusA[7]; - end - - 3'b010 : // RL - begin - Q_t[7:1] = BusA[6:0]; - Q_t[0] = F_In[Flag_C]; - F_Out[Flag_C] = BusA[7]; - end - - 3'b001 : // RRC - begin - Q_t[6:0] = BusA[7:1]; - Q_t[7] = BusA[0]; - F_Out[Flag_C] = BusA[0]; - end - - 3'b011 : // RR - begin - Q_t[6:0] = BusA[7:1]; - Q_t[7] = F_In[Flag_C]; - F_Out[Flag_C] = BusA[0]; - end - - 3'b100 : // SLA - begin - Q_t[7:1] = BusA[6:0]; - Q_t[0] = 1'b0; - F_Out[Flag_C] = BusA[7]; - end - - 3'b110 : // SLL (Undocumented) / SWAP - begin - if (Mode == 3 ) - begin - Q_t[7:4] = BusA[3:0]; - Q_t[3:0] = BusA[7:4]; - F_Out[Flag_C] = 1'b0; - end - else - begin - Q_t[7:1] = BusA[6:0]; - Q_t[0] = 1'b1; - F_Out[Flag_C] = BusA[7]; - end // else: !if(Mode == 3 ) - end // case: 3'b110 - - 3'b101 : // SRA - begin - Q_t[6:0] = BusA[7:1]; - Q_t[7] = BusA[7]; - F_Out[Flag_C] = BusA[0]; - end - - default : // SRL - begin - Q_t[6:0] = BusA[7:1]; - Q_t[7] = 1'b0; - F_Out[Flag_C] = BusA[0]; - end - endcase // case(IR[5:3]) - - F_Out[Flag_H] = 1'b0; - F_Out[Flag_N] = 1'b0; - F_Out[Flag_X] = Q_t[3]; - F_Out[Flag_Y] = Q_t[5]; - F_Out[Flag_S] = Q_t[7]; - if (Q_t[7:0] == 8'b00000000 ) - begin - F_Out[Flag_Z] = 1'b1; - end - else - begin - F_Out[Flag_Z] = 1'b0; - end - F_Out[Flag_P] = ~(^Q_t); - - if (ISet == 2'b00 ) - begin - F_Out[Flag_P] = F_In[Flag_P]; - F_Out[Flag_S] = F_In[Flag_S]; - F_Out[Flag_Z] = F_In[Flag_Z]; - end - end // case: 4'b1000 - - - default : - ; - - endcase // case(ALU_Op) - - Q = Q_t; - end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - -endmodule // T80_ALU diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/tv80/tv80_core.v b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/tv80/tv80_core.v deleted file mode 100644 index 197e983d..00000000 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/tv80/tv80_core.v +++ /dev/null @@ -1,1391 +0,0 @@ -`timescale 1ns/1ns - -// -// TV80 8-Bit Microprocessor Core -// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) -// -// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a -// copy of this software and associated documentation files (the "Software"), -// to deal in the Software without restriction, including without limitation -// the rights to use, copy, modify, merge, publish, distribute, sublicense, -// and/or sell copies of the Software, and to permit persons to whom the -// Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included -// in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -module tv80_core (/*AUTOARG*/ - // Outputs - m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, dout, mc, - ts, intcycle_n, IntE, stop, - // Inputs - reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di - ); - // Beginning of automatic inputs (from unused autoinst inputs) - // End of automatics - - parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle - parameter Flag_C = 0; - parameter Flag_N = 1; - parameter Flag_P = 2; - parameter Flag_X = 3; - parameter Flag_H = 4; - parameter Flag_Y = 5; - parameter Flag_Z = 6; - parameter Flag_S = 7; - - input reset_n; - input clk; - input cen; - input wait_n; - input int_n; - input nmi_n; - input busrq_n; - output m1_n; - output iorq; - output no_read; - output write; - output rfsh_n; - output halt_n; - output busak_n; - output [15:0] A; - input [7:0] dinst; - input [7:0] di; - output [7:0] dout; - output [6:0] mc; - output [6:0] ts; - output intcycle_n; - output IntE; - output stop; - - reg m1_n; - reg iorq; -`ifdef TV80_REFRESH - reg rfsh_n; -`endif - reg halt_n; - reg busak_n; - reg [15:0] A; - reg [7:0] dout; - reg [6:0] mc; - reg [6:0] ts; - reg intcycle_n; - reg IntE; - reg stop; - - parameter aNone = 3'b111; - parameter aBC = 3'b000; - parameter aDE = 3'b001; - parameter aXY = 3'b010; - parameter aIOA = 3'b100; - parameter aSP = 3'b101; - parameter aZI = 3'b110; - - // Registers - reg [7:0] ACC, F; - reg [7:0] Ap, Fp; - reg [7:0] I; -`ifdef TV80_REFRESH - reg [7:0] R; -`endif - reg [15:0] SP, PC; - reg [7:0] RegDIH; - reg [7:0] RegDIL; - wire [15:0] RegBusA; - wire [15:0] RegBusB; - wire [15:0] RegBusC; - reg [2:0] RegAddrA_r; - reg [2:0] RegAddrA; - reg [2:0] RegAddrB_r; - reg [2:0] RegAddrB; - reg [2:0] RegAddrC; - reg RegWEH; - reg RegWEL; - reg Alternate; - - // Help Registers - reg [15:0] TmpAddr; // Temporary address register - reg [7:0] IR; // Instruction register - reg [1:0] ISet; // Instruction set selector - reg [15:0] RegBusA_r; - - reg [15:0] ID16; - reg [7:0] Save_Mux; - - reg [6:0] tstate; - reg [6:0] mcycle; - reg last_mcycle, last_tstate; - reg IntE_FF1; - reg IntE_FF2; - reg Halt_FF; - reg BusReq_s; - reg BusAck; - reg ClkEn; - reg NMI_s; - reg INT_s; - reg [1:0] IStatus; - - reg [7:0] DI_Reg; - reg T_Res; - reg [1:0] XY_State; - reg [2:0] Pre_XY_F_M; - reg NextIs_XY_Fetch; - reg XY_Ind; - reg No_BTR; - reg BTR_r; - reg Auto_Wait; - reg Auto_Wait_t1; - reg Auto_Wait_t2; - reg IncDecZ; - - // ALU signals - reg [7:0] BusB; - reg [7:0] BusA; - wire [7:0] ALU_Q; - wire [7:0] F_Out; - - // Registered micro code outputs - reg [4:0] Read_To_Reg_r; - reg Arith16_r; - reg Z16_r; - reg [3:0] ALU_Op_r; - reg Save_ALU_r; - reg PreserveC_r; - reg [2:0] mcycles; - - // Micro code outputs - wire [2:0] mcycles_d; - wire [2:0] tstates; - reg IntCycle; - reg NMICycle; - wire Inc_PC; - wire Inc_WZ; - wire [3:0] IncDec_16; - wire [1:0] Prefix; - wire Read_To_Acc; - wire Read_To_Reg; - wire [3:0] Set_BusB_To; - wire [3:0] Set_BusA_To; - wire [3:0] ALU_Op; - wire Save_ALU; - wire PreserveC; - wire Arith16; - wire [2:0] Set_Addr_To; - wire Jump; - wire JumpE; - wire JumpXY; - wire Call; - wire RstP; - wire LDZ; - wire LDW; - wire LDSPHL; - wire iorq_i; - wire [2:0] Special_LD; - wire ExchangeDH; - wire ExchangeRp; - wire ExchangeAF; - wire ExchangeRS; - wire I_DJNZ; - wire I_CPL; - wire I_CCF; - wire I_SCF; - wire I_RETN; - wire I_BT; - wire I_BC; - wire I_BTR; - wire I_RLD; - wire I_RRD; - wire I_INRC; - wire SetDI; - wire SetEI; - wire [1:0] IMode; - wire Halt; - - reg [15:0] PC16; - reg [15:0] PC16_B; - reg [15:0] SP16, SP16_A, SP16_B; - reg [15:0] ID16_B; - reg Oldnmi_n; - - tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode - ( - .IR (IR), - .ISet (ISet), - .MCycle (mcycle), - .F (F), - .NMICycle (NMICycle), - .IntCycle (IntCycle), - .MCycles (mcycles_d), - .TStates (tstates), - .Prefix (Prefix), - .Inc_PC (Inc_PC), - .Inc_WZ (Inc_WZ), - .IncDec_16 (IncDec_16), - .Read_To_Acc (Read_To_Acc), - .Read_To_Reg (Read_To_Reg), - .Set_BusB_To (Set_BusB_To), - .Set_BusA_To (Set_BusA_To), - .ALU_Op (ALU_Op), - .Save_ALU (Save_ALU), - .PreserveC (PreserveC), - .Arith16 (Arith16), - .Set_Addr_To (Set_Addr_To), - .IORQ (iorq_i), - .Jump (Jump), - .JumpE (JumpE), - .JumpXY (JumpXY), - .Call (Call), - .RstP (RstP), - .LDZ (LDZ), - .LDW (LDW), - .LDSPHL (LDSPHL), - .Special_LD (Special_LD), - .ExchangeDH (ExchangeDH), - .ExchangeRp (ExchangeRp), - .ExchangeAF (ExchangeAF), - .ExchangeRS (ExchangeRS), - .I_DJNZ (I_DJNZ), - .I_CPL (I_CPL), - .I_CCF (I_CCF), - .I_SCF (I_SCF), - .I_RETN (I_RETN), - .I_BT (I_BT), - .I_BC (I_BC), - .I_BTR (I_BTR), - .I_RLD (I_RLD), - .I_RRD (I_RRD), - .I_INRC (I_INRC), - .SetDI (SetDI), - .SetEI (SetEI), - .IMode (IMode), - .Halt (Halt), - .NoRead (no_read), - .Write (write) - ); - - tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu - ( - .Arith16 (Arith16_r), - .Z16 (Z16_r), - .ALU_Op (ALU_Op_r), - .IR (IR[5:0]), - .ISet (ISet), - .BusA (BusA), - .BusB (BusB), - .F_In (F), - .Q (ALU_Q), - .F_Out (F_Out) - ); - - function [6:0] number_to_bitvec; - input [2:0] num; - begin - casex (num) - 1 : number_to_bitvec = 7'b0000001; - 2 : number_to_bitvec = 7'b0000010; - 3 : number_to_bitvec = 7'b0000100; - 4 : number_to_bitvec = 7'b0001000; - 5 : number_to_bitvec = 7'b0010000; - 6 : number_to_bitvec = 7'b0100000; - 7 : number_to_bitvec = 7'b1000000; - default : number_to_bitvec = 7'bx; - endcase // case(num) - end - endfunction // number_to_bitvec - - function [2:0] mcyc_to_number; - input [6:0] mcyc; - begin - casez (mcyc) - 7'b1zzzzzz : mcyc_to_number = 3'h7; - 7'b01zzzzz : mcyc_to_number = 3'h6; - 7'b001zzzz : mcyc_to_number = 3'h5; - 7'b0001zzz : mcyc_to_number = 3'h4; - 7'b00001zz : mcyc_to_number = 3'h3; - 7'b000001z : mcyc_to_number = 3'h2; - 7'b0000001 : mcyc_to_number = 3'h1; - default : mcyc_to_number = 3'h1; - endcase - end - endfunction - - always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates) - begin - case (mcycles) - 1 : last_mcycle = mcycle[0]; - 2 : last_mcycle = mcycle[1]; - 3 : last_mcycle = mcycle[2]; - 4 : last_mcycle = mcycle[3]; - 5 : last_mcycle = mcycle[4]; - 6 : last_mcycle = mcycle[5]; - 7 : last_mcycle = mcycle[6]; - default : last_mcycle = 1'bx; - endcase // case(mcycles) - - case (tstates) - 0 : last_tstate = tstate[0]; - 1 : last_tstate = tstate[1]; - 2 : last_tstate = tstate[2]; - 3 : last_tstate = tstate[3]; - 4 : last_tstate = tstate[4]; - 5 : last_tstate = tstate[5]; - 6 : last_tstate = tstate[6]; - default : last_tstate = 1'bx; - endcase - end // always @ (... - - - always @(/*AUTOSENSE*/ALU_Q or BusAck or BusB or DI_Reg - or ExchangeRp or IR or Save_ALU_r or Set_Addr_To or XY_Ind - or XY_State or cen or last_tstate or mcycle) - begin - ClkEn = cen && ~ BusAck; - - if (last_tstate) - T_Res = 1'b1; - else T_Res = 1'b0; - - if (XY_State != 2'b00 && XY_Ind == 1'b0 && - ((Set_Addr_To == aXY) || - (mcycle[0] && IR == 8'b11001011) || - (mcycle[0] && IR == 8'b00110110))) - NextIs_XY_Fetch = 1'b1; - else - NextIs_XY_Fetch = 1'b0; - - if (ExchangeRp) - Save_Mux = BusB; - else if (!Save_ALU_r) - Save_Mux = DI_Reg; - else - Save_Mux = ALU_Q; - end // always @ * - - always @ (posedge clk or negedge reset_n) - begin - if (reset_n == 1'b0 ) - begin - PC <= #1 0; // Program Counter - A <= #1 0; - TmpAddr <= #1 0; - IR <= #1 8'b00000000; - ISet <= #1 2'b00; - XY_State <= #1 2'b00; - IStatus <= #1 2'b00; - mcycles <= #1 3'b000; - dout <= #1 8'b00000000; - - ACC <= #1 8'hFF; - F <= #1 8'hFF; - Ap <= #1 8'hFF; - Fp <= #1 8'hFF; - I <= #1 0; - `ifdef TV80_REFRESH - R <= #1 0; - `endif - SP <= #1 16'hFFFF; - Alternate <= #1 1'b0; - - Read_To_Reg_r <= #1 5'b00000; - Arith16_r <= #1 1'b0; - BTR_r <= #1 1'b0; - Z16_r <= #1 1'b0; - ALU_Op_r <= #1 4'b0000; - Save_ALU_r <= #1 1'b0; - PreserveC_r <= #1 1'b0; - XY_Ind <= #1 1'b0; - end - else - begin - - if (ClkEn == 1'b1 ) - begin - - ALU_Op_r <= #1 4'b0000; - Save_ALU_r <= #1 1'b0; - Read_To_Reg_r <= #1 5'b00000; - - mcycles <= #1 mcycles_d; - - if (IMode != 2'b11 ) - begin - IStatus <= #1 IMode; - end - - Arith16_r <= #1 Arith16; - PreserveC_r <= #1 PreserveC; - if (ISet == 2'b10 && ALU_Op[2] == 1'b0 && ALU_Op[0] == 1'b1 && mcycle[2] ) - begin - Z16_r <= #1 1'b1; - end - else - begin - Z16_r <= #1 1'b0; - end - - if (mcycle[0] && (tstate[1] | tstate[2] | tstate[3] )) - begin - // mcycle == 1 && tstate == 1, 2, || 3 - if (tstate[2] && wait_n == 1'b1 ) - begin - `ifdef TV80_REFRESH - if (Mode < 2 ) - begin - A[7:0] <= #1 R; - A[15:8] <= #1 I; - R[6:0] <= #1 R[6:0] + 1; - end - `endif - if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 || Halt == 1'b1) ) - begin - PC <= #1 PC16; - end - - if (IntCycle == 1'b1 && IStatus == 2'b01 ) - begin - IR <= #1 8'b11111111; - end - else if (Halt_FF == 1'b1 || (IntCycle == 1'b1 && IStatus == 2'b10) || NMICycle == 1'b1 ) - begin - IR <= #1 8'b00000000; - TmpAddr[7:0] <= #1 dinst; // Special M1 vector fetch - end - else - begin - IR <= #1 dinst; - end - - ISet <= #1 2'b00; - if (Prefix != 2'b00 ) - begin - if (Prefix == 2'b11 ) - begin - if (IR[5] == 1'b1 ) - begin - XY_State <= #1 2'b10; - end - else - begin - XY_State <= #1 2'b01; - end - end - else - begin - if (Prefix == 2'b10 ) - begin - XY_State <= #1 2'b00; - XY_Ind <= #1 1'b0; - end - ISet <= #1 Prefix; - end - end - else - begin - XY_State <= #1 2'b00; - XY_Ind <= #1 1'b0; - end - end // if (tstate == 2 && wait_n == 1'b1 ) - - - end - else - begin - // either (mcycle > 1) OR (mcycle == 1 AND tstate > 3) - - if (mcycle[5] ) - begin - XY_Ind <= #1 1'b1; - if (Prefix == 2'b01 ) - begin - ISet <= #1 2'b01; - end - end - - if (T_Res == 1'b1 ) - begin - BTR_r <= #1 (I_BT || I_BC || I_BTR) && ~ No_BTR; - if (Jump == 1'b1 ) - begin - A[15:8] <= #1 DI_Reg; - A[7:0] <= #1 TmpAddr[7:0]; - PC[15:8] <= #1 DI_Reg; - PC[7:0] <= #1 TmpAddr[7:0]; - end - else if (JumpXY == 1'b1 ) - begin - A <= #1 RegBusC; - PC <= #1 RegBusC; - end else if (Call == 1'b1 || RstP == 1'b1 ) - begin - A <= #1 TmpAddr; - PC <= #1 TmpAddr; - end - else if (last_mcycle && NMICycle == 1'b1 ) - begin - A <= #1 16'b0000000001100110; - PC <= #1 16'b0000000001100110; - end - else if (mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 ) - begin - A[15:8] <= #1 I; - A[7:0] <= #1 TmpAddr[7:0]; - PC[15:8] <= #1 I; - PC[7:0] <= #1 TmpAddr[7:0]; - end - else - begin - case (Set_Addr_To) - aXY : - begin - if (XY_State == 2'b00 ) - begin - A <= #1 RegBusC; - end - else - begin - if (NextIs_XY_Fetch == 1'b1 ) - begin - A <= #1 PC; - end - else - begin - A <= #1 TmpAddr; - end - end // else: !if(XY_State == 2'b00 ) - end // case: aXY - - aIOA : - begin - if (Mode == 3 ) - begin - // Memory map I/O on GBZ80 - A[15:8] <= #1 8'hFF; - end - else if (Mode == 2 ) - begin - // Duplicate I/O address on 8080 - A[15:8] <= #1 DI_Reg; - end - else - begin - A[15:8] <= #1 ACC; - end - A[7:0] <= #1 DI_Reg; - end // case: aIOA - - - aSP : - begin - A <= #1 SP; - end - - aBC : - begin - if (Mode == 3 && iorq_i == 1'b1 ) - begin - // Memory map I/O on GBZ80 - A[15:8] <= #1 8'hFF; - A[7:0] <= #1 RegBusC[7:0]; - end - else - begin - A <= #1 RegBusC; - end - end // case: aBC - - aDE : - begin - A <= #1 RegBusC; - end - - aZI : - begin - if (Inc_WZ == 1'b1 ) - begin - A <= #1 TmpAddr + 1; - end - else - begin - A[15:8] <= #1 DI_Reg; - A[7:0] <= #1 TmpAddr[7:0]; - end - end // case: aZI - - default : - begin - A <= #1 PC; - end - endcase // case(Set_Addr_To) - - end // else: !if(mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 ) - - - Save_ALU_r <= #1 Save_ALU; - ALU_Op_r <= #1 ALU_Op; - - if (I_CPL == 1'b1 ) - begin - // CPL - ACC <= #1 ~ ACC; - F[Flag_Y] <= #1 ~ ACC[5]; - F[Flag_H] <= #1 1'b1; - F[Flag_X] <= #1 ~ ACC[3]; - F[Flag_N] <= #1 1'b1; - end - if (I_CCF == 1'b1 ) - begin - // CCF - F[Flag_C] <= #1 ~ F[Flag_C]; - F[Flag_Y] <= #1 ACC[5]; - F[Flag_H] <= #1 F[Flag_C]; - F[Flag_X] <= #1 ACC[3]; - F[Flag_N] <= #1 1'b0; - end - if (I_SCF == 1'b1 ) - begin - // SCF - F[Flag_C] <= #1 1'b1; - F[Flag_Y] <= #1 ACC[5]; - F[Flag_H] <= #1 1'b0; - F[Flag_X] <= #1 ACC[3]; - F[Flag_N] <= #1 1'b0; - end - end // if (T_Res == 1'b1 ) - - - if (tstate[2] && wait_n == 1'b1 ) - begin - if (ISet == 2'b01 && mcycle[6] ) - begin - IR <= #1 dinst; - end - if (JumpE == 1'b1 ) - begin - PC <= #1 PC16; - end - else if (Inc_PC == 1'b1 ) - begin - //PC <= #1 PC + 1; - PC <= #1 PC16; - end - if (BTR_r == 1'b1 ) - begin - //PC <= #1 PC - 2; - PC <= #1 PC16; - end - if (RstP == 1'b1 ) - begin - TmpAddr <= #1 { 10'h0, IR[5:3], 3'h0 }; - //TmpAddr <= #1 (others =>1'b0); - //TmpAddr[5:3] <= #1 IR[5:3]; - end - end - if (tstate[3] && mcycle[5] ) - begin - TmpAddr <= #1 SP16; - end - - if ((tstate[2] && wait_n == 1'b1) || (tstate[4] && mcycle[0]) ) - begin - if (IncDec_16[2:0] == 3'b111 ) - begin - SP <= #1 SP16; - end - end - - if (LDSPHL == 1'b1 ) - begin - SP <= #1 RegBusC; - end - if (ExchangeAF == 1'b1 ) - begin - Ap <= #1 ACC; - ACC <= #1 Ap; - Fp <= #1 F; - F <= #1 Fp; - end - if (ExchangeRS == 1'b1 ) - begin - Alternate <= #1 ~ Alternate; - end - end // else: !if(mcycle == 3'b001 && tstate(2) == 1'b0 ) - - - if (tstate[3] ) - begin - if (LDZ == 1'b1 ) - begin - TmpAddr[7:0] <= #1 DI_Reg; - end - if (LDW == 1'b1 ) - begin - TmpAddr[15:8] <= #1 DI_Reg; - end - - if (Special_LD[2] == 1'b1 ) - begin - case (Special_LD[1:0]) - 2'b00 : - begin - ACC <= #1 I; - F[Flag_P] <= #1 IntE_FF2; - F[Flag_Z] <= (I == 0); - F[Flag_S] <= I[7]; - F[Flag_H] <= 0; - F[Flag_N] <= 0; - end - - 2'b01 : - begin - `ifdef TV80_REFRESH - ACC <= #1 R; - `else - ACC <= #1 0; - `endif - F[Flag_P] <= #1 IntE_FF2; - F[Flag_Z] <= (I == 0); - F[Flag_S] <= I[7]; - F[Flag_H] <= 0; - F[Flag_N] <= 0; - end - - 2'b10 : - I <= #1 ACC; - - `ifdef TV80_REFRESH - default : - R <= #1 ACC; - `else - default : ; - `endif - endcase - end - end // if (tstate == 3 ) - - - if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 ) - begin - if (Mode == 3 ) - begin - F[6] <= #1 F_Out[6]; - F[5] <= #1 F_Out[5]; - F[7] <= #1 F_Out[7]; - if (PreserveC_r == 1'b0 ) - begin - F[4] <= #1 F_Out[4]; - end - end - else - begin - F[7:1] <= #1 F_Out[7:1]; - if (PreserveC_r == 1'b0 ) - begin - F[Flag_C] <= #1 F_Out[0]; - end - end - end // if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 ) - - if (T_Res == 1'b1 && I_INRC == 1'b1 ) - begin - F[Flag_H] <= #1 1'b0; - F[Flag_N] <= #1 1'b0; - if (DI_Reg[7:0] == 8'b00000000 ) - begin - F[Flag_Z] <= #1 1'b1; - end - else - begin - F[Flag_Z] <= #1 1'b0; - end - F[Flag_S] <= #1 DI_Reg[7]; - F[Flag_P] <= #1 ~ (^DI_Reg[7:0]); - end // if (T_Res == 1'b1 && I_INRC == 1'b1 ) - - - if (tstate[1] && Auto_Wait_t1 == 1'b0 ) - begin - dout <= #1 BusB; - if (I_RLD == 1'b1 ) - begin - dout[3:0] <= #1 BusA[3:0]; - dout[7:4] <= #1 BusB[3:0]; - end - if (I_RRD == 1'b1 ) - begin - dout[3:0] <= #1 BusB[7:4]; - dout[7:4] <= #1 BusA[3:0]; - end - end - - if (T_Res == 1'b1 ) - begin - Read_To_Reg_r[3:0] <= #1 Set_BusA_To; - Read_To_Reg_r[4] <= #1 Read_To_Reg; - if (Read_To_Acc == 1'b1 ) - begin - Read_To_Reg_r[3:0] <= #1 4'b0111; - Read_To_Reg_r[4] <= #1 1'b1; - end - end - - if (tstate[1] && I_BT == 1'b1 ) - begin - F[Flag_X] <= #1 ALU_Q[3]; - F[Flag_Y] <= #1 ALU_Q[1]; - F[Flag_H] <= #1 1'b0; - F[Flag_N] <= #1 1'b0; - end - if (I_BC == 1'b1 || I_BT == 1'b1 ) - begin - F[Flag_P] <= #1 IncDecZ; - end - - if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) || - (Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) ) - begin - case (Read_To_Reg_r) - 5'b10111 : - ACC <= #1 Save_Mux; - 5'b10110 : - dout <= #1 Save_Mux; - 5'b11000 : - SP[7:0] <= #1 Save_Mux; - 5'b11001 : - SP[15:8] <= #1 Save_Mux; - 5'b11011 : - F <= #1 Save_Mux; - default : ; - endcase - end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||... - end // if (ClkEn == 1'b1 ) - end // else: !if(reset_n == 1'b0 ) - end - - - //------------------------------------------------------------------------- - // - // BC('), DE('), HL('), IX && IY - // - //------------------------------------------------------------------------- - always @ (posedge clk) - begin - if (ClkEn == 1'b1 ) - begin - // Bus A / Write - RegAddrA_r <= #1 { Alternate, Set_BusA_To[2:1] }; - if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusA_To[2:1] == 2'b10 ) - begin - RegAddrA_r <= #1 { XY_State[1], 2'b11 }; - end - - // Bus B - RegAddrB_r <= #1 { Alternate, Set_BusB_To[2:1] }; - if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusB_To[2:1] == 2'b10 ) - begin - RegAddrB_r <= #1 { XY_State[1], 2'b11 }; - end - - // Address from register - RegAddrC <= #1 { Alternate, Set_Addr_To[1:0] }; - // Jump (HL), LD SP,HL - if ((JumpXY == 1'b1 || LDSPHL == 1'b1) ) - begin - RegAddrC <= #1 { Alternate, 2'b10 }; - end - if (((JumpXY == 1'b1 || LDSPHL == 1'b1) && XY_State != 2'b00) || (mcycle[5]) ) - begin - RegAddrC <= #1 { XY_State[1], 2'b11 }; - end - - if (I_DJNZ == 1'b1 && Save_ALU_r == 1'b1 && Mode < 2 ) - begin - IncDecZ <= #1 F_Out[Flag_Z]; - end - if ((tstate[2] || (tstate[3] && mcycle[0])) && IncDec_16[2:0] == 3'b100 ) - begin - if (ID16 == 0 ) - begin - IncDecZ <= #1 1'b0; - end - else - begin - IncDecZ <= #1 1'b1; - end - end - - RegBusA_r <= #1 RegBusA; - end - - end // always @ (posedge clk) - - - always @(/*AUTOSENSE*/Alternate or ExchangeDH or IncDec_16 - or RegAddrA_r or RegAddrB_r or XY_State or mcycle or tstate) - begin - if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && XY_State == 2'b00) - RegAddrA = { Alternate, IncDec_16[1:0] }; - else if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && IncDec_16[1:0] == 2'b10) - RegAddrA = { XY_State[1], 2'b11 }; - else if (ExchangeDH == 1'b1 && tstate[3]) - RegAddrA = { Alternate, 2'b10 }; - else if (ExchangeDH == 1'b1 && tstate[4]) - RegAddrA = { Alternate, 2'b01 }; - else - RegAddrA = RegAddrA_r; - - if (ExchangeDH == 1'b1 && tstate[3]) - RegAddrB = { Alternate, 2'b01 }; - else - RegAddrB = RegAddrB_r; - end // always @ * - - - always @(/*AUTOSENSE*/ALU_Op_r or Auto_Wait_t1 or ExchangeDH - or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle - or tstate or wait_n) - begin - RegWEH = 1'b0; - RegWEL = 1'b0; - if ((tstate[1] && ~Save_ALU_r && ~Auto_Wait_t1) || - (Save_ALU_r && (ALU_Op_r != 4'b0111)) ) - begin - case (Read_To_Reg_r) - 5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 : - begin - RegWEH = ~ Read_To_Reg_r[0]; - RegWEL = Read_To_Reg_r[0]; - end // UNMATCHED !! - default : ; - endcase // case(Read_To_Reg_r) - - end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||... - - - if (ExchangeDH && (tstate[3] || tstate[4]) ) - begin - RegWEH = 1'b1; - RegWEL = 1'b1; - end - - if (IncDec_16[2] && ((tstate[2] && wait_n && ~mcycle[0]) || (tstate[3] && mcycle[0])) ) - begin - case (IncDec_16[1:0]) - 2'b00 , 2'b01 , 2'b10 : - begin - RegWEH = 1'b1; - RegWEL = 1'b1; - end // UNMATCHED !! - default : ; - endcase - end - end // always @ * - - - always @(/*AUTOSENSE*/ExchangeDH or ID16 or IncDec_16 or RegBusA_r - or RegBusB or Save_Mux or mcycle or tstate) - begin - RegDIH = Save_Mux; - RegDIL = Save_Mux; - - if (ExchangeDH == 1'b1 && tstate[3] ) - begin - RegDIH = RegBusB[15:8]; - RegDIL = RegBusB[7:0]; - end - else if (ExchangeDH == 1'b1 && tstate[4] ) - begin - RegDIH = RegBusA_r[15:8]; - RegDIL = RegBusA_r[7:0]; - end - else if (IncDec_16[2] == 1'b1 && ((tstate[2] && ~mcycle[0]) || (tstate[3] && mcycle[0])) ) - begin - RegDIH = ID16[15:8]; - RegDIL = ID16[7:0]; - end - end - - tv80_reg i_reg - ( - .clk (clk), - .CEN (ClkEn), - .WEH (RegWEH), - .WEL (RegWEL), - .AddrA (RegAddrA), - .AddrB (RegAddrB), - .AddrC (RegAddrC), - .DIH (RegDIH), - .DIL (RegDIL), - .DOAH (RegBusA[15:8]), - .DOAL (RegBusA[7:0]), - .DOBH (RegBusB[15:8]), - .DOBL (RegBusB[7:0]), - .DOCH (RegBusC[15:8]), - .DOCL (RegBusC[7:0]) - ); - - //------------------------------------------------------------------------- - // - // Buses - // - //------------------------------------------------------------------------- - - always @ (posedge clk) - begin - if (ClkEn == 1'b1 ) - begin - case (Set_BusB_To) - 4'b0111 : - BusB <= #1 ACC; - 4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 : - begin - if (Set_BusB_To[0] == 1'b1 ) - begin - BusB <= #1 RegBusB[7:0]; - end - else - begin - BusB <= #1 RegBusB[15:8]; - end - end - 4'b0110 : - BusB <= #1 DI_Reg; - 4'b1000 : - BusB <= #1 SP[7:0]; - 4'b1001 : - BusB <= #1 SP[15:8]; - 4'b1010 : - BusB <= #1 8'b00000001; - 4'b1011 : - BusB <= #1 F; - 4'b1100 : - BusB <= #1 PC[7:0]; - 4'b1101 : - BusB <= #1 PC[15:8]; - 4'b1110 : - BusB <= #1 8'b00000000; - default : - BusB <= #1 8'h0; - endcase - - case (Set_BusA_To) - 4'b0111 : - BusA <= #1 ACC; - 4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 : - begin - if (Set_BusA_To[0] == 1'b1 ) - begin - BusA <= #1 RegBusA[7:0]; - end - else - begin - BusA <= #1 RegBusA[15:8]; - end - end - 4'b0110 : - BusA <= #1 DI_Reg; - 4'b1000 : - BusA <= #1 SP[7:0]; - 4'b1001 : - BusA <= #1 SP[15:8]; - 4'b1010 : - BusA <= #1 8'b00000000; - default : - BusA <= #1 8'h0; - endcase - end - end - - //------------------------------------------------------------------------- - // - // Generate external control signals - // - //------------------------------------------------------------------------- -`ifdef TV80_REFRESH - always @ (posedge clk or negedge reset_n) - begin - if (reset_n == 1'b0 ) - begin - rfsh_n <= #1 1'b1; - end - else - begin - if (cen == 1'b1 ) - begin - if (mcycle[0] && ((tstate[2] && wait_n == 1'b1) || tstate[3]) ) - begin - rfsh_n <= #1 1'b0; - end - else - begin - rfsh_n <= #1 1'b1; - end - end - end - end // always @ (posedge clk or negedge reset_n) -`else // !`ifdef TV80_REFRESH - assign rfsh_n = 1'b1; -`endif - - always @(/*AUTOSENSE*/BusAck or Halt_FF or I_DJNZ or IntCycle - or IntE_FF1 or di or iorq_i or mcycle or tstate) - begin - mc = mcycle; - ts = tstate; - DI_Reg = di; - halt_n = ~ Halt_FF; - busak_n = ~ BusAck; - intcycle_n = ~ IntCycle; - IntE = IntE_FF1; - iorq = iorq_i; - stop = I_DJNZ; - end - - //----------------------------------------------------------------------- - // - // Syncronise inputs - // - //----------------------------------------------------------------------- - - always @ (posedge clk or negedge reset_n) - begin : sync_inputs - if (~reset_n) - begin - BusReq_s <= #1 1'b0; - INT_s <= #1 1'b0; - NMI_s <= #1 1'b0; - Oldnmi_n <= #1 1'b0; - end - else - begin - if (cen == 1'b1 ) - begin - BusReq_s <= #1 ~ busrq_n; - INT_s <= #1 ~ int_n; - if (NMICycle == 1'b1 ) - begin - NMI_s <= #1 1'b0; - end - else if (nmi_n == 1'b0 && Oldnmi_n == 1'b1 ) - begin - NMI_s <= #1 1'b1; - end - Oldnmi_n <= #1 nmi_n; - end - end - end - - //----------------------------------------------------------------------- - // - // Main state machine - // - //----------------------------------------------------------------------- - - always @ (posedge clk or negedge reset_n) - begin - if (reset_n == 1'b0 ) - begin - mcycle <= #1 7'b0000001; - tstate <= #1 7'b0000001; - Pre_XY_F_M <= #1 3'b000; - Halt_FF <= #1 1'b0; - BusAck <= #1 1'b0; - NMICycle <= #1 1'b0; - IntCycle <= #1 1'b0; - IntE_FF1 <= #1 1'b0; - IntE_FF2 <= #1 1'b0; - No_BTR <= #1 1'b0; - Auto_Wait_t1 <= #1 1'b0; - Auto_Wait_t2 <= #1 1'b0; - m1_n <= #1 1'b1; - end - else - begin - if (cen == 1'b1 ) - begin - if (T_Res == 1'b1 ) - begin - Auto_Wait_t1 <= #1 1'b0; - end - else - begin - Auto_Wait_t1 <= #1 Auto_Wait || (iorq_i & ~Auto_Wait_t2); - end - Auto_Wait_t2 <= #1 Auto_Wait_t1 & !T_Res; - No_BTR <= #1 (I_BT && (~ IR[4] || ~ F[Flag_P])) || - (I_BC && (~ IR[4] || F[Flag_Z] || ~ F[Flag_P])) || - (I_BTR && (~ IR[4] || F[Flag_Z])); - if (tstate[2] ) - begin - if (SetEI == 1'b1 ) - begin - if (!NMICycle) - IntE_FF1 <= #1 1'b1; - IntE_FF2 <= #1 1'b1; - end - if (I_RETN == 1'b1 ) - begin - IntE_FF1 <= #1 IntE_FF2; - end - end - if (tstate[3] ) - begin - if (SetDI == 1'b1 ) - begin - IntE_FF1 <= #1 1'b0; - IntE_FF2 <= #1 1'b0; - end - end - if (IntCycle == 1'b1 || NMICycle == 1'b1 ) - begin - Halt_FF <= #1 1'b0; - end - if (mcycle[0] && tstate[2] && wait_n == 1'b1 ) - begin - m1_n <= #1 1'b1; - end - if (BusReq_s == 1'b1 && BusAck == 1'b1 ) - begin - end - else - begin - BusAck <= #1 1'b0; - if (tstate[2] && wait_n == 1'b0 ) - begin - end - else if (T_Res == 1'b1 ) - begin - if (Halt == 1'b1 ) - begin - Halt_FF <= #1 1'b1; - end - if (BusReq_s == 1'b1 ) - begin - BusAck <= #1 1'b1; - end - else - begin - tstate <= #1 7'b0000010; - if (NextIs_XY_Fetch == 1'b1 ) - begin - mcycle <= #1 7'b0100000; - Pre_XY_F_M <= #1 mcyc_to_number(mcycle); - if (IR == 8'b00110110 && Mode == 0 ) - begin - Pre_XY_F_M <= #1 3'b010; - end - end - else if ((mcycle[6]) || (mcycle[5] && Mode == 1 && ISet != 2'b01) ) - begin - mcycle <= #1 number_to_bitvec(Pre_XY_F_M + 1); - end - else if ((last_mcycle) || - No_BTR == 1'b1 || - (mcycle[1] && I_DJNZ == 1'b1 && IncDecZ == 1'b1) ) - begin - m1_n <= #1 1'b0; - mcycle <= #1 7'b0000001; - IntCycle <= #1 1'b0; - NMICycle <= #1 1'b0; - if (NMI_s == 1'b1 && Prefix == 2'b00 ) - begin - NMICycle <= #1 1'b1; - IntE_FF1 <= #1 1'b0; - end - else if ((IntE_FF1 == 1'b1 && INT_s == 1'b1) && Prefix == 2'b00 && SetEI == 1'b0 ) - begin - IntCycle <= #1 1'b1; - IntE_FF1 <= #1 1'b0; - IntE_FF2 <= #1 1'b0; - end - end - else - begin - mcycle <= #1 { mcycle[5:0], mcycle[6] }; - end - end - end - else - begin // verilog has no "nor" operator - if ( ~(Auto_Wait == 1'b1 && Auto_Wait_t2 == 1'b0) && - ~(IOWait == 1 && iorq_i == 1'b1 && Auto_Wait_t1 == 1'b0) ) - begin - tstate <= #1 { tstate[5:0], tstate[6] }; - end - end - end - if (tstate[0]) - begin - m1_n <= #1 1'b0; - end - end - end - end - - always @(/*AUTOSENSE*/BTR_r or DI_Reg or IncDec_16 or JumpE or PC - or RegBusA or RegBusC or SP or tstate) - begin - if (JumpE == 1'b1 ) - begin - PC16_B = { {8{DI_Reg[7]}}, DI_Reg }; - end - else if (BTR_r == 1'b1 ) - begin - PC16_B = -2; - end - else - begin - PC16_B = 1; - end - - if (tstate[3]) - begin - SP16_A = RegBusC; - SP16_B = { {8{DI_Reg[7]}}, DI_Reg }; - end - else - begin - // suspect that ID16 and SP16 could be shared - SP16_A = SP; - - if (IncDec_16[3] == 1'b1) - SP16_B = -1; - else - SP16_B = 1; - end - - if (IncDec_16[3]) - ID16_B = -1; - else - ID16_B = 1; - - ID16 = RegBusA + ID16_B; - PC16 = PC + PC16_B; - SP16 = SP16_A + SP16_B; - end // always @ * - - - always @(/*AUTOSENSE*/IntCycle or NMICycle or mcycle) - begin - Auto_Wait = 1'b0; - if (IntCycle == 1'b1 || NMICycle == 1'b1 ) - begin - if (mcycle[0] ) - begin - Auto_Wait = 1'b1; - end - end - end // always @ * - -endmodule // T80 - diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/tv80/tv80_mcode.v b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/tv80/tv80_mcode.v deleted file mode 100644 index 40622d2b..00000000 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/tv80/tv80_mcode.v +++ /dev/null @@ -1,2650 +0,0 @@ -// -// TV80 8-Bit Microprocessor Core -// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) -// -// Copyright (c) 2004,2007 Guy Hutchison (ghutchis@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a -// copy of this software and associated documentation files (the "Software"), -// to deal in the Software without restriction, including without limitation -// the rights to use, copy, modify, merge, publish, distribute, sublicense, -// and/or sell copies of the Software, and to permit persons to whom the -// Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included -// in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -module tv80_mcode - (/*AUTOARG*/ - // Outputs - MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg, - Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC, - Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ, - LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF, - ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR, - I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write, - // Inputs - IR, ISet, MCycle, F, NMICycle, IntCycle - ); - - parameter Mode = 0; - parameter Flag_C = 0; - parameter Flag_N = 1; - parameter Flag_P = 2; - parameter Flag_X = 3; - parameter Flag_H = 4; - parameter Flag_Y = 5; - parameter Flag_Z = 6; - parameter Flag_S = 7; - - input [7:0] IR; - input [1:0] ISet ; - input [6:0] MCycle ; - input [7:0] F ; - input NMICycle ; - input IntCycle ; - output [2:0] MCycles ; - output [2:0] TStates ; - output [1:0] Prefix ; // None,BC,ED,DD/FD - output Inc_PC ; - output Inc_WZ ; - output [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc - output Read_To_Reg ; - output Read_To_Acc ; - output [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - output [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - output [3:0] ALU_Op ; - output Save_ALU ; - output PreserveC ; - output Arith16 ; - output [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI - output IORQ ; - output Jump ; - output JumpE ; - output JumpXY ; - output Call ; - output RstP ; - output LDZ ; - output LDW ; - output LDSPHL ; - output [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None - output ExchangeDH ; - output ExchangeRp ; - output ExchangeAF ; - output ExchangeRS ; - output I_DJNZ ; - output I_CPL ; - output I_CCF ; - output I_SCF ; - output I_RETN ; - output I_BT ; - output I_BC ; - output I_BTR ; - output I_RLD ; - output I_RRD ; - output I_INRC ; - output SetDI ; - output SetEI ; - output [1:0] IMode ; - output Halt ; - output NoRead ; - output Write ; - - // regs - reg [2:0] MCycles ; - reg [2:0] TStates ; - reg [1:0] Prefix ; // None,BC,ED,DD/FD - reg Inc_PC ; - reg Inc_WZ ; - reg [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc - reg Read_To_Reg ; - reg Read_To_Acc ; - reg [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - reg [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - reg [3:0] ALU_Op ; - reg Save_ALU ; - reg PreserveC ; - reg Arith16 ; - reg [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI - reg IORQ ; - reg Jump ; - reg JumpE ; - reg JumpXY ; - reg Call ; - reg RstP ; - reg LDZ ; - reg LDW ; - reg LDSPHL ; - reg [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None - reg ExchangeDH ; - reg ExchangeRp ; - reg ExchangeAF ; - reg ExchangeRS ; - reg I_DJNZ ; - reg I_CPL ; - reg I_CCF ; - reg I_SCF ; - reg I_RETN ; - reg I_BT ; - reg I_BC ; - reg I_BTR ; - reg I_RLD ; - reg I_RRD ; - reg I_INRC ; - reg SetDI ; - reg SetEI ; - reg [1:0] IMode ; - reg Halt ; - reg NoRead ; - reg Write ; - - parameter aNone = 3'b111; - parameter aBC = 3'b000; - parameter aDE = 3'b001; - parameter aXY = 3'b010; - parameter aIOA = 3'b100; - parameter aSP = 3'b101; - parameter aZI = 3'b110; - // constant aNone : std_logic_vector[2:0] = 3'b000; - // constant aXY : std_logic_vector[2:0] = 3'b001; - // constant aIOA : std_logic_vector[2:0] = 3'b010; - // constant aSP : std_logic_vector[2:0] = 3'b011; - // constant aBC : std_logic_vector[2:0] = 3'b100; - // constant aDE : std_logic_vector[2:0] = 3'b101; - // constant aZI : std_logic_vector[2:0] = 3'b110; - - function is_cc_true; - input [7:0] FF; - input [2:0] cc; - begin - if (Mode == 3 ) - begin - case (cc) - 3'b000 : is_cc_true = FF[7] == 1'b0; // NZ - 3'b001 : is_cc_true = FF[7] == 1'b1; // Z - 3'b010 : is_cc_true = FF[4] == 1'b0; // NC - 3'b011 : is_cc_true = FF[4] == 1'b1; // C - 3'b100 : is_cc_true = 0; - 3'b101 : is_cc_true = 0; - 3'b110 : is_cc_true = 0; - 3'b111 : is_cc_true = 0; - endcase - end - else - begin - case (cc) - 3'b000 : is_cc_true = FF[6] == 1'b0; // NZ - 3'b001 : is_cc_true = FF[6] == 1'b1; // Z - 3'b010 : is_cc_true = FF[0] == 1'b0; // NC - 3'b011 : is_cc_true = FF[0] == 1'b1; // C - 3'b100 : is_cc_true = FF[2] == 1'b0; // PO - 3'b101 : is_cc_true = FF[2] == 1'b1; // PE - 3'b110 : is_cc_true = FF[7] == 1'b0; // P - 3'b111 : is_cc_true = FF[7] == 1'b1; // M - endcase - end - end - endfunction // is_cc_true - - - reg [2:0] DDD; - reg [2:0] SSS; - reg [1:0] DPAIR; - - always @ (/*AUTOSENSE*/F or IR or ISet or IntCycle or MCycle - or NMICycle) - begin - DDD = IR[5:3]; - SSS = IR[2:0]; - DPAIR = IR[5:4]; - - MCycles = 3'b001; - if (MCycle[0] ) - begin - TStates = 3'b100; - end - else - begin - TStates = 3'b011; - end - Prefix = 2'b00; - Inc_PC = 1'b0; - Inc_WZ = 1'b0; - IncDec_16 = 4'b0000; - Read_To_Acc = 1'b0; - Read_To_Reg = 1'b0; - Set_BusB_To = 4'b0000; - Set_BusA_To = 4'b0000; - ALU_Op = { 1'b0, IR[5:3] }; - Save_ALU = 1'b0; - PreserveC = 1'b0; - Arith16 = 1'b0; - IORQ = 1'b0; - Set_Addr_To = aNone; - Jump = 1'b0; - JumpE = 1'b0; - JumpXY = 1'b0; - Call = 1'b0; - RstP = 1'b0; - LDZ = 1'b0; - LDW = 1'b0; - LDSPHL = 1'b0; - Special_LD = 3'b000; - ExchangeDH = 1'b0; - ExchangeRp = 1'b0; - ExchangeAF = 1'b0; - ExchangeRS = 1'b0; - I_DJNZ = 1'b0; - I_CPL = 1'b0; - I_CCF = 1'b0; - I_SCF = 1'b0; - I_RETN = 1'b0; - I_BT = 1'b0; - I_BC = 1'b0; - I_BTR = 1'b0; - I_RLD = 1'b0; - I_RRD = 1'b0; - I_INRC = 1'b0; - SetDI = 1'b0; - SetEI = 1'b0; - IMode = 2'b11; - Halt = 1'b0; - NoRead = 1'b0; - Write = 1'b0; - - case (ISet) - 2'b00 : - begin - - //---------------------------------------------------------------------------- - // - // Unprefixed instructions - // - //---------------------------------------------------------------------------- - - casez (IR) - // 8 BIT LOAD GROUP - 8'b01zzzzzz : - begin - if (IR[5:0] == 6'b110110) - Halt = 1'b1; - else if (IR[2:0] == 3'b110) - begin - // LD r,(HL) - MCycles = 3'b010; - if (MCycle[0]) - Set_Addr_To = aXY; - if (MCycle[1]) - begin - Set_BusA_To[2:0] = DDD; - Read_To_Reg = 1'b1; - end - end // if (IR[2:0] == 3'b110) - else if (IR[5:3] == 3'b110) - begin - // LD (HL),r - MCycles = 3'b010; - if (MCycle[0]) - begin - Set_Addr_To = aXY; - Set_BusB_To[2:0] = SSS; - Set_BusB_To[3] = 1'b0; - end - if (MCycle[1]) - Write = 1'b1; - end // if (IR[5:3] == 3'b110) - else - begin - Set_BusB_To[2:0] = SSS; - ExchangeRp = 1'b1; - Set_BusA_To[2:0] = DDD; - Read_To_Reg = 1'b1; - end // else: !if(IR[5:3] == 3'b110) - end // case: 8'b01zzzzzz - - 8'b00zzz110 : - begin - if (IR[5:3] == 3'b110) - begin - // LD (HL),n - MCycles = 3'b011; - if (MCycle[1]) - begin - Inc_PC = 1'b1; - Set_Addr_To = aXY; - Set_BusB_To[2:0] = SSS; - Set_BusB_To[3] = 1'b0; - end - if (MCycle[2]) - Write = 1'b1; - end // if (IR[5:3] == 3'b110) - else - begin - // LD r,n - MCycles = 3'b010; - if (MCycle[1]) - begin - Inc_PC = 1'b1; - Set_BusA_To[2:0] = DDD; - Read_To_Reg = 1'b1; - end - end - end - - 8'b00001010 : - begin - // LD A,(BC) - MCycles = 3'b010; - if (MCycle[0]) - Set_Addr_To = aBC; - if (MCycle[1]) - Read_To_Acc = 1'b1; - end // case: 8'b00001010 - - 8'b00011010 : - begin - // LD A,(DE) - MCycles = 3'b010; - if (MCycle[0]) - Set_Addr_To = aDE; - if (MCycle[1]) - Read_To_Acc = 1'b1; - end // case: 8'b00011010 - - 8'b00111010 : - begin - if (Mode == 3 ) - begin - // LDD A,(HL) - MCycles = 3'b010; - if (MCycle[0]) - Set_Addr_To = aXY; - if (MCycle[1]) - begin - Read_To_Acc = 1'b1; - IncDec_16 = 4'b1110; - end - end - else - begin - // LD A,(nn) - MCycles = 3'b100; - if (MCycle[1]) - begin - Inc_PC = 1'b1; - LDZ = 1'b1; - end - if (MCycle[2]) - begin - Set_Addr_To = aZI; - Inc_PC = 1'b1; - end - if (MCycle[3]) - begin - Read_To_Acc = 1'b1; - end - end // else: !if(Mode == 3 ) - end // case: 8'b00111010 - - 8'b00000010 : - begin - // LD (BC),A - MCycles = 3'b010; - if (MCycle[0]) - begin - Set_Addr_To = aBC; - Set_BusB_To = 4'b0111; - end - if (MCycle[1]) - begin - Write = 1'b1; - end - end // case: 8'b00000010 - - 8'b00010010 : - begin - // LD (DE),A - MCycles = 3'b010; - case (1'b1) // MCycle - MCycle[0] : - begin - Set_Addr_To = aDE; - Set_BusB_To = 4'b0111; - end - MCycle[1] : - Write = 1'b1; - default :; - endcase // case(MCycle) - end // case: 8'b00010010 - - 8'b00110010 : - begin - if (Mode == 3 ) - begin - // LDD (HL),A - MCycles = 3'b010; - case (1'b1) // MCycle - MCycle[0] : - begin - Set_Addr_To = aXY; - Set_BusB_To = 4'b0111; - end - MCycle[1] : - begin - Write = 1'b1; - IncDec_16 = 4'b1110; - end - default :; - endcase // case(MCycle) - - end - else - begin - // LD (nn),A - MCycles = 3'b100; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - LDZ = 1'b1; - end - MCycle[2] : - begin - Set_Addr_To = aZI; - Inc_PC = 1'b1; - Set_BusB_To = 4'b0111; - end - MCycle[3] : - begin - Write = 1'b1; - end - default :; - endcase - end // else: !if(Mode == 3 ) - end // case: 8'b00110010 - - - // 16 BIT LOAD GROUP - 8'b00000001,8'b00010001,8'b00100001,8'b00110001 : - begin - // LD dd,nn - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - Read_To_Reg = 1'b1; - if (DPAIR == 2'b11 ) - begin - Set_BusA_To[3:0] = 4'b1000; - end - else - begin - Set_BusA_To[2:1] = DPAIR; - Set_BusA_To[0] = 1'b1; - end - end // case: 2 - - MCycle[2] : - begin - Inc_PC = 1'b1; - Read_To_Reg = 1'b1; - if (DPAIR == 2'b11 ) - begin - Set_BusA_To[3:0] = 4'b1001; - end - else - begin - Set_BusA_To[2:1] = DPAIR; - Set_BusA_To[0] = 1'b0; - end - end // case: 3 - - default :; - endcase // case(MCycle) - end // case: 8'b00000001,8'b00010001,8'b00100001,8'b00110001 - - 8'b00101010 : - begin - if (Mode == 3 ) - begin - // LDI A,(HL) - MCycles = 3'b010; - case (1'b1) // MCycle - MCycle[0] : - Set_Addr_To = aXY; - MCycle[1] : - begin - Read_To_Acc = 1'b1; - IncDec_16 = 4'b0110; - end - - default :; - endcase - end - else - begin - // LD HL,(nn) - MCycles = 3'b101; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - LDZ = 1'b1; - end - MCycle[2] : - begin - Set_Addr_To = aZI; - Inc_PC = 1'b1; - LDW = 1'b1; - end - MCycle[3] : - begin - Set_BusA_To[2:0] = 3'b101; // L - Read_To_Reg = 1'b1; - Inc_WZ = 1'b1; - Set_Addr_To = aZI; - end - MCycle[4] : - begin - Set_BusA_To[2:0] = 3'b100; // H - Read_To_Reg = 1'b1; - end - default :; - endcase - end // else: !if(Mode == 3 ) - end // case: 8'b00101010 - - 8'b00100010 : - begin - if (Mode == 3 ) - begin - // LDI (HL),A - MCycles = 3'b010; - case (1'b1) // MCycle - MCycle[0] : - begin - Set_Addr_To = aXY; - Set_BusB_To = 4'b0111; - end - MCycle[1] : - begin - Write = 1'b1; - IncDec_16 = 4'b0110; - end - default :; - endcase - end - else - begin - // LD (nn),HL - MCycles = 3'b101; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - LDZ = 1'b1; - end - - MCycle[2] : - begin - Set_Addr_To = aZI; - Inc_PC = 1'b1; - LDW = 1'b1; - Set_BusB_To = 4'b0101; // L - end - - MCycle[3] : - begin - Inc_WZ = 1'b1; - Set_Addr_To = aZI; - Write = 1'b1; - Set_BusB_To = 4'b0100; // H - end - MCycle[4] : - Write = 1'b1; - default :; - endcase - end // else: !if(Mode == 3 ) - end // case: 8'b00100010 - - 8'b11111001 : - begin - // LD SP,HL - TStates = 3'b110; - LDSPHL = 1'b1; - end - - 8'b11zz0101 : - begin - // PUSH qq - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[0] : - begin - TStates = 3'b101; - IncDec_16 = 4'b1111; - Set_Addr_To = aSP; - if (DPAIR == 2'b11 ) - begin - Set_BusB_To = 4'b0111; - end - else - begin - Set_BusB_To[2:1] = DPAIR; - Set_BusB_To[0] = 1'b0; - Set_BusB_To[3] = 1'b0; - end - end // case: 1 - - MCycle[1] : - begin - IncDec_16 = 4'b1111; - Set_Addr_To = aSP; - if (DPAIR == 2'b11 ) - begin - Set_BusB_To = 4'b1011; - end - else - begin - Set_BusB_To[2:1] = DPAIR; - Set_BusB_To[0] = 1'b1; - Set_BusB_To[3] = 1'b0; - end - Write = 1'b1; - end // case: 2 - - MCycle[2] : - Write = 1'b1; - default :; - endcase // case(MCycle) - end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101 - - 8'b11zz0001 : - begin - // POP qq - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[0] : - Set_Addr_To = aSP; - MCycle[1] : - begin - IncDec_16 = 4'b0111; - Set_Addr_To = aSP; - Read_To_Reg = 1'b1; - if (DPAIR == 2'b11 ) - begin - Set_BusA_To[3:0] = 4'b1011; - end - else - begin - Set_BusA_To[2:1] = DPAIR; - Set_BusA_To[0] = 1'b1; - end - end // case: 2 - - MCycle[2] : - begin - IncDec_16 = 4'b0111; - Read_To_Reg = 1'b1; - if (DPAIR == 2'b11 ) - begin - Set_BusA_To[3:0] = 4'b0111; - end - else - begin - Set_BusA_To[2:1] = DPAIR; - Set_BusA_To[0] = 1'b0; - end - end // case: 3 - - default :; - endcase // case(MCycle) - end // case: 8'b11000001,8'b11010001,8'b11100001,8'b11110001 - - - // EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - 8'b11101011 : - begin - if (Mode != 3 ) - begin - // EX DE,HL - ExchangeDH = 1'b1; - end - end - - 8'b00001000 : - begin - if (Mode == 3 ) - begin - // LD (nn),SP - MCycles = 3'b101; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - LDZ = 1'b1; - end - - MCycle[2] : - begin - Set_Addr_To = aZI; - Inc_PC = 1'b1; - LDW = 1'b1; - Set_BusB_To = 4'b1000; - end - - MCycle[3] : - begin - Inc_WZ = 1'b1; - Set_Addr_To = aZI; - Write = 1'b1; - Set_BusB_To = 4'b1001; - end - - MCycle[4] : - Write = 1'b1; - default :; - endcase - end - else if (Mode < 2 ) - begin - // EX AF,AF' - ExchangeAF = 1'b1; - end - end // case: 8'b00001000 - - 8'b11011001 : - begin - if (Mode == 3 ) - begin - // RETI - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[0] : - Set_Addr_To = aSP; - MCycle[1] : - begin - IncDec_16 = 4'b0111; - Set_Addr_To = aSP; - LDZ = 1'b1; - end - - MCycle[2] : - begin - Jump = 1'b1; - IncDec_16 = 4'b0111; - I_RETN = 1'b1; - SetEI = 1'b1; - end - default :; - endcase - end - else if (Mode < 2 ) - begin - // EXX - ExchangeRS = 1'b1; - end - end // case: 8'b11011001 - - 8'b11100011 : - begin - if (Mode != 3 ) - begin - // EX (SP),HL - MCycles = 3'b101; - case (1'b1) // MCycle - MCycle[0] : - Set_Addr_To = aSP; - MCycle[1] : - begin - Read_To_Reg = 1'b1; - Set_BusA_To = 4'b0101; - Set_BusB_To = 4'b0101; - Set_Addr_To = aSP; - end - MCycle[2] : - begin - IncDec_16 = 4'b0111; - Set_Addr_To = aSP; - TStates = 3'b100; - Write = 1'b1; - end - MCycle[3] : - begin - Read_To_Reg = 1'b1; - Set_BusA_To = 4'b0100; - Set_BusB_To = 4'b0100; - Set_Addr_To = aSP; - end - MCycle[4] : - begin - IncDec_16 = 4'b1111; - TStates = 3'b101; - Write = 1'b1; - end - - default :; - endcase - end // if (Mode != 3 ) - end // case: 8'b11100011 - - - // 8 BIT ARITHMETIC AND LOGICAL GROUP - 8'b10zzzzzz : - begin - if (IR[2:0] == 3'b110) - begin - // ADD A,(HL) - // ADC A,(HL) - // SUB A,(HL) - // SBC A,(HL) - // AND A,(HL) - // OR A,(HL) - // XOR A,(HL) - // CP A,(HL) - MCycles = 3'b010; - case (1'b1) // MCycle - MCycle[0] : - Set_Addr_To = aXY; - MCycle[1] : - begin - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - Set_BusB_To[2:0] = SSS; - Set_BusA_To[2:0] = 3'b111; - end - - default :; - endcase // case(MCycle) - end // if (IR[2:0] == 3'b110) - else - begin - // ADD A,r - // ADC A,r - // SUB A,r - // SBC A,r - // AND A,r - // OR A,r - // XOR A,r - // CP A,r - Set_BusB_To[2:0] = SSS; - Set_BusA_To[2:0] = 3'b111; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - end // else: !if(IR[2:0] == 3'b110) - end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,... - - 8'b11zzz110 : - begin - // ADD A,n - // ADC A,n - // SUB A,n - // SBC A,n - // AND A,n - // OR A,n - // XOR A,n - // CP A,n - MCycles = 3'b010; - if (MCycle[1] ) - begin - Inc_PC = 1'b1; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - Set_BusB_To[2:0] = SSS; - Set_BusA_To[2:0] = 3'b111; - end - end - - 8'b00zzz100 : - begin - if (IR[5:3] == 3'b110) - begin - // INC (HL) - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[0] : - Set_Addr_To = aXY; - MCycle[1] : - begin - TStates = 3'b100; - Set_Addr_To = aXY; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - PreserveC = 1'b1; - ALU_Op = 4'b0000; - Set_BusB_To = 4'b1010; - Set_BusA_To[2:0] = DDD; - end // case: 2 - - MCycle[2] : - Write = 1'b1; - default :; - endcase // case(MCycle) - end // case: 8'b00110100 - else - begin - // INC r - Set_BusB_To = 4'b1010; - Set_BusA_To[2:0] = DDD; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - PreserveC = 1'b1; - ALU_Op = 4'b0000; - end - end - - 8'b00zzz101 : - begin - if (IR[5:3] == 3'b110) - begin - // DEC (HL) - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[0] : - Set_Addr_To = aXY; - MCycle[1] : - begin - TStates = 3'b100; - Set_Addr_To = aXY; - ALU_Op = 4'b0010; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - PreserveC = 1'b1; - Set_BusB_To = 4'b1010; - Set_BusA_To[2:0] = DDD; - end // case: 2 - - MCycle[2] : - Write = 1'b1; - default :; - endcase // case(MCycle) - end - else - begin - // DEC r - Set_BusB_To = 4'b1010; - Set_BusA_To[2:0] = DDD; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - PreserveC = 1'b1; - ALU_Op = 4'b0010; - end - end - - // GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - 8'b00100111 : - begin - // DAA - Set_BusA_To[2:0] = 3'b111; - Read_To_Reg = 1'b1; - ALU_Op = 4'b1100; - Save_ALU = 1'b1; - end - - 8'b00101111 : - // CPL - I_CPL = 1'b1; - - 8'b00111111 : - // CCF - I_CCF = 1'b1; - - 8'b00110111 : - // SCF - I_SCF = 1'b1; - - 8'b00000000 : - begin - if (NMICycle == 1'b1 ) - begin - // NMI - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[0] : - begin - TStates = 3'b101; - IncDec_16 = 4'b1111; - Set_Addr_To = aSP; - Set_BusB_To = 4'b1101; - end - - MCycle[1] : - begin - TStates = 3'b100; - Write = 1'b1; - IncDec_16 = 4'b1111; - Set_Addr_To = aSP; - Set_BusB_To = 4'b1100; - end - - MCycle[2] : - begin - TStates = 3'b100; - Write = 1'b1; - end - - default :; - endcase // case(MCycle) - - end - else if (IntCycle == 1'b1 ) - begin - // INT (IM 2) - MCycles = 3'b101; - case (1'b1) // MCycle - MCycle[0] : - begin - LDZ = 1'b1; - TStates = 3'b101; - IncDec_16 = 4'b1111; - Set_Addr_To = aSP; - Set_BusB_To = 4'b1101; - end - - MCycle[1] : - begin - TStates = 3'b100; - Write = 1'b1; - IncDec_16 = 4'b1111; - Set_Addr_To = aSP; - Set_BusB_To = 4'b1100; - end - - MCycle[2] : - begin - TStates = 3'b100; - Write = 1'b1; - end - - MCycle[3] : - begin - Inc_PC = 1'b1; - LDZ = 1'b1; - end - - MCycle[4] : - Jump = 1'b1; - default :; - endcase - end - end // case: 8'b00000000 - - 8'b11110011 : - // DI - SetDI = 1'b1; - - 8'b11111011 : - // EI - SetEI = 1'b1; - - // 16 BIT ARITHMETIC GROUP - 8'b00zz1001 : - begin - // ADD HL,ss - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[1] : - begin - NoRead = 1'b1; - ALU_Op = 4'b0000; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - Set_BusA_To[2:0] = 3'b101; - case (IR[5:4]) - 0,1,2 : - begin - Set_BusB_To[2:1] = IR[5:4]; - Set_BusB_To[0] = 1'b1; - end - - default : - Set_BusB_To = 4'b1000; - endcase // case(IR[5:4]) - - TStates = 3'b100; - Arith16 = 1'b1; - end // case: 2 - - MCycle[2] : - begin - NoRead = 1'b1; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - ALU_Op = 4'b0001; - Set_BusA_To[2:0] = 3'b100; - case (IR[5:4]) - 0,1,2 : - Set_BusB_To[2:1] = IR[5:4]; - default : - Set_BusB_To = 4'b1001; - endcase - Arith16 = 1'b1; - end // case: 3 - - default :; - endcase // case(MCycle) - end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001 - - 8'b00zz0011 : - begin - // INC ss - TStates = 3'b110; - IncDec_16[3:2] = 2'b01; - IncDec_16[1:0] = DPAIR; - end - - 8'b00zz1011 : - begin - // DEC ss - TStates = 3'b110; - IncDec_16[3:2] = 2'b11; - IncDec_16[1:0] = DPAIR; - end - - // ROTATE AND SHIFT GROUP - 8'b00000111, - // RLCA - 8'b00010111, - // RLA - 8'b00001111, - // RRCA - 8'b00011111 : - // RRA - begin - Set_BusA_To[2:0] = 3'b111; - ALU_Op = 4'b1000; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - end // case: 8'b00000111,... - - - // JUMP GROUP - 8'b11000011 : - begin - // JP nn - MCycles = 3'b011; - if (MCycle[1]) - begin - Inc_PC = 1'b1; - LDZ = 1'b1; - end - - if (MCycle[2]) - begin - Inc_PC = 1'b1; - Jump = 1'b1; - end - - end // case: 8'b11000011 - - 8'b11zzz010 : - begin - if (IR[5] == 1'b1 && Mode == 3 ) - begin - case (IR[4:3]) - 2'b00 : - begin - // LD ($FF00+C),A - MCycles = 3'b010; - case (1'b1) // MCycle - MCycle[0] : - begin - Set_Addr_To = aBC; - Set_BusB_To = 4'b0111; - end - MCycle[1] : - begin - Write = 1'b1; - IORQ = 1'b1; - end - - default :; - endcase // case(MCycle) - end // case: 2'b00 - - 2'b01 : - begin - // LD (nn),A - MCycles = 3'b100; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - LDZ = 1'b1; - end - - MCycle[2] : - begin - Set_Addr_To = aZI; - Inc_PC = 1'b1; - Set_BusB_To = 4'b0111; - end - - MCycle[3] : - Write = 1'b1; - default :; - endcase // case(MCycle) - end // case: default :... - - 2'b10 : - begin - // LD A,($FF00+C) - MCycles = 3'b010; - case (1'b1) // MCycle - MCycle[0] : - Set_Addr_To = aBC; - MCycle[1] : - begin - Read_To_Acc = 1'b1; - IORQ = 1'b1; - end - default :; - endcase // case(MCycle) - end // case: 2'b10 - - 2'b11 : - begin - // LD A,(nn) - MCycles = 3'b100; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - LDZ = 1'b1; - end - MCycle[2] : - begin - Set_Addr_To = aZI; - Inc_PC = 1'b1; - end - MCycle[3] : - Read_To_Acc = 1'b1; - default :; - endcase // case(MCycle) - end - endcase - end - else - begin - // JP cc,nn - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - LDZ = 1'b1; - end - MCycle[2] : - begin - Inc_PC = 1'b1; - if (is_cc_true(F, IR[5:3]) ) - begin - Jump = 1'b1; - end - end - - default :; - endcase - end // else: !if(DPAIR == 2'b11 ) - end // case: 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010 - - 8'b00011000 : - begin - if (Mode != 2 ) - begin - // JR e - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[1] : - Inc_PC = 1'b1; - MCycle[2] : - begin - NoRead = 1'b1; - JumpE = 1'b1; - TStates = 3'b101; - end - default :; - endcase - end // if (Mode != 2 ) - end // case: 8'b00011000 - - // Conditional relative jumps (JR [C/NC/Z/NZ], e) - 8'b001zz000 : - begin - if (Mode != 2 ) - begin - MCycles = 3'd3; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - - case (IR[4:3]) - 0 : MCycles = (F[Flag_Z]) ? 3'd2 : 3'd3; - 1 : MCycles = (!F[Flag_Z]) ? 3'd2 : 3'd3; - 2 : MCycles = (F[Flag_C]) ? 3'd2 : 3'd3; - 3 : MCycles = (!F[Flag_C]) ? 3'd2 : 3'd3; - endcase - end - - MCycle[2] : - begin - NoRead = 1'b1; - JumpE = 1'b1; - TStates = 3'd5; - end - default :; - endcase - end // if (Mode != 2 ) - end // case: 8'b00111000 - - 8'b11101001 : - // JP (HL) - JumpXY = 1'b1; - - 8'b00010000 : - begin - if (Mode == 3 ) - begin - I_DJNZ = 1'b1; - end - else if (Mode < 2 ) - begin - // DJNZ,e - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[0] : - begin - TStates = 3'b101; - I_DJNZ = 1'b1; - Set_BusB_To = 4'b1010; - Set_BusA_To[2:0] = 3'b000; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - ALU_Op = 4'b0010; - end - MCycle[1] : - begin - I_DJNZ = 1'b1; - Inc_PC = 1'b1; - end - MCycle[2] : - begin - NoRead = 1'b1; - JumpE = 1'b1; - TStates = 3'b101; - end - default :; - endcase - end // if (Mode < 2 ) - end // case: 8'b00010000 - - - // CALL AND RETURN GROUP - 8'b11001101 : - begin - // CALL nn - MCycles = 3'b101; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - LDZ = 1'b1; - end - MCycle[2] : - begin - IncDec_16 = 4'b1111; - Inc_PC = 1'b1; - TStates = 3'b100; - Set_Addr_To = aSP; - LDW = 1'b1; - Set_BusB_To = 4'b1101; - end - MCycle[3] : - begin - Write = 1'b1; - IncDec_16 = 4'b1111; - Set_Addr_To = aSP; - Set_BusB_To = 4'b1100; - end - MCycle[4] : - begin - Write = 1'b1; - Call = 1'b1; - end - default :; - endcase // case(MCycle) - end // case: 8'b11001101 - - 8'b11zzz100 : - begin - if (IR[5] == 1'b0 || Mode != 3 ) - begin - // CALL cc,nn - MCycles = 3'b101; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - LDZ = 1'b1; - end - MCycle[2] : - begin - Inc_PC = 1'b1; - LDW = 1'b1; - if (is_cc_true(F, IR[5:3]) ) - begin - IncDec_16 = 4'b1111; - Set_Addr_To = aSP; - TStates = 3'b100; - Set_BusB_To = 4'b1101; - end - else - begin - MCycles = 3'b011; - end // else: !if(is_cc_true(F, IR[5:3]) ) - end // case: 3 - - MCycle[3] : - begin - Write = 1'b1; - IncDec_16 = 4'b1111; - Set_Addr_To = aSP; - Set_BusB_To = 4'b1100; - end - - MCycle[4] : - begin - Write = 1'b1; - Call = 1'b1; - end - - default :; - endcase - end // if (IR[5] == 1'b0 || Mode != 3 ) - end // case: 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100 - - 8'b11001001 : - begin - // RET - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[0] : - begin - TStates = 3'b101; - Set_Addr_To = aSP; - end - - MCycle[1] : - begin - IncDec_16 = 4'b0111; - Set_Addr_To = aSP; - LDZ = 1'b1; - end - - MCycle[2] : - begin - Jump = 1'b1; - IncDec_16 = 4'b0111; - end - - default :; - endcase // case(MCycle) - end // case: 8'b11001001 - - 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 : - begin - if (IR[5] == 1'b1 && Mode == 3 ) - begin - case (IR[4:3]) - 2'b00 : - begin - // LD ($FF00+nn),A - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - Set_Addr_To = aIOA; - Set_BusB_To = 4'b0111; - end - - MCycle[2] : - Write = 1'b1; - default :; - endcase // case(MCycle) - end // case: 2'b00 - - 2'b01 : - begin - // ADD SP,n - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[1] : - begin - ALU_Op = 4'b0000; - Inc_PC = 1'b1; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - Set_BusA_To = 4'b1000; - Set_BusB_To = 4'b0110; - end - - MCycle[2] : - begin - NoRead = 1'b1; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - ALU_Op = 4'b0001; - Set_BusA_To = 4'b1001; - Set_BusB_To = 4'b1110; // Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - end - - default :; - endcase // case(MCycle) - end // case: 2'b01 - - 2'b10 : - begin - // LD A,($FF00+nn) - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - Set_Addr_To = aIOA; - end - - MCycle[2] : - Read_To_Acc = 1'b1; - default :; - endcase // case(MCycle) - end // case: 2'b10 - - 2'b11 : - begin - // LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles = 3'b101; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - LDZ = 1'b1; - end - - MCycle[2] : - begin - Set_Addr_To = aZI; - Inc_PC = 1'b1; - LDW = 1'b1; - end - - MCycle[3] : - begin - Set_BusA_To[2:0] = 3'b101; // L - Read_To_Reg = 1'b1; - Inc_WZ = 1'b1; - Set_Addr_To = aZI; - end - - MCycle[4] : - begin - Set_BusA_To[2:0] = 3'b100; // H - Read_To_Reg = 1'b1; - end - - default :; - endcase // case(MCycle) - end // case: 2'b11 - - endcase // case(IR[4:3]) - - end - else - begin - // RET cc - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[0] : - begin - if (is_cc_true(F, IR[5:3]) ) - begin - Set_Addr_To = aSP; - end - else - begin - MCycles = 3'b001; - end - TStates = 3'b101; - end // case: 1 - - MCycle[1] : - begin - IncDec_16 = 4'b0111; - Set_Addr_To = aSP; - LDZ = 1'b1; - end - MCycle[2] : - begin - Jump = 1'b1; - IncDec_16 = 4'b0111; - end - default :; - endcase - end // else: !if(IR[5] == 1'b1 && Mode == 3 ) - end // case: 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 - - 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 : - begin - // RST p - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[0] : - begin - TStates = 3'b101; - IncDec_16 = 4'b1111; - Set_Addr_To = aSP; - Set_BusB_To = 4'b1101; - end - - MCycle[1] : - begin - Write = 1'b1; - IncDec_16 = 4'b1111; - Set_Addr_To = aSP; - Set_BusB_To = 4'b1100; - end - - MCycle[2] : - begin - Write = 1'b1; - RstP = 1'b1; - end - - default :; - endcase // case(MCycle) - end // case: 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 - - // INPUT AND OUTPUT GROUP - 8'b11011011 : - begin - if (Mode != 3 ) - begin - // IN A,(n) - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - Set_Addr_To = aIOA; - end - - MCycle[2] : - begin - Read_To_Acc = 1'b1; - IORQ = 1'b1; - end - - default :; - endcase - end // if (Mode != 3 ) - end // case: 8'b11011011 - - 8'b11010011 : - begin - if (Mode != 3 ) - begin - // OUT (n),A - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - Set_Addr_To = aIOA; - Set_BusB_To = 4'b0111; - end - - MCycle[2] : - begin - Write = 1'b1; - IORQ = 1'b1; - end - - default :; - endcase - end // if (Mode != 3 ) - end // case: 8'b11010011 - - - //---------------------------------------------------------------------------- - //---------------------------------------------------------------------------- - // MULTIBYTE INSTRUCTIONS - //---------------------------------------------------------------------------- - //---------------------------------------------------------------------------- - - 8'b11001011 : - begin - if (Mode != 2 ) - begin - Prefix = 2'b01; - end - end - - 8'b11101101 : - begin - if (Mode < 2 ) - begin - Prefix = 2'b10; - end - end - - 8'b11011101,8'b11111101 : - begin - if (Mode < 2 ) - begin - Prefix = 2'b11; - end - end - - endcase // case(IR) - end // case: 2'b00 - - - 2'b01 : - begin - - - //---------------------------------------------------------------------------- - // - // CB prefixed instructions - // - //---------------------------------------------------------------------------- - - Set_BusA_To[2:0] = IR[2:0]; - Set_BusB_To[2:0] = IR[2:0]; - - casez (IR) - 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111, - 8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111, - 8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111, - 8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111, - 8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111, - 8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111, - 8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111, - 8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 : - begin - // RLC r - // RL r - // RRC r - // RR r - // SLA r - // SRA r - // SRL r - // SLL r (Undocumented) / SWAP r - if (MCycle[0] ) begin - ALU_Op = 4'b1000; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - end - end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,... - - 8'b00zzz110 : - begin - // RLC (HL) - // RL (HL) - // RRC (HL) - // RR (HL) - // SRA (HL) - // SRL (HL) - // SLA (HL) - // SLL (HL) (Undocumented) / SWAP (HL) - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[0], MCycle[6] : - Set_Addr_To = aXY; - MCycle[1] : - begin - ALU_Op = 4'b1000; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - Set_Addr_To = aXY; - TStates = 3'b100; - end - - MCycle[2] : - Write = 1'b1; - default :; - endcase // case(MCycle) - end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110 - - 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111, - 8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111, - 8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111, - 8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111, - 8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111, - 8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111, - 8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111, - 8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 : - begin - // BIT b,r - if (MCycle[0] ) - begin - Set_BusB_To[2:0] = IR[2:0]; - ALU_Op = 4'b1001; - end - end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,... - - 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 : - begin - // BIT b,(HL) - MCycles = 3'b010; - case (1'b1) // MCycle - MCycle[0], MCycle[6] : - Set_Addr_To = aXY; - MCycle[1] : - begin - ALU_Op = 4'b1001; - TStates = 3'b100; - end - - default :; - endcase // case(MCycle) - end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 - - 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111, - 8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111, - 8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111, - 8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111, - 8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111, - 8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111, - 8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111, - 8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 : - begin - // SET b,r - if (MCycle[0] ) - begin - ALU_Op = 4'b1010; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - end - end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,... - - 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 : - begin - // SET b,(HL) - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[0], MCycle[6] : - Set_Addr_To = aXY; - MCycle[1] : - begin - ALU_Op = 4'b1010; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - Set_Addr_To = aXY; - TStates = 3'b100; - end - MCycle[2] : - Write = 1'b1; - default :; - endcase // case(MCycle) - end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 - - 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111, - 8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111, - 8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111, - 8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111, - 8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111, - 8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111, - 8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111, - 8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 : - begin - // RES b,r - if (MCycle[0] ) - begin - ALU_Op = 4'b1011; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - end - end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,... - - 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 : - begin - // RES b,(HL) - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[0], MCycle[6] : - Set_Addr_To = aXY; - MCycle[1] : - begin - ALU_Op = 4'b1011; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - Set_Addr_To = aXY; - TStates = 3'b100; - end - - MCycle[2] : - Write = 1'b1; - default :; - endcase // case(MCycle) - end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 - - endcase // case(IR) - end // case: 2'b01 - - - default : - begin : default_ed_block - - //---------------------------------------------------------------------------- - // - // ED prefixed instructions - // - //---------------------------------------------------------------------------- - - casez (IR) - /* - * Undocumented NOP instructions commented out to reduce size of mcode - * - 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111 - ,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111 - ,8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010110,8'b00010111 - ,8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011110,8'b00011111 - ,8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100110,8'b00100111 - ,8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101110,8'b00101111 - ,8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110110,8'b00110111 - ,8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111110,8'b00111111 - - - ,8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000110,8'b10000111 - ,8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001110,8'b10001111 - ,8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010110,8'b10010111 - ,8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011110,8'b10011111 - , 8'b10100100,8'b10100101,8'b10100110,8'b10100111 - , 8'b10101100,8'b10101101,8'b10101110,8'b10101111 - , 8'b10110100,8'b10110101,8'b10110110,8'b10110111 - , 8'b10111100,8'b10111101,8'b10111110,8'b10111111 - ,8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000110,8'b11000111 - ,8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001110,8'b11001111 - ,8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010110,8'b11010111 - ,8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011110,8'b11011111 - ,8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100110,8'b11100111 - ,8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101110,8'b11101111 - ,8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110110,8'b11110111 - ,8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111110,8'b11111111 : - ; // NOP, undocumented - - 8'b01111110,8'b01111111 : - // NOP, undocumented - ; - */ - - // 8 BIT LOAD GROUP - 8'b01010111 : - begin - // LD A,I - Special_LD = 3'b100; - TStates = 3'b101; - end - - 8'b01011111 : - begin - // LD A,R - Special_LD = 3'b101; - TStates = 3'b101; - end - - 8'b01000111 : - begin - // LD I,A - Special_LD = 3'b110; - TStates = 3'b101; - end - - 8'b01001111 : - begin - // LD R,A - Special_LD = 3'b111; - TStates = 3'b101; - end - - // 16 BIT LOAD GROUP - 8'b01001011,8'b01011011,8'b01101011,8'b01111011 : - begin - // LD dd,(nn) - MCycles = 3'b101; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - LDZ = 1'b1; - end - - MCycle[2] : - begin - Set_Addr_To = aZI; - Inc_PC = 1'b1; - LDW = 1'b1; - end - - MCycle[3] : - begin - Read_To_Reg = 1'b1; - if (IR[5:4] == 2'b11 ) - begin - Set_BusA_To = 4'b1000; - end - else - begin - Set_BusA_To[2:1] = IR[5:4]; - Set_BusA_To[0] = 1'b1; - end - Inc_WZ = 1'b1; - Set_Addr_To = aZI; - end // case: 4 - - MCycle[4] : - begin - Read_To_Reg = 1'b1; - if (IR[5:4] == 2'b11 ) - begin - Set_BusA_To = 4'b1001; - end - else - begin - Set_BusA_To[2:1] = IR[5:4]; - Set_BusA_To[0] = 1'b0; - end - end // case: 5 - - default :; - endcase // case(MCycle) - end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011 - - - 8'b01000011,8'b01010011,8'b01100011,8'b01110011 : - begin - // LD (nn),dd - MCycles = 3'b101; - case (1'b1) // MCycle - MCycle[1] : - begin - Inc_PC = 1'b1; - LDZ = 1'b1; - end - - MCycle[2] : - begin - Set_Addr_To = aZI; - Inc_PC = 1'b1; - LDW = 1'b1; - if (IR[5:4] == 2'b11 ) - begin - Set_BusB_To = 4'b1000; - end - else - begin - Set_BusB_To[2:1] = IR[5:4]; - Set_BusB_To[0] = 1'b1; - Set_BusB_To[3] = 1'b0; - end - end // case: 3 - - MCycle[3] : - begin - Inc_WZ = 1'b1; - Set_Addr_To = aZI; - Write = 1'b1; - if (IR[5:4] == 2'b11 ) - begin - Set_BusB_To = 4'b1001; - end - else - begin - Set_BusB_To[2:1] = IR[5:4]; - Set_BusB_To[0] = 1'b0; - Set_BusB_To[3] = 1'b0; - end - end // case: 4 - - MCycle[4] : - begin - Write = 1'b1; - end - - default :; - endcase // case(MCycle) - end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011 - - 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 : - begin - // LDI, LDD, LDIR, LDDR - MCycles = 3'b100; - case (1'b1) // MCycle - MCycle[0] : - begin - Set_Addr_To = aXY; - IncDec_16 = 4'b1100; // BC - end - - MCycle[1] : - begin - Set_BusB_To = 4'b0110; - Set_BusA_To[2:0] = 3'b111; - ALU_Op = 4'b0000; - Set_Addr_To = aDE; - if (IR[3] == 1'b0 ) - begin - IncDec_16 = 4'b0110; // IX - end - else - begin - IncDec_16 = 4'b1110; - end - end // case: 2 - - MCycle[2] : - begin - I_BT = 1'b1; - TStates = 3'b101; - Write = 1'b1; - if (IR[3] == 1'b0 ) - begin - IncDec_16 = 4'b0101; // DE - end - else - begin - IncDec_16 = 4'b1101; - end - end // case: 3 - - MCycle[3] : - begin - NoRead = 1'b1; - TStates = 3'b101; - end - - default :; - endcase // case(MCycle) - end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 - - 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 : - begin - // CPI, CPD, CPIR, CPDR - MCycles = 3'b100; - case (1'b1) // MCycle - MCycle[0] : - begin - Set_Addr_To = aXY; - IncDec_16 = 4'b1100; // BC - end - - MCycle[1] : - begin - Set_BusB_To = 4'b0110; - Set_BusA_To[2:0] = 3'b111; - ALU_Op = 4'b0111; - Save_ALU = 1'b1; - PreserveC = 1'b1; - if (IR[3] == 1'b0 ) - begin - IncDec_16 = 4'b0110; - end - else - begin - IncDec_16 = 4'b1110; - end - end // case: 2 - - MCycle[2] : - begin - NoRead = 1'b1; - I_BC = 1'b1; - TStates = 3'b101; - end - - MCycle[3] : - begin - NoRead = 1'b1; - TStates = 3'b101; - end - - default :; - endcase // case(MCycle) - end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 - - 8'b01000100,8'b01001100,8'b01010100,8'b01011100,8'b01100100,8'b01101100,8'b01110100,8'b01111100 : - begin - // NEG - ALU_Op = 4'b0010; - Set_BusB_To = 4'b0111; - Set_BusA_To = 4'b1010; - Read_To_Acc = 1'b1; - Save_ALU = 1'b1; - end - - 8'b01000110,8'b01001110,8'b01100110,8'b01101110 : - begin - // IM 0 - IMode = 2'b00; - end - - 8'b01010110,8'b01110110 : - // IM 1 - IMode = 2'b01; - - 8'b01011110,8'b01110111 : - // IM 2 - IMode = 2'b10; - - // 16 bit arithmetic - 8'b01001010,8'b01011010,8'b01101010,8'b01111010 : - begin - // ADC HL,ss - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[1] : - begin - NoRead = 1'b1; - ALU_Op = 4'b0001; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - Set_BusA_To[2:0] = 3'b101; - case (IR[5:4]) - 0,1,2 : - begin - Set_BusB_To[2:1] = IR[5:4]; - Set_BusB_To[0] = 1'b1; - end - default : - Set_BusB_To = 4'b1000; - endcase - TStates = 3'b100; - end // case: 2 - - MCycle[2] : - begin - NoRead = 1'b1; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - ALU_Op = 4'b0001; - Set_BusA_To[2:0] = 3'b100; - case (IR[5:4]) - 0,1,2 : - begin - Set_BusB_To[2:1] = IR[5:4]; - Set_BusB_To[0] = 1'b0; - end - default : - Set_BusB_To = 4'b1001; - endcase // case(IR[5:4]) - end // case: 3 - - default :; - endcase // case(MCycle) - end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010 - - 8'b01000010,8'b01010010,8'b01100010,8'b01110010 : - begin - // SBC HL,ss - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[1] : - begin - NoRead = 1'b1; - ALU_Op = 4'b0011; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - Set_BusA_To[2:0] = 3'b101; - case (IR[5:4]) - 0,1,2 : - begin - Set_BusB_To[2:1] = IR[5:4]; - Set_BusB_To[0] = 1'b1; - end - default : - Set_BusB_To = 4'b1000; - endcase - TStates = 3'b100; - end // case: 2 - - MCycle[2] : - begin - NoRead = 1'b1; - ALU_Op = 4'b0011; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - Set_BusA_To[2:0] = 3'b100; - case (IR[5:4]) - 0,1,2 : - Set_BusB_To[2:1] = IR[5:4]; - default : - Set_BusB_To = 4'b1001; - endcase - end // case: 3 - - default :; - - endcase // case(MCycle) - end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010 - - 8'b01101111 : - begin - // RLD - MCycles = 3'b100; - case (1'b1) // MCycle - MCycle[1] : - begin - NoRead = 1'b1; - Set_Addr_To = aXY; - end - - MCycle[2] : - begin - Read_To_Reg = 1'b1; - Set_BusB_To[2:0] = 3'b110; - Set_BusA_To[2:0] = 3'b111; - ALU_Op = 4'b1101; - TStates = 3'b100; - Set_Addr_To = aXY; - Save_ALU = 1'b1; - end - - MCycle[3] : - begin - I_RLD = 1'b1; - Write = 1'b1; - end - - default :; - endcase // case(MCycle) - end // case: 8'b01101111 - - 8'b01100111 : - begin - // RRD - MCycles = 3'b100; - case (1'b1) // MCycle - MCycle[1] : - Set_Addr_To = aXY; - MCycle[2] : - begin - Read_To_Reg = 1'b1; - Set_BusB_To[2:0] = 3'b110; - Set_BusA_To[2:0] = 3'b111; - ALU_Op = 4'b1110; - TStates = 3'b100; - Set_Addr_To = aXY; - Save_ALU = 1'b1; - end - - MCycle[3] : - begin - I_RRD = 1'b1; - Write = 1'b1; - end - - default :; - endcase // case(MCycle) - end // case: 8'b01100111 - - 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 : - begin - // RETI, RETN - MCycles = 3'b011; - case (1'b1) // MCycle - MCycle[0] : - Set_Addr_To = aSP; - - MCycle[1] : - begin - IncDec_16 = 4'b0111; - Set_Addr_To = aSP; - LDZ = 1'b1; - end - - MCycle[2] : - begin - Jump = 1'b1; - IncDec_16 = 4'b0111; - I_RETN = 1'b1; - end - - default :; - endcase // case(MCycle) - end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 - - 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 : - begin - // IN r,(C) - MCycles = 3'b010; - case (1'b1) // MCycle - MCycle[0] : - Set_Addr_To = aBC; - - MCycle[1] : - begin - IORQ = 1'b1; - if (IR[5:3] != 3'b110 ) - begin - Read_To_Reg = 1'b1; - Set_BusA_To[2:0] = IR[5:3]; - end - I_INRC = 1'b1; - end - - default :; - endcase // case(MCycle) - end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 - - 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 : - begin - // OUT (C),r - // OUT (C),0 - MCycles = 3'b010; - case (1'b1) // MCycle - MCycle[0] : - begin - Set_Addr_To = aBC; - Set_BusB_To[2:0] = IR[5:3]; - if (IR[5:3] == 3'b110 ) - begin - Set_BusB_To[3] = 1'b1; - end - end - - MCycle[1] : - begin - Write = 1'b1; - IORQ = 1'b1; - end - - default :; - endcase // case(MCycle) - end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 - - 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 : - begin - // INI, IND, INIR, INDR - MCycles = 3'b100; - case (1'b1) // MCycle - MCycle[0] : - begin - Set_Addr_To = aBC; - Set_BusB_To = 4'b1010; - Set_BusA_To = 4'b0000; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - ALU_Op = 4'b0010; - end - - MCycle[1] : - begin - IORQ = 1'b1; - Set_BusB_To = 4'b0110; - Set_Addr_To = aXY; - end - - MCycle[2] : - begin - if (IR[3] == 1'b0 ) - begin - IncDec_16 = 4'b0110; - end - else - begin - IncDec_16 = 4'b1110; - end - TStates = 3'b100; - Write = 1'b1; - I_BTR = 1'b1; - end // case: 3 - - MCycle[3] : - begin - NoRead = 1'b1; - TStates = 3'b101; - end - - default :; - endcase // case(MCycle) - end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 - - 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 : - begin - // OUTI, OUTD, OTIR, OTDR - MCycles = 3'b100; - case (1'b1) // MCycle - MCycle[0] : - begin - TStates = 3'b101; - Set_Addr_To = aXY; - Set_BusB_To = 4'b1010; - Set_BusA_To = 4'b0000; - Read_To_Reg = 1'b1; - Save_ALU = 1'b1; - ALU_Op = 4'b0010; - end - - MCycle[1] : - begin - Set_BusB_To = 4'b0110; - Set_Addr_To = aBC; - if (IR[3] == 1'b0 ) - begin - IncDec_16 = 4'b0110; - end - else - begin - IncDec_16 = 4'b1110; - end - end - - MCycle[2] : - begin - if (IR[3] == 1'b0 ) - begin - IncDec_16 = 4'b0010; - end - else - begin - IncDec_16 = 4'b1010; - end - IORQ = 1'b1; - Write = 1'b1; - I_BTR = 1'b1; - end // case: 3 - - MCycle[3] : - begin - NoRead = 1'b1; - TStates = 3'b101; - end - - default :; - endcase // case(MCycle) - end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 - - default : ; - - endcase // case(IR) - end // block: default_ed_block - endcase // case(ISet) - - if (Mode == 1 ) - begin - if (MCycle[0] ) - begin - //TStates = 3'b100; - end - else - begin - TStates = 3'b011; - end - end - - if (Mode == 3 ) - begin - if (MCycle[0] ) - begin - //TStates = 3'b100; - end - else - begin - TStates = 3'b100; - end - end - - if (Mode < 2 ) - begin - if (MCycle[5] ) - begin - Inc_PC = 1'b1; - if (Mode == 1 ) - begin - Set_Addr_To = aXY; - TStates = 3'b100; - Set_BusB_To[2:0] = SSS; - Set_BusB_To[3] = 1'b0; - end - if (IR == 8'b00110110 || IR == 8'b11001011 ) - begin - Set_Addr_To = aNone; - end - end - if (MCycle[6] ) - begin - if (Mode == 0 ) - begin - TStates = 3'b101; - end - if (ISet != 2'b01 ) - begin - Set_Addr_To = aXY; - end - Set_BusB_To[2:0] = SSS; - Set_BusB_To[3] = 1'b0; - if (IR == 8'b00110110 || ISet == 2'b01 ) - begin - // LD (HL),n - Inc_PC = 1'b1; - end - else - begin - NoRead = 1'b1; - end - end - end // if (Mode < 2 ) - - end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle) -endmodule // T80_MCode diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/tv80/tv80_reg.v b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/tv80/tv80_reg.v deleted file mode 100644 index 889766cf..00000000 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/tv80/tv80_reg.v +++ /dev/null @@ -1,77 +0,0 @@ -// -// TV80 8-Bit Microprocessor Core -// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) -// -// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) -// -// Permission is hereby granted, free of charge, to any person obtaining a -// copy of this software and associated documentation files (the "Software"), -// to deal in the Software without restriction, including without limitation -// the rights to use, copy, modify, merge, publish, distribute, sublicense, -// and/or sell copies of the Software, and to permit persons to whom the -// Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included -// in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -module tv80_reg (/*AUTOARG*/ - // Outputs - DOBH, DOAL, DOCL, DOBL, DOCH, DOAH, - // Inputs - AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL - ); - input [2:0] AddrC; - output [7:0] DOBH; - input [2:0] AddrA; - input [2:0] AddrB; - input [7:0] DIH; - output [7:0] DOAL; - output [7:0] DOCL; - input [7:0] DIL; - output [7:0] DOBL; - output [7:0] DOCH; - output [7:0] DOAH; - input clk, CEN, WEH, WEL; - - reg [7:0] RegsH [0:7]; - reg [7:0] RegsL [0:7]; - - always @(posedge clk) - begin - if (CEN) - begin - if (WEH) RegsH[AddrA] <= DIH; - if (WEL) RegsL[AddrA] <= DIL; - end - end - - assign DOAH = RegsH[AddrA]; - assign DOAL = RegsL[AddrA]; - assign DOBH = RegsH[AddrB]; - assign DOBL = RegsL[AddrB]; - assign DOCH = RegsH[AddrC]; - assign DOCL = RegsL[AddrC]; - - // break out ram bits for waveform debug -// synopsys translate_off - wire [7:0] B = RegsH[0]; - wire [7:0] C = RegsL[0]; - wire [7:0] D = RegsH[1]; - wire [7:0] E = RegsL[1]; - wire [7:0] H = RegsH[2]; - wire [7:0] L = RegsL[2]; - - wire [15:0] IX = { RegsH[3], RegsL[3] }; - wire [15:0] IY = { RegsH[7], RegsL[7] }; -// synopsys translate_on - -endmodule - diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/video_mixer.sv b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/video_mixer.sv deleted file mode 100644 index 126ca276..00000000 --- a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 768, - parameter HALF_DEPTH = 0, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/Midway MCR 1/Kickman_MiST/Kickman.qsf b/Arcade_MiST/Midway MCR 1/Kickman_MiST/Kickman.qsf index 79ab876a..f6ff2706 100644 --- a/Arcade_MiST/Midway MCR 1/Kickman_MiST/Kickman.qsf +++ b/Arcade_MiST/Midway MCR 1/Kickman_MiST/Kickman.qsf @@ -41,7 +41,7 @@ # ======================== set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" # Pin & Location Assignments diff --git a/Arcade_MiST/Midway MCR 1/Kickman_MiST/rtl/Kickman_MiST.sv b/Arcade_MiST/Midway MCR 1/Kickman_MiST/rtl/Kickman_MiST.sv index 11c3852d..f84ce6b4 100644 --- a/Arcade_MiST/Midway MCR 1/Kickman_MiST/rtl/Kickman_MiST.sv +++ b/Arcade_MiST/Midway MCR 1/Kickman_MiST/rtl/Kickman_MiST.sv @@ -53,7 +53,7 @@ localparam CONF_STR = { "O5,Blend,Off,On;", "O6,Service,Off,On;", "T0,Reset;", - "V,v1.0.",`BUILD_DATE + "V,v1.1.",`BUILD_DATE }; wire rotate = status[2]; diff --git a/Arcade_MiST/Midway MCR 1/SolarFox_MiST/SolarFox.qsf b/Arcade_MiST/Midway MCR 1/SolarFox_MiST/SolarFox.qsf index 603df671..aa3b3b42 100644 --- a/Arcade_MiST/Midway MCR 1/SolarFox_MiST/SolarFox.qsf +++ b/Arcade_MiST/Midway MCR 1/SolarFox_MiST/SolarFox.qsf @@ -41,7 +41,7 @@ # ======================== set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" # Pin & Location Assignments diff --git a/Arcade_MiST/Midway MCR 1/SolarFox_MiST/rtl/pll_mist.qip b/Arcade_MiST/Midway MCR 1/SolarFox_MiST/rtl/pll_mist.qip deleted file mode 100644 index d4720390..00000000 --- a/Arcade_MiST/Midway MCR 1/SolarFox_MiST/rtl/pll_mist.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"] diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/ReadMe.txt b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/ReadMe.txt deleted file mode 100644 index 2265b0dd..00000000 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/ReadMe.txt +++ /dev/null @@ -1,36 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Defender port to MiST by Gehstock --- 11 June 2019 --- ---------------------------------------------------------------------------------- --- A simulation model of Williams 6809 hardware --- by Dar (darfpga@aol.fr) --- http://darfpga.blogspot.fr - ---------------------------------------------------------------------------------- --- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- Fire = Fire or Space --- Thrust = Fire2 or ALT --- Smart Bomb = Fire3 or CTRL --- Hyperspace = Fire4 or 1 --- Change Direction = Left or Right --- Up = Up --- Down = Down - --- Advance = A --- Auto up = U --- Score_reset = H --- --- Joystick support. --- ---------------------------------------------------------------------------------- - - -DEFENDER.ROM is required at the root of the SD-Card. - diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/pll_mist.qip b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/pll_mist.qip deleted file mode 100644 index d4720390..00000000 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/pll_mist.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"] diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/ReadMe.txt b/Arcade_MiST/Williams 6809 rev.1 Hardware/ReadMe.txt index 4e297083..2265b0dd 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/ReadMe.txt +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/ReadMe.txt @@ -1,13 +1,36 @@ -Games that should work on this Hardware +--------------------------------------------------------------------------------- +-- +-- Arcade: Defender port to MiST by Gehstock +-- 11 June 2019 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Williams 6809 hardware +-- by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr + +--------------------------------------------------------------------------------- +-- +-- Only controls and OSD are rotated on Video output. +-- +-- +-- Keyboard inputs : +-- +-- Fire = Fire or Space +-- Thrust = Fire2 or ALT +-- Smart Bomb = Fire3 or CTRL +-- Hyperspace = Fire4 or 1 +-- Change Direction = Left or Right +-- Up = Up +-- Down = Down + +-- Advance = A +-- Auto up = U +-- Score_reset = H +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- + + +DEFENDER.ROM is required at the root of the SD-Card. -Alien Arena -Blaster -Bubbles -Joust -Lotto Fun -Playball! -Robotron -Sinistar -Speed Ball -Splat! -Stargate \ No newline at end of file diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.qpf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Williams6809rev1_MiST.qpf similarity index 96% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.qpf rename to Arcade_MiST/Williams 6809 rev.1 Hardware/Williams6809rev1_MiST.qpf index 020bef32..1d8ef194 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.qpf +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Williams6809rev1_MiST.qpf @@ -28,4 +28,4 @@ DATE = "04:04:47 October 16, 2017" # Revisions -PROJECT_REVISION = "Defender_MiST" +PROJECT_REVISION = "Williams6809rev1_MiST" diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.qsf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Williams6809rev1_MiST.qsf similarity index 96% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.qsf rename to Arcade_MiST/Williams 6809 rev.1 Hardware/Williams6809rev1_MiST.qsf index 2c8cbc60..7c26700a 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.qsf +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Williams6809rev1_MiST.qsf @@ -25,7 +25,7 @@ # Notes: # # 1) The default values for assignments are stored in the file: -# Defender_MiST_assignment_defaults.qdf +# Williams6809rev1_MiST_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # @@ -43,7 +43,7 @@ set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:22:13 JUNE 04, 2019" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name SMART_RECOMPILE ON # Pin & Location Assignments @@ -171,26 +171,9 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # Pin & Location Assignments # ========================== -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_* -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO # start DESIGN_PARTITION(Top) @@ -198,9 +181,6 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO # Incremental Compilation Assignments # =================================== -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- @@ -218,7 +198,27 @@ set_global_assignment -name QIP_FILE rtl/pll_mist.qip set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv set_global_assignment -name VHDL_FILE rtl/dpram.vhd set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd -set_global_assignment -name VHDL_FILE ../../../common/IO/pia6821.vhd -set_global_assignment -name VHDL_FILE ../../../common/CPU/MC6809/cpu09l_128a.vhd -set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip +set_global_assignment -name VHDL_FILE ../../common/IO/pia6821.vhd +set_global_assignment -name VHDL_FILE ../../common/CPU/MC6809/cpu09l_128a.vhd +set_global_assignment -name QIP_FILE ../../common/mist/mist.qip +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_* +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.sdc b/Arcade_MiST/Williams 6809 rev.1 Hardware/Williams6809rev1_MiST.sdc similarity index 100% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.sdc rename to Arcade_MiST/Williams 6809 rev.1 Hardware/Williams6809rev1_MiST.sdc diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/clean.bat b/Arcade_MiST/Williams 6809 rev.1 Hardware/clean.bat similarity index 100% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/clean.bat rename to Arcade_MiST/Williams 6809 rev.1 Hardware/clean.bat diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/Defender_MiST.sv b/Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/Defender_MiST.sv similarity index 100% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/Defender_MiST.sv rename to Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/Defender_MiST.sv diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/build_id.tcl b/Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/build_id.tcl similarity index 100% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/build_id.tcl rename to Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/build_id.tcl diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/cpu68.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/cpu68.vhd similarity index 100% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/cpu68.vhd rename to Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/cpu68.vhd diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/dac.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/dac.vhd similarity index 100% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/dac.vhd rename to Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/dac.vhd diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/defender.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/defender.vhd similarity index 100% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/defender.vhd rename to Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/defender.vhd diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/defender_cmos_ram.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/defender_cmos_ram.vhd similarity index 100% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/defender_cmos_ram.vhd rename to Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/defender_cmos_ram.vhd diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/defender_sound_board.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/defender_sound_board.vhd similarity index 100% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/defender_sound_board.vhd rename to Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/defender_sound_board.vhd diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/dpram.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/dpram.vhd similarity index 100% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/dpram.vhd rename to Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/dpram.vhd diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/gen_ram.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/gen_ram.vhd similarity index 100% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/gen_ram.vhd rename to Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/gen_ram.vhd diff --git a/Arcade_MiST/Midway MCR 1/Kickman_MiST/rtl/pll_mist.qip b/Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/pll_mist.qip similarity index 100% rename from Arcade_MiST/Midway MCR 1/Kickman_MiST/rtl/pll_mist.qip rename to Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/pll_mist.qip diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/pll_mist.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/pll_mist.vhd similarity index 100% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/pll_mist.vhd rename to Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/pll_mist.vhd diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/sdram.sv b/Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/sdram.sv similarity index 100% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/sdram.sv rename to Arcade_MiST/Williams 6809 rev.1 Hardware/rtl/sdram.sv