diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qpf new file mode 100644 index 00000000..7fbf41ef --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qpf @@ -0,0 +1,29 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 11:56:24 October 19, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "11:56:24 October 19, 2019" + +# Revisions +PROJECT_REVISION = "DevilFish" diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qsf new file mode 100644 index 00000000..c82d8975 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qsf @@ -0,0 +1,185 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 11:54:39 October 19, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# MoonCresta_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/DevilFish.sv +set_global_assignment -name VHDL_FILE rtl/galaxian.vhd +set_global_assignment -name VHDL_FILE rtl/mc_video.vhd +set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd +set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd +set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd +set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd +set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd +set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd +set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd +set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd +set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd +set_global_assignment -name VHDL_FILE rtl/sine_package.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name TOP_LEVEL_ENTITY DevilFish + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ----------------------- +# start ENTITY(DevilFish) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(DevilFish) +# --------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/README.txt new file mode 100644 index 00000000..846fd542 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/README.txt @@ -0,0 +1,24 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Moon Cresta port to MiST by Gehstock +-- 18 December 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Galaxian hardware +-- Copyright(c) 2004 Katsumi Degawa +--------------------------------------------------------------------------------- +-- +-- Only controls and OSD are rotated on Video output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F1 : Start 1 player +-- F2 : Start 2 player +-- SPACE : Fire +-- ARROW KEYS : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/Release/DevilFish.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/Release/DevilFish.rbf new file mode 100644 index 00000000..32c078c0 Binary files /dev/null and b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/Release/DevilFish.rbf differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/DevilFish.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/DevilFish.sv new file mode 100644 index 00000000..4099ec89 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/DevilFish.sv @@ -0,0 +1,187 @@ +//============================================================================ +// Arcade: Devil Fish +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module DevilFish( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "DevilFish;;", + "O2,Rotate Controls,Off,On;", + "O34,Scanlines,Off,25%,50%,75%;", + "T6,Reset;", + "V,v1.20.",`BUILD_DATE +}; + +assign LED = 1; +assign AUDIO_R = AUDIO_L; + +wire clk_24, clk_18, clk_12, clk_6; +wire pll_locked; +pll pll( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_24), + .c1(clk_18), + .c2(clk_12), + .c3(clk_6) + ); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire [7:0] audio_a, audio_b; +wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; +wire hs, vs; +wire hb, vb; +wire blankn = ~(hb | vb); +wire [2:0] r,g,b; + +galaxian devilfish( + .W_CLK_18M(clk_18), + .W_CLK_12M(clk_12), + .W_CLK_6M(clk_6), + .I_RESET(status[0] | status[6] | buttons[1]), + .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}), + .P2_CSJUDLR({1'b0,btn_two_players,m_fire,m_up,m_down,m_left,m_right}), + .W_R(r), + .W_G(g), + .W_B(b), + .W_H_SYNC(hs), + .W_V_SYNC(vs), + .HBLANK(hb), + .VBLANK(vb), + .W_SDAT_A(audio_a), + .W_SDAT_B(audio_b) + ); + +mist_video #(.COLOR_DEPTH(3)) mist_video( + .clk_sys(clk_24), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn ? r : 0), + .G(blankn ? g : 0), + .B(blankn ? b : 0), + .HSync(~hs), + .VSync(~vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .rotate({1'b0,status[2]}), +// .ce_devide(1), + .scandoubler_disable(scandoublerD), + .scanlines(status[4:3]), + .ypbpr(ypbpr) + ); + +user_io #( + .STRLEN(($size(CONF_STR)>>3))) +user_io( + .clk_sys (clk_24 ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac #( + .C_bits(11)) +dac( + .clk_i(clk_24), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +// Rotated Normal +wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; +wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; +wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; +wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; +wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; +//wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; + +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +//reg btn_fire2 = 0; +//reg btn_fire3 = 0; +reg btn_coin = 0; +wire key_pressed; +wire [7:0] key_code; +wire key_strobe; + +always @(posedge clk_24) begin + if(key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 +// 'h14: btn_fire3 <= key_pressed; // ctrl +// 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1H.vhd new file mode 100644 index 00000000..9a0ffdb7 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1H.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_1H is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_1H is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + 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Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1K.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_1K is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_1K is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"0E",X"3F",X"7F",X"73",X"E3",X"E3",X"00",X"00",X"00",X"80",X"E0",X"E0",X"F0",X"F0", + X"E0",X"E0",X"70",X"7F",X"3F",X"0E",X"00",X"00",X"F0",X"F0",X"E0",X"E0",X"80",X"00",X"00",X"00", + X"00",X"00",X"0E",X"3F",X"7F",X"70",X"E0",X"E0",X"00",X"00",X"00",X"80",X"E0",X"E0",X"70",X"70", + X"E3",X"E3",X"7F",X"7F",X"3F",X"0E",X"00",X"00",X"F0",X"F0",X"E0",X"E0",X"80",X"00",X"00",X"00", + X"00",X"00",X"0E",X"3F",X"7F",X"70",X"F0",X"F0",X"00",X"00",X"00",X"80",X"E0",X"E0",X"70",X"70", + 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"2F",X"7F",X"6F",X"EF",X"EF",X"F7"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_6L.vhd new file mode 100644 index 00000000..7432acf2 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_6L.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_6L is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_6L is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"17",X"C7",X"F6",X"00",X"17",X"C0",X"3F",X"00",X"07",X"C0",X"3F",X"00",X"C0",X"C4",X"07", + X"00",X"C7",X"31",X"17",X"00",X"31",X"C7",X"3F",X"00",X"F6",X"07",X"F0",X"00",X"3F",X"07",X"C4"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_FIR.vhd new file mode 100644 index 00000000..5aff2022 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_FIR.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_FIR is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_FIR is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal 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X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E", + X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82", + X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_HIT.vhd new file mode 100644 index 00000000..7d2fd29c --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_HIT.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_HIT is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_HIT is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", + X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", + X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", + X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", + X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", + X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", + X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", + X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70", + 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in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AF",X"32",X"01",X"70",X"C3",X"8E",X"00",X"FF",X"C3",X"73",X"00",X"FF",X"FF",X"FF",X"FF",X"FF", + X"77",X"23",X"10",X"FC",X"C9",X"FF",X"FF",X"FF",X"11",X"20",X"00",X"77",X"19",X"10",X"FC",X"C9", + X"85",X"6F",X"3E",X"00",X"8C",X"67",X"7E",X"C9",X"87",X"E1",X"D5",X"5F",X"16",X"00",X"19",X"5E", + X"23",X"56",X"EB",X"D1",X"E9",X"FF",X"FF",X"FF",X"00",X"00",X"C3",X"B7",X"01",X"3A",X"0E",X"41", + X"21",X"02",X"40",X"86",X"23",X"86",X"5F",X"23",X"7E",X"41",X"00",X"00",X"00",X"CD",X"87",X"10", + X"CD",X"50",X"0C",X"00",X"00",X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"21",X"E6",X"43",X"DD",X"7E",X"01",X"77",X"E6",X"0F",X"E7", + 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X"2E",X"2E",X"10",X"10",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"10",X"10",X"2A",X"2A",X"2A",X"FF", + X"4E",X"50",X"2A",X"10",X"10",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"10",X"10",X"2E",X"10",X"10", + X"10",X"10",X"2E",X"10",X"10",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"10",X"10",X"2A",X"FF",X"4F", + X"50",X"2A",X"10",X"10",X"10",X"10",X"10",X"10",X"2A",X"2A",X"10",X"10",X"2E",X"10",X"10",X"10", + X"10",X"2E",X"10",X"10",X"2A",X"2A",X"10",X"10",X"10",X"31",X"10",X"10",X"2A",X"FF",X"50",X"50", + X"2A",X"10",X"10",X"10",X"10",X"10",X"10",X"2A",X"2A",X"10",X"10",X"2E",X"10",X"10",X"10",X"10", + X"2E",X"10",X"10",X"2A",X"2A",X"10",X"10",X"10",X"10",X"10",X"10",X"2A",X"FF",X"51",X"50",X"2A", + X"33",X"10",X"2A",X"2A",X"10",X"10",X"2A",X"2A",X"10",X"10",X"2E",X"10",X"10",X"10",X"10",X"2E", + X"10",X"10",X"2A",X"2A",X"10",X"10",X"2A",X"2A",X"10",X"10",X"2A",X"FF",X"12",X"50",X"2A",X"2A", + X"2A",X"10",X"10",X"2A",X"2A",X"10",X"10",X"2A",X"2A",X"10",X"10",X"2E",X"2E",X"2E",X"2E",X"2E", + X"2E",X"10",X"10",X"2A",X"2A",X"33",X"10",X"2A",X"2A",X"10",X"10",X"2A",X"2A",X"2A",X"FF",X"13", + X"50",X"10",X"10",X"10",X"10",X"10",X"2A",X"2A",X"10",X"10",X"2A",X"2A",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"2A",X"2A",X"10",X"10",X"2A",X"2A",X"10",X"10",X"10",X"10", + X"10",X"FF",X"14",X"50",X"10",X"10",X"10",X"10",X"10",X"2A",X"2A",X"10",X"10",X"31",X"10",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"2A",X"2A",X"10", + X"10",X"10",X"10",X"10",X"FF",X"15",X"50",X"2A",X"2A",X"2A",X"10",X"10",X"2A",X"2A",X"10",X"10", + X"10",X"10",X"10",X"10",X"2A",X"2A",X"10",X"10",X"2A",X"2A",X"10",X"10",X"10",X"10",X"10",X"10", + X"2A",X"2A",X"10",X"10",X"2A",X"2A",X"2A",X"FF",X"56",X"50",X"2A",X"10",X"10",X"2A",X"2A",X"2A", + X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"10",X"10",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A", + X"2A",X"2A",X"2A",X"10",X"10",X"2A",X"FF",X"57",X"50",X"2A",X"10",X"10",X"2A",X"2A",X"2A",X"2A", + X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"10",X"10",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A", + X"2A",X"2A",X"10",X"10",X"2A",X"FF",X"58",X"50",X"2A",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"31",X"10",X"10",X"10", + X"10",X"10",X"10",X"2A",X"FF",X"59",X"50",X"2A",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"2A",X"FF",X"5A",X"50",X"2A",X"10",X"10",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A", + X"2A",X"10",X"10",X"2A",X"2A",X"10",X"10",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"33", + X"10",X"2A",X"FF",X"5B",X"50",X"2A",X"10",X"10",X"10",X"10",X"10",X"10",X"31",X"10",X"10",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + X"2A",X"FF",X"5C",X"50",X"2A",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"2A", + X"FF",X"5D",X"50",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A", + X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"2A",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..c07d2629 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1093 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..6bd576cf --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..ee217402 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,2026 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..679730ab --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80as.vhd new file mode 100644 index 00000000..fe477f50 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80as.vhd @@ -0,0 +1,283 @@ +------------------------------------------------------------------------------ +-- t80as.vhd : The non-tristate signal edition of t80a.vhd +-- +-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh +-- +-- 1.separate 'D' to 'DO' and 'DI'. +-- 2.added 'DOE' to 'DO' enable signal.(data direction) +-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. +-- +-- There is a mark of "--AS" in all the change points. +-- +------------------------------------------------------------------------------ + +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80as is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); +--AS-- D : inout std_logic_vector(7 downto 0) +--AS>> + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + DOE : out std_logic +--< 'Z'); +--AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); +--AS>> + MREQ_n <= MREQ_n_i; + IORQ_n <= IORQ_n_i; + RD_n <= RD_n_i; + WR_n <= WR_n_i; + RFSH_n <= RFSH_n_i; + A <= A_i; + DOE <= Write when BUSAK_n_i = '1' else '0'; +--< Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, +-- DInst => D, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then +--AS-- DI_Reg <= to_x01(D); +--AS>> + DI_Reg <= to_x01(DI); +--< 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..dafe8385 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/galaxian.vhd new file mode 100644 index 00000000..05956ffa --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/galaxian.vhd @@ -0,0 +1,452 @@ +------------------------------------------------------------------------------ +-- FPGA GALAXIAN +-- +-- Version downto 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important not +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +-- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--use work.pkg_galaxian.all; + +entity galaxian is + port( + W_CLK_18M : in std_logic; + W_CLK_12M : in std_logic; + W_CLK_6M : in std_logic; + + P1_CSJUDLR : in std_logic_vector(6 downto 0); + P2_CSJUDLR : in std_logic_vector(6 downto 0); + I_RESET : in std_logic; + + W_R : out std_logic_vector(2 downto 0); + W_G : out std_logic_vector(2 downto 0); + W_B : out std_logic_vector(2 downto 0); + HBLANK : out std_logic; + VBLANK : out std_logic; + W_H_SYNC : out std_logic; + W_V_SYNC : out std_logic; + W_SDAT_A : out std_logic_vector( 7 downto 0); + W_SDAT_B : out std_logic_vector( 7 downto 0); + O_CMPBL : out std_logic + ); +end; + +architecture RTL of galaxian is + -- CPU ADDRESS BUS + signal W_A : std_logic_vector(15 downto 0) := (others => '0'); + -- CPU IF + signal W_CPU_CLK : std_logic := '0'; + signal W_CPU_MREQn : std_logic := '0'; + signal W_CPU_NMIn : std_logic := '0'; + signal W_CPU_RDn : std_logic := '0'; + signal W_CPU_RFSHn : std_logic := '0'; + signal W_CPU_WAITn : std_logic := '0'; + signal W_CPU_WRn : std_logic := '0'; + signal W_CPU_WR : std_logic := '0'; + signal W_RESETn : std_logic := '0'; + -------- H and V COUNTER ------------------------- + signal W_C_BLn : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_C_BLXn : std_logic := '0'; + signal W_H_BL : std_logic := '0'; + signal W_H_SYNC_int : std_logic := '0'; + signal W_V_BLn : std_logic := '0'; + signal W_V_BL2n : std_logic := '0'; + signal W_V_SYNC_int : std_logic := '0'; + signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); + -------- CPU RAM ---------------------------- + signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); + -------- ADDRESS DECDER ---------------------- + signal W_BD_G : std_logic := '0'; + signal W_CPU_RAM_CS : std_logic := '0'; + signal W_CPU_RAM_RD : std_logic := '0'; +-- signal W_CPU_RAM_WR : std_logic := '0'; + signal W_CPU_ROM_CS : std_logic := '0'; + signal W_DIP_OE : std_logic := '0'; + signal W_H_FLIP : std_logic := '0'; + signal W_DRIVER_WE : std_logic := '0'; + signal W_OBJ_RAM_RD : std_logic := '0'; + signal W_OBJ_RAM_RQ : std_logic := '0'; + signal W_OBJ_RAM_WR : std_logic := '0'; + signal W_PITCH : std_logic := '0'; + signal W_SOUND_WE : std_logic := '0'; + signal W_STARS_ON : std_logic := '0'; + signal W_STARS_OFFn : std_logic := '0'; + signal W_SW0_OE : std_logic := '0'; + signal W_SW1_OE : std_logic := '0'; + signal W_V_FLIP : std_logic := '0'; + signal W_VID_RAM_RD : std_logic := '0'; + signal W_VID_RAM_WR : std_logic := '0'; + signal W_WDR_OE : std_logic := '0'; + --------- INPORT ----------------------------- + signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); + --------- VIDEO ----------------------------- + signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); + ----- DATA I/F ------------------------------------- + signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_RAM_CLK : std_logic := '0'; + signal W_VOL1 : std_logic := '0'; + signal W_VOL2 : std_logic := '0'; + signal W_FIRE : std_logic := '0'; + signal W_HIT : std_logic := '0'; + signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); + + signal blx_comb : std_logic := '0'; + signal W_1VF : std_logic := '0'; + signal W_256HnX : std_logic := '0'; + signal W_8HF : std_logic := '0'; + signal W_DAC_A : std_logic := '0'; + signal W_DAC_B : std_logic := '0'; + signal W_MISSILEn : std_logic := '0'; + signal W_SHELLn : std_logic := '0'; + signal W_MS_D : std_logic := '0'; + signal W_MS_R : std_logic := '0'; + signal W_MS_G : std_logic := '0'; + signal W_MS_B : std_logic := '0'; + + signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); + signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); + signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); + +begin + mc_vid : entity work.MC_VIDEO + port map( + I_CLK_18M => W_CLK_18M, + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT => W_H_CNT, + I_V_CNT => W_V_CNT, + I_H_FLIP => W_H_FLIP, + I_V_FLIP => W_V_FLIP, + I_V_BLn => W_V_BLn, + I_C_BLn => W_C_BLn, + I_A => W_A(9 downto 0), + I_OBJ_SUB_A => "000", + I_BD => W_BDI, + I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + I_OBJ_RAM_RD => W_OBJ_RAM_RD, + I_OBJ_RAM_WR => W_OBJ_RAM_WR, + I_VID_RAM_RD => W_VID_RAM_RD, + I_VID_RAM_WR => W_VID_RAM_WR, + I_DRIVER_WR => W_DRIVER_WE, + O_C_BLnX => W_C_BLnX, + O_8HF => W_8HF, + O_256HnX => W_256HnX, + O_1VF => W_1VF, + O_MISSILEn => W_MISSILEn, + O_SHELLn => W_SHELLn, + O_BD => W_VID_DO, + O_VID => W_VID, + O_COL => W_COL + ); + + cpu : entity work.T80as + port map ( + RESET_n => W_RESETn, + CLK_n => W_CPU_CLK, + WAIT_n => W_CPU_WAITn, + INT_n => W_CPU_NMIn, + NMI_n => '1', + BUSRQ_n => '1', + MREQ_n => W_CPU_MREQn, + RD_n => W_CPU_RDn, + WR_n => W_CPU_WRn, + RFSH_n => W_CPU_RFSHn, + A => W_A, + DI => W_BDO, + DO => W_BDI, + M1_n => open, + IORQ_n => open, + HALT_n => open, + BUSAK_n => open, + DOE => open + ); + + mc_cpu_ram : entity work.MC_CPU_RAM + port map ( + I_CLK => W_CPU_RAM_CLK, + I_ADDR => W_A(10 downto 0), + I_D => W_BDI, + I_WE => W_CPU_WR, + I_OE => W_CPU_RAM_RD, + O_D => W_CPU_RAM_DO + ); + + mc_adec : entity work.MC_ADEC + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_CPU_CLK => W_CPU_CLK, + I_RSTn => W_RESETn, + + I_CPU_A => W_A, + I_CPU_D => W_BDI(0), + I_MREQn => W_CPU_MREQn, + I_RFSHn => W_CPU_RFSHn, + I_RDn => W_CPU_RDn, + I_WRn => W_CPU_WRn, + I_H_BL => W_H_BL, + I_V_BLn => W_V_BLn, + + O_WAITn => W_CPU_WAITn, + O_NMIn => W_CPU_NMIn, + O_CPU_ROM_CS => W_CPU_ROM_CS, + O_CPU_RAM_RD => W_CPU_RAM_RD, +-- O_CPU_RAM_WR => W_CPU_RAM_WR, + O_CPU_RAM_CS => W_CPU_RAM_CS, + O_OBJ_RAM_RD => W_OBJ_RAM_RD, + O_OBJ_RAM_WR => W_OBJ_RAM_WR, + O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + O_VID_RAM_RD => W_VID_RAM_RD, + O_VID_RAM_WR => W_VID_RAM_WR, + O_SW0_OE => W_SW0_OE, + O_SW1_OE => W_SW1_OE, + O_DIP_OE => W_DIP_OE, + O_WDR_OE => W_WDR_OE, + O_DRIVER_WE => W_DRIVER_WE, + O_SOUND_WE => W_SOUND_WE, + O_PITCH => W_PITCH, + O_H_FLIP => W_H_FLIP, + O_V_FLIP => W_V_FLIP, + O_BD_G => W_BD_G, + O_STARS_ON => W_STARS_ON + ); + + -- active high buttons + mc_inport : entity work.MC_INPORT + port map ( + I_COIN1 => P1_CSJUDLR(6), + I_COIN2 => P2_CSJUDLR(6), + I_1P_START => P1_CSJUDLR(5), + I_2P_START => P2_CSJUDLR(5), + I_1P_SH => P1_CSJUDLR(4), + I_2P_SH => P2_CSJUDLR(4), + + I_1P_UP => P1_CSJUDLR(3), + I_2P_UP => P2_CSJUDLR(3), + I_1P_DN => P1_CSJUDLR(2), + I_2P_DN => P2_CSJUDLR(2), + + I_1P_LE => P1_CSJUDLR(1), + I_2P_LE => P2_CSJUDLR(1), + I_1P_RI => P1_CSJUDLR(0), + I_2P_RI => P2_CSJUDLR(0), + I_SW0_OE => W_SW0_OE, + I_SW1_OE => W_SW1_OE, + I_DIP_OE => W_DIP_OE, + O_D => W_SW_DO + ); + + mc_hv : entity work.MC_HV_COUNT + port map( + I_CLK => W_CLK_6M, + I_RSTn => W_RESETn, + O_H_CNT => W_H_CNT, + O_H_SYNC => W_H_SYNC_int, + O_H_BL => W_H_BL, + O_V_CNT => W_V_CNT, + O_V_SYNC => W_V_SYNC_int, + O_V_BL2n => W_V_BL2n, + O_V_BLn => W_V_BLn, + O_C_BLn => W_C_BLn + ); + + mc_col_pal : entity work.MC_COL_PAL + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_VID => W_VID, + I_COL => W_COL, + I_C_BLnX => W_C_BLnX, + O_C_BLXn => W_C_BLXn, + O_STARS_OFFn => W_STARS_OFFn, + O_R => W_VIDEO_R, + O_G => W_VIDEO_G, + O_B => W_VIDEO_B + ); + + mc_stars : entity work.MC_STARS + port map ( + I_CLK_18M => W_CLK_18M, + I_CLK_6M => W_CLK_6M, + I_H_FLIP => W_H_FLIP, + I_V_SYNC => W_V_SYNC_int, + I_8HF => W_8HF, + I_256HnX => W_256HnX, + I_1VF => W_1VF, + I_2V => W_V_CNT(1), + I_STARS_ON => W_STARS_ON, + I_STARS_OFFn => W_STARS_OFFn, + O_R => W_STARS_R, + O_G => W_STARS_G, + O_B => W_STARS_B, + O_NOISE => open + ); + + mc_sound_a : entity work.MC_SOUND_A + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT1 => W_H_CNT(1), + I_BD => W_BDI, + I_PITCH => W_PITCH, + I_VOL1 => W_VOL1, + I_VOL2 => W_VOL2, + O_SDAT => W_SDAT_A, + O_DO => open + ); + + vmc_sound_b : entity work.MC_SOUND_B + port map( + I_CLK1 => W_CLK_6M, + I_RSTn => rst_count(3), + I_SW => new_sw, + I_DAC => W_DAC, + I_FS => W_FS, + O_SDAT => W_SDAT_B + ); + +--------- ROM ------------------------------------------------------- + mc_roms : entity work.ROM_PGM_0 + port map ( + CLK => W_CLK_12M, + ADDR => W_A(13 downto 0), + DATA => W_CPU_ROM_DO + ); + +-------- VIDEO ----------------------------- + blx_comb <= not ( W_C_BLXn and W_V_BL2n ); + W_V_SYNC <= not W_V_SYNC_int; + W_H_SYNC <= not W_H_SYNC_int; + O_CMPBL <= W_C_BLnX; + + -- MISSILE => Yellow ; + -- SHELL => White ; + W_MS_D <= not (W_MISSILEn and W_SHELLn); + W_MS_R <= not blx_comb and W_MS_D; + W_MS_G <= not blx_comb and W_MS_D; + W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; + + W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); + W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); + W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); + + process(W_CLK_6M) + begin + if rising_edge(W_CLK_6M) then + HBLANK <= not W_C_BLXn; + VBLANK <= not W_V_BL2n; + end if; + end process; + + +----- CPU I/F ------------------------------------- + + W_CPU_CLK <= W_H_CNT(0); + W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; + + W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); + + W_RESETn <= not I_RESET; + W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; + W_CPU_WR <= not W_CPU_WRn; + + new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; + + process(W_CPU_CLK, I_RESET) + begin + if (I_RESET = '1') then + rst_count <= (others => '0'); + elsif rising_edge( W_CPU_CLK) then + if ( rst_count /= x"f") then + rst_count <= rst_count + 1; + end if; + end if; + end process; + +----- Parts 9L --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_FS <= (others=>'0'); + W_HIT <= '0'; + W_FIRE <= '0'; + W_VOL1 <= '0'; + W_VOL2 <= '0'; + elsif rising_edge(W_CLK_12M) then + if (W_SOUND_WE = '1') then + case(W_A(2 downto 0)) is + when "000" => W_FS(0) <= W_BDI(0); + when "001" => W_FS(1) <= W_BDI(0); + when "010" => W_FS(2) <= W_BDI(0); + when "011" => W_HIT <= W_BDI(0); +-- when "100" => UNUSED <= W_BDI(0); + when "101" => W_FIRE <= W_BDI(0); + when "110" => W_VOL1 <= W_BDI(0); + when "111" => W_VOL2 <= W_BDI(0); + when others => null; + end case; + end if; + end if; + end process; + +----- Parts 9M --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_DAC <= (others=>'0'); + elsif rising_edge(W_CLK_12M) then + if (W_DRIVER_WE = '1') then + case(W_A(2 downto 0)) is + -- next 4 outputs go off board via ULN2075 buffer +-- when "000" => 1P START <= W_BDI(0); +-- when "001" => 2P START <= W_BDI(0); +-- when "010" => COIN LOCK <= W_BDI(0); +-- when "011" => COIN CTR <= W_BDI(0); + when "100" => W_DAC(0) <= W_BDI(0); -- 1M + when "101" => W_DAC(1) <= W_BDI(0); -- 470K + when "110" => W_DAC(2) <= W_BDI(0); -- 220K + when "111" => W_DAC(3) <= W_BDI(0); -- 100K + when others => null; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_adec.vhd new file mode 100644 index 00000000..51676803 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_adec.vhd @@ -0,0 +1,251 @@ +--------------------------------------------------------------------- +-- FPGA GALAXIAN ADDRESS DECDER +-- +-- Version : 2.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +--------------------------------------------------------------------- +-- +--GALAXIAN Address Map +-- +-- Address Item(R..read-mode W..wight-mode) Parts +--0000 - 1FFF CPU-ROM..R ( 7H or 7K ) +--2000 - 3FFF CPU-ROM..R ( 7L ) +--4000 - 47FF CPU-RAM..RW ( 7N & 7P ) +--5000 - 57FF VID-RAM..RW +--5800 - 5FFF OBJ-RAM..RW +--6000 - SW0..R LAMP......W +--6800 - SW1..R SOUND.....W +--7000 - DIP..R +--7001 NMI_ON....W +--7004 STARS_ON..W +--7006 H_FLIP....W +--7007 V-FLIP....W +--7800 WDR..R PITCH.....W +-- +--W MODE +--6000 1P START +--6001 2P START +--6002 COIN LOCKOUT +--6003 COIN COUNTER +--6004 - 6007 SOUND CONTROL(OSC) +-- +--6800 SOUND CONTROL(FS1) +--6801 SOUND CONTROL(FS2) +--6802 SOUND CONTROL(FS3) +--6803 SOUND CONTROL(HIT) +--6805 SOUND CONTROL(SHOT) +--6806 SOUND CONTROL(VOL1) +--6807 SOUND CONTROL(VOL2) +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_ADEC is + port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_CPU_CLK : in std_logic; + I_RSTn : in std_logic; + + I_CPU_A : in std_logic_vector(15 downto 0); + I_CPU_D : in std_logic; + I_MREQn : in std_logic; + I_RFSHn : in std_logic; + I_RDn : in std_logic; + I_WRn : in std_logic; + I_H_BL : in std_logic; + I_V_BLn : in std_logic; + + O_WAITn : out std_logic; + O_NMIn : out std_logic; + O_CPU_ROM_CS : out std_logic; + O_CPU_RAM_RD : out std_logic; + O_CPU_RAM_WR : out std_logic; + O_CPU_RAM_CS : out std_logic; + O_OBJ_RAM_RD : out std_logic; + O_OBJ_RAM_WR : out std_logic; + O_OBJ_RAM_RQ : out std_logic; + O_VID_RAM_RD : out std_logic; + O_VID_RAM_WR : out std_logic; + O_SW0_OE : out std_logic; + O_SW1_OE : out std_logic; + O_DIP_OE : out std_logic; + O_WDR_OE : out std_logic; + O_DRIVER_WE : out std_logic; + O_SOUND_WE : out std_logic; + O_PITCH : out std_logic; + O_H_FLIP : out std_logic; + O_V_FLIP : out std_logic; + O_BD_G : out std_logic; + O_STARS_ON : out std_logic + ); +end; + +architecture RTL of MC_ADEC is + signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_NMI_ONn : std_logic := '0'; + -------- CPU WAITn ---------------------------------------------- +-- signal W_6S1_Q : std_logic := '0'; + signal W_6S1_Qn : std_logic := '0'; +-- signal W_6S2_Qn : std_logic := '0'; + + signal W_V_BL : std_logic := '0'; + +begin + W_NMI_ONn <= W_9N_Q(1); -- galaxian + +-- O_WAITn <= '1' ; -- No Wait + O_WAITn <= W_6S1_Qn; + + process(I_CPU_CLK, I_V_BLn) + begin + if (I_V_BLn = '0') then +-- W_6S1_Q <= '0'; + W_6S1_Qn <= '1'; + elsif rising_edge(I_CPU_CLK) then +-- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); + W_6S1_Qn <= I_H_BL or W_8P_Q(2); + end if; + end process; + +-- process(I_CPU_CLK) +-- begin +-- if falling_edge(I_CPU_CLK) then +-- W_6S2_Qn <= not W_6S1_Q; +-- end if; +-- end process; + +-------- CPU NMIn ----------------------------------------------- + W_V_BL <= not I_V_BLn; + process(W_V_BL, W_NMI_ONn) + begin + if (W_NMI_ONn = '0') then + O_NMIn <= '1'; + elsif rising_edge(W_V_BL) then + O_NMIn <= '0'; + end if; + end process; + + ------------------------------------------------------------------- + u_8e1 : entity work.LOGIC_74XX139 + port map ( + I_G => I_MREQn, + I_Sel(1) => I_CPU_A(15), + I_Sel(0) => I_CPU_A(14), + O_Q => W_8E1_Q + ); + + ---------- CPU_ROM CS 0000 - 3FFF --------------------------- + u_8e2 : entity work.LOGIC_74XX139 + port map ( + I_G => I_RDn, + I_Sel(1) => W_8E1_Q(0), + I_Sel(0) => I_CPU_A(13), + O_Q => W_8E2_Q + ); + + O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF + ------------------------------------------------------------------- + -- ADDRESS + -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE + -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 + -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE + -- W_8E1_Q[3] = C000 - FFFF + + u_8p : entity work.LOGIC_74XX138 + port map ( + I_G1 => I_RFSHn, + I_G2a => W_8E1_Q(1), -- <= *1 + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8P_Q + ); + + u_8n : entity work.LOGIC_74XX138 + port map ( + I_G1 => '1', + I_G2a => I_RDn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8N_Q + ); + + u_8m : entity work.LOGIC_74XX138 + port map ( + -- I_G1 => W_6S2_Qn, + I_G1 => '1', -- No Wait + I_G2a => I_WRn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8M_Q + ); + + O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); + O_OBJ_RAM_RQ <= not W_8P_Q(3); + + O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); + + O_WDR_OE <= not W_8N_Q(7); + O_DIP_OE <= not W_8N_Q(6); + O_SW1_OE <= not W_8N_Q(5); + O_SW0_OE <= not W_8N_Q(4); + O_OBJ_RAM_RD <= not W_8N_Q(3); + O_VID_RAM_RD <= not W_8N_Q(2); +-- UNUSED <= not W_8N_Q(1); + O_CPU_RAM_RD <= not W_8N_Q(0); + + O_PITCH <= not W_8M_Q(7); +-- STARS_ON_ENA <= not W_8M_Q(6); + O_SOUND_WE <= not W_8M_Q(5); + O_DRIVER_WE <= not W_8M_Q(4); + O_OBJ_RAM_WR <= not W_8M_Q(3); + O_VID_RAM_WR <= not W_8M_Q(2); +-- UNUSED <= not W_8M_Q(1); + O_CPU_RAM_WR <= not W_8M_Q(0); + + ----- Parts 9N --------- + + process(I_CLK_12M, I_RSTn) + begin + if (I_RSTn = '0') then + W_9N_Q <= (others => '0'); + elsif rising_edge(I_CLK_12M) then + if (W_8M_Q(6) = '0') then + case I_CPU_A(2 downto 0) is + when "000" => W_9N_Q(0) <= I_CPU_D; + when "001" => W_9N_Q(1) <= I_CPU_D; + when "010" => W_9N_Q(2) <= I_CPU_D; + when "011" => W_9N_Q(3) <= I_CPU_D; + when "100" => W_9N_Q(4) <= I_CPU_D; + when "101" => W_9N_Q(5) <= I_CPU_D; + when "110" => W_9N_Q(6) <= I_CPU_D; + when "111" => W_9N_Q(7) <= I_CPU_D; + when others => null; + end case; + end if; + end if; + end process; + + O_STARS_ON <= W_9N_Q(4); + O_H_FLIP <= W_9N_Q(6); + O_V_FLIP <= W_9N_Q(7); + +end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_bram.vhd new file mode 100644 index 00000000..ca6808bf --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_bram.vhd @@ -0,0 +1,182 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA & GALAXIAN +-- FPGA BLOCK RAM I/F (XILINX SPARTAN) +-- +-- Version : 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- mc_col_rom(6L) added by k.Degawa +-- +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. K.Degawa +-- 2004- 9-18 added Xilinx Device K.Degawa +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_top.v use +entity MC_CPU_RAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(10 downto 0); + I_D : in std_logic_vector(7 downto 0); + I_WE : in std_logic; + I_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) + ); +end; +architecture RTL of MC_CPU_RAM is + + signal W_D : std_logic_vector(7 downto 0) := (others => '0'); +begin + O_D <= W_D when I_OE ='1' else (others=>'0'); + + ram_inst : work.spram generic map(11,8) + port map + ( + address => I_ADDR, + clock => I_CLK, + data => I_D, + wren => I_WE, + q => W_D + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_OBJ_RAM is + port( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(7 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(7 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); + end; + +architecture RTL of MC_OBJ_RAM is +begin + + ram_inst : work.dpram generic map(8,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_VID_RAM is + port ( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(9 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(9 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of MC_VID_RAM is +begin + ram_inst : work.dpram generic map(10,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_LRAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(7 downto 0); + I_D : in std_logic_vector(4 downto 0); + I_WE : in std_logic; + O_Dn : out std_logic_vector(4 downto 0) + ); +end; + +architecture RTL of MC_LRAM is + signal W_D : std_logic_vector(4 downto 0) := (others => '0'); +begin + + O_Dn <= not W_D; + + ram_inst : work.dpram generic map(8,5) + port map + ( + clock_a => I_CLK, + address_a => I_ADDR, + data_a => I_D, + wren_a => not I_WE, + + clock_b => not I_CLK, + address_b => I_ADDR, + data_b => (others => '0'), + q_b => W_D, + enable_b => '1', + wren_b => '0' + ); +end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_clocks.vhd new file mode 100644 index 00000000..014e6f7a --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_clocks.vhd @@ -0,0 +1,88 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA CLOCK GEN +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +----------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library unisim; + use unisim.vcomponents.all; + +entity CLOCKGEN is +port ( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + -- + O_CLK_24M : out std_logic; + O_CLK_18M : out std_logic; + O_CLK_12M : out std_logic; + O_CLK_06M : out std_logic +); +end; + +architecture RTL of CLOCKGEN is + signal state : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); + signal CLKFB_IN : std_logic := '0'; + signal CLK0_BUF : std_logic := '0'; + signal CLKFX_BUF : std_logic := '0'; + signal CLK_72M : std_logic := '0'; + signal I_DCM_LOCKED : std_logic := '0'; + +begin + dcm_inst : DCM_SP + generic map ( + CLKFX_MULTIPLY => 9, + CLKFX_DIVIDE => 4, + CLKIN_PERIOD => 31.25 + ) + port map ( + CLKIN => CLKIN_IN, + CLKFB => CLKFB_IN, + RST => RST_IN, + CLK0 => CLK0_BUF, + CLKFX => CLKFX_BUF, + LOCKED => I_DCM_LOCKED + ); + + BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); + BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); + O_CLK_06M <= ctr2(2); + O_CLK_12M <= ctr2(1); + O_CLK_24M <= ctr2(0); + O_CLK_18M <= ctr1(1); + + -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz + process(CLK_72M) + begin + if rising_edge(CLK_72M) then + if (I_DCM_LOCKED = '0') then + state <= "00"; + ctr1 <= (others=>'0'); + ctr2 <= (others=>'0'); + else + ctr1 <= ctr1 + 1; + case state is + when "00" => state <= "01"; ctr2 <= ctr2 + 1; + when "01" => state <= "10"; ctr2 <= ctr2 + 1; + when "10" => state <= "00"; + when "11" => state <= "00"; + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_col_pal.vhd new file mode 100644 index 00000000..c4dc06ad --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_col_pal.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA COLOR-PALETTE +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-18 added Xilinx Device. K.Degawa +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; +-- use ieee.numeric_std.all; + +--library UNISIM; +-- use UNISIM.Vcomponents.all; + +entity MC_COL_PAL is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_VID : in std_logic_vector(1 downto 0); + I_COL : in std_logic_vector(2 downto 0); + I_C_BLnX : in std_logic; + + O_C_BLXn : out std_logic; + O_STARS_OFFn : out std_logic; + O_R : out std_logic_vector(2 downto 0); + O_G : out std_logic_vector(2 downto 0); + O_B : out std_logic_vector(2 downto 0) +); +end; + +architecture RTL of MC_COL_PAL is + --- Parts 6M -------------------------------------------------------- + signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_CLR : std_logic := '0'; + +begin + W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; + W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); + O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); + O_STARS_OFFn <= W_6M_DO(1); + +--always@(posedge I_CLK_6M or negedge W_6M_CLR) + process(I_CLK_6M, W_6M_CLR) + begin + if (W_6M_CLR = '0') then + W_6M_DO <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + W_6M_DO <= W_6M_DI; + end if; + end process; + + --- COL ROM -------------------------------------------------------- +--wire W_COL_ROM_OEn = W_6M_DO[1]; + + galaxian_6l : entity work.GALAXIAN_6L + port map ( + CLK => I_CLK_12M, + ADDR => W_6M_DO(6 downto 2), + DATA => W_COL_ROM_DO + ); + + --- VID OUT -------------------------------------------------------- + O_R <= W_COL_ROM_DO(2 downto 0); + O_G <= W_COL_ROM_DO(5 downto 3); + O_B <= W_COL_ROM_DO(7 downto 6) & "0"; + +end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_hv_count.vhd new file mode 100644 index 00000000..f310321b --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_hv_count.vhd @@ -0,0 +1,145 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA H & V COUNTER +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 +----------------------------------------------------------------------- +-- MoonCrest hv_count +-- H_CNT 0 - 255 , 384 - 511 Total 384 count +-- V_CNT 0 - 255 , 504 - 511 Total 264 count +------------------------------------------------------------------------------------------- +-- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], +-- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_HV_COUNT is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + O_H_CNT : out std_logic_vector(8 downto 0); + O_H_SYNC : out std_logic; + O_H_BL : out std_logic; + O_V_BL2n : out std_logic; + O_V_CNT : out std_logic_vector(7 downto 0); + O_V_SYNC : out std_logic; + O_V_BLn : out std_logic; + O_C_BLn : out std_logic + ); +end; + +architecture RTL of MC_HV_COUNT is + signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal H_SYNC : std_logic := '0'; + signal H_CLK : std_logic := '0'; + signal H_BL : std_logic := '0'; + signal V_BLn : std_logic := '0'; + signal V_BL2n : std_logic := '0'; + +begin +--------- H_COUNT ---------------------------------------- + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if (H_CNT = 255) then + H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); + else + H_CNT <= H_CNT + 1 ; + end if; + end if; + end process; + + O_H_CNT <= H_CNT; + +--------- H_SYNC ---------------------------------------- + H_CLK <= H_CNT(4); + process(H_CLK, H_CNT(8)) + begin + if (H_CNT(8) = '0') then + H_SYNC <= '0'; + elsif rising_edge(H_CLK) then + H_SYNC <= (not H_CNT(6) ) and H_CNT(5); + end if; + end process; + + O_H_SYNC <= H_SYNC; + +--------- H_BL ------------------------------------------ + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if H_CNT = 387 then + H_BL <= '1'; + elsif H_CNT = 503 then + H_BL <= '0'; + end if; + end if; + end process; + + O_H_BL <= H_BL; + +--------- V_COUNT ---------------------------------------- + process(H_SYNC, I_RSTn) + begin + if (I_RSTn = '0') then + V_CNT <= (others => '0'); + elsif rising_edge(H_SYNC) then + if (V_CNT = 255) then + V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); + else + V_CNT <= V_CNT + 1 ; + end if; + end if; + end process; + + O_V_CNT <= V_CNT(7 downto 0); + O_V_SYNC <= V_CNT(8); + +--------- V_BLn ------------------------------------------ + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BLn <= '0'; + elsif V_CNT(7 downto 0) = 15 then + V_BLn <= '1'; + end if; + end if; + end process; + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BL2n <= '0'; + elsif V_CNT(7 downto 0) = 16 then + V_BL2n <= '1'; + end if; + end if; + end process; + + O_V_BLn <= V_BLn; + O_V_BL2n <= V_BL2n; +------- C_BLn ------------------------------------------ + O_C_BLn <= V_BLn and (not H_CNT(8)); + +end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_inport.vhd new file mode 100644 index 00000000..4c47368c --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_inport.vhd @@ -0,0 +1,78 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA INPORT +-- +-- Version : 1.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004-4-30 galaxian modify by K.DEGAWA +----------------------------------------------------------------------- + +-- DIP SW 0 1 2 3 4 5 +----------------------------------------------------------------- +-- COIN CHUTE +-- 1 COIN/1 PLAY 1'b0 1'b0 +-- 2 COIN/1 PLAY 1'b1 1'b0 +-- 1 COIN/2 PLAY 1'b0 1'b1 +-- FREE PLAY 1'b1 1'b1 +-- BOUNS +-- 1'b0 1'b0 +-- 1'b1 1'b0 +-- 1'b0 1'b1 +-- 1'b1 1'b1 +-- LIVES +-- 2 1'b0 +-- 3 1'b1 +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_INPORT is +port ( + I_COIN1 : in std_logic; -- active high + I_COIN2 : in std_logic; -- active high + I_1P_LE : in std_logic; -- active high + I_1P_RI : in std_logic; -- active high + I_1P_SH : in std_logic; -- active high + I_2P_LE : in std_logic; + I_2P_RI : in std_logic; + I_2P_SH : in std_logic; + I_1P_UP : in std_logic; + I_2P_UP : in std_logic; + I_1P_DN : in std_logic; + I_2P_DN : in std_logic; + I_1P_START : in std_logic; -- active high + I_2P_START : in std_logic; -- active high + I_SW0_OE : in std_logic; + I_SW1_OE : in std_logic; + I_DIP_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) +); + +end; + +architecture RTL of MC_INPORT is + + constant W_TABLE : std_logic := '0'; -- UP = 0; + constant W_TEST : std_logic := '0'; + constant W_SERVICE : std_logic := '0'; + + signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); + +begin + + W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_2P_UP & I_1P_DN & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else "01" & I_2P_DN & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; + O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; + +end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_ld_pls.vhd new file mode 100644 index 00000000..0945fe35 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_ld_pls.vhd @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA VIDEO-LD_PLS_GEN +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_LD_PLS is + port ( + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_3D_DI : in std_logic; + + O_LDn : out std_logic; + O_CNTRLDn : out std_logic; + O_CNTRCLRn : out std_logic; + O_COLLn : out std_logic; + O_VPLn : out std_logic; + O_OBJDATALn : out std_logic; + O_MLDn : out std_logic; + O_SLDn : out std_logic + ); +end; + +architecture RTL of MC_LD_PLS is + signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C1_Q3 : std_logic := '0'; + signal W_4C2_B : std_logic := '0'; + signal W_4D1_G : std_logic := '0'; + signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_5C_Q : std_logic := '0'; + signal W_HCNT : std_logic := '0'; +begin + O_LDn <= W_4D1_G; + O_CNTRLDn <= W_4D1_Q(2); + O_CNTRCLRn <= W_4D1_Q(0); + O_COLLn <= W_4D2_Q(2); + O_VPLn <= W_4D2_Q(0); + O_OBJDATALn <= W_4C1_Q(2); + O_MLDn <= W_4C2_Q(0); + O_SLDn <= W_4C2_Q(1); + W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); + W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); + -- Parts 4D + u_4d1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_G, + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q =>W_4D1_Q + ); + + u_4d2 : entity work.LOGIC_74XX139 + port map( + I_G => W_5C_Q, + I_Sel(1) => I_H_CNT(2), + I_Sel(0) => I_H_CNT(1), + O_Q => W_4D2_Q + ); + + -- Parts 4C + u_4c1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D2_Q(1), + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q => W_4C1_Q + ); + + u_4c2 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_Q(3), + I_Sel(1) => W_4C2_B, + I_Sel(0) => W_HCNT, + O_Q => W_4C2_Q + ); + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_5C_Q <= I_H_CNT(0); + end if; + end process; + + -- 2004-9-22 added + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + W_4C1_Q3 <= W_4C1_Q(3); + end if; + end process; + + process(W_4C1_Q3) + begin + if rising_edge(W_4C1_Q3) then + W_4C2_B <= I_3D_DI; + end if; + end process; + +end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_logic.vhd new file mode 100644 index 00000000..5dae8a87 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_logic.vhd @@ -0,0 +1,92 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA LOGIC IP MODULE +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx138 +-- 3-to-8 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX138 is + port ( + I_G1 : in std_logic; + I_G2a : in std_logic; + I_G2b : in std_logic; + I_Sel : in std_logic_vector(2 downto 0); + O_Q : out std_logic_vector(7 downto 0) + ); +end logic_74xx138; + +architecture RTL of LOGIC_74XX138 is + signal I_G : std_logic_vector(2 downto 0) := (others => '0'); + +begin + I_G <= I_G1 & I_G2a & I_G2b; + + xx138 : process(I_G, I_Sel) + begin + if(I_G = "100" ) then + case I_Sel is + when "000" => O_Q <= "11111110"; + when "001" => O_Q <= "11111101"; + when "010" => O_Q <= "11111011"; + when "011" => O_Q <= "11110111"; + when "100" => O_Q <= "11101111"; + when "101" => O_Q <= "11011111"; + when "110" => O_Q <= "10111111"; + when "111" => O_Q <= "01111111"; + when others => null; + end case; + else + O_Q <= (others => '1'); + end if; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx139 +-- 2-to-4 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX139 is + port ( + I_G : in std_logic; + I_Sel : in std_logic_vector(1 downto 0); + O_Q : out std_logic_vector(3 downto 0) + ); +end; + +architecture RTL of LOGIC_74XX139 is +begin + xx139 : process (I_G, I_Sel) + begin + if I_G = '0' then + case I_Sel is + when "00" => O_Q <= "1110"; + when "01" => O_Q <= "1101"; + when "10" => O_Q <= "1011"; + when "11" => O_Q <= "0111"; + when others => null; + end case; + else + O_Q <= "1111"; + end if; + end process; +end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_missile.vhd new file mode 100644 index 00000000..c5aa6633 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_missile.vhd @@ -0,0 +1,107 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA VIDEO-MISSILE +---- +---- Version : 2.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_MISSILE is + port( + I_CLK_6M : in std_logic; + I_CLK_18M : in std_logic; + I_C_BLn_X : in std_logic; + I_MLDn : in std_logic; + I_SLDn : in std_logic; + I_HPOS : in std_logic_vector (7 downto 0); + + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic + ); +end; + +architecture RTL of MC_MISSILE is + signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_5P1_Q : std_logic := '0'; + signal W_5P2_Q : std_logic := '0'; + signal W_5P1_CLK : std_logic := '0'; + signal W_5P2_CLK : std_logic := '0'; +begin + + O_MISSILEn <= W_5P1_CLK; + O_SHELLn <= W_5P2_CLK; + + -- missile counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if (I_MLDn = '0') then + W_45R_Q <= I_HPOS; + else + if (I_C_BLn_X = '1') then + W_45R_Q <= W_45R_Q + 1; + if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then + W_5P1_CLK <= '0'; + else + W_5P1_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- shell counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if(I_SLDn = '0') then + W_45S_Q <= I_HPOS; + else + if(I_C_BLn_X = '1') then + W_45S_Q <= W_45S_Q + 1; + if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then + W_5P2_CLK <= '0'; + else + W_5P2_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) + process(W_5P1_CLK, I_MLDn) + begin + if (I_MLDn = '0') then + W_5P1_Q <= '1'; + elsif rising_edge(W_5P1_CLK) then + W_5P1_Q <= '0'; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) + process(W_5P2_CLK, I_SLDn) + begin + if (I_SLDn = '0') then + W_5P2_Q <= '1'; + elsif rising_edge(W_5P2_CLK) then + W_5P2_Q <= '0'; + end if; + end process; + +end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_a.vhd new file mode 100644 index 00000000..ee0c66be --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_a.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA SOUND I/F +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + use IEEE.std_logic_arith.all; + +entity MC_SOUND_A is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT1 : in std_logic; + I_BD : in std_logic_vector(7 downto 0); + I_PITCH : in std_logic; + I_VOL1 : in std_logic; + I_VOL2 : in std_logic; + + O_SDAT : out std_logic_vector(7 downto 0); + O_DO : out std_logic_vector(3 downto 0) +); +end; + +architecture RTL of MC_SOUND_A is + signal W_PITCH : std_logic := '0'; + signal W_89K_LDn : std_logic := '0'; + signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); + +begin + O_DO <= W_6T_Q; + + process (I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_PITCH <= I_PITCH; + if (W_89K_Q = x"ff") then + W_89K_LDn <= '0' ; + else + W_89K_LDn <= '1' ; + end if; + end if; + end process; + + -- Parts 9J + process (W_PITCH) + begin + if falling_edge(W_PITCH) then + W_89K_LDATA <= I_BD; + end if; + end process; + + process (I_H_CNT1) + begin + if rising_edge(I_H_CNT1) then + if (W_89K_LDn = '0') then + W_89K_Q <= W_89K_LDATA; + else + W_89K_Q <= W_89K_Q + 1; + end if; + end if; + end process; + + process (W_89K_LDn) + begin + if falling_edge(W_89K_LDn) then + W_6T_Q <= W_6T_Q + 1; + end if; + end process; + + process (I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); + + if W_6T_Q(0)='1' then + W_SDAT0 <= x"2a"; + else + W_SDAT0 <= (others => '0'); + end if; + + if W_6T_Q(2)='1' then + if I_VOL1 = '1' then + W_SDAT2 <= x"69"; + else + W_SDAT2 <= x"39"; + end if; + else + W_SDAT2 <= (others => '0'); + end if; + + if (W_6T_Q(3)='1') and (I_VOL2 = '1') then + W_SDAT3 <= x"48" ; + else + W_SDAT3 <= (others => '0'); + end if; + + end if; + end process; + +end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_b.vhd new file mode 100644 index 00000000..b74e4bb1 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_b.vhd @@ -0,0 +1,253 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA WAVE SOUND +---- +---- Version : 1.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does no guarantee this program. +---- You can use this at your own risk. +---- +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--pragma translate_off +-- use ieee.std_logic_textio.all; +-- use std.textio.all; +--pragma translate_on + +entity MC_SOUND_B is + port( + I_CLK1 : in std_logic; -- 6MHz + I_RSTn : in std_logic; + I_SW : in std_logic_vector( 2 downto 0); + I_DAC : in std_logic_vector( 3 downto 0); + I_FS : in std_logic_vector( 2 downto 0); + O_SDAT : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_B is +constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz +constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; +constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; + +signal sample : std_logic_vector(10 downto 0) := (others => '0'); +signal sample_pls : std_logic := '0'; +signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s0_trg : std_logic := '0'; +signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s1_trg : std_logic := '0'; +signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); +signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); + +signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); +signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + +signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); + +signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); + +begin + -- ideally we should divide by 5 because this is the sum of 5 channels + -- but in practice we divide by 4 and just clip sounds that are too loud. + O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds + + process(I_CLK1) + begin + if rising_edge(I_CLK1) then + SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + sample <= (others => '0'); + sample_pls <= '0'; + elsif rising_edge(I_CLK1) then + if (sample = sample_time - 1) then + sample <= (others => '0'); + sample_pls <= '1'; + else + sample <= sample + 1; + sample_pls <= '0'; + end if; + end if; + end process; + +------------- FIRE SOUND ------------------------------------------ + mc_roms_fire : entity work.GAL_FIR + port map ( + CLK => I_CLK1, + ADDR => fire_addr(12 downto 0), + DATA => WAV_D0 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s0_trg_ff <= (others => '0'); + s0_trg <= '0'; + elsif rising_edge(I_CLK1) then + s0_trg_ff(0) <= I_SW(0); + s0_trg_ff(1) <= s0_trg_ff(0); + s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + fire_addr <= fire_cnt; + elsif rising_edge(I_CLK1) then + if (s0_trg = '1') then + fire_addr <= (others => '0'); + else + if(sample_pls = '1') then + if(fire_addr <= fire_cnt) then + fire_addr <= fire_addr + 1; + else + fire_addr <= fire_addr ; + end if; + end if; + end if; + end if; + end process; + +------------- HIT SOUND ------------------------------------------ + mc_roms_hit : entity work.GAL_HIT + port map ( + CLK => I_CLK1, + ADDR => hit_addr(12 downto 0), + DATA => WAV_D1 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s1_trg_ff <= (others => '0'); + s1_trg <= '0'; + elsif rising_edge(I_CLK1) then + s1_trg_ff(0) <= I_SW(1); + s1_trg_ff(1) <= s1_trg_ff(0); + s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + hit_addr <= hit_cnt; + elsif rising_edge(I_CLK1) then + if (s1_trg = '1') then + hit_addr <= (others => '0'); + else + if (sample_pls = '1') then + if (hit_addr <= hit_cnt) then + hit_addr <= hit_addr + 1 ; + else + hit_addr <= hit_addr ; + end if; + end if; + end if; + end if; + end process; + +--------------- EFFECT SOUND --------------------------------------- + +-- 9R modulator voltage generator based on DAC value + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + VCO_CTR <= (others=>'0'); + elsif rising_edge(I_CLK1) then + VCO_CTR <= VCO_CTR + (not I_DAC); + end if; + end process; + + -- modulator frequency lookup tables for the three VCOs + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + elsif rising_edge(I_CLK1) then + case VCO_CTR(23 downto 19) is + when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; + when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; + when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; + when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; + when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; + when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; + when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; + when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; + when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; + when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; + when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; + when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; + when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; + when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; + when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; + when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; + when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; + when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; + when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; + when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; + when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; + when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; + when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; + when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; + when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; + when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; + when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; + when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; + when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; + when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; + when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; + when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; + when others => null; + end case; + end if; + end process; + +-- 8R VCO 240Hz - 140Hz (8) + mc_vco1 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(0), + I_STEP => W_VCO1_STEP, + O_WAV => W_VCO1_OUT + ); + +-- 8S VCO 330Hz - 190Hz (11) + mc_vco2 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(1), + I_STEP => W_VCO2_STEP, + O_WAV => W_VCO2_OUT + ); + +-- 8T VCO 480Hz - 270Hz (16) + mc_vco3 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(2), + I_STEP => W_VCO3_STEP, + O_WAV => W_VCO3_OUT + ); +end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_vco.vhd new file mode 100644 index 00000000..e2a63e85 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_vco.vhd @@ -0,0 +1,49 @@ +-------------------------------------------------------------------------------- +---- FPGA VCO +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +use work.sine_package.all; + +-- O_CLK = (I_CLK / 2^20) * I_STEP +entity MC_SOUND_VCO is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + I_FS : in std_logic; + I_STEP : in std_logic_vector( 7 downto 0); + O_WAV : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_VCO is + signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); + signal sine : std_logic_vector(14 downto 0) := (others => '0'); + +begin + O_WAV <= sine(14 downto 7); + process(I_CLK, I_RSTn) + begin + if (I_RSTn = '0') then + VCO1_CTR <= (others=>'0'); + elsif rising_edge(I_CLK) then + if I_FS = '1' then + VCO1_CTR <= VCO1_CTR + I_STEP; + case VCO1_CTR(19 downto 18) is + when "00" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "01" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when "10" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "11" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_stars.vhd new file mode 100644 index 00000000..b91197b3 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_stars.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA STARS +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity MC_STARS is + port ( + I_CLK_18M : in std_logic; + I_CLK_6M : in std_logic; + I_H_FLIP : in std_logic; + I_V_SYNC : in std_logic; + I_8HF : in std_logic; + I_256HnX : in std_logic; + I_1VF : in std_logic; + I_2V : in std_logic; + I_STARS_ON : in std_logic; + I_STARS_OFFn : in std_logic; + + O_R : out std_logic_vector(1 downto 0); + O_G : out std_logic_vector(1 downto 0); + O_B : out std_logic_vector(1 downto 0); + O_NOISE : out std_logic + ); +end; + +architecture RTL of MC_STARS is + signal CLK_1C : std_logic := '0'; + signal W_2D_Qn : std_logic := '0'; + + signal W_3B : std_logic := '0'; + signal noise : std_logic := '0'; + signal W_2A : std_logic := '0'; + signal W_4P : std_logic := '0'; + signal CLK_1AB : std_logic := '0'; + signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); + signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); +begin + O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + + CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); + CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); + W_3B <= W_2D_Qn xor W_1AB_Q(4); + + W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; + W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); + + O_NOISE <= noise ; + + process(I_2V) + begin + if rising_edge(I_2V) then + noise <= W_2D_Qn; + end if; + end process; + + process(CLK_1C, I_V_SYNC) + begin + if(I_V_SYNC = '1') then + W_1C_Q <= (others => '0'); + elsif rising_edge(CLK_1C) then + W_1C_Q <= W_1C_Q(0) & '1'; + end if; + end process; + + process(CLK_1AB, I_STARS_ON) + begin + if(I_STARS_ON = '0') then + W_1AB_Q <= (others => '0'); + W_2D_Qn <= '1'; + elsif rising_edge(CLK_1AB) then + W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; + W_2D_Qn <= not W_1AB_Q(15); + end if; + end process; +end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_video.vhd new file mode 100644 index 00000000..27a8432b --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_video.vhd @@ -0,0 +1,434 @@ +-------------------------------------------------------------------------------- +---- FPGA GALAXIAN VIDEO +---- +---- Version : 2.50 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 4-30 galaxian modify by K.DEGAWA +---- 2004- 5- 6 first release. +---- 2004- 8-23 Improvement with T80-IP. +---- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +-------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------- +-- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), +-- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_VIDEO is + port( + I_CLK_18M : in std_logic; + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_V_CNT : in std_logic_vector(7 downto 0); + I_H_FLIP : in std_logic; + I_V_FLIP : in std_logic; + I_V_BLn : in std_logic; + I_C_BLn : in std_logic; + + I_A : in std_logic_vector(9 downto 0); + I_BD : in std_logic_vector(7 downto 0); + I_OBJ_SUB_A : in std_logic_vector(2 downto 0); + I_OBJ_RAM_RQ : in std_logic; + I_OBJ_RAM_RD : in std_logic; + I_OBJ_RAM_WR : in std_logic; + I_VID_RAM_RD : in std_logic; + I_VID_RAM_WR : in std_logic; + I_DRIVER_WR : in std_logic; + + O_C_BLnX : out std_logic; + O_8HF : out std_logic; + O_256HnX : out std_logic; + O_1VF : out std_logic; + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic; + + O_BD : out std_logic_vector(7 downto 0); + O_VID : out std_logic_vector(1 downto 0); + O_COL : out std_logic_vector(2 downto 0) + ); +end; + +architecture RTL of MC_VIDEO is + + signal WB_LDn : std_logic := '0'; + signal WB_CNTRLDn : std_logic := '0'; + signal WB_CNTRCLRn : std_logic := '0'; + signal WB_COLLn : std_logic := '0'; + signal WB_VPLn : std_logic := '0'; + signal WB_OBJDATALn : std_logic := '0'; + signal WB_MLDn : std_logic := '0'; + signal WB_SLDn : std_logic := '0'; + signal W_3D : std_logic := '0'; + signal W_LDn : std_logic := '0'; + signal W_CNTRLDn : std_logic := '0'; + signal W_CNTRCLRn : std_logic := '0'; + signal W_COLLn : std_logic := '0'; + signal W_VPLn : std_logic := '0'; + signal W_OBJDATALn : std_logic := '0'; + signal W_MLDn : std_logic := '0'; + signal W_SLDn : std_logic := '0'; + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); + signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); + signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); + signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); + signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); +-- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_BANK : std_logic; + signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_256HnX : std_logic := '0'; + signal W_2N : std_logic := '0'; + signal W_45T_CLR : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_H_FLIP1 : std_logic := '0'; + signal W_H_FLIP2 : std_logic := '0'; + signal W_H_FLIP1X : std_logic := '0'; + signal W_H_FLIP2X : std_logic := '0'; + signal W_LRAM_AND : std_logic := '0'; + signal W_RAW0 : std_logic := '0'; + signal W_RAW1 : std_logic := '0'; + signal W_RAW_OR : std_logic := '0'; + signal W_SRCLK : std_logic := '0'; + signal W_SRLD : std_logic := '0'; + signal W_VID_RAM_CS : std_logic := '0'; + signal W_CLK_6Mn : std_logic := '0'; + +begin + ld_pls : entity work.MC_LD_PLS + port map( + I_CLK_6M => I_CLK_6M, + I_H_CNT => I_H_CNT, + I_3D_DI => W_3D, + + O_LDn => WB_LDn, + O_CNTRLDn => WB_CNTRLDn, + O_CNTRCLRn => WB_CNTRCLRn, + O_COLLn => WB_COLLn, + O_VPLn => WB_VPLn, + O_OBJDATALn => WB_OBJDATALn, + O_MLDn => WB_MLDn, + O_SLDn => WB_SLDn + ); + + obj_ram : entity work.MC_OBJ_RAM + port map( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(7 downto 0), + I_WEA => I_OBJ_RAM_WR, + I_CEA => I_OBJ_RAM_RQ, + I_DA => I_BD, + O_DA => W_OBJ_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_OBJ_RAM_AB, + I_WEB => '0', + I_CEB => '1', + I_DB => x"00", + O_DB => W_OBJ_RAM_DOB + ); + + lram : entity work.MC_LRAM + port map( + I_CLK => I_CLK_18M, + I_ADDR => W_LRAM_A, + I_WE => W_CLK_6Mn, + I_D => W_LRAM_DI, + O_Dn => W_LRAM_DO + ); + + missile : entity work.MC_MISSILE + port map( + I_CLK_18M => I_CLK_18M, + I_CLK_6M => I_CLK_6M, + I_C_BLn_X => W_C_BLnX, + I_MLDn => W_MLDn, + I_SLDn => W_SLDn, + I_HPOS => W_H_POSI, + O_MISSILEn => O_MISSILEn, + O_SHELLn => O_SHELLn + ); + + vid_ram : entity work.MC_VID_RAM + port map ( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(9 downto 0), + I_DA => W_VID_RAM_DI, + I_WEA => I_VID_RAM_WR, + I_CEA => W_VID_RAM_CS, + O_DA => W_VID_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_VID_RAM_A(9 downto 0), + I_DB => x"00", + I_WEB => '0', + I_CEB => '1', + O_DB => W_VID_RAM_DOB + ); + + -- 1K VID-Rom + k_rom : entity work.GALAXIAN_1K + port map ( + CLK => I_CLK_12M, + ADDR => W_OBJ_ROM_BANK & W_O_OBJ_ROM_A, + DATA => W_1K_D + ); + + -- 1H VID-Rom + h_rom : entity work.GALAXIAN_1H + port map( + CLK => I_CLK_12M, + ADDR => W_OBJ_ROM_BANK & W_O_OBJ_ROM_A, + DATA => W_1H_D + ); + +----------------------------------------------------------------------------------- + + process(I_CLK_12M) + begin + if falling_edge(I_CLK_12M) then + W_LDn <= WB_LDn; + W_CNTRLDn <= WB_CNTRLDn; + W_CNTRCLRn <= WB_CNTRCLRn; + W_COLLn <= WB_COLLn; + W_VPLn <= WB_VPLn; + W_OBJDATALn <= WB_OBJDATALn; + W_MLDn <= WB_MLDn; + W_SLDn <= WB_SLDn; + end if; + end process; + + W_CLK_6Mn <= not I_CLK_6M; + + W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); + W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); + W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; + + W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; + + W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); + W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; + + O_8HF <= W_HF_CNT(3); + O_1VF <= W_VF_CNT(0); + W_H_FLIP2 <= W_6J_Q(3); + +-- Parts 4F,5F + W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); +-- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; + + process(I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_H_POSI <= W_OBJ_RAM_DOB; + end if; + end process; + + W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); + +-- Parts 4L + process(W_OBJDATALn) + begin + if rising_edge(W_OBJDATALn) then + W_OBJ_D <= W_H_POSI; + end if; + end process; + +-- Parts 4,5N + W_45N_Q <= W_VF_CNT + W_H_POSI; + W_3D <= '0' when W_45N_Q = x"FF" else '1'; + + process(W_VPLn, I_V_BLn) + begin + if (I_V_BLn = '0') then + W_2M_Q <= (others => '0'); + elsif rising_edge(W_VPLn) then + W_2M_Q <= W_45N_Q; + end if; + end process; + + W_2N <= I_H_CNT(8) and W_OBJ_D(7); + W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); + W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; + W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); + W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) + W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); + W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; + W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); + +---- VIDEO DATA OUTPUT -------------- + W_OBJ_ROM_BANK<= not I_H_CNT(8); + O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; + W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); + W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); + W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; + W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); + +----------------------------------------------------------------------------------- + + W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; + W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; + W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 + C_2HJ <= W_3L_Y(1 downto 0); + C_2KL <= W_3L_Y(1 downto 0); + W_RAW0 <= W_3L_Y(2); + W_RAW1 <= W_3L_Y(3); + W_SRCLK <= I_CLK_6M; + +-------- PARTS 2KL ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2KL) is + when "00" => reg_2KL <= reg_2KL; + when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; + when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); + when "11" => reg_2KL <= W_1K_D; + when others => null; + end case; + end if; + end process; + +-------- PARTS 2HJ ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2HJ) is + when "00" => reg_2HJ <= reg_2HJ; + when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; + when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); + when "11" => reg_2HJ <= W_1H_D; + when others => null; + end case; + end if; + end process; + +------- SHT2 ----------------------------------------------------- + +-- Parts 6K + process(W_COLLn) + begin + if rising_edge(W_COLLn) then + W_6K_Q <= W_H_POSI(2 downto 0); + end if; + end process; + +-- Parts 6P + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + if (W_LDn = '0') then + W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); + else + W_6P_Q <= W_6P_Q; + end if; + end if; + end process; + + W_H_FLIP2X <= W_6P_Q(6); + W_H_FLIP1X <= W_6P_Q(5); + W_C_BLnX <= W_6P_Q(4); + W_256HnX <= W_6P_Q(3); + W_CD <= W_6P_Q(2 downto 0); + O_256HnX <= W_256HnX; + O_C_BLnX <= W_C_BLnX; + W_45T_CLR <= W_CNTRCLRn or W_256HnX ; + + process(I_CLK_6M, W_45T_CLR) + begin + if (W_45T_CLR = '0') then + W_45T_Q <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + if (W_CNTRLDn = '0') then + W_45T_Q <= W_H_POSI; + else + W_45T_Q <= W_45T_Q + 1; + end if; + end if; + end process; + + W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_RV <= W_LRAM_DO(1 downto 0); + W_RC <= W_LRAM_DO(4 downto 2); + end if; + end process; + + W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); + W_RAW_OR <= W_RAW0 or W_RAW1 ; + + W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); + W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); + W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); + W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); + W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); + + O_VID <= W_VID; + O_COL <= W_COL; + + W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); + W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); + W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); + W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); + W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); + +end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.qip b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.vhd new file mode 100644 index 00000000..2822d752 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.vhd @@ -0,0 +1,451 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 9, + clk0_duty_cycle => 50, + clk0_multiply_by => 8, + clk0_phase_shift => "0", + clk1_divide_by => 3, + clk1_duty_cycle => 50, + clk1_multiply_by => 2, + clk1_phase_shift => "0", + clk2_divide_by => 9, + clk2_duty_cycle => 50, + clk2_multiply_by => 4, + clk2_phase_shift => "0", + clk3_divide_by => 9, + clk3_duty_cycle => 50, + clk3_multiply_by => 2, + clk3_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/sine_package.vhd new file mode 100644 index 00000000..473caa04 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/sine_package.vhd @@ -0,0 +1,152 @@ +library ieee; +use ieee.std_logic_1164.all; + +package sine_package is + + subtype table_value_type is integer range 0 to 16383; + subtype table_index_type is std_logic_vector( 6 downto 0 ); + + function get_table_value (table_index: table_index_type) return table_value_type; + +end; + +package body sine_package is + + function get_table_value (table_index: table_index_type) return table_value_type is + variable table_value: table_value_type; + begin + case table_index is + when "0000000" => table_value := 101; + when "0000001" => table_value := 302; + when "0000010" => table_value := 503; + when "0000011" => table_value := 703; + when "0000100" => table_value := 904; + when "0000101" => table_value := 1105; + when "0000110" => table_value := 1305; + when "0000111" => table_value := 1506; + when "0001000" => table_value := 1706; + when "0001001" => table_value := 1906; + when "0001010" => table_value := 2105; + when "0001011" => table_value := 2304; + when "0001100" => table_value := 2503; + when "0001101" => table_value := 2702; + when "0001110" => table_value := 2900; + when "0001111" => table_value := 3098; + when "0010000" => table_value := 3295; + when "0010001" => table_value := 3491; + when "0010010" => table_value := 3688; + when "0010011" => table_value := 3883; + when "0010100" => table_value := 4078; + when "0010101" => table_value := 4273; + when "0010110" => table_value := 4466; + when "0010111" => table_value := 4659; + when "0011000" => table_value := 4852; + when "0011001" => table_value := 5044; + when "0011010" => table_value := 5234; + when "0011011" => table_value := 5425; + when "0011100" => table_value := 5614; + when "0011101" => table_value := 5802; + when "0011110" => table_value := 5990; + when "0011111" => table_value := 6177; + when "0100000" => table_value := 6362; + when "0100001" => table_value := 6547; + when "0100010" => table_value := 6731; + when "0100011" => table_value := 6914; + when "0100100" => table_value := 7095; + when "0100101" => table_value := 7276; + when "0100110" => table_value := 7456; + when "0100111" => table_value := 7634; + when "0101000" => table_value := 7811; + when "0101001" => table_value := 7988; + when "0101010" => table_value := 8162; + when "0101011" => table_value := 8336; + when "0101100" => table_value := 8509; + when "0101101" => table_value := 8680; + when "0101110" => table_value := 8850; + when "0101111" => table_value := 9018; + when "0110000" => table_value := 9185; + when "0110001" => table_value := 9351; + when "0110010" => table_value := 9515; + when "0110011" => table_value := 9678; + when "0110100" => table_value := 9840; + when "0110101" => table_value := 10000; + when "0110110" => table_value := 10158; + when "0110111" => table_value := 10315; + when "0111000" => table_value := 10471; + when "0111001" => table_value := 10625; + when "0111010" => table_value := 10777; + when "0111011" => table_value := 10927; + when "0111100" => table_value := 11076; + when "0111101" => table_value := 11224; + when "0111110" => table_value := 11369; + when "0111111" => table_value := 11513; + when "1000000" => table_value := 11655; + when "1000001" => table_value := 11796; + when "1000010" => table_value := 11934; + when "1000011" => table_value := 12071; + when "1000100" => table_value := 12206; + when "1000101" => table_value := 12339; + when "1000110" => table_value := 12471; + when "1000111" => table_value := 12600; + when "1001000" => table_value := 12728; + when "1001001" => table_value := 12853; + when "1001010" => table_value := 12977; + when "1001011" => table_value := 13099; + when "1001100" => table_value := 13219; + when "1001101" => table_value := 13336; + when "1001110" => table_value := 13452; + when "1001111" => table_value := 13566; + when "1010000" => table_value := 13678; + when "1010001" => table_value := 13787; + when "1010010" => table_value := 13895; + when "1010011" => table_value := 14000; + when "1010100" => table_value := 14104; + when "1010101" => table_value := 14205; + when "1010110" => table_value := 14304; + when "1010111" => table_value := 14401; + when "1011000" => table_value := 14496; + when "1011001" => table_value := 14588; + when "1011010" => table_value := 14679; + when "1011011" => table_value := 14767; + when "1011100" => table_value := 14853; + when "1011101" => table_value := 14936; + when "1011110" => table_value := 15018; + when "1011111" => table_value := 15097; + when "1100000" => table_value := 15174; + when "1100001" => table_value := 15249; + when "1100010" => table_value := 15321; + when "1100011" => table_value := 15391; + when "1100100" => table_value := 15459; + when "1100101" => table_value := 15524; + when "1100110" => table_value := 15587; + when "1100111" => table_value := 15648; + when "1101000" => table_value := 15706; + when "1101001" => table_value := 15762; + when "1101010" => table_value := 15816; + when "1101011" => table_value := 15867; + when "1101100" => table_value := 15916; + when "1101101" => table_value := 15963; + when "1101110" => table_value := 16007; + when "1101111" => table_value := 16048; + when "1110000" => table_value := 16088; + when "1110001" => table_value := 16124; + when "1110010" => table_value := 16159; + when "1110011" => table_value := 16191; + when "1110100" => table_value := 16220; + when "1110101" => table_value := 16247; + when "1110110" => table_value := 16272; + when "1110111" => table_value := 16294; + when "1111000" => table_value := 16314; + when "1111001" => table_value := 16331; + when "1111010" => table_value := 16346; + when "1111011" => table_value := 16358; + when "1111100" => table_value := 16368; + when "1111101" => table_value := 16375; + when "1111110" => table_value := 16380; + when "1111111" => table_value := 16383; + when others => null; + end case; + return table_value; + end; + +end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/spram.vhd new file mode 100644 index 00000000..ad6b58b5 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/spram.vhd @@ -0,0 +1,55 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY spram IS + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "NORMAL", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone V", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + width_a => data_width_g, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + clocken0 => clken, + data_a => data, + wren_a => wren, + q_a => q + ); + + + +END SYN;